]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/mmc/host/dw_mmc.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: dw_mmc: remove declaration of dw_mci_card_busy
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
b6d2d81c 22#include <linux/iopoll.h>
f95f3850
WN		 23#include <linux/ioport.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
a6db2c86 26#include <linux/pm_runtime.h>
f95f3850
WN		 27#include <linux/seq_file.h>
28#include <linux/slab.h>
29#include <linux/stat.h>
30#include <linux/delay.h>
31#include <linux/irq.h>
b24c8b26 32#include <linux/mmc/card.h>
f95f3850
WN		 33#include <linux/mmc/host.h>
34#include <linux/mmc/mmc.h>
01730558 35#include <linux/mmc/sd.h>
90c2143a 36#include <linux/mmc/sdio.h>
f95f3850 37#include <linux/bitops.h>
c07946a3 38#include <linux/regulator/consumer.h>
c91eab4b 39#include <linux/of.h>
55a6ceb2 40#include <linux/of_gpio.h>
bf626e55 41#include <linux/mmc/slot-gpio.h>
f95f3850
WN		 42
43#include "dw_mmc.h"
44
45/* Common flag combinations */
3f7eec62 46#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
f95f3850 47 SDMMC_INT_HTO | SDMMC_INT_SBE | \
7a3c5677 48 SDMMC_INT_EBE | SDMMC_INT_HLE)
f95f3850 49#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
7a3c5677 50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
f95f3850 51#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
7a3c5677 52 DW_MCI_CMD_ERROR_FLAGS)
f95f3850
WN		 53#define DW_MCI_SEND_STATUS 1
54#define DW_MCI_RECV_STATUS 2
55#define DW_MCI_DMA_THRESHOLD 16
56
1f44a2a5 57#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
72e83577 58#define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
1f44a2a5 59
fc79a4d6
JS		 60#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
cc190d4c
SL		 65#define DESC_RING_BUF_SZ PAGE_SIZE
66
69d99fdc
PT		 67struct idmac_desc_64addr {
68 u32 des0; /* Control Descriptor */
b6d2d81c
SL		 69#define IDMAC_OWN_CLR64(x) \
70 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
69d99fdc
PT		 71
72 u32 des1; /* Reserved */
73
74 u32 des2; /*Buffer sizes */
75#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
6687c42f
BD		 76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
69d99fdc
PT		 78
79 u32 des3; /* Reserved */
80
81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
83
84 u32 des6; /* Lower 32-bits of Next Descriptor Address */
85 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86};
87
f95f3850 88struct idmac_desc {
6687c42f 89 __le32 des0; /* Control Descriptor */
f95f3850
WN		 90#define IDMAC_DES0_DIC BIT(1)
91#define IDMAC_DES0_LD BIT(2)
92#define IDMAC_DES0_FD BIT(3)
93#define IDMAC_DES0_CH BIT(4)
94#define IDMAC_DES0_ER BIT(5)
95#define IDMAC_DES0_CES BIT(30)
96#define IDMAC_DES0_OWN BIT(31)
97
6687c42f 98 __le32 des1; /* Buffer sizes */
f95f3850 99#define IDMAC_SET_BUFFER1_SIZE(d, s) \
e5306c3a 100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
f95f3850 101
6687c42f 102 __le32 des2; /* buffer 1 physical address */
f95f3850 103
6687c42f 104 __le32 des3; /* buffer 2 physical address */
f95f3850 105};
5959b32e
AB		 106
107/* Each descriptor can transfer up to 4KB of data in chained mode */
108#define DW_MCI_DESC_DATA_LENGTH 0x1000
f95f3850 109
f95f3850
WN		 110#if defined(CONFIG_DEBUG_FS)
111static int dw_mci_req_show(struct seq_file *s, void *v)
112{
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
118
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
121 mrq = slot->mrq;
122
123 if (mrq) {
124 cmd = mrq->cmd;
125 data = mrq->data;
126 stop = mrq->stop;
127
128 if (cmd)
129 seq_printf(s,
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
134 if (data)
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
138 if (stop)
139 seq_printf(s,
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
144 }
145
146 spin_unlock_bh(&slot->host->lock);
147
148 return 0;
149}
150
151static int dw_mci_req_open(struct inode *inode, struct file *file)
152{
153 return single_open(file, dw_mci_req_show, inode->i_private);
154}
155
156static const struct file_operations dw_mci_req_fops = {
157 .owner = THIS_MODULE,
158 .open = dw_mci_req_open,
159 .read = seq_read,
160 .llseek = seq_lseek,
161 .release = single_release,
162};
163
164static int dw_mci_regs_show(struct seq_file *s, void *v)
165{
21657ebd
JC		 166 struct dw_mci *host = s->private;
167
168 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
169 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
170 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
171 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
172 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
173 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
f95f3850
WN		 174
175 return 0;
176}
177
178static int dw_mci_regs_open(struct inode *inode, struct file *file)
179{
180 return single_open(file, dw_mci_regs_show, inode->i_private);
181}
182
183static const struct file_operations dw_mci_regs_fops = {
184 .owner = THIS_MODULE,
185 .open = dw_mci_regs_open,
186 .read = seq_read,
187 .llseek = seq_lseek,
188 .release = single_release,
189};
190
191static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
192{
193 struct mmc_host *mmc = slot->mmc;
194 struct dw_mci *host = slot->host;
195 struct dentry *root;
196 struct dentry *node;
197
198 root = mmc->debugfs_root;
199 if (!root)
200 return;
201
202 node = debugfs_create_file("regs", S_IRUSR, root, host,
203 &dw_mci_regs_fops);
204 if (!node)
205 goto err;
206
207 node = debugfs_create_file("req", S_IRUSR, root, slot,
208 &dw_mci_req_fops);
209 if (!node)
210 goto err;
211
212 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
213 if (!node)
214 goto err;
215
216 node = debugfs_create_x32("pending_events", S_IRUSR, root,
217 (u32 *)&host->pending_events);
218 if (!node)
219 goto err;
220
221 node = debugfs_create_x32("completed_events", S_IRUSR, root,
222 (u32 *)&host->completed_events);
223 if (!node)
224 goto err;
225
226 return;
227
228err:
229 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
230}
231#endif /* defined(CONFIG_DEBUG_FS) */
232
01730558 233static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
8e6db1f6
SL		 234static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
235{
236 u32 ctrl;
237
238 ctrl = mci_readl(host, CTRL);
239 ctrl |= reset;
240 mci_writel(host, CTRL, ctrl);
241
242 /* wait till resets clear */
243 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
244 !(ctrl & reset),
245 1, 500 * USEC_PER_MSEC)) {
246 dev_err(host->dev,
247 "Timeout resetting block (ctrl reset %#x)\n",
248 ctrl & reset);
249 return false;
250 }
251
252 return true;
253}
01730558 254
f95f3850
WN		 255static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
256{
800d78bf 257 struct dw_mci_slot *slot = mmc_priv(mmc);
01730558 258 struct dw_mci *host = slot->host;
f95f3850 259 u32 cmdr;
f95f3850 260
0e3a22c0 261 cmd->error = -EINPROGRESS;
f95f3850
WN		 262 cmdr = cmd->opcode;
263
90c2143a
SJ		 264 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
265 cmd->opcode == MMC_GO_IDLE_STATE ||
266 cmd->opcode == MMC_GO_INACTIVE_STATE ||
267 (cmd->opcode == SD_IO_RW_DIRECT &&
268 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
f95f3850 269 cmdr |= SDMMC_CMD_STOP;
4a1b27ad
JC		 270 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
271 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
f95f3850 272
01730558
DA		 273 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
274 u32 clk_en_a;
275
276 /* Special bit makes CMD11 not die */
277 cmdr |= SDMMC_CMD_VOLT_SWITCH;
278
279 /* Change state to continue to handle CMD11 weirdness */
280 WARN_ON(slot->host->state != STATE_SENDING_CMD);
281 slot->host->state = STATE_SENDING_CMD11;
282
283 /*
284 * We need to disable low power mode (automatic clock stop)
285 * while doing voltage switch so we don't confuse the card,
286 * since stopping the clock is a specific part of the UHS
287 * voltage change dance.
288 *
289 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
290 * unconditionally turned back on in dw_mci_setup_bus() if it's
291 * ever called with a non-zero clock. That shouldn't happen
292 * until the voltage change is all done.
293 */
294 clk_en_a = mci_readl(host, CLKENA);
295 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
296 mci_writel(host, CLKENA, clk_en_a);
297 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
298 SDMMC_CMD_PRV_DAT_WAIT, 0);
299 }
300
f95f3850
WN		 301 if (cmd->flags & MMC_RSP_PRESENT) {
302 /* We expect a response, so set this bit */
303 cmdr |= SDMMC_CMD_RESP_EXP;
304 if (cmd->flags & MMC_RSP_136)
305 cmdr |= SDMMC_CMD_RESP_LONG;
306 }
307
308 if (cmd->flags & MMC_RSP_CRC)
309 cmdr |= SDMMC_CMD_RESP_CRC;
310
0349c085 311 if (cmd->data) {
f95f3850 312 cmdr |= SDMMC_CMD_DAT_EXP;
0349c085 313 if (cmd->data->flags & MMC_DATA_WRITE)
f95f3850
WN		 314 cmdr |= SDMMC_CMD_DAT_WR;
315 }
316
aaaaeb7a
JC		 317 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
318 cmdr |= SDMMC_CMD_USE_HOLD_REG;
800d78bf 319
f95f3850
WN		 320 return cmdr;
321}
322
90c2143a
SJ		 323static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
324{
325 struct mmc_command *stop;
326 u32 cmdr;
327
328 if (!cmd->data)
329 return 0;
330
331 stop = &host->stop_abort;
332 cmdr = cmd->opcode;
333 memset(stop, 0, sizeof(struct mmc_command));
334
335 if (cmdr == MMC_READ_SINGLE_BLOCK ||
336 cmdr == MMC_READ_MULTIPLE_BLOCK ||
337 cmdr == MMC_WRITE_BLOCK ||
6c2c6506
UH		 338 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
339 cmdr == MMC_SEND_TUNING_BLOCK ||
340 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
90c2143a
SJ		 341 stop->opcode = MMC_STOP_TRANSMISSION;
342 stop->arg = 0;
343 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
344 } else if (cmdr == SD_IO_RW_EXTENDED) {
345 stop->opcode = SD_IO_RW_DIRECT;
346 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
347 ((cmd->arg >> 28) & 0x7);
348 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
349 } else {
350 return 0;
351 }
352
353 cmdr = stop->opcode | SDMMC_CMD_STOP |
354 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
355
8c005b40
JC		 356 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->cur_slot->flags))
357 cmdr |= SDMMC_CMD_USE_HOLD_REG;
358
90c2143a
SJ		 359 return cmdr;
360}
361
0bdbd0e8
DA		 362static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
363{
b6d2d81c 364 u32 status;
0bdbd0e8
DA		 365
366 /*
367 * Databook says that before issuing a new data transfer command
368 * we need to check to see if the card is busy. Data transfer commands
369 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
370 *
371 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
372 * expected.
373 */
374 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
375 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
b6d2d81c
SL		 376 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
377 status,
378 !(status & SDMMC_STATUS_BUSY),
379 10, 500 * USEC_PER_MSEC))
380 dev_err(host->dev, "Busy; trying anyway\n");
0bdbd0e8
DA		 381 }
382}
383
f95f3850
WN		 384static void dw_mci_start_command(struct dw_mci *host,
385 struct mmc_command *cmd, u32 cmd_flags)
386{
387 host->cmd = cmd;
4a90920c 388 dev_vdbg(host->dev,
f95f3850
WN		 389 "start command: ARGR=0x%08x CMDR=0x%08x\n",
390 cmd->arg, cmd_flags);
391
392 mci_writel(host, CMDARG, cmd->arg);
0e3a22c0 393 wmb(); /* drain writebuffer */
0bdbd0e8 394 dw_mci_wait_while_busy(host, cmd_flags);
f95f3850
WN		 395
396 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
397}
398
90c2143a 399static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
f95f3850 400{
e13c3c08 401 struct mmc_command *stop = &host->stop_abort;
0e3a22c0 402
90c2143a 403 dw_mci_start_command(host, stop, host->stop_cmdr);
f95f3850
WN		 404}
405
406/* DMA interface functions */
407static void dw_mci_stop_dma(struct dw_mci *host)
408{
03e8cb53 409 if (host->using_dma) {
f95f3850
WN		 410 host->dma_ops->stop(host);
411 host->dma_ops->cleanup(host);
f95f3850 412 }
aa50f259
SJ		 413
414 /* Data transfer was stopped by the interrupt handler */
415 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
f95f3850
WN		 416}
417
9aa51408
SJ		 418static int dw_mci_get_dma_dir(struct mmc_data *data)
419{
420 if (data->flags & MMC_DATA_WRITE)
421 return DMA_TO_DEVICE;
422 else
423 return DMA_FROM_DEVICE;
424}
425
f95f3850
WN		 426static void dw_mci_dma_cleanup(struct dw_mci *host)
427{
428 struct mmc_data *data = host->data;
429
a4cc7eb4
JC		 430 if (data && data->host_cookie == COOKIE_MAPPED) {
431 dma_unmap_sg(host->dev,
432 data->sg,
433 data->sg_len,
434 dw_mci_get_dma_dir(data));
435 data->host_cookie = COOKIE_UNMAPPED;
436 }
f95f3850
WN		 437}
438
5ce9d961
SJ		 439static void dw_mci_idmac_reset(struct dw_mci *host)
440{
441 u32 bmod = mci_readl(host, BMOD);
442 /* Software reset of DMA */
443 bmod |= SDMMC_IDMAC_SWRESET;
444 mci_writel(host, BMOD, bmod);
445}
446
f95f3850
WN		 447static void dw_mci_idmac_stop_dma(struct dw_mci *host)
448{
449 u32 temp;
450
451 /* Disable and reset the IDMAC interface */
452 temp = mci_readl(host, CTRL);
453 temp &= ~SDMMC_CTRL_USE_IDMAC;
454 temp |= SDMMC_CTRL_DMA_RESET;
455 mci_writel(host, CTRL, temp);
456
457 /* Stop the IDMAC running */
458 temp = mci_readl(host, BMOD);
a5289a43 459 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
5ce9d961 460 temp |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 461 mci_writel(host, BMOD, temp);
462}
463
3fc7eaef 464static void dw_mci_dmac_complete_dma(void *arg)
f95f3850 465{
3fc7eaef 466 struct dw_mci *host = arg;
f95f3850
WN		 467 struct mmc_data *data = host->data;
468
4a90920c 469 dev_vdbg(host->dev, "DMA complete\n");
f95f3850 470
3fc7eaef
SL		 471 if ((host->use_dma == TRANS_MODE_EDMAC) &&
472 data && (data->flags & MMC_DATA_READ))
473 /* Invalidate cache after read */
474 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
475 data->sg,
476 data->sg_len,
477 DMA_FROM_DEVICE);
478
f95f3850
WN		 479 host->dma_ops->cleanup(host);
480
481 /*
482 * If the card was removed, data will be NULL. No point in trying to
483 * send the stop command or waiting for NBUSY in this case.
484 */
485 if (data) {
486 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
487 tasklet_schedule(&host->tasklet);
488 }
489}
490
3b2a067b
SL		 491static int dw_mci_idmac_init(struct dw_mci *host)
492{
493 int i;
494
495 if (host->dma_64bit_address == 1) {
496 struct idmac_desc_64addr *p;
497 /* Number of descriptors in the ring buffer */
cc190d4c
SL		 498 host->ring_size =
499 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
3b2a067b
SL		 500
501 /* Forward link the descriptor list */
502 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
503 i++, p++) {
504 p->des6 = (host->sg_dma +
505 (sizeof(struct idmac_desc_64addr) *
506 (i + 1))) & 0xffffffff;
507
508 p->des7 = (u64)(host->sg_dma +
509 (sizeof(struct idmac_desc_64addr) *
510 (i + 1))) >> 32;
511 /* Initialize reserved and buffer size fields to "0" */
512 p->des1 = 0;
513 p->des2 = 0;
514 p->des3 = 0;
515 }
516
517 /* Set the last descriptor as the end-of-ring descriptor */
518 p->des6 = host->sg_dma & 0xffffffff;
519 p->des7 = (u64)host->sg_dma >> 32;
520 p->des0 = IDMAC_DES0_ER;
521
522 } else {
523 struct idmac_desc *p;
524 /* Number of descriptors in the ring buffer */
cc190d4c
SL		 525 host->ring_size =
526 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
3b2a067b
SL		 527
528 /* Forward link the descriptor list */
529 for (i = 0, p = host->sg_cpu;
530 i < host->ring_size - 1;
531 i++, p++) {
532 p->des3 = cpu_to_le32(host->sg_dma +
533 (sizeof(struct idmac_desc) * (i + 1)));
534 p->des1 = 0;
535 }
536
537 /* Set the last descriptor as the end-of-ring descriptor */
538 p->des3 = cpu_to_le32(host->sg_dma);
539 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
540 }
541
542 dw_mci_idmac_reset(host);
543
544 if (host->dma_64bit_address == 1) {
545 /* Mask out interrupts - get Tx & Rx complete only */
546 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
547 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
548 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
549
550 /* Set the descriptor base address */
551 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
552 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
553
554 } else {
555 /* Mask out interrupts - get Tx & Rx complete only */
556 mci_writel(host, IDSTS, IDMAC_INT_CLR);
557 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
558 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
559
560 /* Set the descriptor base address */
561 mci_writel(host, DBADDR, host->sg_dma);
562 }
563
564 return 0;
565}
566
567static inline int dw_mci_prepare_desc64(struct dw_mci *host,
ec0baaa6
SL		 568 struct mmc_data *data,
569 unsigned int sg_len)
f95f3850 570{
5959b32e 571 unsigned int desc_len;
ec0baaa6 572 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
b6d2d81c 573 u32 val;
f95f3850 574 int i;
0e3a22c0 575
ec0baaa6 576 desc_first = desc_last = desc = host->sg_cpu;
5959b32e 577
ec0baaa6
SL		 578 for (i = 0; i < sg_len; i++) {
579 unsigned int length = sg_dma_len(&data->sg[i]);
69d99fdc 580
ec0baaa6 581 u64 mem_addr = sg_dma_address(&data->sg[i]);
0e3a22c0 582
ec0baaa6
SL		 583 for ( ; length ; desc++) {
584 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
585 length : DW_MCI_DESC_DATA_LENGTH;
f95f3850 586
ec0baaa6 587 length -= desc_len;
5959b32e 588
3b2a067b
SL		 589 /*
590 * Wait for the former clear OWN bit operation
591 * of IDMAC to make sure that this descriptor
592 * isn't still owned by IDMAC as IDMAC's write
593 * ops and CPU's read ops are asynchronous.
594 */
b6d2d81c
SL		 595 if (readl_poll_timeout_atomic(&desc->des0, val,
596 !(val & IDMAC_DES0_OWN),
597 10, 100 * USEC_PER_MSEC))
598 goto err_own_bit;
3b2a067b 599
ec0baaa6
SL		 600 /*
601 * Set the OWN bit and disable interrupts
602 * for this descriptor
603 */
604 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
605 IDMAC_DES0_CH;
5959b32e 606
ec0baaa6
SL		 607 /* Buffer length */
608 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
5959b32e 609
ec0baaa6
SL		 610 /* Physical address to DMA to/from */
611 desc->des4 = mem_addr & 0xffffffff;
612 desc->des5 = mem_addr >> 32;
5959b32e 613
ec0baaa6
SL		 614 /* Update physical address for the next desc */
615 mem_addr += desc_len;
5959b32e 616
ec0baaa6
SL		 617 /* Save pointer to the last descriptor */
618 desc_last = desc;
69d99fdc 619 }
ec0baaa6 620 }
f95f3850 621
ec0baaa6
SL		 622 /* Set first descriptor */
623 desc_first->des0 |= IDMAC_DES0_FD;
f95f3850 624
ec0baaa6
SL		 625 /* Set last descriptor */
626 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
627 desc_last->des0 |= IDMAC_DES0_LD;
3b2a067b
SL		 628
629 return 0;
630err_own_bit:
631 /* restore the descriptor chain as it's polluted */
26be9d70 632 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
cc190d4c 633 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
3b2a067b
SL		 634 dw_mci_idmac_init(host);
635 return -EINVAL;
ec0baaa6 636}
5959b32e 637
69d99fdc 638
3b2a067b 639static inline int dw_mci_prepare_desc32(struct dw_mci *host,
ec0baaa6
SL		 640 struct mmc_data *data,
641 unsigned int sg_len)
642{
643 unsigned int desc_len;
644 struct idmac_desc *desc_first, *desc_last, *desc;
b6d2d81c 645 u32 val;
ec0baaa6 646 int i;
0e3a22c0 647
ec0baaa6 648 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 649
ec0baaa6
SL		 650 for (i = 0; i < sg_len; i++) {
651 unsigned int length = sg_dma_len(&data->sg[i]);
5959b32e 652
ec0baaa6 653 u32 mem_addr = sg_dma_address(&data->sg[i]);
5959b32e 654
ec0baaa6
SL		 655 for ( ; length ; desc++) {
656 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
657 length : DW_MCI_DESC_DATA_LENGTH;
5959b32e 658
ec0baaa6 659 length -= desc_len;
f95f3850 660
3b2a067b
SL		 661 /*
662 * Wait for the former clear OWN bit operation
663 * of IDMAC to make sure that this descriptor
664 * isn't still owned by IDMAC as IDMAC's write
665 * ops and CPU's read ops are asynchronous.
666 */
b6d2d81c
SL		 667 if (readl_poll_timeout_atomic(&desc->des0, val,
668 IDMAC_OWN_CLR64(val),
669 10,
670 100 * USEC_PER_MSEC))
671 goto err_own_bit;
3b2a067b 672
ec0baaa6
SL		 673 /*
674 * Set the OWN bit and disable interrupts
675 * for this descriptor
676 */
677 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
678 IDMAC_DES0_DIC |
679 IDMAC_DES0_CH);
5959b32e 680
ec0baaa6
SL		 681 /* Buffer length */
682 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
5959b32e 683
ec0baaa6
SL		 684 /* Physical address to DMA to/from */
685 desc->des2 = cpu_to_le32(mem_addr);
69d99fdc 686
ec0baaa6
SL		 687 /* Update physical address for the next desc */
688 mem_addr += desc_len;
f95f3850 689
ec0baaa6
SL		 690 /* Save pointer to the last descriptor */
691 desc_last = desc;
692 }
69d99fdc 693 }
f95f3850 694
ec0baaa6
SL		 695 /* Set first descriptor */
696 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
697
698 /* Set last descriptor */
699 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
700 IDMAC_DES0_DIC));
701 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
3b2a067b
SL		 702
703 return 0;
704err_own_bit:
705 /* restore the descriptor chain as it's polluted */
26be9d70 706 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
cc190d4c 707 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
3b2a067b
SL		 708 dw_mci_idmac_init(host);
709 return -EINVAL;
f95f3850
WN		 710}
711
3fc7eaef 712static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
f95f3850
WN		 713{
714 u32 temp;
3b2a067b 715 int ret;
f95f3850 716
ec0baaa6 717 if (host->dma_64bit_address == 1)
3b2a067b 718 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
ec0baaa6 719 else
3b2a067b
SL		 720 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
721
722 if (ret)
723 goto out;
ec0baaa6
SL		 724
725 /* drain writebuffer */
726 wmb();
f95f3850 727
536f6b91
SR		 728 /* Make sure to reset DMA in case we did PIO before this */
729 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
730 dw_mci_idmac_reset(host);
731
f95f3850
WN		 732 /* Select IDMAC interface */
733 temp = mci_readl(host, CTRL);
734 temp |= SDMMC_CTRL_USE_IDMAC;
735 mci_writel(host, CTRL, temp);
736
0e3a22c0 737 /* drain writebuffer */
f95f3850
WN		 738 wmb();
739
740 /* Enable the IDMAC */
741 temp = mci_readl(host, BMOD);
a5289a43 742 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 743 mci_writel(host, BMOD, temp);
744
745 /* Start it running */
746 mci_writel(host, PLDMND, 1);
3fc7eaef 747
3b2a067b
SL		 748out:
749 return ret;
f95f3850
WN		 750}
751
8e2b36ea 752static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 753 .init = dw_mci_idmac_init,
754 .start = dw_mci_idmac_start_dma,
755 .stop = dw_mci_idmac_stop_dma,
3fc7eaef
SL		 756 .complete = dw_mci_dmac_complete_dma,
757 .cleanup = dw_mci_dma_cleanup,
758};
759
760static void dw_mci_edmac_stop_dma(struct dw_mci *host)
761{
ab925a31 762 dmaengine_terminate_async(host->dms->ch);
3fc7eaef
SL		 763}
764
765static int dw_mci_edmac_start_dma(struct dw_mci *host,
766 unsigned int sg_len)
767{
768 struct dma_slave_config cfg;
769 struct dma_async_tx_descriptor *desc = NULL;
770 struct scatterlist *sgl = host->data->sg;
771 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
772 u32 sg_elems = host->data->sg_len;
773 u32 fifoth_val;
774 u32 fifo_offset = host->fifo_reg - host->regs;
775 int ret = 0;
776
777 /* Set external dma config: burst size, burst width */
260b3164 778 cfg.dst_addr = host->phy_regs + fifo_offset;
3fc7eaef
SL		 779 cfg.src_addr = cfg.dst_addr;
780 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
781 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
782
783 /* Match burst msize with external dma config */
784 fifoth_val = mci_readl(host, FIFOTH);
785 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
786 cfg.src_maxburst = cfg.dst_maxburst;
787
788 if (host->data->flags & MMC_DATA_WRITE)
789 cfg.direction = DMA_MEM_TO_DEV;
790 else
791 cfg.direction = DMA_DEV_TO_MEM;
792
793 ret = dmaengine_slave_config(host->dms->ch, &cfg);
794 if (ret) {
795 dev_err(host->dev, "Failed to config edmac.\n");
796 return -EBUSY;
797 }
798
799 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
800 sg_len, cfg.direction,
801 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
802 if (!desc) {
803 dev_err(host->dev, "Can't prepare slave sg.\n");
804 return -EBUSY;
805 }
806
807 /* Set dw_mci_dmac_complete_dma as callback */
808 desc->callback = dw_mci_dmac_complete_dma;
809 desc->callback_param = (void *)host;
810 dmaengine_submit(desc);
811
812 /* Flush cache before write */
813 if (host->data->flags & MMC_DATA_WRITE)
814 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
815 sg_elems, DMA_TO_DEVICE);
816
817 dma_async_issue_pending(host->dms->ch);
818
819 return 0;
820}
821
822static int dw_mci_edmac_init(struct dw_mci *host)
823{
824 /* Request external dma channel */
825 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
826 if (!host->dms)
827 return -ENOMEM;
828
829 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
830 if (!host->dms->ch) {
4539d36e 831 dev_err(host->dev, "Failed to get external DMA channel.\n");
3fc7eaef
SL		 832 kfree(host->dms);
833 host->dms = NULL;
834 return -ENXIO;
835 }
836
837 return 0;
838}
839
840static void dw_mci_edmac_exit(struct dw_mci *host)
841{
842 if (host->dms) {
843 if (host->dms->ch) {
844 dma_release_channel(host->dms->ch);
845 host->dms->ch = NULL;
846 }
847 kfree(host->dms);
848 host->dms = NULL;
849 }
850}
851
852static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
853 .init = dw_mci_edmac_init,
854 .exit = dw_mci_edmac_exit,
855 .start = dw_mci_edmac_start_dma,
856 .stop = dw_mci_edmac_stop_dma,
857 .complete = dw_mci_dmac_complete_dma,
885c3e80
SJ		 858 .cleanup = dw_mci_dma_cleanup,
859};
885c3e80 860
9aa51408
SJ		 861static int dw_mci_pre_dma_transfer(struct dw_mci *host,
862 struct mmc_data *data,
a4cc7eb4 863 int cookie)
f95f3850
WN		 864{
865 struct scatterlist *sg;
9aa51408 866 unsigned int i, sg_len;
03e8cb53 867
a4cc7eb4
JC		 868 if (data->host_cookie == COOKIE_PRE_MAPPED)
869 return data->sg_len;
f95f3850
WN		 870
871 /*
872 * We don't do DMA on "complex" transfers, i.e. with
873 * non-word-aligned buffers or lengths. Also, we don't bother
874 * with all the DMA setup overhead for short transfers.
875 */
876 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
877 return -EINVAL;
9aa51408 878
f95f3850
WN		 879 if (data->blksz & 3)
880 return -EINVAL;
881
882 for_each_sg(data->sg, sg, data->sg_len, i) {
883 if (sg->offset & 3 || sg->length & 3)
884 return -EINVAL;
885 }
886
4a90920c 887 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 888 data->sg,
889 data->sg_len,
890 dw_mci_get_dma_dir(data));
891 if (sg_len == 0)
892 return -EINVAL;
03e8cb53 893
a4cc7eb4 894 data->host_cookie = cookie;
f95f3850 895
9aa51408
SJ		 896 return sg_len;
897}
898
9aa51408 899static void dw_mci_pre_req(struct mmc_host *mmc,
d3c6aac3 900 struct mmc_request *mrq)
9aa51408
SJ		 901{
902 struct dw_mci_slot *slot = mmc_priv(mmc);
903 struct mmc_data *data = mrq->data;
904
905 if (!slot->host->use_dma || !data)
906 return;
907
a4cc7eb4
JC		 908 /* This data might be unmapped at this time */
909 data->host_cookie = COOKIE_UNMAPPED;
9aa51408 910
a4cc7eb4
JC		 911 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
912 COOKIE_PRE_MAPPED) < 0)
913 data->host_cookie = COOKIE_UNMAPPED;
9aa51408
SJ		 914}
915
916static void dw_mci_post_req(struct mmc_host *mmc,
917 struct mmc_request *mrq,
918 int err)
919{
920 struct dw_mci_slot *slot = mmc_priv(mmc);
921 struct mmc_data *data = mrq->data;
922
923 if (!slot->host->use_dma || !data)
924 return;
925
a4cc7eb4 926 if (data->host_cookie != COOKIE_UNMAPPED)
4a90920c 927 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 928 data->sg,
929 data->sg_len,
930 dw_mci_get_dma_dir(data));
a4cc7eb4 931 data->host_cookie = COOKIE_UNMAPPED;
9aa51408
SJ		 932}
933
671fa142
SL		 934static int dw_mci_get_cd(struct mmc_host *mmc)
935{
936 int present;
937 struct dw_mci_slot *slot = mmc_priv(mmc);
938 struct dw_mci *host = slot->host;
939 int gpio_cd = mmc_gpio_get_cd(mmc);
940
941 /* Use platform get_cd function, else try onboard card detect */
942 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
943 || !mmc_card_is_removable(mmc))) {
944 present = 1;
945
946 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
947 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
948 dev_info(&mmc->class_dev,
949 "card is polling.\n");
950 } else {
951 dev_info(&mmc->class_dev,
952 "card is non-removable.\n");
953 }
954 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
955 }
956
957 return present;
958 } else if (gpio_cd >= 0)
959 present = gpio_cd;
960 else
961 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
962 == 0 ? 1 : 0;
963
964 spin_lock_bh(&host->lock);
965 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
966 dev_dbg(&mmc->class_dev, "card is present\n");
967 else if (!present &&
968 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
969 dev_dbg(&mmc->class_dev, "card is not present\n");
970 spin_unlock_bh(&host->lock);
971
972 return present;
973}
974
52426899
SJ		 975static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
976{
52426899
SJ		 977 unsigned int blksz = data->blksz;
978 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
979 u32 fifo_width = 1 << host->data_shift;
980 u32 blksz_depth = blksz / fifo_width, fifoth_val;
981 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
0e3a22c0 982 int idx = ARRAY_SIZE(mszs) - 1;
52426899 983
3fc7eaef
SL		 984 /* pio should ship this scenario */
985 if (!host->use_dma)
986 return;
987
52426899
SJ		 988 tx_wmark = (host->fifo_depth) / 2;
989 tx_wmark_invers = host->fifo_depth - tx_wmark;
990
991 /*
992 * MSIZE is '1',
993 * if blksz is not a multiple of the FIFO width
994 */
20753569 995 if (blksz % fifo_width)
52426899 996 goto done;
52426899
SJ		 997
998 do {
999 if (!((blksz_depth % mszs[idx]) ||
1000 (tx_wmark_invers % mszs[idx]))) {
1001 msize = idx;
1002 rx_wmark = mszs[idx] - 1;
1003 break;
1004 }
1005 } while (--idx > 0);
1006 /*
1007 * If idx is '0', it won't be tried
1008 * Thus, initial values are uesed
1009 */
1010done:
1011 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1012 mci_writel(host, FIFOTH, fifoth_val);
52426899
SJ		 1013}
1014
7e4bf1bc 1015static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
f1d2736c
SJ		 1016{
1017 unsigned int blksz = data->blksz;
1018 u32 blksz_depth, fifo_depth;
1019 u16 thld_size;
7e4bf1bc 1020 u8 enable;
f1d2736c 1021
66dfd101
JH		 1022 /*
1023 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1024 * in the FIFO region, so we really shouldn't access it).
1025 */
7e4bf1bc
JC		 1026 if (host->verid < DW_MMC_240A ||
1027 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1028 return;
1029
1030 /*
1031 * Card write Threshold is introduced since 2.80a
1032 * It's used when HS400 mode is enabled.
1033 */
1034 if (data->flags & MMC_DATA_WRITE &&
1035 !(host->timing != MMC_TIMING_MMC_HS400))
66dfd101
JH		 1036 return;
1037
7e4bf1bc
JC		 1038 if (data->flags & MMC_DATA_WRITE)
1039 enable = SDMMC_CARD_WR_THR_EN;
1040 else
1041 enable = SDMMC_CARD_RD_THR_EN;
1042
f1d2736c
SJ		 1043 if (host->timing != MMC_TIMING_MMC_HS200 &&
1044 host->timing != MMC_TIMING_UHS_SDR104)
1045 goto disable;
1046
1047 blksz_depth = blksz / (1 << host->data_shift);
1048 fifo_depth = host->fifo_depth;
1049
1050 if (blksz_depth > fifo_depth)
1051 goto disable;
1052
1053 /*
1054 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1055 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1056 * Currently just choose blksz.
1057 */
1058 thld_size = blksz;
7e4bf1bc 1059 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
f1d2736c
SJ		 1060 return;
1061
1062disable:
7e4bf1bc 1063 mci_writel(host, CDTHRCTL, 0);
f1d2736c
SJ		 1064}
1065
9aa51408
SJ		 1066static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1067{
f8c58c11 1068 unsigned long irqflags;
9aa51408
SJ		 1069 int sg_len;
1070 u32 temp;
1071
1072 host->using_dma = 0;
1073
1074 /* If we don't have a channel, we can't do DMA */
1075 if (!host->use_dma)
1076 return -ENODEV;
1077
a4cc7eb4 1078 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
a99aa9b9
SJ		 1079 if (sg_len < 0) {
1080 host->dma_ops->stop(host);
9aa51408 1081 return sg_len;
a99aa9b9 1082 }
9aa51408
SJ		 1083
1084 host->using_dma = 1;
f95f3850 1085
3fc7eaef
SL		 1086 if (host->use_dma == TRANS_MODE_IDMAC)
1087 dev_vdbg(host->dev,
1088 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1089 (unsigned long)host->sg_cpu,
1090 (unsigned long)host->sg_dma,
1091 sg_len);
f95f3850 1092
52426899
SJ		 1093 /*
1094 * Decide the MSIZE and RX/TX Watermark.
1095 * If current block size is same with previous size,
1096 * no need to update fifoth.
1097 */
1098 if (host->prev_blksz != data->blksz)
1099 dw_mci_adjust_fifoth(host, data);
1100
f95f3850
WN		 1101 /* Enable the DMA interface */
1102 temp = mci_readl(host, CTRL);
1103 temp |= SDMMC_CTRL_DMA_ENABLE;
1104 mci_writel(host, CTRL, temp);
1105
1106 /* Disable RX/TX IRQs, let DMA handle it */
f8c58c11 1107 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1108 temp = mci_readl(host, INTMASK);
1109 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1110 mci_writel(host, INTMASK, temp);
f8c58c11 1111 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850 1112
3fc7eaef 1113 if (host->dma_ops->start(host, sg_len)) {
647f80a1 1114 host->dma_ops->stop(host);
d12d0cb1
SL		 1115 /* We can't do DMA, try PIO for this one */
1116 dev_dbg(host->dev,
1117 "%s: fall back to PIO mode for current transfer\n",
1118 __func__);
3fc7eaef
SL		 1119 return -ENODEV;
1120 }
f95f3850
WN		 1121
1122 return 0;
1123}
1124
1125static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1126{
f8c58c11 1127 unsigned long irqflags;
0e3a22c0 1128 int flags = SG_MITER_ATOMIC;
f95f3850
WN		 1129 u32 temp;
1130
1131 data->error = -EINPROGRESS;
1132
1133 WARN_ON(host->data);
1134 host->sg = NULL;
1135 host->data = data;
1136
7e4bf1bc 1137 if (data->flags & MMC_DATA_READ)
55c5efbc 1138 host->dir_status = DW_MCI_RECV_STATUS;
7e4bf1bc 1139 else
55c5efbc 1140 host->dir_status = DW_MCI_SEND_STATUS;
7e4bf1bc
JC		 1141
1142 dw_mci_ctrl_thld(host, data);
55c5efbc 1143
f95f3850 1144 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 1145 if (host->data->flags & MMC_DATA_READ)
1146 flags |= SG_MITER_TO_SG;
1147 else
1148 flags |= SG_MITER_FROM_SG;
1149
1150 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 1151 host->sg = data->sg;
34b664a2
JH		 1152 host->part_buf_start = 0;
1153 host->part_buf_count = 0;
f95f3850 1154
b40af3aa 1155 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f8c58c11
DA		 1156
1157 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1158 temp = mci_readl(host, INTMASK);
1159 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1160 mci_writel(host, INTMASK, temp);
f8c58c11 1161 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 1162
1163 temp = mci_readl(host, CTRL);
1164 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1165 mci_writel(host, CTRL, temp);
52426899
SJ		 1166
1167 /*
d6fced83
JN		 1168 * Use the initial fifoth_val for PIO mode. If wm_algined
1169 * is set, we set watermark same as data size.
52426899
SJ		 1170 * If next issued data may be transfered by DMA mode,
1171 * prev_blksz should be invalidated.
1172 */
d6fced83
JN		 1173 if (host->wm_aligned)
1174 dw_mci_adjust_fifoth(host, data);
1175 else
1176 mci_writel(host, FIFOTH, host->fifoth_val);
52426899
SJ		 1177 host->prev_blksz = 0;
1178 } else {
1179 /*
1180 * Keep the current block size.
1181 * It will be used to decide whether to update
1182 * fifoth register next time.
1183 */
1184 host->prev_blksz = data->blksz;
f95f3850
WN		 1185 }
1186}
1187
1188static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1189{
1190 struct dw_mci *host = slot->host;
f95f3850
WN		 1191 unsigned int cmd_status = 0;
1192
1193 mci_writel(host, CMDARG, arg);
0e3a22c0 1194 wmb(); /* drain writebuffer */
0bdbd0e8 1195 dw_mci_wait_while_busy(host, cmd);
f95f3850
WN		 1196 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1197
b6d2d81c
SL		 1198 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
1199 !(cmd_status & SDMMC_CMD_START),
1200 1, 500 * USEC_PER_MSEC))
1201 dev_err(&slot->mmc->class_dev,
1202 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1203 cmd, arg, cmd_status);
f95f3850
WN		 1204}
1205
ab269128 1206static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 1207{
1208 struct dw_mci *host = slot->host;
fdf492a1 1209 unsigned int clock = slot->clock;
f95f3850 1210 u32 div;
9623b5b9 1211 u32 clk_en_a;
01730558
DA		 1212 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1213
1214 /* We must continue to set bit 28 in CMD until the change is complete */
1215 if (host->state == STATE_WAITING_CMD11_DONE)
1216 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
f95f3850 1217
fdf492a1
DA		 1218 if (!clock) {
1219 mci_writel(host, CLKENA, 0);
01730558 1220 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
fdf492a1
DA		 1221 } else if (clock != host->current_speed || force_clkinit) {
1222 div = host->bus_hz / clock;
1223 if (host->bus_hz % clock && host->bus_hz > clock)
f95f3850
WN		 1224 /*
1225 * move the + 1 after the divide to prevent
1226 * over-clocking the card.
1227 */
e419990b
SJ		 1228 div += 1;
1229
fdf492a1 1230 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850 1231
e6cd7a8e
JC		 1232 if ((clock != slot->__clk_old &&
1233 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1234 force_clkinit) {
ce69e2fe
SL		 1235 /* Silent the verbose log if calling from PM context */
1236 if (!force_clkinit)
1237 dev_info(&slot->mmc->class_dev,
1238 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1239 slot->id, host->bus_hz, clock,
1240 div ? ((host->bus_hz / div) >> 1) :
1241 host->bus_hz, div);
f95f3850 1242
e6cd7a8e
JC		 1243 /*
1244 * If card is polling, display the message only
1245 * one time at boot time.
1246 */
1247 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1248 slot->mmc->f_min == clock)
1249 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1250 }
1251
f95f3850
WN		 1252 /* disable clock */
1253 mci_writel(host, CLKENA, 0);
1254 mci_writel(host, CLKSRC, 0);
1255
1256 /* inform CIU */
01730558 1257 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850
WN		 1258
1259 /* set clock to desired speed */
1260 mci_writel(host, CLKDIV, div);
1261
1262 /* inform CIU */
01730558 1263 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1264
9623b5b9
DA		 1265 /* enable clock; only low power if no SDIO */
1266 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
b24c8b26 1267 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
9623b5b9
DA		 1268 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1269 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 1270
1271 /* inform CIU */
01730558 1272 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
005d675a
JC		 1273
1274 /* keep the last clock value that was requested from core */
1275 slot->__clk_old = clock;
f95f3850
WN		 1276 }
1277
fdf492a1
DA		 1278 host->current_speed = clock;
1279
f95f3850 1280 /* Set the current slot bus width */
1d56c453 1281 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 1282}
1283
053b3ce6
SJ		 1284static void __dw_mci_start_request(struct dw_mci *host,
1285 struct dw_mci_slot *slot,
1286 struct mmc_command *cmd)
f95f3850
WN		 1287{
1288 struct mmc_request *mrq;
f95f3850
WN		 1289 struct mmc_data *data;
1290 u32 cmdflags;
1291
1292 mrq = slot->mrq;
f95f3850 1293
f95f3850
WN		 1294 host->cur_slot = slot;
1295 host->mrq = mrq;
1296
1297 host->pending_events = 0;
1298 host->completed_events = 0;
e352c813 1299 host->cmd_status = 0;
f95f3850 1300 host->data_status = 0;
e352c813 1301 host->dir_status = 0;
f95f3850 1302
053b3ce6 1303 data = cmd->data;
f95f3850 1304 if (data) {
f16afa88 1305 mci_writel(host, TMOUT, 0xFFFFFFFF);
f95f3850
WN		 1306 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1307 mci_writel(host, BLKSIZ, data->blksz);
1308 }
1309
f95f3850
WN		 1310 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1311
1312 /* this is the first command, send the initialization clock */
1313 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1314 cmdflags |= SDMMC_CMD_INIT;
1315
1316 if (data) {
1317 dw_mci_submit_data(host, data);
0e3a22c0 1318 wmb(); /* drain writebuffer */
f95f3850
WN		 1319 }
1320
1321 dw_mci_start_command(host, cmd, cmdflags);
1322
5c935165 1323 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
49ba0302
DA		 1324 unsigned long irqflags;
1325
5c935165 1326 /*
8886a6fd
DA		 1327 * Databook says to fail after 2ms w/ no response, but evidence
1328 * shows that sometimes the cmd11 interrupt takes over 130ms.
1329 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1330 * is just about to roll over.
49ba0302
DA		 1331 *
1332 * We do this whole thing under spinlock and only if the
1333 * command hasn't already completed (indicating the the irq
1334 * already ran so we don't want the timeout).
5c935165 1335 */
49ba0302
DA		 1336 spin_lock_irqsave(&host->irq_lock, irqflags);
1337 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1338 mod_timer(&host->cmd11_timer,
1339 jiffies + msecs_to_jiffies(500) + 1);
1340 spin_unlock_irqrestore(&host->irq_lock, irqflags);
5c935165
DA		 1341 }
1342
e13c3c08 1343 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
f95f3850
WN		 1344}
1345
053b3ce6
SJ		 1346static void dw_mci_start_request(struct dw_mci *host,
1347 struct dw_mci_slot *slot)
1348{
1349 struct mmc_request *mrq = slot->mrq;
1350 struct mmc_command *cmd;
1351
1352 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1353 __dw_mci_start_request(host, slot, cmd);
1354}
1355
7456caae 1356/* must be called with host->lock held */
f95f3850
WN		 1357static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1358 struct mmc_request *mrq)
1359{
1360 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1361 host->state);
1362
f95f3850
WN		 1363 slot->mrq = mrq;
1364
01730558
DA		 1365 if (host->state == STATE_WAITING_CMD11_DONE) {
1366 dev_warn(&slot->mmc->class_dev,
1367 "Voltage change didn't complete\n");
1368 /*
1369 * this case isn't expected to happen, so we can
1370 * either crash here or just try to continue on
1371 * in the closest possible state
1372 */
1373 host->state = STATE_IDLE;
1374 }
1375
f95f3850
WN		 1376 if (host->state == STATE_IDLE) {
1377 host->state = STATE_SENDING_CMD;
1378 dw_mci_start_request(host, slot);
1379 } else {
1380 list_add_tail(&slot->queue_node, &host->queue);
1381 }
f95f3850
WN		 1382}
1383
1384static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1385{
1386 struct dw_mci_slot *slot = mmc_priv(mmc);
1387 struct dw_mci *host = slot->host;
1388
1389 WARN_ON(slot->mrq);
1390
7456caae
JH		 1391 /*
1392 * The check for card presence and queueing of the request must be
1393 * atomic, otherwise the card could be removed in between and the
1394 * request wouldn't fail until another card was inserted.
1395 */
7456caae 1396
56f6911c 1397 if (!dw_mci_get_cd(mmc)) {
f95f3850
WN		 1398 mrq->cmd->error = -ENOMEDIUM;
1399 mmc_request_done(mmc, mrq);
1400 return;
1401 }
1402
56f6911c
SL		 1403 spin_lock_bh(&host->lock);
1404
f95f3850 1405 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 1406
1407 spin_unlock_bh(&host->lock);
f95f3850
WN		 1408}
1409
1410static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1411{
1412 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 1413 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 1414 u32 regs;
51da2240 1415 int ret;
f95f3850 1416
f95f3850 1417 switch (ios->bus_width) {
f95f3850
WN		 1418 case MMC_BUS_WIDTH_4:
1419 slot->ctype = SDMMC_CTYPE_4BIT;
1420 break;
c9b2a06f
JC		 1421 case MMC_BUS_WIDTH_8:
1422 slot->ctype = SDMMC_CTYPE_8BIT;
1423 break;
b2f7cb45
JC		 1424 default:
1425 /* set default 1 bit mode */
1426 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 1427 }
1428
3f514291
SJ		 1429 regs = mci_readl(slot->host, UHS_REG);
1430
41babf75 1431 /* DDR mode set */
80113132 1432 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
7cc8d580 1433 ios->timing == MMC_TIMING_UHS_DDR50 ||
80113132 1434 ios->timing == MMC_TIMING_MMC_HS400)
c69042a5 1435 regs |= ((0x1 << slot->id) << 16);
3f514291 1436 else
c69042a5 1437 regs &= ~((0x1 << slot->id) << 16);
3f514291
SJ		 1438
1439 mci_writel(slot->host, UHS_REG, regs);
f1d2736c 1440 slot->host->timing = ios->timing;
41babf75 1441
fdf492a1
DA		 1442 /*
1443 * Use mirror of ios->clock to prevent race with mmc
1444 * core ios update when finding the minimum.
1445 */
1446 slot->clock = ios->clock;
f95f3850 1447
cb27a843
JH		 1448 if (drv_data && drv_data->set_ios)
1449 drv_data->set_ios(slot->host, ios);
800d78bf 1450
f95f3850
WN		 1451 switch (ios->power_mode) {
1452 case MMC_POWER_UP:
51da2240
YC		 1453 if (!IS_ERR(mmc->supply.vmmc)) {
1454 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1455 ios->vdd);
1456 if (ret) {
1457 dev_err(slot->host->dev,
1458 "failed to enable vmmc regulator\n");
1459 /*return, if failed turn on vmmc*/
1460 return;
1461 }
1462 }
29d0d161
DA		 1463 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1464 regs = mci_readl(slot->host, PWREN);
1465 regs |= (1 << slot->id);
1466 mci_writel(slot->host, PWREN, regs);
1467 break;
1468 case MMC_POWER_ON:
d1f1dd86
DA		 1469 if (!slot->host->vqmmc_enabled) {
1470 if (!IS_ERR(mmc->supply.vqmmc)) {
1471 ret = regulator_enable(mmc->supply.vqmmc);
1472 if (ret < 0)
1473 dev_err(slot->host->dev,
1474 "failed to enable vqmmc\n");
1475 else
1476 slot->host->vqmmc_enabled = true;
1477
1478 } else {
1479 /* Keep track so we don't reset again */
51da2240 1480 slot->host->vqmmc_enabled = true;
d1f1dd86
DA		 1481 }
1482
1483 /* Reset our state machine after powering on */
1484 dw_mci_ctrl_reset(slot->host,
1485 SDMMC_CTRL_ALL_RESET_FLAGS);
51da2240 1486 }
655babbd
DA		 1487
1488 /* Adjust clock / bus width after power is up */
1489 dw_mci_setup_bus(slot, false);
1490
e6f34e2f
JH		 1491 break;
1492 case MMC_POWER_OFF:
655babbd
DA		 1493 /* Turn clock off before power goes down */
1494 dw_mci_setup_bus(slot, false);
1495
51da2240
YC		 1496 if (!IS_ERR(mmc->supply.vmmc))
1497 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1498
d1f1dd86 1499 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
51da2240 1500 regulator_disable(mmc->supply.vqmmc);
d1f1dd86 1501 slot->host->vqmmc_enabled = false;
51da2240 1502
4366dcc5
JC		 1503 regs = mci_readl(slot->host, PWREN);
1504 regs &= ~(1 << slot->id);
1505 mci_writel(slot->host, PWREN, regs);
f95f3850
WN		 1506 break;
1507 default:
1508 break;
1509 }
655babbd
DA		 1510
1511 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1512 slot->host->state = STATE_IDLE;
f95f3850
WN		 1513}
1514
01730558
DA		 1515static int dw_mci_card_busy(struct mmc_host *mmc)
1516{
1517 struct dw_mci_slot *slot = mmc_priv(mmc);
1518 u32 status;
1519
1520 /*
1521 * Check the busy bit which is low when DAT[3:0]
1522 * (the data lines) are 0000
1523 */
1524 status = mci_readl(slot->host, STATUS);
1525
1526 return !!(status & SDMMC_STATUS_BUSY);
1527}
1528
1529static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1530{
1531 struct dw_mci_slot *slot = mmc_priv(mmc);
1532 struct dw_mci *host = slot->host;
8f7849c4 1533 const struct dw_mci_drv_data *drv_data = host->drv_data;
01730558
DA		 1534 u32 uhs;
1535 u32 v18 = SDMMC_UHS_18V << slot->id;
01730558
DA		 1536 int ret;
1537
8f7849c4
ZG		 1538 if (drv_data && drv_data->switch_voltage)
1539 return drv_data->switch_voltage(mmc, ios);
1540
01730558
DA		 1541 /*
1542 * Program the voltage. Note that some instances of dw_mmc may use
1543 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1544 * does no harm but you need to set the regulator directly. Try both.
1545 */
1546 uhs = mci_readl(host, UHS_REG);
e0848f5d 1547 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
01730558 1548 uhs &= ~v18;
e0848f5d 1549 else
01730558 1550 uhs |= v18;
e0848f5d 1551
01730558 1552 if (!IS_ERR(mmc->supply.vqmmc)) {
e0848f5d 1553 ret = mmc_regulator_set_vqmmc(mmc, ios);
01730558
DA		 1554
1555 if (ret) {
b19caf37 1556 dev_dbg(&mmc->class_dev,
e0848f5d
DA		 1557 "Regulator set error %d - %s V\n",
1558 ret, uhs & v18 ? "1.8" : "3.3");
01730558
DA		 1559 return ret;
1560 }
1561 }
1562 mci_writel(host, UHS_REG, uhs);
1563
1564 return 0;
1565}
1566
f95f3850
WN		 1567static int dw_mci_get_ro(struct mmc_host *mmc)
1568{
1569 int read_only;
1570 struct dw_mci_slot *slot = mmc_priv(mmc);
9795a846 1571 int gpio_ro = mmc_gpio_get_ro(mmc);
f95f3850
WN		 1572
1573 /* Use platform get_ro function, else try on board write protect */
287980e4 1574 if (gpio_ro >= 0)
9795a846 1575 read_only = gpio_ro;
f95f3850
WN		 1576 else
1577 read_only =
1578 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1579
1580 dev_dbg(&mmc->class_dev, "card is %s\n",
1581 read_only ? "read-only" : "read-write");
1582
1583 return read_only;
1584}
1585
935a665e
SL		 1586static void dw_mci_hw_reset(struct mmc_host *mmc)
1587{
1588 struct dw_mci_slot *slot = mmc_priv(mmc);
1589 struct dw_mci *host = slot->host;
1590 int reset;
1591
1592 if (host->use_dma == TRANS_MODE_IDMAC)
1593 dw_mci_idmac_reset(host);
1594
1595 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1596 SDMMC_CTRL_FIFO_RESET))
1597 return;
1598
1599 /*
1600 * According to eMMC spec, card reset procedure:
1601 * tRstW >= 1us: RST_n pulse width
1602 * tRSCA >= 200us: RST_n to Command time
1603 * tRSTH >= 1us: RST_n high period
1604 */
1605 reset = mci_readl(host, RST_N);
1606 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1607 mci_writel(host, RST_N, reset);
1608 usleep_range(1, 2);
1609 reset |= SDMMC_RST_HWACTIVE << slot->id;
1610 mci_writel(host, RST_N, reset);
1611 usleep_range(200, 300);
1612}
1613
b24c8b26 1614static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
9623b5b9 1615{
b24c8b26 1616 struct dw_mci_slot *slot = mmc_priv(mmc);
9623b5b9 1617 struct dw_mci *host = slot->host;
9623b5b9 1618
b24c8b26
DA		 1619 /*
1620 * Low power mode will stop the card clock when idle. According to the
1621 * description of the CLKENA register we should disable low power mode
1622 * for SDIO cards if we need SDIO interrupts to work.
1623 */
1624 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1625 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1626 u32 clk_en_a_old;
1627 u32 clk_en_a;
9623b5b9 1628
b24c8b26
DA		 1629 clk_en_a_old = mci_readl(host, CLKENA);
1630
1631 if (card->type == MMC_TYPE_SDIO ||
1632 card->type == MMC_TYPE_SD_COMBO) {
a6db2c86
DA		 1633 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) {
1634 pm_runtime_get_noresume(mmc->parent);
1635 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1636 }
b24c8b26
DA		 1637 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1638 } else {
a6db2c86
DA		 1639 if (test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) {
1640 pm_runtime_put_noidle(mmc->parent);
1641 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1642 }
b24c8b26
DA		 1643 clk_en_a = clk_en_a_old | clken_low_pwr;
1644 }
1645
1646 if (clk_en_a != clk_en_a_old) {
1647 mci_writel(host, CLKENA, clk_en_a);
1648 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1649 SDMMC_CMD_PRV_DAT_WAIT, 0);
1650 }
9623b5b9
DA		 1651 }
1652}
1653
1a5c8e1f
SH		 1654static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1655{
1656 struct dw_mci_slot *slot = mmc_priv(mmc);
1657 struct dw_mci *host = slot->host;
f8c58c11 1658 unsigned long irqflags;
1a5c8e1f
SH		 1659 u32 int_mask;
1660
f8c58c11
DA		 1661 spin_lock_irqsave(&host->irq_lock, irqflags);
1662
1a5c8e1f
SH		 1663 /* Enable/disable Slot Specific SDIO interrupt */
1664 int_mask = mci_readl(host, INTMASK);
b24c8b26
DA		 1665 if (enb)
1666 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1667 else
1668 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1669 mci_writel(host, INTMASK, int_mask);
f8c58c11
DA		 1670
1671 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1a5c8e1f
SH		 1672}
1673
0976f16d
SJ		 1674static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1675{
1676 struct dw_mci_slot *slot = mmc_priv(mmc);
1677 struct dw_mci *host = slot->host;
1678 const struct dw_mci_drv_data *drv_data = host->drv_data;
0e3a22c0 1679 int err = -EINVAL;
0976f16d 1680
0976f16d 1681 if (drv_data && drv_data->execute_tuning)
9979dbe5 1682 err = drv_data->execute_tuning(slot, opcode);
0976f16d
SJ		 1683 return err;
1684}
1685
0e3a22c0
SL		 1686static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1687 struct mmc_ios *ios)
80113132
SJ		 1688{
1689 struct dw_mci_slot *slot = mmc_priv(mmc);
1690 struct dw_mci *host = slot->host;
1691 const struct dw_mci_drv_data *drv_data = host->drv_data;
1692
1693 if (drv_data && drv_data->prepare_hs400_tuning)
1694 return drv_data->prepare_hs400_tuning(host, ios);
1695
1696 return 0;
1697}
1698
4e7392b2
SL		 1699static bool dw_mci_reset(struct dw_mci *host)
1700{
1701 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1702 bool ret = false;
1703
1704 /*
1705 * Resetting generates a block interrupt, hence setting
1706 * the scatter-gather pointer to NULL.
1707 */
1708 if (host->sg) {
1709 sg_miter_stop(&host->sg_miter);
1710 host->sg = NULL;
1711 }
1712
1713 if (host->use_dma)
1714 flags |= SDMMC_CTRL_DMA_RESET;
1715
1716 if (dw_mci_ctrl_reset(host, flags)) {
1717 /*
1718 * In all cases we clear the RAWINTS register to clear any
1719 * interrupts.
1720 */
1721 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1722
1723 /* if using dma we wait for dma_req to clear */
1724 if (host->use_dma) {
1725 u32 status;
1726
1727 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1728 status,
1729 !(status & SDMMC_STATUS_DMA_REQ),
1730 1, 500 * USEC_PER_MSEC)) {
1731 dev_err(host->dev,
1732 "%s: Timeout waiting for dma_req to clear during reset\n",
1733 __func__);
1734 goto ciu_out;
1735 }
1736
1737 /* when using DMA next we reset the fifo again */
1738 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1739 goto ciu_out;
1740 }
1741 } else {
1742 /* if the controller reset bit did clear, then set clock regs */
1743 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1744 dev_err(host->dev,
1745 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1746 __func__);
1747 goto ciu_out;
1748 }
1749 }
1750
1751 if (host->use_dma == TRANS_MODE_IDMAC)
1752 /* It is also recommended that we reset and reprogram idmac */
1753 dw_mci_idmac_reset(host);
1754
1755 ret = true;
1756
1757ciu_out:
1758 /* After a CTRL reset we need to have CIU set clock registers */
1759 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
1760
1761 return ret;
1762}
1763
f95f3850 1764static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 1765 .request = dw_mci_request,
9aa51408
SJ		 1766 .pre_req = dw_mci_pre_req,
1767 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 1768 .set_ios = dw_mci_set_ios,
1769 .get_ro = dw_mci_get_ro,
1770 .get_cd = dw_mci_get_cd,
935a665e 1771 .hw_reset = dw_mci_hw_reset,
1a5c8e1f 1772 .enable_sdio_irq = dw_mci_enable_sdio_irq,
0976f16d 1773 .execute_tuning = dw_mci_execute_tuning,
01730558
DA		 1774 .card_busy = dw_mci_card_busy,
1775 .start_signal_voltage_switch = dw_mci_switch_voltage,
b24c8b26 1776 .init_card = dw_mci_init_card,
80113132 1777 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
f95f3850
WN		 1778};
1779
1780static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1781 __releases(&host->lock)
1782 __acquires(&host->lock)
1783{
1784 struct dw_mci_slot *slot;
1785 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1786
1787 WARN_ON(host->cmd || host->data);
1788
1789 host->cur_slot->mrq = NULL;
1790 host->mrq = NULL;
1791 if (!list_empty(&host->queue)) {
1792 slot = list_entry(host->queue.next,
1793 struct dw_mci_slot, queue_node);
1794 list_del(&slot->queue_node);
4a90920c 1795 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 1796 mmc_hostname(slot->mmc));
1797 host->state = STATE_SENDING_CMD;
1798 dw_mci_start_request(host, slot);
1799 } else {
4a90920c 1800 dev_vdbg(host->dev, "list empty\n");
01730558
DA		 1801
1802 if (host->state == STATE_SENDING_CMD11)
1803 host->state = STATE_WAITING_CMD11_DONE;
1804 else
1805 host->state = STATE_IDLE;
f95f3850
WN		 1806 }
1807
1808 spin_unlock(&host->lock);
1809 mmc_request_done(prev_mmc, mrq);
1810 spin_lock(&host->lock);
1811}
1812
e352c813 1813static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
f95f3850
WN		 1814{
1815 u32 status = host->cmd_status;
1816
1817 host->cmd_status = 0;
1818
1819 /* Read the response from the card (up to 16 bytes) */
1820 if (cmd->flags & MMC_RSP_PRESENT) {
1821 if (cmd->flags & MMC_RSP_136) {
1822 cmd->resp[3] = mci_readl(host, RESP0);
1823 cmd->resp[2] = mci_readl(host, RESP1);
1824 cmd->resp[1] = mci_readl(host, RESP2);
1825 cmd->resp[0] = mci_readl(host, RESP3);
1826 } else {
1827 cmd->resp[0] = mci_readl(host, RESP0);
1828 cmd->resp[1] = 0;
1829 cmd->resp[2] = 0;
1830 cmd->resp[3] = 0;
1831 }
1832 }
1833
1834 if (status & SDMMC_INT_RTO)
1835 cmd->error = -ETIMEDOUT;
1836 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1837 cmd->error = -EILSEQ;
1838 else if (status & SDMMC_INT_RESP_ERR)
1839 cmd->error = -EIO;
1840 else
1841 cmd->error = 0;
1842
e352c813
SJ		 1843 return cmd->error;
1844}
1845
1846static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1847{
31bff450 1848 u32 status = host->data_status;
e352c813
SJ		 1849
1850 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1851 if (status & SDMMC_INT_DRTO) {
1852 data->error = -ETIMEDOUT;
1853 } else if (status & SDMMC_INT_DCRC) {
1854 data->error = -EILSEQ;
1855 } else if (status & SDMMC_INT_EBE) {
1856 if (host->dir_status ==
1857 DW_MCI_SEND_STATUS) {
1858 /*
1859 * No data CRC status was returned.
1860 * The number of bytes transferred
1861 * will be exaggerated in PIO mode.
1862 */
1863 data->bytes_xfered = 0;
1864 data->error = -ETIMEDOUT;
1865 } else if (host->dir_status ==
1866 DW_MCI_RECV_STATUS) {
e7a1dec1 1867 data->error = -EILSEQ;
e352c813
SJ		 1868 }
1869 } else {
1870 /* SDMMC_INT_SBE is included */
e7a1dec1 1871 data->error = -EILSEQ;
e352c813
SJ		 1872 }
1873
e6cc0123 1874 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
e352c813
SJ		 1875
1876 /*
1877 * After an error, there may be data lingering
31bff450 1878 * in the FIFO
e352c813 1879 */
3a33a94c 1880 dw_mci_reset(host);
e352c813
SJ		 1881 } else {
1882 data->bytes_xfered = data->blocks * data->blksz;
1883 data->error = 0;
1884 }
1885
1886 return data->error;
f95f3850
WN		 1887}
1888
57e10486
AK		 1889static void dw_mci_set_drto(struct dw_mci *host)
1890{
1891 unsigned int drto_clks;
1892 unsigned int drto_ms;
1893
1894 drto_clks = mci_readl(host, TMOUT) >> 8;
1895 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1896
1897 /* add a bit spare time */
1898 drto_ms += 10;
1899
1900 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1901}
1902
f95f3850
WN		 1903static void dw_mci_tasklet_func(unsigned long priv)
1904{
1905 struct dw_mci *host = (struct dw_mci *)priv;
1906 struct mmc_data *data;
1907 struct mmc_command *cmd;
e352c813 1908 struct mmc_request *mrq;
f95f3850
WN		 1909 enum dw_mci_state state;
1910 enum dw_mci_state prev_state;
e352c813 1911 unsigned int err;
f95f3850
WN		 1912
1913 spin_lock(&host->lock);
1914
1915 state = host->state;
1916 data = host->data;
e352c813 1917 mrq = host->mrq;
f95f3850
WN		 1918
1919 do {
1920 prev_state = state;
1921
1922 switch (state) {
1923 case STATE_IDLE:
01730558 1924 case STATE_WAITING_CMD11_DONE:
f95f3850
WN		 1925 break;
1926
01730558 1927 case STATE_SENDING_CMD11:
f95f3850
WN		 1928 case STATE_SENDING_CMD:
1929 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1930 &host->pending_events))
1931 break;
1932
1933 cmd = host->cmd;
1934 host->cmd = NULL;
1935 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
e352c813
SJ		 1936 err = dw_mci_command_complete(host, cmd);
1937 if (cmd == mrq->sbc && !err) {
053b3ce6
SJ		 1938 prev_state = state = STATE_SENDING_CMD;
1939 __dw_mci_start_request(host, host->cur_slot,
e352c813 1940 mrq->cmd);
053b3ce6
SJ		 1941 goto unlock;
1942 }
1943
e352c813 1944 if (cmd->data && err) {
46d17952
DA		 1945 /*
1946 * During UHS tuning sequence, sending the stop
1947 * command after the response CRC error would
1948 * throw the system into a confused state
1949 * causing all future tuning phases to report
1950 * failure.
1951 *
1952 * In such case controller will move into a data
1953 * transfer state after a response error or
1954 * response CRC error. Let's let that finish
1955 * before trying to send a stop, so we'll go to
1956 * STATE_SENDING_DATA.
1957 *
1958 * Although letting the data transfer take place
1959 * will waste a bit of time (we already know
1960 * the command was bad), it can't cause any
1961 * errors since it's possible it would have
1962 * taken place anyway if this tasklet got
1963 * delayed. Allowing the transfer to take place
1964 * avoids races and keeps things simple.
1965 */
1966 if ((err != -ETIMEDOUT) &&
1967 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1968 state = STATE_SENDING_DATA;
1969 continue;
1970 }
1971
71abb133 1972 dw_mci_stop_dma(host);
90c2143a
SJ		 1973 send_stop_abort(host, data);
1974 state = STATE_SENDING_STOP;
1975 break;
71abb133
SJ		 1976 }
1977
e352c813
SJ		 1978 if (!cmd->data || err) {
1979 dw_mci_request_end(host, mrq);
f95f3850
WN		 1980 goto unlock;
1981 }
1982
1983 prev_state = state = STATE_SENDING_DATA;
1984 /* fall through */
1985
1986 case STATE_SENDING_DATA:
2aa35465
DA		 1987 /*
1988 * We could get a data error and never a transfer
1989 * complete so we'd better check for it here.
1990 *
1991 * Note that we don't really care if we also got a
1992 * transfer complete; stopping the DMA and sending an
1993 * abort won't hurt.
1994 */
f95f3850
WN		 1995 if (test_and_clear_bit(EVENT_DATA_ERROR,
1996 &host->pending_events)) {
1997 dw_mci_stop_dma(host);
e13c3c08 1998 if (!(host->data_status & (SDMMC_INT_DRTO |
bdb9a90b 1999 SDMMC_INT_EBE)))
2000 send_stop_abort(host, data);
f95f3850
WN		 2001 state = STATE_DATA_ERROR;
2002 break;
2003 }
2004
2005 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
57e10486
AK		 2006 &host->pending_events)) {
2007 /*
2008 * If all data-related interrupts don't come
2009 * within the given time in reading data state.
2010 */
16a34574 2011 if (host->dir_status == DW_MCI_RECV_STATUS)
57e10486 2012 dw_mci_set_drto(host);
f95f3850 2013 break;
57e10486 2014 }
f95f3850
WN		 2015
2016 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2aa35465
DA		 2017
2018 /*
2019 * Handle an EVENT_DATA_ERROR that might have shown up
2020 * before the transfer completed. This might not have
2021 * been caught by the check above because the interrupt
2022 * could have gone off between the previous check and
2023 * the check for transfer complete.
2024 *
2025 * Technically this ought not be needed assuming we
2026 * get a DATA_COMPLETE eventually (we'll notice the
2027 * error and end the request), but it shouldn't hurt.
2028 *
2029 * This has the advantage of sending the stop command.
2030 */
2031 if (test_and_clear_bit(EVENT_DATA_ERROR,
2032 &host->pending_events)) {
2033 dw_mci_stop_dma(host);
e13c3c08 2034 if (!(host->data_status & (SDMMC_INT_DRTO |
bdb9a90b 2035 SDMMC_INT_EBE)))
2036 send_stop_abort(host, data);
2aa35465
DA		 2037 state = STATE_DATA_ERROR;
2038 break;
2039 }
f95f3850 2040 prev_state = state = STATE_DATA_BUSY;
2aa35465 2041
f95f3850
WN		 2042 /* fall through */
2043
2044 case STATE_DATA_BUSY:
2045 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
57e10486
AK		 2046 &host->pending_events)) {
2047 /*
2048 * If data error interrupt comes but data over
2049 * interrupt doesn't come within the given time.
2050 * in reading data state.
2051 */
16a34574 2052 if (host->dir_status == DW_MCI_RECV_STATUS)
57e10486 2053 dw_mci_set_drto(host);
f95f3850 2054 break;
57e10486 2055 }
f95f3850
WN		 2056
2057 host->data = NULL;
2058 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
e352c813
SJ		 2059 err = dw_mci_data_complete(host, data);
2060
2061 if (!err) {
2062 if (!data->stop || mrq->sbc) {
17c8bc85 2063 if (mrq->sbc && data->stop)
e352c813
SJ		 2064 data->stop->error = 0;
2065 dw_mci_request_end(host, mrq);
2066 goto unlock;
f95f3850 2067 }
f95f3850 2068
e352c813
SJ		 2069 /* stop command for open-ended transfer*/
2070 if (data->stop)
2071 send_stop_abort(host, data);
2aa35465
DA		 2072 } else {
2073 /*
2074 * If we don't have a command complete now we'll
2075 * never get one since we just reset everything;
2076 * better end the request.
2077 *
2078 * If we do have a command complete we'll fall
2079 * through to the SENDING_STOP command and
2080 * everything will be peachy keen.
2081 */
2082 if (!test_bit(EVENT_CMD_COMPLETE,
2083 &host->pending_events)) {
2084 host->cmd = NULL;
2085 dw_mci_request_end(host, mrq);
2086 goto unlock;
2087 }
053b3ce6
SJ		 2088 }
2089
e352c813
SJ		 2090 /*
2091 * If err has non-zero,
2092 * stop-abort command has been already issued.
2093 */
f95f3850 2094 prev_state = state = STATE_SENDING_STOP;
e352c813 2095
f95f3850
WN		 2096 /* fall through */
2097
2098 case STATE_SENDING_STOP:
2099 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2100 &host->pending_events))
2101 break;
2102
71abb133 2103 /* CMD error in data command */
31bff450 2104 if (mrq->cmd->error && mrq->data)
3a33a94c 2105 dw_mci_reset(host);
71abb133 2106
f95f3850 2107 host->cmd = NULL;
71abb133 2108 host->data = NULL;
90c2143a 2109
e13c3c08 2110 if (!mrq->sbc && mrq->stop)
e352c813 2111 dw_mci_command_complete(host, mrq->stop);
90c2143a
SJ		 2112 else
2113 host->cmd_status = 0;
2114
e352c813 2115 dw_mci_request_end(host, mrq);
f95f3850
WN		 2116 goto unlock;
2117
2118 case STATE_DATA_ERROR:
2119 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2120 &host->pending_events))
2121 break;
2122
2123 state = STATE_DATA_BUSY;
2124 break;
2125 }
2126 } while (state != prev_state);
2127
2128 host->state = state;
2129unlock:
2130 spin_unlock(&host->lock);
2131
2132}
2133
34b664a2
JH		 2134/* push final bytes to part_buf, only use during push */
2135static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 2136{
34b664a2
JH		 2137 memcpy((void *)&host->part_buf, buf, cnt);
2138 host->part_buf_count = cnt;
2139}
f95f3850 2140
34b664a2
JH		 2141/* append bytes to part_buf, only use during push */
2142static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2143{
2144 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2145 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2146 host->part_buf_count += cnt;
2147 return cnt;
2148}
f95f3850 2149
34b664a2
JH		 2150/* pull first bytes from part_buf, only use during pull */
2151static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2152{
0e3a22c0 2153 cnt = min_t(int, cnt, host->part_buf_count);
34b664a2
JH		 2154 if (cnt) {
2155 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2156 cnt);
2157 host->part_buf_count -= cnt;
2158 host->part_buf_start += cnt;
f95f3850 2159 }
34b664a2 2160 return cnt;
f95f3850
WN		 2161}
2162
34b664a2
JH		 2163/* pull final bytes from the part_buf, assuming it's just been filled */
2164static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 2165{
34b664a2
JH		 2166 memcpy(buf, &host->part_buf, cnt);
2167 host->part_buf_start = cnt;
2168 host->part_buf_count = (1 << host->data_shift) - cnt;
2169}
f95f3850 2170
34b664a2
JH		 2171static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2172{
cfbeb59c
MC		 2173 struct mmc_data *data = host->data;
2174 int init_cnt = cnt;
2175
34b664a2
JH		 2176 /* try and push anything in the part_buf */
2177 if (unlikely(host->part_buf_count)) {
2178 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2179
34b664a2
JH		 2180 buf += len;
2181 cnt -= len;
cfbeb59c 2182 if (host->part_buf_count == 2) {
76184ac1 2183 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 2184 host->part_buf_count = 0;
2185 }
2186 }
2187#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2188 if (unlikely((unsigned long)buf & 0x1)) {
2189 while (cnt >= 2) {
2190 u16 aligned_buf[64];
2191 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2192 int items = len >> 1;
2193 int i;
2194 /* memcpy from input buffer into aligned buffer */
2195 memcpy(aligned_buf, buf, len);
2196 buf += len;
2197 cnt -= len;
2198 /* push data from aligned buffer into fifo */
2199 for (i = 0; i < items; ++i)
76184ac1 2200 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2201 }
2202 } else
2203#endif
2204 {
2205 u16 *pdata = buf;
0e3a22c0 2206
34b664a2 2207 for (; cnt >= 2; cnt -= 2)
76184ac1 2208 mci_fifo_writew(host->fifo_reg, *pdata++);
34b664a2
JH		 2209 buf = pdata;
2210 }
2211 /* put anything remaining in the part_buf */
2212 if (cnt) {
2213 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2214 /* Push data if we have reached the expected data length */
2215 if ((data->bytes_xfered + init_cnt) ==
2216 (data->blksz * data->blocks))
76184ac1 2217 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 2218 }
2219}
f95f3850 2220
34b664a2
JH		 2221static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2222{
2223#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2224 if (unlikely((unsigned long)buf & 0x1)) {
2225 while (cnt >= 2) {
2226 /* pull data from fifo into aligned buffer */
2227 u16 aligned_buf[64];
2228 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2229 int items = len >> 1;
2230 int i;
0e3a22c0 2231
34b664a2 2232 for (i = 0; i < items; ++i)
76184ac1 2233 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2234 /* memcpy from aligned buffer into output buffer */
2235 memcpy(buf, aligned_buf, len);
2236 buf += len;
2237 cnt -= len;
2238 }
2239 } else
2240#endif
2241 {
2242 u16 *pdata = buf;
0e3a22c0 2243
34b664a2 2244 for (; cnt >= 2; cnt -= 2)
76184ac1 2245 *pdata++ = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2246 buf = pdata;
2247 }
2248 if (cnt) {
76184ac1 2249 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
34b664a2 2250 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2251 }
2252}
2253
2254static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2255{
cfbeb59c
MC		 2256 struct mmc_data *data = host->data;
2257 int init_cnt = cnt;
2258
34b664a2
JH		 2259 /* try and push anything in the part_buf */
2260 if (unlikely(host->part_buf_count)) {
2261 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2262
34b664a2
JH		 2263 buf += len;
2264 cnt -= len;
cfbeb59c 2265 if (host->part_buf_count == 4) {
76184ac1 2266 mci_fifo_writel(host->fifo_reg, host->part_buf32);
34b664a2
JH		 2267 host->part_buf_count = 0;
2268 }
2269 }
2270#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2271 if (unlikely((unsigned long)buf & 0x3)) {
2272 while (cnt >= 4) {
2273 u32 aligned_buf[32];
2274 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2275 int items = len >> 2;
2276 int i;
2277 /* memcpy from input buffer into aligned buffer */
2278 memcpy(aligned_buf, buf, len);
2279 buf += len;
2280 cnt -= len;
2281 /* push data from aligned buffer into fifo */
2282 for (i = 0; i < items; ++i)
76184ac1 2283 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2284 }
2285 } else
2286#endif
2287 {
2288 u32 *pdata = buf;
0e3a22c0 2289
34b664a2 2290 for (; cnt >= 4; cnt -= 4)
76184ac1 2291 mci_fifo_writel(host->fifo_reg, *pdata++);
34b664a2
JH		 2292 buf = pdata;
2293 }
2294 /* put anything remaining in the part_buf */
2295 if (cnt) {
2296 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2297 /* Push data if we have reached the expected data length */
2298 if ((data->bytes_xfered + init_cnt) ==
2299 (data->blksz * data->blocks))
76184ac1 2300 mci_fifo_writel(host->fifo_reg, host->part_buf32);
f95f3850
WN		 2301 }
2302}
2303
2304static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2305{
34b664a2
JH		 2306#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2307 if (unlikely((unsigned long)buf & 0x3)) {
2308 while (cnt >= 4) {
2309 /* pull data from fifo into aligned buffer */
2310 u32 aligned_buf[32];
2311 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2312 int items = len >> 2;
2313 int i;
0e3a22c0 2314
34b664a2 2315 for (i = 0; i < items; ++i)
76184ac1 2316 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2317 /* memcpy from aligned buffer into output buffer */
2318 memcpy(buf, aligned_buf, len);
2319 buf += len;
2320 cnt -= len;
2321 }
2322 } else
2323#endif
2324 {
2325 u32 *pdata = buf;
0e3a22c0 2326
34b664a2 2327 for (; cnt >= 4; cnt -= 4)
76184ac1 2328 *pdata++ = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2329 buf = pdata;
2330 }
2331 if (cnt) {
76184ac1 2332 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
34b664a2 2333 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2334 }
2335}
2336
2337static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2338{
cfbeb59c
MC		 2339 struct mmc_data *data = host->data;
2340 int init_cnt = cnt;
2341
34b664a2
JH		 2342 /* try and push anything in the part_buf */
2343 if (unlikely(host->part_buf_count)) {
2344 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2345
34b664a2
JH		 2346 buf += len;
2347 cnt -= len;
c09fbd74 2348
cfbeb59c 2349 if (host->part_buf_count == 8) {
76184ac1 2350 mci_fifo_writeq(host->fifo_reg, host->part_buf);
34b664a2
JH		 2351 host->part_buf_count = 0;
2352 }
2353 }
2354#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2355 if (unlikely((unsigned long)buf & 0x7)) {
2356 while (cnt >= 8) {
2357 u64 aligned_buf[16];
2358 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2359 int items = len >> 3;
2360 int i;
2361 /* memcpy from input buffer into aligned buffer */
2362 memcpy(aligned_buf, buf, len);
2363 buf += len;
2364 cnt -= len;
2365 /* push data from aligned buffer into fifo */
2366 for (i = 0; i < items; ++i)
76184ac1 2367 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2368 }
2369 } else
2370#endif
2371 {
2372 u64 *pdata = buf;
0e3a22c0 2373
34b664a2 2374 for (; cnt >= 8; cnt -= 8)
76184ac1 2375 mci_fifo_writeq(host->fifo_reg, *pdata++);
34b664a2
JH		 2376 buf = pdata;
2377 }
2378 /* put anything remaining in the part_buf */
2379 if (cnt) {
2380 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2381 /* Push data if we have reached the expected data length */
2382 if ((data->bytes_xfered + init_cnt) ==
2383 (data->blksz * data->blocks))
76184ac1 2384 mci_fifo_writeq(host->fifo_reg, host->part_buf);
f95f3850
WN		 2385 }
2386}
2387
2388static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2389{
34b664a2
JH		 2390#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2391 if (unlikely((unsigned long)buf & 0x7)) {
2392 while (cnt >= 8) {
2393 /* pull data from fifo into aligned buffer */
2394 u64 aligned_buf[16];
2395 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2396 int items = len >> 3;
2397 int i;
0e3a22c0 2398
34b664a2 2399 for (i = 0; i < items; ++i)
76184ac1
BD		 2400 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2401
34b664a2
JH		 2402 /* memcpy from aligned buffer into output buffer */
2403 memcpy(buf, aligned_buf, len);
2404 buf += len;
2405 cnt -= len;
2406 }
2407 } else
2408#endif
2409 {
2410 u64 *pdata = buf;
0e3a22c0 2411
34b664a2 2412 for (; cnt >= 8; cnt -= 8)
76184ac1 2413 *pdata++ = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2414 buf = pdata;
2415 }
2416 if (cnt) {
76184ac1 2417 host->part_buf = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2418 dw_mci_pull_final_bytes(host, buf, cnt);
2419 }
2420}
f95f3850 2421
34b664a2
JH		 2422static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2423{
2424 int len;
f95f3850 2425
34b664a2
JH		 2426 /* get remaining partial bytes */
2427 len = dw_mci_pull_part_bytes(host, buf, cnt);
2428 if (unlikely(len == cnt))
2429 return;
2430 buf += len;
2431 cnt -= len;
2432
2433 /* get the rest of the data */
2434 host->pull_data(host, buf, cnt);
f95f3850
WN		 2435}
2436
87a74d39 2437static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
f95f3850 2438{
f9c2a0dc
SJ		 2439 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2440 void *buf;
2441 unsigned int offset;
f95f3850
WN		 2442 struct mmc_data *data = host->data;
2443 int shift = host->data_shift;
2444 u32 status;
3e4b0d8b 2445 unsigned int len;
f9c2a0dc 2446 unsigned int remain, fcnt;
f95f3850
WN		 2447
2448 do {
f9c2a0dc
SJ		 2449 if (!sg_miter_next(sg_miter))
2450 goto done;
2451
4225fc85 2452 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2453 buf = sg_miter->addr;
2454 remain = sg_miter->length;
2455 offset = 0;
2456
2457 do {
2458 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2459 << shift) + host->part_buf_count;
2460 len = min(remain, fcnt);
2461 if (!len)
2462 break;
34b664a2 2463 dw_mci_pull_data(host, (void *)(buf + offset), len);
3e4b0d8b 2464 data->bytes_xfered += len;
f95f3850 2465 offset += len;
f9c2a0dc
SJ		 2466 remain -= len;
2467 } while (remain);
f95f3850 2468
e74f3a9c 2469 sg_miter->consumed = offset;
f95f3850
WN		 2470 status = mci_readl(host, MINTSTS);
2471 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
87a74d39
KK		 2472 /* if the RXDR is ready read again */
2473 } while ((status & SDMMC_INT_RXDR) ||
2474 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
f9c2a0dc
SJ		 2475
2476 if (!remain) {
2477 if (!sg_miter_next(sg_miter))
2478 goto done;
2479 sg_miter->consumed = 0;
2480 }
2481 sg_miter_stop(sg_miter);
f95f3850
WN		 2482 return;
2483
2484done:
f9c2a0dc
SJ		 2485 sg_miter_stop(sg_miter);
2486 host->sg = NULL;
0e3a22c0 2487 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2488 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2489}
2490
2491static void dw_mci_write_data_pio(struct dw_mci *host)
2492{
f9c2a0dc
SJ		 2493 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2494 void *buf;
2495 unsigned int offset;
f95f3850
WN		 2496 struct mmc_data *data = host->data;
2497 int shift = host->data_shift;
2498 u32 status;
3e4b0d8b 2499 unsigned int len;
f9c2a0dc
SJ		 2500 unsigned int fifo_depth = host->fifo_depth;
2501 unsigned int remain, fcnt;
f95f3850
WN		 2502
2503 do {
f9c2a0dc
SJ		 2504 if (!sg_miter_next(sg_miter))
2505 goto done;
2506
4225fc85 2507 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2508 buf = sg_miter->addr;
2509 remain = sg_miter->length;
2510 offset = 0;
2511
2512 do {
2513 fcnt = ((fifo_depth -
2514 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2515 << shift) - host->part_buf_count;
2516 len = min(remain, fcnt);
2517 if (!len)
2518 break;
f95f3850 2519 host->push_data(host, (void *)(buf + offset), len);
3e4b0d8b 2520 data->bytes_xfered += len;
f95f3850 2521 offset += len;
f9c2a0dc
SJ		 2522 remain -= len;
2523 } while (remain);
f95f3850 2524
e74f3a9c 2525 sg_miter->consumed = offset;
f95f3850
WN		 2526 status = mci_readl(host, MINTSTS);
2527 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 2528 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f9c2a0dc
SJ		 2529
2530 if (!remain) {
2531 if (!sg_miter_next(sg_miter))
2532 goto done;
2533 sg_miter->consumed = 0;
2534 }
2535 sg_miter_stop(sg_miter);
f95f3850
WN		 2536 return;
2537
2538done:
f9c2a0dc
SJ		 2539 sg_miter_stop(sg_miter);
2540 host->sg = NULL;
0e3a22c0 2541 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2542 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2543}
2544
2545static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2546{
2547 if (!host->cmd_status)
2548 host->cmd_status = status;
2549
0e3a22c0 2550 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2551
2552 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2553 tasklet_schedule(&host->tasklet);
2554}
2555
6130e7a9
DA		 2556static void dw_mci_handle_cd(struct dw_mci *host)
2557{
2558 int i;
2559
2560 for (i = 0; i < host->num_slots; i++) {
2561 struct dw_mci_slot *slot = host->slot[i];
2562
2563 if (!slot)
2564 continue;
2565
2566 if (slot->mmc->ops->card_event)
2567 slot->mmc->ops->card_event(slot->mmc);
2568 mmc_detect_change(slot->mmc,
2569 msecs_to_jiffies(host->pdata->detect_delay_ms));
2570 }
2571}
2572
f95f3850
WN		 2573static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2574{
2575 struct dw_mci *host = dev_id;
182c9081 2576 u32 pending;
1a5c8e1f 2577 int i;
f95f3850 2578
1fb5f68a
MC		 2579 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2580
476d79f1 2581 if (pending) {
01730558
DA		 2582 /* Check volt switch first, since it can look like an error */
2583 if ((host->state == STATE_SENDING_CMD11) &&
2584 (pending & SDMMC_INT_VOLT_SWITCH)) {
49ba0302 2585 unsigned long irqflags;
5c935165 2586
01730558
DA		 2587 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2588 pending &= ~SDMMC_INT_VOLT_SWITCH;
49ba0302
DA		 2589
2590 /*
2591 * Hold the lock; we know cmd11_timer can't be kicked
2592 * off after the lock is released, so safe to delete.
2593 */
2594 spin_lock_irqsave(&host->irq_lock, irqflags);
01730558 2595 dw_mci_cmd_interrupt(host, pending);
49ba0302
DA		 2596 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2597
2598 del_timer(&host->cmd11_timer);
01730558
DA		 2599 }
2600
f95f3850
WN		 2601 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2602 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 2603 host->cmd_status = pending;
0e3a22c0 2604 smp_wmb(); /* drain writebuffer */
f95f3850 2605 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 2606 }
2607
2608 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2609 /* if there is an error report DATA_ERROR */
2610 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 2611 host->data_status = pending;
0e3a22c0 2612 smp_wmb(); /* drain writebuffer */
f95f3850 2613 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 2614 tasklet_schedule(&host->tasklet);
f95f3850
WN		 2615 }
2616
2617 if (pending & SDMMC_INT_DATA_OVER) {
16a34574 2618 del_timer(&host->dto_timer);
57e10486 2619
f95f3850
WN		 2620 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2621 if (!host->data_status)
182c9081 2622 host->data_status = pending;
0e3a22c0 2623 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2624 if (host->dir_status == DW_MCI_RECV_STATUS) {
2625 if (host->sg != NULL)
87a74d39 2626 dw_mci_read_data_pio(host, true);
f95f3850
WN		 2627 }
2628 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2629 tasklet_schedule(&host->tasklet);
2630 }
2631
2632 if (pending & SDMMC_INT_RXDR) {
2633 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 2634 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
87a74d39 2635 dw_mci_read_data_pio(host, false);
f95f3850
WN		 2636 }
2637
2638 if (pending & SDMMC_INT_TXDR) {
2639 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 2640 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 2641 dw_mci_write_data_pio(host);
2642 }
2643
2644 if (pending & SDMMC_INT_CMD_DONE) {
2645 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 2646 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 2647 }
2648
2649 if (pending & SDMMC_INT_CD) {
2650 mci_writel(host, RINTSTS, SDMMC_INT_CD);
6130e7a9 2651 dw_mci_handle_cd(host);
f95f3850
WN		 2652 }
2653
1a5c8e1f
SH		 2654 /* Handle SDIO Interrupts */
2655 for (i = 0; i < host->num_slots; i++) {
2656 struct dw_mci_slot *slot = host->slot[i];
ed2540ef
DA		 2657
2658 if (!slot)
2659 continue;
2660
76756234
AK		 2661 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2662 mci_writel(host, RINTSTS,
2663 SDMMC_INT_SDIO(slot->sdio_id));
1a5c8e1f
SH		 2664 mmc_signal_sdio_irq(slot->mmc);
2665 }
2666 }
2667
1fb5f68a 2668 }
f95f3850 2669
3fc7eaef
SL		 2670 if (host->use_dma != TRANS_MODE_IDMAC)
2671 return IRQ_HANDLED;
2672
2673 /* Handle IDMA interrupts */
69d99fdc
PT		 2674 if (host->dma_64bit_address == 1) {
2675 pending = mci_readl(host, IDSTS64);
2676 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2677 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2678 SDMMC_IDMAC_INT_RI);
2679 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
faecf411
SL		 2680 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2681 host->dma_ops->complete((void *)host);
69d99fdc
PT		 2682 }
2683 } else {
2684 pending = mci_readl(host, IDSTS);
2685 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2686 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2687 SDMMC_IDMAC_INT_RI);
2688 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
faecf411
SL		 2689 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2690 host->dma_ops->complete((void *)host);
69d99fdc 2691 }
f95f3850 2692 }
f95f3850
WN		 2693
2694 return IRQ_HANDLED;
2695}
2696
36c179a9 2697static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 2698{
2699 struct mmc_host *mmc;
2700 struct dw_mci_slot *slot;
e95baf13 2701 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2702 int ctrl_id, ret;
1f44a2a5 2703 u32 freq[2];
f95f3850 2704
4a90920c 2705 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 2706 if (!mmc)
2707 return -ENOMEM;
2708
2709 slot = mmc_priv(mmc);
2710 slot->id = id;
76756234 2711 slot->sdio_id = host->sdio_id0 + id;
f95f3850
WN		 2712 slot->mmc = mmc;
2713 slot->host = host;
c91eab4b 2714 host->slot[id] = slot;
f95f3850
WN		 2715
2716 mmc->ops = &dw_mci_ops;
1f44a2a5
SJ		 2717 if (of_property_read_u32_array(host->dev->of_node,
2718 "clock-freq-min-max", freq, 2)) {
2719 mmc->f_min = DW_MCI_FREQ_MIN;
2720 mmc->f_max = DW_MCI_FREQ_MAX;
2721 } else {
b023030f
JC		 2722 dev_info(host->dev,
2723 "'clock-freq-min-max' property was deprecated.\n");
1f44a2a5
SJ		 2724 mmc->f_min = freq[0];
2725 mmc->f_max = freq[1];
2726 }
f95f3850 2727
51da2240
YC		 2728 /*if there are external regulators, get them*/
2729 ret = mmc_regulator_get_supply(mmc);
2730 if (ret == -EPROBE_DEFER)
3cf890fc 2731 goto err_host_allocated;
51da2240
YC		 2732
2733 if (!mmc->ocr_avail)
2734 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
f95f3850 2735
fc3d7720
JC		 2736 if (host->pdata->caps)
2737 mmc->caps = host->pdata->caps;
fc3d7720 2738
6024e166
JC		 2739 /*
2740 * Support MMC_CAP_ERASE by default.
2741 * It needs to use trim/discard/erase commands.
2742 */
2743 mmc->caps |= MMC_CAP_ERASE;
2744
ab269128
AK		 2745 if (host->pdata->pm_caps)
2746 mmc->pm_caps = host->pdata->pm_caps;
2747
800d78bf
TA		 2748 if (host->dev->of_node) {
2749 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2750 if (ctrl_id < 0)
2751 ctrl_id = 0;
2752 } else {
2753 ctrl_id = to_platform_device(host->dev)->id;
2754 }
cb27a843
JH		 2755 if (drv_data && drv_data->caps)
2756 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 2757
4f408cc6
SJ		 2758 if (host->pdata->caps2)
2759 mmc->caps2 = host->pdata->caps2;
4f408cc6 2760
3cf890fc
DA		 2761 ret = mmc_of_parse(mmc);
2762 if (ret)
2763 goto err_host_allocated;
f95f3850 2764
2b708df2 2765 /* Useful defaults if platform data is unset. */
3fc7eaef 2766 if (host->use_dma == TRANS_MODE_IDMAC) {
2b708df2 2767 mmc->max_segs = host->ring_size;
225faf87 2768 mmc->max_blk_size = 65535;
2b708df2
JC		 2769 mmc->max_seg_size = 0x1000;
2770 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2771 mmc->max_blk_count = mmc->max_req_size / 512;
3fc7eaef
SL		 2772 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2773 mmc->max_segs = 64;
225faf87 2774 mmc->max_blk_size = 65535;
3fc7eaef
SL		 2775 mmc->max_blk_count = 65535;
2776 mmc->max_req_size =
2777 mmc->max_blk_size * mmc->max_blk_count;
2778 mmc->max_seg_size = mmc->max_req_size;
f95f3850 2779 } else {
3fc7eaef 2780 /* TRANS_MODE_PIO */
2b708df2 2781 mmc->max_segs = 64;
225faf87 2782 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2b708df2
JC		 2783 mmc->max_blk_count = 512;
2784 mmc->max_req_size = mmc->max_blk_size *
2785 mmc->max_blk_count;
2786 mmc->max_seg_size = mmc->max_req_size;
a39e5746 2787 }
f95f3850 2788
c0834a58 2789 dw_mci_get_cd(mmc);
ae0eb348 2790
0cea529d
JC		 2791 ret = mmc_add_host(mmc);
2792 if (ret)
3cf890fc 2793 goto err_host_allocated;
f95f3850
WN		 2794
2795#if defined(CONFIG_DEBUG_FS)
2796 dw_mci_init_debugfs(slot);
2797#endif
2798
f95f3850 2799 return 0;
800d78bf 2800
3cf890fc 2801err_host_allocated:
800d78bf 2802 mmc_free_host(mmc);
51da2240 2803 return ret;
f95f3850
WN		 2804}
2805
2806static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2807{
f95f3850
WN		 2808 /* Debugfs stuff is cleaned up by mmc core */
2809 mmc_remove_host(slot->mmc);
2810 slot->host->slot[id] = NULL;
2811 mmc_free_host(slot->mmc);
2812}
2813
2814static void dw_mci_init_dma(struct dw_mci *host)
2815{
69d99fdc 2816 int addr_config;
3fc7eaef
SL		 2817 struct device *dev = host->dev;
2818 struct device_node *np = dev->of_node;
69d99fdc 2819
3fc7eaef
SL		 2820 /*
2821 * Check tansfer mode from HCON[17:16]
2822 * Clear the ambiguous description of dw_mmc databook:
2823 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2824 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2825 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2826 * 2b'11: Non DW DMA Interface -> pio only
2827 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2828 * simpler request/acknowledge handshake mechanism and both of them
2829 * are regarded as external dma master for dw_mmc.
2830 */
2831 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2832 if (host->use_dma == DMA_INTERFACE_IDMA) {
2833 host->use_dma = TRANS_MODE_IDMAC;
2834 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2835 host->use_dma == DMA_INTERFACE_GDMA) {
2836 host->use_dma = TRANS_MODE_EDMAC;
2837 } else {
f95f3850
WN		 2838 goto no_dma;
2839 }
2840
2841 /* Determine which DMA interface to use */
3fc7eaef
SL		 2842 if (host->use_dma == TRANS_MODE_IDMAC) {
2843 /*
2844 * Check ADDR_CONFIG bit in HCON to find
2845 * IDMAC address bus width
2846 */
70692752 2847 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
3fc7eaef
SL		 2848
2849 if (addr_config == 1) {
2850 /* host supports IDMAC in 64-bit address mode */
2851 host->dma_64bit_address = 1;
2852 dev_info(host->dev,
2853 "IDMAC supports 64-bit address mode.\n");
2854 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2855 dma_set_coherent_mask(host->dev,
2856 DMA_BIT_MASK(64));
2857 } else {
2858 /* host supports IDMAC in 32-bit address mode */
2859 host->dma_64bit_address = 0;
2860 dev_info(host->dev,
2861 "IDMAC supports 32-bit address mode.\n");
2862 }
f95f3850 2863
3fc7eaef 2864 /* Alloc memory for sg translation */
cc190d4c
SL		 2865 host->sg_cpu = dmam_alloc_coherent(host->dev,
2866 DESC_RING_BUF_SZ,
3fc7eaef
SL		 2867 &host->sg_dma, GFP_KERNEL);
2868 if (!host->sg_cpu) {
2869 dev_err(host->dev,
2870 "%s: could not alloc DMA memory\n",
2871 __func__);
2872 goto no_dma;
2873 }
2874
2875 host->dma_ops = &dw_mci_idmac_ops;
2876 dev_info(host->dev, "Using internal DMA controller.\n");
2877 } else {
2878 /* TRANS_MODE_EDMAC: check dma bindings again */
2879 if ((of_property_count_strings(np, "dma-names") < 0) ||
2880 (!of_find_property(np, "dmas", NULL))) {
2881 goto no_dma;
2882 }
2883 host->dma_ops = &dw_mci_edmac_ops;
2884 dev_info(host->dev, "Using external DMA controller.\n");
2885 }
f95f3850 2886
e1631f98
JC		 2887 if (host->dma_ops->init && host->dma_ops->start &&
2888 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 2889 if (host->dma_ops->init(host)) {
0e3a22c0
SL		 2890 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2891 __func__);
f95f3850
WN		 2892 goto no_dma;
2893 }
2894 } else {
4a90920c 2895 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 2896 goto no_dma;
2897 }
2898
f95f3850
WN		 2899 return;
2900
2901no_dma:
4a90920c 2902 dev_info(host->dev, "Using PIO mode.\n");
3fc7eaef 2903 host->use_dma = TRANS_MODE_PIO;
f95f3850
WN		 2904}
2905
5c935165
DA		 2906static void dw_mci_cmd11_timer(unsigned long arg)
2907{
2908 struct dw_mci *host = (struct dw_mci *)arg;
2909
fd674198
DA		 2910 if (host->state != STATE_SENDING_CMD11) {
2911 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2912 return;
2913 }
5c935165
DA		 2914
2915 host->cmd_status = SDMMC_INT_RTO;
2916 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2917 tasklet_schedule(&host->tasklet);
2918}
2919
57e10486
AK		 2920static void dw_mci_dto_timer(unsigned long arg)
2921{
2922 struct dw_mci *host = (struct dw_mci *)arg;
2923
2924 switch (host->state) {
2925 case STATE_SENDING_DATA:
2926 case STATE_DATA_BUSY:
2927 /*
2928 * If DTO interrupt does NOT come in sending data state,
2929 * we should notify the driver to terminate current transfer
2930 * and report a data timeout to the core.
2931 */
2932 host->data_status = SDMMC_INT_DRTO;
2933 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2934 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2935 tasklet_schedule(&host->tasklet);
2936 break;
2937 default:
2938 break;
2939 }
2940}
2941
c91eab4b 2942#ifdef CONFIG_OF
c91eab4b
TA		 2943static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2944{
2945 struct dw_mci_board *pdata;
2946 struct device *dev = host->dev;
2947 struct device_node *np = dev->of_node;
e95baf13 2948 const struct dw_mci_drv_data *drv_data = host->drv_data;
e8cc37b8 2949 int ret;
3c6d89ea 2950 u32 clock_frequency;
c91eab4b
TA		 2951
2952 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
bf3707ea 2953 if (!pdata)
c91eab4b 2954 return ERR_PTR(-ENOMEM);
c91eab4b 2955
d6786fef 2956 /* find reset controller when exist */
3a667e3f 2957 pdata->rstc = devm_reset_control_get_optional(dev, "reset");
d6786fef
GX		 2958 if (IS_ERR(pdata->rstc)) {
2959 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2960 return ERR_PTR(-EPROBE_DEFER);
2961 }
2962
c91eab4b 2963 /* find out number of slots supported */
8a629d26 2964 of_property_read_u32(np, "num-slots", &pdata->num_slots);
c91eab4b 2965
c91eab4b 2966 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
0e3a22c0
SL		 2967 dev_info(dev,
2968 "fifo-depth property not found, using value of FIFOTH register as default\n");
c91eab4b
TA		 2969
2970 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2971
a0361c1a
JN		 2972 of_property_read_u32(np, "data-addr", &host->data_addr_override);
2973
d6fced83
JN		 2974 if (of_get_property(np, "fifo-watermark-aligned", NULL))
2975 host->wm_aligned = true;
2976
3c6d89ea
DA		 2977 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2978 pdata->bus_hz = clock_frequency;
2979
cb27a843
JH		 2980 if (drv_data && drv_data->parse_dt) {
2981 ret = drv_data->parse_dt(host);
800d78bf
TA		 2982 if (ret)
2983 return ERR_PTR(ret);
2984 }
2985
c91eab4b
TA		 2986 return pdata;
2987}
2988
2989#else /* CONFIG_OF */
2990static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2991{
2992 return ERR_PTR(-EINVAL);
2993}
2994#endif /* CONFIG_OF */
2995
fa0c3283
DA		 2996static void dw_mci_enable_cd(struct dw_mci *host)
2997{
fa0c3283
DA		 2998 unsigned long irqflags;
2999 u32 temp;
3000 int i;
e8cc37b8 3001 struct dw_mci_slot *slot;
fa0c3283 3002
e8cc37b8
SL		 3003 /*
3004 * No need for CD if all slots have a non-error GPIO
3005 * as well as broken card detection is found.
3006 */
fa0c3283 3007 for (i = 0; i < host->num_slots; i++) {
e8cc37b8
SL		 3008 slot = host->slot[i];
3009 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3010 return;
fa0c3283 3011
287980e4 3012 if (mmc_gpio_get_cd(slot->mmc) < 0)
fa0c3283
DA		 3013 break;
3014 }
3015 if (i == host->num_slots)
3016 return;
3017
3018 spin_lock_irqsave(&host->irq_lock, irqflags);
3019 temp = mci_readl(host, INTMASK);
3020 temp |= SDMMC_INT_CD;
3021 mci_writel(host, INTMASK, temp);
3022 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3023}
3024
62ca8034 3025int dw_mci_probe(struct dw_mci *host)
f95f3850 3026{
e95baf13 3027 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 3028 int width, i, ret = 0;
f95f3850 3029 u32 fifo_size;
1c2215b7 3030 int init_slots = 0;
f95f3850 3031
c91eab4b
TA		 3032 if (!host->pdata) {
3033 host->pdata = dw_mci_parse_dt(host);
d6786fef
GX		 3034 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3035 return -EPROBE_DEFER;
3036 } else if (IS_ERR(host->pdata)) {
c91eab4b
TA		 3037 dev_err(host->dev, "platform data not available\n");
3038 return -EINVAL;
3039 }
f95f3850
WN		 3040 }
3041
780f22af 3042 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 3043 if (IS_ERR(host->biu_clk)) {
3044 dev_dbg(host->dev, "biu clock not available\n");
3045 } else {
3046 ret = clk_prepare_enable(host->biu_clk);
3047 if (ret) {
3048 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 3049 return ret;
3050 }
3051 }
3052
780f22af 3053 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 3054 if (IS_ERR(host->ciu_clk)) {
3055 dev_dbg(host->dev, "ciu clock not available\n");
3c6d89ea 3056 host->bus_hz = host->pdata->bus_hz;
f90a0612
TA		 3057 } else {
3058 ret = clk_prepare_enable(host->ciu_clk);
3059 if (ret) {
3060 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 3061 goto err_clk_biu;
3062 }
f90a0612 3063
3c6d89ea
DA		 3064 if (host->pdata->bus_hz) {
3065 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3066 if (ret)
3067 dev_warn(host->dev,
612de4c1 3068 "Unable to set bus rate to %uHz\n",
3c6d89ea
DA		 3069 host->pdata->bus_hz);
3070 }
f90a0612 3071 host->bus_hz = clk_get_rate(host->ciu_clk);
3c6d89ea 3072 }
f90a0612 3073
612de4c1
JC		 3074 if (!host->bus_hz) {
3075 dev_err(host->dev,
3076 "Platform data must supply bus speed\n");
3077 ret = -ENODEV;
3078 goto err_clk_ciu;
3079 }
3080
002f0d5c
YK		 3081 if (drv_data && drv_data->init) {
3082 ret = drv_data->init(host);
3083 if (ret) {
3084 dev_err(host->dev,
3085 "implementation specific init failed\n");
3086 goto err_clk_ciu;
3087 }
3088 }
3089
d6786fef
GX		 3090 if (!IS_ERR(host->pdata->rstc)) {
3091 reset_control_assert(host->pdata->rstc);
3092 usleep_range(10, 50);
3093 reset_control_deassert(host->pdata->rstc);
3094 }
3095
5c935165
DA		 3096 setup_timer(&host->cmd11_timer,
3097 dw_mci_cmd11_timer, (unsigned long)host);
3098
16a34574
JC		 3099 setup_timer(&host->dto_timer,
3100 dw_mci_dto_timer, (unsigned long)host);
57e10486 3101
f95f3850 3102 spin_lock_init(&host->lock);
f8c58c11 3103 spin_lock_init(&host->irq_lock);
f95f3850
WN		 3104 INIT_LIST_HEAD(&host->queue);
3105
f95f3850
WN		 3106 /*
3107 * Get the host data width - this assumes that HCON has been set with
3108 * the correct values.
3109 */
70692752 3110 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
f95f3850
WN		 3111 if (!i) {
3112 host->push_data = dw_mci_push_data16;
3113 host->pull_data = dw_mci_pull_data16;
3114 width = 16;
3115 host->data_shift = 1;
3116 } else if (i == 2) {
3117 host->push_data = dw_mci_push_data64;
3118 host->pull_data = dw_mci_pull_data64;
3119 width = 64;
3120 host->data_shift = 3;
3121 } else {
3122 /* Check for a reserved value, and warn if it is */
3123 WARN((i != 1),
3124 "HCON reports a reserved host data width!\n"
3125 "Defaulting to 32-bit access.\n");
3126 host->push_data = dw_mci_push_data32;
3127 host->pull_data = dw_mci_pull_data32;
3128 width = 32;
3129 host->data_shift = 2;
3130 }
3131
3132 /* Reset all blocks */
3744415c
SL		 3133 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3134 ret = -ENODEV;
3135 goto err_clk_ciu;
3136 }
141a712a
SJ		 3137
3138 host->dma_ops = host->pdata->dma_ops;
3139 dw_mci_init_dma(host);
f95f3850
WN		 3140
3141 /* Clear the interrupts for the host controller */
3142 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3143 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3144
3145 /* Put in max timeout */
3146 mci_writel(host, TMOUT, 0xFFFFFFFF);
3147
3148 /*
3149 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3150 * Tx Mark = fifo_size / 2 DMA Size = 8
3151 */
b86d8253
JH		 3152 if (!host->pdata->fifo_depth) {
3153 /*
3154 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3155 * have been overwritten by the bootloader, just like we're
3156 * about to do, so if you know the value for your hardware, you
3157 * should put it in the platform data.
3158 */
3159 fifo_size = mci_readl(host, FIFOTH);
8234e869 3160 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 3161 } else {
3162 fifo_size = host->pdata->fifo_depth;
3163 }
3164 host->fifo_depth = fifo_size;
52426899
SJ		 3165 host->fifoth_val =
3166 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
e61cf118 3167 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 3168
3169 /* disable clock to CIU */
3170 mci_writel(host, CLKENA, 0);
3171 mci_writel(host, CLKSRC, 0);
3172
63008768
JH		 3173 /*
3174 * In 2.40a spec, Data offset is changed.
3175 * Need to check the version-id and set data-offset for DATA register.
3176 */
3177 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3178 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3179
a0361c1a
JN		 3180 if (host->data_addr_override)
3181 host->fifo_reg = host->regs + host->data_addr_override;
3182 else if (host->verid < DW_MMC_240A)
76184ac1 3183 host->fifo_reg = host->regs + DATA_OFFSET;
63008768 3184 else
76184ac1 3185 host->fifo_reg = host->regs + DATA_240A_OFFSET;
63008768 3186
f95f3850 3187 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
780f22af
SJ		 3188 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3189 host->irq_flags, "dw-mci", host);
f95f3850 3190 if (ret)
6130e7a9 3191 goto err_dmaunmap;
f95f3850 3192
f95f3850
WN		 3193 if (host->pdata->num_slots)
3194 host->num_slots = host->pdata->num_slots;
3195 else
8a629d26
SL		 3196 host->num_slots = 1;
3197
3198 if (host->num_slots < 1 ||
3199 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3200 dev_err(host->dev,
3201 "Platform data must supply correct num_slots.\n");
3202 ret = -ENODEV;
3203 goto err_clk_ciu;
3204 }
f95f3850 3205
2da1d7f2 3206 /*
fa0c3283 3207 * Enable interrupts for command done, data over, data empty,
2da1d7f2
YC		 3208 * receive ready and error such as transmit, receive timeout, crc error
3209 */
2da1d7f2
YC		 3210 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3211 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3212 DW_MCI_ERROR_FLAGS);
0e3a22c0
SL		 3213 /* Enable mci interrupt */
3214 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2da1d7f2 3215
0e3a22c0
SL		 3216 dev_info(host->dev,
3217 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
2da1d7f2
YC		 3218 host->irq, width, fifo_size);
3219
f95f3850
WN		 3220 /* We need at least one slot to succeed */
3221 for (i = 0; i < host->num_slots; i++) {
3222 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 3223 if (ret)
3224 dev_dbg(host->dev, "slot %d init failed\n", i);
3225 else
3226 init_slots++;
3227 }
3228
3229 if (init_slots) {
3230 dev_info(host->dev, "%d slots initialized\n", init_slots);
3231 } else {
0e3a22c0
SL		 3232 dev_dbg(host->dev,
3233 "attempted to initialize %d slots, but failed on all\n",
3234 host->num_slots);
6130e7a9 3235 goto err_dmaunmap;
f95f3850
WN		 3236 }
3237
b793f658
DA		 3238 /* Now that slots are all setup, we can enable card detect */
3239 dw_mci_enable_cd(host);
3240
f95f3850
WN		 3241 return 0;
3242
f95f3850
WN		 3243err_dmaunmap:
3244 if (host->use_dma && host->dma_ops->exit)
3245 host->dma_ops->exit(host);
f90a0612 3246
d6786fef
GX		 3247 if (!IS_ERR(host->pdata->rstc))
3248 reset_control_assert(host->pdata->rstc);
3249
f90a0612 3250err_clk_ciu:
7037f3be 3251 clk_disable_unprepare(host->ciu_clk);
780f22af 3252
f90a0612 3253err_clk_biu:
7037f3be 3254 clk_disable_unprepare(host->biu_clk);
780f22af 3255
f95f3850
WN		 3256 return ret;
3257}
62ca8034 3258EXPORT_SYMBOL(dw_mci_probe);
f95f3850 3259
62ca8034 3260void dw_mci_remove(struct dw_mci *host)
f95f3850 3261{
f95f3850
WN		 3262 int i;
3263
f95f3850 3264 for (i = 0; i < host->num_slots; i++) {
4a90920c 3265 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 3266 if (host->slot[i])
3267 dw_mci_cleanup_slot(host->slot[i], i);
3268 }
3269
048fd7e6
PT		 3270 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3271 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3272
f95f3850
WN		 3273 /* disable clock to CIU */
3274 mci_writel(host, CLKENA, 0);
3275 mci_writel(host, CLKSRC, 0);
3276
f95f3850
WN		 3277 if (host->use_dma && host->dma_ops->exit)
3278 host->dma_ops->exit(host);
3279
d6786fef
GX		 3280 if (!IS_ERR(host->pdata->rstc))
3281 reset_control_assert(host->pdata->rstc);
3282
7037f3be
JC		 3283 clk_disable_unprepare(host->ciu_clk);
3284 clk_disable_unprepare(host->biu_clk);
f95f3850 3285}
62ca8034
SH		 3286EXPORT_SYMBOL(dw_mci_remove);
3287
3288
f95f3850 3289
e9ed8835 3290#ifdef CONFIG_PM
ed24e1ff 3291int dw_mci_runtime_suspend(struct device *dev)
f95f3850 3292{
ed24e1ff
SL		 3293 struct dw_mci *host = dev_get_drvdata(dev);
3294
3fc7eaef
SL		 3295 if (host->use_dma && host->dma_ops->exit)
3296 host->dma_ops->exit(host);
3297
ed24e1ff
SL		 3298 clk_disable_unprepare(host->ciu_clk);
3299
3300 if (host->cur_slot &&
3301 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3302 !mmc_card_is_removable(host->cur_slot->mmc)))
3303 clk_disable_unprepare(host->biu_clk);
3304
f95f3850
WN		 3305 return 0;
3306}
ed24e1ff 3307EXPORT_SYMBOL(dw_mci_runtime_suspend);
f95f3850 3308
ed24e1ff 3309int dw_mci_runtime_resume(struct device *dev)
f95f3850 3310{
ed24e1ff
SL		 3311 int i, ret = 0;
3312 struct dw_mci *host = dev_get_drvdata(dev);
f95f3850 3313
ed24e1ff
SL		 3314 if (host->cur_slot &&
3315 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3316 !mmc_card_is_removable(host->cur_slot->mmc))) {
3317 ret = clk_prepare_enable(host->biu_clk);
3318 if (ret)
3319 return ret;
e61cf118
JC		 3320 }
3321
ed24e1ff
SL		 3322 ret = clk_prepare_enable(host->ciu_clk);
3323 if (ret)
df9bcc2b
JS		 3324 goto err;
3325
3326 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3327 clk_disable_unprepare(host->ciu_clk);
3328 ret = -ENODEV;
3329 goto err;
3330 }
ed24e1ff 3331
3bfe619d 3332 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 3333 host->dma_ops->init(host);
3334
52426899
SJ		 3335 /*
3336 * Restore the initial value at FIFOTH register
3337 * And Invalidate the prev_blksz with zero
3338 */
ed24e1ff
SL		 3339 mci_writel(host, FIFOTH, host->fifoth_val);
3340 host->prev_blksz = 0;
e61cf118 3341
2eb2944f
DA		 3342 /* Put in max timeout */
3343 mci_writel(host, TMOUT, 0xFFFFFFFF);
3344
e61cf118
JC		 3345 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3346 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3347 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3348 DW_MCI_ERROR_FLAGS);
e61cf118
JC		 3349 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3350
f95f3850
WN		 3351 for (i = 0; i < host->num_slots; i++) {
3352 struct dw_mci_slot *slot = host->slot[i];
0e3a22c0 3353
f95f3850
WN		 3354 if (!slot)
3355 continue;
e9748e03 3356 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
ab269128 3357 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
e9748e03
ZX		 3358
3359 /* Force setup bus to guarantee available clock output */
3360 dw_mci_setup_bus(slot, true);
f95f3850 3361 }
fa0c3283
DA		 3362
3363 /* Now that slots are all setup, we can enable card detect */
3364 dw_mci_enable_cd(host);
3365
df9bcc2b
JS		 3366 return 0;
3367
3368err:
3369 if (host->cur_slot &&
3370 (mmc_can_gpio_cd(host->cur_slot->mmc) ||
3371 !mmc_card_is_removable(host->cur_slot->mmc)))
3372 clk_disable_unprepare(host->biu_clk);
3373
ed24e1ff 3374 return ret;
e9ed8835
SL		 3375}
3376EXPORT_SYMBOL(dw_mci_runtime_resume);
3377#endif /* CONFIG_PM */
6fe8890d 3378
f95f3850
WN		 3379static int __init dw_mci_init(void)
3380{
8e1c4e4d 3381 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
62ca8034 3382 return 0;
f95f3850
WN		 3383}
3384
3385static void __exit dw_mci_exit(void)
3386{
f95f3850
WN		 3387}
3388
3389module_init(dw_mci_init);
3390module_exit(dw_mci_exit);
3391
3392MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3393MODULE_AUTHOR("NXP Semiconductor VietNam");
3394MODULE_AUTHOR("Imagination Technologies Ltd");
3395MODULE_LICENSE("GPL v2");
ubuntu-bionic-kernel mirror