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mmc: remove MMC bus legacy suspend/resume method
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
32#include <linux/mmc/dw_mmc.h>
33#include <linux/bitops.h>
c07946a3 34#include <linux/regulator/consumer.h>
1791b13e 35#include <linux/workqueue.h>
f95f3850
WN		 36
37#include "dw_mmc.h"
38
39/* Common flag combinations */
40#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
41 SDMMC_INT_HTO | SDMMC_INT_SBE | \
42 SDMMC_INT_EBE)
43#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
44 SDMMC_INT_RESP_ERR)
45#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
46 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
47#define DW_MCI_SEND_STATUS 1
48#define DW_MCI_RECV_STATUS 2
49#define DW_MCI_DMA_THRESHOLD 16
50
51#ifdef CONFIG_MMC_DW_IDMAC
52struct idmac_desc {
53 u32 des0; /* Control Descriptor */
54#define IDMAC_DES0_DIC BIT(1)
55#define IDMAC_DES0_LD BIT(2)
56#define IDMAC_DES0_FD BIT(3)
57#define IDMAC_DES0_CH BIT(4)
58#define IDMAC_DES0_ER BIT(5)
59#define IDMAC_DES0_CES BIT(30)
60#define IDMAC_DES0_OWN BIT(31)
61
62 u32 des1; /* Buffer sizes */
63#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 64 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850
WN		 65
66 u32 des2; /* buffer 1 physical address */
67
68 u32 des3; /* buffer 2 physical address */
69};
70#endif /* CONFIG_MMC_DW_IDMAC */
71
72/**
73 * struct dw_mci_slot - MMC slot state
74 * @mmc: The mmc_host representing this slot.
75 * @host: The MMC controller this slot is using.
76 * @ctype: Card type for this slot.
77 * @mrq: mmc_request currently being processed or waiting to be
78 * processed, or NULL when the slot is idle.
79 * @queue_node: List node for placing this node in the @queue list of
80 * &struct dw_mci.
81 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
82 * @flags: Random state bits associated with the slot.
83 * @id: Number of this slot.
84 * @last_detect_state: Most recently observed card detect state.
85 */
86struct dw_mci_slot {
87 struct mmc_host *mmc;
88 struct dw_mci *host;
89
90 u32 ctype;
91
92 struct mmc_request *mrq;
93 struct list_head queue_node;
94
95 unsigned int clock;
96 unsigned long flags;
97#define DW_MMC_CARD_PRESENT 0
98#define DW_MMC_CARD_NEED_INIT 1
99 int id;
100 int last_detect_state;
101};
102
1791b13e
JH		 103static struct workqueue_struct *dw_mci_card_workqueue;
104
f95f3850
WN		 105#if defined(CONFIG_DEBUG_FS)
106static int dw_mci_req_show(struct seq_file *s, void *v)
107{
108 struct dw_mci_slot *slot = s->private;
109 struct mmc_request *mrq;
110 struct mmc_command *cmd;
111 struct mmc_command *stop;
112 struct mmc_data *data;
113
114 /* Make sure we get a consistent snapshot */
115 spin_lock_bh(&slot->host->lock);
116 mrq = slot->mrq;
117
118 if (mrq) {
119 cmd = mrq->cmd;
120 data = mrq->data;
121 stop = mrq->stop;
122
123 if (cmd)
124 seq_printf(s,
125 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
126 cmd->opcode, cmd->arg, cmd->flags,
127 cmd->resp[0], cmd->resp[1], cmd->resp[2],
128 cmd->resp[2], cmd->error);
129 if (data)
130 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
131 data->bytes_xfered, data->blocks,
132 data->blksz, data->flags, data->error);
133 if (stop)
134 seq_printf(s,
135 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
136 stop->opcode, stop->arg, stop->flags,
137 stop->resp[0], stop->resp[1], stop->resp[2],
138 stop->resp[2], stop->error);
139 }
140
141 spin_unlock_bh(&slot->host->lock);
142
143 return 0;
144}
145
146static int dw_mci_req_open(struct inode *inode, struct file *file)
147{
148 return single_open(file, dw_mci_req_show, inode->i_private);
149}
150
151static const struct file_operations dw_mci_req_fops = {
152 .owner = THIS_MODULE,
153 .open = dw_mci_req_open,
154 .read = seq_read,
155 .llseek = seq_lseek,
156 .release = single_release,
157};
158
159static int dw_mci_regs_show(struct seq_file *s, void *v)
160{
161 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
162 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
163 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
164 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
165 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
166 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
167
168 return 0;
169}
170
171static int dw_mci_regs_open(struct inode *inode, struct file *file)
172{
173 return single_open(file, dw_mci_regs_show, inode->i_private);
174}
175
176static const struct file_operations dw_mci_regs_fops = {
177 .owner = THIS_MODULE,
178 .open = dw_mci_regs_open,
179 .read = seq_read,
180 .llseek = seq_lseek,
181 .release = single_release,
182};
183
184static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
185{
186 struct mmc_host *mmc = slot->mmc;
187 struct dw_mci *host = slot->host;
188 struct dentry *root;
189 struct dentry *node;
190
191 root = mmc->debugfs_root;
192 if (!root)
193 return;
194
195 node = debugfs_create_file("regs", S_IRUSR, root, host,
196 &dw_mci_regs_fops);
197 if (!node)
198 goto err;
199
200 node = debugfs_create_file("req", S_IRUSR, root, slot,
201 &dw_mci_req_fops);
202 if (!node)
203 goto err;
204
205 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
206 if (!node)
207 goto err;
208
209 node = debugfs_create_x32("pending_events", S_IRUSR, root,
210 (u32 *)&host->pending_events);
211 if (!node)
212 goto err;
213
214 node = debugfs_create_x32("completed_events", S_IRUSR, root,
215 (u32 *)&host->completed_events);
216 if (!node)
217 goto err;
218
219 return;
220
221err:
222 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
223}
224#endif /* defined(CONFIG_DEBUG_FS) */
225
226static void dw_mci_set_timeout(struct dw_mci *host)
227{
228 /* timeout (maximum) */
229 mci_writel(host, TMOUT, 0xffffffff);
230}
231
232static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
233{
234 struct mmc_data *data;
235 u32 cmdr;
236 cmd->error = -EINPROGRESS;
237
238 cmdr = cmd->opcode;
239
240 if (cmdr == MMC_STOP_TRANSMISSION)
241 cmdr |= SDMMC_CMD_STOP;
242 else
243 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
244
245 if (cmd->flags & MMC_RSP_PRESENT) {
246 /* We expect a response, so set this bit */
247 cmdr |= SDMMC_CMD_RESP_EXP;
248 if (cmd->flags & MMC_RSP_136)
249 cmdr |= SDMMC_CMD_RESP_LONG;
250 }
251
252 if (cmd->flags & MMC_RSP_CRC)
253 cmdr |= SDMMC_CMD_RESP_CRC;
254
255 data = cmd->data;
256 if (data) {
257 cmdr |= SDMMC_CMD_DAT_EXP;
258 if (data->flags & MMC_DATA_STREAM)
259 cmdr |= SDMMC_CMD_STRM_MODE;
260 if (data->flags & MMC_DATA_WRITE)
261 cmdr |= SDMMC_CMD_DAT_WR;
262 }
263
264 return cmdr;
265}
266
267static void dw_mci_start_command(struct dw_mci *host,
268 struct mmc_command *cmd, u32 cmd_flags)
269{
270 host->cmd = cmd;
62ca8034 271 dev_vdbg(&host->dev,
f95f3850
WN		 272 "start command: ARGR=0x%08x CMDR=0x%08x\n",
273 cmd->arg, cmd_flags);
274
275 mci_writel(host, CMDARG, cmd->arg);
276 wmb();
277
278 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
279}
280
281static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
282{
283 dw_mci_start_command(host, data->stop, host->stop_cmdr);
284}
285
286/* DMA interface functions */
287static void dw_mci_stop_dma(struct dw_mci *host)
288{
03e8cb53 289 if (host->using_dma) {
f95f3850
WN		 290 host->dma_ops->stop(host);
291 host->dma_ops->cleanup(host);
292 } else {
293 /* Data transfer was stopped by the interrupt handler */
294 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
295 }
296}
297
9aa51408
SJ		 298static int dw_mci_get_dma_dir(struct mmc_data *data)
299{
300 if (data->flags & MMC_DATA_WRITE)
301 return DMA_TO_DEVICE;
302 else
303 return DMA_FROM_DEVICE;
304}
305
9beee912 306#ifdef CONFIG_MMC_DW_IDMAC
f95f3850
WN		 307static void dw_mci_dma_cleanup(struct dw_mci *host)
308{
309 struct mmc_data *data = host->data;
310
311 if (data)
9aa51408
SJ		 312 if (!data->host_cookie)
313 dma_unmap_sg(&host->dev,
314 data->sg,
315 data->sg_len,
316 dw_mci_get_dma_dir(data));
f95f3850
WN		 317}
318
319static void dw_mci_idmac_stop_dma(struct dw_mci *host)
320{
321 u32 temp;
322
323 /* Disable and reset the IDMAC interface */
324 temp = mci_readl(host, CTRL);
325 temp &= ~SDMMC_CTRL_USE_IDMAC;
326 temp |= SDMMC_CTRL_DMA_RESET;
327 mci_writel(host, CTRL, temp);
328
329 /* Stop the IDMAC running */
330 temp = mci_readl(host, BMOD);
a5289a43 331 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
f95f3850
WN		 332 mci_writel(host, BMOD, temp);
333}
334
335static void dw_mci_idmac_complete_dma(struct dw_mci *host)
336{
337 struct mmc_data *data = host->data;
338
62ca8034 339 dev_vdbg(&host->dev, "DMA complete\n");
f95f3850
WN		 340
341 host->dma_ops->cleanup(host);
342
343 /*
344 * If the card was removed, data will be NULL. No point in trying to
345 * send the stop command or waiting for NBUSY in this case.
346 */
347 if (data) {
348 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
349 tasklet_schedule(&host->tasklet);
350 }
351}
352
353static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
354 unsigned int sg_len)
355{
356 int i;
357 struct idmac_desc *desc = host->sg_cpu;
358
359 for (i = 0; i < sg_len; i++, desc++) {
360 unsigned int length = sg_dma_len(&data->sg[i]);
361 u32 mem_addr = sg_dma_address(&data->sg[i]);
362
363 /* Set the OWN bit and disable interrupts for this descriptor */
364 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
365
366 /* Buffer length */
367 IDMAC_SET_BUFFER1_SIZE(desc, length);
368
369 /* Physical address to DMA to/from */
370 desc->des2 = mem_addr;
371 }
372
373 /* Set first descriptor */
374 desc = host->sg_cpu;
375 desc->des0 |= IDMAC_DES0_FD;
376
377 /* Set last descriptor */
378 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
379 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
380 desc->des0 |= IDMAC_DES0_LD;
381
382 wmb();
383}
384
385static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
386{
387 u32 temp;
388
389 dw_mci_translate_sglist(host, host->data, sg_len);
390
391 /* Select IDMAC interface */
392 temp = mci_readl(host, CTRL);
393 temp |= SDMMC_CTRL_USE_IDMAC;
394 mci_writel(host, CTRL, temp);
395
396 wmb();
397
398 /* Enable the IDMAC */
399 temp = mci_readl(host, BMOD);
a5289a43 400 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 401 mci_writel(host, BMOD, temp);
402
403 /* Start it running */
404 mci_writel(host, PLDMND, 1);
405}
406
407static int dw_mci_idmac_init(struct dw_mci *host)
408{
409 struct idmac_desc *p;
410 int i;
411
412 /* Number of descriptors in the ring buffer */
413 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
414
415 /* Forward link the descriptor list */
416 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
417 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
418
419 /* Set the last descriptor as the end-of-ring descriptor */
420 p->des3 = host->sg_dma;
421 p->des0 = IDMAC_DES0_ER;
422
423 /* Mask out interrupts - get Tx & Rx complete only */
424 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
425 SDMMC_IDMAC_INT_TI);
426
427 /* Set the descriptor base address */
428 mci_writel(host, DBADDR, host->sg_dma);
429 return 0;
430}
431
885c3e80
SJ		 432static struct dw_mci_dma_ops dw_mci_idmac_ops = {
433 .init = dw_mci_idmac_init,
434 .start = dw_mci_idmac_start_dma,
435 .stop = dw_mci_idmac_stop_dma,
436 .complete = dw_mci_idmac_complete_dma,
437 .cleanup = dw_mci_dma_cleanup,
438};
439#endif /* CONFIG_MMC_DW_IDMAC */
440
9aa51408
SJ		 441static int dw_mci_pre_dma_transfer(struct dw_mci *host,
442 struct mmc_data *data,
443 bool next)
f95f3850
WN		 444{
445 struct scatterlist *sg;
9aa51408 446 unsigned int i, sg_len;
03e8cb53 447
9aa51408
SJ		 448 if (!next && data->host_cookie)
449 return data->host_cookie;
f95f3850
WN		 450
451 /*
452 * We don't do DMA on "complex" transfers, i.e. with
453 * non-word-aligned buffers or lengths. Also, we don't bother
454 * with all the DMA setup overhead for short transfers.
455 */
456 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
457 return -EINVAL;
9aa51408 458
f95f3850
WN		 459 if (data->blksz & 3)
460 return -EINVAL;
461
462 for_each_sg(data->sg, sg, data->sg_len, i) {
463 if (sg->offset & 3 || sg->length & 3)
464 return -EINVAL;
465 }
466
9aa51408
SJ		 467 sg_len = dma_map_sg(&host->dev,
468 data->sg,
469 data->sg_len,
470 dw_mci_get_dma_dir(data));
471 if (sg_len == 0)
472 return -EINVAL;
03e8cb53 473
9aa51408
SJ		 474 if (next)
475 data->host_cookie = sg_len;
f95f3850 476
9aa51408
SJ		 477 return sg_len;
478}
479
9aa51408
SJ		 480static void dw_mci_pre_req(struct mmc_host *mmc,
481 struct mmc_request *mrq,
482 bool is_first_req)
483{
484 struct dw_mci_slot *slot = mmc_priv(mmc);
485 struct mmc_data *data = mrq->data;
486
487 if (!slot->host->use_dma || !data)
488 return;
489
490 if (data->host_cookie) {
491 data->host_cookie = 0;
492 return;
493 }
494
495 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
496 data->host_cookie = 0;
497}
498
499static void dw_mci_post_req(struct mmc_host *mmc,
500 struct mmc_request *mrq,
501 int err)
502{
503 struct dw_mci_slot *slot = mmc_priv(mmc);
504 struct mmc_data *data = mrq->data;
505
506 if (!slot->host->use_dma || !data)
507 return;
508
509 if (data->host_cookie)
510 dma_unmap_sg(&slot->host->dev,
511 data->sg,
512 data->sg_len,
513 dw_mci_get_dma_dir(data));
514 data->host_cookie = 0;
515}
516
517static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
518{
519 int sg_len;
520 u32 temp;
521
522 host->using_dma = 0;
523
524 /* If we don't have a channel, we can't do DMA */
525 if (!host->use_dma)
526 return -ENODEV;
527
528 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
529 if (sg_len < 0)
530 return sg_len;
531
532 host->using_dma = 1;
f95f3850 533
62ca8034 534 dev_vdbg(&host->dev,
f95f3850
WN		 535 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
536 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
537 sg_len);
538
539 /* Enable the DMA interface */
540 temp = mci_readl(host, CTRL);
541 temp |= SDMMC_CTRL_DMA_ENABLE;
542 mci_writel(host, CTRL, temp);
543
544 /* Disable RX/TX IRQs, let DMA handle it */
545 temp = mci_readl(host, INTMASK);
546 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
547 mci_writel(host, INTMASK, temp);
548
549 host->dma_ops->start(host, sg_len);
550
551 return 0;
552}
553
554static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
555{
556 u32 temp;
557
558 data->error = -EINPROGRESS;
559
560 WARN_ON(host->data);
561 host->sg = NULL;
562 host->data = data;
563
55c5efbc
JH		 564 if (data->flags & MMC_DATA_READ)
565 host->dir_status = DW_MCI_RECV_STATUS;
566 else
567 host->dir_status = DW_MCI_SEND_STATUS;
568
f95f3850 569 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 570 int flags = SG_MITER_ATOMIC;
571 if (host->data->flags & MMC_DATA_READ)
572 flags |= SG_MITER_TO_SG;
573 else
574 flags |= SG_MITER_FROM_SG;
575
576 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 577 host->sg = data->sg;
34b664a2
JH		 578 host->part_buf_start = 0;
579 host->part_buf_count = 0;
f95f3850 580
b40af3aa 581 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 582 temp = mci_readl(host, INTMASK);
583 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
584 mci_writel(host, INTMASK, temp);
585
586 temp = mci_readl(host, CTRL);
587 temp &= ~SDMMC_CTRL_DMA_ENABLE;
588 mci_writel(host, CTRL, temp);
589 }
590}
591
592static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
593{
594 struct dw_mci *host = slot->host;
595 unsigned long timeout = jiffies + msecs_to_jiffies(500);
596 unsigned int cmd_status = 0;
597
598 mci_writel(host, CMDARG, arg);
599 wmb();
600 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
601
602 while (time_before(jiffies, timeout)) {
603 cmd_status = mci_readl(host, CMD);
604 if (!(cmd_status & SDMMC_CMD_START))
605 return;
606 }
607 dev_err(&slot->mmc->class_dev,
608 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
609 cmd, arg, cmd_status);
610}
611
612static void dw_mci_setup_bus(struct dw_mci_slot *slot)
613{
614 struct dw_mci *host = slot->host;
615 u32 div;
616
617 if (slot->clock != host->current_speed) {
618 if (host->bus_hz % slot->clock)
619 /*
620 * move the + 1 after the divide to prevent
621 * over-clocking the card.
622 */
623 div = ((host->bus_hz / slot->clock) >> 1) + 1;
624 else
625 div = (host->bus_hz / slot->clock) >> 1;
626
627 dev_info(&slot->mmc->class_dev,
628 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
629 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
630 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
631
632 /* disable clock */
633 mci_writel(host, CLKENA, 0);
634 mci_writel(host, CLKSRC, 0);
635
636 /* inform CIU */
637 mci_send_cmd(slot,
638 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
639
640 /* set clock to desired speed */
641 mci_writel(host, CLKDIV, div);
642
643 /* inform CIU */
644 mci_send_cmd(slot,
645 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
646
647 /* enable clock */
e3891dc5
JC		 648 mci_writel(host, CLKENA, ((SDMMC_CLKEN_ENABLE |
649 SDMMC_CLKEN_LOW_PWR) << slot->id));
f95f3850
WN		 650
651 /* inform CIU */
652 mci_send_cmd(slot,
653 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
654
655 host->current_speed = slot->clock;
656 }
657
658 /* Set the current slot bus width */
1d56c453 659 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 660}
661
053b3ce6
SJ		 662static void __dw_mci_start_request(struct dw_mci *host,
663 struct dw_mci_slot *slot,
664 struct mmc_command *cmd)
f95f3850
WN		 665{
666 struct mmc_request *mrq;
f95f3850
WN		 667 struct mmc_data *data;
668 u32 cmdflags;
669
670 mrq = slot->mrq;
671 if (host->pdata->select_slot)
672 host->pdata->select_slot(slot->id);
673
674 /* Slot specific timing and width adjustment */
675 dw_mci_setup_bus(slot);
676
677 host->cur_slot = slot;
678 host->mrq = mrq;
679
680 host->pending_events = 0;
681 host->completed_events = 0;
682 host->data_status = 0;
683
053b3ce6 684 data = cmd->data;
f95f3850
WN		 685 if (data) {
686 dw_mci_set_timeout(host);
687 mci_writel(host, BYTCNT, data->blksz*data->blocks);
688 mci_writel(host, BLKSIZ, data->blksz);
689 }
690
f95f3850
WN		 691 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
692
693 /* this is the first command, send the initialization clock */
694 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
695 cmdflags |= SDMMC_CMD_INIT;
696
697 if (data) {
698 dw_mci_submit_data(host, data);
699 wmb();
700 }
701
702 dw_mci_start_command(host, cmd, cmdflags);
703
704 if (mrq->stop)
705 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
706}
707
053b3ce6
SJ		 708static void dw_mci_start_request(struct dw_mci *host,
709 struct dw_mci_slot *slot)
710{
711 struct mmc_request *mrq = slot->mrq;
712 struct mmc_command *cmd;
713
714 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
715 __dw_mci_start_request(host, slot, cmd);
716}
717
7456caae 718/* must be called with host->lock held */
f95f3850
WN		 719static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
720 struct mmc_request *mrq)
721{
722 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
723 host->state);
724
f95f3850
WN		 725 slot->mrq = mrq;
726
727 if (host->state == STATE_IDLE) {
728 host->state = STATE_SENDING_CMD;
729 dw_mci_start_request(host, slot);
730 } else {
731 list_add_tail(&slot->queue_node, &host->queue);
732 }
f95f3850
WN		 733}
734
735static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
736{
737 struct dw_mci_slot *slot = mmc_priv(mmc);
738 struct dw_mci *host = slot->host;
739
740 WARN_ON(slot->mrq);
741
7456caae
JH		 742 /*
743 * The check for card presence and queueing of the request must be
744 * atomic, otherwise the card could be removed in between and the
745 * request wouldn't fail until another card was inserted.
746 */
747 spin_lock_bh(&host->lock);
748
f95f3850 749 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 750 spin_unlock_bh(&host->lock);
f95f3850
WN		 751 mrq->cmd->error = -ENOMEDIUM;
752 mmc_request_done(mmc, mrq);
753 return;
754 }
755
f95f3850 756 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 757
758 spin_unlock_bh(&host->lock);
f95f3850
WN		 759}
760
761static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
762{
763 struct dw_mci_slot *slot = mmc_priv(mmc);
41babf75 764 u32 regs;
f95f3850
WN		 765
766 /* set default 1 bit mode */
767 slot->ctype = SDMMC_CTYPE_1BIT;
768
769 switch (ios->bus_width) {
770 case MMC_BUS_WIDTH_1:
771 slot->ctype = SDMMC_CTYPE_1BIT;
772 break;
773 case MMC_BUS_WIDTH_4:
774 slot->ctype = SDMMC_CTYPE_4BIT;
775 break;
c9b2a06f
JC		 776 case MMC_BUS_WIDTH_8:
777 slot->ctype = SDMMC_CTYPE_8BIT;
778 break;
f95f3850
WN		 779 }
780
3f514291
SJ		 781 regs = mci_readl(slot->host, UHS_REG);
782
41babf75 783 /* DDR mode set */
3f514291 784 if (ios->timing == MMC_TIMING_UHS_DDR50)
41babf75 785 regs |= (0x1 << slot->id) << 16;
3f514291
SJ		 786 else
787 regs &= ~(0x1 << slot->id) << 16;
788
789 mci_writel(slot->host, UHS_REG, regs);
41babf75 790
f95f3850
WN		 791 if (ios->clock) {
792 /*
793 * Use mirror of ios->clock to prevent race with mmc
794 * core ios update when finding the minimum.
795 */
796 slot->clock = ios->clock;
797 }
798
799 switch (ios->power_mode) {
800 case MMC_POWER_UP:
801 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
802 break;
803 default:
804 break;
805 }
806}
807
808static int dw_mci_get_ro(struct mmc_host *mmc)
809{
810 int read_only;
811 struct dw_mci_slot *slot = mmc_priv(mmc);
812 struct dw_mci_board *brd = slot->host->pdata;
813
814 /* Use platform get_ro function, else try on board write protect */
815 if (brd->get_ro)
816 read_only = brd->get_ro(slot->id);
817 else
818 read_only =
819 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
820
821 dev_dbg(&mmc->class_dev, "card is %s\n",
822 read_only ? "read-only" : "read-write");
823
824 return read_only;
825}
826
827static int dw_mci_get_cd(struct mmc_host *mmc)
828{
829 int present;
830 struct dw_mci_slot *slot = mmc_priv(mmc);
831 struct dw_mci_board *brd = slot->host->pdata;
832
833 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 834 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
835 present = 1;
836 else if (brd->get_cd)
f95f3850
WN		 837 present = !brd->get_cd(slot->id);
838 else
839 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
840 == 0 ? 1 : 0;
841
842 if (present)
843 dev_dbg(&mmc->class_dev, "card is present\n");
844 else
845 dev_dbg(&mmc->class_dev, "card is not present\n");
846
847 return present;
848}
849
1a5c8e1f
SH		 850static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
851{
852 struct dw_mci_slot *slot = mmc_priv(mmc);
853 struct dw_mci *host = slot->host;
854 u32 int_mask;
855
856 /* Enable/disable Slot Specific SDIO interrupt */
857 int_mask = mci_readl(host, INTMASK);
858 if (enb) {
859 mci_writel(host, INTMASK,
860 (int_mask | (1 << SDMMC_INT_SDIO(slot->id))));
861 } else {
862 mci_writel(host, INTMASK,
863 (int_mask & ~(1 << SDMMC_INT_SDIO(slot->id))));
864 }
865}
866
f95f3850 867static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 868 .request = dw_mci_request,
9aa51408
SJ		 869 .pre_req = dw_mci_pre_req,
870 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 871 .set_ios = dw_mci_set_ios,
872 .get_ro = dw_mci_get_ro,
873 .get_cd = dw_mci_get_cd,
874 .enable_sdio_irq = dw_mci_enable_sdio_irq,
f95f3850
WN		 875};
876
877static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
878 __releases(&host->lock)
879 __acquires(&host->lock)
880{
881 struct dw_mci_slot *slot;
882 struct mmc_host *prev_mmc = host->cur_slot->mmc;
883
884 WARN_ON(host->cmd || host->data);
885
886 host->cur_slot->mrq = NULL;
887 host->mrq = NULL;
888 if (!list_empty(&host->queue)) {
889 slot = list_entry(host->queue.next,
890 struct dw_mci_slot, queue_node);
891 list_del(&slot->queue_node);
62ca8034 892 dev_vdbg(&host->dev, "list not empty: %s is next\n",
f95f3850
WN		 893 mmc_hostname(slot->mmc));
894 host->state = STATE_SENDING_CMD;
895 dw_mci_start_request(host, slot);
896 } else {
62ca8034 897 dev_vdbg(&host->dev, "list empty\n");
f95f3850
WN		 898 host->state = STATE_IDLE;
899 }
900
901 spin_unlock(&host->lock);
902 mmc_request_done(prev_mmc, mrq);
903 spin_lock(&host->lock);
904}
905
906static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
907{
908 u32 status = host->cmd_status;
909
910 host->cmd_status = 0;
911
912 /* Read the response from the card (up to 16 bytes) */
913 if (cmd->flags & MMC_RSP_PRESENT) {
914 if (cmd->flags & MMC_RSP_136) {
915 cmd->resp[3] = mci_readl(host, RESP0);
916 cmd->resp[2] = mci_readl(host, RESP1);
917 cmd->resp[1] = mci_readl(host, RESP2);
918 cmd->resp[0] = mci_readl(host, RESP3);
919 } else {
920 cmd->resp[0] = mci_readl(host, RESP0);
921 cmd->resp[1] = 0;
922 cmd->resp[2] = 0;
923 cmd->resp[3] = 0;
924 }
925 }
926
927 if (status & SDMMC_INT_RTO)
928 cmd->error = -ETIMEDOUT;
929 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
930 cmd->error = -EILSEQ;
931 else if (status & SDMMC_INT_RESP_ERR)
932 cmd->error = -EIO;
933 else
934 cmd->error = 0;
935
936 if (cmd->error) {
937 /* newer ip versions need a delay between retries */
938 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
939 mdelay(20);
940
941 if (cmd->data) {
942 host->data = NULL;
943 dw_mci_stop_dma(host);
944 }
945 }
946}
947
948static void dw_mci_tasklet_func(unsigned long priv)
949{
950 struct dw_mci *host = (struct dw_mci *)priv;
951 struct mmc_data *data;
952 struct mmc_command *cmd;
953 enum dw_mci_state state;
954 enum dw_mci_state prev_state;
94dd5b33 955 u32 status, ctrl;
f95f3850
WN		 956
957 spin_lock(&host->lock);
958
959 state = host->state;
960 data = host->data;
961
962 do {
963 prev_state = state;
964
965 switch (state) {
966 case STATE_IDLE:
967 break;
968
969 case STATE_SENDING_CMD:
970 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
971 &host->pending_events))
972 break;
973
974 cmd = host->cmd;
975 host->cmd = NULL;
976 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
053b3ce6
SJ		 977 dw_mci_command_complete(host, cmd);
978 if (cmd == host->mrq->sbc && !cmd->error) {
979 prev_state = state = STATE_SENDING_CMD;
980 __dw_mci_start_request(host, host->cur_slot,
981 host->mrq->cmd);
982 goto unlock;
983 }
984
f95f3850
WN		 985 if (!host->mrq->data || cmd->error) {
986 dw_mci_request_end(host, host->mrq);
987 goto unlock;
988 }
989
990 prev_state = state = STATE_SENDING_DATA;
991 /* fall through */
992
993 case STATE_SENDING_DATA:
994 if (test_and_clear_bit(EVENT_DATA_ERROR,
995 &host->pending_events)) {
996 dw_mci_stop_dma(host);
997 if (data->stop)
998 send_stop_cmd(host, data);
999 state = STATE_DATA_ERROR;
1000 break;
1001 }
1002
1003 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1004 &host->pending_events))
1005 break;
1006
1007 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1008 prev_state = state = STATE_DATA_BUSY;
1009 /* fall through */
1010
1011 case STATE_DATA_BUSY:
1012 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1013 &host->pending_events))
1014 break;
1015
1016 host->data = NULL;
1017 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1018 status = host->data_status;
1019
1020 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1021 if (status & SDMMC_INT_DTO) {
f95f3850
WN		 1022 data->error = -ETIMEDOUT;
1023 } else if (status & SDMMC_INT_DCRC) {
f95f3850 1024 data->error = -EILSEQ;
55c5efbc
JH		 1025 } else if (status & SDMMC_INT_EBE &&
1026 host->dir_status ==
1027 DW_MCI_SEND_STATUS) {
1028 /*
1029 * No data CRC status was returned.
1030 * The number of bytes transferred will
1031 * be exaggerated in PIO mode.
1032 */
1033 data->bytes_xfered = 0;
1034 data->error = -ETIMEDOUT;
f95f3850 1035 } else {
62ca8034 1036 dev_err(&host->dev,
f95f3850
WN		 1037 "data FIFO error "
1038 "(status=%08x)\n",
1039 status);
1040 data->error = -EIO;
1041 }
94dd5b33
JH		 1042 /*
1043 * After an error, there may be data lingering
1044 * in the FIFO, so reset it - doing so
1045 * generates a block interrupt, hence setting
1046 * the scatter-gather pointer to NULL.
1047 */
f9c2a0dc 1048 sg_miter_stop(&host->sg_miter);
94dd5b33
JH		 1049 host->sg = NULL;
1050 ctrl = mci_readl(host, CTRL);
1051 ctrl |= SDMMC_CTRL_FIFO_RESET;
1052 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 1053 } else {
1054 data->bytes_xfered = data->blocks * data->blksz;
1055 data->error = 0;
1056 }
1057
1058 if (!data->stop) {
1059 dw_mci_request_end(host, host->mrq);
1060 goto unlock;
1061 }
1062
053b3ce6
SJ		 1063 if (host->mrq->sbc && !data->error) {
1064 data->stop->error = 0;
1065 dw_mci_request_end(host, host->mrq);
1066 goto unlock;
1067 }
1068
f95f3850
WN		 1069 prev_state = state = STATE_SENDING_STOP;
1070 if (!data->error)
1071 send_stop_cmd(host, data);
1072 /* fall through */
1073
1074 case STATE_SENDING_STOP:
1075 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1076 &host->pending_events))
1077 break;
1078
1079 host->cmd = NULL;
1080 dw_mci_command_complete(host, host->mrq->stop);
1081 dw_mci_request_end(host, host->mrq);
1082 goto unlock;
1083
1084 case STATE_DATA_ERROR:
1085 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1086 &host->pending_events))
1087 break;
1088
1089 state = STATE_DATA_BUSY;
1090 break;
1091 }
1092 } while (state != prev_state);
1093
1094 host->state = state;
1095unlock:
1096 spin_unlock(&host->lock);
1097
1098}
1099
34b664a2
JH		 1100/* push final bytes to part_buf, only use during push */
1101static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1102{
34b664a2
JH		 1103 memcpy((void *)&host->part_buf, buf, cnt);
1104 host->part_buf_count = cnt;
1105}
f95f3850 1106
34b664a2
JH		 1107/* append bytes to part_buf, only use during push */
1108static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1109{
1110 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1111 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1112 host->part_buf_count += cnt;
1113 return cnt;
1114}
f95f3850 1115
34b664a2
JH		 1116/* pull first bytes from part_buf, only use during pull */
1117static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1118{
1119 cnt = min(cnt, (int)host->part_buf_count);
1120 if (cnt) {
1121 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1122 cnt);
1123 host->part_buf_count -= cnt;
1124 host->part_buf_start += cnt;
f95f3850 1125 }
34b664a2 1126 return cnt;
f95f3850
WN		 1127}
1128
34b664a2
JH		 1129/* pull final bytes from the part_buf, assuming it's just been filled */
1130static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1131{
34b664a2
JH		 1132 memcpy(buf, &host->part_buf, cnt);
1133 host->part_buf_start = cnt;
1134 host->part_buf_count = (1 << host->data_shift) - cnt;
1135}
f95f3850 1136
34b664a2
JH		 1137static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1138{
1139 /* try and push anything in the part_buf */
1140 if (unlikely(host->part_buf_count)) {
1141 int len = dw_mci_push_part_bytes(host, buf, cnt);
1142 buf += len;
1143 cnt -= len;
1144 if (!sg_next(host->sg) || host->part_buf_count == 2) {
4e0a5adf
JC		 1145 mci_writew(host, DATA(host->data_offset),
1146 host->part_buf16);
34b664a2
JH		 1147 host->part_buf_count = 0;
1148 }
1149 }
1150#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1151 if (unlikely((unsigned long)buf & 0x1)) {
1152 while (cnt >= 2) {
1153 u16 aligned_buf[64];
1154 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1155 int items = len >> 1;
1156 int i;
1157 /* memcpy from input buffer into aligned buffer */
1158 memcpy(aligned_buf, buf, len);
1159 buf += len;
1160 cnt -= len;
1161 /* push data from aligned buffer into fifo */
1162 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1163 mci_writew(host, DATA(host->data_offset),
1164 aligned_buf[i]);
34b664a2
JH		 1165 }
1166 } else
1167#endif
1168 {
1169 u16 *pdata = buf;
1170 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1171 mci_writew(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1172 buf = pdata;
1173 }
1174 /* put anything remaining in the part_buf */
1175 if (cnt) {
1176 dw_mci_set_part_bytes(host, buf, cnt);
1177 if (!sg_next(host->sg))
4e0a5adf
JC		 1178 mci_writew(host, DATA(host->data_offset),
1179 host->part_buf16);
34b664a2
JH		 1180 }
1181}
f95f3850 1182
34b664a2
JH		 1183static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1184{
1185#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1186 if (unlikely((unsigned long)buf & 0x1)) {
1187 while (cnt >= 2) {
1188 /* pull data from fifo into aligned buffer */
1189 u16 aligned_buf[64];
1190 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1191 int items = len >> 1;
1192 int i;
1193 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1194 aligned_buf[i] = mci_readw(host,
1195 DATA(host->data_offset));
34b664a2
JH		 1196 /* memcpy from aligned buffer into output buffer */
1197 memcpy(buf, aligned_buf, len);
1198 buf += len;
1199 cnt -= len;
1200 }
1201 } else
1202#endif
1203 {
1204 u16 *pdata = buf;
1205 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1206 *pdata++ = mci_readw(host, DATA(host->data_offset));
34b664a2
JH		 1207 buf = pdata;
1208 }
1209 if (cnt) {
4e0a5adf 1210 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
34b664a2 1211 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1212 }
1213}
1214
1215static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1216{
34b664a2
JH		 1217 /* try and push anything in the part_buf */
1218 if (unlikely(host->part_buf_count)) {
1219 int len = dw_mci_push_part_bytes(host, buf, cnt);
1220 buf += len;
1221 cnt -= len;
1222 if (!sg_next(host->sg) || host->part_buf_count == 4) {
4e0a5adf
JC		 1223 mci_writel(host, DATA(host->data_offset),
1224 host->part_buf32);
34b664a2
JH		 1225 host->part_buf_count = 0;
1226 }
1227 }
1228#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1229 if (unlikely((unsigned long)buf & 0x3)) {
1230 while (cnt >= 4) {
1231 u32 aligned_buf[32];
1232 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1233 int items = len >> 2;
1234 int i;
1235 /* memcpy from input buffer into aligned buffer */
1236 memcpy(aligned_buf, buf, len);
1237 buf += len;
1238 cnt -= len;
1239 /* push data from aligned buffer into fifo */
1240 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1241 mci_writel(host, DATA(host->data_offset),
1242 aligned_buf[i]);
34b664a2
JH		 1243 }
1244 } else
1245#endif
1246 {
1247 u32 *pdata = buf;
1248 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1249 mci_writel(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1250 buf = pdata;
1251 }
1252 /* put anything remaining in the part_buf */
1253 if (cnt) {
1254 dw_mci_set_part_bytes(host, buf, cnt);
1255 if (!sg_next(host->sg))
4e0a5adf
JC		 1256 mci_writel(host, DATA(host->data_offset),
1257 host->part_buf32);
f95f3850
WN		 1258 }
1259}
1260
1261static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1262{
34b664a2
JH		 1263#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1264 if (unlikely((unsigned long)buf & 0x3)) {
1265 while (cnt >= 4) {
1266 /* pull data from fifo into aligned buffer */
1267 u32 aligned_buf[32];
1268 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1269 int items = len >> 2;
1270 int i;
1271 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1272 aligned_buf[i] = mci_readl(host,
1273 DATA(host->data_offset));
34b664a2
JH		 1274 /* memcpy from aligned buffer into output buffer */
1275 memcpy(buf, aligned_buf, len);
1276 buf += len;
1277 cnt -= len;
1278 }
1279 } else
1280#endif
1281 {
1282 u32 *pdata = buf;
1283 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1284 *pdata++ = mci_readl(host, DATA(host->data_offset));
34b664a2
JH		 1285 buf = pdata;
1286 }
1287 if (cnt) {
4e0a5adf 1288 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
34b664a2 1289 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1290 }
1291}
1292
1293static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1294{
34b664a2
JH		 1295 /* try and push anything in the part_buf */
1296 if (unlikely(host->part_buf_count)) {
1297 int len = dw_mci_push_part_bytes(host, buf, cnt);
1298 buf += len;
1299 cnt -= len;
1300 if (!sg_next(host->sg) || host->part_buf_count == 8) {
4e0a5adf
JC		 1301 mci_writew(host, DATA(host->data_offset),
1302 host->part_buf);
34b664a2
JH		 1303 host->part_buf_count = 0;
1304 }
1305 }
1306#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1307 if (unlikely((unsigned long)buf & 0x7)) {
1308 while (cnt >= 8) {
1309 u64 aligned_buf[16];
1310 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1311 int items = len >> 3;
1312 int i;
1313 /* memcpy from input buffer into aligned buffer */
1314 memcpy(aligned_buf, buf, len);
1315 buf += len;
1316 cnt -= len;
1317 /* push data from aligned buffer into fifo */
1318 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1319 mci_writeq(host, DATA(host->data_offset),
1320 aligned_buf[i]);
34b664a2
JH		 1321 }
1322 } else
1323#endif
1324 {
1325 u64 *pdata = buf;
1326 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1327 mci_writeq(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1328 buf = pdata;
1329 }
1330 /* put anything remaining in the part_buf */
1331 if (cnt) {
1332 dw_mci_set_part_bytes(host, buf, cnt);
1333 if (!sg_next(host->sg))
4e0a5adf
JC		 1334 mci_writeq(host, DATA(host->data_offset),
1335 host->part_buf);
f95f3850
WN		 1336 }
1337}
1338
1339static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1340{
34b664a2
JH		 1341#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1342 if (unlikely((unsigned long)buf & 0x7)) {
1343 while (cnt >= 8) {
1344 /* pull data from fifo into aligned buffer */
1345 u64 aligned_buf[16];
1346 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1347 int items = len >> 3;
1348 int i;
1349 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1350 aligned_buf[i] = mci_readq(host,
1351 DATA(host->data_offset));
34b664a2
JH		 1352 /* memcpy from aligned buffer into output buffer */
1353 memcpy(buf, aligned_buf, len);
1354 buf += len;
1355 cnt -= len;
1356 }
1357 } else
1358#endif
1359 {
1360 u64 *pdata = buf;
1361 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1362 *pdata++ = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1363 buf = pdata;
1364 }
1365 if (cnt) {
4e0a5adf 1366 host->part_buf = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1367 dw_mci_pull_final_bytes(host, buf, cnt);
1368 }
1369}
f95f3850 1370
34b664a2
JH		 1371static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1372{
1373 int len;
f95f3850 1374
34b664a2
JH		 1375 /* get remaining partial bytes */
1376 len = dw_mci_pull_part_bytes(host, buf, cnt);
1377 if (unlikely(len == cnt))
1378 return;
1379 buf += len;
1380 cnt -= len;
1381
1382 /* get the rest of the data */
1383 host->pull_data(host, buf, cnt);
f95f3850
WN		 1384}
1385
1386static void dw_mci_read_data_pio(struct dw_mci *host)
1387{
f9c2a0dc
SJ		 1388 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1389 void *buf;
1390 unsigned int offset;
f95f3850
WN		 1391 struct mmc_data *data = host->data;
1392 int shift = host->data_shift;
1393 u32 status;
ba6a902d 1394 unsigned int nbytes = 0, len;
f9c2a0dc 1395 unsigned int remain, fcnt;
f95f3850
WN		 1396
1397 do {
f9c2a0dc
SJ		 1398 if (!sg_miter_next(sg_miter))
1399 goto done;
1400
1401 host->sg = sg_miter->__sg;
1402 buf = sg_miter->addr;
1403 remain = sg_miter->length;
1404 offset = 0;
1405
1406 do {
1407 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1408 << shift) + host->part_buf_count;
1409 len = min(remain, fcnt);
1410 if (!len)
1411 break;
34b664a2 1412 dw_mci_pull_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1413 offset += len;
1414 nbytes += len;
f9c2a0dc
SJ		 1415 remain -= len;
1416 } while (remain);
1417 sg_miter->consumed = offset;
f95f3850
WN		 1418
1419 status = mci_readl(host, MINTSTS);
1420 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1421 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1422 host->data_status = status;
1423 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1424 sg_miter_stop(sg_miter);
1425 host->sg = NULL;
f95f3850
WN		 1426 smp_wmb();
1427
1428 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1429
1430 tasklet_schedule(&host->tasklet);
1431 return;
1432 }
f95f3850 1433 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
f95f3850 1434 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1435
1436 if (!remain) {
1437 if (!sg_miter_next(sg_miter))
1438 goto done;
1439 sg_miter->consumed = 0;
1440 }
1441 sg_miter_stop(sg_miter);
f95f3850
WN		 1442 return;
1443
1444done:
1445 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1446 sg_miter_stop(sg_miter);
1447 host->sg = NULL;
f95f3850
WN		 1448 smp_wmb();
1449 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1450}
1451
1452static void dw_mci_write_data_pio(struct dw_mci *host)
1453{
f9c2a0dc
SJ		 1454 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1455 void *buf;
1456 unsigned int offset;
f95f3850
WN		 1457 struct mmc_data *data = host->data;
1458 int shift = host->data_shift;
1459 u32 status;
1460 unsigned int nbytes = 0, len;
f9c2a0dc
SJ		 1461 unsigned int fifo_depth = host->fifo_depth;
1462 unsigned int remain, fcnt;
f95f3850
WN		 1463
1464 do {
f9c2a0dc
SJ		 1465 if (!sg_miter_next(sg_miter))
1466 goto done;
1467
1468 host->sg = sg_miter->__sg;
1469 buf = sg_miter->addr;
1470 remain = sg_miter->length;
1471 offset = 0;
1472
1473 do {
1474 fcnt = ((fifo_depth -
1475 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1476 << shift) - host->part_buf_count;
1477 len = min(remain, fcnt);
1478 if (!len)
1479 break;
f95f3850 1480 host->push_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1481 offset += len;
1482 nbytes += len;
f9c2a0dc
SJ		 1483 remain -= len;
1484 } while (remain);
1485 sg_miter->consumed = offset;
f95f3850
WN		 1486
1487 status = mci_readl(host, MINTSTS);
1488 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1489 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1490 host->data_status = status;
1491 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1492 sg_miter_stop(sg_miter);
1493 host->sg = NULL;
f95f3850
WN		 1494
1495 smp_wmb();
1496
1497 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1498
1499 tasklet_schedule(&host->tasklet);
1500 return;
1501 }
1502 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f95f3850 1503 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1504
1505 if (!remain) {
1506 if (!sg_miter_next(sg_miter))
1507 goto done;
1508 sg_miter->consumed = 0;
1509 }
1510 sg_miter_stop(sg_miter);
f95f3850
WN		 1511 return;
1512
1513done:
1514 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1515 sg_miter_stop(sg_miter);
1516 host->sg = NULL;
f95f3850
WN		 1517 smp_wmb();
1518 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1519}
1520
1521static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1522{
1523 if (!host->cmd_status)
1524 host->cmd_status = status;
1525
1526 smp_wmb();
1527
1528 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1529 tasklet_schedule(&host->tasklet);
1530}
1531
1532static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1533{
1534 struct dw_mci *host = dev_id;
1535 u32 status, pending;
1536 unsigned int pass_count = 0;
1a5c8e1f 1537 int i;
f95f3850
WN		 1538
1539 do {
1540 status = mci_readl(host, RINTSTS);
1541 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1542
1543 /*
1544 * DTO fix - version 2.10a and below, and only if internal DMA
1545 * is configured.
1546 */
1547 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1548 if (!pending &&
1549 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1550 pending |= SDMMC_INT_DATA_OVER;
1551 }
1552
1553 if (!pending)
1554 break;
1555
1556 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1557 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1558 host->cmd_status = status;
1559 smp_wmb();
1560 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1561 }
1562
1563 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1564 /* if there is an error report DATA_ERROR */
1565 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1566 host->data_status = status;
1567 smp_wmb();
1568 set_bit(EVENT_DATA_ERROR, &host->pending_events);
6e83e10d
SJ		 1569 if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1570 SDMMC_INT_SBE | SDMMC_INT_EBE)))
1571 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1572 }
1573
1574 if (pending & SDMMC_INT_DATA_OVER) {
1575 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1576 if (!host->data_status)
1577 host->data_status = status;
1578 smp_wmb();
1579 if (host->dir_status == DW_MCI_RECV_STATUS) {
1580 if (host->sg != NULL)
1581 dw_mci_read_data_pio(host);
1582 }
1583 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1584 tasklet_schedule(&host->tasklet);
1585 }
1586
1587 if (pending & SDMMC_INT_RXDR) {
1588 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 1589 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
f95f3850
WN		 1590 dw_mci_read_data_pio(host);
1591 }
1592
1593 if (pending & SDMMC_INT_TXDR) {
1594 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 1595 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 1596 dw_mci_write_data_pio(host);
1597 }
1598
1599 if (pending & SDMMC_INT_CMD_DONE) {
1600 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1601 dw_mci_cmd_interrupt(host, status);
1602 }
1603
1604 if (pending & SDMMC_INT_CD) {
1605 mci_writel(host, RINTSTS, SDMMC_INT_CD);
1791b13e 1606 queue_work(dw_mci_card_workqueue, &host->card_work);
f95f3850
WN		 1607 }
1608
1a5c8e1f
SH		 1609 /* Handle SDIO Interrupts */
1610 for (i = 0; i < host->num_slots; i++) {
1611 struct dw_mci_slot *slot = host->slot[i];
1612 if (pending & SDMMC_INT_SDIO(i)) {
1613 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1614 mmc_signal_sdio_irq(slot->mmc);
1615 }
1616 }
1617
f95f3850
WN		 1618 } while (pass_count++ < 5);
1619
1620#ifdef CONFIG_MMC_DW_IDMAC
1621 /* Handle DMA interrupts */
1622 pending = mci_readl(host, IDSTS);
1623 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1624 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1625 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1626 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1627 host->dma_ops->complete(host);
1628 }
1629#endif
1630
1631 return IRQ_HANDLED;
1632}
1633
1791b13e 1634static void dw_mci_work_routine_card(struct work_struct *work)
f95f3850 1635{
1791b13e 1636 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
f95f3850
WN		 1637 int i;
1638
1639 for (i = 0; i < host->num_slots; i++) {
1640 struct dw_mci_slot *slot = host->slot[i];
1641 struct mmc_host *mmc = slot->mmc;
1642 struct mmc_request *mrq;
1643 int present;
1644 u32 ctrl;
1645
1646 present = dw_mci_get_cd(mmc);
1647 while (present != slot->last_detect_state) {
f95f3850
WN		 1648 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1649 present ? "inserted" : "removed");
1650
1791b13e
JH		 1651 /* Power up slot (before spin_lock, may sleep) */
1652 if (present != 0 && host->pdata->setpower)
1653 host->pdata->setpower(slot->id, mmc->ocr_avail);
1654
1655 spin_lock_bh(&host->lock);
1656
f95f3850
WN		 1657 /* Card change detected */
1658 slot->last_detect_state = present;
1659
1791b13e
JH		 1660 /* Mark card as present if applicable */
1661 if (present != 0)
f95f3850 1662 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850
WN		 1663
1664 /* Clean up queue if present */
1665 mrq = slot->mrq;
1666 if (mrq) {
1667 if (mrq == host->mrq) {
1668 host->data = NULL;
1669 host->cmd = NULL;
1670
1671 switch (host->state) {
1672 case STATE_IDLE:
1673 break;
1674 case STATE_SENDING_CMD:
1675 mrq->cmd->error = -ENOMEDIUM;
1676 if (!mrq->data)
1677 break;
1678 /* fall through */
1679 case STATE_SENDING_DATA:
1680 mrq->data->error = -ENOMEDIUM;
1681 dw_mci_stop_dma(host);
1682 break;
1683 case STATE_DATA_BUSY:
1684 case STATE_DATA_ERROR:
1685 if (mrq->data->error == -EINPROGRESS)
1686 mrq->data->error = -ENOMEDIUM;
1687 if (!mrq->stop)
1688 break;
1689 /* fall through */
1690 case STATE_SENDING_STOP:
1691 mrq->stop->error = -ENOMEDIUM;
1692 break;
1693 }
1694
1695 dw_mci_request_end(host, mrq);
1696 } else {
1697 list_del(&slot->queue_node);
1698 mrq->cmd->error = -ENOMEDIUM;
1699 if (mrq->data)
1700 mrq->data->error = -ENOMEDIUM;
1701 if (mrq->stop)
1702 mrq->stop->error = -ENOMEDIUM;
1703
1704 spin_unlock(&host->lock);
1705 mmc_request_done(slot->mmc, mrq);
1706 spin_lock(&host->lock);
1707 }
1708 }
1709
1710 /* Power down slot */
1711 if (present == 0) {
f95f3850
WN		 1712 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1713
1714 /*
1715 * Clear down the FIFO - doing so generates a
1716 * block interrupt, hence setting the
1717 * scatter-gather pointer to NULL.
1718 */
f9c2a0dc 1719 sg_miter_stop(&host->sg_miter);
f95f3850
WN		 1720 host->sg = NULL;
1721
1722 ctrl = mci_readl(host, CTRL);
1723 ctrl |= SDMMC_CTRL_FIFO_RESET;
1724 mci_writel(host, CTRL, ctrl);
1725
1726#ifdef CONFIG_MMC_DW_IDMAC
1727 ctrl = mci_readl(host, BMOD);
1728 ctrl |= 0x01; /* Software reset of DMA */
1729 mci_writel(host, BMOD, ctrl);
1730#endif
1731
1732 }
1733
1791b13e
JH		 1734 spin_unlock_bh(&host->lock);
1735
1736 /* Power down slot (after spin_unlock, may sleep) */
1737 if (present == 0 && host->pdata->setpower)
1738 host->pdata->setpower(slot->id, 0);
1739
f95f3850
WN		 1740 present = dw_mci_get_cd(mmc);
1741 }
1742
1743 mmc_detect_change(slot->mmc,
1744 msecs_to_jiffies(host->pdata->detect_delay_ms));
1745 }
1746}
1747
1748static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1749{
1750 struct mmc_host *mmc;
1751 struct dw_mci_slot *slot;
1752
62ca8034 1753 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->dev);
f95f3850
WN		 1754 if (!mmc)
1755 return -ENOMEM;
1756
1757 slot = mmc_priv(mmc);
1758 slot->id = id;
1759 slot->mmc = mmc;
1760 slot->host = host;
1761
1762 mmc->ops = &dw_mci_ops;
1763 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1764 mmc->f_max = host->bus_hz;
1765
1766 if (host->pdata->get_ocr)
1767 mmc->ocr_avail = host->pdata->get_ocr(id);
1768 else
1769 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1770
1771 /*
1772 * Start with slot power disabled, it will be enabled when a card
1773 * is detected.
1774 */
1775 if (host->pdata->setpower)
1776 host->pdata->setpower(id, 0);
1777
fc3d7720
JC		 1778 if (host->pdata->caps)
1779 mmc->caps = host->pdata->caps;
fc3d7720 1780
4f408cc6
SJ		 1781 if (host->pdata->caps2)
1782 mmc->caps2 = host->pdata->caps2;
4f408cc6 1783
f95f3850
WN		 1784 if (host->pdata->get_bus_wd)
1785 if (host->pdata->get_bus_wd(slot->id) >= 4)
1786 mmc->caps |= MMC_CAP_4_BIT_DATA;
1787
1788 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
6daa7778 1789 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
f95f3850 1790
356ac2cf
JC		 1791 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
1792 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
1793 else
1794 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
1795
f95f3850
WN		 1796 if (host->pdata->blk_settings) {
1797 mmc->max_segs = host->pdata->blk_settings->max_segs;
1798 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1799 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1800 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1801 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1802 } else {
1803 /* Useful defaults if platform data is unset. */
a39e5746
JC		 1804#ifdef CONFIG_MMC_DW_IDMAC
1805 mmc->max_segs = host->ring_size;
1806 mmc->max_blk_size = 65536;
1807 mmc->max_blk_count = host->ring_size;
1808 mmc->max_seg_size = 0x1000;
1809 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1810#else
f95f3850
WN		 1811 mmc->max_segs = 64;
1812 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1813 mmc->max_blk_count = 512;
1814 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1815 mmc->max_seg_size = mmc->max_req_size;
f95f3850 1816#endif /* CONFIG_MMC_DW_IDMAC */
a39e5746 1817 }
f95f3850 1818
c07946a3
JC		 1819 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1820 if (IS_ERR(host->vmmc)) {
a3c76eb9 1821 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
c07946a3
JC		 1822 host->vmmc = NULL;
1823 } else
1824 regulator_enable(host->vmmc);
1825
f95f3850
WN		 1826 if (dw_mci_get_cd(mmc))
1827 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1828 else
1829 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1830
1831 host->slot[id] = slot;
1832 mmc_add_host(mmc);
1833
1834#if defined(CONFIG_DEBUG_FS)
1835 dw_mci_init_debugfs(slot);
1836#endif
1837
1838 /* Card initially undetected */
1839 slot->last_detect_state = 0;
1840
dd6c4b98
WN		 1841 /*
1842 * Card may have been plugged in prior to boot so we
1843 * need to run the detect tasklet
1844 */
1791b13e 1845 queue_work(dw_mci_card_workqueue, &host->card_work);
dd6c4b98 1846
f95f3850
WN		 1847 return 0;
1848}
1849
1850static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1851{
1852 /* Shutdown detect IRQ */
1853 if (slot->host->pdata->exit)
1854 slot->host->pdata->exit(id);
1855
1856 /* Debugfs stuff is cleaned up by mmc core */
1857 mmc_remove_host(slot->mmc);
1858 slot->host->slot[id] = NULL;
1859 mmc_free_host(slot->mmc);
1860}
1861
1862static void dw_mci_init_dma(struct dw_mci *host)
1863{
1864 /* Alloc memory for sg translation */
62ca8034 1865 host->sg_cpu = dma_alloc_coherent(&host->dev, PAGE_SIZE,
f95f3850
WN		 1866 &host->sg_dma, GFP_KERNEL);
1867 if (!host->sg_cpu) {
62ca8034 1868 dev_err(&host->dev, "%s: could not alloc DMA memory\n",
f95f3850
WN		 1869 __func__);
1870 goto no_dma;
1871 }
1872
1873 /* Determine which DMA interface to use */
1874#ifdef CONFIG_MMC_DW_IDMAC
1875 host->dma_ops = &dw_mci_idmac_ops;
62ca8034 1876 dev_info(&host->dev, "Using internal DMA controller.\n");
f95f3850
WN		 1877#endif
1878
1879 if (!host->dma_ops)
1880 goto no_dma;
1881
1882 if (host->dma_ops->init) {
1883 if (host->dma_ops->init(host)) {
62ca8034 1884 dev_err(&host->dev, "%s: Unable to initialize "
f95f3850
WN		 1885 "DMA Controller.\n", __func__);
1886 goto no_dma;
1887 }
1888 } else {
62ca8034 1889 dev_err(&host->dev, "DMA initialization not found.\n");
f95f3850
WN		 1890 goto no_dma;
1891 }
1892
1893 host->use_dma = 1;
1894 return;
1895
1896no_dma:
62ca8034 1897 dev_info(&host->dev, "Using PIO mode.\n");
f95f3850
WN		 1898 host->use_dma = 0;
1899 return;
1900}
1901
1902static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1903{
1904 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1905 unsigned int ctrl;
1906
1907 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1908 SDMMC_CTRL_DMA_RESET));
1909
1910 /* wait till resets clear */
1911 do {
1912 ctrl = mci_readl(host, CTRL);
1913 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1914 SDMMC_CTRL_DMA_RESET)))
1915 return true;
1916 } while (time_before(jiffies, timeout));
1917
1918 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1919
1920 return false;
1921}
1922
62ca8034 1923int dw_mci_probe(struct dw_mci *host)
f95f3850 1924{
62ca8034 1925 int width, i, ret = 0;
f95f3850
WN		 1926 u32 fifo_size;
1927
62ca8034
SH		 1928 if (!host->pdata || !host->pdata->init) {
1929 dev_err(&host->dev,
f95f3850 1930 "Platform data must supply init function\n");
62ca8034 1931 return -ENODEV;
f95f3850
WN		 1932 }
1933
62ca8034
SH		 1934 if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
1935 dev_err(&host->dev,
f95f3850 1936 "Platform data must supply select_slot function\n");
62ca8034 1937 return -ENODEV;
f95f3850
WN		 1938 }
1939
62ca8034
SH		 1940 if (!host->pdata->bus_hz) {
1941 dev_err(&host->dev,
f95f3850 1942 "Platform data must supply bus speed\n");
62ca8034 1943 return -ENODEV;
f95f3850
WN		 1944 }
1945
62ca8034
SH		 1946 host->bus_hz = host->pdata->bus_hz;
1947 host->quirks = host->pdata->quirks;
f95f3850
WN		 1948
1949 spin_lock_init(&host->lock);
1950 INIT_LIST_HEAD(&host->queue);
1951
f95f3850 1952
62ca8034 1953 host->dma_ops = host->pdata->dma_ops;
f95f3850
WN		 1954 dw_mci_init_dma(host);
1955
1956 /*
1957 * Get the host data width - this assumes that HCON has been set with
1958 * the correct values.
1959 */
1960 i = (mci_readl(host, HCON) >> 7) & 0x7;
1961 if (!i) {
1962 host->push_data = dw_mci_push_data16;
1963 host->pull_data = dw_mci_pull_data16;
1964 width = 16;
1965 host->data_shift = 1;
1966 } else if (i == 2) {
1967 host->push_data = dw_mci_push_data64;
1968 host->pull_data = dw_mci_pull_data64;
1969 width = 64;
1970 host->data_shift = 3;
1971 } else {
1972 /* Check for a reserved value, and warn if it is */
1973 WARN((i != 1),
1974 "HCON reports a reserved host data width!\n"
1975 "Defaulting to 32-bit access.\n");
1976 host->push_data = dw_mci_push_data32;
1977 host->pull_data = dw_mci_pull_data32;
1978 width = 32;
1979 host->data_shift = 2;
1980 }
1981
1982 /* Reset all blocks */
62ca8034 1983 if (!mci_wait_reset(&host->dev, host)) {
f95f3850
WN		 1984 ret = -ENODEV;
1985 goto err_dmaunmap;
1986 }
1987
1988 /* Clear the interrupts for the host controller */
1989 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1990 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1991
1992 /* Put in max timeout */
1993 mci_writel(host, TMOUT, 0xFFFFFFFF);
1994
1995 /*
1996 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
1997 * Tx Mark = fifo_size / 2 DMA Size = 8
1998 */
b86d8253
JH		 1999 if (!host->pdata->fifo_depth) {
2000 /*
2001 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2002 * have been overwritten by the bootloader, just like we're
2003 * about to do, so if you know the value for your hardware, you
2004 * should put it in the platform data.
2005 */
2006 fifo_size = mci_readl(host, FIFOTH);
8234e869 2007 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 2008 } else {
2009 fifo_size = host->pdata->fifo_depth;
2010 }
2011 host->fifo_depth = fifo_size;
e61cf118
JC		 2012 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2013 ((fifo_size/2) << 0));
2014 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 2015
2016 /* disable clock to CIU */
2017 mci_writel(host, CLKENA, 0);
2018 mci_writel(host, CLKSRC, 0);
2019
2020 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1791b13e
JH		 2021 dw_mci_card_workqueue = alloc_workqueue("dw-mci-card",
2022 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
2023 if (!dw_mci_card_workqueue)
2024 goto err_dmaunmap;
2025 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
62ca8034 2026 ret = request_irq(host->irq, dw_mci_interrupt, host->irq_flags, "dw-mci", host);
f95f3850 2027 if (ret)
1791b13e 2028 goto err_workqueue;
f95f3850 2029
f95f3850
WN		 2030 if (host->pdata->num_slots)
2031 host->num_slots = host->pdata->num_slots;
2032 else
2033 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2034
2035 /* We need at least one slot to succeed */
2036 for (i = 0; i < host->num_slots; i++) {
2037 ret = dw_mci_init_slot(host, i);
2038 if (ret) {
2039 ret = -ENODEV;
2040 goto err_init_slot;
2041 }
2042 }
2043
4e0a5adf
JC		 2044 /*
2045 * In 2.40a spec, Data offset is changed.
2046 * Need to check the version-id and set data-offset for DATA register.
2047 */
2048 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
62ca8034 2049 dev_info(&host->dev, "Version ID is %04x\n", host->verid);
4e0a5adf
JC		 2050
2051 if (host->verid < DW_MMC_240A)
2052 host->data_offset = DATA_OFFSET;
2053 else
2054 host->data_offset = DATA_240A_OFFSET;
2055
f95f3850
WN		 2056 /*
2057 * Enable interrupts for command done, data over, data empty, card det,
2058 * receive ready and error such as transmit, receive timeout, crc error
2059 */
2060 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2061 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2062 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2063 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2064 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2065
62ca8034 2066 dev_info(&host->dev, "DW MMC controller at irq %d, "
b86d8253
JH		 2067 "%d bit host data width, "
2068 "%u deep fifo\n",
62ca8034 2069 host->irq, width, fifo_size);
f95f3850 2070 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
62ca8034 2071 dev_info(&host->dev, "Internal DMAC interrupt fix enabled.\n");
f95f3850
WN		 2072
2073 return 0;
2074
2075err_init_slot:
2076 /* De-init any initialized slots */
2077 while (i > 0) {
2078 if (host->slot[i])
2079 dw_mci_cleanup_slot(host->slot[i], i);
2080 i--;
2081 }
62ca8034 2082 free_irq(host->irq, host);
f95f3850 2083
1791b13e
JH		 2084err_workqueue:
2085 destroy_workqueue(dw_mci_card_workqueue);
2086
f95f3850
WN		 2087err_dmaunmap:
2088 if (host->use_dma && host->dma_ops->exit)
2089 host->dma_ops->exit(host);
62ca8034 2090 dma_free_coherent(&host->dev, PAGE_SIZE,
f95f3850 2091 host->sg_cpu, host->sg_dma);
f95f3850 2092
c07946a3
JC		 2093 if (host->vmmc) {
2094 regulator_disable(host->vmmc);
2095 regulator_put(host->vmmc);
2096 }
f95f3850
WN		 2097 return ret;
2098}
62ca8034 2099EXPORT_SYMBOL(dw_mci_probe);
f95f3850 2100
62ca8034 2101void dw_mci_remove(struct dw_mci *host)
f95f3850 2102{
f95f3850
WN		 2103 int i;
2104
2105 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2106 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2107
f95f3850 2108 for (i = 0; i < host->num_slots; i++) {
62ca8034 2109 dev_dbg(&host->dev, "remove slot %d\n", i);
f95f3850
WN		 2110 if (host->slot[i])
2111 dw_mci_cleanup_slot(host->slot[i], i);
2112 }
2113
2114 /* disable clock to CIU */
2115 mci_writel(host, CLKENA, 0);
2116 mci_writel(host, CLKSRC, 0);
2117
62ca8034 2118 free_irq(host->irq, host);
1791b13e 2119 destroy_workqueue(dw_mci_card_workqueue);
62ca8034 2120 dma_free_coherent(&host->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
f95f3850
WN		 2121
2122 if (host->use_dma && host->dma_ops->exit)
2123 host->dma_ops->exit(host);
2124
c07946a3
JC		 2125 if (host->vmmc) {
2126 regulator_disable(host->vmmc);
2127 regulator_put(host->vmmc);
2128 }
2129
f95f3850 2130}
62ca8034
SH		 2131EXPORT_SYMBOL(dw_mci_remove);
2132
2133
f95f3850 2134
6fe8890d 2135#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 2136/*
2137 * TODO: we should probably disable the clock to the card in the suspend path.
2138 */
62ca8034 2139int dw_mci_suspend(struct dw_mci *host)
f95f3850 2140{
62ca8034 2141 int i, ret = 0;
f95f3850
WN		 2142
2143 for (i = 0; i < host->num_slots; i++) {
2144 struct dw_mci_slot *slot = host->slot[i];
2145 if (!slot)
2146 continue;
2147 ret = mmc_suspend_host(slot->mmc);
2148 if (ret < 0) {
2149 while (--i >= 0) {
2150 slot = host->slot[i];
2151 if (slot)
2152 mmc_resume_host(host->slot[i]->mmc);
2153 }
2154 return ret;
2155 }
2156 }
2157
c07946a3
JC		 2158 if (host->vmmc)
2159 regulator_disable(host->vmmc);
2160
f95f3850
WN		 2161 return 0;
2162}
62ca8034 2163EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 2164
62ca8034 2165int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 2166{
2167 int i, ret;
f95f3850 2168
1d6c4e0a
JC		 2169 if (host->vmmc)
2170 regulator_enable(host->vmmc);
2171
e61cf118
JC		 2172 if (host->dma_ops->init)
2173 host->dma_ops->init(host);
2174
62ca8034 2175 if (!mci_wait_reset(&host->dev, host)) {
e61cf118
JC		 2176 ret = -ENODEV;
2177 return ret;
2178 }
2179
2180 /* Restore the old value at FIFOTH register */
2181 mci_writel(host, FIFOTH, host->fifoth_val);
2182
2183 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2184 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2185 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2186 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2187 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2188
f95f3850
WN		 2189 for (i = 0; i < host->num_slots; i++) {
2190 struct dw_mci_slot *slot = host->slot[i];
2191 if (!slot)
2192 continue;
2193 ret = mmc_resume_host(host->slot[i]->mmc);
2194 if (ret < 0)
2195 return ret;
2196 }
f95f3850
WN		 2197 return 0;
2198}
62ca8034 2199EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 2200#endif /* CONFIG_PM_SLEEP */
2201
f95f3850
WN		 2202static int __init dw_mci_init(void)
2203{
62ca8034
SH		 2204 printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2205 return 0;
f95f3850
WN		 2206}
2207
2208static void __exit dw_mci_exit(void)
2209{
f95f3850
WN		 2210}
2211
2212module_init(dw_mci_init);
2213module_exit(dw_mci_exit);
2214
2215MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2216MODULE_AUTHOR("NXP Semiconductor VietNam");
2217MODULE_AUTHOR("Imagination Technologies Ltd");
2218MODULE_LICENSE("GPL v2");
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