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mmc: core: Remove unused mmc_list_to_card() macro
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
01730558 32#include <linux/mmc/sd.h>
90c2143a 33#include <linux/mmc/sdio.h>
f95f3850
WN		 34#include <linux/mmc/dw_mmc.h>
35#include <linux/bitops.h>
c07946a3 36#include <linux/regulator/consumer.h>
1791b13e 37#include <linux/workqueue.h>
c91eab4b 38#include <linux/of.h>
55a6ceb2 39#include <linux/of_gpio.h>
bf626e55 40#include <linux/mmc/slot-gpio.h>
f95f3850
WN		 41
42#include "dw_mmc.h"
43
44/* Common flag combinations */
3f7eec62 45#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
f95f3850
WN		 46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52#define DW_MCI_SEND_STATUS 1
53#define DW_MCI_RECV_STATUS 2
54#define DW_MCI_DMA_THRESHOLD 16
55
1f44a2a5
SJ		 56#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
f95f3850 59#ifdef CONFIG_MMC_DW_IDMAC
fc79a4d6
JS		 60#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
f95f3850
WN		 65struct idmac_desc {
66 u32 des0; /* Control Descriptor */
67#define IDMAC_DES0_DIC BIT(1)
68#define IDMAC_DES0_LD BIT(2)
69#define IDMAC_DES0_FD BIT(3)
70#define IDMAC_DES0_CH BIT(4)
71#define IDMAC_DES0_ER BIT(5)
72#define IDMAC_DES0_CES BIT(30)
73#define IDMAC_DES0_OWN BIT(31)
74
75 u32 des1; /* Buffer sizes */
76#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 77 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850
WN		 78
79 u32 des2; /* buffer 1 physical address */
80
81 u32 des3; /* buffer 2 physical address */
82};
83#endif /* CONFIG_MMC_DW_IDMAC */
84
3a33a94c 85static bool dw_mci_reset(struct dw_mci *host);
31bff450 86
f95f3850
WN		 87#if defined(CONFIG_DEBUG_FS)
88static int dw_mci_req_show(struct seq_file *s, void *v)
89{
90 struct dw_mci_slot *slot = s->private;
91 struct mmc_request *mrq;
92 struct mmc_command *cmd;
93 struct mmc_command *stop;
94 struct mmc_data *data;
95
96 /* Make sure we get a consistent snapshot */
97 spin_lock_bh(&slot->host->lock);
98 mrq = slot->mrq;
99
100 if (mrq) {
101 cmd = mrq->cmd;
102 data = mrq->data;
103 stop = mrq->stop;
104
105 if (cmd)
106 seq_printf(s,
107 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
108 cmd->opcode, cmd->arg, cmd->flags,
109 cmd->resp[0], cmd->resp[1], cmd->resp[2],
110 cmd->resp[2], cmd->error);
111 if (data)
112 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
113 data->bytes_xfered, data->blocks,
114 data->blksz, data->flags, data->error);
115 if (stop)
116 seq_printf(s,
117 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
118 stop->opcode, stop->arg, stop->flags,
119 stop->resp[0], stop->resp[1], stop->resp[2],
120 stop->resp[2], stop->error);
121 }
122
123 spin_unlock_bh(&slot->host->lock);
124
125 return 0;
126}
127
128static int dw_mci_req_open(struct inode *inode, struct file *file)
129{
130 return single_open(file, dw_mci_req_show, inode->i_private);
131}
132
133static const struct file_operations dw_mci_req_fops = {
134 .owner = THIS_MODULE,
135 .open = dw_mci_req_open,
136 .read = seq_read,
137 .llseek = seq_lseek,
138 .release = single_release,
139};
140
141static int dw_mci_regs_show(struct seq_file *s, void *v)
142{
143 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
144 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
145 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
146 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
147 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
148 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
149
150 return 0;
151}
152
153static int dw_mci_regs_open(struct inode *inode, struct file *file)
154{
155 return single_open(file, dw_mci_regs_show, inode->i_private);
156}
157
158static const struct file_operations dw_mci_regs_fops = {
159 .owner = THIS_MODULE,
160 .open = dw_mci_regs_open,
161 .read = seq_read,
162 .llseek = seq_lseek,
163 .release = single_release,
164};
165
166static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
167{
168 struct mmc_host *mmc = slot->mmc;
169 struct dw_mci *host = slot->host;
170 struct dentry *root;
171 struct dentry *node;
172
173 root = mmc->debugfs_root;
174 if (!root)
175 return;
176
177 node = debugfs_create_file("regs", S_IRUSR, root, host,
178 &dw_mci_regs_fops);
179 if (!node)
180 goto err;
181
182 node = debugfs_create_file("req", S_IRUSR, root, slot,
183 &dw_mci_req_fops);
184 if (!node)
185 goto err;
186
187 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
188 if (!node)
189 goto err;
190
191 node = debugfs_create_x32("pending_events", S_IRUSR, root,
192 (u32 *)&host->pending_events);
193 if (!node)
194 goto err;
195
196 node = debugfs_create_x32("completed_events", S_IRUSR, root,
197 (u32 *)&host->completed_events);
198 if (!node)
199 goto err;
200
201 return;
202
203err:
204 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
205}
206#endif /* defined(CONFIG_DEBUG_FS) */
207
01730558
DA		 208static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
209
f95f3850
WN		 210static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
211{
212 struct mmc_data *data;
800d78bf 213 struct dw_mci_slot *slot = mmc_priv(mmc);
01730558 214 struct dw_mci *host = slot->host;
e95baf13 215 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
f95f3850
WN		 216 u32 cmdr;
217 cmd->error = -EINPROGRESS;
218
219 cmdr = cmd->opcode;
220
90c2143a
SJ		 221 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
222 cmd->opcode == MMC_GO_IDLE_STATE ||
223 cmd->opcode == MMC_GO_INACTIVE_STATE ||
224 (cmd->opcode == SD_IO_RW_DIRECT &&
225 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
f95f3850 226 cmdr |= SDMMC_CMD_STOP;
4a1b27ad
JC		 227 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
228 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
f95f3850 229
01730558
DA		 230 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
231 u32 clk_en_a;
232
233 /* Special bit makes CMD11 not die */
234 cmdr |= SDMMC_CMD_VOLT_SWITCH;
235
236 /* Change state to continue to handle CMD11 weirdness */
237 WARN_ON(slot->host->state != STATE_SENDING_CMD);
238 slot->host->state = STATE_SENDING_CMD11;
239
240 /*
241 * We need to disable low power mode (automatic clock stop)
242 * while doing voltage switch so we don't confuse the card,
243 * since stopping the clock is a specific part of the UHS
244 * voltage change dance.
245 *
246 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
247 * unconditionally turned back on in dw_mci_setup_bus() if it's
248 * ever called with a non-zero clock. That shouldn't happen
249 * until the voltage change is all done.
250 */
251 clk_en_a = mci_readl(host, CLKENA);
252 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
253 mci_writel(host, CLKENA, clk_en_a);
254 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
255 SDMMC_CMD_PRV_DAT_WAIT, 0);
256 }
257
f95f3850
WN		 258 if (cmd->flags & MMC_RSP_PRESENT) {
259 /* We expect a response, so set this bit */
260 cmdr |= SDMMC_CMD_RESP_EXP;
261 if (cmd->flags & MMC_RSP_136)
262 cmdr |= SDMMC_CMD_RESP_LONG;
263 }
264
265 if (cmd->flags & MMC_RSP_CRC)
266 cmdr |= SDMMC_CMD_RESP_CRC;
267
268 data = cmd->data;
269 if (data) {
270 cmdr |= SDMMC_CMD_DAT_EXP;
271 if (data->flags & MMC_DATA_STREAM)
272 cmdr |= SDMMC_CMD_STRM_MODE;
273 if (data->flags & MMC_DATA_WRITE)
274 cmdr |= SDMMC_CMD_DAT_WR;
275 }
276
cb27a843
JH		 277 if (drv_data && drv_data->prepare_command)
278 drv_data->prepare_command(slot->host, &cmdr);
800d78bf 279
f95f3850
WN		 280 return cmdr;
281}
282
90c2143a
SJ		 283static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
284{
285 struct mmc_command *stop;
286 u32 cmdr;
287
288 if (!cmd->data)
289 return 0;
290
291 stop = &host->stop_abort;
292 cmdr = cmd->opcode;
293 memset(stop, 0, sizeof(struct mmc_command));
294
295 if (cmdr == MMC_READ_SINGLE_BLOCK ||
296 cmdr == MMC_READ_MULTIPLE_BLOCK ||
297 cmdr == MMC_WRITE_BLOCK ||
298 cmdr == MMC_WRITE_MULTIPLE_BLOCK) {
299 stop->opcode = MMC_STOP_TRANSMISSION;
300 stop->arg = 0;
301 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
302 } else if (cmdr == SD_IO_RW_EXTENDED) {
303 stop->opcode = SD_IO_RW_DIRECT;
304 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
305 ((cmd->arg >> 28) & 0x7);
306 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
307 } else {
308 return 0;
309 }
310
311 cmdr = stop->opcode | SDMMC_CMD_STOP |
312 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
313
314 return cmdr;
315}
316
f95f3850
WN		 317static void dw_mci_start_command(struct dw_mci *host,
318 struct mmc_command *cmd, u32 cmd_flags)
319{
320 host->cmd = cmd;
4a90920c 321 dev_vdbg(host->dev,
f95f3850
WN		 322 "start command: ARGR=0x%08x CMDR=0x%08x\n",
323 cmd->arg, cmd_flags);
324
325 mci_writel(host, CMDARG, cmd->arg);
326 wmb();
327
328 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
329}
330
90c2143a 331static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
f95f3850 332{
90c2143a
SJ		 333 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
334 dw_mci_start_command(host, stop, host->stop_cmdr);
f95f3850
WN		 335}
336
337/* DMA interface functions */
338static void dw_mci_stop_dma(struct dw_mci *host)
339{
03e8cb53 340 if (host->using_dma) {
f95f3850
WN		 341 host->dma_ops->stop(host);
342 host->dma_ops->cleanup(host);
f95f3850 343 }
aa50f259
SJ		 344
345 /* Data transfer was stopped by the interrupt handler */
346 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
f95f3850
WN		 347}
348
9aa51408
SJ		 349static int dw_mci_get_dma_dir(struct mmc_data *data)
350{
351 if (data->flags & MMC_DATA_WRITE)
352 return DMA_TO_DEVICE;
353 else
354 return DMA_FROM_DEVICE;
355}
356
9beee912 357#ifdef CONFIG_MMC_DW_IDMAC
f95f3850
WN		 358static void dw_mci_dma_cleanup(struct dw_mci *host)
359{
360 struct mmc_data *data = host->data;
361
362 if (data)
9aa51408 363 if (!data->host_cookie)
4a90920c 364 dma_unmap_sg(host->dev,
9aa51408
SJ		 365 data->sg,
366 data->sg_len,
367 dw_mci_get_dma_dir(data));
f95f3850
WN		 368}
369
5ce9d961
SJ		 370static void dw_mci_idmac_reset(struct dw_mci *host)
371{
372 u32 bmod = mci_readl(host, BMOD);
373 /* Software reset of DMA */
374 bmod |= SDMMC_IDMAC_SWRESET;
375 mci_writel(host, BMOD, bmod);
376}
377
f95f3850
WN		 378static void dw_mci_idmac_stop_dma(struct dw_mci *host)
379{
380 u32 temp;
381
382 /* Disable and reset the IDMAC interface */
383 temp = mci_readl(host, CTRL);
384 temp &= ~SDMMC_CTRL_USE_IDMAC;
385 temp |= SDMMC_CTRL_DMA_RESET;
386 mci_writel(host, CTRL, temp);
387
388 /* Stop the IDMAC running */
389 temp = mci_readl(host, BMOD);
a5289a43 390 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
5ce9d961 391 temp |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 392 mci_writel(host, BMOD, temp);
393}
394
395static void dw_mci_idmac_complete_dma(struct dw_mci *host)
396{
397 struct mmc_data *data = host->data;
398
4a90920c 399 dev_vdbg(host->dev, "DMA complete\n");
f95f3850
WN		 400
401 host->dma_ops->cleanup(host);
402
403 /*
404 * If the card was removed, data will be NULL. No point in trying to
405 * send the stop command or waiting for NBUSY in this case.
406 */
407 if (data) {
408 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
409 tasklet_schedule(&host->tasklet);
410 }
411}
412
413static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
414 unsigned int sg_len)
415{
416 int i;
417 struct idmac_desc *desc = host->sg_cpu;
418
419 for (i = 0; i < sg_len; i++, desc++) {
420 unsigned int length = sg_dma_len(&data->sg[i]);
421 u32 mem_addr = sg_dma_address(&data->sg[i]);
422
423 /* Set the OWN bit and disable interrupts for this descriptor */
424 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
425
426 /* Buffer length */
427 IDMAC_SET_BUFFER1_SIZE(desc, length);
428
429 /* Physical address to DMA to/from */
430 desc->des2 = mem_addr;
431 }
432
433 /* Set first descriptor */
434 desc = host->sg_cpu;
435 desc->des0 |= IDMAC_DES0_FD;
436
437 /* Set last descriptor */
438 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
439 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
440 desc->des0 |= IDMAC_DES0_LD;
441
442 wmb();
443}
444
445static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
446{
447 u32 temp;
448
449 dw_mci_translate_sglist(host, host->data, sg_len);
450
451 /* Select IDMAC interface */
452 temp = mci_readl(host, CTRL);
453 temp |= SDMMC_CTRL_USE_IDMAC;
454 mci_writel(host, CTRL, temp);
455
456 wmb();
457
458 /* Enable the IDMAC */
459 temp = mci_readl(host, BMOD);
a5289a43 460 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 461 mci_writel(host, BMOD, temp);
462
463 /* Start it running */
464 mci_writel(host, PLDMND, 1);
465}
466
467static int dw_mci_idmac_init(struct dw_mci *host)
468{
469 struct idmac_desc *p;
897b69e7 470 int i;
f95f3850
WN		 471
472 /* Number of descriptors in the ring buffer */
473 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
474
475 /* Forward link the descriptor list */
476 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
477 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
478
479 /* Set the last descriptor as the end-of-ring descriptor */
480 p->des3 = host->sg_dma;
481 p->des0 = IDMAC_DES0_ER;
482
5ce9d961 483 dw_mci_idmac_reset(host);
141a712a 484
f95f3850 485 /* Mask out interrupts - get Tx & Rx complete only */
fc79a4d6 486 mci_writel(host, IDSTS, IDMAC_INT_CLR);
f95f3850
WN		 487 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
488 SDMMC_IDMAC_INT_TI);
489
490 /* Set the descriptor base address */
491 mci_writel(host, DBADDR, host->sg_dma);
492 return 0;
493}
494
8e2b36ea 495static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 496 .init = dw_mci_idmac_init,
497 .start = dw_mci_idmac_start_dma,
498 .stop = dw_mci_idmac_stop_dma,
499 .complete = dw_mci_idmac_complete_dma,
500 .cleanup = dw_mci_dma_cleanup,
501};
502#endif /* CONFIG_MMC_DW_IDMAC */
503
9aa51408
SJ		 504static int dw_mci_pre_dma_transfer(struct dw_mci *host,
505 struct mmc_data *data,
506 bool next)
f95f3850
WN		 507{
508 struct scatterlist *sg;
9aa51408 509 unsigned int i, sg_len;
03e8cb53 510
9aa51408
SJ		 511 if (!next && data->host_cookie)
512 return data->host_cookie;
f95f3850
WN		 513
514 /*
515 * We don't do DMA on "complex" transfers, i.e. with
516 * non-word-aligned buffers or lengths. Also, we don't bother
517 * with all the DMA setup overhead for short transfers.
518 */
519 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
520 return -EINVAL;
9aa51408 521
f95f3850
WN		 522 if (data->blksz & 3)
523 return -EINVAL;
524
525 for_each_sg(data->sg, sg, data->sg_len, i) {
526 if (sg->offset & 3 || sg->length & 3)
527 return -EINVAL;
528 }
529
4a90920c 530 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 531 data->sg,
532 data->sg_len,
533 dw_mci_get_dma_dir(data));
534 if (sg_len == 0)
535 return -EINVAL;
03e8cb53 536
9aa51408
SJ		 537 if (next)
538 data->host_cookie = sg_len;
f95f3850 539
9aa51408
SJ		 540 return sg_len;
541}
542
9aa51408
SJ		 543static void dw_mci_pre_req(struct mmc_host *mmc,
544 struct mmc_request *mrq,
545 bool is_first_req)
546{
547 struct dw_mci_slot *slot = mmc_priv(mmc);
548 struct mmc_data *data = mrq->data;
549
550 if (!slot->host->use_dma || !data)
551 return;
552
553 if (data->host_cookie) {
554 data->host_cookie = 0;
555 return;
556 }
557
558 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
559 data->host_cookie = 0;
560}
561
562static void dw_mci_post_req(struct mmc_host *mmc,
563 struct mmc_request *mrq,
564 int err)
565{
566 struct dw_mci_slot *slot = mmc_priv(mmc);
567 struct mmc_data *data = mrq->data;
568
569 if (!slot->host->use_dma || !data)
570 return;
571
572 if (data->host_cookie)
4a90920c 573 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 574 data->sg,
575 data->sg_len,
576 dw_mci_get_dma_dir(data));
577 data->host_cookie = 0;
578}
579
52426899
SJ		 580static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
581{
582#ifdef CONFIG_MMC_DW_IDMAC
583 unsigned int blksz = data->blksz;
584 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
585 u32 fifo_width = 1 << host->data_shift;
586 u32 blksz_depth = blksz / fifo_width, fifoth_val;
587 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
588 int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
589
590 tx_wmark = (host->fifo_depth) / 2;
591 tx_wmark_invers = host->fifo_depth - tx_wmark;
592
593 /*
594 * MSIZE is '1',
595 * if blksz is not a multiple of the FIFO width
596 */
597 if (blksz % fifo_width) {
598 msize = 0;
599 rx_wmark = 1;
600 goto done;
601 }
602
603 do {
604 if (!((blksz_depth % mszs[idx]) ||
605 (tx_wmark_invers % mszs[idx]))) {
606 msize = idx;
607 rx_wmark = mszs[idx] - 1;
608 break;
609 }
610 } while (--idx > 0);
611 /*
612 * If idx is '0', it won't be tried
613 * Thus, initial values are uesed
614 */
615done:
616 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
617 mci_writel(host, FIFOTH, fifoth_val);
618#endif
619}
620
f1d2736c
SJ		 621static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
622{
623 unsigned int blksz = data->blksz;
624 u32 blksz_depth, fifo_depth;
625 u16 thld_size;
626
627 WARN_ON(!(data->flags & MMC_DATA_READ));
628
629 if (host->timing != MMC_TIMING_MMC_HS200 &&
630 host->timing != MMC_TIMING_UHS_SDR104)
631 goto disable;
632
633 blksz_depth = blksz / (1 << host->data_shift);
634 fifo_depth = host->fifo_depth;
635
636 if (blksz_depth > fifo_depth)
637 goto disable;
638
639 /*
640 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
641 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
642 * Currently just choose blksz.
643 */
644 thld_size = blksz;
645 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
646 return;
647
648disable:
649 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
650}
651
9aa51408
SJ		 652static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
653{
654 int sg_len;
655 u32 temp;
656
657 host->using_dma = 0;
658
659 /* If we don't have a channel, we can't do DMA */
660 if (!host->use_dma)
661 return -ENODEV;
662
663 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 664 if (sg_len < 0) {
665 host->dma_ops->stop(host);
9aa51408 666 return sg_len;
a99aa9b9 667 }
9aa51408
SJ		 668
669 host->using_dma = 1;
f95f3850 670
4a90920c 671 dev_vdbg(host->dev,
f95f3850
WN		 672 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
673 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
674 sg_len);
675
52426899
SJ		 676 /*
677 * Decide the MSIZE and RX/TX Watermark.
678 * If current block size is same with previous size,
679 * no need to update fifoth.
680 */
681 if (host->prev_blksz != data->blksz)
682 dw_mci_adjust_fifoth(host, data);
683
f95f3850
WN		 684 /* Enable the DMA interface */
685 temp = mci_readl(host, CTRL);
686 temp |= SDMMC_CTRL_DMA_ENABLE;
687 mci_writel(host, CTRL, temp);
688
689 /* Disable RX/TX IRQs, let DMA handle it */
690 temp = mci_readl(host, INTMASK);
691 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
692 mci_writel(host, INTMASK, temp);
693
694 host->dma_ops->start(host, sg_len);
695
696 return 0;
697}
698
699static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
700{
701 u32 temp;
702
703 data->error = -EINPROGRESS;
704
705 WARN_ON(host->data);
706 host->sg = NULL;
707 host->data = data;
708
f1d2736c 709 if (data->flags & MMC_DATA_READ) {
55c5efbc 710 host->dir_status = DW_MCI_RECV_STATUS;
f1d2736c
SJ		 711 dw_mci_ctrl_rd_thld(host, data);
712 } else {
55c5efbc 713 host->dir_status = DW_MCI_SEND_STATUS;
f1d2736c 714 }
55c5efbc 715
f95f3850 716 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 717 int flags = SG_MITER_ATOMIC;
718 if (host->data->flags & MMC_DATA_READ)
719 flags |= SG_MITER_TO_SG;
720 else
721 flags |= SG_MITER_FROM_SG;
722
723 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 724 host->sg = data->sg;
34b664a2
JH		 725 host->part_buf_start = 0;
726 host->part_buf_count = 0;
f95f3850 727
b40af3aa 728 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 729 temp = mci_readl(host, INTMASK);
730 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
731 mci_writel(host, INTMASK, temp);
732
733 temp = mci_readl(host, CTRL);
734 temp &= ~SDMMC_CTRL_DMA_ENABLE;
735 mci_writel(host, CTRL, temp);
52426899
SJ		 736
737 /*
738 * Use the initial fifoth_val for PIO mode.
739 * If next issued data may be transfered by DMA mode,
740 * prev_blksz should be invalidated.
741 */
742 mci_writel(host, FIFOTH, host->fifoth_val);
743 host->prev_blksz = 0;
744 } else {
745 /*
746 * Keep the current block size.
747 * It will be used to decide whether to update
748 * fifoth register next time.
749 */
750 host->prev_blksz = data->blksz;
f95f3850
WN		 751 }
752}
753
754static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
755{
756 struct dw_mci *host = slot->host;
757 unsigned long timeout = jiffies + msecs_to_jiffies(500);
758 unsigned int cmd_status = 0;
759
760 mci_writel(host, CMDARG, arg);
761 wmb();
762 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
763
764 while (time_before(jiffies, timeout)) {
765 cmd_status = mci_readl(host, CMD);
766 if (!(cmd_status & SDMMC_CMD_START))
767 return;
768 }
769 dev_err(&slot->mmc->class_dev,
770 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
771 cmd, arg, cmd_status);
772}
773
ab269128 774static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 775{
776 struct dw_mci *host = slot->host;
fdf492a1 777 unsigned int clock = slot->clock;
f95f3850 778 u32 div;
9623b5b9 779 u32 clk_en_a;
01730558
DA		 780 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
781
782 /* We must continue to set bit 28 in CMD until the change is complete */
783 if (host->state == STATE_WAITING_CMD11_DONE)
784 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
f95f3850 785
fdf492a1
DA		 786 if (!clock) {
787 mci_writel(host, CLKENA, 0);
01730558 788 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
fdf492a1
DA		 789 } else if (clock != host->current_speed || force_clkinit) {
790 div = host->bus_hz / clock;
791 if (host->bus_hz % clock && host->bus_hz > clock)
f95f3850
WN		 792 /*
793 * move the + 1 after the divide to prevent
794 * over-clocking the card.
795 */
e419990b
SJ		 796 div += 1;
797
fdf492a1 798 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850 799
fdf492a1
DA		 800 if ((clock << div) != slot->__clk_old || force_clkinit)
801 dev_info(&slot->mmc->class_dev,
802 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
803 slot->id, host->bus_hz, clock,
804 div ? ((host->bus_hz / div) >> 1) :
805 host->bus_hz, div);
f95f3850
WN		 806
807 /* disable clock */
808 mci_writel(host, CLKENA, 0);
809 mci_writel(host, CLKSRC, 0);
810
811 /* inform CIU */
01730558 812 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850
WN		 813
814 /* set clock to desired speed */
815 mci_writel(host, CLKDIV, div);
816
817 /* inform CIU */
01730558 818 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 819
9623b5b9
DA		 820 /* enable clock; only low power if no SDIO */
821 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
822 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
823 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
824 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 825
826 /* inform CIU */
01730558 827 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 828
fdf492a1
DA		 829 /* keep the clock with reflecting clock dividor */
830 slot->__clk_old = clock << div;
f95f3850
WN		 831 }
832
fdf492a1
DA		 833 host->current_speed = clock;
834
f95f3850 835 /* Set the current slot bus width */
1d56c453 836 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 837}
838
053b3ce6
SJ		 839static void __dw_mci_start_request(struct dw_mci *host,
840 struct dw_mci_slot *slot,
841 struct mmc_command *cmd)
f95f3850
WN		 842{
843 struct mmc_request *mrq;
f95f3850
WN		 844 struct mmc_data *data;
845 u32 cmdflags;
846
847 mrq = slot->mrq;
f95f3850 848
f95f3850
WN		 849 host->cur_slot = slot;
850 host->mrq = mrq;
851
852 host->pending_events = 0;
853 host->completed_events = 0;
e352c813 854 host->cmd_status = 0;
f95f3850 855 host->data_status = 0;
e352c813 856 host->dir_status = 0;
f95f3850 857
053b3ce6 858 data = cmd->data;
f95f3850 859 if (data) {
f16afa88 860 mci_writel(host, TMOUT, 0xFFFFFFFF);
f95f3850
WN		 861 mci_writel(host, BYTCNT, data->blksz*data->blocks);
862 mci_writel(host, BLKSIZ, data->blksz);
863 }
864
f95f3850
WN		 865 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
866
867 /* this is the first command, send the initialization clock */
868 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
869 cmdflags |= SDMMC_CMD_INIT;
870
871 if (data) {
872 dw_mci_submit_data(host, data);
873 wmb();
874 }
875
876 dw_mci_start_command(host, cmd, cmdflags);
877
878 if (mrq->stop)
879 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
90c2143a
SJ		 880 else
881 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
f95f3850
WN		 882}
883
053b3ce6
SJ		 884static void dw_mci_start_request(struct dw_mci *host,
885 struct dw_mci_slot *slot)
886{
887 struct mmc_request *mrq = slot->mrq;
888 struct mmc_command *cmd;
889
890 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
891 __dw_mci_start_request(host, slot, cmd);
892}
893
7456caae 894/* must be called with host->lock held */
f95f3850
WN		 895static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
896 struct mmc_request *mrq)
897{
898 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
899 host->state);
900
f95f3850
WN		 901 slot->mrq = mrq;
902
01730558
DA		 903 if (host->state == STATE_WAITING_CMD11_DONE) {
904 dev_warn(&slot->mmc->class_dev,
905 "Voltage change didn't complete\n");
906 /*
907 * this case isn't expected to happen, so we can
908 * either crash here or just try to continue on
909 * in the closest possible state
910 */
911 host->state = STATE_IDLE;
912 }
913
f95f3850
WN		 914 if (host->state == STATE_IDLE) {
915 host->state = STATE_SENDING_CMD;
916 dw_mci_start_request(host, slot);
917 } else {
918 list_add_tail(&slot->queue_node, &host->queue);
919 }
f95f3850
WN		 920}
921
922static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
923{
924 struct dw_mci_slot *slot = mmc_priv(mmc);
925 struct dw_mci *host = slot->host;
926
927 WARN_ON(slot->mrq);
928
7456caae
JH		 929 /*
930 * The check for card presence and queueing of the request must be
931 * atomic, otherwise the card could be removed in between and the
932 * request wouldn't fail until another card was inserted.
933 */
934 spin_lock_bh(&host->lock);
935
f95f3850 936 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 937 spin_unlock_bh(&host->lock);
f95f3850
WN		 938 mrq->cmd->error = -ENOMEDIUM;
939 mmc_request_done(mmc, mrq);
940 return;
941 }
942
f95f3850 943 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 944
945 spin_unlock_bh(&host->lock);
f95f3850
WN		 946}
947
948static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
949{
950 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 951 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 952 u32 regs;
51da2240 953 int ret;
f95f3850 954
f95f3850 955 switch (ios->bus_width) {
f95f3850
WN		 956 case MMC_BUS_WIDTH_4:
957 slot->ctype = SDMMC_CTYPE_4BIT;
958 break;
c9b2a06f
JC		 959 case MMC_BUS_WIDTH_8:
960 slot->ctype = SDMMC_CTYPE_8BIT;
961 break;
b2f7cb45
JC		 962 default:
963 /* set default 1 bit mode */
964 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 965 }
966
3f514291
SJ		 967 regs = mci_readl(slot->host, UHS_REG);
968
41babf75 969 /* DDR mode set */
cab3a802 970 if (ios->timing == MMC_TIMING_MMC_DDR52)
c69042a5 971 regs |= ((0x1 << slot->id) << 16);
3f514291 972 else
c69042a5 973 regs &= ~((0x1 << slot->id) << 16);
3f514291
SJ		 974
975 mci_writel(slot->host, UHS_REG, regs);
f1d2736c 976 slot->host->timing = ios->timing;
41babf75 977
fdf492a1
DA		 978 /*
979 * Use mirror of ios->clock to prevent race with mmc
980 * core ios update when finding the minimum.
981 */
982 slot->clock = ios->clock;
f95f3850 983
cb27a843
JH		 984 if (drv_data && drv_data->set_ios)
985 drv_data->set_ios(slot->host, ios);
800d78bf 986
bf7cb224
JC		 987 /* Slot specific timing and width adjustment */
988 dw_mci_setup_bus(slot, false);
989
01730558
DA		 990 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
991 slot->host->state = STATE_IDLE;
992
f95f3850
WN		 993 switch (ios->power_mode) {
994 case MMC_POWER_UP:
51da2240
YC		 995 if (!IS_ERR(mmc->supply.vmmc)) {
996 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
997 ios->vdd);
998 if (ret) {
999 dev_err(slot->host->dev,
1000 "failed to enable vmmc regulator\n");
1001 /*return, if failed turn on vmmc*/
1002 return;
1003 }
1004 }
1005 if (!IS_ERR(mmc->supply.vqmmc) && !slot->host->vqmmc_enabled) {
1006 ret = regulator_enable(mmc->supply.vqmmc);
1007 if (ret < 0)
1008 dev_err(slot->host->dev,
1009 "failed to enable vqmmc regulator\n");
1010 else
1011 slot->host->vqmmc_enabled = true;
1012 }
f95f3850 1013 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
4366dcc5
JC		 1014 regs = mci_readl(slot->host, PWREN);
1015 regs |= (1 << slot->id);
1016 mci_writel(slot->host, PWREN, regs);
e6f34e2f
JH		 1017 break;
1018 case MMC_POWER_OFF:
51da2240
YC		 1019 if (!IS_ERR(mmc->supply.vmmc))
1020 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1021
1022 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) {
1023 regulator_disable(mmc->supply.vqmmc);
1024 slot->host->vqmmc_enabled = false;
1025 }
1026
4366dcc5
JC		 1027 regs = mci_readl(slot->host, PWREN);
1028 regs &= ~(1 << slot->id);
1029 mci_writel(slot->host, PWREN, regs);
f95f3850
WN		 1030 break;
1031 default:
1032 break;
1033 }
1034}
1035
01730558
DA		 1036static int dw_mci_card_busy(struct mmc_host *mmc)
1037{
1038 struct dw_mci_slot *slot = mmc_priv(mmc);
1039 u32 status;
1040
1041 /*
1042 * Check the busy bit which is low when DAT[3:0]
1043 * (the data lines) are 0000
1044 */
1045 status = mci_readl(slot->host, STATUS);
1046
1047 return !!(status & SDMMC_STATUS_BUSY);
1048}
1049
1050static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1051{
1052 struct dw_mci_slot *slot = mmc_priv(mmc);
1053 struct dw_mci *host = slot->host;
1054 u32 uhs;
1055 u32 v18 = SDMMC_UHS_18V << slot->id;
1056 int min_uv, max_uv;
1057 int ret;
1058
1059 /*
1060 * Program the voltage. Note that some instances of dw_mmc may use
1061 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1062 * does no harm but you need to set the regulator directly. Try both.
1063 */
1064 uhs = mci_readl(host, UHS_REG);
1065 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
1066 min_uv = 2700000;
1067 max_uv = 3600000;
1068 uhs &= ~v18;
1069 } else {
1070 min_uv = 1700000;
1071 max_uv = 1950000;
1072 uhs |= v18;
1073 }
1074 if (!IS_ERR(mmc->supply.vqmmc)) {
1075 ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv);
1076
1077 if (ret) {
1078 dev_err(&mmc->class_dev,
1079 "Regulator set error %d: %d - %d\n",
1080 ret, min_uv, max_uv);
1081 return ret;
1082 }
1083 }
1084 mci_writel(host, UHS_REG, uhs);
1085
1086 return 0;
1087}
1088
f95f3850
WN		 1089static int dw_mci_get_ro(struct mmc_host *mmc)
1090{
1091 int read_only;
1092 struct dw_mci_slot *slot = mmc_priv(mmc);
9795a846 1093 int gpio_ro = mmc_gpio_get_ro(mmc);
f95f3850
WN		 1094
1095 /* Use platform get_ro function, else try on board write protect */
26375b5c
JC		 1096 if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) ||
1097 (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT))
b4967aa5 1098 read_only = 0;
9795a846
JC		 1099 else if (!IS_ERR_VALUE(gpio_ro))
1100 read_only = gpio_ro;
f95f3850
WN		 1101 else
1102 read_only =
1103 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1104
1105 dev_dbg(&mmc->class_dev, "card is %s\n",
1106 read_only ? "read-only" : "read-write");
1107
1108 return read_only;
1109}
1110
1111static int dw_mci_get_cd(struct mmc_host *mmc)
1112{
1113 int present;
1114 struct dw_mci_slot *slot = mmc_priv(mmc);
1115 struct dw_mci_board *brd = slot->host->pdata;
7cf347bd
ZG		 1116 struct dw_mci *host = slot->host;
1117 int gpio_cd = mmc_gpio_get_cd(mmc);
f95f3850
WN		 1118
1119 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 1120 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
1121 present = 1;
bf626e55 1122 else if (!IS_ERR_VALUE(gpio_cd))
7cf347bd 1123 present = gpio_cd;
f95f3850
WN		 1124 else
1125 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1126 == 0 ? 1 : 0;
1127
7cf347bd 1128 spin_lock_bh(&host->lock);
bf626e55
ZG		 1129 if (present) {
1130 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1131 dev_dbg(&mmc->class_dev, "card is present\n");
bf626e55
ZG		 1132 } else {
1133 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1134 dev_dbg(&mmc->class_dev, "card is not present\n");
bf626e55 1135 }
7cf347bd 1136 spin_unlock_bh(&host->lock);
f95f3850
WN		 1137
1138 return present;
1139}
1140
9623b5b9
DA		 1141/*
1142 * Disable lower power mode.
1143 *
1144 * Low power mode will stop the card clock when idle. According to the
1145 * description of the CLKENA register we should disable low power mode
1146 * for SDIO cards if we need SDIO interrupts to work.
1147 *
1148 * This function is fast if low power mode is already disabled.
1149 */
1150static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
1151{
1152 struct dw_mci *host = slot->host;
1153 u32 clk_en_a;
1154 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1155
1156 clk_en_a = mci_readl(host, CLKENA);
1157
1158 if (clk_en_a & clken_low_pwr) {
1159 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
1160 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1161 SDMMC_CMD_PRV_DAT_WAIT, 0);
1162 }
1163}
1164
1a5c8e1f
SH		 1165static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1166{
1167 struct dw_mci_slot *slot = mmc_priv(mmc);
1168 struct dw_mci *host = slot->host;
1169 u32 int_mask;
1170
1171 /* Enable/disable Slot Specific SDIO interrupt */
1172 int_mask = mci_readl(host, INTMASK);
1173 if (enb) {
9623b5b9
DA		 1174 /*
1175 * Turn off low power mode if it was enabled. This is a bit of
1176 * a heavy operation and we disable / enable IRQs a lot, so
1177 * we'll leave low power mode disabled and it will get
1178 * re-enabled again in dw_mci_setup_bus().
1179 */
1180 dw_mci_disable_low_power(slot);
1181
1a5c8e1f 1182 mci_writel(host, INTMASK,
705ad047 1183 (int_mask | SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 1184 } else {
1185 mci_writel(host, INTMASK,
705ad047 1186 (int_mask & ~SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 1187 }
1188}
1189
0976f16d
SJ		 1190static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1191{
1192 struct dw_mci_slot *slot = mmc_priv(mmc);
1193 struct dw_mci *host = slot->host;
1194 const struct dw_mci_drv_data *drv_data = host->drv_data;
1195 struct dw_mci_tuning_data tuning_data;
1196 int err = -ENOSYS;
1197
1198 if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1199 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
1200 tuning_data.blk_pattern = tuning_blk_pattern_8bit;
1201 tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
1202 } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
1203 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1204 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1205 } else {
1206 return -EINVAL;
1207 }
1208 } else if (opcode == MMC_SEND_TUNING_BLOCK) {
1209 tuning_data.blk_pattern = tuning_blk_pattern_4bit;
1210 tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
1211 } else {
1212 dev_err(host->dev,
1213 "Undefined command(%d) for tuning\n", opcode);
1214 return -EINVAL;
1215 }
1216
1217 if (drv_data && drv_data->execute_tuning)
1218 err = drv_data->execute_tuning(slot, opcode, &tuning_data);
1219 return err;
1220}
1221
f95f3850 1222static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 1223 .request = dw_mci_request,
9aa51408
SJ		 1224 .pre_req = dw_mci_pre_req,
1225 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 1226 .set_ios = dw_mci_set_ios,
1227 .get_ro = dw_mci_get_ro,
1228 .get_cd = dw_mci_get_cd,
1229 .enable_sdio_irq = dw_mci_enable_sdio_irq,
0976f16d 1230 .execute_tuning = dw_mci_execute_tuning,
01730558
DA		 1231 .card_busy = dw_mci_card_busy,
1232 .start_signal_voltage_switch = dw_mci_switch_voltage,
1233
f95f3850
WN		 1234};
1235
1236static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1237 __releases(&host->lock)
1238 __acquires(&host->lock)
1239{
1240 struct dw_mci_slot *slot;
1241 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1242
1243 WARN_ON(host->cmd || host->data);
1244
1245 host->cur_slot->mrq = NULL;
1246 host->mrq = NULL;
1247 if (!list_empty(&host->queue)) {
1248 slot = list_entry(host->queue.next,
1249 struct dw_mci_slot, queue_node);
1250 list_del(&slot->queue_node);
4a90920c 1251 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 1252 mmc_hostname(slot->mmc));
1253 host->state = STATE_SENDING_CMD;
1254 dw_mci_start_request(host, slot);
1255 } else {
4a90920c 1256 dev_vdbg(host->dev, "list empty\n");
01730558
DA		 1257
1258 if (host->state == STATE_SENDING_CMD11)
1259 host->state = STATE_WAITING_CMD11_DONE;
1260 else
1261 host->state = STATE_IDLE;
f95f3850
WN		 1262 }
1263
1264 spin_unlock(&host->lock);
1265 mmc_request_done(prev_mmc, mrq);
1266 spin_lock(&host->lock);
1267}
1268
e352c813 1269static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
f95f3850
WN		 1270{
1271 u32 status = host->cmd_status;
1272
1273 host->cmd_status = 0;
1274
1275 /* Read the response from the card (up to 16 bytes) */
1276 if (cmd->flags & MMC_RSP_PRESENT) {
1277 if (cmd->flags & MMC_RSP_136) {
1278 cmd->resp[3] = mci_readl(host, RESP0);
1279 cmd->resp[2] = mci_readl(host, RESP1);
1280 cmd->resp[1] = mci_readl(host, RESP2);
1281 cmd->resp[0] = mci_readl(host, RESP3);
1282 } else {
1283 cmd->resp[0] = mci_readl(host, RESP0);
1284 cmd->resp[1] = 0;
1285 cmd->resp[2] = 0;
1286 cmd->resp[3] = 0;
1287 }
1288 }
1289
1290 if (status & SDMMC_INT_RTO)
1291 cmd->error = -ETIMEDOUT;
1292 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1293 cmd->error = -EILSEQ;
1294 else if (status & SDMMC_INT_RESP_ERR)
1295 cmd->error = -EIO;
1296 else
1297 cmd->error = 0;
1298
1299 if (cmd->error) {
1300 /* newer ip versions need a delay between retries */
1301 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1302 mdelay(20);
f95f3850 1303 }
e352c813
SJ		 1304
1305 return cmd->error;
1306}
1307
1308static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1309{
31bff450 1310 u32 status = host->data_status;
e352c813
SJ		 1311
1312 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1313 if (status & SDMMC_INT_DRTO) {
1314 data->error = -ETIMEDOUT;
1315 } else if (status & SDMMC_INT_DCRC) {
1316 data->error = -EILSEQ;
1317 } else if (status & SDMMC_INT_EBE) {
1318 if (host->dir_status ==
1319 DW_MCI_SEND_STATUS) {
1320 /*
1321 * No data CRC status was returned.
1322 * The number of bytes transferred
1323 * will be exaggerated in PIO mode.
1324 */
1325 data->bytes_xfered = 0;
1326 data->error = -ETIMEDOUT;
1327 } else if (host->dir_status ==
1328 DW_MCI_RECV_STATUS) {
1329 data->error = -EIO;
1330 }
1331 } else {
1332 /* SDMMC_INT_SBE is included */
1333 data->error = -EIO;
1334 }
1335
e6cc0123 1336 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
e352c813
SJ		 1337
1338 /*
1339 * After an error, there may be data lingering
31bff450 1340 * in the FIFO
e352c813 1341 */
3a33a94c 1342 dw_mci_reset(host);
e352c813
SJ		 1343 } else {
1344 data->bytes_xfered = data->blocks * data->blksz;
1345 data->error = 0;
1346 }
1347
1348 return data->error;
f95f3850
WN		 1349}
1350
1351static void dw_mci_tasklet_func(unsigned long priv)
1352{
1353 struct dw_mci *host = (struct dw_mci *)priv;
1354 struct mmc_data *data;
1355 struct mmc_command *cmd;
e352c813 1356 struct mmc_request *mrq;
f95f3850
WN		 1357 enum dw_mci_state state;
1358 enum dw_mci_state prev_state;
e352c813 1359 unsigned int err;
f95f3850
WN		 1360
1361 spin_lock(&host->lock);
1362
1363 state = host->state;
1364 data = host->data;
e352c813 1365 mrq = host->mrq;
f95f3850
WN		 1366
1367 do {
1368 prev_state = state;
1369
1370 switch (state) {
1371 case STATE_IDLE:
01730558 1372 case STATE_WAITING_CMD11_DONE:
f95f3850
WN		 1373 break;
1374
01730558 1375 case STATE_SENDING_CMD11:
f95f3850
WN		 1376 case STATE_SENDING_CMD:
1377 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1378 &host->pending_events))
1379 break;
1380
1381 cmd = host->cmd;
1382 host->cmd = NULL;
1383 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
e352c813
SJ		 1384 err = dw_mci_command_complete(host, cmd);
1385 if (cmd == mrq->sbc && !err) {
053b3ce6
SJ		 1386 prev_state = state = STATE_SENDING_CMD;
1387 __dw_mci_start_request(host, host->cur_slot,
e352c813 1388 mrq->cmd);
053b3ce6
SJ		 1389 goto unlock;
1390 }
1391
e352c813 1392 if (cmd->data && err) {
71abb133 1393 dw_mci_stop_dma(host);
90c2143a
SJ		 1394 send_stop_abort(host, data);
1395 state = STATE_SENDING_STOP;
1396 break;
71abb133
SJ		 1397 }
1398
e352c813
SJ		 1399 if (!cmd->data || err) {
1400 dw_mci_request_end(host, mrq);
f95f3850
WN		 1401 goto unlock;
1402 }
1403
1404 prev_state = state = STATE_SENDING_DATA;
1405 /* fall through */
1406
1407 case STATE_SENDING_DATA:
2aa35465
DA		 1408 /*
1409 * We could get a data error and never a transfer
1410 * complete so we'd better check for it here.
1411 *
1412 * Note that we don't really care if we also got a
1413 * transfer complete; stopping the DMA and sending an
1414 * abort won't hurt.
1415 */
f95f3850
WN		 1416 if (test_and_clear_bit(EVENT_DATA_ERROR,
1417 &host->pending_events)) {
1418 dw_mci_stop_dma(host);
90c2143a 1419 send_stop_abort(host, data);
f95f3850
WN		 1420 state = STATE_DATA_ERROR;
1421 break;
1422 }
1423
1424 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1425 &host->pending_events))
1426 break;
1427
1428 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2aa35465
DA		 1429
1430 /*
1431 * Handle an EVENT_DATA_ERROR that might have shown up
1432 * before the transfer completed. This might not have
1433 * been caught by the check above because the interrupt
1434 * could have gone off between the previous check and
1435 * the check for transfer complete.
1436 *
1437 * Technically this ought not be needed assuming we
1438 * get a DATA_COMPLETE eventually (we'll notice the
1439 * error and end the request), but it shouldn't hurt.
1440 *
1441 * This has the advantage of sending the stop command.
1442 */
1443 if (test_and_clear_bit(EVENT_DATA_ERROR,
1444 &host->pending_events)) {
1445 dw_mci_stop_dma(host);
1446 send_stop_abort(host, data);
1447 state = STATE_DATA_ERROR;
1448 break;
1449 }
f95f3850 1450 prev_state = state = STATE_DATA_BUSY;
2aa35465 1451
f95f3850
WN		 1452 /* fall through */
1453
1454 case STATE_DATA_BUSY:
1455 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1456 &host->pending_events))
1457 break;
1458
1459 host->data = NULL;
1460 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
e352c813
SJ		 1461 err = dw_mci_data_complete(host, data);
1462
1463 if (!err) {
1464 if (!data->stop || mrq->sbc) {
17c8bc85 1465 if (mrq->sbc && data->stop)
e352c813
SJ		 1466 data->stop->error = 0;
1467 dw_mci_request_end(host, mrq);
1468 goto unlock;
f95f3850 1469 }
f95f3850 1470
e352c813
SJ		 1471 /* stop command for open-ended transfer*/
1472 if (data->stop)
1473 send_stop_abort(host, data);
2aa35465
DA		 1474 } else {
1475 /*
1476 * If we don't have a command complete now we'll
1477 * never get one since we just reset everything;
1478 * better end the request.
1479 *
1480 * If we do have a command complete we'll fall
1481 * through to the SENDING_STOP command and
1482 * everything will be peachy keen.
1483 */
1484 if (!test_bit(EVENT_CMD_COMPLETE,
1485 &host->pending_events)) {
1486 host->cmd = NULL;
1487 dw_mci_request_end(host, mrq);
1488 goto unlock;
1489 }
053b3ce6
SJ		 1490 }
1491
e352c813
SJ		 1492 /*
1493 * If err has non-zero,
1494 * stop-abort command has been already issued.
1495 */
f95f3850 1496 prev_state = state = STATE_SENDING_STOP;
e352c813 1497
f95f3850
WN		 1498 /* fall through */
1499
1500 case STATE_SENDING_STOP:
1501 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1502 &host->pending_events))
1503 break;
1504
71abb133 1505 /* CMD error in data command */
31bff450 1506 if (mrq->cmd->error && mrq->data)
3a33a94c 1507 dw_mci_reset(host);
71abb133 1508
f95f3850 1509 host->cmd = NULL;
71abb133 1510 host->data = NULL;
90c2143a 1511
e352c813
SJ		 1512 if (mrq->stop)
1513 dw_mci_command_complete(host, mrq->stop);
90c2143a
SJ		 1514 else
1515 host->cmd_status = 0;
1516
e352c813 1517 dw_mci_request_end(host, mrq);
f95f3850
WN		 1518 goto unlock;
1519
1520 case STATE_DATA_ERROR:
1521 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1522 &host->pending_events))
1523 break;
1524
1525 state = STATE_DATA_BUSY;
1526 break;
1527 }
1528 } while (state != prev_state);
1529
1530 host->state = state;
1531unlock:
1532 spin_unlock(&host->lock);
1533
1534}
1535
34b664a2
JH		 1536/* push final bytes to part_buf, only use during push */
1537static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1538{
34b664a2
JH		 1539 memcpy((void *)&host->part_buf, buf, cnt);
1540 host->part_buf_count = cnt;
1541}
f95f3850 1542
34b664a2
JH		 1543/* append bytes to part_buf, only use during push */
1544static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1545{
1546 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1547 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1548 host->part_buf_count += cnt;
1549 return cnt;
1550}
f95f3850 1551
34b664a2
JH		 1552/* pull first bytes from part_buf, only use during pull */
1553static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1554{
1555 cnt = min(cnt, (int)host->part_buf_count);
1556 if (cnt) {
1557 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1558 cnt);
1559 host->part_buf_count -= cnt;
1560 host->part_buf_start += cnt;
f95f3850 1561 }
34b664a2 1562 return cnt;
f95f3850
WN		 1563}
1564
34b664a2
JH		 1565/* pull final bytes from the part_buf, assuming it's just been filled */
1566static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1567{
34b664a2
JH		 1568 memcpy(buf, &host->part_buf, cnt);
1569 host->part_buf_start = cnt;
1570 host->part_buf_count = (1 << host->data_shift) - cnt;
1571}
f95f3850 1572
34b664a2
JH		 1573static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1574{
cfbeb59c
MC		 1575 struct mmc_data *data = host->data;
1576 int init_cnt = cnt;
1577
34b664a2
JH		 1578 /* try and push anything in the part_buf */
1579 if (unlikely(host->part_buf_count)) {
1580 int len = dw_mci_push_part_bytes(host, buf, cnt);
1581 buf += len;
1582 cnt -= len;
cfbeb59c 1583 if (host->part_buf_count == 2) {
4e0a5adf
JC		 1584 mci_writew(host, DATA(host->data_offset),
1585 host->part_buf16);
34b664a2
JH		 1586 host->part_buf_count = 0;
1587 }
1588 }
1589#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1590 if (unlikely((unsigned long)buf & 0x1)) {
1591 while (cnt >= 2) {
1592 u16 aligned_buf[64];
1593 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1594 int items = len >> 1;
1595 int i;
1596 /* memcpy from input buffer into aligned buffer */
1597 memcpy(aligned_buf, buf, len);
1598 buf += len;
1599 cnt -= len;
1600 /* push data from aligned buffer into fifo */
1601 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1602 mci_writew(host, DATA(host->data_offset),
1603 aligned_buf[i]);
34b664a2
JH		 1604 }
1605 } else
1606#endif
1607 {
1608 u16 *pdata = buf;
1609 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1610 mci_writew(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1611 buf = pdata;
1612 }
1613 /* put anything remaining in the part_buf */
1614 if (cnt) {
1615 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 1616 /* Push data if we have reached the expected data length */
1617 if ((data->bytes_xfered + init_cnt) ==
1618 (data->blksz * data->blocks))
4e0a5adf 1619 mci_writew(host, DATA(host->data_offset),
cfbeb59c 1620 host->part_buf16);
34b664a2
JH		 1621 }
1622}
f95f3850 1623
34b664a2
JH		 1624static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1625{
1626#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1627 if (unlikely((unsigned long)buf & 0x1)) {
1628 while (cnt >= 2) {
1629 /* pull data from fifo into aligned buffer */
1630 u16 aligned_buf[64];
1631 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1632 int items = len >> 1;
1633 int i;
1634 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1635 aligned_buf[i] = mci_readw(host,
1636 DATA(host->data_offset));
34b664a2
JH		 1637 /* memcpy from aligned buffer into output buffer */
1638 memcpy(buf, aligned_buf, len);
1639 buf += len;
1640 cnt -= len;
1641 }
1642 } else
1643#endif
1644 {
1645 u16 *pdata = buf;
1646 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1647 *pdata++ = mci_readw(host, DATA(host->data_offset));
34b664a2
JH		 1648 buf = pdata;
1649 }
1650 if (cnt) {
4e0a5adf 1651 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
34b664a2 1652 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1653 }
1654}
1655
1656static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1657{
cfbeb59c
MC		 1658 struct mmc_data *data = host->data;
1659 int init_cnt = cnt;
1660
34b664a2
JH		 1661 /* try and push anything in the part_buf */
1662 if (unlikely(host->part_buf_count)) {
1663 int len = dw_mci_push_part_bytes(host, buf, cnt);
1664 buf += len;
1665 cnt -= len;
cfbeb59c 1666 if (host->part_buf_count == 4) {
4e0a5adf
JC		 1667 mci_writel(host, DATA(host->data_offset),
1668 host->part_buf32);
34b664a2
JH		 1669 host->part_buf_count = 0;
1670 }
1671 }
1672#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1673 if (unlikely((unsigned long)buf & 0x3)) {
1674 while (cnt >= 4) {
1675 u32 aligned_buf[32];
1676 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1677 int items = len >> 2;
1678 int i;
1679 /* memcpy from input buffer into aligned buffer */
1680 memcpy(aligned_buf, buf, len);
1681 buf += len;
1682 cnt -= len;
1683 /* push data from aligned buffer into fifo */
1684 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1685 mci_writel(host, DATA(host->data_offset),
1686 aligned_buf[i]);
34b664a2
JH		 1687 }
1688 } else
1689#endif
1690 {
1691 u32 *pdata = buf;
1692 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1693 mci_writel(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1694 buf = pdata;
1695 }
1696 /* put anything remaining in the part_buf */
1697 if (cnt) {
1698 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 1699 /* Push data if we have reached the expected data length */
1700 if ((data->bytes_xfered + init_cnt) ==
1701 (data->blksz * data->blocks))
4e0a5adf 1702 mci_writel(host, DATA(host->data_offset),
cfbeb59c 1703 host->part_buf32);
f95f3850
WN		 1704 }
1705}
1706
1707static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1708{
34b664a2
JH		 1709#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1710 if (unlikely((unsigned long)buf & 0x3)) {
1711 while (cnt >= 4) {
1712 /* pull data from fifo into aligned buffer */
1713 u32 aligned_buf[32];
1714 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1715 int items = len >> 2;
1716 int i;
1717 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1718 aligned_buf[i] = mci_readl(host,
1719 DATA(host->data_offset));
34b664a2
JH		 1720 /* memcpy from aligned buffer into output buffer */
1721 memcpy(buf, aligned_buf, len);
1722 buf += len;
1723 cnt -= len;
1724 }
1725 } else
1726#endif
1727 {
1728 u32 *pdata = buf;
1729 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1730 *pdata++ = mci_readl(host, DATA(host->data_offset));
34b664a2
JH		 1731 buf = pdata;
1732 }
1733 if (cnt) {
4e0a5adf 1734 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
34b664a2 1735 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1736 }
1737}
1738
1739static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1740{
cfbeb59c
MC		 1741 struct mmc_data *data = host->data;
1742 int init_cnt = cnt;
1743
34b664a2
JH		 1744 /* try and push anything in the part_buf */
1745 if (unlikely(host->part_buf_count)) {
1746 int len = dw_mci_push_part_bytes(host, buf, cnt);
1747 buf += len;
1748 cnt -= len;
c09fbd74 1749
cfbeb59c 1750 if (host->part_buf_count == 8) {
c09fbd74 1751 mci_writeq(host, DATA(host->data_offset),
4e0a5adf 1752 host->part_buf);
34b664a2
JH		 1753 host->part_buf_count = 0;
1754 }
1755 }
1756#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1757 if (unlikely((unsigned long)buf & 0x7)) {
1758 while (cnt >= 8) {
1759 u64 aligned_buf[16];
1760 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1761 int items = len >> 3;
1762 int i;
1763 /* memcpy from input buffer into aligned buffer */
1764 memcpy(aligned_buf, buf, len);
1765 buf += len;
1766 cnt -= len;
1767 /* push data from aligned buffer into fifo */
1768 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1769 mci_writeq(host, DATA(host->data_offset),
1770 aligned_buf[i]);
34b664a2
JH		 1771 }
1772 } else
1773#endif
1774 {
1775 u64 *pdata = buf;
1776 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1777 mci_writeq(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1778 buf = pdata;
1779 }
1780 /* put anything remaining in the part_buf */
1781 if (cnt) {
1782 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 1783 /* Push data if we have reached the expected data length */
1784 if ((data->bytes_xfered + init_cnt) ==
1785 (data->blksz * data->blocks))
4e0a5adf 1786 mci_writeq(host, DATA(host->data_offset),
cfbeb59c 1787 host->part_buf);
f95f3850
WN		 1788 }
1789}
1790
1791static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1792{
34b664a2
JH		 1793#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1794 if (unlikely((unsigned long)buf & 0x7)) {
1795 while (cnt >= 8) {
1796 /* pull data from fifo into aligned buffer */
1797 u64 aligned_buf[16];
1798 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1799 int items = len >> 3;
1800 int i;
1801 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1802 aligned_buf[i] = mci_readq(host,
1803 DATA(host->data_offset));
34b664a2
JH		 1804 /* memcpy from aligned buffer into output buffer */
1805 memcpy(buf, aligned_buf, len);
1806 buf += len;
1807 cnt -= len;
1808 }
1809 } else
1810#endif
1811 {
1812 u64 *pdata = buf;
1813 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1814 *pdata++ = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1815 buf = pdata;
1816 }
1817 if (cnt) {
4e0a5adf 1818 host->part_buf = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1819 dw_mci_pull_final_bytes(host, buf, cnt);
1820 }
1821}
f95f3850 1822
34b664a2
JH		 1823static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1824{
1825 int len;
f95f3850 1826
34b664a2
JH		 1827 /* get remaining partial bytes */
1828 len = dw_mci_pull_part_bytes(host, buf, cnt);
1829 if (unlikely(len == cnt))
1830 return;
1831 buf += len;
1832 cnt -= len;
1833
1834 /* get the rest of the data */
1835 host->pull_data(host, buf, cnt);
f95f3850
WN		 1836}
1837
87a74d39 1838static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
f95f3850 1839{
f9c2a0dc
SJ		 1840 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1841 void *buf;
1842 unsigned int offset;
f95f3850
WN		 1843 struct mmc_data *data = host->data;
1844 int shift = host->data_shift;
1845 u32 status;
3e4b0d8b 1846 unsigned int len;
f9c2a0dc 1847 unsigned int remain, fcnt;
f95f3850
WN		 1848
1849 do {
f9c2a0dc
SJ		 1850 if (!sg_miter_next(sg_miter))
1851 goto done;
1852
4225fc85 1853 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 1854 buf = sg_miter->addr;
1855 remain = sg_miter->length;
1856 offset = 0;
1857
1858 do {
1859 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1860 << shift) + host->part_buf_count;
1861 len = min(remain, fcnt);
1862 if (!len)
1863 break;
34b664a2 1864 dw_mci_pull_data(host, (void *)(buf + offset), len);
3e4b0d8b 1865 data->bytes_xfered += len;
f95f3850 1866 offset += len;
f9c2a0dc
SJ		 1867 remain -= len;
1868 } while (remain);
f95f3850 1869
e74f3a9c 1870 sg_miter->consumed = offset;
f95f3850
WN		 1871 status = mci_readl(host, MINTSTS);
1872 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
87a74d39
KK		 1873 /* if the RXDR is ready read again */
1874 } while ((status & SDMMC_INT_RXDR) ||
1875 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
f9c2a0dc
SJ		 1876
1877 if (!remain) {
1878 if (!sg_miter_next(sg_miter))
1879 goto done;
1880 sg_miter->consumed = 0;
1881 }
1882 sg_miter_stop(sg_miter);
f95f3850
WN		 1883 return;
1884
1885done:
f9c2a0dc
SJ		 1886 sg_miter_stop(sg_miter);
1887 host->sg = NULL;
f95f3850
WN		 1888 smp_wmb();
1889 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1890}
1891
1892static void dw_mci_write_data_pio(struct dw_mci *host)
1893{
f9c2a0dc
SJ		 1894 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1895 void *buf;
1896 unsigned int offset;
f95f3850
WN		 1897 struct mmc_data *data = host->data;
1898 int shift = host->data_shift;
1899 u32 status;
3e4b0d8b 1900 unsigned int len;
f9c2a0dc
SJ		 1901 unsigned int fifo_depth = host->fifo_depth;
1902 unsigned int remain, fcnt;
f95f3850
WN		 1903
1904 do {
f9c2a0dc
SJ		 1905 if (!sg_miter_next(sg_miter))
1906 goto done;
1907
4225fc85 1908 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 1909 buf = sg_miter->addr;
1910 remain = sg_miter->length;
1911 offset = 0;
1912
1913 do {
1914 fcnt = ((fifo_depth -
1915 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1916 << shift) - host->part_buf_count;
1917 len = min(remain, fcnt);
1918 if (!len)
1919 break;
f95f3850 1920 host->push_data(host, (void *)(buf + offset), len);
3e4b0d8b 1921 data->bytes_xfered += len;
f95f3850 1922 offset += len;
f9c2a0dc
SJ		 1923 remain -= len;
1924 } while (remain);
f95f3850 1925
e74f3a9c 1926 sg_miter->consumed = offset;
f95f3850
WN		 1927 status = mci_readl(host, MINTSTS);
1928 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 1929 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f9c2a0dc
SJ		 1930
1931 if (!remain) {
1932 if (!sg_miter_next(sg_miter))
1933 goto done;
1934 sg_miter->consumed = 0;
1935 }
1936 sg_miter_stop(sg_miter);
f95f3850
WN		 1937 return;
1938
1939done:
f9c2a0dc
SJ		 1940 sg_miter_stop(sg_miter);
1941 host->sg = NULL;
f95f3850
WN		 1942 smp_wmb();
1943 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1944}
1945
1946static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1947{
1948 if (!host->cmd_status)
1949 host->cmd_status = status;
1950
1951 smp_wmb();
1952
1953 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1954 tasklet_schedule(&host->tasklet);
1955}
1956
1957static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1958{
1959 struct dw_mci *host = dev_id;
182c9081 1960 u32 pending;
1a5c8e1f 1961 int i;
f95f3850 1962
1fb5f68a
MC		 1963 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1964
476d79f1
DA		 1965 /*
1966 * DTO fix - version 2.10a and below, and only if internal DMA
1967 * is configured.
1968 */
1969 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1970 if (!pending &&
1971 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1972 pending |= SDMMC_INT_DATA_OVER;
1973 }
f95f3850 1974
476d79f1 1975 if (pending) {
01730558
DA		 1976 /* Check volt switch first, since it can look like an error */
1977 if ((host->state == STATE_SENDING_CMD11) &&
1978 (pending & SDMMC_INT_VOLT_SWITCH)) {
1979 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
1980 pending &= ~SDMMC_INT_VOLT_SWITCH;
1981 dw_mci_cmd_interrupt(host, pending);
1982 }
1983
f95f3850
WN		 1984 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1985 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 1986 host->cmd_status = pending;
f95f3850
WN		 1987 smp_wmb();
1988 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1989 }
1990
1991 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1992 /* if there is an error report DATA_ERROR */
1993 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 1994 host->data_status = pending;
f95f3850
WN		 1995 smp_wmb();
1996 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 1997 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1998 }
1999
2000 if (pending & SDMMC_INT_DATA_OVER) {
2001 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2002 if (!host->data_status)
182c9081 2003 host->data_status = pending;
f95f3850
WN		 2004 smp_wmb();
2005 if (host->dir_status == DW_MCI_RECV_STATUS) {
2006 if (host->sg != NULL)
87a74d39 2007 dw_mci_read_data_pio(host, true);
f95f3850
WN		 2008 }
2009 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2010 tasklet_schedule(&host->tasklet);
2011 }
2012
2013 if (pending & SDMMC_INT_RXDR) {
2014 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 2015 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
87a74d39 2016 dw_mci_read_data_pio(host, false);
f95f3850
WN		 2017 }
2018
2019 if (pending & SDMMC_INT_TXDR) {
2020 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 2021 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 2022 dw_mci_write_data_pio(host);
2023 }
2024
2025 if (pending & SDMMC_INT_CMD_DONE) {
2026 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 2027 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 2028 }
2029
2030 if (pending & SDMMC_INT_CD) {
2031 mci_writel(host, RINTSTS, SDMMC_INT_CD);
95dcc2cb 2032 queue_work(host->card_workqueue, &host->card_work);
f95f3850
WN		 2033 }
2034
1a5c8e1f
SH		 2035 /* Handle SDIO Interrupts */
2036 for (i = 0; i < host->num_slots; i++) {
2037 struct dw_mci_slot *slot = host->slot[i];
2038 if (pending & SDMMC_INT_SDIO(i)) {
2039 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
2040 mmc_signal_sdio_irq(slot->mmc);
2041 }
2042 }
2043
1fb5f68a 2044 }
f95f3850
WN		 2045
2046#ifdef CONFIG_MMC_DW_IDMAC
2047 /* Handle DMA interrupts */
2048 pending = mci_readl(host, IDSTS);
2049 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2050 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
2051 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
f95f3850
WN		 2052 host->dma_ops->complete(host);
2053 }
2054#endif
2055
2056 return IRQ_HANDLED;
2057}
2058
1791b13e 2059static void dw_mci_work_routine_card(struct work_struct *work)
f95f3850 2060{
1791b13e 2061 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
f95f3850
WN		 2062 int i;
2063
2064 for (i = 0; i < host->num_slots; i++) {
2065 struct dw_mci_slot *slot = host->slot[i];
2066 struct mmc_host *mmc = slot->mmc;
2067 struct mmc_request *mrq;
2068 int present;
f95f3850
WN		 2069
2070 present = dw_mci_get_cd(mmc);
2071 while (present != slot->last_detect_state) {
f95f3850
WN		 2072 dev_dbg(&slot->mmc->class_dev, "card %s\n",
2073 present ? "inserted" : "removed");
2074
1791b13e
JH		 2075 spin_lock_bh(&host->lock);
2076
f95f3850
WN		 2077 /* Card change detected */
2078 slot->last_detect_state = present;
2079
f95f3850
WN		 2080 /* Clean up queue if present */
2081 mrq = slot->mrq;
2082 if (mrq) {
2083 if (mrq == host->mrq) {
2084 host->data = NULL;
2085 host->cmd = NULL;
2086
2087 switch (host->state) {
2088 case STATE_IDLE:
01730558 2089 case STATE_WAITING_CMD11_DONE:
f95f3850 2090 break;
01730558 2091 case STATE_SENDING_CMD11:
f95f3850
WN		 2092 case STATE_SENDING_CMD:
2093 mrq->cmd->error = -ENOMEDIUM;
2094 if (!mrq->data)
2095 break;
2096 /* fall through */
2097 case STATE_SENDING_DATA:
2098 mrq->data->error = -ENOMEDIUM;
2099 dw_mci_stop_dma(host);
2100 break;
2101 case STATE_DATA_BUSY:
2102 case STATE_DATA_ERROR:
2103 if (mrq->data->error == -EINPROGRESS)
2104 mrq->data->error = -ENOMEDIUM;
f95f3850
WN		 2105 /* fall through */
2106 case STATE_SENDING_STOP:
90c2143a
SJ		 2107 if (mrq->stop)
2108 mrq->stop->error = -ENOMEDIUM;
f95f3850
WN		 2109 break;
2110 }
2111
2112 dw_mci_request_end(host, mrq);
2113 } else {
2114 list_del(&slot->queue_node);
2115 mrq->cmd->error = -ENOMEDIUM;
2116 if (mrq->data)
2117 mrq->data->error = -ENOMEDIUM;
2118 if (mrq->stop)
2119 mrq->stop->error = -ENOMEDIUM;
2120
2121 spin_unlock(&host->lock);
2122 mmc_request_done(slot->mmc, mrq);
2123 spin_lock(&host->lock);
2124 }
2125 }
2126
2127 /* Power down slot */
3a33a94c
SR		 2128 if (present == 0)
2129 dw_mci_reset(host);
f95f3850 2130
1791b13e
JH		 2131 spin_unlock_bh(&host->lock);
2132
f95f3850
WN		 2133 present = dw_mci_get_cd(mmc);
2134 }
2135
2136 mmc_detect_change(slot->mmc,
2137 msecs_to_jiffies(host->pdata->detect_delay_ms));
2138 }
2139}
2140
c91eab4b
TA		 2141#ifdef CONFIG_OF
2142/* given a slot id, find out the device node representing that slot */
2143static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
2144{
2145 struct device_node *np;
2146 const __be32 *addr;
2147 int len;
2148
2149 if (!dev || !dev->of_node)
2150 return NULL;
2151
2152 for_each_child_of_node(dev->of_node, np) {
2153 addr = of_get_property(np, "reg", &len);
2154 if (!addr || (len < sizeof(int)))
2155 continue;
2156 if (be32_to_cpup(addr) == slot)
2157 return np;
2158 }
2159 return NULL;
2160}
2161
a70aaa64
DA		 2162static struct dw_mci_of_slot_quirks {
2163 char *quirk;
2164 int id;
2165} of_slot_quirks[] = {
2166 {
2167 .quirk = "disable-wp",
2168 .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
2169 },
2170};
2171
2172static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2173{
2174 struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
2175 int quirks = 0;
2176 int idx;
2177
2178 /* get quirks */
2179 for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
26375b5c
JC		 2180 if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) {
2181 dev_warn(dev, "Slot quirk %s is deprecated\n",
2182 of_slot_quirks[idx].quirk);
a70aaa64 2183 quirks |= of_slot_quirks[idx].id;
26375b5c 2184 }
a70aaa64
DA		 2185
2186 return quirks;
2187}
c91eab4b 2188#else /* CONFIG_OF */
a70aaa64
DA		 2189static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
2190{
2191 return 0;
2192}
c91eab4b
TA		 2193#endif /* CONFIG_OF */
2194
36c179a9 2195static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 2196{
2197 struct mmc_host *mmc;
2198 struct dw_mci_slot *slot;
e95baf13 2199 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2200 int ctrl_id, ret;
1f44a2a5 2201 u32 freq[2];
f95f3850 2202
4a90920c 2203 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 2204 if (!mmc)
2205 return -ENOMEM;
2206
2207 slot = mmc_priv(mmc);
2208 slot->id = id;
2209 slot->mmc = mmc;
2210 slot->host = host;
c91eab4b 2211 host->slot[id] = slot;
f95f3850 2212
a70aaa64
DA		 2213 slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
2214
f95f3850 2215 mmc->ops = &dw_mci_ops;
1f44a2a5
SJ		 2216 if (of_property_read_u32_array(host->dev->of_node,
2217 "clock-freq-min-max", freq, 2)) {
2218 mmc->f_min = DW_MCI_FREQ_MIN;
2219 mmc->f_max = DW_MCI_FREQ_MAX;
2220 } else {
2221 mmc->f_min = freq[0];
2222 mmc->f_max = freq[1];
2223 }
f95f3850 2224
51da2240
YC		 2225 /*if there are external regulators, get them*/
2226 ret = mmc_regulator_get_supply(mmc);
2227 if (ret == -EPROBE_DEFER)
3cf890fc 2228 goto err_host_allocated;
51da2240
YC		 2229
2230 if (!mmc->ocr_avail)
2231 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
f95f3850 2232
fc3d7720
JC		 2233 if (host->pdata->caps)
2234 mmc->caps = host->pdata->caps;
fc3d7720 2235
ab269128
AK		 2236 if (host->pdata->pm_caps)
2237 mmc->pm_caps = host->pdata->pm_caps;
2238
800d78bf
TA		 2239 if (host->dev->of_node) {
2240 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2241 if (ctrl_id < 0)
2242 ctrl_id = 0;
2243 } else {
2244 ctrl_id = to_platform_device(host->dev)->id;
2245 }
cb27a843
JH		 2246 if (drv_data && drv_data->caps)
2247 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 2248
4f408cc6
SJ		 2249 if (host->pdata->caps2)
2250 mmc->caps2 = host->pdata->caps2;
4f408cc6 2251
3cf890fc
DA		 2252 ret = mmc_of_parse(mmc);
2253 if (ret)
2254 goto err_host_allocated;
f95f3850 2255
f95f3850
WN		 2256 if (host->pdata->blk_settings) {
2257 mmc->max_segs = host->pdata->blk_settings->max_segs;
2258 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
2259 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
2260 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
2261 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
2262 } else {
2263 /* Useful defaults if platform data is unset. */
a39e5746
JC		 2264#ifdef CONFIG_MMC_DW_IDMAC
2265 mmc->max_segs = host->ring_size;
2266 mmc->max_blk_size = 65536;
2267 mmc->max_blk_count = host->ring_size;
2268 mmc->max_seg_size = 0x1000;
2269 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
2270#else
f95f3850
WN		 2271 mmc->max_segs = 64;
2272 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2273 mmc->max_blk_count = 512;
2274 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2275 mmc->max_seg_size = mmc->max_req_size;
f95f3850 2276#endif /* CONFIG_MMC_DW_IDMAC */
a39e5746 2277 }
f95f3850 2278
ae0eb348
JC		 2279 if (dw_mci_get_cd(mmc))
2280 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2281 else
2282 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2283
0cea529d
JC		 2284 ret = mmc_add_host(mmc);
2285 if (ret)
3cf890fc 2286 goto err_host_allocated;
f95f3850
WN		 2287
2288#if defined(CONFIG_DEBUG_FS)
2289 dw_mci_init_debugfs(slot);
2290#endif
2291
2292 /* Card initially undetected */
2293 slot->last_detect_state = 0;
2294
2295 return 0;
800d78bf 2296
3cf890fc 2297err_host_allocated:
800d78bf 2298 mmc_free_host(mmc);
51da2240 2299 return ret;
f95f3850
WN		 2300}
2301
2302static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2303{
f95f3850
WN		 2304 /* Debugfs stuff is cleaned up by mmc core */
2305 mmc_remove_host(slot->mmc);
2306 slot->host->slot[id] = NULL;
2307 mmc_free_host(slot->mmc);
2308}
2309
2310static void dw_mci_init_dma(struct dw_mci *host)
2311{
2312 /* Alloc memory for sg translation */
780f22af 2313 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
f95f3850
WN		 2314 &host->sg_dma, GFP_KERNEL);
2315 if (!host->sg_cpu) {
4a90920c 2316 dev_err(host->dev, "%s: could not alloc DMA memory\n",
f95f3850
WN		 2317 __func__);
2318 goto no_dma;
2319 }
2320
2321 /* Determine which DMA interface to use */
2322#ifdef CONFIG_MMC_DW_IDMAC
2323 host->dma_ops = &dw_mci_idmac_ops;
00956ea3 2324 dev_info(host->dev, "Using internal DMA controller.\n");
f95f3850
WN		 2325#endif
2326
2327 if (!host->dma_ops)
2328 goto no_dma;
2329
e1631f98
JC		 2330 if (host->dma_ops->init && host->dma_ops->start &&
2331 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 2332 if (host->dma_ops->init(host)) {
4a90920c 2333 dev_err(host->dev, "%s: Unable to initialize "
f95f3850
WN		 2334 "DMA Controller.\n", __func__);
2335 goto no_dma;
2336 }
2337 } else {
4a90920c 2338 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 2339 goto no_dma;
2340 }
2341
2342 host->use_dma = 1;
2343 return;
2344
2345no_dma:
4a90920c 2346 dev_info(host->dev, "Using PIO mode.\n");
f95f3850
WN		 2347 host->use_dma = 0;
2348 return;
2349}
2350
31bff450 2351static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
f95f3850
WN		 2352{
2353 unsigned long timeout = jiffies + msecs_to_jiffies(500);
31bff450 2354 u32 ctrl;
f95f3850 2355
31bff450
SJ		 2356 ctrl = mci_readl(host, CTRL);
2357 ctrl |= reset;
2358 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 2359
2360 /* wait till resets clear */
2361 do {
2362 ctrl = mci_readl(host, CTRL);
31bff450 2363 if (!(ctrl & reset))
f95f3850
WN		 2364 return true;
2365 } while (time_before(jiffies, timeout));
2366
31bff450
SJ		 2367 dev_err(host->dev,
2368 "Timeout resetting block (ctrl reset %#x)\n",
2369 ctrl & reset);
f95f3850
WN		 2370
2371 return false;
2372}
2373
3a33a94c 2374static bool dw_mci_reset(struct dw_mci *host)
31bff450 2375{
3a33a94c
SR		 2376 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2377 bool ret = false;
2378
31bff450
SJ		 2379 /*
2380 * Reseting generates a block interrupt, hence setting
2381 * the scatter-gather pointer to NULL.
2382 */
2383 if (host->sg) {
2384 sg_miter_stop(&host->sg_miter);
2385 host->sg = NULL;
2386 }
2387
3a33a94c
SR		 2388 if (host->use_dma)
2389 flags |= SDMMC_CTRL_DMA_RESET;
31bff450 2390
3a33a94c
SR		 2391 if (dw_mci_ctrl_reset(host, flags)) {
2392 /*
2393 * In all cases we clear the RAWINTS register to clear any
2394 * interrupts.
2395 */
2396 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2397
2398 /* if using dma we wait for dma_req to clear */
2399 if (host->use_dma) {
2400 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2401 u32 status;
2402 do {
2403 status = mci_readl(host, STATUS);
2404 if (!(status & SDMMC_STATUS_DMA_REQ))
2405 break;
2406 cpu_relax();
2407 } while (time_before(jiffies, timeout));
2408
2409 if (status & SDMMC_STATUS_DMA_REQ) {
2410 dev_err(host->dev,
2411 "%s: Timeout waiting for dma_req to "
2412 "clear during reset\n", __func__);
2413 goto ciu_out;
2414 }
2415
2416 /* when using DMA next we reset the fifo again */
2417 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2418 goto ciu_out;
2419 }
2420 } else {
2421 /* if the controller reset bit did clear, then set clock regs */
2422 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
2423 dev_err(host->dev, "%s: fifo/dma reset bits didn't "
2424 "clear but ciu was reset, doing clock update\n",
2425 __func__);
2426 goto ciu_out;
2427 }
2428 }
2429
2430#if IS_ENABLED(CONFIG_MMC_DW_IDMAC)
2431 /* It is also recommended that we reset and reprogram idmac */
2432 dw_mci_idmac_reset(host);
2433#endif
2434
2435 ret = true;
2436
2437ciu_out:
2438 /* After a CTRL reset we need to have CIU set clock registers */
2439 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2440
2441 return ret;
31bff450
SJ		 2442}
2443
c91eab4b
TA		 2444#ifdef CONFIG_OF
2445static struct dw_mci_of_quirks {
2446 char *quirk;
2447 int id;
2448} of_quirks[] = {
2449 {
c91eab4b
TA		 2450 .quirk = "broken-cd",
2451 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
26375b5c
JC		 2452 }, {
2453 .quirk = "disable-wp",
2454 .id = DW_MCI_QUIRK_NO_WRITE_PROTECT,
c91eab4b
TA		 2455 },
2456};
2457
2458static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2459{
2460 struct dw_mci_board *pdata;
2461 struct device *dev = host->dev;
2462 struct device_node *np = dev->of_node;
e95baf13 2463 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2464 int idx, ret;
3c6d89ea 2465 u32 clock_frequency;
c91eab4b
TA		 2466
2467 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2468 if (!pdata) {
2469 dev_err(dev, "could not allocate memory for pdata\n");
2470 return ERR_PTR(-ENOMEM);
2471 }
2472
2473 /* find out number of slots supported */
2474 if (of_property_read_u32(dev->of_node, "num-slots",
2475 &pdata->num_slots)) {
2476 dev_info(dev, "num-slots property not found, "
2477 "assuming 1 slot is available\n");
2478 pdata->num_slots = 1;
2479 }
2480
2481 /* get quirks */
2482 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2483 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2484 pdata->quirks |= of_quirks[idx].id;
2485
2486 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
2487 dev_info(dev, "fifo-depth property not found, using "
2488 "value of FIFOTH register as default\n");
2489
2490 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2491
3c6d89ea
DA		 2492 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2493 pdata->bus_hz = clock_frequency;
2494
cb27a843
JH		 2495 if (drv_data && drv_data->parse_dt) {
2496 ret = drv_data->parse_dt(host);
800d78bf
TA		 2497 if (ret)
2498 return ERR_PTR(ret);
2499 }
2500
10b49841
SJ		 2501 if (of_find_property(np, "supports-highspeed", NULL))
2502 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2503
c91eab4b
TA		 2504 return pdata;
2505}
2506
2507#else /* CONFIG_OF */
2508static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2509{
2510 return ERR_PTR(-EINVAL);
2511}
2512#endif /* CONFIG_OF */
2513
62ca8034 2514int dw_mci_probe(struct dw_mci *host)
f95f3850 2515{
e95baf13 2516 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 2517 int width, i, ret = 0;
f95f3850 2518 u32 fifo_size;
1c2215b7 2519 int init_slots = 0;
f95f3850 2520
c91eab4b
TA		 2521 if (!host->pdata) {
2522 host->pdata = dw_mci_parse_dt(host);
2523 if (IS_ERR(host->pdata)) {
2524 dev_err(host->dev, "platform data not available\n");
2525 return -EINVAL;
2526 }
f95f3850
WN		 2527 }
2528
907abd51 2529 if (host->pdata->num_slots > 1) {
4a90920c 2530 dev_err(host->dev,
907abd51 2531 "Platform data must supply num_slots.\n");
62ca8034 2532 return -ENODEV;
f95f3850
WN		 2533 }
2534
780f22af 2535 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 2536 if (IS_ERR(host->biu_clk)) {
2537 dev_dbg(host->dev, "biu clock not available\n");
2538 } else {
2539 ret = clk_prepare_enable(host->biu_clk);
2540 if (ret) {
2541 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 2542 return ret;
2543 }
2544 }
2545
780f22af 2546 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 2547 if (IS_ERR(host->ciu_clk)) {
2548 dev_dbg(host->dev, "ciu clock not available\n");
3c6d89ea 2549 host->bus_hz = host->pdata->bus_hz;
f90a0612
TA		 2550 } else {
2551 ret = clk_prepare_enable(host->ciu_clk);
2552 if (ret) {
2553 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 2554 goto err_clk_biu;
2555 }
f90a0612 2556
3c6d89ea
DA		 2557 if (host->pdata->bus_hz) {
2558 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2559 if (ret)
2560 dev_warn(host->dev,
612de4c1 2561 "Unable to set bus rate to %uHz\n",
3c6d89ea
DA		 2562 host->pdata->bus_hz);
2563 }
f90a0612 2564 host->bus_hz = clk_get_rate(host->ciu_clk);
3c6d89ea 2565 }
f90a0612 2566
612de4c1
JC		 2567 if (!host->bus_hz) {
2568 dev_err(host->dev,
2569 "Platform data must supply bus speed\n");
2570 ret = -ENODEV;
2571 goto err_clk_ciu;
2572 }
2573
002f0d5c
YK		 2574 if (drv_data && drv_data->init) {
2575 ret = drv_data->init(host);
2576 if (ret) {
2577 dev_err(host->dev,
2578 "implementation specific init failed\n");
2579 goto err_clk_ciu;
2580 }
2581 }
2582
cb27a843
JH		 2583 if (drv_data && drv_data->setup_clock) {
2584 ret = drv_data->setup_clock(host);
800d78bf
TA		 2585 if (ret) {
2586 dev_err(host->dev,
2587 "implementation specific clock setup failed\n");
2588 goto err_clk_ciu;
2589 }
2590 }
2591
62ca8034 2592 host->quirks = host->pdata->quirks;
f95f3850
WN		 2593
2594 spin_lock_init(&host->lock);
2595 INIT_LIST_HEAD(&host->queue);
2596
f95f3850
WN		 2597 /*
2598 * Get the host data width - this assumes that HCON has been set with
2599 * the correct values.
2600 */
2601 i = (mci_readl(host, HCON) >> 7) & 0x7;
2602 if (!i) {
2603 host->push_data = dw_mci_push_data16;
2604 host->pull_data = dw_mci_pull_data16;
2605 width = 16;
2606 host->data_shift = 1;
2607 } else if (i == 2) {
2608 host->push_data = dw_mci_push_data64;
2609 host->pull_data = dw_mci_pull_data64;
2610 width = 64;
2611 host->data_shift = 3;
2612 } else {
2613 /* Check for a reserved value, and warn if it is */
2614 WARN((i != 1),
2615 "HCON reports a reserved host data width!\n"
2616 "Defaulting to 32-bit access.\n");
2617 host->push_data = dw_mci_push_data32;
2618 host->pull_data = dw_mci_pull_data32;
2619 width = 32;
2620 host->data_shift = 2;
2621 }
2622
2623 /* Reset all blocks */
3a33a94c 2624 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
141a712a
SJ		 2625 return -ENODEV;
2626
2627 host->dma_ops = host->pdata->dma_ops;
2628 dw_mci_init_dma(host);
f95f3850
WN		 2629
2630 /* Clear the interrupts for the host controller */
2631 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2632 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2633
2634 /* Put in max timeout */
2635 mci_writel(host, TMOUT, 0xFFFFFFFF);
2636
2637 /*
2638 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2639 * Tx Mark = fifo_size / 2 DMA Size = 8
2640 */
b86d8253
JH		 2641 if (!host->pdata->fifo_depth) {
2642 /*
2643 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2644 * have been overwritten by the bootloader, just like we're
2645 * about to do, so if you know the value for your hardware, you
2646 * should put it in the platform data.
2647 */
2648 fifo_size = mci_readl(host, FIFOTH);
8234e869 2649 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 2650 } else {
2651 fifo_size = host->pdata->fifo_depth;
2652 }
2653 host->fifo_depth = fifo_size;
52426899
SJ		 2654 host->fifoth_val =
2655 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
e61cf118 2656 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 2657
2658 /* disable clock to CIU */
2659 mci_writel(host, CLKENA, 0);
2660 mci_writel(host, CLKSRC, 0);
2661
63008768
JH		 2662 /*
2663 * In 2.40a spec, Data offset is changed.
2664 * Need to check the version-id and set data-offset for DATA register.
2665 */
2666 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
2667 dev_info(host->dev, "Version ID is %04x\n", host->verid);
2668
2669 if (host->verid < DW_MMC_240A)
2670 host->data_offset = DATA_OFFSET;
2671 else
2672 host->data_offset = DATA_240A_OFFSET;
2673
f95f3850 2674 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
95dcc2cb 2675 host->card_workqueue = alloc_workqueue("dw-mci-card",
59ff3eb6 2676 WQ_MEM_RECLAIM, 1);
ef7aef9a
WY		 2677 if (!host->card_workqueue) {
2678 ret = -ENOMEM;
1791b13e 2679 goto err_dmaunmap;
ef7aef9a 2680 }
1791b13e 2681 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
780f22af
SJ		 2682 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
2683 host->irq_flags, "dw-mci", host);
f95f3850 2684 if (ret)
1791b13e 2685 goto err_workqueue;
f95f3850 2686
f95f3850
WN		 2687 if (host->pdata->num_slots)
2688 host->num_slots = host->pdata->num_slots;
2689 else
2690 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2691
2da1d7f2
YC		 2692 /*
2693 * Enable interrupts for command done, data over, data empty, card det,
2694 * receive ready and error such as transmit, receive timeout, crc error
2695 */
2696 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2697 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2698 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2699 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2700 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2701
2702 dev_info(host->dev, "DW MMC controller at irq %d, "
2703 "%d bit host data width, "
2704 "%u deep fifo\n",
2705 host->irq, width, fifo_size);
2706
f95f3850
WN		 2707 /* We need at least one slot to succeed */
2708 for (i = 0; i < host->num_slots; i++) {
2709 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 2710 if (ret)
2711 dev_dbg(host->dev, "slot %d init failed\n", i);
2712 else
2713 init_slots++;
2714 }
2715
2716 if (init_slots) {
2717 dev_info(host->dev, "%d slots initialized\n", init_slots);
2718 } else {
2719 dev_dbg(host->dev, "attempted to initialize %d slots, "
2720 "but failed on all\n", host->num_slots);
780f22af 2721 goto err_workqueue;
f95f3850
WN		 2722 }
2723
f95f3850 2724 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4a90920c 2725 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
f95f3850
WN		 2726
2727 return 0;
2728
1791b13e 2729err_workqueue:
95dcc2cb 2730 destroy_workqueue(host->card_workqueue);
1791b13e 2731
f95f3850
WN		 2732err_dmaunmap:
2733 if (host->use_dma && host->dma_ops->exit)
2734 host->dma_ops->exit(host);
f90a0612
TA		 2735
2736err_clk_ciu:
780f22af 2737 if (!IS_ERR(host->ciu_clk))
f90a0612 2738 clk_disable_unprepare(host->ciu_clk);
780f22af 2739
f90a0612 2740err_clk_biu:
780f22af 2741 if (!IS_ERR(host->biu_clk))
f90a0612 2742 clk_disable_unprepare(host->biu_clk);
780f22af 2743
f95f3850
WN		 2744 return ret;
2745}
62ca8034 2746EXPORT_SYMBOL(dw_mci_probe);
f95f3850 2747
62ca8034 2748void dw_mci_remove(struct dw_mci *host)
f95f3850 2749{
f95f3850
WN		 2750 int i;
2751
2752 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2753 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2754
f95f3850 2755 for (i = 0; i < host->num_slots; i++) {
4a90920c 2756 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 2757 if (host->slot[i])
2758 dw_mci_cleanup_slot(host->slot[i], i);
2759 }
2760
2761 /* disable clock to CIU */
2762 mci_writel(host, CLKENA, 0);
2763 mci_writel(host, CLKSRC, 0);
2764
95dcc2cb 2765 destroy_workqueue(host->card_workqueue);
f95f3850
WN		 2766
2767 if (host->use_dma && host->dma_ops->exit)
2768 host->dma_ops->exit(host);
2769
f90a0612
TA		 2770 if (!IS_ERR(host->ciu_clk))
2771 clk_disable_unprepare(host->ciu_clk);
780f22af 2772
f90a0612
TA		 2773 if (!IS_ERR(host->biu_clk))
2774 clk_disable_unprepare(host->biu_clk);
f95f3850 2775}
62ca8034
SH		 2776EXPORT_SYMBOL(dw_mci_remove);
2777
2778
f95f3850 2779
6fe8890d 2780#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 2781/*
2782 * TODO: we should probably disable the clock to the card in the suspend path.
2783 */
62ca8034 2784int dw_mci_suspend(struct dw_mci *host)
f95f3850 2785{
f95f3850
WN		 2786 return 0;
2787}
62ca8034 2788EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 2789
62ca8034 2790int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 2791{
2792 int i, ret;
f95f3850 2793
3a33a94c 2794 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
e61cf118
JC		 2795 ret = -ENODEV;
2796 return ret;
2797 }
2798
3bfe619d 2799 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 2800 host->dma_ops->init(host);
2801
52426899
SJ		 2802 /*
2803 * Restore the initial value at FIFOTH register
2804 * And Invalidate the prev_blksz with zero
2805 */
e61cf118 2806 mci_writel(host, FIFOTH, host->fifoth_val);
52426899 2807 host->prev_blksz = 0;
e61cf118 2808
2eb2944f
DA		 2809 /* Put in max timeout */
2810 mci_writel(host, TMOUT, 0xFFFFFFFF);
2811
e61cf118
JC		 2812 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2813 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2814 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2815 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2816 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2817
f95f3850
WN		 2818 for (i = 0; i < host->num_slots; i++) {
2819 struct dw_mci_slot *slot = host->slot[i];
2820 if (!slot)
2821 continue;
ab269128
AK		 2822 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
2823 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
2824 dw_mci_setup_bus(slot, true);
2825 }
f95f3850 2826 }
f95f3850
WN		 2827 return 0;
2828}
62ca8034 2829EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 2830#endif /* CONFIG_PM_SLEEP */
2831
f95f3850
WN		 2832static int __init dw_mci_init(void)
2833{
8e1c4e4d 2834 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
62ca8034 2835 return 0;
f95f3850
WN		 2836}
2837
2838static void __exit dw_mci_exit(void)
2839{
f95f3850
WN		 2840}
2841
2842module_init(dw_mci_init);
2843module_exit(dw_mci_exit);
2844
2845MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2846MODULE_AUTHOR("NXP Semiconductor VietNam");
2847MODULE_AUTHOR("Imagination Technologies Ltd");
2848MODULE_LICENSE("GPL v2");
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