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mmc: dw_mmc: avoid race condition of cpu and IDMAC
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
b24c8b26 30#include <linux/mmc/card.h>
f95f3850
WN		 31#include <linux/mmc/host.h>
32#include <linux/mmc/mmc.h>
01730558 33#include <linux/mmc/sd.h>
90c2143a 34#include <linux/mmc/sdio.h>
f95f3850
WN		 35#include <linux/mmc/dw_mmc.h>
36#include <linux/bitops.h>
c07946a3 37#include <linux/regulator/consumer.h>
c91eab4b 38#include <linux/of.h>
55a6ceb2 39#include <linux/of_gpio.h>
bf626e55 40#include <linux/mmc/slot-gpio.h>
f95f3850
WN		 41
42#include "dw_mmc.h"
43
44/* Common flag combinations */
3f7eec62 45#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
f95f3850 46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
7a3c5677 47 SDMMC_INT_EBE | SDMMC_INT_HLE)
f95f3850 48#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
7a3c5677 49 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
f95f3850 50#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
7a3c5677 51 DW_MCI_CMD_ERROR_FLAGS)
f95f3850
WN		 52#define DW_MCI_SEND_STATUS 1
53#define DW_MCI_RECV_STATUS 2
54#define DW_MCI_DMA_THRESHOLD 16
55
1f44a2a5
SJ		 56#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
fc79a4d6
JS		 59#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
62 SDMMC_IDMAC_INT_TI)
63
69d99fdc
PT		 64struct idmac_desc_64addr {
65 u32 des0; /* Control Descriptor */
66
67 u32 des1; /* Reserved */
68
69 u32 des2; /*Buffer sizes */
70#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
6687c42f
BD		 71 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
72 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
69d99fdc
PT		 73
74 u32 des3; /* Reserved */
75
76 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
77 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
78
79 u32 des6; /* Lower 32-bits of Next Descriptor Address */
80 u32 des7; /* Upper 32-bits of Next Descriptor Address */
81};
82
f95f3850 83struct idmac_desc {
6687c42f 84 __le32 des0; /* Control Descriptor */
f95f3850
WN		 85#define IDMAC_DES0_DIC BIT(1)
86#define IDMAC_DES0_LD BIT(2)
87#define IDMAC_DES0_FD BIT(3)
88#define IDMAC_DES0_CH BIT(4)
89#define IDMAC_DES0_ER BIT(5)
90#define IDMAC_DES0_CES BIT(30)
91#define IDMAC_DES0_OWN BIT(31)
92
6687c42f 93 __le32 des1; /* Buffer sizes */
f95f3850 94#define IDMAC_SET_BUFFER1_SIZE(d, s) \
e5306c3a 95 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
f95f3850 96
6687c42f 97 __le32 des2; /* buffer 1 physical address */
f95f3850 98
6687c42f 99 __le32 des3; /* buffer 2 physical address */
f95f3850 100};
5959b32e
AB		 101
102/* Each descriptor can transfer up to 4KB of data in chained mode */
103#define DW_MCI_DESC_DATA_LENGTH 0x1000
f95f3850 104
3a33a94c 105static bool dw_mci_reset(struct dw_mci *host);
536f6b91 106static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
0bdbd0e8 107static int dw_mci_card_busy(struct mmc_host *mmc);
56f6911c 108static int dw_mci_get_cd(struct mmc_host *mmc);
31bff450 109
f95f3850
WN		 110#if defined(CONFIG_DEBUG_FS)
111static int dw_mci_req_show(struct seq_file *s, void *v)
112{
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
118
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
121 mrq = slot->mrq;
122
123 if (mrq) {
124 cmd = mrq->cmd;
125 data = mrq->data;
126 stop = mrq->stop;
127
128 if (cmd)
129 seq_printf(s,
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
134 if (data)
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
138 if (stop)
139 seq_printf(s,
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
144 }
145
146 spin_unlock_bh(&slot->host->lock);
147
148 return 0;
149}
150
151static int dw_mci_req_open(struct inode *inode, struct file *file)
152{
153 return single_open(file, dw_mci_req_show, inode->i_private);
154}
155
156static const struct file_operations dw_mci_req_fops = {
157 .owner = THIS_MODULE,
158 .open = dw_mci_req_open,
159 .read = seq_read,
160 .llseek = seq_lseek,
161 .release = single_release,
162};
163
164static int dw_mci_regs_show(struct seq_file *s, void *v)
165{
166 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
167 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
168 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
169 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
170 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
171 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
172
173 return 0;
174}
175
176static int dw_mci_regs_open(struct inode *inode, struct file *file)
177{
178 return single_open(file, dw_mci_regs_show, inode->i_private);
179}
180
181static const struct file_operations dw_mci_regs_fops = {
182 .owner = THIS_MODULE,
183 .open = dw_mci_regs_open,
184 .read = seq_read,
185 .llseek = seq_lseek,
186 .release = single_release,
187};
188
189static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
190{
191 struct mmc_host *mmc = slot->mmc;
192 struct dw_mci *host = slot->host;
193 struct dentry *root;
194 struct dentry *node;
195
196 root = mmc->debugfs_root;
197 if (!root)
198 return;
199
200 node = debugfs_create_file("regs", S_IRUSR, root, host,
201 &dw_mci_regs_fops);
202 if (!node)
203 goto err;
204
205 node = debugfs_create_file("req", S_IRUSR, root, slot,
206 &dw_mci_req_fops);
207 if (!node)
208 goto err;
209
210 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
211 if (!node)
212 goto err;
213
214 node = debugfs_create_x32("pending_events", S_IRUSR, root,
215 (u32 *)&host->pending_events);
216 if (!node)
217 goto err;
218
219 node = debugfs_create_x32("completed_events", S_IRUSR, root,
220 (u32 *)&host->completed_events);
221 if (!node)
222 goto err;
223
224 return;
225
226err:
227 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
228}
229#endif /* defined(CONFIG_DEBUG_FS) */
230
01730558
DA		 231static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
232
f95f3850
WN		 233static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
234{
235 struct mmc_data *data;
800d78bf 236 struct dw_mci_slot *slot = mmc_priv(mmc);
01730558 237 struct dw_mci *host = slot->host;
f95f3850 238 u32 cmdr;
f95f3850 239
0e3a22c0 240 cmd->error = -EINPROGRESS;
f95f3850
WN		 241 cmdr = cmd->opcode;
242
90c2143a
SJ		 243 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
244 cmd->opcode == MMC_GO_IDLE_STATE ||
245 cmd->opcode == MMC_GO_INACTIVE_STATE ||
246 (cmd->opcode == SD_IO_RW_DIRECT &&
247 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
f95f3850 248 cmdr |= SDMMC_CMD_STOP;
4a1b27ad
JC		 249 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
250 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
f95f3850 251
01730558
DA		 252 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
253 u32 clk_en_a;
254
255 /* Special bit makes CMD11 not die */
256 cmdr |= SDMMC_CMD_VOLT_SWITCH;
257
258 /* Change state to continue to handle CMD11 weirdness */
259 WARN_ON(slot->host->state != STATE_SENDING_CMD);
260 slot->host->state = STATE_SENDING_CMD11;
261
262 /*
263 * We need to disable low power mode (automatic clock stop)
264 * while doing voltage switch so we don't confuse the card,
265 * since stopping the clock is a specific part of the UHS
266 * voltage change dance.
267 *
268 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
269 * unconditionally turned back on in dw_mci_setup_bus() if it's
270 * ever called with a non-zero clock. That shouldn't happen
271 * until the voltage change is all done.
272 */
273 clk_en_a = mci_readl(host, CLKENA);
274 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
275 mci_writel(host, CLKENA, clk_en_a);
276 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
277 SDMMC_CMD_PRV_DAT_WAIT, 0);
278 }
279
f95f3850
WN		 280 if (cmd->flags & MMC_RSP_PRESENT) {
281 /* We expect a response, so set this bit */
282 cmdr |= SDMMC_CMD_RESP_EXP;
283 if (cmd->flags & MMC_RSP_136)
284 cmdr |= SDMMC_CMD_RESP_LONG;
285 }
286
287 if (cmd->flags & MMC_RSP_CRC)
288 cmdr |= SDMMC_CMD_RESP_CRC;
289
290 data = cmd->data;
291 if (data) {
292 cmdr |= SDMMC_CMD_DAT_EXP;
f95f3850
WN		 293 if (data->flags & MMC_DATA_WRITE)
294 cmdr |= SDMMC_CMD_DAT_WR;
295 }
296
aaaaeb7a
JC		 297 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
298 cmdr |= SDMMC_CMD_USE_HOLD_REG;
800d78bf 299
f95f3850
WN		 300 return cmdr;
301}
302
90c2143a
SJ		 303static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
304{
305 struct mmc_command *stop;
306 u32 cmdr;
307
308 if (!cmd->data)
309 return 0;
310
311 stop = &host->stop_abort;
312 cmdr = cmd->opcode;
313 memset(stop, 0, sizeof(struct mmc_command));
314
315 if (cmdr == MMC_READ_SINGLE_BLOCK ||
316 cmdr == MMC_READ_MULTIPLE_BLOCK ||
317 cmdr == MMC_WRITE_BLOCK ||
6c2c6506
UH		 318 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
319 cmdr == MMC_SEND_TUNING_BLOCK ||
320 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
90c2143a
SJ		 321 stop->opcode = MMC_STOP_TRANSMISSION;
322 stop->arg = 0;
323 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
324 } else if (cmdr == SD_IO_RW_EXTENDED) {
325 stop->opcode = SD_IO_RW_DIRECT;
326 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
327 ((cmd->arg >> 28) & 0x7);
328 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
329 } else {
330 return 0;
331 }
332
333 cmdr = stop->opcode | SDMMC_CMD_STOP |
334 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
335
336 return cmdr;
337}
338
0bdbd0e8
DA		 339static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
340{
341 unsigned long timeout = jiffies + msecs_to_jiffies(500);
342
343 /*
344 * Databook says that before issuing a new data transfer command
345 * we need to check to see if the card is busy. Data transfer commands
346 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
347 *
348 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
349 * expected.
350 */
351 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
352 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
353 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
354 if (time_after(jiffies, timeout)) {
355 /* Command will fail; we'll pass error then */
356 dev_err(host->dev, "Busy; trying anyway\n");
357 break;
358 }
359 udelay(10);
360 }
361 }
362}
363
f95f3850
WN		 364static void dw_mci_start_command(struct dw_mci *host,
365 struct mmc_command *cmd, u32 cmd_flags)
366{
367 host->cmd = cmd;
4a90920c 368 dev_vdbg(host->dev,
f95f3850
WN		 369 "start command: ARGR=0x%08x CMDR=0x%08x\n",
370 cmd->arg, cmd_flags);
371
372 mci_writel(host, CMDARG, cmd->arg);
0e3a22c0 373 wmb(); /* drain writebuffer */
0bdbd0e8 374 dw_mci_wait_while_busy(host, cmd_flags);
f95f3850
WN		 375
376 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
377}
378
90c2143a 379static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
f95f3850 380{
90c2143a 381 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
0e3a22c0 382
90c2143a 383 dw_mci_start_command(host, stop, host->stop_cmdr);
f95f3850
WN		 384}
385
386/* DMA interface functions */
387static void dw_mci_stop_dma(struct dw_mci *host)
388{
03e8cb53 389 if (host->using_dma) {
f95f3850
WN		 390 host->dma_ops->stop(host);
391 host->dma_ops->cleanup(host);
f95f3850 392 }
aa50f259
SJ		 393
394 /* Data transfer was stopped by the interrupt handler */
395 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
f95f3850
WN		 396}
397
9aa51408
SJ		 398static int dw_mci_get_dma_dir(struct mmc_data *data)
399{
400 if (data->flags & MMC_DATA_WRITE)
401 return DMA_TO_DEVICE;
402 else
403 return DMA_FROM_DEVICE;
404}
405
f95f3850
WN		 406static void dw_mci_dma_cleanup(struct dw_mci *host)
407{
408 struct mmc_data *data = host->data;
409
410 if (data)
9aa51408 411 if (!data->host_cookie)
4a90920c 412 dma_unmap_sg(host->dev,
9aa51408
SJ		 413 data->sg,
414 data->sg_len,
415 dw_mci_get_dma_dir(data));
f95f3850
WN		 416}
417
5ce9d961
SJ		 418static void dw_mci_idmac_reset(struct dw_mci *host)
419{
420 u32 bmod = mci_readl(host, BMOD);
421 /* Software reset of DMA */
422 bmod |= SDMMC_IDMAC_SWRESET;
423 mci_writel(host, BMOD, bmod);
424}
425
f95f3850
WN		 426static void dw_mci_idmac_stop_dma(struct dw_mci *host)
427{
428 u32 temp;
429
430 /* Disable and reset the IDMAC interface */
431 temp = mci_readl(host, CTRL);
432 temp &= ~SDMMC_CTRL_USE_IDMAC;
433 temp |= SDMMC_CTRL_DMA_RESET;
434 mci_writel(host, CTRL, temp);
435
436 /* Stop the IDMAC running */
437 temp = mci_readl(host, BMOD);
a5289a43 438 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
5ce9d961 439 temp |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 440 mci_writel(host, BMOD, temp);
441}
442
3fc7eaef 443static void dw_mci_dmac_complete_dma(void *arg)
f95f3850 444{
3fc7eaef 445 struct dw_mci *host = arg;
f95f3850
WN		 446 struct mmc_data *data = host->data;
447
4a90920c 448 dev_vdbg(host->dev, "DMA complete\n");
f95f3850 449
3fc7eaef
SL		 450 if ((host->use_dma == TRANS_MODE_EDMAC) &&
451 data && (data->flags & MMC_DATA_READ))
452 /* Invalidate cache after read */
453 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
454 data->sg,
455 data->sg_len,
456 DMA_FROM_DEVICE);
457
f95f3850
WN		 458 host->dma_ops->cleanup(host);
459
460 /*
461 * If the card was removed, data will be NULL. No point in trying to
462 * send the stop command or waiting for NBUSY in this case.
463 */
464 if (data) {
465 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
466 tasklet_schedule(&host->tasklet);
467 }
468}
469
3b2a067b
SL		 470static int dw_mci_idmac_init(struct dw_mci *host)
471{
472 int i;
473
474 if (host->dma_64bit_address == 1) {
475 struct idmac_desc_64addr *p;
476 /* Number of descriptors in the ring buffer */
477 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
478
479 /* Forward link the descriptor list */
480 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
481 i++, p++) {
482 p->des6 = (host->sg_dma +
483 (sizeof(struct idmac_desc_64addr) *
484 (i + 1))) & 0xffffffff;
485
486 p->des7 = (u64)(host->sg_dma +
487 (sizeof(struct idmac_desc_64addr) *
488 (i + 1))) >> 32;
489 /* Initialize reserved and buffer size fields to "0" */
490 p->des1 = 0;
491 p->des2 = 0;
492 p->des3 = 0;
493 }
494
495 /* Set the last descriptor as the end-of-ring descriptor */
496 p->des6 = host->sg_dma & 0xffffffff;
497 p->des7 = (u64)host->sg_dma >> 32;
498 p->des0 = IDMAC_DES0_ER;
499
500 } else {
501 struct idmac_desc *p;
502 /* Number of descriptors in the ring buffer */
503 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
504
505 /* Forward link the descriptor list */
506 for (i = 0, p = host->sg_cpu;
507 i < host->ring_size - 1;
508 i++, p++) {
509 p->des3 = cpu_to_le32(host->sg_dma +
510 (sizeof(struct idmac_desc) * (i + 1)));
511 p->des1 = 0;
512 }
513
514 /* Set the last descriptor as the end-of-ring descriptor */
515 p->des3 = cpu_to_le32(host->sg_dma);
516 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
517 }
518
519 dw_mci_idmac_reset(host);
520
521 if (host->dma_64bit_address == 1) {
522 /* Mask out interrupts - get Tx & Rx complete only */
523 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
524 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
525 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
526
527 /* Set the descriptor base address */
528 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
529 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
530
531 } else {
532 /* Mask out interrupts - get Tx & Rx complete only */
533 mci_writel(host, IDSTS, IDMAC_INT_CLR);
534 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
535 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
536
537 /* Set the descriptor base address */
538 mci_writel(host, DBADDR, host->sg_dma);
539 }
540
541 return 0;
542}
543
544static inline int dw_mci_prepare_desc64(struct dw_mci *host,
ec0baaa6
SL		 545 struct mmc_data *data,
546 unsigned int sg_len)
f95f3850 547{
5959b32e 548 unsigned int desc_len;
ec0baaa6 549 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
3b2a067b 550 unsigned long timeout;
f95f3850 551 int i;
0e3a22c0 552
ec0baaa6 553 desc_first = desc_last = desc = host->sg_cpu;
5959b32e 554
ec0baaa6
SL		 555 for (i = 0; i < sg_len; i++) {
556 unsigned int length = sg_dma_len(&data->sg[i]);
69d99fdc 557
ec0baaa6 558 u64 mem_addr = sg_dma_address(&data->sg[i]);
0e3a22c0 559
ec0baaa6
SL		 560 for ( ; length ; desc++) {
561 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
562 length : DW_MCI_DESC_DATA_LENGTH;
f95f3850 563
ec0baaa6 564 length -= desc_len;
5959b32e 565
3b2a067b
SL		 566 /*
567 * Wait for the former clear OWN bit operation
568 * of IDMAC to make sure that this descriptor
569 * isn't still owned by IDMAC as IDMAC's write
570 * ops and CPU's read ops are asynchronous.
571 */
572 timeout = jiffies + msecs_to_jiffies(100);
573 while (readl(&desc->des0) & IDMAC_DES0_OWN) {
574 if (time_after(jiffies, timeout))
575 goto err_own_bit;
576 udelay(10);
577 }
578
ec0baaa6
SL		 579 /*
580 * Set the OWN bit and disable interrupts
581 * for this descriptor
582 */
583 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
584 IDMAC_DES0_CH;
5959b32e 585
ec0baaa6
SL		 586 /* Buffer length */
587 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
5959b32e 588
ec0baaa6
SL		 589 /* Physical address to DMA to/from */
590 desc->des4 = mem_addr & 0xffffffff;
591 desc->des5 = mem_addr >> 32;
5959b32e 592
ec0baaa6
SL		 593 /* Update physical address for the next desc */
594 mem_addr += desc_len;
5959b32e 595
ec0baaa6
SL		 596 /* Save pointer to the last descriptor */
597 desc_last = desc;
69d99fdc 598 }
ec0baaa6 599 }
f95f3850 600
ec0baaa6
SL		 601 /* Set first descriptor */
602 desc_first->des0 |= IDMAC_DES0_FD;
f95f3850 603
ec0baaa6
SL		 604 /* Set last descriptor */
605 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
606 desc_last->des0 |= IDMAC_DES0_LD;
3b2a067b
SL		 607
608 return 0;
609err_own_bit:
610 /* restore the descriptor chain as it's polluted */
611 dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
612 memset(host->sg_cpu, 0, PAGE_SIZE);
613 dw_mci_idmac_init(host);
614 return -EINVAL;
ec0baaa6 615}
5959b32e 616
69d99fdc 617
3b2a067b 618static inline int dw_mci_prepare_desc32(struct dw_mci *host,
ec0baaa6
SL		 619 struct mmc_data *data,
620 unsigned int sg_len)
621{
622 unsigned int desc_len;
623 struct idmac_desc *desc_first, *desc_last, *desc;
3b2a067b 624 unsigned long timeout;
ec0baaa6 625 int i;
0e3a22c0 626
ec0baaa6 627 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 628
ec0baaa6
SL		 629 for (i = 0; i < sg_len; i++) {
630 unsigned int length = sg_dma_len(&data->sg[i]);
5959b32e 631
ec0baaa6 632 u32 mem_addr = sg_dma_address(&data->sg[i]);
5959b32e 633
ec0baaa6
SL		 634 for ( ; length ; desc++) {
635 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
636 length : DW_MCI_DESC_DATA_LENGTH;
5959b32e 637
ec0baaa6 638 length -= desc_len;
f95f3850 639
3b2a067b
SL		 640 /*
641 * Wait for the former clear OWN bit operation
642 * of IDMAC to make sure that this descriptor
643 * isn't still owned by IDMAC as IDMAC's write
644 * ops and CPU's read ops are asynchronous.
645 */
646 timeout = jiffies + msecs_to_jiffies(100);
647 while (readl(&desc->des0) &
648 cpu_to_le32(IDMAC_DES0_OWN)) {
649 if (time_after(jiffies, timeout))
650 goto err_own_bit;
651 udelay(10);
652 }
653
ec0baaa6
SL		 654 /*
655 * Set the OWN bit and disable interrupts
656 * for this descriptor
657 */
658 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
659 IDMAC_DES0_DIC |
660 IDMAC_DES0_CH);
5959b32e 661
ec0baaa6
SL		 662 /* Buffer length */
663 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
5959b32e 664
ec0baaa6
SL		 665 /* Physical address to DMA to/from */
666 desc->des2 = cpu_to_le32(mem_addr);
69d99fdc 667
ec0baaa6
SL		 668 /* Update physical address for the next desc */
669 mem_addr += desc_len;
f95f3850 670
ec0baaa6
SL		 671 /* Save pointer to the last descriptor */
672 desc_last = desc;
673 }
69d99fdc 674 }
f95f3850 675
ec0baaa6
SL		 676 /* Set first descriptor */
677 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
678
679 /* Set last descriptor */
680 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
681 IDMAC_DES0_DIC));
682 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
3b2a067b
SL		 683
684 return 0;
685err_own_bit:
686 /* restore the descriptor chain as it's polluted */
687 dev_dbg(host->dev, "desciptor is still owned by IDMAC.\n");
688 memset(host->sg_cpu, 0, PAGE_SIZE);
689 dw_mci_idmac_init(host);
690 return -EINVAL;
f95f3850
WN		 691}
692
3fc7eaef 693static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
f95f3850
WN		 694{
695 u32 temp;
3b2a067b 696 int ret;
f95f3850 697
ec0baaa6 698 if (host->dma_64bit_address == 1)
3b2a067b 699 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
ec0baaa6 700 else
3b2a067b
SL		 701 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
702
703 if (ret)
704 goto out;
ec0baaa6
SL		 705
706 /* drain writebuffer */
707 wmb();
f95f3850 708
536f6b91
SR		 709 /* Make sure to reset DMA in case we did PIO before this */
710 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
711 dw_mci_idmac_reset(host);
712
f95f3850
WN		 713 /* Select IDMAC interface */
714 temp = mci_readl(host, CTRL);
715 temp |= SDMMC_CTRL_USE_IDMAC;
716 mci_writel(host, CTRL, temp);
717
0e3a22c0 718 /* drain writebuffer */
f95f3850
WN		 719 wmb();
720
721 /* Enable the IDMAC */
722 temp = mci_readl(host, BMOD);
a5289a43 723 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 724 mci_writel(host, BMOD, temp);
725
726 /* Start it running */
727 mci_writel(host, PLDMND, 1);
3fc7eaef 728
3b2a067b
SL		 729out:
730 return ret;
f95f3850
WN		 731}
732
8e2b36ea 733static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 734 .init = dw_mci_idmac_init,
735 .start = dw_mci_idmac_start_dma,
736 .stop = dw_mci_idmac_stop_dma,
3fc7eaef
SL		 737 .complete = dw_mci_dmac_complete_dma,
738 .cleanup = dw_mci_dma_cleanup,
739};
740
741static void dw_mci_edmac_stop_dma(struct dw_mci *host)
742{
ab925a31 743 dmaengine_terminate_async(host->dms->ch);
3fc7eaef
SL		 744}
745
746static int dw_mci_edmac_start_dma(struct dw_mci *host,
747 unsigned int sg_len)
748{
749 struct dma_slave_config cfg;
750 struct dma_async_tx_descriptor *desc = NULL;
751 struct scatterlist *sgl = host->data->sg;
752 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
753 u32 sg_elems = host->data->sg_len;
754 u32 fifoth_val;
755 u32 fifo_offset = host->fifo_reg - host->regs;
756 int ret = 0;
757
758 /* Set external dma config: burst size, burst width */
260b3164 759 cfg.dst_addr = host->phy_regs + fifo_offset;
3fc7eaef
SL		 760 cfg.src_addr = cfg.dst_addr;
761 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
762 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
763
764 /* Match burst msize with external dma config */
765 fifoth_val = mci_readl(host, FIFOTH);
766 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
767 cfg.src_maxburst = cfg.dst_maxburst;
768
769 if (host->data->flags & MMC_DATA_WRITE)
770 cfg.direction = DMA_MEM_TO_DEV;
771 else
772 cfg.direction = DMA_DEV_TO_MEM;
773
774 ret = dmaengine_slave_config(host->dms->ch, &cfg);
775 if (ret) {
776 dev_err(host->dev, "Failed to config edmac.\n");
777 return -EBUSY;
778 }
779
780 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
781 sg_len, cfg.direction,
782 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
783 if (!desc) {
784 dev_err(host->dev, "Can't prepare slave sg.\n");
785 return -EBUSY;
786 }
787
788 /* Set dw_mci_dmac_complete_dma as callback */
789 desc->callback = dw_mci_dmac_complete_dma;
790 desc->callback_param = (void *)host;
791 dmaengine_submit(desc);
792
793 /* Flush cache before write */
794 if (host->data->flags & MMC_DATA_WRITE)
795 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
796 sg_elems, DMA_TO_DEVICE);
797
798 dma_async_issue_pending(host->dms->ch);
799
800 return 0;
801}
802
803static int dw_mci_edmac_init(struct dw_mci *host)
804{
805 /* Request external dma channel */
806 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
807 if (!host->dms)
808 return -ENOMEM;
809
810 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
811 if (!host->dms->ch) {
4539d36e 812 dev_err(host->dev, "Failed to get external DMA channel.\n");
3fc7eaef
SL		 813 kfree(host->dms);
814 host->dms = NULL;
815 return -ENXIO;
816 }
817
818 return 0;
819}
820
821static void dw_mci_edmac_exit(struct dw_mci *host)
822{
823 if (host->dms) {
824 if (host->dms->ch) {
825 dma_release_channel(host->dms->ch);
826 host->dms->ch = NULL;
827 }
828 kfree(host->dms);
829 host->dms = NULL;
830 }
831}
832
833static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
834 .init = dw_mci_edmac_init,
835 .exit = dw_mci_edmac_exit,
836 .start = dw_mci_edmac_start_dma,
837 .stop = dw_mci_edmac_stop_dma,
838 .complete = dw_mci_dmac_complete_dma,
885c3e80
SJ		 839 .cleanup = dw_mci_dma_cleanup,
840};
885c3e80 841
9aa51408
SJ		 842static int dw_mci_pre_dma_transfer(struct dw_mci *host,
843 struct mmc_data *data,
844 bool next)
f95f3850
WN		 845{
846 struct scatterlist *sg;
9aa51408 847 unsigned int i, sg_len;
03e8cb53 848
9aa51408
SJ		 849 if (!next && data->host_cookie)
850 return data->host_cookie;
f95f3850
WN		 851
852 /*
853 * We don't do DMA on "complex" transfers, i.e. with
854 * non-word-aligned buffers or lengths. Also, we don't bother
855 * with all the DMA setup overhead for short transfers.
856 */
857 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
858 return -EINVAL;
9aa51408 859
f95f3850
WN		 860 if (data->blksz & 3)
861 return -EINVAL;
862
863 for_each_sg(data->sg, sg, data->sg_len, i) {
864 if (sg->offset & 3 || sg->length & 3)
865 return -EINVAL;
866 }
867
4a90920c 868 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 869 data->sg,
870 data->sg_len,
871 dw_mci_get_dma_dir(data));
872 if (sg_len == 0)
873 return -EINVAL;
03e8cb53 874
9aa51408
SJ		 875 if (next)
876 data->host_cookie = sg_len;
f95f3850 877
9aa51408
SJ		 878 return sg_len;
879}
880
9aa51408
SJ		 881static void dw_mci_pre_req(struct mmc_host *mmc,
882 struct mmc_request *mrq,
883 bool is_first_req)
884{
885 struct dw_mci_slot *slot = mmc_priv(mmc);
886 struct mmc_data *data = mrq->data;
887
888 if (!slot->host->use_dma || !data)
889 return;
890
891 if (data->host_cookie) {
892 data->host_cookie = 0;
893 return;
894 }
895
896 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
897 data->host_cookie = 0;
898}
899
900static void dw_mci_post_req(struct mmc_host *mmc,
901 struct mmc_request *mrq,
902 int err)
903{
904 struct dw_mci_slot *slot = mmc_priv(mmc);
905 struct mmc_data *data = mrq->data;
906
907 if (!slot->host->use_dma || !data)
908 return;
909
910 if (data->host_cookie)
4a90920c 911 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 912 data->sg,
913 data->sg_len,
914 dw_mci_get_dma_dir(data));
915 data->host_cookie = 0;
916}
917
52426899
SJ		 918static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
919{
52426899
SJ		 920 unsigned int blksz = data->blksz;
921 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
922 u32 fifo_width = 1 << host->data_shift;
923 u32 blksz_depth = blksz / fifo_width, fifoth_val;
924 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
0e3a22c0 925 int idx = ARRAY_SIZE(mszs) - 1;
52426899 926
3fc7eaef
SL		 927 /* pio should ship this scenario */
928 if (!host->use_dma)
929 return;
930
52426899
SJ		 931 tx_wmark = (host->fifo_depth) / 2;
932 tx_wmark_invers = host->fifo_depth - tx_wmark;
933
934 /*
935 * MSIZE is '1',
936 * if blksz is not a multiple of the FIFO width
937 */
938 if (blksz % fifo_width) {
939 msize = 0;
940 rx_wmark = 1;
941 goto done;
942 }
943
944 do {
945 if (!((blksz_depth % mszs[idx]) ||
946 (tx_wmark_invers % mszs[idx]))) {
947 msize = idx;
948 rx_wmark = mszs[idx] - 1;
949 break;
950 }
951 } while (--idx > 0);
952 /*
953 * If idx is '0', it won't be tried
954 * Thus, initial values are uesed
955 */
956done:
957 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
958 mci_writel(host, FIFOTH, fifoth_val);
52426899
SJ		 959}
960
7e4bf1bc 961static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
f1d2736c
SJ		 962{
963 unsigned int blksz = data->blksz;
964 u32 blksz_depth, fifo_depth;
965 u16 thld_size;
7e4bf1bc 966 u8 enable;
f1d2736c 967
66dfd101
JH		 968 /*
969 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
970 * in the FIFO region, so we really shouldn't access it).
971 */
7e4bf1bc
JC		 972 if (host->verid < DW_MMC_240A ||
973 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
974 return;
975
976 /*
977 * Card write Threshold is introduced since 2.80a
978 * It's used when HS400 mode is enabled.
979 */
980 if (data->flags & MMC_DATA_WRITE &&
981 !(host->timing != MMC_TIMING_MMC_HS400))
66dfd101
JH		 982 return;
983
7e4bf1bc
JC		 984 if (data->flags & MMC_DATA_WRITE)
985 enable = SDMMC_CARD_WR_THR_EN;
986 else
987 enable = SDMMC_CARD_RD_THR_EN;
988
f1d2736c
SJ		 989 if (host->timing != MMC_TIMING_MMC_HS200 &&
990 host->timing != MMC_TIMING_UHS_SDR104)
991 goto disable;
992
993 blksz_depth = blksz / (1 << host->data_shift);
994 fifo_depth = host->fifo_depth;
995
996 if (blksz_depth > fifo_depth)
997 goto disable;
998
999 /*
1000 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1001 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1002 * Currently just choose blksz.
1003 */
1004 thld_size = blksz;
7e4bf1bc 1005 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
f1d2736c
SJ		 1006 return;
1007
1008disable:
7e4bf1bc 1009 mci_writel(host, CDTHRCTL, 0);
f1d2736c
SJ		 1010}
1011
9aa51408
SJ		 1012static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1013{
f8c58c11 1014 unsigned long irqflags;
9aa51408
SJ		 1015 int sg_len;
1016 u32 temp;
1017
1018 host->using_dma = 0;
1019
1020 /* If we don't have a channel, we can't do DMA */
1021 if (!host->use_dma)
1022 return -ENODEV;
1023
1024 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 1025 if (sg_len < 0) {
1026 host->dma_ops->stop(host);
9aa51408 1027 return sg_len;
a99aa9b9 1028 }
9aa51408
SJ		 1029
1030 host->using_dma = 1;
f95f3850 1031
3fc7eaef
SL		 1032 if (host->use_dma == TRANS_MODE_IDMAC)
1033 dev_vdbg(host->dev,
1034 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1035 (unsigned long)host->sg_cpu,
1036 (unsigned long)host->sg_dma,
1037 sg_len);
f95f3850 1038
52426899
SJ		 1039 /*
1040 * Decide the MSIZE and RX/TX Watermark.
1041 * If current block size is same with previous size,
1042 * no need to update fifoth.
1043 */
1044 if (host->prev_blksz != data->blksz)
1045 dw_mci_adjust_fifoth(host, data);
1046
f95f3850
WN		 1047 /* Enable the DMA interface */
1048 temp = mci_readl(host, CTRL);
1049 temp |= SDMMC_CTRL_DMA_ENABLE;
1050 mci_writel(host, CTRL, temp);
1051
1052 /* Disable RX/TX IRQs, let DMA handle it */
f8c58c11 1053 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1054 temp = mci_readl(host, INTMASK);
1055 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1056 mci_writel(host, INTMASK, temp);
f8c58c11 1057 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850 1058
3fc7eaef
SL		 1059 if (host->dma_ops->start(host, sg_len)) {
1060 /* We can't do DMA */
1061 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
1062 return -ENODEV;
1063 }
f95f3850
WN		 1064
1065 return 0;
1066}
1067
1068static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1069{
f8c58c11 1070 unsigned long irqflags;
0e3a22c0 1071 int flags = SG_MITER_ATOMIC;
f95f3850
WN		 1072 u32 temp;
1073
1074 data->error = -EINPROGRESS;
1075
1076 WARN_ON(host->data);
1077 host->sg = NULL;
1078 host->data = data;
1079
7e4bf1bc 1080 if (data->flags & MMC_DATA_READ)
55c5efbc 1081 host->dir_status = DW_MCI_RECV_STATUS;
7e4bf1bc 1082 else
55c5efbc 1083 host->dir_status = DW_MCI_SEND_STATUS;
7e4bf1bc
JC		 1084
1085 dw_mci_ctrl_thld(host, data);
55c5efbc 1086
f95f3850 1087 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 1088 if (host->data->flags & MMC_DATA_READ)
1089 flags |= SG_MITER_TO_SG;
1090 else
1091 flags |= SG_MITER_FROM_SG;
1092
1093 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 1094 host->sg = data->sg;
34b664a2
JH		 1095 host->part_buf_start = 0;
1096 host->part_buf_count = 0;
f95f3850 1097
b40af3aa 1098 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f8c58c11
DA		 1099
1100 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1101 temp = mci_readl(host, INTMASK);
1102 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1103 mci_writel(host, INTMASK, temp);
f8c58c11 1104 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 1105
1106 temp = mci_readl(host, CTRL);
1107 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1108 mci_writel(host, CTRL, temp);
52426899
SJ		 1109
1110 /*
1111 * Use the initial fifoth_val for PIO mode.
1112 * If next issued data may be transfered by DMA mode,
1113 * prev_blksz should be invalidated.
1114 */
1115 mci_writel(host, FIFOTH, host->fifoth_val);
1116 host->prev_blksz = 0;
1117 } else {
1118 /*
1119 * Keep the current block size.
1120 * It will be used to decide whether to update
1121 * fifoth register next time.
1122 */
1123 host->prev_blksz = data->blksz;
f95f3850
WN		 1124 }
1125}
1126
1127static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1128{
1129 struct dw_mci *host = slot->host;
1130 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1131 unsigned int cmd_status = 0;
1132
1133 mci_writel(host, CMDARG, arg);
0e3a22c0 1134 wmb(); /* drain writebuffer */
0bdbd0e8 1135 dw_mci_wait_while_busy(host, cmd);
f95f3850
WN		 1136 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1137
1138 while (time_before(jiffies, timeout)) {
1139 cmd_status = mci_readl(host, CMD);
1140 if (!(cmd_status & SDMMC_CMD_START))
1141 return;
1142 }
1143 dev_err(&slot->mmc->class_dev,
1144 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1145 cmd, arg, cmd_status);
1146}
1147
ab269128 1148static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 1149{
1150 struct dw_mci *host = slot->host;
fdf492a1 1151 unsigned int clock = slot->clock;
f95f3850 1152 u32 div;
9623b5b9 1153 u32 clk_en_a;
01730558
DA		 1154 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1155
1156 /* We must continue to set bit 28 in CMD until the change is complete */
1157 if (host->state == STATE_WAITING_CMD11_DONE)
1158 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
f95f3850 1159
fdf492a1
DA		 1160 if (!clock) {
1161 mci_writel(host, CLKENA, 0);
01730558 1162 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
fdf492a1
DA		 1163 } else if (clock != host->current_speed || force_clkinit) {
1164 div = host->bus_hz / clock;
1165 if (host->bus_hz % clock && host->bus_hz > clock)
f95f3850
WN		 1166 /*
1167 * move the + 1 after the divide to prevent
1168 * over-clocking the card.
1169 */
e419990b
SJ		 1170 div += 1;
1171
fdf492a1 1172 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850 1173
005d675a
JC		 1174 if (clock != slot->__clk_old || force_clkinit)
1175 dev_info(&slot->mmc->class_dev,
1176 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1177 slot->id, host->bus_hz, clock,
1178 div ? ((host->bus_hz / div) >> 1) :
1179 host->bus_hz, div);
f95f3850
WN		 1180
1181 /* disable clock */
1182 mci_writel(host, CLKENA, 0);
1183 mci_writel(host, CLKSRC, 0);
1184
1185 /* inform CIU */
01730558 1186 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850
WN		 1187
1188 /* set clock to desired speed */
1189 mci_writel(host, CLKDIV, div);
1190
1191 /* inform CIU */
01730558 1192 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1193
9623b5b9
DA		 1194 /* enable clock; only low power if no SDIO */
1195 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
b24c8b26 1196 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
9623b5b9
DA		 1197 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1198 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 1199
1200 /* inform CIU */
01730558 1201 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
005d675a
JC		 1202
1203 /* keep the last clock value that was requested from core */
1204 slot->__clk_old = clock;
f95f3850
WN		 1205 }
1206
fdf492a1
DA		 1207 host->current_speed = clock;
1208
f95f3850 1209 /* Set the current slot bus width */
1d56c453 1210 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 1211}
1212
053b3ce6
SJ		 1213static void __dw_mci_start_request(struct dw_mci *host,
1214 struct dw_mci_slot *slot,
1215 struct mmc_command *cmd)
f95f3850
WN		 1216{
1217 struct mmc_request *mrq;
f95f3850
WN		 1218 struct mmc_data *data;
1219 u32 cmdflags;
1220
1221 mrq = slot->mrq;
f95f3850 1222
f95f3850
WN		 1223 host->cur_slot = slot;
1224 host->mrq = mrq;
1225
1226 host->pending_events = 0;
1227 host->completed_events = 0;
e352c813 1228 host->cmd_status = 0;
f95f3850 1229 host->data_status = 0;
e352c813 1230 host->dir_status = 0;
f95f3850 1231
053b3ce6 1232 data = cmd->data;
f95f3850 1233 if (data) {
f16afa88 1234 mci_writel(host, TMOUT, 0xFFFFFFFF);
f95f3850
WN		 1235 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1236 mci_writel(host, BLKSIZ, data->blksz);
1237 }
1238
f95f3850
WN		 1239 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1240
1241 /* this is the first command, send the initialization clock */
1242 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1243 cmdflags |= SDMMC_CMD_INIT;
1244
1245 if (data) {
1246 dw_mci_submit_data(host, data);
0e3a22c0 1247 wmb(); /* drain writebuffer */
f95f3850
WN		 1248 }
1249
1250 dw_mci_start_command(host, cmd, cmdflags);
1251
5c935165 1252 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
49ba0302
DA		 1253 unsigned long irqflags;
1254
5c935165 1255 /*
8886a6fd
DA		 1256 * Databook says to fail after 2ms w/ no response, but evidence
1257 * shows that sometimes the cmd11 interrupt takes over 130ms.
1258 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1259 * is just about to roll over.
49ba0302
DA		 1260 *
1261 * We do this whole thing under spinlock and only if the
1262 * command hasn't already completed (indicating the the irq
1263 * already ran so we don't want the timeout).
5c935165 1264 */
49ba0302
DA		 1265 spin_lock_irqsave(&host->irq_lock, irqflags);
1266 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1267 mod_timer(&host->cmd11_timer,
1268 jiffies + msecs_to_jiffies(500) + 1);
1269 spin_unlock_irqrestore(&host->irq_lock, irqflags);
5c935165
DA		 1270 }
1271
f95f3850
WN		 1272 if (mrq->stop)
1273 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
90c2143a
SJ		 1274 else
1275 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
f95f3850
WN		 1276}
1277
053b3ce6
SJ		 1278static void dw_mci_start_request(struct dw_mci *host,
1279 struct dw_mci_slot *slot)
1280{
1281 struct mmc_request *mrq = slot->mrq;
1282 struct mmc_command *cmd;
1283
1284 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1285 __dw_mci_start_request(host, slot, cmd);
1286}
1287
7456caae 1288/* must be called with host->lock held */
f95f3850
WN		 1289static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1290 struct mmc_request *mrq)
1291{
1292 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1293 host->state);
1294
f95f3850
WN		 1295 slot->mrq = mrq;
1296
01730558
DA		 1297 if (host->state == STATE_WAITING_CMD11_DONE) {
1298 dev_warn(&slot->mmc->class_dev,
1299 "Voltage change didn't complete\n");
1300 /*
1301 * this case isn't expected to happen, so we can
1302 * either crash here or just try to continue on
1303 * in the closest possible state
1304 */
1305 host->state = STATE_IDLE;
1306 }
1307
f95f3850
WN		 1308 if (host->state == STATE_IDLE) {
1309 host->state = STATE_SENDING_CMD;
1310 dw_mci_start_request(host, slot);
1311 } else {
1312 list_add_tail(&slot->queue_node, &host->queue);
1313 }
f95f3850
WN		 1314}
1315
1316static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1317{
1318 struct dw_mci_slot *slot = mmc_priv(mmc);
1319 struct dw_mci *host = slot->host;
1320
1321 WARN_ON(slot->mrq);
1322
7456caae
JH		 1323 /*
1324 * The check for card presence and queueing of the request must be
1325 * atomic, otherwise the card could be removed in between and the
1326 * request wouldn't fail until another card was inserted.
1327 */
7456caae 1328
56f6911c 1329 if (!dw_mci_get_cd(mmc)) {
f95f3850
WN		 1330 mrq->cmd->error = -ENOMEDIUM;
1331 mmc_request_done(mmc, mrq);
1332 return;
1333 }
1334
56f6911c
SL		 1335 spin_lock_bh(&host->lock);
1336
f95f3850 1337 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 1338
1339 spin_unlock_bh(&host->lock);
f95f3850
WN		 1340}
1341
1342static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1343{
1344 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 1345 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 1346 u32 regs;
51da2240 1347 int ret;
f95f3850 1348
f95f3850 1349 switch (ios->bus_width) {
f95f3850
WN		 1350 case MMC_BUS_WIDTH_4:
1351 slot->ctype = SDMMC_CTYPE_4BIT;
1352 break;
c9b2a06f
JC		 1353 case MMC_BUS_WIDTH_8:
1354 slot->ctype = SDMMC_CTYPE_8BIT;
1355 break;
b2f7cb45
JC		 1356 default:
1357 /* set default 1 bit mode */
1358 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 1359 }
1360
3f514291
SJ		 1361 regs = mci_readl(slot->host, UHS_REG);
1362
41babf75 1363 /* DDR mode set */
80113132 1364 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
7cc8d580 1365 ios->timing == MMC_TIMING_UHS_DDR50 ||
80113132 1366 ios->timing == MMC_TIMING_MMC_HS400)
c69042a5 1367 regs |= ((0x1 << slot->id) << 16);
3f514291 1368 else
c69042a5 1369 regs &= ~((0x1 << slot->id) << 16);
3f514291
SJ		 1370
1371 mci_writel(slot->host, UHS_REG, regs);
f1d2736c 1372 slot->host->timing = ios->timing;
41babf75 1373
fdf492a1
DA		 1374 /*
1375 * Use mirror of ios->clock to prevent race with mmc
1376 * core ios update when finding the minimum.
1377 */
1378 slot->clock = ios->clock;
f95f3850 1379
cb27a843
JH		 1380 if (drv_data && drv_data->set_ios)
1381 drv_data->set_ios(slot->host, ios);
800d78bf 1382
f95f3850
WN		 1383 switch (ios->power_mode) {
1384 case MMC_POWER_UP:
51da2240
YC		 1385 if (!IS_ERR(mmc->supply.vmmc)) {
1386 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1387 ios->vdd);
1388 if (ret) {
1389 dev_err(slot->host->dev,
1390 "failed to enable vmmc regulator\n");
1391 /*return, if failed turn on vmmc*/
1392 return;
1393 }
1394 }
29d0d161
DA		 1395 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1396 regs = mci_readl(slot->host, PWREN);
1397 regs |= (1 << slot->id);
1398 mci_writel(slot->host, PWREN, regs);
1399 break;
1400 case MMC_POWER_ON:
d1f1dd86
DA		 1401 if (!slot->host->vqmmc_enabled) {
1402 if (!IS_ERR(mmc->supply.vqmmc)) {
1403 ret = regulator_enable(mmc->supply.vqmmc);
1404 if (ret < 0)
1405 dev_err(slot->host->dev,
1406 "failed to enable vqmmc\n");
1407 else
1408 slot->host->vqmmc_enabled = true;
1409
1410 } else {
1411 /* Keep track so we don't reset again */
51da2240 1412 slot->host->vqmmc_enabled = true;
d1f1dd86
DA		 1413 }
1414
1415 /* Reset our state machine after powering on */
1416 dw_mci_ctrl_reset(slot->host,
1417 SDMMC_CTRL_ALL_RESET_FLAGS);
51da2240 1418 }
655babbd
DA		 1419
1420 /* Adjust clock / bus width after power is up */
1421 dw_mci_setup_bus(slot, false);
1422
e6f34e2f
JH		 1423 break;
1424 case MMC_POWER_OFF:
655babbd
DA		 1425 /* Turn clock off before power goes down */
1426 dw_mci_setup_bus(slot, false);
1427
51da2240
YC		 1428 if (!IS_ERR(mmc->supply.vmmc))
1429 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1430
d1f1dd86 1431 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
51da2240 1432 regulator_disable(mmc->supply.vqmmc);
d1f1dd86 1433 slot->host->vqmmc_enabled = false;
51da2240 1434
4366dcc5
JC		 1435 regs = mci_readl(slot->host, PWREN);
1436 regs &= ~(1 << slot->id);
1437 mci_writel(slot->host, PWREN, regs);
f95f3850
WN		 1438 break;
1439 default:
1440 break;
1441 }
655babbd
DA		 1442
1443 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1444 slot->host->state = STATE_IDLE;
f95f3850
WN		 1445}
1446
01730558
DA		 1447static int dw_mci_card_busy(struct mmc_host *mmc)
1448{
1449 struct dw_mci_slot *slot = mmc_priv(mmc);
1450 u32 status;
1451
1452 /*
1453 * Check the busy bit which is low when DAT[3:0]
1454 * (the data lines) are 0000
1455 */
1456 status = mci_readl(slot->host, STATUS);
1457
1458 return !!(status & SDMMC_STATUS_BUSY);
1459}
1460
1461static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1462{
1463 struct dw_mci_slot *slot = mmc_priv(mmc);
1464 struct dw_mci *host = slot->host;
8f7849c4 1465 const struct dw_mci_drv_data *drv_data = host->drv_data;
01730558
DA		 1466 u32 uhs;
1467 u32 v18 = SDMMC_UHS_18V << slot->id;
01730558
DA		 1468 int ret;
1469
8f7849c4
ZG		 1470 if (drv_data && drv_data->switch_voltage)
1471 return drv_data->switch_voltage(mmc, ios);
1472
01730558
DA		 1473 /*
1474 * Program the voltage. Note that some instances of dw_mmc may use
1475 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1476 * does no harm but you need to set the regulator directly. Try both.
1477 */
1478 uhs = mci_readl(host, UHS_REG);
e0848f5d 1479 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
01730558 1480 uhs &= ~v18;
e0848f5d 1481 else
01730558 1482 uhs |= v18;
e0848f5d 1483
01730558 1484 if (!IS_ERR(mmc->supply.vqmmc)) {
e0848f5d 1485 ret = mmc_regulator_set_vqmmc(mmc, ios);
01730558
DA		 1486
1487 if (ret) {
b19caf37 1488 dev_dbg(&mmc->class_dev,
e0848f5d
DA		 1489 "Regulator set error %d - %s V\n",
1490 ret, uhs & v18 ? "1.8" : "3.3");
01730558
DA		 1491 return ret;
1492 }
1493 }
1494 mci_writel(host, UHS_REG, uhs);
1495
1496 return 0;
1497}
1498
f95f3850
WN		 1499static int dw_mci_get_ro(struct mmc_host *mmc)
1500{
1501 int read_only;
1502 struct dw_mci_slot *slot = mmc_priv(mmc);
9795a846 1503 int gpio_ro = mmc_gpio_get_ro(mmc);
f95f3850
WN		 1504
1505 /* Use platform get_ro function, else try on board write protect */
287980e4 1506 if (gpio_ro >= 0)
9795a846 1507 read_only = gpio_ro;
f95f3850
WN		 1508 else
1509 read_only =
1510 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1511
1512 dev_dbg(&mmc->class_dev, "card is %s\n",
1513 read_only ? "read-only" : "read-write");
1514
1515 return read_only;
1516}
1517
1518static int dw_mci_get_cd(struct mmc_host *mmc)
1519{
1520 int present;
1521 struct dw_mci_slot *slot = mmc_priv(mmc);
7cf347bd
ZG		 1522 struct dw_mci *host = slot->host;
1523 int gpio_cd = mmc_gpio_get_cd(mmc);
f95f3850
WN		 1524
1525 /* Use platform get_cd function, else try onboard card detect */
860951c5 1526 if ((mmc->caps & MMC_CAP_NEEDS_POLL) || !mmc_card_is_removable(mmc))
fc3d7720 1527 present = 1;
287980e4 1528 else if (gpio_cd >= 0)
7cf347bd 1529 present = gpio_cd;
f95f3850
WN		 1530 else
1531 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1532 == 0 ? 1 : 0;
1533
7cf347bd 1534 spin_lock_bh(&host->lock);
bf626e55
ZG		 1535 if (present) {
1536 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1537 dev_dbg(&mmc->class_dev, "card is present\n");
bf626e55
ZG		 1538 } else {
1539 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1540 dev_dbg(&mmc->class_dev, "card is not present\n");
bf626e55 1541 }
7cf347bd 1542 spin_unlock_bh(&host->lock);
f95f3850
WN		 1543
1544 return present;
1545}
1546
935a665e
SL		 1547static void dw_mci_hw_reset(struct mmc_host *mmc)
1548{
1549 struct dw_mci_slot *slot = mmc_priv(mmc);
1550 struct dw_mci *host = slot->host;
1551 int reset;
1552
1553 if (host->use_dma == TRANS_MODE_IDMAC)
1554 dw_mci_idmac_reset(host);
1555
1556 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1557 SDMMC_CTRL_FIFO_RESET))
1558 return;
1559
1560 /*
1561 * According to eMMC spec, card reset procedure:
1562 * tRstW >= 1us: RST_n pulse width
1563 * tRSCA >= 200us: RST_n to Command time
1564 * tRSTH >= 1us: RST_n high period
1565 */
1566 reset = mci_readl(host, RST_N);
1567 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1568 mci_writel(host, RST_N, reset);
1569 usleep_range(1, 2);
1570 reset |= SDMMC_RST_HWACTIVE << slot->id;
1571 mci_writel(host, RST_N, reset);
1572 usleep_range(200, 300);
1573}
1574
b24c8b26 1575static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
9623b5b9 1576{
b24c8b26 1577 struct dw_mci_slot *slot = mmc_priv(mmc);
9623b5b9 1578 struct dw_mci *host = slot->host;
9623b5b9 1579
b24c8b26
DA		 1580 /*
1581 * Low power mode will stop the card clock when idle. According to the
1582 * description of the CLKENA register we should disable low power mode
1583 * for SDIO cards if we need SDIO interrupts to work.
1584 */
1585 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1586 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1587 u32 clk_en_a_old;
1588 u32 clk_en_a;
9623b5b9 1589
b24c8b26
DA		 1590 clk_en_a_old = mci_readl(host, CLKENA);
1591
1592 if (card->type == MMC_TYPE_SDIO ||
1593 card->type == MMC_TYPE_SD_COMBO) {
1594 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1595 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1596 } else {
1597 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1598 clk_en_a = clk_en_a_old | clken_low_pwr;
1599 }
1600
1601 if (clk_en_a != clk_en_a_old) {
1602 mci_writel(host, CLKENA, clk_en_a);
1603 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1604 SDMMC_CMD_PRV_DAT_WAIT, 0);
1605 }
9623b5b9
DA		 1606 }
1607}
1608
1a5c8e1f
SH		 1609static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1610{
1611 struct dw_mci_slot *slot = mmc_priv(mmc);
1612 struct dw_mci *host = slot->host;
f8c58c11 1613 unsigned long irqflags;
1a5c8e1f
SH		 1614 u32 int_mask;
1615
f8c58c11
DA		 1616 spin_lock_irqsave(&host->irq_lock, irqflags);
1617
1a5c8e1f
SH		 1618 /* Enable/disable Slot Specific SDIO interrupt */
1619 int_mask = mci_readl(host, INTMASK);
b24c8b26
DA		 1620 if (enb)
1621 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1622 else
1623 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1624 mci_writel(host, INTMASK, int_mask);
f8c58c11
DA		 1625
1626 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1a5c8e1f
SH		 1627}
1628
0976f16d
SJ		 1629static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1630{
1631 struct dw_mci_slot *slot = mmc_priv(mmc);
1632 struct dw_mci *host = slot->host;
1633 const struct dw_mci_drv_data *drv_data = host->drv_data;
0e3a22c0 1634 int err = -EINVAL;
0976f16d 1635
0976f16d 1636 if (drv_data && drv_data->execute_tuning)
9979dbe5 1637 err = drv_data->execute_tuning(slot, opcode);
0976f16d
SJ		 1638 return err;
1639}
1640
0e3a22c0
SL		 1641static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1642 struct mmc_ios *ios)
80113132
SJ		 1643{
1644 struct dw_mci_slot *slot = mmc_priv(mmc);
1645 struct dw_mci *host = slot->host;
1646 const struct dw_mci_drv_data *drv_data = host->drv_data;
1647
1648 if (drv_data && drv_data->prepare_hs400_tuning)
1649 return drv_data->prepare_hs400_tuning(host, ios);
1650
1651 return 0;
1652}
1653
f95f3850 1654static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 1655 .request = dw_mci_request,
9aa51408
SJ		 1656 .pre_req = dw_mci_pre_req,
1657 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 1658 .set_ios = dw_mci_set_ios,
1659 .get_ro = dw_mci_get_ro,
1660 .get_cd = dw_mci_get_cd,
935a665e 1661 .hw_reset = dw_mci_hw_reset,
1a5c8e1f 1662 .enable_sdio_irq = dw_mci_enable_sdio_irq,
0976f16d 1663 .execute_tuning = dw_mci_execute_tuning,
01730558
DA		 1664 .card_busy = dw_mci_card_busy,
1665 .start_signal_voltage_switch = dw_mci_switch_voltage,
b24c8b26 1666 .init_card = dw_mci_init_card,
80113132 1667 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
f95f3850
WN		 1668};
1669
1670static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1671 __releases(&host->lock)
1672 __acquires(&host->lock)
1673{
1674 struct dw_mci_slot *slot;
1675 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1676
1677 WARN_ON(host->cmd || host->data);
1678
1679 host->cur_slot->mrq = NULL;
1680 host->mrq = NULL;
1681 if (!list_empty(&host->queue)) {
1682 slot = list_entry(host->queue.next,
1683 struct dw_mci_slot, queue_node);
1684 list_del(&slot->queue_node);
4a90920c 1685 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 1686 mmc_hostname(slot->mmc));
1687 host->state = STATE_SENDING_CMD;
1688 dw_mci_start_request(host, slot);
1689 } else {
4a90920c 1690 dev_vdbg(host->dev, "list empty\n");
01730558
DA		 1691
1692 if (host->state == STATE_SENDING_CMD11)
1693 host->state = STATE_WAITING_CMD11_DONE;
1694 else
1695 host->state = STATE_IDLE;
f95f3850
WN		 1696 }
1697
1698 spin_unlock(&host->lock);
1699 mmc_request_done(prev_mmc, mrq);
1700 spin_lock(&host->lock);
1701}
1702
e352c813 1703static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
f95f3850
WN		 1704{
1705 u32 status = host->cmd_status;
1706
1707 host->cmd_status = 0;
1708
1709 /* Read the response from the card (up to 16 bytes) */
1710 if (cmd->flags & MMC_RSP_PRESENT) {
1711 if (cmd->flags & MMC_RSP_136) {
1712 cmd->resp[3] = mci_readl(host, RESP0);
1713 cmd->resp[2] = mci_readl(host, RESP1);
1714 cmd->resp[1] = mci_readl(host, RESP2);
1715 cmd->resp[0] = mci_readl(host, RESP3);
1716 } else {
1717 cmd->resp[0] = mci_readl(host, RESP0);
1718 cmd->resp[1] = 0;
1719 cmd->resp[2] = 0;
1720 cmd->resp[3] = 0;
1721 }
1722 }
1723
1724 if (status & SDMMC_INT_RTO)
1725 cmd->error = -ETIMEDOUT;
1726 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1727 cmd->error = -EILSEQ;
1728 else if (status & SDMMC_INT_RESP_ERR)
1729 cmd->error = -EIO;
1730 else
1731 cmd->error = 0;
1732
e352c813
SJ		 1733 return cmd->error;
1734}
1735
1736static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1737{
31bff450 1738 u32 status = host->data_status;
e352c813
SJ		 1739
1740 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1741 if (status & SDMMC_INT_DRTO) {
1742 data->error = -ETIMEDOUT;
1743 } else if (status & SDMMC_INT_DCRC) {
1744 data->error = -EILSEQ;
1745 } else if (status & SDMMC_INT_EBE) {
1746 if (host->dir_status ==
1747 DW_MCI_SEND_STATUS) {
1748 /*
1749 * No data CRC status was returned.
1750 * The number of bytes transferred
1751 * will be exaggerated in PIO mode.
1752 */
1753 data->bytes_xfered = 0;
1754 data->error = -ETIMEDOUT;
1755 } else if (host->dir_status ==
1756 DW_MCI_RECV_STATUS) {
e7a1dec1 1757 data->error = -EILSEQ;
e352c813
SJ		 1758 }
1759 } else {
1760 /* SDMMC_INT_SBE is included */
e7a1dec1 1761 data->error = -EILSEQ;
e352c813
SJ		 1762 }
1763
e6cc0123 1764 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
e352c813
SJ		 1765
1766 /*
1767 * After an error, there may be data lingering
31bff450 1768 * in the FIFO
e352c813 1769 */
3a33a94c 1770 dw_mci_reset(host);
e352c813
SJ		 1771 } else {
1772 data->bytes_xfered = data->blocks * data->blksz;
1773 data->error = 0;
1774 }
1775
1776 return data->error;
f95f3850
WN		 1777}
1778
57e10486
AK		 1779static void dw_mci_set_drto(struct dw_mci *host)
1780{
1781 unsigned int drto_clks;
1782 unsigned int drto_ms;
1783
1784 drto_clks = mci_readl(host, TMOUT) >> 8;
1785 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1786
1787 /* add a bit spare time */
1788 drto_ms += 10;
1789
1790 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1791}
1792
f95f3850
WN		 1793static void dw_mci_tasklet_func(unsigned long priv)
1794{
1795 struct dw_mci *host = (struct dw_mci *)priv;
1796 struct mmc_data *data;
1797 struct mmc_command *cmd;
e352c813 1798 struct mmc_request *mrq;
f95f3850
WN		 1799 enum dw_mci_state state;
1800 enum dw_mci_state prev_state;
e352c813 1801 unsigned int err;
f95f3850
WN		 1802
1803 spin_lock(&host->lock);
1804
1805 state = host->state;
1806 data = host->data;
e352c813 1807 mrq = host->mrq;
f95f3850
WN		 1808
1809 do {
1810 prev_state = state;
1811
1812 switch (state) {
1813 case STATE_IDLE:
01730558 1814 case STATE_WAITING_CMD11_DONE:
f95f3850
WN		 1815 break;
1816
01730558 1817 case STATE_SENDING_CMD11:
f95f3850
WN		 1818 case STATE_SENDING_CMD:
1819 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1820 &host->pending_events))
1821 break;
1822
1823 cmd = host->cmd;
1824 host->cmd = NULL;
1825 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
e352c813
SJ		 1826 err = dw_mci_command_complete(host, cmd);
1827 if (cmd == mrq->sbc && !err) {
053b3ce6
SJ		 1828 prev_state = state = STATE_SENDING_CMD;
1829 __dw_mci_start_request(host, host->cur_slot,
e352c813 1830 mrq->cmd);
053b3ce6
SJ		 1831 goto unlock;
1832 }
1833
e352c813 1834 if (cmd->data && err) {
46d17952
DA		 1835 /*
1836 * During UHS tuning sequence, sending the stop
1837 * command after the response CRC error would
1838 * throw the system into a confused state
1839 * causing all future tuning phases to report
1840 * failure.
1841 *
1842 * In such case controller will move into a data
1843 * transfer state after a response error or
1844 * response CRC error. Let's let that finish
1845 * before trying to send a stop, so we'll go to
1846 * STATE_SENDING_DATA.
1847 *
1848 * Although letting the data transfer take place
1849 * will waste a bit of time (we already know
1850 * the command was bad), it can't cause any
1851 * errors since it's possible it would have
1852 * taken place anyway if this tasklet got
1853 * delayed. Allowing the transfer to take place
1854 * avoids races and keeps things simple.
1855 */
1856 if ((err != -ETIMEDOUT) &&
1857 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1858 state = STATE_SENDING_DATA;
1859 continue;
1860 }
1861
71abb133 1862 dw_mci_stop_dma(host);
90c2143a
SJ		 1863 send_stop_abort(host, data);
1864 state = STATE_SENDING_STOP;
1865 break;
71abb133
SJ		 1866 }
1867
e352c813
SJ		 1868 if (!cmd->data || err) {
1869 dw_mci_request_end(host, mrq);
f95f3850
WN		 1870 goto unlock;
1871 }
1872
1873 prev_state = state = STATE_SENDING_DATA;
1874 /* fall through */
1875
1876 case STATE_SENDING_DATA:
2aa35465
DA		 1877 /*
1878 * We could get a data error and never a transfer
1879 * complete so we'd better check for it here.
1880 *
1881 * Note that we don't really care if we also got a
1882 * transfer complete; stopping the DMA and sending an
1883 * abort won't hurt.
1884 */
f95f3850
WN		 1885 if (test_and_clear_bit(EVENT_DATA_ERROR,
1886 &host->pending_events)) {
1887 dw_mci_stop_dma(host);
bdb9a90b 1888 if (data->stop ||
1889 !(host->data_status & (SDMMC_INT_DRTO |
1890 SDMMC_INT_EBE)))
1891 send_stop_abort(host, data);
f95f3850
WN		 1892 state = STATE_DATA_ERROR;
1893 break;
1894 }
1895
1896 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
57e10486
AK		 1897 &host->pending_events)) {
1898 /*
1899 * If all data-related interrupts don't come
1900 * within the given time in reading data state.
1901 */
16a34574 1902 if (host->dir_status == DW_MCI_RECV_STATUS)
57e10486 1903 dw_mci_set_drto(host);
f95f3850 1904 break;
57e10486 1905 }
f95f3850
WN		 1906
1907 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2aa35465
DA		 1908
1909 /*
1910 * Handle an EVENT_DATA_ERROR that might have shown up
1911 * before the transfer completed. This might not have
1912 * been caught by the check above because the interrupt
1913 * could have gone off between the previous check and
1914 * the check for transfer complete.
1915 *
1916 * Technically this ought not be needed assuming we
1917 * get a DATA_COMPLETE eventually (we'll notice the
1918 * error and end the request), but it shouldn't hurt.
1919 *
1920 * This has the advantage of sending the stop command.
1921 */
1922 if (test_and_clear_bit(EVENT_DATA_ERROR,
1923 &host->pending_events)) {
1924 dw_mci_stop_dma(host);
bdb9a90b 1925 if (data->stop ||
1926 !(host->data_status & (SDMMC_INT_DRTO |
1927 SDMMC_INT_EBE)))
1928 send_stop_abort(host, data);
2aa35465
DA		 1929 state = STATE_DATA_ERROR;
1930 break;
1931 }
f95f3850 1932 prev_state = state = STATE_DATA_BUSY;
2aa35465 1933
f95f3850
WN		 1934 /* fall through */
1935
1936 case STATE_DATA_BUSY:
1937 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
57e10486
AK		 1938 &host->pending_events)) {
1939 /*
1940 * If data error interrupt comes but data over
1941 * interrupt doesn't come within the given time.
1942 * in reading data state.
1943 */
16a34574 1944 if (host->dir_status == DW_MCI_RECV_STATUS)
57e10486 1945 dw_mci_set_drto(host);
f95f3850 1946 break;
57e10486 1947 }
f95f3850
WN		 1948
1949 host->data = NULL;
1950 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
e352c813
SJ		 1951 err = dw_mci_data_complete(host, data);
1952
1953 if (!err) {
1954 if (!data->stop || mrq->sbc) {
17c8bc85 1955 if (mrq->sbc && data->stop)
e352c813
SJ		 1956 data->stop->error = 0;
1957 dw_mci_request_end(host, mrq);
1958 goto unlock;
f95f3850 1959 }
f95f3850 1960
e352c813
SJ		 1961 /* stop command for open-ended transfer*/
1962 if (data->stop)
1963 send_stop_abort(host, data);
2aa35465
DA		 1964 } else {
1965 /*
1966 * If we don't have a command complete now we'll
1967 * never get one since we just reset everything;
1968 * better end the request.
1969 *
1970 * If we do have a command complete we'll fall
1971 * through to the SENDING_STOP command and
1972 * everything will be peachy keen.
1973 */
1974 if (!test_bit(EVENT_CMD_COMPLETE,
1975 &host->pending_events)) {
1976 host->cmd = NULL;
1977 dw_mci_request_end(host, mrq);
1978 goto unlock;
1979 }
053b3ce6
SJ		 1980 }
1981
e352c813
SJ		 1982 /*
1983 * If err has non-zero,
1984 * stop-abort command has been already issued.
1985 */
f95f3850 1986 prev_state = state = STATE_SENDING_STOP;
e352c813 1987
f95f3850
WN		 1988 /* fall through */
1989
1990 case STATE_SENDING_STOP:
1991 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1992 &host->pending_events))
1993 break;
1994
71abb133 1995 /* CMD error in data command */
31bff450 1996 if (mrq->cmd->error && mrq->data)
3a33a94c 1997 dw_mci_reset(host);
71abb133 1998
f95f3850 1999 host->cmd = NULL;
71abb133 2000 host->data = NULL;
90c2143a 2001
e352c813
SJ		 2002 if (mrq->stop)
2003 dw_mci_command_complete(host, mrq->stop);
90c2143a
SJ		 2004 else
2005 host->cmd_status = 0;
2006
e352c813 2007 dw_mci_request_end(host, mrq);
f95f3850
WN		 2008 goto unlock;
2009
2010 case STATE_DATA_ERROR:
2011 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2012 &host->pending_events))
2013 break;
2014
2015 state = STATE_DATA_BUSY;
2016 break;
2017 }
2018 } while (state != prev_state);
2019
2020 host->state = state;
2021unlock:
2022 spin_unlock(&host->lock);
2023
2024}
2025
34b664a2
JH		 2026/* push final bytes to part_buf, only use during push */
2027static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 2028{
34b664a2
JH		 2029 memcpy((void *)&host->part_buf, buf, cnt);
2030 host->part_buf_count = cnt;
2031}
f95f3850 2032
34b664a2
JH		 2033/* append bytes to part_buf, only use during push */
2034static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2035{
2036 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2037 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2038 host->part_buf_count += cnt;
2039 return cnt;
2040}
f95f3850 2041
34b664a2
JH		 2042/* pull first bytes from part_buf, only use during pull */
2043static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2044{
0e3a22c0 2045 cnt = min_t(int, cnt, host->part_buf_count);
34b664a2
JH		 2046 if (cnt) {
2047 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2048 cnt);
2049 host->part_buf_count -= cnt;
2050 host->part_buf_start += cnt;
f95f3850 2051 }
34b664a2 2052 return cnt;
f95f3850
WN		 2053}
2054
34b664a2
JH		 2055/* pull final bytes from the part_buf, assuming it's just been filled */
2056static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 2057{
34b664a2
JH		 2058 memcpy(buf, &host->part_buf, cnt);
2059 host->part_buf_start = cnt;
2060 host->part_buf_count = (1 << host->data_shift) - cnt;
2061}
f95f3850 2062
34b664a2
JH		 2063static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2064{
cfbeb59c
MC		 2065 struct mmc_data *data = host->data;
2066 int init_cnt = cnt;
2067
34b664a2
JH		 2068 /* try and push anything in the part_buf */
2069 if (unlikely(host->part_buf_count)) {
2070 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2071
34b664a2
JH		 2072 buf += len;
2073 cnt -= len;
cfbeb59c 2074 if (host->part_buf_count == 2) {
76184ac1 2075 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 2076 host->part_buf_count = 0;
2077 }
2078 }
2079#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2080 if (unlikely((unsigned long)buf & 0x1)) {
2081 while (cnt >= 2) {
2082 u16 aligned_buf[64];
2083 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2084 int items = len >> 1;
2085 int i;
2086 /* memcpy from input buffer into aligned buffer */
2087 memcpy(aligned_buf, buf, len);
2088 buf += len;
2089 cnt -= len;
2090 /* push data from aligned buffer into fifo */
2091 for (i = 0; i < items; ++i)
76184ac1 2092 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2093 }
2094 } else
2095#endif
2096 {
2097 u16 *pdata = buf;
0e3a22c0 2098
34b664a2 2099 for (; cnt >= 2; cnt -= 2)
76184ac1 2100 mci_fifo_writew(host->fifo_reg, *pdata++);
34b664a2
JH		 2101 buf = pdata;
2102 }
2103 /* put anything remaining in the part_buf */
2104 if (cnt) {
2105 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2106 /* Push data if we have reached the expected data length */
2107 if ((data->bytes_xfered + init_cnt) ==
2108 (data->blksz * data->blocks))
76184ac1 2109 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 2110 }
2111}
f95f3850 2112
34b664a2
JH		 2113static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2114{
2115#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2116 if (unlikely((unsigned long)buf & 0x1)) {
2117 while (cnt >= 2) {
2118 /* pull data from fifo into aligned buffer */
2119 u16 aligned_buf[64];
2120 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2121 int items = len >> 1;
2122 int i;
0e3a22c0 2123
34b664a2 2124 for (i = 0; i < items; ++i)
76184ac1 2125 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2126 /* memcpy from aligned buffer into output buffer */
2127 memcpy(buf, aligned_buf, len);
2128 buf += len;
2129 cnt -= len;
2130 }
2131 } else
2132#endif
2133 {
2134 u16 *pdata = buf;
0e3a22c0 2135
34b664a2 2136 for (; cnt >= 2; cnt -= 2)
76184ac1 2137 *pdata++ = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2138 buf = pdata;
2139 }
2140 if (cnt) {
76184ac1 2141 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
34b664a2 2142 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2143 }
2144}
2145
2146static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2147{
cfbeb59c
MC		 2148 struct mmc_data *data = host->data;
2149 int init_cnt = cnt;
2150
34b664a2
JH		 2151 /* try and push anything in the part_buf */
2152 if (unlikely(host->part_buf_count)) {
2153 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2154
34b664a2
JH		 2155 buf += len;
2156 cnt -= len;
cfbeb59c 2157 if (host->part_buf_count == 4) {
76184ac1 2158 mci_fifo_writel(host->fifo_reg, host->part_buf32);
34b664a2
JH		 2159 host->part_buf_count = 0;
2160 }
2161 }
2162#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2163 if (unlikely((unsigned long)buf & 0x3)) {
2164 while (cnt >= 4) {
2165 u32 aligned_buf[32];
2166 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2167 int items = len >> 2;
2168 int i;
2169 /* memcpy from input buffer into aligned buffer */
2170 memcpy(aligned_buf, buf, len);
2171 buf += len;
2172 cnt -= len;
2173 /* push data from aligned buffer into fifo */
2174 for (i = 0; i < items; ++i)
76184ac1 2175 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2176 }
2177 } else
2178#endif
2179 {
2180 u32 *pdata = buf;
0e3a22c0 2181
34b664a2 2182 for (; cnt >= 4; cnt -= 4)
76184ac1 2183 mci_fifo_writel(host->fifo_reg, *pdata++);
34b664a2
JH		 2184 buf = pdata;
2185 }
2186 /* put anything remaining in the part_buf */
2187 if (cnt) {
2188 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2189 /* Push data if we have reached the expected data length */
2190 if ((data->bytes_xfered + init_cnt) ==
2191 (data->blksz * data->blocks))
76184ac1 2192 mci_fifo_writel(host->fifo_reg, host->part_buf32);
f95f3850
WN		 2193 }
2194}
2195
2196static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2197{
34b664a2
JH		 2198#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2199 if (unlikely((unsigned long)buf & 0x3)) {
2200 while (cnt >= 4) {
2201 /* pull data from fifo into aligned buffer */
2202 u32 aligned_buf[32];
2203 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2204 int items = len >> 2;
2205 int i;
0e3a22c0 2206
34b664a2 2207 for (i = 0; i < items; ++i)
76184ac1 2208 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2209 /* memcpy from aligned buffer into output buffer */
2210 memcpy(buf, aligned_buf, len);
2211 buf += len;
2212 cnt -= len;
2213 }
2214 } else
2215#endif
2216 {
2217 u32 *pdata = buf;
0e3a22c0 2218
34b664a2 2219 for (; cnt >= 4; cnt -= 4)
76184ac1 2220 *pdata++ = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2221 buf = pdata;
2222 }
2223 if (cnt) {
76184ac1 2224 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
34b664a2 2225 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2226 }
2227}
2228
2229static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2230{
cfbeb59c
MC		 2231 struct mmc_data *data = host->data;
2232 int init_cnt = cnt;
2233
34b664a2
JH		 2234 /* try and push anything in the part_buf */
2235 if (unlikely(host->part_buf_count)) {
2236 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2237
34b664a2
JH		 2238 buf += len;
2239 cnt -= len;
c09fbd74 2240
cfbeb59c 2241 if (host->part_buf_count == 8) {
76184ac1 2242 mci_fifo_writeq(host->fifo_reg, host->part_buf);
34b664a2
JH		 2243 host->part_buf_count = 0;
2244 }
2245 }
2246#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2247 if (unlikely((unsigned long)buf & 0x7)) {
2248 while (cnt >= 8) {
2249 u64 aligned_buf[16];
2250 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2251 int items = len >> 3;
2252 int i;
2253 /* memcpy from input buffer into aligned buffer */
2254 memcpy(aligned_buf, buf, len);
2255 buf += len;
2256 cnt -= len;
2257 /* push data from aligned buffer into fifo */
2258 for (i = 0; i < items; ++i)
76184ac1 2259 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2260 }
2261 } else
2262#endif
2263 {
2264 u64 *pdata = buf;
0e3a22c0 2265
34b664a2 2266 for (; cnt >= 8; cnt -= 8)
76184ac1 2267 mci_fifo_writeq(host->fifo_reg, *pdata++);
34b664a2
JH		 2268 buf = pdata;
2269 }
2270 /* put anything remaining in the part_buf */
2271 if (cnt) {
2272 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2273 /* Push data if we have reached the expected data length */
2274 if ((data->bytes_xfered + init_cnt) ==
2275 (data->blksz * data->blocks))
76184ac1 2276 mci_fifo_writeq(host->fifo_reg, host->part_buf);
f95f3850
WN		 2277 }
2278}
2279
2280static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2281{
34b664a2
JH		 2282#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2283 if (unlikely((unsigned long)buf & 0x7)) {
2284 while (cnt >= 8) {
2285 /* pull data from fifo into aligned buffer */
2286 u64 aligned_buf[16];
2287 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2288 int items = len >> 3;
2289 int i;
0e3a22c0 2290
34b664a2 2291 for (i = 0; i < items; ++i)
76184ac1
BD		 2292 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2293
34b664a2
JH		 2294 /* memcpy from aligned buffer into output buffer */
2295 memcpy(buf, aligned_buf, len);
2296 buf += len;
2297 cnt -= len;
2298 }
2299 } else
2300#endif
2301 {
2302 u64 *pdata = buf;
0e3a22c0 2303
34b664a2 2304 for (; cnt >= 8; cnt -= 8)
76184ac1 2305 *pdata++ = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2306 buf = pdata;
2307 }
2308 if (cnt) {
76184ac1 2309 host->part_buf = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2310 dw_mci_pull_final_bytes(host, buf, cnt);
2311 }
2312}
f95f3850 2313
34b664a2
JH		 2314static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2315{
2316 int len;
f95f3850 2317
34b664a2
JH		 2318 /* get remaining partial bytes */
2319 len = dw_mci_pull_part_bytes(host, buf, cnt);
2320 if (unlikely(len == cnt))
2321 return;
2322 buf += len;
2323 cnt -= len;
2324
2325 /* get the rest of the data */
2326 host->pull_data(host, buf, cnt);
f95f3850
WN		 2327}
2328
87a74d39 2329static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
f95f3850 2330{
f9c2a0dc
SJ		 2331 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2332 void *buf;
2333 unsigned int offset;
f95f3850
WN		 2334 struct mmc_data *data = host->data;
2335 int shift = host->data_shift;
2336 u32 status;
3e4b0d8b 2337 unsigned int len;
f9c2a0dc 2338 unsigned int remain, fcnt;
f95f3850
WN		 2339
2340 do {
f9c2a0dc
SJ		 2341 if (!sg_miter_next(sg_miter))
2342 goto done;
2343
4225fc85 2344 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2345 buf = sg_miter->addr;
2346 remain = sg_miter->length;
2347 offset = 0;
2348
2349 do {
2350 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2351 << shift) + host->part_buf_count;
2352 len = min(remain, fcnt);
2353 if (!len)
2354 break;
34b664a2 2355 dw_mci_pull_data(host, (void *)(buf + offset), len);
3e4b0d8b 2356 data->bytes_xfered += len;
f95f3850 2357 offset += len;
f9c2a0dc
SJ		 2358 remain -= len;
2359 } while (remain);
f95f3850 2360
e74f3a9c 2361 sg_miter->consumed = offset;
f95f3850
WN		 2362 status = mci_readl(host, MINTSTS);
2363 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
87a74d39
KK		 2364 /* if the RXDR is ready read again */
2365 } while ((status & SDMMC_INT_RXDR) ||
2366 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
f9c2a0dc
SJ		 2367
2368 if (!remain) {
2369 if (!sg_miter_next(sg_miter))
2370 goto done;
2371 sg_miter->consumed = 0;
2372 }
2373 sg_miter_stop(sg_miter);
f95f3850
WN		 2374 return;
2375
2376done:
f9c2a0dc
SJ		 2377 sg_miter_stop(sg_miter);
2378 host->sg = NULL;
0e3a22c0 2379 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2380 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2381}
2382
2383static void dw_mci_write_data_pio(struct dw_mci *host)
2384{
f9c2a0dc
SJ		 2385 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2386 void *buf;
2387 unsigned int offset;
f95f3850
WN		 2388 struct mmc_data *data = host->data;
2389 int shift = host->data_shift;
2390 u32 status;
3e4b0d8b 2391 unsigned int len;
f9c2a0dc
SJ		 2392 unsigned int fifo_depth = host->fifo_depth;
2393 unsigned int remain, fcnt;
f95f3850
WN		 2394
2395 do {
f9c2a0dc
SJ		 2396 if (!sg_miter_next(sg_miter))
2397 goto done;
2398
4225fc85 2399 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2400 buf = sg_miter->addr;
2401 remain = sg_miter->length;
2402 offset = 0;
2403
2404 do {
2405 fcnt = ((fifo_depth -
2406 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2407 << shift) - host->part_buf_count;
2408 len = min(remain, fcnt);
2409 if (!len)
2410 break;
f95f3850 2411 host->push_data(host, (void *)(buf + offset), len);
3e4b0d8b 2412 data->bytes_xfered += len;
f95f3850 2413 offset += len;
f9c2a0dc
SJ		 2414 remain -= len;
2415 } while (remain);
f95f3850 2416
e74f3a9c 2417 sg_miter->consumed = offset;
f95f3850
WN		 2418 status = mci_readl(host, MINTSTS);
2419 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 2420 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f9c2a0dc
SJ		 2421
2422 if (!remain) {
2423 if (!sg_miter_next(sg_miter))
2424 goto done;
2425 sg_miter->consumed = 0;
2426 }
2427 sg_miter_stop(sg_miter);
f95f3850
WN		 2428 return;
2429
2430done:
f9c2a0dc
SJ		 2431 sg_miter_stop(sg_miter);
2432 host->sg = NULL;
0e3a22c0 2433 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2434 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2435}
2436
2437static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2438{
2439 if (!host->cmd_status)
2440 host->cmd_status = status;
2441
0e3a22c0 2442 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2443
2444 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2445 tasklet_schedule(&host->tasklet);
2446}
2447
6130e7a9
DA		 2448static void dw_mci_handle_cd(struct dw_mci *host)
2449{
2450 int i;
2451
2452 for (i = 0; i < host->num_slots; i++) {
2453 struct dw_mci_slot *slot = host->slot[i];
2454
2455 if (!slot)
2456 continue;
2457
2458 if (slot->mmc->ops->card_event)
2459 slot->mmc->ops->card_event(slot->mmc);
2460 mmc_detect_change(slot->mmc,
2461 msecs_to_jiffies(host->pdata->detect_delay_ms));
2462 }
2463}
2464
f95f3850
WN		 2465static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2466{
2467 struct dw_mci *host = dev_id;
182c9081 2468 u32 pending;
1a5c8e1f 2469 int i;
f95f3850 2470
1fb5f68a
MC		 2471 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2472
476d79f1 2473 if (pending) {
01730558
DA		 2474 /* Check volt switch first, since it can look like an error */
2475 if ((host->state == STATE_SENDING_CMD11) &&
2476 (pending & SDMMC_INT_VOLT_SWITCH)) {
49ba0302 2477 unsigned long irqflags;
5c935165 2478
01730558
DA		 2479 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2480 pending &= ~SDMMC_INT_VOLT_SWITCH;
49ba0302
DA		 2481
2482 /*
2483 * Hold the lock; we know cmd11_timer can't be kicked
2484 * off after the lock is released, so safe to delete.
2485 */
2486 spin_lock_irqsave(&host->irq_lock, irqflags);
01730558 2487 dw_mci_cmd_interrupt(host, pending);
49ba0302
DA		 2488 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2489
2490 del_timer(&host->cmd11_timer);
01730558
DA		 2491 }
2492
f95f3850
WN		 2493 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2494 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 2495 host->cmd_status = pending;
0e3a22c0 2496 smp_wmb(); /* drain writebuffer */
f95f3850 2497 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 2498 }
2499
2500 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2501 /* if there is an error report DATA_ERROR */
2502 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 2503 host->data_status = pending;
0e3a22c0 2504 smp_wmb(); /* drain writebuffer */
f95f3850 2505 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 2506 tasklet_schedule(&host->tasklet);
f95f3850
WN		 2507 }
2508
2509 if (pending & SDMMC_INT_DATA_OVER) {
16a34574 2510 del_timer(&host->dto_timer);
57e10486 2511
f95f3850
WN		 2512 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2513 if (!host->data_status)
182c9081 2514 host->data_status = pending;
0e3a22c0 2515 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2516 if (host->dir_status == DW_MCI_RECV_STATUS) {
2517 if (host->sg != NULL)
87a74d39 2518 dw_mci_read_data_pio(host, true);
f95f3850
WN		 2519 }
2520 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2521 tasklet_schedule(&host->tasklet);
2522 }
2523
2524 if (pending & SDMMC_INT_RXDR) {
2525 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 2526 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
87a74d39 2527 dw_mci_read_data_pio(host, false);
f95f3850
WN		 2528 }
2529
2530 if (pending & SDMMC_INT_TXDR) {
2531 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 2532 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 2533 dw_mci_write_data_pio(host);
2534 }
2535
2536 if (pending & SDMMC_INT_CMD_DONE) {
2537 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 2538 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 2539 }
2540
2541 if (pending & SDMMC_INT_CD) {
2542 mci_writel(host, RINTSTS, SDMMC_INT_CD);
6130e7a9 2543 dw_mci_handle_cd(host);
f95f3850
WN		 2544 }
2545
1a5c8e1f
SH		 2546 /* Handle SDIO Interrupts */
2547 for (i = 0; i < host->num_slots; i++) {
2548 struct dw_mci_slot *slot = host->slot[i];
ed2540ef
DA		 2549
2550 if (!slot)
2551 continue;
2552
76756234
AK		 2553 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2554 mci_writel(host, RINTSTS,
2555 SDMMC_INT_SDIO(slot->sdio_id));
1a5c8e1f
SH		 2556 mmc_signal_sdio_irq(slot->mmc);
2557 }
2558 }
2559
1fb5f68a 2560 }
f95f3850 2561
3fc7eaef
SL		 2562 if (host->use_dma != TRANS_MODE_IDMAC)
2563 return IRQ_HANDLED;
2564
2565 /* Handle IDMA interrupts */
69d99fdc
PT		 2566 if (host->dma_64bit_address == 1) {
2567 pending = mci_readl(host, IDSTS64);
2568 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2569 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2570 SDMMC_IDMAC_INT_RI);
2571 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
faecf411
SL		 2572 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2573 host->dma_ops->complete((void *)host);
69d99fdc
PT		 2574 }
2575 } else {
2576 pending = mci_readl(host, IDSTS);
2577 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2578 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2579 SDMMC_IDMAC_INT_RI);
2580 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
faecf411
SL		 2581 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2582 host->dma_ops->complete((void *)host);
69d99fdc 2583 }
f95f3850 2584 }
f95f3850
WN		 2585
2586 return IRQ_HANDLED;
2587}
2588
36c179a9 2589static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 2590{
2591 struct mmc_host *mmc;
2592 struct dw_mci_slot *slot;
e95baf13 2593 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2594 int ctrl_id, ret;
1f44a2a5 2595 u32 freq[2];
f95f3850 2596
4a90920c 2597 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 2598 if (!mmc)
2599 return -ENOMEM;
2600
2601 slot = mmc_priv(mmc);
2602 slot->id = id;
76756234 2603 slot->sdio_id = host->sdio_id0 + id;
f95f3850
WN		 2604 slot->mmc = mmc;
2605 slot->host = host;
c91eab4b 2606 host->slot[id] = slot;
f95f3850
WN		 2607
2608 mmc->ops = &dw_mci_ops;
1f44a2a5
SJ		 2609 if (of_property_read_u32_array(host->dev->of_node,
2610 "clock-freq-min-max", freq, 2)) {
2611 mmc->f_min = DW_MCI_FREQ_MIN;
2612 mmc->f_max = DW_MCI_FREQ_MAX;
2613 } else {
2614 mmc->f_min = freq[0];
2615 mmc->f_max = freq[1];
2616 }
f95f3850 2617
51da2240
YC		 2618 /*if there are external regulators, get them*/
2619 ret = mmc_regulator_get_supply(mmc);
2620 if (ret == -EPROBE_DEFER)
3cf890fc 2621 goto err_host_allocated;
51da2240
YC		 2622
2623 if (!mmc->ocr_avail)
2624 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
f95f3850 2625
fc3d7720
JC		 2626 if (host->pdata->caps)
2627 mmc->caps = host->pdata->caps;
fc3d7720 2628
6024e166
JC		 2629 /*
2630 * Support MMC_CAP_ERASE by default.
2631 * It needs to use trim/discard/erase commands.
2632 */
2633 mmc->caps |= MMC_CAP_ERASE;
2634
ab269128
AK		 2635 if (host->pdata->pm_caps)
2636 mmc->pm_caps = host->pdata->pm_caps;
2637
800d78bf
TA		 2638 if (host->dev->of_node) {
2639 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2640 if (ctrl_id < 0)
2641 ctrl_id = 0;
2642 } else {
2643 ctrl_id = to_platform_device(host->dev)->id;
2644 }
cb27a843
JH		 2645 if (drv_data && drv_data->caps)
2646 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 2647
4f408cc6
SJ		 2648 if (host->pdata->caps2)
2649 mmc->caps2 = host->pdata->caps2;
4f408cc6 2650
3cf890fc
DA		 2651 ret = mmc_of_parse(mmc);
2652 if (ret)
2653 goto err_host_allocated;
f95f3850 2654
2b708df2 2655 /* Useful defaults if platform data is unset. */
3fc7eaef 2656 if (host->use_dma == TRANS_MODE_IDMAC) {
2b708df2 2657 mmc->max_segs = host->ring_size;
225faf87 2658 mmc->max_blk_size = 65535;
2b708df2
JC		 2659 mmc->max_seg_size = 0x1000;
2660 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2661 mmc->max_blk_count = mmc->max_req_size / 512;
3fc7eaef
SL		 2662 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2663 mmc->max_segs = 64;
225faf87 2664 mmc->max_blk_size = 65535;
3fc7eaef
SL		 2665 mmc->max_blk_count = 65535;
2666 mmc->max_req_size =
2667 mmc->max_blk_size * mmc->max_blk_count;
2668 mmc->max_seg_size = mmc->max_req_size;
f95f3850 2669 } else {
3fc7eaef 2670 /* TRANS_MODE_PIO */
2b708df2 2671 mmc->max_segs = 64;
225faf87 2672 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2b708df2
JC		 2673 mmc->max_blk_count = 512;
2674 mmc->max_req_size = mmc->max_blk_size *
2675 mmc->max_blk_count;
2676 mmc->max_seg_size = mmc->max_req_size;
a39e5746 2677 }
f95f3850 2678
c0834a58 2679 dw_mci_get_cd(mmc);
ae0eb348 2680
0cea529d
JC		 2681 ret = mmc_add_host(mmc);
2682 if (ret)
3cf890fc 2683 goto err_host_allocated;
f95f3850
WN		 2684
2685#if defined(CONFIG_DEBUG_FS)
2686 dw_mci_init_debugfs(slot);
2687#endif
2688
f95f3850 2689 return 0;
800d78bf 2690
3cf890fc 2691err_host_allocated:
800d78bf 2692 mmc_free_host(mmc);
51da2240 2693 return ret;
f95f3850
WN		 2694}
2695
2696static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2697{
f95f3850
WN		 2698 /* Debugfs stuff is cleaned up by mmc core */
2699 mmc_remove_host(slot->mmc);
2700 slot->host->slot[id] = NULL;
2701 mmc_free_host(slot->mmc);
2702}
2703
2704static void dw_mci_init_dma(struct dw_mci *host)
2705{
69d99fdc 2706 int addr_config;
3fc7eaef
SL		 2707 struct device *dev = host->dev;
2708 struct device_node *np = dev->of_node;
69d99fdc 2709
3fc7eaef
SL		 2710 /*
2711 * Check tansfer mode from HCON[17:16]
2712 * Clear the ambiguous description of dw_mmc databook:
2713 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2714 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2715 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2716 * 2b'11: Non DW DMA Interface -> pio only
2717 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2718 * simpler request/acknowledge handshake mechanism and both of them
2719 * are regarded as external dma master for dw_mmc.
2720 */
2721 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2722 if (host->use_dma == DMA_INTERFACE_IDMA) {
2723 host->use_dma = TRANS_MODE_IDMAC;
2724 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2725 host->use_dma == DMA_INTERFACE_GDMA) {
2726 host->use_dma = TRANS_MODE_EDMAC;
2727 } else {
f95f3850
WN		 2728 goto no_dma;
2729 }
2730
2731 /* Determine which DMA interface to use */
3fc7eaef
SL		 2732 if (host->use_dma == TRANS_MODE_IDMAC) {
2733 /*
2734 * Check ADDR_CONFIG bit in HCON to find
2735 * IDMAC address bus width
2736 */
70692752 2737 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
3fc7eaef
SL		 2738
2739 if (addr_config == 1) {
2740 /* host supports IDMAC in 64-bit address mode */
2741 host->dma_64bit_address = 1;
2742 dev_info(host->dev,
2743 "IDMAC supports 64-bit address mode.\n");
2744 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2745 dma_set_coherent_mask(host->dev,
2746 DMA_BIT_MASK(64));
2747 } else {
2748 /* host supports IDMAC in 32-bit address mode */
2749 host->dma_64bit_address = 0;
2750 dev_info(host->dev,
2751 "IDMAC supports 32-bit address mode.\n");
2752 }
f95f3850 2753
3fc7eaef
SL		 2754 /* Alloc memory for sg translation */
2755 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2756 &host->sg_dma, GFP_KERNEL);
2757 if (!host->sg_cpu) {
2758 dev_err(host->dev,
2759 "%s: could not alloc DMA memory\n",
2760 __func__);
2761 goto no_dma;
2762 }
2763
2764 host->dma_ops = &dw_mci_idmac_ops;
2765 dev_info(host->dev, "Using internal DMA controller.\n");
2766 } else {
2767 /* TRANS_MODE_EDMAC: check dma bindings again */
2768 if ((of_property_count_strings(np, "dma-names") < 0) ||
2769 (!of_find_property(np, "dmas", NULL))) {
2770 goto no_dma;
2771 }
2772 host->dma_ops = &dw_mci_edmac_ops;
2773 dev_info(host->dev, "Using external DMA controller.\n");
2774 }
f95f3850 2775
e1631f98
JC		 2776 if (host->dma_ops->init && host->dma_ops->start &&
2777 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 2778 if (host->dma_ops->init(host)) {
0e3a22c0
SL		 2779 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2780 __func__);
f95f3850
WN		 2781 goto no_dma;
2782 }
2783 } else {
4a90920c 2784 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 2785 goto no_dma;
2786 }
2787
f95f3850
WN		 2788 return;
2789
2790no_dma:
4a90920c 2791 dev_info(host->dev, "Using PIO mode.\n");
3fc7eaef 2792 host->use_dma = TRANS_MODE_PIO;
f95f3850
WN		 2793}
2794
31bff450 2795static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
f95f3850
WN		 2796{
2797 unsigned long timeout = jiffies + msecs_to_jiffies(500);
31bff450 2798 u32 ctrl;
f95f3850 2799
31bff450
SJ		 2800 ctrl = mci_readl(host, CTRL);
2801 ctrl |= reset;
2802 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 2803
2804 /* wait till resets clear */
2805 do {
2806 ctrl = mci_readl(host, CTRL);
31bff450 2807 if (!(ctrl & reset))
f95f3850
WN		 2808 return true;
2809 } while (time_before(jiffies, timeout));
2810
31bff450
SJ		 2811 dev_err(host->dev,
2812 "Timeout resetting block (ctrl reset %#x)\n",
2813 ctrl & reset);
f95f3850
WN		 2814
2815 return false;
2816}
2817
3a33a94c 2818static bool dw_mci_reset(struct dw_mci *host)
31bff450 2819{
3a33a94c
SR		 2820 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2821 bool ret = false;
2822
31bff450
SJ		 2823 /*
2824 * Reseting generates a block interrupt, hence setting
2825 * the scatter-gather pointer to NULL.
2826 */
2827 if (host->sg) {
2828 sg_miter_stop(&host->sg_miter);
2829 host->sg = NULL;
2830 }
2831
3a33a94c
SR		 2832 if (host->use_dma)
2833 flags |= SDMMC_CTRL_DMA_RESET;
31bff450 2834
3a33a94c
SR		 2835 if (dw_mci_ctrl_reset(host, flags)) {
2836 /*
2837 * In all cases we clear the RAWINTS register to clear any
2838 * interrupts.
2839 */
2840 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2841
2842 /* if using dma we wait for dma_req to clear */
2843 if (host->use_dma) {
2844 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2845 u32 status;
0e3a22c0 2846
3a33a94c
SR		 2847 do {
2848 status = mci_readl(host, STATUS);
2849 if (!(status & SDMMC_STATUS_DMA_REQ))
2850 break;
2851 cpu_relax();
2852 } while (time_before(jiffies, timeout));
2853
2854 if (status & SDMMC_STATUS_DMA_REQ) {
2855 dev_err(host->dev,
0e3a22c0
SL		 2856 "%s: Timeout waiting for dma_req to clear during reset\n",
2857 __func__);
3a33a94c
SR		 2858 goto ciu_out;
2859 }
2860
2861 /* when using DMA next we reset the fifo again */
2862 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2863 goto ciu_out;
2864 }
2865 } else {
2866 /* if the controller reset bit did clear, then set clock regs */
2867 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
0e3a22c0
SL		 2868 dev_err(host->dev,
2869 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
3a33a94c
SR		 2870 __func__);
2871 goto ciu_out;
2872 }
2873 }
2874
3fc7eaef
SL		 2875 if (host->use_dma == TRANS_MODE_IDMAC)
2876 /* It is also recommended that we reset and reprogram idmac */
2877 dw_mci_idmac_reset(host);
3a33a94c
SR		 2878
2879 ret = true;
2880
2881ciu_out:
2882 /* After a CTRL reset we need to have CIU set clock registers */
2883 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2884
2885 return ret;
31bff450
SJ		 2886}
2887
5c935165
DA		 2888static void dw_mci_cmd11_timer(unsigned long arg)
2889{
2890 struct dw_mci *host = (struct dw_mci *)arg;
2891
fd674198
DA		 2892 if (host->state != STATE_SENDING_CMD11) {
2893 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2894 return;
2895 }
5c935165
DA		 2896
2897 host->cmd_status = SDMMC_INT_RTO;
2898 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2899 tasklet_schedule(&host->tasklet);
2900}
2901
57e10486
AK		 2902static void dw_mci_dto_timer(unsigned long arg)
2903{
2904 struct dw_mci *host = (struct dw_mci *)arg;
2905
2906 switch (host->state) {
2907 case STATE_SENDING_DATA:
2908 case STATE_DATA_BUSY:
2909 /*
2910 * If DTO interrupt does NOT come in sending data state,
2911 * we should notify the driver to terminate current transfer
2912 * and report a data timeout to the core.
2913 */
2914 host->data_status = SDMMC_INT_DRTO;
2915 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2916 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2917 tasklet_schedule(&host->tasklet);
2918 break;
2919 default:
2920 break;
2921 }
2922}
2923
c91eab4b 2924#ifdef CONFIG_OF
c91eab4b
TA		 2925static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2926{
2927 struct dw_mci_board *pdata;
2928 struct device *dev = host->dev;
2929 struct device_node *np = dev->of_node;
e95baf13 2930 const struct dw_mci_drv_data *drv_data = host->drv_data;
e8cc37b8 2931 int ret;
3c6d89ea 2932 u32 clock_frequency;
c91eab4b
TA		 2933
2934 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
bf3707ea 2935 if (!pdata)
c91eab4b 2936 return ERR_PTR(-ENOMEM);
c91eab4b 2937
d6786fef
GX		 2938 /* find reset controller when exist */
2939 pdata->rstc = devm_reset_control_get_optional(dev, NULL);
2940 if (IS_ERR(pdata->rstc)) {
2941 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2942 return ERR_PTR(-EPROBE_DEFER);
2943 }
2944
c91eab4b 2945 /* find out number of slots supported */
8a629d26 2946 of_property_read_u32(np, "num-slots", &pdata->num_slots);
c91eab4b 2947
c91eab4b 2948 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
0e3a22c0
SL		 2949 dev_info(dev,
2950 "fifo-depth property not found, using value of FIFOTH register as default\n");
c91eab4b
TA		 2951
2952 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2953
3c6d89ea
DA		 2954 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2955 pdata->bus_hz = clock_frequency;
2956
cb27a843
JH		 2957 if (drv_data && drv_data->parse_dt) {
2958 ret = drv_data->parse_dt(host);
800d78bf
TA		 2959 if (ret)
2960 return ERR_PTR(ret);
2961 }
2962
40a7a463
JC		 2963 if (of_find_property(np, "supports-highspeed", NULL)) {
2964 dev_info(dev, "supports-highspeed property is deprecated.\n");
10b49841 2965 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
40a7a463 2966 }
10b49841 2967
c91eab4b
TA		 2968 return pdata;
2969}
2970
2971#else /* CONFIG_OF */
2972static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2973{
2974 return ERR_PTR(-EINVAL);
2975}
2976#endif /* CONFIG_OF */
2977
fa0c3283
DA		 2978static void dw_mci_enable_cd(struct dw_mci *host)
2979{
fa0c3283
DA		 2980 unsigned long irqflags;
2981 u32 temp;
2982 int i;
e8cc37b8 2983 struct dw_mci_slot *slot;
fa0c3283 2984
e8cc37b8
SL		 2985 /*
2986 * No need for CD if all slots have a non-error GPIO
2987 * as well as broken card detection is found.
2988 */
fa0c3283 2989 for (i = 0; i < host->num_slots; i++) {
e8cc37b8
SL		 2990 slot = host->slot[i];
2991 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
2992 return;
fa0c3283 2993
287980e4 2994 if (mmc_gpio_get_cd(slot->mmc) < 0)
fa0c3283
DA		 2995 break;
2996 }
2997 if (i == host->num_slots)
2998 return;
2999
3000 spin_lock_irqsave(&host->irq_lock, irqflags);
3001 temp = mci_readl(host, INTMASK);
3002 temp |= SDMMC_INT_CD;
3003 mci_writel(host, INTMASK, temp);
3004 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3005}
3006
62ca8034 3007int dw_mci_probe(struct dw_mci *host)
f95f3850 3008{
e95baf13 3009 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 3010 int width, i, ret = 0;
f95f3850 3011 u32 fifo_size;
1c2215b7 3012 int init_slots = 0;
f95f3850 3013
c91eab4b
TA		 3014 if (!host->pdata) {
3015 host->pdata = dw_mci_parse_dt(host);
d6786fef
GX		 3016 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3017 return -EPROBE_DEFER;
3018 } else if (IS_ERR(host->pdata)) {
c91eab4b
TA		 3019 dev_err(host->dev, "platform data not available\n");
3020 return -EINVAL;
3021 }
f95f3850
WN		 3022 }
3023
780f22af 3024 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 3025 if (IS_ERR(host->biu_clk)) {
3026 dev_dbg(host->dev, "biu clock not available\n");
3027 } else {
3028 ret = clk_prepare_enable(host->biu_clk);
3029 if (ret) {
3030 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 3031 return ret;
3032 }
3033 }
3034
780f22af 3035 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 3036 if (IS_ERR(host->ciu_clk)) {
3037 dev_dbg(host->dev, "ciu clock not available\n");
3c6d89ea 3038 host->bus_hz = host->pdata->bus_hz;
f90a0612
TA		 3039 } else {
3040 ret = clk_prepare_enable(host->ciu_clk);
3041 if (ret) {
3042 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 3043 goto err_clk_biu;
3044 }
f90a0612 3045
3c6d89ea
DA		 3046 if (host->pdata->bus_hz) {
3047 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3048 if (ret)
3049 dev_warn(host->dev,
612de4c1 3050 "Unable to set bus rate to %uHz\n",
3c6d89ea
DA		 3051 host->pdata->bus_hz);
3052 }
f90a0612 3053 host->bus_hz = clk_get_rate(host->ciu_clk);
3c6d89ea 3054 }
f90a0612 3055
612de4c1
JC		 3056 if (!host->bus_hz) {
3057 dev_err(host->dev,
3058 "Platform data must supply bus speed\n");
3059 ret = -ENODEV;
3060 goto err_clk_ciu;
3061 }
3062
002f0d5c
YK		 3063 if (drv_data && drv_data->init) {
3064 ret = drv_data->init(host);
3065 if (ret) {
3066 dev_err(host->dev,
3067 "implementation specific init failed\n");
3068 goto err_clk_ciu;
3069 }
3070 }
3071
d6786fef
GX		 3072 if (!IS_ERR(host->pdata->rstc)) {
3073 reset_control_assert(host->pdata->rstc);
3074 usleep_range(10, 50);
3075 reset_control_deassert(host->pdata->rstc);
3076 }
3077
5c935165
DA		 3078 setup_timer(&host->cmd11_timer,
3079 dw_mci_cmd11_timer, (unsigned long)host);
3080
16a34574
JC		 3081 setup_timer(&host->dto_timer,
3082 dw_mci_dto_timer, (unsigned long)host);
57e10486 3083
f95f3850 3084 spin_lock_init(&host->lock);
f8c58c11 3085 spin_lock_init(&host->irq_lock);
f95f3850
WN		 3086 INIT_LIST_HEAD(&host->queue);
3087
f95f3850
WN		 3088 /*
3089 * Get the host data width - this assumes that HCON has been set with
3090 * the correct values.
3091 */
70692752 3092 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
f95f3850
WN		 3093 if (!i) {
3094 host->push_data = dw_mci_push_data16;
3095 host->pull_data = dw_mci_pull_data16;
3096 width = 16;
3097 host->data_shift = 1;
3098 } else if (i == 2) {
3099 host->push_data = dw_mci_push_data64;
3100 host->pull_data = dw_mci_pull_data64;
3101 width = 64;
3102 host->data_shift = 3;
3103 } else {
3104 /* Check for a reserved value, and warn if it is */
3105 WARN((i != 1),
3106 "HCON reports a reserved host data width!\n"
3107 "Defaulting to 32-bit access.\n");
3108 host->push_data = dw_mci_push_data32;
3109 host->pull_data = dw_mci_pull_data32;
3110 width = 32;
3111 host->data_shift = 2;
3112 }
3113
3114 /* Reset all blocks */
3744415c
SL		 3115 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3116 ret = -ENODEV;
3117 goto err_clk_ciu;
3118 }
141a712a
SJ		 3119
3120 host->dma_ops = host->pdata->dma_ops;
3121 dw_mci_init_dma(host);
f95f3850
WN		 3122
3123 /* Clear the interrupts for the host controller */
3124 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3125 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3126
3127 /* Put in max timeout */
3128 mci_writel(host, TMOUT, 0xFFFFFFFF);
3129
3130 /*
3131 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3132 * Tx Mark = fifo_size / 2 DMA Size = 8
3133 */
b86d8253
JH		 3134 if (!host->pdata->fifo_depth) {
3135 /*
3136 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3137 * have been overwritten by the bootloader, just like we're
3138 * about to do, so if you know the value for your hardware, you
3139 * should put it in the platform data.
3140 */
3141 fifo_size = mci_readl(host, FIFOTH);
8234e869 3142 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 3143 } else {
3144 fifo_size = host->pdata->fifo_depth;
3145 }
3146 host->fifo_depth = fifo_size;
52426899
SJ		 3147 host->fifoth_val =
3148 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
e61cf118 3149 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 3150
3151 /* disable clock to CIU */
3152 mci_writel(host, CLKENA, 0);
3153 mci_writel(host, CLKSRC, 0);
3154
63008768
JH		 3155 /*
3156 * In 2.40a spec, Data offset is changed.
3157 * Need to check the version-id and set data-offset for DATA register.
3158 */
3159 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3160 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3161
3162 if (host->verid < DW_MMC_240A)
76184ac1 3163 host->fifo_reg = host->regs + DATA_OFFSET;
63008768 3164 else
76184ac1 3165 host->fifo_reg = host->regs + DATA_240A_OFFSET;
63008768 3166
f95f3850 3167 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
780f22af
SJ		 3168 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3169 host->irq_flags, "dw-mci", host);
f95f3850 3170 if (ret)
6130e7a9 3171 goto err_dmaunmap;
f95f3850 3172
f95f3850
WN		 3173 if (host->pdata->num_slots)
3174 host->num_slots = host->pdata->num_slots;
3175 else
8a629d26
SL		 3176 host->num_slots = 1;
3177
3178 if (host->num_slots < 1 ||
3179 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3180 dev_err(host->dev,
3181 "Platform data must supply correct num_slots.\n");
3182 ret = -ENODEV;
3183 goto err_clk_ciu;
3184 }
f95f3850 3185
2da1d7f2 3186 /*
fa0c3283 3187 * Enable interrupts for command done, data over, data empty,
2da1d7f2
YC		 3188 * receive ready and error such as transmit, receive timeout, crc error
3189 */
2da1d7f2
YC		 3190 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3191 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3192 DW_MCI_ERROR_FLAGS);
0e3a22c0
SL		 3193 /* Enable mci interrupt */
3194 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2da1d7f2 3195
0e3a22c0
SL		 3196 dev_info(host->dev,
3197 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
2da1d7f2
YC		 3198 host->irq, width, fifo_size);
3199
f95f3850
WN		 3200 /* We need at least one slot to succeed */
3201 for (i = 0; i < host->num_slots; i++) {
3202 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 3203 if (ret)
3204 dev_dbg(host->dev, "slot %d init failed\n", i);
3205 else
3206 init_slots++;
3207 }
3208
3209 if (init_slots) {
3210 dev_info(host->dev, "%d slots initialized\n", init_slots);
3211 } else {
0e3a22c0
SL		 3212 dev_dbg(host->dev,
3213 "attempted to initialize %d slots, but failed on all\n",
3214 host->num_slots);
6130e7a9 3215 goto err_dmaunmap;
f95f3850
WN		 3216 }
3217
b793f658
DA		 3218 /* Now that slots are all setup, we can enable card detect */
3219 dw_mci_enable_cd(host);
3220
f95f3850
WN		 3221 return 0;
3222
f95f3850
WN		 3223err_dmaunmap:
3224 if (host->use_dma && host->dma_ops->exit)
3225 host->dma_ops->exit(host);
f90a0612 3226
d6786fef
GX		 3227 if (!IS_ERR(host->pdata->rstc))
3228 reset_control_assert(host->pdata->rstc);
3229
f90a0612 3230err_clk_ciu:
7037f3be 3231 clk_disable_unprepare(host->ciu_clk);
780f22af 3232
f90a0612 3233err_clk_biu:
7037f3be 3234 clk_disable_unprepare(host->biu_clk);
780f22af 3235
f95f3850
WN		 3236 return ret;
3237}
62ca8034 3238EXPORT_SYMBOL(dw_mci_probe);
f95f3850 3239
62ca8034 3240void dw_mci_remove(struct dw_mci *host)
f95f3850 3241{
f95f3850
WN		 3242 int i;
3243
f95f3850 3244 for (i = 0; i < host->num_slots; i++) {
4a90920c 3245 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 3246 if (host->slot[i])
3247 dw_mci_cleanup_slot(host->slot[i], i);
3248 }
3249
048fd7e6
PT		 3250 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3251 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3252
f95f3850
WN		 3253 /* disable clock to CIU */
3254 mci_writel(host, CLKENA, 0);
3255 mci_writel(host, CLKSRC, 0);
3256
f95f3850
WN		 3257 if (host->use_dma && host->dma_ops->exit)
3258 host->dma_ops->exit(host);
3259
d6786fef
GX		 3260 if (!IS_ERR(host->pdata->rstc))
3261 reset_control_assert(host->pdata->rstc);
3262
7037f3be
JC		 3263 clk_disable_unprepare(host->ciu_clk);
3264 clk_disable_unprepare(host->biu_clk);
f95f3850 3265}
62ca8034
SH		 3266EXPORT_SYMBOL(dw_mci_remove);
3267
3268
f95f3850 3269
6fe8890d 3270#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 3271/*
3272 * TODO: we should probably disable the clock to the card in the suspend path.
3273 */
62ca8034 3274int dw_mci_suspend(struct dw_mci *host)
f95f3850 3275{
3fc7eaef
SL		 3276 if (host->use_dma && host->dma_ops->exit)
3277 host->dma_ops->exit(host);
3278
f95f3850
WN		 3279 return 0;
3280}
62ca8034 3281EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 3282
62ca8034 3283int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 3284{
3285 int i, ret;
f95f3850 3286
3a33a94c 3287 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
e61cf118
JC		 3288 ret = -ENODEV;
3289 return ret;
3290 }
3291
3bfe619d 3292 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 3293 host->dma_ops->init(host);
3294
52426899
SJ		 3295 /*
3296 * Restore the initial value at FIFOTH register
3297 * And Invalidate the prev_blksz with zero
3298 */
e61cf118 3299 mci_writel(host, FIFOTH, host->fifoth_val);
52426899 3300 host->prev_blksz = 0;
e61cf118 3301
2eb2944f
DA		 3302 /* Put in max timeout */
3303 mci_writel(host, TMOUT, 0xFFFFFFFF);
3304
e61cf118
JC		 3305 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3306 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3307 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3308 DW_MCI_ERROR_FLAGS);
e61cf118
JC		 3309 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3310
f95f3850
WN		 3311 for (i = 0; i < host->num_slots; i++) {
3312 struct dw_mci_slot *slot = host->slot[i];
0e3a22c0 3313
f95f3850
WN		 3314 if (!slot)
3315 continue;
ab269128
AK		 3316 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3317 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3318 dw_mci_setup_bus(slot, true);
3319 }
f95f3850 3320 }
fa0c3283
DA		 3321
3322 /* Now that slots are all setup, we can enable card detect */
3323 dw_mci_enable_cd(host);
3324
f95f3850
WN		 3325 return 0;
3326}
62ca8034 3327EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 3328#endif /* CONFIG_PM_SLEEP */
3329
f95f3850
WN		 3330static int __init dw_mci_init(void)
3331{
8e1c4e4d 3332 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
62ca8034 3333 return 0;
f95f3850
WN		 3334}
3335
3336static void __exit dw_mci_exit(void)
3337{
f95f3850
WN		 3338}
3339
3340module_init(dw_mci_init);
3341module_exit(dw_mci_exit);
3342
3343MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3344MODULE_AUTHOR("NXP Semiconductor VietNam");
3345MODULE_AUTHOR("Imagination Technologies Ltd");
3346MODULE_LICENSE("GPL v2");
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