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mmc: sdhci-s3c: Fix return value in sdhci_s3c_suspend/resume()
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/scatterlist.h>
26#include <linux/seq_file.h>
27#include <linux/slab.h>
28#include <linux/stat.h>
29#include <linux/delay.h>
30#include <linux/irq.h>
31#include <linux/mmc/host.h>
32#include <linux/mmc/mmc.h>
33#include <linux/mmc/dw_mmc.h>
34#include <linux/bitops.h>
c07946a3 35#include <linux/regulator/consumer.h>
1791b13e 36#include <linux/workqueue.h>
f95f3850
WN		 37
38#include "dw_mmc.h"
39
40/* Common flag combinations */
41#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
42 SDMMC_INT_HTO | SDMMC_INT_SBE | \
43 SDMMC_INT_EBE)
44#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
45 SDMMC_INT_RESP_ERR)
46#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
47 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
48#define DW_MCI_SEND_STATUS 1
49#define DW_MCI_RECV_STATUS 2
50#define DW_MCI_DMA_THRESHOLD 16
51
52#ifdef CONFIG_MMC_DW_IDMAC
53struct idmac_desc {
54 u32 des0; /* Control Descriptor */
55#define IDMAC_DES0_DIC BIT(1)
56#define IDMAC_DES0_LD BIT(2)
57#define IDMAC_DES0_FD BIT(3)
58#define IDMAC_DES0_CH BIT(4)
59#define IDMAC_DES0_ER BIT(5)
60#define IDMAC_DES0_CES BIT(30)
61#define IDMAC_DES0_OWN BIT(31)
62
63 u32 des1; /* Buffer sizes */
64#define IDMAC_SET_BUFFER1_SIZE(d, s) \
65 ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff))
66
67 u32 des2; /* buffer 1 physical address */
68
69 u32 des3; /* buffer 2 physical address */
70};
71#endif /* CONFIG_MMC_DW_IDMAC */
72
73/**
74 * struct dw_mci_slot - MMC slot state
75 * @mmc: The mmc_host representing this slot.
76 * @host: The MMC controller this slot is using.
77 * @ctype: Card type for this slot.
78 * @mrq: mmc_request currently being processed or waiting to be
79 * processed, or NULL when the slot is idle.
80 * @queue_node: List node for placing this node in the @queue list of
81 * &struct dw_mci.
82 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
83 * @flags: Random state bits associated with the slot.
84 * @id: Number of this slot.
85 * @last_detect_state: Most recently observed card detect state.
86 */
87struct dw_mci_slot {
88 struct mmc_host *mmc;
89 struct dw_mci *host;
90
91 u32 ctype;
92
93 struct mmc_request *mrq;
94 struct list_head queue_node;
95
96 unsigned int clock;
97 unsigned long flags;
98#define DW_MMC_CARD_PRESENT 0
99#define DW_MMC_CARD_NEED_INIT 1
100 int id;
101 int last_detect_state;
102};
103
1791b13e
JH		 104static struct workqueue_struct *dw_mci_card_workqueue;
105
f95f3850
WN		 106#if defined(CONFIG_DEBUG_FS)
107static int dw_mci_req_show(struct seq_file *s, void *v)
108{
109 struct dw_mci_slot *slot = s->private;
110 struct mmc_request *mrq;
111 struct mmc_command *cmd;
112 struct mmc_command *stop;
113 struct mmc_data *data;
114
115 /* Make sure we get a consistent snapshot */
116 spin_lock_bh(&slot->host->lock);
117 mrq = slot->mrq;
118
119 if (mrq) {
120 cmd = mrq->cmd;
121 data = mrq->data;
122 stop = mrq->stop;
123
124 if (cmd)
125 seq_printf(s,
126 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
127 cmd->opcode, cmd->arg, cmd->flags,
128 cmd->resp[0], cmd->resp[1], cmd->resp[2],
129 cmd->resp[2], cmd->error);
130 if (data)
131 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
132 data->bytes_xfered, data->blocks,
133 data->blksz, data->flags, data->error);
134 if (stop)
135 seq_printf(s,
136 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
137 stop->opcode, stop->arg, stop->flags,
138 stop->resp[0], stop->resp[1], stop->resp[2],
139 stop->resp[2], stop->error);
140 }
141
142 spin_unlock_bh(&slot->host->lock);
143
144 return 0;
145}
146
147static int dw_mci_req_open(struct inode *inode, struct file *file)
148{
149 return single_open(file, dw_mci_req_show, inode->i_private);
150}
151
152static const struct file_operations dw_mci_req_fops = {
153 .owner = THIS_MODULE,
154 .open = dw_mci_req_open,
155 .read = seq_read,
156 .llseek = seq_lseek,
157 .release = single_release,
158};
159
160static int dw_mci_regs_show(struct seq_file *s, void *v)
161{
162 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
163 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
164 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
165 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
166 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
167 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
168
169 return 0;
170}
171
172static int dw_mci_regs_open(struct inode *inode, struct file *file)
173{
174 return single_open(file, dw_mci_regs_show, inode->i_private);
175}
176
177static const struct file_operations dw_mci_regs_fops = {
178 .owner = THIS_MODULE,
179 .open = dw_mci_regs_open,
180 .read = seq_read,
181 .llseek = seq_lseek,
182 .release = single_release,
183};
184
185static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
186{
187 struct mmc_host *mmc = slot->mmc;
188 struct dw_mci *host = slot->host;
189 struct dentry *root;
190 struct dentry *node;
191
192 root = mmc->debugfs_root;
193 if (!root)
194 return;
195
196 node = debugfs_create_file("regs", S_IRUSR, root, host,
197 &dw_mci_regs_fops);
198 if (!node)
199 goto err;
200
201 node = debugfs_create_file("req", S_IRUSR, root, slot,
202 &dw_mci_req_fops);
203 if (!node)
204 goto err;
205
206 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
207 if (!node)
208 goto err;
209
210 node = debugfs_create_x32("pending_events", S_IRUSR, root,
211 (u32 *)&host->pending_events);
212 if (!node)
213 goto err;
214
215 node = debugfs_create_x32("completed_events", S_IRUSR, root,
216 (u32 *)&host->completed_events);
217 if (!node)
218 goto err;
219
220 return;
221
222err:
223 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
224}
225#endif /* defined(CONFIG_DEBUG_FS) */
226
227static void dw_mci_set_timeout(struct dw_mci *host)
228{
229 /* timeout (maximum) */
230 mci_writel(host, TMOUT, 0xffffffff);
231}
232
233static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
234{
235 struct mmc_data *data;
236 u32 cmdr;
237 cmd->error = -EINPROGRESS;
238
239 cmdr = cmd->opcode;
240
241 if (cmdr == MMC_STOP_TRANSMISSION)
242 cmdr |= SDMMC_CMD_STOP;
243 else
244 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
245
246 if (cmd->flags & MMC_RSP_PRESENT) {
247 /* We expect a response, so set this bit */
248 cmdr |= SDMMC_CMD_RESP_EXP;
249 if (cmd->flags & MMC_RSP_136)
250 cmdr |= SDMMC_CMD_RESP_LONG;
251 }
252
253 if (cmd->flags & MMC_RSP_CRC)
254 cmdr |= SDMMC_CMD_RESP_CRC;
255
256 data = cmd->data;
257 if (data) {
258 cmdr |= SDMMC_CMD_DAT_EXP;
259 if (data->flags & MMC_DATA_STREAM)
260 cmdr |= SDMMC_CMD_STRM_MODE;
261 if (data->flags & MMC_DATA_WRITE)
262 cmdr |= SDMMC_CMD_DAT_WR;
263 }
264
265 return cmdr;
266}
267
268static void dw_mci_start_command(struct dw_mci *host,
269 struct mmc_command *cmd, u32 cmd_flags)
270{
271 host->cmd = cmd;
272 dev_vdbg(&host->pdev->dev,
273 "start command: ARGR=0x%08x CMDR=0x%08x\n",
274 cmd->arg, cmd_flags);
275
276 mci_writel(host, CMDARG, cmd->arg);
277 wmb();
278
279 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
280}
281
282static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
283{
284 dw_mci_start_command(host, data->stop, host->stop_cmdr);
285}
286
287/* DMA interface functions */
288static void dw_mci_stop_dma(struct dw_mci *host)
289{
290 if (host->use_dma) {
291 host->dma_ops->stop(host);
292 host->dma_ops->cleanup(host);
293 } else {
294 /* Data transfer was stopped by the interrupt handler */
295 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
296 }
297}
298
299#ifdef CONFIG_MMC_DW_IDMAC
300static void dw_mci_dma_cleanup(struct dw_mci *host)
301{
302 struct mmc_data *data = host->data;
303
304 if (data)
305 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
306 ((data->flags & MMC_DATA_WRITE)
307 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
308}
309
310static void dw_mci_idmac_stop_dma(struct dw_mci *host)
311{
312 u32 temp;
313
314 /* Disable and reset the IDMAC interface */
315 temp = mci_readl(host, CTRL);
316 temp &= ~SDMMC_CTRL_USE_IDMAC;
317 temp |= SDMMC_CTRL_DMA_RESET;
318 mci_writel(host, CTRL, temp);
319
320 /* Stop the IDMAC running */
321 temp = mci_readl(host, BMOD);
a5289a43 322 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
f95f3850
WN		 323 mci_writel(host, BMOD, temp);
324}
325
326static void dw_mci_idmac_complete_dma(struct dw_mci *host)
327{
328 struct mmc_data *data = host->data;
329
330 dev_vdbg(&host->pdev->dev, "DMA complete\n");
331
332 host->dma_ops->cleanup(host);
333
334 /*
335 * If the card was removed, data will be NULL. No point in trying to
336 * send the stop command or waiting for NBUSY in this case.
337 */
338 if (data) {
339 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
340 tasklet_schedule(&host->tasklet);
341 }
342}
343
344static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
345 unsigned int sg_len)
346{
347 int i;
348 struct idmac_desc *desc = host->sg_cpu;
349
350 for (i = 0; i < sg_len; i++, desc++) {
351 unsigned int length = sg_dma_len(&data->sg[i]);
352 u32 mem_addr = sg_dma_address(&data->sg[i]);
353
354 /* Set the OWN bit and disable interrupts for this descriptor */
355 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
356
357 /* Buffer length */
358 IDMAC_SET_BUFFER1_SIZE(desc, length);
359
360 /* Physical address to DMA to/from */
361 desc->des2 = mem_addr;
362 }
363
364 /* Set first descriptor */
365 desc = host->sg_cpu;
366 desc->des0 |= IDMAC_DES0_FD;
367
368 /* Set last descriptor */
369 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
370 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
371 desc->des0 |= IDMAC_DES0_LD;
372
373 wmb();
374}
375
376static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
377{
378 u32 temp;
379
380 dw_mci_translate_sglist(host, host->data, sg_len);
381
382 /* Select IDMAC interface */
383 temp = mci_readl(host, CTRL);
384 temp |= SDMMC_CTRL_USE_IDMAC;
385 mci_writel(host, CTRL, temp);
386
387 wmb();
388
389 /* Enable the IDMAC */
390 temp = mci_readl(host, BMOD);
a5289a43 391 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 392 mci_writel(host, BMOD, temp);
393
394 /* Start it running */
395 mci_writel(host, PLDMND, 1);
396}
397
398static int dw_mci_idmac_init(struct dw_mci *host)
399{
400 struct idmac_desc *p;
401 int i;
402
403 /* Number of descriptors in the ring buffer */
404 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
405
406 /* Forward link the descriptor list */
407 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
408 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
409
410 /* Set the last descriptor as the end-of-ring descriptor */
411 p->des3 = host->sg_dma;
412 p->des0 = IDMAC_DES0_ER;
413
414 /* Mask out interrupts - get Tx & Rx complete only */
415 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
416 SDMMC_IDMAC_INT_TI);
417
418 /* Set the descriptor base address */
419 mci_writel(host, DBADDR, host->sg_dma);
420 return 0;
421}
422
423static struct dw_mci_dma_ops dw_mci_idmac_ops = {
424 .init = dw_mci_idmac_init,
425 .start = dw_mci_idmac_start_dma,
426 .stop = dw_mci_idmac_stop_dma,
427 .complete = dw_mci_idmac_complete_dma,
428 .cleanup = dw_mci_dma_cleanup,
429};
430#endif /* CONFIG_MMC_DW_IDMAC */
431
432static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
433{
434 struct scatterlist *sg;
435 unsigned int i, direction, sg_len;
436 u32 temp;
437
438 /* If we don't have a channel, we can't do DMA */
439 if (!host->use_dma)
440 return -ENODEV;
441
442 /*
443 * We don't do DMA on "complex" transfers, i.e. with
444 * non-word-aligned buffers or lengths. Also, we don't bother
445 * with all the DMA setup overhead for short transfers.
446 */
447 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
448 return -EINVAL;
449 if (data->blksz & 3)
450 return -EINVAL;
451
452 for_each_sg(data->sg, sg, data->sg_len, i) {
453 if (sg->offset & 3 || sg->length & 3)
454 return -EINVAL;
455 }
456
457 if (data->flags & MMC_DATA_READ)
458 direction = DMA_FROM_DEVICE;
459 else
460 direction = DMA_TO_DEVICE;
461
462 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
463 direction);
464
465 dev_vdbg(&host->pdev->dev,
466 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
467 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
468 sg_len);
469
470 /* Enable the DMA interface */
471 temp = mci_readl(host, CTRL);
472 temp |= SDMMC_CTRL_DMA_ENABLE;
473 mci_writel(host, CTRL, temp);
474
475 /* Disable RX/TX IRQs, let DMA handle it */
476 temp = mci_readl(host, INTMASK);
477 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
478 mci_writel(host, INTMASK, temp);
479
480 host->dma_ops->start(host, sg_len);
481
482 return 0;
483}
484
485static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
486{
487 u32 temp;
488
489 data->error = -EINPROGRESS;
490
491 WARN_ON(host->data);
492 host->sg = NULL;
493 host->data = data;
494
495 if (dw_mci_submit_data_dma(host, data)) {
496 host->sg = data->sg;
497 host->pio_offset = 0;
34b664a2
JH		 498 host->part_buf_start = 0;
499 host->part_buf_count = 0;
f95f3850
WN		 500 if (data->flags & MMC_DATA_READ)
501 host->dir_status = DW_MCI_RECV_STATUS;
502 else
503 host->dir_status = DW_MCI_SEND_STATUS;
504
b40af3aa 505 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 506 temp = mci_readl(host, INTMASK);
507 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
508 mci_writel(host, INTMASK, temp);
509
510 temp = mci_readl(host, CTRL);
511 temp &= ~SDMMC_CTRL_DMA_ENABLE;
512 mci_writel(host, CTRL, temp);
513 }
514}
515
516static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
517{
518 struct dw_mci *host = slot->host;
519 unsigned long timeout = jiffies + msecs_to_jiffies(500);
520 unsigned int cmd_status = 0;
521
522 mci_writel(host, CMDARG, arg);
523 wmb();
524 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
525
526 while (time_before(jiffies, timeout)) {
527 cmd_status = mci_readl(host, CMD);
528 if (!(cmd_status & SDMMC_CMD_START))
529 return;
530 }
531 dev_err(&slot->mmc->class_dev,
532 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
533 cmd, arg, cmd_status);
534}
535
536static void dw_mci_setup_bus(struct dw_mci_slot *slot)
537{
538 struct dw_mci *host = slot->host;
539 u32 div;
540
541 if (slot->clock != host->current_speed) {
542 if (host->bus_hz % slot->clock)
543 /*
544 * move the + 1 after the divide to prevent
545 * over-clocking the card.
546 */
547 div = ((host->bus_hz / slot->clock) >> 1) + 1;
548 else
549 div = (host->bus_hz / slot->clock) >> 1;
550
551 dev_info(&slot->mmc->class_dev,
552 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
553 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
554 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
555
556 /* disable clock */
557 mci_writel(host, CLKENA, 0);
558 mci_writel(host, CLKSRC, 0);
559
560 /* inform CIU */
561 mci_send_cmd(slot,
562 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
563
564 /* set clock to desired speed */
565 mci_writel(host, CLKDIV, div);
566
567 /* inform CIU */
568 mci_send_cmd(slot,
569 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
570
571 /* enable clock */
aadb9f41
WN		 572 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
573 SDMMC_CLKEN_LOW_PWR);
f95f3850
WN		 574
575 /* inform CIU */
576 mci_send_cmd(slot,
577 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
578
579 host->current_speed = slot->clock;
580 }
581
582 /* Set the current slot bus width */
1d56c453 583 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 584}
585
586static void dw_mci_start_request(struct dw_mci *host,
587 struct dw_mci_slot *slot)
588{
589 struct mmc_request *mrq;
590 struct mmc_command *cmd;
591 struct mmc_data *data;
592 u32 cmdflags;
593
594 mrq = slot->mrq;
595 if (host->pdata->select_slot)
596 host->pdata->select_slot(slot->id);
597
598 /* Slot specific timing and width adjustment */
599 dw_mci_setup_bus(slot);
600
601 host->cur_slot = slot;
602 host->mrq = mrq;
603
604 host->pending_events = 0;
605 host->completed_events = 0;
606 host->data_status = 0;
607
608 data = mrq->data;
609 if (data) {
610 dw_mci_set_timeout(host);
611 mci_writel(host, BYTCNT, data->blksz*data->blocks);
612 mci_writel(host, BLKSIZ, data->blksz);
613 }
614
615 cmd = mrq->cmd;
616 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
617
618 /* this is the first command, send the initialization clock */
619 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
620 cmdflags |= SDMMC_CMD_INIT;
621
622 if (data) {
623 dw_mci_submit_data(host, data);
624 wmb();
625 }
626
627 dw_mci_start_command(host, cmd, cmdflags);
628
629 if (mrq->stop)
630 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
631}
632
7456caae 633/* must be called with host->lock held */
f95f3850
WN		 634static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
635 struct mmc_request *mrq)
636{
637 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
638 host->state);
639
f95f3850
WN		 640 slot->mrq = mrq;
641
642 if (host->state == STATE_IDLE) {
643 host->state = STATE_SENDING_CMD;
644 dw_mci_start_request(host, slot);
645 } else {
646 list_add_tail(&slot->queue_node, &host->queue);
647 }
f95f3850
WN		 648}
649
650static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
651{
652 struct dw_mci_slot *slot = mmc_priv(mmc);
653 struct dw_mci *host = slot->host;
654
655 WARN_ON(slot->mrq);
656
7456caae
JH		 657 /*
658 * The check for card presence and queueing of the request must be
659 * atomic, otherwise the card could be removed in between and the
660 * request wouldn't fail until another card was inserted.
661 */
662 spin_lock_bh(&host->lock);
663
f95f3850 664 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 665 spin_unlock_bh(&host->lock);
f95f3850
WN		 666 mrq->cmd->error = -ENOMEDIUM;
667 mmc_request_done(mmc, mrq);
668 return;
669 }
670
f95f3850 671 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 672
673 spin_unlock_bh(&host->lock);
f95f3850
WN		 674}
675
676static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
677{
678 struct dw_mci_slot *slot = mmc_priv(mmc);
41babf75 679 u32 regs;
f95f3850
WN		 680
681 /* set default 1 bit mode */
682 slot->ctype = SDMMC_CTYPE_1BIT;
683
684 switch (ios->bus_width) {
685 case MMC_BUS_WIDTH_1:
686 slot->ctype = SDMMC_CTYPE_1BIT;
687 break;
688 case MMC_BUS_WIDTH_4:
689 slot->ctype = SDMMC_CTYPE_4BIT;
690 break;
c9b2a06f
JC		 691 case MMC_BUS_WIDTH_8:
692 slot->ctype = SDMMC_CTYPE_8BIT;
693 break;
f95f3850
WN		 694 }
695
41babf75
JC		 696 /* DDR mode set */
697 if (ios->ddr) {
698 regs = mci_readl(slot->host, UHS_REG);
699 regs |= (0x1 << slot->id) << 16;
700 mci_writel(slot->host, UHS_REG, regs);
701 }
702
f95f3850
WN		 703 if (ios->clock) {
704 /*
705 * Use mirror of ios->clock to prevent race with mmc
706 * core ios update when finding the minimum.
707 */
708 slot->clock = ios->clock;
709 }
710
711 switch (ios->power_mode) {
712 case MMC_POWER_UP:
713 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
714 break;
715 default:
716 break;
717 }
718}
719
720static int dw_mci_get_ro(struct mmc_host *mmc)
721{
722 int read_only;
723 struct dw_mci_slot *slot = mmc_priv(mmc);
724 struct dw_mci_board *brd = slot->host->pdata;
725
726 /* Use platform get_ro function, else try on board write protect */
727 if (brd->get_ro)
728 read_only = brd->get_ro(slot->id);
729 else
730 read_only =
731 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
732
733 dev_dbg(&mmc->class_dev, "card is %s\n",
734 read_only ? "read-only" : "read-write");
735
736 return read_only;
737}
738
739static int dw_mci_get_cd(struct mmc_host *mmc)
740{
741 int present;
742 struct dw_mci_slot *slot = mmc_priv(mmc);
743 struct dw_mci_board *brd = slot->host->pdata;
744
745 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 746 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
747 present = 1;
748 else if (brd->get_cd)
f95f3850
WN		 749 present = !brd->get_cd(slot->id);
750 else
751 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
752 == 0 ? 1 : 0;
753
754 if (present)
755 dev_dbg(&mmc->class_dev, "card is present\n");
756 else
757 dev_dbg(&mmc->class_dev, "card is not present\n");
758
759 return present;
760}
761
762static const struct mmc_host_ops dw_mci_ops = {
763 .request = dw_mci_request,
764 .set_ios = dw_mci_set_ios,
765 .get_ro = dw_mci_get_ro,
766 .get_cd = dw_mci_get_cd,
767};
768
769static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
770 __releases(&host->lock)
771 __acquires(&host->lock)
772{
773 struct dw_mci_slot *slot;
774 struct mmc_host *prev_mmc = host->cur_slot->mmc;
775
776 WARN_ON(host->cmd || host->data);
777
778 host->cur_slot->mrq = NULL;
779 host->mrq = NULL;
780 if (!list_empty(&host->queue)) {
781 slot = list_entry(host->queue.next,
782 struct dw_mci_slot, queue_node);
783 list_del(&slot->queue_node);
784 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
785 mmc_hostname(slot->mmc));
786 host->state = STATE_SENDING_CMD;
787 dw_mci_start_request(host, slot);
788 } else {
789 dev_vdbg(&host->pdev->dev, "list empty\n");
790 host->state = STATE_IDLE;
791 }
792
793 spin_unlock(&host->lock);
794 mmc_request_done(prev_mmc, mrq);
795 spin_lock(&host->lock);
796}
797
798static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
799{
800 u32 status = host->cmd_status;
801
802 host->cmd_status = 0;
803
804 /* Read the response from the card (up to 16 bytes) */
805 if (cmd->flags & MMC_RSP_PRESENT) {
806 if (cmd->flags & MMC_RSP_136) {
807 cmd->resp[3] = mci_readl(host, RESP0);
808 cmd->resp[2] = mci_readl(host, RESP1);
809 cmd->resp[1] = mci_readl(host, RESP2);
810 cmd->resp[0] = mci_readl(host, RESP3);
811 } else {
812 cmd->resp[0] = mci_readl(host, RESP0);
813 cmd->resp[1] = 0;
814 cmd->resp[2] = 0;
815 cmd->resp[3] = 0;
816 }
817 }
818
819 if (status & SDMMC_INT_RTO)
820 cmd->error = -ETIMEDOUT;
821 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
822 cmd->error = -EILSEQ;
823 else if (status & SDMMC_INT_RESP_ERR)
824 cmd->error = -EIO;
825 else
826 cmd->error = 0;
827
828 if (cmd->error) {
829 /* newer ip versions need a delay between retries */
830 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
831 mdelay(20);
832
833 if (cmd->data) {
834 host->data = NULL;
835 dw_mci_stop_dma(host);
836 }
837 }
838}
839
840static void dw_mci_tasklet_func(unsigned long priv)
841{
842 struct dw_mci *host = (struct dw_mci *)priv;
843 struct mmc_data *data;
844 struct mmc_command *cmd;
845 enum dw_mci_state state;
846 enum dw_mci_state prev_state;
847 u32 status;
848
849 spin_lock(&host->lock);
850
851 state = host->state;
852 data = host->data;
853
854 do {
855 prev_state = state;
856
857 switch (state) {
858 case STATE_IDLE:
859 break;
860
861 case STATE_SENDING_CMD:
862 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
863 &host->pending_events))
864 break;
865
866 cmd = host->cmd;
867 host->cmd = NULL;
868 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
869 dw_mci_command_complete(host, host->mrq->cmd);
870 if (!host->mrq->data || cmd->error) {
871 dw_mci_request_end(host, host->mrq);
872 goto unlock;
873 }
874
875 prev_state = state = STATE_SENDING_DATA;
876 /* fall through */
877
878 case STATE_SENDING_DATA:
879 if (test_and_clear_bit(EVENT_DATA_ERROR,
880 &host->pending_events)) {
881 dw_mci_stop_dma(host);
882 if (data->stop)
883 send_stop_cmd(host, data);
884 state = STATE_DATA_ERROR;
885 break;
886 }
887
888 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
889 &host->pending_events))
890 break;
891
892 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
893 prev_state = state = STATE_DATA_BUSY;
894 /* fall through */
895
896 case STATE_DATA_BUSY:
897 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
898 &host->pending_events))
899 break;
900
901 host->data = NULL;
902 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
903 status = host->data_status;
904
905 if (status & DW_MCI_DATA_ERROR_FLAGS) {
906 if (status & SDMMC_INT_DTO) {
907 dev_err(&host->pdev->dev,
908 "data timeout error\n");
909 data->error = -ETIMEDOUT;
910 } else if (status & SDMMC_INT_DCRC) {
911 dev_err(&host->pdev->dev,
912 "data CRC error\n");
913 data->error = -EILSEQ;
914 } else {
915 dev_err(&host->pdev->dev,
916 "data FIFO error "
917 "(status=%08x)\n",
918 status);
919 data->error = -EIO;
920 }
921 } else {
922 data->bytes_xfered = data->blocks * data->blksz;
923 data->error = 0;
924 }
925
926 if (!data->stop) {
927 dw_mci_request_end(host, host->mrq);
928 goto unlock;
929 }
930
931 prev_state = state = STATE_SENDING_STOP;
932 if (!data->error)
933 send_stop_cmd(host, data);
934 /* fall through */
935
936 case STATE_SENDING_STOP:
937 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
938 &host->pending_events))
939 break;
940
941 host->cmd = NULL;
942 dw_mci_command_complete(host, host->mrq->stop);
943 dw_mci_request_end(host, host->mrq);
944 goto unlock;
945
946 case STATE_DATA_ERROR:
947 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
948 &host->pending_events))
949 break;
950
951 state = STATE_DATA_BUSY;
952 break;
953 }
954 } while (state != prev_state);
955
956 host->state = state;
957unlock:
958 spin_unlock(&host->lock);
959
960}
961
34b664a2
JH		 962/* push final bytes to part_buf, only use during push */
963static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 964{
34b664a2
JH		 965 memcpy((void *)&host->part_buf, buf, cnt);
966 host->part_buf_count = cnt;
967}
f95f3850 968
34b664a2
JH		 969/* append bytes to part_buf, only use during push */
970static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
971{
972 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
973 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
974 host->part_buf_count += cnt;
975 return cnt;
976}
f95f3850 977
34b664a2
JH		 978/* pull first bytes from part_buf, only use during pull */
979static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
980{
981 cnt = min(cnt, (int)host->part_buf_count);
982 if (cnt) {
983 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
984 cnt);
985 host->part_buf_count -= cnt;
986 host->part_buf_start += cnt;
f95f3850 987 }
34b664a2 988 return cnt;
f95f3850
WN		 989}
990
34b664a2
JH		 991/* pull final bytes from the part_buf, assuming it's just been filled */
992static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 993{
34b664a2
JH		 994 memcpy(buf, &host->part_buf, cnt);
995 host->part_buf_start = cnt;
996 host->part_buf_count = (1 << host->data_shift) - cnt;
997}
f95f3850 998
34b664a2
JH		 999static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1000{
1001 /* try and push anything in the part_buf */
1002 if (unlikely(host->part_buf_count)) {
1003 int len = dw_mci_push_part_bytes(host, buf, cnt);
1004 buf += len;
1005 cnt -= len;
1006 if (!sg_next(host->sg) || host->part_buf_count == 2) {
1007 mci_writew(host, DATA, host->part_buf16);
1008 host->part_buf_count = 0;
1009 }
1010 }
1011#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1012 if (unlikely((unsigned long)buf & 0x1)) {
1013 while (cnt >= 2) {
1014 u16 aligned_buf[64];
1015 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1016 int items = len >> 1;
1017 int i;
1018 /* memcpy from input buffer into aligned buffer */
1019 memcpy(aligned_buf, buf, len);
1020 buf += len;
1021 cnt -= len;
1022 /* push data from aligned buffer into fifo */
1023 for (i = 0; i < items; ++i)
1024 mci_writew(host, DATA, aligned_buf[i]);
1025 }
1026 } else
1027#endif
1028 {
1029 u16 *pdata = buf;
1030 for (; cnt >= 2; cnt -= 2)
1031 mci_writew(host, DATA, *pdata++);
1032 buf = pdata;
1033 }
1034 /* put anything remaining in the part_buf */
1035 if (cnt) {
1036 dw_mci_set_part_bytes(host, buf, cnt);
1037 if (!sg_next(host->sg))
1038 mci_writew(host, DATA, host->part_buf16);
1039 }
1040}
f95f3850 1041
34b664a2
JH		 1042static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1043{
1044#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1045 if (unlikely((unsigned long)buf & 0x1)) {
1046 while (cnt >= 2) {
1047 /* pull data from fifo into aligned buffer */
1048 u16 aligned_buf[64];
1049 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1050 int items = len >> 1;
1051 int i;
1052 for (i = 0; i < items; ++i)
1053 aligned_buf[i] = mci_readw(host, DATA);
1054 /* memcpy from aligned buffer into output buffer */
1055 memcpy(buf, aligned_buf, len);
1056 buf += len;
1057 cnt -= len;
1058 }
1059 } else
1060#endif
1061 {
1062 u16 *pdata = buf;
1063 for (; cnt >= 2; cnt -= 2)
1064 *pdata++ = mci_readw(host, DATA);
1065 buf = pdata;
1066 }
1067 if (cnt) {
1068 host->part_buf16 = mci_readw(host, DATA);
1069 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1070 }
1071}
1072
1073static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1074{
34b664a2
JH		 1075 /* try and push anything in the part_buf */
1076 if (unlikely(host->part_buf_count)) {
1077 int len = dw_mci_push_part_bytes(host, buf, cnt);
1078 buf += len;
1079 cnt -= len;
1080 if (!sg_next(host->sg) || host->part_buf_count == 4) {
1081 mci_writel(host, DATA, host->part_buf32);
1082 host->part_buf_count = 0;
1083 }
1084 }
1085#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1086 if (unlikely((unsigned long)buf & 0x3)) {
1087 while (cnt >= 4) {
1088 u32 aligned_buf[32];
1089 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1090 int items = len >> 2;
1091 int i;
1092 /* memcpy from input buffer into aligned buffer */
1093 memcpy(aligned_buf, buf, len);
1094 buf += len;
1095 cnt -= len;
1096 /* push data from aligned buffer into fifo */
1097 for (i = 0; i < items; ++i)
1098 mci_writel(host, DATA, aligned_buf[i]);
1099 }
1100 } else
1101#endif
1102 {
1103 u32 *pdata = buf;
1104 for (; cnt >= 4; cnt -= 4)
1105 mci_writel(host, DATA, *pdata++);
1106 buf = pdata;
1107 }
1108 /* put anything remaining in the part_buf */
1109 if (cnt) {
1110 dw_mci_set_part_bytes(host, buf, cnt);
1111 if (!sg_next(host->sg))
1112 mci_writel(host, DATA, host->part_buf32);
f95f3850
WN		 1113 }
1114}
1115
1116static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1117{
34b664a2
JH		 1118#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1119 if (unlikely((unsigned long)buf & 0x3)) {
1120 while (cnt >= 4) {
1121 /* pull data from fifo into aligned buffer */
1122 u32 aligned_buf[32];
1123 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1124 int items = len >> 2;
1125 int i;
1126 for (i = 0; i < items; ++i)
1127 aligned_buf[i] = mci_readl(host, DATA);
1128 /* memcpy from aligned buffer into output buffer */
1129 memcpy(buf, aligned_buf, len);
1130 buf += len;
1131 cnt -= len;
1132 }
1133 } else
1134#endif
1135 {
1136 u32 *pdata = buf;
1137 for (; cnt >= 4; cnt -= 4)
1138 *pdata++ = mci_readl(host, DATA);
1139 buf = pdata;
1140 }
1141 if (cnt) {
1142 host->part_buf32 = mci_readl(host, DATA);
1143 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1144 }
1145}
1146
1147static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1148{
34b664a2
JH		 1149 /* try and push anything in the part_buf */
1150 if (unlikely(host->part_buf_count)) {
1151 int len = dw_mci_push_part_bytes(host, buf, cnt);
1152 buf += len;
1153 cnt -= len;
1154 if (!sg_next(host->sg) || host->part_buf_count == 8) {
1155 mci_writew(host, DATA, host->part_buf);
1156 host->part_buf_count = 0;
1157 }
1158 }
1159#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1160 if (unlikely((unsigned long)buf & 0x7)) {
1161 while (cnt >= 8) {
1162 u64 aligned_buf[16];
1163 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1164 int items = len >> 3;
1165 int i;
1166 /* memcpy from input buffer into aligned buffer */
1167 memcpy(aligned_buf, buf, len);
1168 buf += len;
1169 cnt -= len;
1170 /* push data from aligned buffer into fifo */
1171 for (i = 0; i < items; ++i)
1172 mci_writeq(host, DATA, aligned_buf[i]);
1173 }
1174 } else
1175#endif
1176 {
1177 u64 *pdata = buf;
1178 for (; cnt >= 8; cnt -= 8)
1179 mci_writeq(host, DATA, *pdata++);
1180 buf = pdata;
1181 }
1182 /* put anything remaining in the part_buf */
1183 if (cnt) {
1184 dw_mci_set_part_bytes(host, buf, cnt);
1185 if (!sg_next(host->sg))
1186 mci_writeq(host, DATA, host->part_buf);
f95f3850
WN		 1187 }
1188}
1189
1190static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1191{
34b664a2
JH		 1192#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1193 if (unlikely((unsigned long)buf & 0x7)) {
1194 while (cnt >= 8) {
1195 /* pull data from fifo into aligned buffer */
1196 u64 aligned_buf[16];
1197 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1198 int items = len >> 3;
1199 int i;
1200 for (i = 0; i < items; ++i)
1201 aligned_buf[i] = mci_readq(host, DATA);
1202 /* memcpy from aligned buffer into output buffer */
1203 memcpy(buf, aligned_buf, len);
1204 buf += len;
1205 cnt -= len;
1206 }
1207 } else
1208#endif
1209 {
1210 u64 *pdata = buf;
1211 for (; cnt >= 8; cnt -= 8)
1212 *pdata++ = mci_readq(host, DATA);
1213 buf = pdata;
1214 }
1215 if (cnt) {
1216 host->part_buf = mci_readq(host, DATA);
1217 dw_mci_pull_final_bytes(host, buf, cnt);
1218 }
1219}
f95f3850 1220
34b664a2
JH		 1221static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1222{
1223 int len;
f95f3850 1224
34b664a2
JH		 1225 /* get remaining partial bytes */
1226 len = dw_mci_pull_part_bytes(host, buf, cnt);
1227 if (unlikely(len == cnt))
1228 return;
1229 buf += len;
1230 cnt -= len;
1231
1232 /* get the rest of the data */
1233 host->pull_data(host, buf, cnt);
f95f3850
WN		 1234}
1235
1236static void dw_mci_read_data_pio(struct dw_mci *host)
1237{
1238 struct scatterlist *sg = host->sg;
1239 void *buf = sg_virt(sg);
1240 unsigned int offset = host->pio_offset;
1241 struct mmc_data *data = host->data;
1242 int shift = host->data_shift;
1243 u32 status;
ba6a902d 1244 unsigned int nbytes = 0, len;
f95f3850
WN		 1245
1246 do {
34b664a2
JH		 1247 len = host->part_buf_count +
1248 (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
f95f3850 1249 if (offset + len <= sg->length) {
34b664a2 1250 dw_mci_pull_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1251
1252 offset += len;
1253 nbytes += len;
1254
1255 if (offset == sg->length) {
1256 flush_dcache_page(sg_page(sg));
1257 host->sg = sg = sg_next(sg);
1258 if (!sg)
1259 goto done;
1260
1261 offset = 0;
1262 buf = sg_virt(sg);
1263 }
1264 } else {
1265 unsigned int remaining = sg->length - offset;
34b664a2
JH		 1266 dw_mci_pull_data(host, (void *)(buf + offset),
1267 remaining);
f95f3850
WN		 1268 nbytes += remaining;
1269
1270 flush_dcache_page(sg_page(sg));
1271 host->sg = sg = sg_next(sg);
1272 if (!sg)
1273 goto done;
1274
1275 offset = len - remaining;
1276 buf = sg_virt(sg);
34b664a2 1277 dw_mci_pull_data(host, buf, offset);
f95f3850
WN		 1278 nbytes += offset;
1279 }
1280
1281 status = mci_readl(host, MINTSTS);
1282 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1283 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1284 host->data_status = status;
1285 data->bytes_xfered += nbytes;
1286 smp_wmb();
1287
1288 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1289
1290 tasklet_schedule(&host->tasklet);
1291 return;
1292 }
f95f3850 1293 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
f95f3850
WN		 1294 host->pio_offset = offset;
1295 data->bytes_xfered += nbytes;
1296 return;
1297
1298done:
1299 data->bytes_xfered += nbytes;
1300 smp_wmb();
1301 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1302}
1303
1304static void dw_mci_write_data_pio(struct dw_mci *host)
1305{
1306 struct scatterlist *sg = host->sg;
1307 void *buf = sg_virt(sg);
1308 unsigned int offset = host->pio_offset;
1309 struct mmc_data *data = host->data;
1310 int shift = host->data_shift;
1311 u32 status;
1312 unsigned int nbytes = 0, len;
1313
1314 do {
34b664a2
JH		 1315 len = ((host->fifo_depth -
1316 SDMMC_GET_FCNT(mci_readl(host, STATUS))) << shift)
1317 - host->part_buf_count;
f95f3850
WN		 1318 if (offset + len <= sg->length) {
1319 host->push_data(host, (void *)(buf + offset), len);
1320
1321 offset += len;
1322 nbytes += len;
1323 if (offset == sg->length) {
1324 host->sg = sg = sg_next(sg);
1325 if (!sg)
1326 goto done;
1327
1328 offset = 0;
1329 buf = sg_virt(sg);
1330 }
1331 } else {
1332 unsigned int remaining = sg->length - offset;
1333
1334 host->push_data(host, (void *)(buf + offset),
1335 remaining);
1336 nbytes += remaining;
1337
1338 host->sg = sg = sg_next(sg);
1339 if (!sg)
1340 goto done;
1341
1342 offset = len - remaining;
1343 buf = sg_virt(sg);
1344 host->push_data(host, (void *)buf, offset);
1345 nbytes += offset;
1346 }
1347
1348 status = mci_readl(host, MINTSTS);
1349 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1350 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1351 host->data_status = status;
1352 data->bytes_xfered += nbytes;
1353
1354 smp_wmb();
1355
1356 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1357
1358 tasklet_schedule(&host->tasklet);
1359 return;
1360 }
1361 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f95f3850
WN		 1362 host->pio_offset = offset;
1363 data->bytes_xfered += nbytes;
f95f3850
WN		 1364 return;
1365
1366done:
1367 data->bytes_xfered += nbytes;
1368 smp_wmb();
1369 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1370}
1371
1372static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1373{
1374 if (!host->cmd_status)
1375 host->cmd_status = status;
1376
1377 smp_wmb();
1378
1379 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1380 tasklet_schedule(&host->tasklet);
1381}
1382
1383static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1384{
1385 struct dw_mci *host = dev_id;
1386 u32 status, pending;
1387 unsigned int pass_count = 0;
1388
1389 do {
1390 status = mci_readl(host, RINTSTS);
1391 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1392
1393 /*
1394 * DTO fix - version 2.10a and below, and only if internal DMA
1395 * is configured.
1396 */
1397 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1398 if (!pending &&
1399 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1400 pending |= SDMMC_INT_DATA_OVER;
1401 }
1402
1403 if (!pending)
1404 break;
1405
1406 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1407 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1408 host->cmd_status = status;
1409 smp_wmb();
1410 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1411 }
1412
1413 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1414 /* if there is an error report DATA_ERROR */
1415 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1416 host->data_status = status;
1417 smp_wmb();
1418 set_bit(EVENT_DATA_ERROR, &host->pending_events);
6e83e10d
SJ		 1419 if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1420 SDMMC_INT_SBE | SDMMC_INT_EBE)))
1421 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1422 }
1423
1424 if (pending & SDMMC_INT_DATA_OVER) {
1425 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1426 if (!host->data_status)
1427 host->data_status = status;
1428 smp_wmb();
1429 if (host->dir_status == DW_MCI_RECV_STATUS) {
1430 if (host->sg != NULL)
1431 dw_mci_read_data_pio(host);
1432 }
1433 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1434 tasklet_schedule(&host->tasklet);
1435 }
1436
1437 if (pending & SDMMC_INT_RXDR) {
1438 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 1439 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
f95f3850
WN		 1440 dw_mci_read_data_pio(host);
1441 }
1442
1443 if (pending & SDMMC_INT_TXDR) {
1444 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 1445 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 1446 dw_mci_write_data_pio(host);
1447 }
1448
1449 if (pending & SDMMC_INT_CMD_DONE) {
1450 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1451 dw_mci_cmd_interrupt(host, status);
1452 }
1453
1454 if (pending & SDMMC_INT_CD) {
1455 mci_writel(host, RINTSTS, SDMMC_INT_CD);
1791b13e 1456 queue_work(dw_mci_card_workqueue, &host->card_work);
f95f3850
WN		 1457 }
1458
1459 } while (pass_count++ < 5);
1460
1461#ifdef CONFIG_MMC_DW_IDMAC
1462 /* Handle DMA interrupts */
1463 pending = mci_readl(host, IDSTS);
1464 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1465 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1466 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1467 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1468 host->dma_ops->complete(host);
1469 }
1470#endif
1471
1472 return IRQ_HANDLED;
1473}
1474
1791b13e 1475static void dw_mci_work_routine_card(struct work_struct *work)
f95f3850 1476{
1791b13e 1477 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
f95f3850
WN		 1478 int i;
1479
1480 for (i = 0; i < host->num_slots; i++) {
1481 struct dw_mci_slot *slot = host->slot[i];
1482 struct mmc_host *mmc = slot->mmc;
1483 struct mmc_request *mrq;
1484 int present;
1485 u32 ctrl;
1486
1487 present = dw_mci_get_cd(mmc);
1488 while (present != slot->last_detect_state) {
f95f3850
WN		 1489 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1490 present ? "inserted" : "removed");
1491
1791b13e
JH		 1492 /* Power up slot (before spin_lock, may sleep) */
1493 if (present != 0 && host->pdata->setpower)
1494 host->pdata->setpower(slot->id, mmc->ocr_avail);
1495
1496 spin_lock_bh(&host->lock);
1497
f95f3850
WN		 1498 /* Card change detected */
1499 slot->last_detect_state = present;
1500
1791b13e
JH		 1501 /* Mark card as present if applicable */
1502 if (present != 0)
f95f3850 1503 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850
WN		 1504
1505 /* Clean up queue if present */
1506 mrq = slot->mrq;
1507 if (mrq) {
1508 if (mrq == host->mrq) {
1509 host->data = NULL;
1510 host->cmd = NULL;
1511
1512 switch (host->state) {
1513 case STATE_IDLE:
1514 break;
1515 case STATE_SENDING_CMD:
1516 mrq->cmd->error = -ENOMEDIUM;
1517 if (!mrq->data)
1518 break;
1519 /* fall through */
1520 case STATE_SENDING_DATA:
1521 mrq->data->error = -ENOMEDIUM;
1522 dw_mci_stop_dma(host);
1523 break;
1524 case STATE_DATA_BUSY:
1525 case STATE_DATA_ERROR:
1526 if (mrq->data->error == -EINPROGRESS)
1527 mrq->data->error = -ENOMEDIUM;
1528 if (!mrq->stop)
1529 break;
1530 /* fall through */
1531 case STATE_SENDING_STOP:
1532 mrq->stop->error = -ENOMEDIUM;
1533 break;
1534 }
1535
1536 dw_mci_request_end(host, mrq);
1537 } else {
1538 list_del(&slot->queue_node);
1539 mrq->cmd->error = -ENOMEDIUM;
1540 if (mrq->data)
1541 mrq->data->error = -ENOMEDIUM;
1542 if (mrq->stop)
1543 mrq->stop->error = -ENOMEDIUM;
1544
1545 spin_unlock(&host->lock);
1546 mmc_request_done(slot->mmc, mrq);
1547 spin_lock(&host->lock);
1548 }
1549 }
1550
1551 /* Power down slot */
1552 if (present == 0) {
f95f3850
WN		 1553 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1554
1555 /*
1556 * Clear down the FIFO - doing so generates a
1557 * block interrupt, hence setting the
1558 * scatter-gather pointer to NULL.
1559 */
1560 host->sg = NULL;
1561
1562 ctrl = mci_readl(host, CTRL);
1563 ctrl |= SDMMC_CTRL_FIFO_RESET;
1564 mci_writel(host, CTRL, ctrl);
1565
1566#ifdef CONFIG_MMC_DW_IDMAC
1567 ctrl = mci_readl(host, BMOD);
1568 ctrl |= 0x01; /* Software reset of DMA */
1569 mci_writel(host, BMOD, ctrl);
1570#endif
1571
1572 }
1573
1791b13e
JH		 1574 spin_unlock_bh(&host->lock);
1575
1576 /* Power down slot (after spin_unlock, may sleep) */
1577 if (present == 0 && host->pdata->setpower)
1578 host->pdata->setpower(slot->id, 0);
1579
f95f3850
WN		 1580 present = dw_mci_get_cd(mmc);
1581 }
1582
1583 mmc_detect_change(slot->mmc,
1584 msecs_to_jiffies(host->pdata->detect_delay_ms));
1585 }
1586}
1587
1588static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1589{
1590 struct mmc_host *mmc;
1591 struct dw_mci_slot *slot;
1592
1593 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1594 if (!mmc)
1595 return -ENOMEM;
1596
1597 slot = mmc_priv(mmc);
1598 slot->id = id;
1599 slot->mmc = mmc;
1600 slot->host = host;
1601
1602 mmc->ops = &dw_mci_ops;
1603 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1604 mmc->f_max = host->bus_hz;
1605
1606 if (host->pdata->get_ocr)
1607 mmc->ocr_avail = host->pdata->get_ocr(id);
1608 else
1609 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1610
1611 /*
1612 * Start with slot power disabled, it will be enabled when a card
1613 * is detected.
1614 */
1615 if (host->pdata->setpower)
1616 host->pdata->setpower(id, 0);
1617
fc3d7720
JC		 1618 if (host->pdata->caps)
1619 mmc->caps = host->pdata->caps;
1620 else
1621 mmc->caps = 0;
1622
f95f3850
WN		 1623 if (host->pdata->get_bus_wd)
1624 if (host->pdata->get_bus_wd(slot->id) >= 4)
1625 mmc->caps |= MMC_CAP_4_BIT_DATA;
1626
1627 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1628 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1629
1630#ifdef CONFIG_MMC_DW_IDMAC
1631 mmc->max_segs = host->ring_size;
1632 mmc->max_blk_size = 65536;
1633 mmc->max_blk_count = host->ring_size;
1634 mmc->max_seg_size = 0x1000;
1635 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1636#else
1637 if (host->pdata->blk_settings) {
1638 mmc->max_segs = host->pdata->blk_settings->max_segs;
1639 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1640 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1641 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1642 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1643 } else {
1644 /* Useful defaults if platform data is unset. */
1645 mmc->max_segs = 64;
1646 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1647 mmc->max_blk_count = 512;
1648 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1649 mmc->max_seg_size = mmc->max_req_size;
1650 }
1651#endif /* CONFIG_MMC_DW_IDMAC */
1652
c07946a3
JC		 1653 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1654 if (IS_ERR(host->vmmc)) {
1655 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1656 host->vmmc = NULL;
1657 } else
1658 regulator_enable(host->vmmc);
1659
f95f3850
WN		 1660 if (dw_mci_get_cd(mmc))
1661 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1662 else
1663 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1664
1665 host->slot[id] = slot;
1666 mmc_add_host(mmc);
1667
1668#if defined(CONFIG_DEBUG_FS)
1669 dw_mci_init_debugfs(slot);
1670#endif
1671
1672 /* Card initially undetected */
1673 slot->last_detect_state = 0;
1674
dd6c4b98
WN		 1675 /*
1676 * Card may have been plugged in prior to boot so we
1677 * need to run the detect tasklet
1678 */
1791b13e 1679 queue_work(dw_mci_card_workqueue, &host->card_work);
dd6c4b98 1680
f95f3850
WN		 1681 return 0;
1682}
1683
1684static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1685{
1686 /* Shutdown detect IRQ */
1687 if (slot->host->pdata->exit)
1688 slot->host->pdata->exit(id);
1689
1690 /* Debugfs stuff is cleaned up by mmc core */
1691 mmc_remove_host(slot->mmc);
1692 slot->host->slot[id] = NULL;
1693 mmc_free_host(slot->mmc);
1694}
1695
1696static void dw_mci_init_dma(struct dw_mci *host)
1697{
1698 /* Alloc memory for sg translation */
1699 host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1700 &host->sg_dma, GFP_KERNEL);
1701 if (!host->sg_cpu) {
1702 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1703 __func__);
1704 goto no_dma;
1705 }
1706
1707 /* Determine which DMA interface to use */
1708#ifdef CONFIG_MMC_DW_IDMAC
1709 host->dma_ops = &dw_mci_idmac_ops;
1710 dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1711#endif
1712
1713 if (!host->dma_ops)
1714 goto no_dma;
1715
1716 if (host->dma_ops->init) {
1717 if (host->dma_ops->init(host)) {
1718 dev_err(&host->pdev->dev, "%s: Unable to initialize "
1719 "DMA Controller.\n", __func__);
1720 goto no_dma;
1721 }
1722 } else {
1723 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1724 goto no_dma;
1725 }
1726
1727 host->use_dma = 1;
1728 return;
1729
1730no_dma:
1731 dev_info(&host->pdev->dev, "Using PIO mode.\n");
1732 host->use_dma = 0;
1733 return;
1734}
1735
1736static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1737{
1738 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1739 unsigned int ctrl;
1740
1741 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1742 SDMMC_CTRL_DMA_RESET));
1743
1744 /* wait till resets clear */
1745 do {
1746 ctrl = mci_readl(host, CTRL);
1747 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1748 SDMMC_CTRL_DMA_RESET)))
1749 return true;
1750 } while (time_before(jiffies, timeout));
1751
1752 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1753
1754 return false;
1755}
1756
1757static int dw_mci_probe(struct platform_device *pdev)
1758{
1759 struct dw_mci *host;
1760 struct resource *regs;
1761 struct dw_mci_board *pdata;
1762 int irq, ret, i, width;
1763 u32 fifo_size;
1764
1765 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1766 if (!regs)
1767 return -ENXIO;
1768
1769 irq = platform_get_irq(pdev, 0);
1770 if (irq < 0)
1771 return irq;
1772
1773 host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1774 if (!host)
1775 return -ENOMEM;
1776
1777 host->pdev = pdev;
1778 host->pdata = pdata = pdev->dev.platform_data;
1779 if (!pdata || !pdata->init) {
1780 dev_err(&pdev->dev,
1781 "Platform data must supply init function\n");
1782 ret = -ENODEV;
1783 goto err_freehost;
1784 }
1785
1786 if (!pdata->select_slot && pdata->num_slots > 1) {
1787 dev_err(&pdev->dev,
1788 "Platform data must supply select_slot function\n");
1789 ret = -ENODEV;
1790 goto err_freehost;
1791 }
1792
1793 if (!pdata->bus_hz) {
1794 dev_err(&pdev->dev,
1795 "Platform data must supply bus speed\n");
1796 ret = -ENODEV;
1797 goto err_freehost;
1798 }
1799
1800 host->bus_hz = pdata->bus_hz;
1801 host->quirks = pdata->quirks;
1802
1803 spin_lock_init(&host->lock);
1804 INIT_LIST_HEAD(&host->queue);
1805
1806 ret = -ENOMEM;
1807 host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1808 if (!host->regs)
1809 goto err_freehost;
1810
1811 host->dma_ops = pdata->dma_ops;
1812 dw_mci_init_dma(host);
1813
1814 /*
1815 * Get the host data width - this assumes that HCON has been set with
1816 * the correct values.
1817 */
1818 i = (mci_readl(host, HCON) >> 7) & 0x7;
1819 if (!i) {
1820 host->push_data = dw_mci_push_data16;
1821 host->pull_data = dw_mci_pull_data16;
1822 width = 16;
1823 host->data_shift = 1;
1824 } else if (i == 2) {
1825 host->push_data = dw_mci_push_data64;
1826 host->pull_data = dw_mci_pull_data64;
1827 width = 64;
1828 host->data_shift = 3;
1829 } else {
1830 /* Check for a reserved value, and warn if it is */
1831 WARN((i != 1),
1832 "HCON reports a reserved host data width!\n"
1833 "Defaulting to 32-bit access.\n");
1834 host->push_data = dw_mci_push_data32;
1835 host->pull_data = dw_mci_pull_data32;
1836 width = 32;
1837 host->data_shift = 2;
1838 }
1839
1840 /* Reset all blocks */
1841 if (!mci_wait_reset(&pdev->dev, host)) {
1842 ret = -ENODEV;
1843 goto err_dmaunmap;
1844 }
1845
1846 /* Clear the interrupts for the host controller */
1847 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1848 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1849
1850 /* Put in max timeout */
1851 mci_writel(host, TMOUT, 0xFFFFFFFF);
1852
1853 /*
1854 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
1855 * Tx Mark = fifo_size / 2 DMA Size = 8
1856 */
b86d8253
JH		 1857 if (!host->pdata->fifo_depth) {
1858 /*
1859 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
1860 * have been overwritten by the bootloader, just like we're
1861 * about to do, so if you know the value for your hardware, you
1862 * should put it in the platform data.
1863 */
1864 fifo_size = mci_readl(host, FIFOTH);
1865 fifo_size = 1 + ((fifo_size >> 16) & 0x7ff);
1866 } else {
1867 fifo_size = host->pdata->fifo_depth;
1868 }
1869 host->fifo_depth = fifo_size;
e61cf118
JC		 1870 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1871 ((fifo_size/2) << 0));
1872 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 1873
1874 /* disable clock to CIU */
1875 mci_writel(host, CLKENA, 0);
1876 mci_writel(host, CLKSRC, 0);
1877
1878 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1791b13e
JH		 1879 dw_mci_card_workqueue = alloc_workqueue("dw-mci-card",
1880 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
1881 if (!dw_mci_card_workqueue)
1882 goto err_dmaunmap;
1883 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
f95f3850
WN		 1884
1885 ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1886 if (ret)
1791b13e 1887 goto err_workqueue;
f95f3850
WN		 1888
1889 platform_set_drvdata(pdev, host);
1890
1891 if (host->pdata->num_slots)
1892 host->num_slots = host->pdata->num_slots;
1893 else
1894 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1895
1896 /* We need at least one slot to succeed */
1897 for (i = 0; i < host->num_slots; i++) {
1898 ret = dw_mci_init_slot(host, i);
1899 if (ret) {
1900 ret = -ENODEV;
1901 goto err_init_slot;
1902 }
1903 }
1904
1905 /*
1906 * Enable interrupts for command done, data over, data empty, card det,
1907 * receive ready and error such as transmit, receive timeout, crc error
1908 */
1909 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1910 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1911 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1912 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1913 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
1914
1915 dev_info(&pdev->dev, "DW MMC controller at irq %d, "
b86d8253
JH		 1916 "%d bit host data width, "
1917 "%u deep fifo\n",
1918 irq, width, fifo_size);
f95f3850
WN		 1919 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
1920 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
1921
1922 return 0;
1923
1924err_init_slot:
1925 /* De-init any initialized slots */
1926 while (i > 0) {
1927 if (host->slot[i])
1928 dw_mci_cleanup_slot(host->slot[i], i);
1929 i--;
1930 }
1931 free_irq(irq, host);
1932
1791b13e
JH		 1933err_workqueue:
1934 destroy_workqueue(dw_mci_card_workqueue);
1935
f95f3850
WN		 1936err_dmaunmap:
1937 if (host->use_dma && host->dma_ops->exit)
1938 host->dma_ops->exit(host);
1939 dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
1940 host->sg_cpu, host->sg_dma);
1941 iounmap(host->regs);
1942
c07946a3
JC		 1943 if (host->vmmc) {
1944 regulator_disable(host->vmmc);
1945 regulator_put(host->vmmc);
1946 }
1947
1948
f95f3850
WN		 1949err_freehost:
1950 kfree(host);
1951 return ret;
1952}
1953
1954static int __exit dw_mci_remove(struct platform_device *pdev)
1955{
1956 struct dw_mci *host = platform_get_drvdata(pdev);
1957 int i;
1958
1959 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1960 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1961
1962 platform_set_drvdata(pdev, NULL);
1963
1964 for (i = 0; i < host->num_slots; i++) {
1965 dev_dbg(&pdev->dev, "remove slot %d\n", i);
1966 if (host->slot[i])
1967 dw_mci_cleanup_slot(host->slot[i], i);
1968 }
1969
1970 /* disable clock to CIU */
1971 mci_writel(host, CLKENA, 0);
1972 mci_writel(host, CLKSRC, 0);
1973
1974 free_irq(platform_get_irq(pdev, 0), host);
1791b13e 1975 destroy_workqueue(dw_mci_card_workqueue);
f95f3850
WN		 1976 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1977
1978 if (host->use_dma && host->dma_ops->exit)
1979 host->dma_ops->exit(host);
1980
c07946a3
JC		 1981 if (host->vmmc) {
1982 regulator_disable(host->vmmc);
1983 regulator_put(host->vmmc);
1984 }
1985
f95f3850
WN		 1986 iounmap(host->regs);
1987
1988 kfree(host);
1989 return 0;
1990}
1991
1992#ifdef CONFIG_PM
1993/*
1994 * TODO: we should probably disable the clock to the card in the suspend path.
1995 */
1996static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
1997{
1998 int i, ret;
1999 struct dw_mci *host = platform_get_drvdata(pdev);
2000
2001 for (i = 0; i < host->num_slots; i++) {
2002 struct dw_mci_slot *slot = host->slot[i];
2003 if (!slot)
2004 continue;
2005 ret = mmc_suspend_host(slot->mmc);
2006 if (ret < 0) {
2007 while (--i >= 0) {
2008 slot = host->slot[i];
2009 if (slot)
2010 mmc_resume_host(host->slot[i]->mmc);
2011 }
2012 return ret;
2013 }
2014 }
2015
c07946a3
JC		 2016 if (host->vmmc)
2017 regulator_disable(host->vmmc);
2018
f95f3850
WN		 2019 return 0;
2020}
2021
2022static int dw_mci_resume(struct platform_device *pdev)
2023{
2024 int i, ret;
2025 struct dw_mci *host = platform_get_drvdata(pdev);
2026
1d6c4e0a
JC		 2027 if (host->vmmc)
2028 regulator_enable(host->vmmc);
2029
e61cf118
JC		 2030 if (host->dma_ops->init)
2031 host->dma_ops->init(host);
2032
2033 if (!mci_wait_reset(&pdev->dev, host)) {
2034 ret = -ENODEV;
2035 return ret;
2036 }
2037
2038 /* Restore the old value at FIFOTH register */
2039 mci_writel(host, FIFOTH, host->fifoth_val);
2040
2041 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2042 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2043 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2044 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2045 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2046
f95f3850
WN		 2047 for (i = 0; i < host->num_slots; i++) {
2048 struct dw_mci_slot *slot = host->slot[i];
2049 if (!slot)
2050 continue;
2051 ret = mmc_resume_host(host->slot[i]->mmc);
2052 if (ret < 0)
2053 return ret;
2054 }
2055
2056 return 0;
2057}
2058#else
2059#define dw_mci_suspend NULL
2060#define dw_mci_resume NULL
2061#endif /* CONFIG_PM */
2062
2063static struct platform_driver dw_mci_driver = {
2064 .remove = __exit_p(dw_mci_remove),
2065 .suspend = dw_mci_suspend,
2066 .resume = dw_mci_resume,
2067 .driver = {
2068 .name = "dw_mmc",
2069 },
2070};
2071
2072static int __init dw_mci_init(void)
2073{
2074 return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
2075}
2076
2077static void __exit dw_mci_exit(void)
2078{
2079 platform_driver_unregister(&dw_mci_driver);
2080}
2081
2082module_init(dw_mci_init);
2083module_exit(dw_mci_exit);
2084
2085MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2086MODULE_AUTHOR("NXP Semiconductor VietNam");
2087MODULE_AUTHOR("Imagination Technologies Ltd");
2088MODULE_LICENSE("GPL v2");
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