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mmc: dw_mmc: fix race with request and removal
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/scatterlist.h>
26#include <linux/seq_file.h>
27#include <linux/slab.h>
28#include <linux/stat.h>
29#include <linux/delay.h>
30#include <linux/irq.h>
31#include <linux/mmc/host.h>
32#include <linux/mmc/mmc.h>
33#include <linux/mmc/dw_mmc.h>
34#include <linux/bitops.h>
c07946a3 35#include <linux/regulator/consumer.h>
f95f3850
WN		 36
37#include "dw_mmc.h"
38
39/* Common flag combinations */
40#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
41 SDMMC_INT_HTO | SDMMC_INT_SBE | \
42 SDMMC_INT_EBE)
43#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
44 SDMMC_INT_RESP_ERR)
45#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
46 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
47#define DW_MCI_SEND_STATUS 1
48#define DW_MCI_RECV_STATUS 2
49#define DW_MCI_DMA_THRESHOLD 16
50
51#ifdef CONFIG_MMC_DW_IDMAC
52struct idmac_desc {
53 u32 des0; /* Control Descriptor */
54#define IDMAC_DES0_DIC BIT(1)
55#define IDMAC_DES0_LD BIT(2)
56#define IDMAC_DES0_FD BIT(3)
57#define IDMAC_DES0_CH BIT(4)
58#define IDMAC_DES0_ER BIT(5)
59#define IDMAC_DES0_CES BIT(30)
60#define IDMAC_DES0_OWN BIT(31)
61
62 u32 des1; /* Buffer sizes */
63#define IDMAC_SET_BUFFER1_SIZE(d, s) \
64 ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff))
65
66 u32 des2; /* buffer 1 physical address */
67
68 u32 des3; /* buffer 2 physical address */
69};
70#endif /* CONFIG_MMC_DW_IDMAC */
71
72/**
73 * struct dw_mci_slot - MMC slot state
74 * @mmc: The mmc_host representing this slot.
75 * @host: The MMC controller this slot is using.
76 * @ctype: Card type for this slot.
77 * @mrq: mmc_request currently being processed or waiting to be
78 * processed, or NULL when the slot is idle.
79 * @queue_node: List node for placing this node in the @queue list of
80 * &struct dw_mci.
81 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
82 * @flags: Random state bits associated with the slot.
83 * @id: Number of this slot.
84 * @last_detect_state: Most recently observed card detect state.
85 */
86struct dw_mci_slot {
87 struct mmc_host *mmc;
88 struct dw_mci *host;
89
90 u32 ctype;
91
92 struct mmc_request *mrq;
93 struct list_head queue_node;
94
95 unsigned int clock;
96 unsigned long flags;
97#define DW_MMC_CARD_PRESENT 0
98#define DW_MMC_CARD_NEED_INIT 1
99 int id;
100 int last_detect_state;
101};
102
103#if defined(CONFIG_DEBUG_FS)
104static int dw_mci_req_show(struct seq_file *s, void *v)
105{
106 struct dw_mci_slot *slot = s->private;
107 struct mmc_request *mrq;
108 struct mmc_command *cmd;
109 struct mmc_command *stop;
110 struct mmc_data *data;
111
112 /* Make sure we get a consistent snapshot */
113 spin_lock_bh(&slot->host->lock);
114 mrq = slot->mrq;
115
116 if (mrq) {
117 cmd = mrq->cmd;
118 data = mrq->data;
119 stop = mrq->stop;
120
121 if (cmd)
122 seq_printf(s,
123 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
124 cmd->opcode, cmd->arg, cmd->flags,
125 cmd->resp[0], cmd->resp[1], cmd->resp[2],
126 cmd->resp[2], cmd->error);
127 if (data)
128 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
129 data->bytes_xfered, data->blocks,
130 data->blksz, data->flags, data->error);
131 if (stop)
132 seq_printf(s,
133 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
134 stop->opcode, stop->arg, stop->flags,
135 stop->resp[0], stop->resp[1], stop->resp[2],
136 stop->resp[2], stop->error);
137 }
138
139 spin_unlock_bh(&slot->host->lock);
140
141 return 0;
142}
143
144static int dw_mci_req_open(struct inode *inode, struct file *file)
145{
146 return single_open(file, dw_mci_req_show, inode->i_private);
147}
148
149static const struct file_operations dw_mci_req_fops = {
150 .owner = THIS_MODULE,
151 .open = dw_mci_req_open,
152 .read = seq_read,
153 .llseek = seq_lseek,
154 .release = single_release,
155};
156
157static int dw_mci_regs_show(struct seq_file *s, void *v)
158{
159 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
160 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
161 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
162 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
163 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
164 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
165
166 return 0;
167}
168
169static int dw_mci_regs_open(struct inode *inode, struct file *file)
170{
171 return single_open(file, dw_mci_regs_show, inode->i_private);
172}
173
174static const struct file_operations dw_mci_regs_fops = {
175 .owner = THIS_MODULE,
176 .open = dw_mci_regs_open,
177 .read = seq_read,
178 .llseek = seq_lseek,
179 .release = single_release,
180};
181
182static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
183{
184 struct mmc_host *mmc = slot->mmc;
185 struct dw_mci *host = slot->host;
186 struct dentry *root;
187 struct dentry *node;
188
189 root = mmc->debugfs_root;
190 if (!root)
191 return;
192
193 node = debugfs_create_file("regs", S_IRUSR, root, host,
194 &dw_mci_regs_fops);
195 if (!node)
196 goto err;
197
198 node = debugfs_create_file("req", S_IRUSR, root, slot,
199 &dw_mci_req_fops);
200 if (!node)
201 goto err;
202
203 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
204 if (!node)
205 goto err;
206
207 node = debugfs_create_x32("pending_events", S_IRUSR, root,
208 (u32 *)&host->pending_events);
209 if (!node)
210 goto err;
211
212 node = debugfs_create_x32("completed_events", S_IRUSR, root,
213 (u32 *)&host->completed_events);
214 if (!node)
215 goto err;
216
217 return;
218
219err:
220 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
221}
222#endif /* defined(CONFIG_DEBUG_FS) */
223
224static void dw_mci_set_timeout(struct dw_mci *host)
225{
226 /* timeout (maximum) */
227 mci_writel(host, TMOUT, 0xffffffff);
228}
229
230static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
231{
232 struct mmc_data *data;
233 u32 cmdr;
234 cmd->error = -EINPROGRESS;
235
236 cmdr = cmd->opcode;
237
238 if (cmdr == MMC_STOP_TRANSMISSION)
239 cmdr |= SDMMC_CMD_STOP;
240 else
241 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
242
243 if (cmd->flags & MMC_RSP_PRESENT) {
244 /* We expect a response, so set this bit */
245 cmdr |= SDMMC_CMD_RESP_EXP;
246 if (cmd->flags & MMC_RSP_136)
247 cmdr |= SDMMC_CMD_RESP_LONG;
248 }
249
250 if (cmd->flags & MMC_RSP_CRC)
251 cmdr |= SDMMC_CMD_RESP_CRC;
252
253 data = cmd->data;
254 if (data) {
255 cmdr |= SDMMC_CMD_DAT_EXP;
256 if (data->flags & MMC_DATA_STREAM)
257 cmdr |= SDMMC_CMD_STRM_MODE;
258 if (data->flags & MMC_DATA_WRITE)
259 cmdr |= SDMMC_CMD_DAT_WR;
260 }
261
262 return cmdr;
263}
264
265static void dw_mci_start_command(struct dw_mci *host,
266 struct mmc_command *cmd, u32 cmd_flags)
267{
268 host->cmd = cmd;
269 dev_vdbg(&host->pdev->dev,
270 "start command: ARGR=0x%08x CMDR=0x%08x\n",
271 cmd->arg, cmd_flags);
272
273 mci_writel(host, CMDARG, cmd->arg);
274 wmb();
275
276 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
277}
278
279static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
280{
281 dw_mci_start_command(host, data->stop, host->stop_cmdr);
282}
283
284/* DMA interface functions */
285static void dw_mci_stop_dma(struct dw_mci *host)
286{
287 if (host->use_dma) {
288 host->dma_ops->stop(host);
289 host->dma_ops->cleanup(host);
290 } else {
291 /* Data transfer was stopped by the interrupt handler */
292 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
293 }
294}
295
296#ifdef CONFIG_MMC_DW_IDMAC
297static void dw_mci_dma_cleanup(struct dw_mci *host)
298{
299 struct mmc_data *data = host->data;
300
301 if (data)
302 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
303 ((data->flags & MMC_DATA_WRITE)
304 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
305}
306
307static void dw_mci_idmac_stop_dma(struct dw_mci *host)
308{
309 u32 temp;
310
311 /* Disable and reset the IDMAC interface */
312 temp = mci_readl(host, CTRL);
313 temp &= ~SDMMC_CTRL_USE_IDMAC;
314 temp |= SDMMC_CTRL_DMA_RESET;
315 mci_writel(host, CTRL, temp);
316
317 /* Stop the IDMAC running */
318 temp = mci_readl(host, BMOD);
a5289a43 319 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
f95f3850
WN		 320 mci_writel(host, BMOD, temp);
321}
322
323static void dw_mci_idmac_complete_dma(struct dw_mci *host)
324{
325 struct mmc_data *data = host->data;
326
327 dev_vdbg(&host->pdev->dev, "DMA complete\n");
328
329 host->dma_ops->cleanup(host);
330
331 /*
332 * If the card was removed, data will be NULL. No point in trying to
333 * send the stop command or waiting for NBUSY in this case.
334 */
335 if (data) {
336 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
337 tasklet_schedule(&host->tasklet);
338 }
339}
340
341static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
342 unsigned int sg_len)
343{
344 int i;
345 struct idmac_desc *desc = host->sg_cpu;
346
347 for (i = 0; i < sg_len; i++, desc++) {
348 unsigned int length = sg_dma_len(&data->sg[i]);
349 u32 mem_addr = sg_dma_address(&data->sg[i]);
350
351 /* Set the OWN bit and disable interrupts for this descriptor */
352 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
353
354 /* Buffer length */
355 IDMAC_SET_BUFFER1_SIZE(desc, length);
356
357 /* Physical address to DMA to/from */
358 desc->des2 = mem_addr;
359 }
360
361 /* Set first descriptor */
362 desc = host->sg_cpu;
363 desc->des0 |= IDMAC_DES0_FD;
364
365 /* Set last descriptor */
366 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
367 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
368 desc->des0 |= IDMAC_DES0_LD;
369
370 wmb();
371}
372
373static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
374{
375 u32 temp;
376
377 dw_mci_translate_sglist(host, host->data, sg_len);
378
379 /* Select IDMAC interface */
380 temp = mci_readl(host, CTRL);
381 temp |= SDMMC_CTRL_USE_IDMAC;
382 mci_writel(host, CTRL, temp);
383
384 wmb();
385
386 /* Enable the IDMAC */
387 temp = mci_readl(host, BMOD);
a5289a43 388 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 389 mci_writel(host, BMOD, temp);
390
391 /* Start it running */
392 mci_writel(host, PLDMND, 1);
393}
394
395static int dw_mci_idmac_init(struct dw_mci *host)
396{
397 struct idmac_desc *p;
398 int i;
399
400 /* Number of descriptors in the ring buffer */
401 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
402
403 /* Forward link the descriptor list */
404 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
405 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
406
407 /* Set the last descriptor as the end-of-ring descriptor */
408 p->des3 = host->sg_dma;
409 p->des0 = IDMAC_DES0_ER;
410
411 /* Mask out interrupts - get Tx & Rx complete only */
412 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
413 SDMMC_IDMAC_INT_TI);
414
415 /* Set the descriptor base address */
416 mci_writel(host, DBADDR, host->sg_dma);
417 return 0;
418}
419
420static struct dw_mci_dma_ops dw_mci_idmac_ops = {
421 .init = dw_mci_idmac_init,
422 .start = dw_mci_idmac_start_dma,
423 .stop = dw_mci_idmac_stop_dma,
424 .complete = dw_mci_idmac_complete_dma,
425 .cleanup = dw_mci_dma_cleanup,
426};
427#endif /* CONFIG_MMC_DW_IDMAC */
428
429static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
430{
431 struct scatterlist *sg;
432 unsigned int i, direction, sg_len;
433 u32 temp;
434
435 /* If we don't have a channel, we can't do DMA */
436 if (!host->use_dma)
437 return -ENODEV;
438
439 /*
440 * We don't do DMA on "complex" transfers, i.e. with
441 * non-word-aligned buffers or lengths. Also, we don't bother
442 * with all the DMA setup overhead for short transfers.
443 */
444 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
445 return -EINVAL;
446 if (data->blksz & 3)
447 return -EINVAL;
448
449 for_each_sg(data->sg, sg, data->sg_len, i) {
450 if (sg->offset & 3 || sg->length & 3)
451 return -EINVAL;
452 }
453
454 if (data->flags & MMC_DATA_READ)
455 direction = DMA_FROM_DEVICE;
456 else
457 direction = DMA_TO_DEVICE;
458
459 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
460 direction);
461
462 dev_vdbg(&host->pdev->dev,
463 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
464 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
465 sg_len);
466
467 /* Enable the DMA interface */
468 temp = mci_readl(host, CTRL);
469 temp |= SDMMC_CTRL_DMA_ENABLE;
470 mci_writel(host, CTRL, temp);
471
472 /* Disable RX/TX IRQs, let DMA handle it */
473 temp = mci_readl(host, INTMASK);
474 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
475 mci_writel(host, INTMASK, temp);
476
477 host->dma_ops->start(host, sg_len);
478
479 return 0;
480}
481
482static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
483{
484 u32 temp;
485
486 data->error = -EINPROGRESS;
487
488 WARN_ON(host->data);
489 host->sg = NULL;
490 host->data = data;
491
492 if (dw_mci_submit_data_dma(host, data)) {
493 host->sg = data->sg;
494 host->pio_offset = 0;
495 if (data->flags & MMC_DATA_READ)
496 host->dir_status = DW_MCI_RECV_STATUS;
497 else
498 host->dir_status = DW_MCI_SEND_STATUS;
499
b40af3aa 500 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 501 temp = mci_readl(host, INTMASK);
502 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
503 mci_writel(host, INTMASK, temp);
504
505 temp = mci_readl(host, CTRL);
506 temp &= ~SDMMC_CTRL_DMA_ENABLE;
507 mci_writel(host, CTRL, temp);
508 }
509}
510
511static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
512{
513 struct dw_mci *host = slot->host;
514 unsigned long timeout = jiffies + msecs_to_jiffies(500);
515 unsigned int cmd_status = 0;
516
517 mci_writel(host, CMDARG, arg);
518 wmb();
519 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
520
521 while (time_before(jiffies, timeout)) {
522 cmd_status = mci_readl(host, CMD);
523 if (!(cmd_status & SDMMC_CMD_START))
524 return;
525 }
526 dev_err(&slot->mmc->class_dev,
527 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
528 cmd, arg, cmd_status);
529}
530
531static void dw_mci_setup_bus(struct dw_mci_slot *slot)
532{
533 struct dw_mci *host = slot->host;
534 u32 div;
535
536 if (slot->clock != host->current_speed) {
537 if (host->bus_hz % slot->clock)
538 /*
539 * move the + 1 after the divide to prevent
540 * over-clocking the card.
541 */
542 div = ((host->bus_hz / slot->clock) >> 1) + 1;
543 else
544 div = (host->bus_hz / slot->clock) >> 1;
545
546 dev_info(&slot->mmc->class_dev,
547 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
548 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
549 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
550
551 /* disable clock */
552 mci_writel(host, CLKENA, 0);
553 mci_writel(host, CLKSRC, 0);
554
555 /* inform CIU */
556 mci_send_cmd(slot,
557 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
558
559 /* set clock to desired speed */
560 mci_writel(host, CLKDIV, div);
561
562 /* inform CIU */
563 mci_send_cmd(slot,
564 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
565
566 /* enable clock */
aadb9f41
WN		 567 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
568 SDMMC_CLKEN_LOW_PWR);
f95f3850
WN		 569
570 /* inform CIU */
571 mci_send_cmd(slot,
572 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
573
574 host->current_speed = slot->clock;
575 }
576
577 /* Set the current slot bus width */
1d56c453 578 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 579}
580
581static void dw_mci_start_request(struct dw_mci *host,
582 struct dw_mci_slot *slot)
583{
584 struct mmc_request *mrq;
585 struct mmc_command *cmd;
586 struct mmc_data *data;
587 u32 cmdflags;
588
589 mrq = slot->mrq;
590 if (host->pdata->select_slot)
591 host->pdata->select_slot(slot->id);
592
593 /* Slot specific timing and width adjustment */
594 dw_mci_setup_bus(slot);
595
596 host->cur_slot = slot;
597 host->mrq = mrq;
598
599 host->pending_events = 0;
600 host->completed_events = 0;
601 host->data_status = 0;
602
603 data = mrq->data;
604 if (data) {
605 dw_mci_set_timeout(host);
606 mci_writel(host, BYTCNT, data->blksz*data->blocks);
607 mci_writel(host, BLKSIZ, data->blksz);
608 }
609
610 cmd = mrq->cmd;
611 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
612
613 /* this is the first command, send the initialization clock */
614 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
615 cmdflags |= SDMMC_CMD_INIT;
616
617 if (data) {
618 dw_mci_submit_data(host, data);
619 wmb();
620 }
621
622 dw_mci_start_command(host, cmd, cmdflags);
623
624 if (mrq->stop)
625 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
626}
627
7456caae 628/* must be called with host->lock held */
f95f3850
WN		 629static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
630 struct mmc_request *mrq)
631{
632 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
633 host->state);
634
f95f3850
WN		 635 slot->mrq = mrq;
636
637 if (host->state == STATE_IDLE) {
638 host->state = STATE_SENDING_CMD;
639 dw_mci_start_request(host, slot);
640 } else {
641 list_add_tail(&slot->queue_node, &host->queue);
642 }
f95f3850
WN		 643}
644
645static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
646{
647 struct dw_mci_slot *slot = mmc_priv(mmc);
648 struct dw_mci *host = slot->host;
649
650 WARN_ON(slot->mrq);
651
7456caae
JH		 652 /*
653 * The check for card presence and queueing of the request must be
654 * atomic, otherwise the card could be removed in between and the
655 * request wouldn't fail until another card was inserted.
656 */
657 spin_lock_bh(&host->lock);
658
f95f3850 659 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 660 spin_unlock_bh(&host->lock);
f95f3850
WN		 661 mrq->cmd->error = -ENOMEDIUM;
662 mmc_request_done(mmc, mrq);
663 return;
664 }
665
f95f3850 666 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 667
668 spin_unlock_bh(&host->lock);
f95f3850
WN		 669}
670
671static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
672{
673 struct dw_mci_slot *slot = mmc_priv(mmc);
41babf75 674 u32 regs;
f95f3850
WN		 675
676 /* set default 1 bit mode */
677 slot->ctype = SDMMC_CTYPE_1BIT;
678
679 switch (ios->bus_width) {
680 case MMC_BUS_WIDTH_1:
681 slot->ctype = SDMMC_CTYPE_1BIT;
682 break;
683 case MMC_BUS_WIDTH_4:
684 slot->ctype = SDMMC_CTYPE_4BIT;
685 break;
c9b2a06f
JC		 686 case MMC_BUS_WIDTH_8:
687 slot->ctype = SDMMC_CTYPE_8BIT;
688 break;
f95f3850
WN		 689 }
690
41babf75
JC		 691 /* DDR mode set */
692 if (ios->ddr) {
693 regs = mci_readl(slot->host, UHS_REG);
694 regs |= (0x1 << slot->id) << 16;
695 mci_writel(slot->host, UHS_REG, regs);
696 }
697
f95f3850
WN		 698 if (ios->clock) {
699 /*
700 * Use mirror of ios->clock to prevent race with mmc
701 * core ios update when finding the minimum.
702 */
703 slot->clock = ios->clock;
704 }
705
706 switch (ios->power_mode) {
707 case MMC_POWER_UP:
708 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
709 break;
710 default:
711 break;
712 }
713}
714
715static int dw_mci_get_ro(struct mmc_host *mmc)
716{
717 int read_only;
718 struct dw_mci_slot *slot = mmc_priv(mmc);
719 struct dw_mci_board *brd = slot->host->pdata;
720
721 /* Use platform get_ro function, else try on board write protect */
722 if (brd->get_ro)
723 read_only = brd->get_ro(slot->id);
724 else
725 read_only =
726 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
727
728 dev_dbg(&mmc->class_dev, "card is %s\n",
729 read_only ? "read-only" : "read-write");
730
731 return read_only;
732}
733
734static int dw_mci_get_cd(struct mmc_host *mmc)
735{
736 int present;
737 struct dw_mci_slot *slot = mmc_priv(mmc);
738 struct dw_mci_board *brd = slot->host->pdata;
739
740 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 741 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
742 present = 1;
743 else if (brd->get_cd)
f95f3850
WN		 744 present = !brd->get_cd(slot->id);
745 else
746 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
747 == 0 ? 1 : 0;
748
749 if (present)
750 dev_dbg(&mmc->class_dev, "card is present\n");
751 else
752 dev_dbg(&mmc->class_dev, "card is not present\n");
753
754 return present;
755}
756
757static const struct mmc_host_ops dw_mci_ops = {
758 .request = dw_mci_request,
759 .set_ios = dw_mci_set_ios,
760 .get_ro = dw_mci_get_ro,
761 .get_cd = dw_mci_get_cd,
762};
763
764static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
765 __releases(&host->lock)
766 __acquires(&host->lock)
767{
768 struct dw_mci_slot *slot;
769 struct mmc_host *prev_mmc = host->cur_slot->mmc;
770
771 WARN_ON(host->cmd || host->data);
772
773 host->cur_slot->mrq = NULL;
774 host->mrq = NULL;
775 if (!list_empty(&host->queue)) {
776 slot = list_entry(host->queue.next,
777 struct dw_mci_slot, queue_node);
778 list_del(&slot->queue_node);
779 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
780 mmc_hostname(slot->mmc));
781 host->state = STATE_SENDING_CMD;
782 dw_mci_start_request(host, slot);
783 } else {
784 dev_vdbg(&host->pdev->dev, "list empty\n");
785 host->state = STATE_IDLE;
786 }
787
788 spin_unlock(&host->lock);
789 mmc_request_done(prev_mmc, mrq);
790 spin_lock(&host->lock);
791}
792
793static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
794{
795 u32 status = host->cmd_status;
796
797 host->cmd_status = 0;
798
799 /* Read the response from the card (up to 16 bytes) */
800 if (cmd->flags & MMC_RSP_PRESENT) {
801 if (cmd->flags & MMC_RSP_136) {
802 cmd->resp[3] = mci_readl(host, RESP0);
803 cmd->resp[2] = mci_readl(host, RESP1);
804 cmd->resp[1] = mci_readl(host, RESP2);
805 cmd->resp[0] = mci_readl(host, RESP3);
806 } else {
807 cmd->resp[0] = mci_readl(host, RESP0);
808 cmd->resp[1] = 0;
809 cmd->resp[2] = 0;
810 cmd->resp[3] = 0;
811 }
812 }
813
814 if (status & SDMMC_INT_RTO)
815 cmd->error = -ETIMEDOUT;
816 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
817 cmd->error = -EILSEQ;
818 else if (status & SDMMC_INT_RESP_ERR)
819 cmd->error = -EIO;
820 else
821 cmd->error = 0;
822
823 if (cmd->error) {
824 /* newer ip versions need a delay between retries */
825 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
826 mdelay(20);
827
828 if (cmd->data) {
829 host->data = NULL;
830 dw_mci_stop_dma(host);
831 }
832 }
833}
834
835static void dw_mci_tasklet_func(unsigned long priv)
836{
837 struct dw_mci *host = (struct dw_mci *)priv;
838 struct mmc_data *data;
839 struct mmc_command *cmd;
840 enum dw_mci_state state;
841 enum dw_mci_state prev_state;
842 u32 status;
843
844 spin_lock(&host->lock);
845
846 state = host->state;
847 data = host->data;
848
849 do {
850 prev_state = state;
851
852 switch (state) {
853 case STATE_IDLE:
854 break;
855
856 case STATE_SENDING_CMD:
857 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
858 &host->pending_events))
859 break;
860
861 cmd = host->cmd;
862 host->cmd = NULL;
863 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
864 dw_mci_command_complete(host, host->mrq->cmd);
865 if (!host->mrq->data || cmd->error) {
866 dw_mci_request_end(host, host->mrq);
867 goto unlock;
868 }
869
870 prev_state = state = STATE_SENDING_DATA;
871 /* fall through */
872
873 case STATE_SENDING_DATA:
874 if (test_and_clear_bit(EVENT_DATA_ERROR,
875 &host->pending_events)) {
876 dw_mci_stop_dma(host);
877 if (data->stop)
878 send_stop_cmd(host, data);
879 state = STATE_DATA_ERROR;
880 break;
881 }
882
883 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
884 &host->pending_events))
885 break;
886
887 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
888 prev_state = state = STATE_DATA_BUSY;
889 /* fall through */
890
891 case STATE_DATA_BUSY:
892 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
893 &host->pending_events))
894 break;
895
896 host->data = NULL;
897 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
898 status = host->data_status;
899
900 if (status & DW_MCI_DATA_ERROR_FLAGS) {
901 if (status & SDMMC_INT_DTO) {
902 dev_err(&host->pdev->dev,
903 "data timeout error\n");
904 data->error = -ETIMEDOUT;
905 } else if (status & SDMMC_INT_DCRC) {
906 dev_err(&host->pdev->dev,
907 "data CRC error\n");
908 data->error = -EILSEQ;
909 } else {
910 dev_err(&host->pdev->dev,
911 "data FIFO error "
912 "(status=%08x)\n",
913 status);
914 data->error = -EIO;
915 }
916 } else {
917 data->bytes_xfered = data->blocks * data->blksz;
918 data->error = 0;
919 }
920
921 if (!data->stop) {
922 dw_mci_request_end(host, host->mrq);
923 goto unlock;
924 }
925
926 prev_state = state = STATE_SENDING_STOP;
927 if (!data->error)
928 send_stop_cmd(host, data);
929 /* fall through */
930
931 case STATE_SENDING_STOP:
932 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
933 &host->pending_events))
934 break;
935
936 host->cmd = NULL;
937 dw_mci_command_complete(host, host->mrq->stop);
938 dw_mci_request_end(host, host->mrq);
939 goto unlock;
940
941 case STATE_DATA_ERROR:
942 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
943 &host->pending_events))
944 break;
945
946 state = STATE_DATA_BUSY;
947 break;
948 }
949 } while (state != prev_state);
950
951 host->state = state;
952unlock:
953 spin_unlock(&host->lock);
954
955}
956
957static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
958{
959 u16 *pdata = (u16 *)buf;
960
961 WARN_ON(cnt % 2 != 0);
962
963 cnt = cnt >> 1;
964 while (cnt > 0) {
965 mci_writew(host, DATA, *pdata++);
966 cnt--;
967 }
968}
969
970static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
971{
972 u16 *pdata = (u16 *)buf;
973
974 WARN_ON(cnt % 2 != 0);
975
976 cnt = cnt >> 1;
977 while (cnt > 0) {
978 *pdata++ = mci_readw(host, DATA);
979 cnt--;
980 }
981}
982
983static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
984{
985 u32 *pdata = (u32 *)buf;
986
987 WARN_ON(cnt % 4 != 0);
988 WARN_ON((unsigned long)pdata & 0x3);
989
990 cnt = cnt >> 2;
991 while (cnt > 0) {
992 mci_writel(host, DATA, *pdata++);
993 cnt--;
994 }
995}
996
997static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
998{
999 u32 *pdata = (u32 *)buf;
1000
1001 WARN_ON(cnt % 4 != 0);
1002 WARN_ON((unsigned long)pdata & 0x3);
1003
1004 cnt = cnt >> 2;
1005 while (cnt > 0) {
1006 *pdata++ = mci_readl(host, DATA);
1007 cnt--;
1008 }
1009}
1010
1011static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1012{
1013 u64 *pdata = (u64 *)buf;
1014
1015 WARN_ON(cnt % 8 != 0);
1016
1017 cnt = cnt >> 3;
1018 while (cnt > 0) {
1019 mci_writeq(host, DATA, *pdata++);
1020 cnt--;
1021 }
1022}
1023
1024static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1025{
1026 u64 *pdata = (u64 *)buf;
1027
1028 WARN_ON(cnt % 8 != 0);
1029
1030 cnt = cnt >> 3;
1031 while (cnt > 0) {
1032 *pdata++ = mci_readq(host, DATA);
1033 cnt--;
1034 }
1035}
1036
1037static void dw_mci_read_data_pio(struct dw_mci *host)
1038{
1039 struct scatterlist *sg = host->sg;
1040 void *buf = sg_virt(sg);
1041 unsigned int offset = host->pio_offset;
1042 struct mmc_data *data = host->data;
1043 int shift = host->data_shift;
1044 u32 status;
ba6a902d 1045 unsigned int nbytes = 0, len;
f95f3850
WN		 1046
1047 do {
1048 len = SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift;
f95f3850
WN		 1049 if (offset + len <= sg->length) {
1050 host->pull_data(host, (void *)(buf + offset), len);
1051
1052 offset += len;
1053 nbytes += len;
1054
1055 if (offset == sg->length) {
1056 flush_dcache_page(sg_page(sg));
1057 host->sg = sg = sg_next(sg);
1058 if (!sg)
1059 goto done;
1060
1061 offset = 0;
1062 buf = sg_virt(sg);
1063 }
1064 } else {
1065 unsigned int remaining = sg->length - offset;
1066 host->pull_data(host, (void *)(buf + offset),
1067 remaining);
1068 nbytes += remaining;
1069
1070 flush_dcache_page(sg_page(sg));
1071 host->sg = sg = sg_next(sg);
1072 if (!sg)
1073 goto done;
1074
1075 offset = len - remaining;
1076 buf = sg_virt(sg);
1077 host->pull_data(host, buf, offset);
1078 nbytes += offset;
1079 }
1080
1081 status = mci_readl(host, MINTSTS);
1082 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1083 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1084 host->data_status = status;
1085 data->bytes_xfered += nbytes;
1086 smp_wmb();
1087
1088 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1089
1090 tasklet_schedule(&host->tasklet);
1091 return;
1092 }
f95f3850
WN		 1093 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1094 len = SDMMC_GET_FCNT(mci_readl(host, STATUS));
1095 host->pio_offset = offset;
1096 data->bytes_xfered += nbytes;
1097 return;
1098
1099done:
1100 data->bytes_xfered += nbytes;
1101 smp_wmb();
1102 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1103}
1104
1105static void dw_mci_write_data_pio(struct dw_mci *host)
1106{
1107 struct scatterlist *sg = host->sg;
1108 void *buf = sg_virt(sg);
1109 unsigned int offset = host->pio_offset;
1110 struct mmc_data *data = host->data;
1111 int shift = host->data_shift;
1112 u32 status;
1113 unsigned int nbytes = 0, len;
1114
1115 do {
1116 len = SDMMC_FIFO_SZ -
1117 (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1118 if (offset + len <= sg->length) {
1119 host->push_data(host, (void *)(buf + offset), len);
1120
1121 offset += len;
1122 nbytes += len;
1123 if (offset == sg->length) {
1124 host->sg = sg = sg_next(sg);
1125 if (!sg)
1126 goto done;
1127
1128 offset = 0;
1129 buf = sg_virt(sg);
1130 }
1131 } else {
1132 unsigned int remaining = sg->length - offset;
1133
1134 host->push_data(host, (void *)(buf + offset),
1135 remaining);
1136 nbytes += remaining;
1137
1138 host->sg = sg = sg_next(sg);
1139 if (!sg)
1140 goto done;
1141
1142 offset = len - remaining;
1143 buf = sg_virt(sg);
1144 host->push_data(host, (void *)buf, offset);
1145 nbytes += offset;
1146 }
1147
1148 status = mci_readl(host, MINTSTS);
1149 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1150 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1151 host->data_status = status;
1152 data->bytes_xfered += nbytes;
1153
1154 smp_wmb();
1155
1156 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1157
1158 tasklet_schedule(&host->tasklet);
1159 return;
1160 }
1161 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1162
1163 host->pio_offset = offset;
1164 data->bytes_xfered += nbytes;
1165
1166 return;
1167
1168done:
1169 data->bytes_xfered += nbytes;
1170 smp_wmb();
1171 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1172}
1173
1174static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1175{
1176 if (!host->cmd_status)
1177 host->cmd_status = status;
1178
1179 smp_wmb();
1180
1181 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1182 tasklet_schedule(&host->tasklet);
1183}
1184
1185static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1186{
1187 struct dw_mci *host = dev_id;
1188 u32 status, pending;
1189 unsigned int pass_count = 0;
1190
1191 do {
1192 status = mci_readl(host, RINTSTS);
1193 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1194
1195 /*
1196 * DTO fix - version 2.10a and below, and only if internal DMA
1197 * is configured.
1198 */
1199 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1200 if (!pending &&
1201 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1202 pending |= SDMMC_INT_DATA_OVER;
1203 }
1204
1205 if (!pending)
1206 break;
1207
1208 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1209 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1210 host->cmd_status = status;
1211 smp_wmb();
1212 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1213 }
1214
1215 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1216 /* if there is an error report DATA_ERROR */
1217 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1218 host->data_status = status;
1219 smp_wmb();
1220 set_bit(EVENT_DATA_ERROR, &host->pending_events);
6e83e10d
SJ		 1221 if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1222 SDMMC_INT_SBE | SDMMC_INT_EBE)))
1223 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1224 }
1225
1226 if (pending & SDMMC_INT_DATA_OVER) {
1227 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1228 if (!host->data_status)
1229 host->data_status = status;
1230 smp_wmb();
1231 if (host->dir_status == DW_MCI_RECV_STATUS) {
1232 if (host->sg != NULL)
1233 dw_mci_read_data_pio(host);
1234 }
1235 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1236 tasklet_schedule(&host->tasklet);
1237 }
1238
1239 if (pending & SDMMC_INT_RXDR) {
1240 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 1241 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
f95f3850
WN		 1242 dw_mci_read_data_pio(host);
1243 }
1244
1245 if (pending & SDMMC_INT_TXDR) {
1246 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 1247 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 1248 dw_mci_write_data_pio(host);
1249 }
1250
1251 if (pending & SDMMC_INT_CMD_DONE) {
1252 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1253 dw_mci_cmd_interrupt(host, status);
1254 }
1255
1256 if (pending & SDMMC_INT_CD) {
1257 mci_writel(host, RINTSTS, SDMMC_INT_CD);
1258 tasklet_schedule(&host->card_tasklet);
1259 }
1260
1261 } while (pass_count++ < 5);
1262
1263#ifdef CONFIG_MMC_DW_IDMAC
1264 /* Handle DMA interrupts */
1265 pending = mci_readl(host, IDSTS);
1266 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1267 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1268 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1269 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1270 host->dma_ops->complete(host);
1271 }
1272#endif
1273
1274 return IRQ_HANDLED;
1275}
1276
1277static void dw_mci_tasklet_card(unsigned long data)
1278{
1279 struct dw_mci *host = (struct dw_mci *)data;
1280 int i;
1281
1282 for (i = 0; i < host->num_slots; i++) {
1283 struct dw_mci_slot *slot = host->slot[i];
1284 struct mmc_host *mmc = slot->mmc;
1285 struct mmc_request *mrq;
1286 int present;
1287 u32 ctrl;
1288
1289 present = dw_mci_get_cd(mmc);
1290 while (present != slot->last_detect_state) {
1291 spin_lock(&host->lock);
1292
1293 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1294 present ? "inserted" : "removed");
1295
1296 /* Card change detected */
1297 slot->last_detect_state = present;
1298
1299 /* Power up slot */
1300 if (present != 0) {
1301 if (host->pdata->setpower)
1302 host->pdata->setpower(slot->id,
1303 mmc->ocr_avail);
1304
1305 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1306 }
1307
1308 /* Clean up queue if present */
1309 mrq = slot->mrq;
1310 if (mrq) {
1311 if (mrq == host->mrq) {
1312 host->data = NULL;
1313 host->cmd = NULL;
1314
1315 switch (host->state) {
1316 case STATE_IDLE:
1317 break;
1318 case STATE_SENDING_CMD:
1319 mrq->cmd->error = -ENOMEDIUM;
1320 if (!mrq->data)
1321 break;
1322 /* fall through */
1323 case STATE_SENDING_DATA:
1324 mrq->data->error = -ENOMEDIUM;
1325 dw_mci_stop_dma(host);
1326 break;
1327 case STATE_DATA_BUSY:
1328 case STATE_DATA_ERROR:
1329 if (mrq->data->error == -EINPROGRESS)
1330 mrq->data->error = -ENOMEDIUM;
1331 if (!mrq->stop)
1332 break;
1333 /* fall through */
1334 case STATE_SENDING_STOP:
1335 mrq->stop->error = -ENOMEDIUM;
1336 break;
1337 }
1338
1339 dw_mci_request_end(host, mrq);
1340 } else {
1341 list_del(&slot->queue_node);
1342 mrq->cmd->error = -ENOMEDIUM;
1343 if (mrq->data)
1344 mrq->data->error = -ENOMEDIUM;
1345 if (mrq->stop)
1346 mrq->stop->error = -ENOMEDIUM;
1347
1348 spin_unlock(&host->lock);
1349 mmc_request_done(slot->mmc, mrq);
1350 spin_lock(&host->lock);
1351 }
1352 }
1353
1354 /* Power down slot */
1355 if (present == 0) {
1356 if (host->pdata->setpower)
1357 host->pdata->setpower(slot->id, 0);
1358 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1359
1360 /*
1361 * Clear down the FIFO - doing so generates a
1362 * block interrupt, hence setting the
1363 * scatter-gather pointer to NULL.
1364 */
1365 host->sg = NULL;
1366
1367 ctrl = mci_readl(host, CTRL);
1368 ctrl |= SDMMC_CTRL_FIFO_RESET;
1369 mci_writel(host, CTRL, ctrl);
1370
1371#ifdef CONFIG_MMC_DW_IDMAC
1372 ctrl = mci_readl(host, BMOD);
1373 ctrl |= 0x01; /* Software reset of DMA */
1374 mci_writel(host, BMOD, ctrl);
1375#endif
1376
1377 }
1378
1379 spin_unlock(&host->lock);
1380 present = dw_mci_get_cd(mmc);
1381 }
1382
1383 mmc_detect_change(slot->mmc,
1384 msecs_to_jiffies(host->pdata->detect_delay_ms));
1385 }
1386}
1387
1388static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1389{
1390 struct mmc_host *mmc;
1391 struct dw_mci_slot *slot;
1392
1393 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1394 if (!mmc)
1395 return -ENOMEM;
1396
1397 slot = mmc_priv(mmc);
1398 slot->id = id;
1399 slot->mmc = mmc;
1400 slot->host = host;
1401
1402 mmc->ops = &dw_mci_ops;
1403 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1404 mmc->f_max = host->bus_hz;
1405
1406 if (host->pdata->get_ocr)
1407 mmc->ocr_avail = host->pdata->get_ocr(id);
1408 else
1409 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1410
1411 /*
1412 * Start with slot power disabled, it will be enabled when a card
1413 * is detected.
1414 */
1415 if (host->pdata->setpower)
1416 host->pdata->setpower(id, 0);
1417
fc3d7720
JC		 1418 if (host->pdata->caps)
1419 mmc->caps = host->pdata->caps;
1420 else
1421 mmc->caps = 0;
1422
f95f3850
WN		 1423 if (host->pdata->get_bus_wd)
1424 if (host->pdata->get_bus_wd(slot->id) >= 4)
1425 mmc->caps |= MMC_CAP_4_BIT_DATA;
1426
1427 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1428 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1429
1430#ifdef CONFIG_MMC_DW_IDMAC
1431 mmc->max_segs = host->ring_size;
1432 mmc->max_blk_size = 65536;
1433 mmc->max_blk_count = host->ring_size;
1434 mmc->max_seg_size = 0x1000;
1435 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1436#else
1437 if (host->pdata->blk_settings) {
1438 mmc->max_segs = host->pdata->blk_settings->max_segs;
1439 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1440 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1441 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1442 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1443 } else {
1444 /* Useful defaults if platform data is unset. */
1445 mmc->max_segs = 64;
1446 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1447 mmc->max_blk_count = 512;
1448 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1449 mmc->max_seg_size = mmc->max_req_size;
1450 }
1451#endif /* CONFIG_MMC_DW_IDMAC */
1452
c07946a3
JC		 1453 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1454 if (IS_ERR(host->vmmc)) {
1455 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1456 host->vmmc = NULL;
1457 } else
1458 regulator_enable(host->vmmc);
1459
f95f3850
WN		 1460 if (dw_mci_get_cd(mmc))
1461 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1462 else
1463 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1464
1465 host->slot[id] = slot;
1466 mmc_add_host(mmc);
1467
1468#if defined(CONFIG_DEBUG_FS)
1469 dw_mci_init_debugfs(slot);
1470#endif
1471
1472 /* Card initially undetected */
1473 slot->last_detect_state = 0;
1474
dd6c4b98
WN		 1475 /*
1476 * Card may have been plugged in prior to boot so we
1477 * need to run the detect tasklet
1478 */
1479 tasklet_schedule(&host->card_tasklet);
1480
f95f3850
WN		 1481 return 0;
1482}
1483
1484static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1485{
1486 /* Shutdown detect IRQ */
1487 if (slot->host->pdata->exit)
1488 slot->host->pdata->exit(id);
1489
1490 /* Debugfs stuff is cleaned up by mmc core */
1491 mmc_remove_host(slot->mmc);
1492 slot->host->slot[id] = NULL;
1493 mmc_free_host(slot->mmc);
1494}
1495
1496static void dw_mci_init_dma(struct dw_mci *host)
1497{
1498 /* Alloc memory for sg translation */
1499 host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1500 &host->sg_dma, GFP_KERNEL);
1501 if (!host->sg_cpu) {
1502 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1503 __func__);
1504 goto no_dma;
1505 }
1506
1507 /* Determine which DMA interface to use */
1508#ifdef CONFIG_MMC_DW_IDMAC
1509 host->dma_ops = &dw_mci_idmac_ops;
1510 dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1511#endif
1512
1513 if (!host->dma_ops)
1514 goto no_dma;
1515
1516 if (host->dma_ops->init) {
1517 if (host->dma_ops->init(host)) {
1518 dev_err(&host->pdev->dev, "%s: Unable to initialize "
1519 "DMA Controller.\n", __func__);
1520 goto no_dma;
1521 }
1522 } else {
1523 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1524 goto no_dma;
1525 }
1526
1527 host->use_dma = 1;
1528 return;
1529
1530no_dma:
1531 dev_info(&host->pdev->dev, "Using PIO mode.\n");
1532 host->use_dma = 0;
1533 return;
1534}
1535
1536static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1537{
1538 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1539 unsigned int ctrl;
1540
1541 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1542 SDMMC_CTRL_DMA_RESET));
1543
1544 /* wait till resets clear */
1545 do {
1546 ctrl = mci_readl(host, CTRL);
1547 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1548 SDMMC_CTRL_DMA_RESET)))
1549 return true;
1550 } while (time_before(jiffies, timeout));
1551
1552 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1553
1554 return false;
1555}
1556
1557static int dw_mci_probe(struct platform_device *pdev)
1558{
1559 struct dw_mci *host;
1560 struct resource *regs;
1561 struct dw_mci_board *pdata;
1562 int irq, ret, i, width;
1563 u32 fifo_size;
1564
1565 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1566 if (!regs)
1567 return -ENXIO;
1568
1569 irq = platform_get_irq(pdev, 0);
1570 if (irq < 0)
1571 return irq;
1572
1573 host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1574 if (!host)
1575 return -ENOMEM;
1576
1577 host->pdev = pdev;
1578 host->pdata = pdata = pdev->dev.platform_data;
1579 if (!pdata || !pdata->init) {
1580 dev_err(&pdev->dev,
1581 "Platform data must supply init function\n");
1582 ret = -ENODEV;
1583 goto err_freehost;
1584 }
1585
1586 if (!pdata->select_slot && pdata->num_slots > 1) {
1587 dev_err(&pdev->dev,
1588 "Platform data must supply select_slot function\n");
1589 ret = -ENODEV;
1590 goto err_freehost;
1591 }
1592
1593 if (!pdata->bus_hz) {
1594 dev_err(&pdev->dev,
1595 "Platform data must supply bus speed\n");
1596 ret = -ENODEV;
1597 goto err_freehost;
1598 }
1599
1600 host->bus_hz = pdata->bus_hz;
1601 host->quirks = pdata->quirks;
1602
1603 spin_lock_init(&host->lock);
1604 INIT_LIST_HEAD(&host->queue);
1605
1606 ret = -ENOMEM;
1607 host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1608 if (!host->regs)
1609 goto err_freehost;
1610
1611 host->dma_ops = pdata->dma_ops;
1612 dw_mci_init_dma(host);
1613
1614 /*
1615 * Get the host data width - this assumes that HCON has been set with
1616 * the correct values.
1617 */
1618 i = (mci_readl(host, HCON) >> 7) & 0x7;
1619 if (!i) {
1620 host->push_data = dw_mci_push_data16;
1621 host->pull_data = dw_mci_pull_data16;
1622 width = 16;
1623 host->data_shift = 1;
1624 } else if (i == 2) {
1625 host->push_data = dw_mci_push_data64;
1626 host->pull_data = dw_mci_pull_data64;
1627 width = 64;
1628 host->data_shift = 3;
1629 } else {
1630 /* Check for a reserved value, and warn if it is */
1631 WARN((i != 1),
1632 "HCON reports a reserved host data width!\n"
1633 "Defaulting to 32-bit access.\n");
1634 host->push_data = dw_mci_push_data32;
1635 host->pull_data = dw_mci_pull_data32;
1636 width = 32;
1637 host->data_shift = 2;
1638 }
1639
1640 /* Reset all blocks */
1641 if (!mci_wait_reset(&pdev->dev, host)) {
1642 ret = -ENODEV;
1643 goto err_dmaunmap;
1644 }
1645
1646 /* Clear the interrupts for the host controller */
1647 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1648 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1649
1650 /* Put in max timeout */
1651 mci_writel(host, TMOUT, 0xFFFFFFFF);
1652
1653 /*
1654 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
1655 * Tx Mark = fifo_size / 2 DMA Size = 8
1656 */
1657 fifo_size = mci_readl(host, FIFOTH);
1658 fifo_size = (fifo_size >> 16) & 0x7ff;
e61cf118
JC		 1659 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1660 ((fifo_size/2) << 0));
1661 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 1662
1663 /* disable clock to CIU */
1664 mci_writel(host, CLKENA, 0);
1665 mci_writel(host, CLKSRC, 0);
1666
1667 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1668 tasklet_init(&host->card_tasklet,
1669 dw_mci_tasklet_card, (unsigned long)host);
1670
1671 ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1672 if (ret)
1673 goto err_dmaunmap;
1674
1675 platform_set_drvdata(pdev, host);
1676
1677 if (host->pdata->num_slots)
1678 host->num_slots = host->pdata->num_slots;
1679 else
1680 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1681
1682 /* We need at least one slot to succeed */
1683 for (i = 0; i < host->num_slots; i++) {
1684 ret = dw_mci_init_slot(host, i);
1685 if (ret) {
1686 ret = -ENODEV;
1687 goto err_init_slot;
1688 }
1689 }
1690
1691 /*
1692 * Enable interrupts for command done, data over, data empty, card det,
1693 * receive ready and error such as transmit, receive timeout, crc error
1694 */
1695 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1696 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1697 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1698 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1699 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
1700
1701 dev_info(&pdev->dev, "DW MMC controller at irq %d, "
1702 "%d bit host data width\n", irq, width);
1703 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
1704 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
1705
1706 return 0;
1707
1708err_init_slot:
1709 /* De-init any initialized slots */
1710 while (i > 0) {
1711 if (host->slot[i])
1712 dw_mci_cleanup_slot(host->slot[i], i);
1713 i--;
1714 }
1715 free_irq(irq, host);
1716
1717err_dmaunmap:
1718 if (host->use_dma && host->dma_ops->exit)
1719 host->dma_ops->exit(host);
1720 dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
1721 host->sg_cpu, host->sg_dma);
1722 iounmap(host->regs);
1723
c07946a3
JC		 1724 if (host->vmmc) {
1725 regulator_disable(host->vmmc);
1726 regulator_put(host->vmmc);
1727 }
1728
1729
f95f3850
WN		 1730err_freehost:
1731 kfree(host);
1732 return ret;
1733}
1734
1735static int __exit dw_mci_remove(struct platform_device *pdev)
1736{
1737 struct dw_mci *host = platform_get_drvdata(pdev);
1738 int i;
1739
1740 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1741 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1742
1743 platform_set_drvdata(pdev, NULL);
1744
1745 for (i = 0; i < host->num_slots; i++) {
1746 dev_dbg(&pdev->dev, "remove slot %d\n", i);
1747 if (host->slot[i])
1748 dw_mci_cleanup_slot(host->slot[i], i);
1749 }
1750
1751 /* disable clock to CIU */
1752 mci_writel(host, CLKENA, 0);
1753 mci_writel(host, CLKSRC, 0);
1754
1755 free_irq(platform_get_irq(pdev, 0), host);
1756 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1757
1758 if (host->use_dma && host->dma_ops->exit)
1759 host->dma_ops->exit(host);
1760
c07946a3
JC		 1761 if (host->vmmc) {
1762 regulator_disable(host->vmmc);
1763 regulator_put(host->vmmc);
1764 }
1765
f95f3850
WN		 1766 iounmap(host->regs);
1767
1768 kfree(host);
1769 return 0;
1770}
1771
1772#ifdef CONFIG_PM
1773/*
1774 * TODO: we should probably disable the clock to the card in the suspend path.
1775 */
1776static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
1777{
1778 int i, ret;
1779 struct dw_mci *host = platform_get_drvdata(pdev);
1780
1781 for (i = 0; i < host->num_slots; i++) {
1782 struct dw_mci_slot *slot = host->slot[i];
1783 if (!slot)
1784 continue;
1785 ret = mmc_suspend_host(slot->mmc);
1786 if (ret < 0) {
1787 while (--i >= 0) {
1788 slot = host->slot[i];
1789 if (slot)
1790 mmc_resume_host(host->slot[i]->mmc);
1791 }
1792 return ret;
1793 }
1794 }
1795
c07946a3
JC		 1796 if (host->vmmc)
1797 regulator_disable(host->vmmc);
1798
f95f3850
WN		 1799 return 0;
1800}
1801
1802static int dw_mci_resume(struct platform_device *pdev)
1803{
1804 int i, ret;
1805 struct dw_mci *host = platform_get_drvdata(pdev);
1806
1d6c4e0a
JC		 1807 if (host->vmmc)
1808 regulator_enable(host->vmmc);
1809
e61cf118
JC		 1810 if (host->dma_ops->init)
1811 host->dma_ops->init(host);
1812
1813 if (!mci_wait_reset(&pdev->dev, host)) {
1814 ret = -ENODEV;
1815 return ret;
1816 }
1817
1818 /* Restore the old value at FIFOTH register */
1819 mci_writel(host, FIFOTH, host->fifoth_val);
1820
1821 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1822 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1823 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1824 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1825 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
1826
f95f3850
WN		 1827 for (i = 0; i < host->num_slots; i++) {
1828 struct dw_mci_slot *slot = host->slot[i];
1829 if (!slot)
1830 continue;
1831 ret = mmc_resume_host(host->slot[i]->mmc);
1832 if (ret < 0)
1833 return ret;
1834 }
1835
1836 return 0;
1837}
1838#else
1839#define dw_mci_suspend NULL
1840#define dw_mci_resume NULL
1841#endif /* CONFIG_PM */
1842
1843static struct platform_driver dw_mci_driver = {
1844 .remove = __exit_p(dw_mci_remove),
1845 .suspend = dw_mci_suspend,
1846 .resume = dw_mci_resume,
1847 .driver = {
1848 .name = "dw_mmc",
1849 },
1850};
1851
1852static int __init dw_mci_init(void)
1853{
1854 return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
1855}
1856
1857static void __exit dw_mci_exit(void)
1858{
1859 platform_driver_unregister(&dw_mci_driver);
1860}
1861
1862module_init(dw_mci_init);
1863module_exit(dw_mci_exit);
1864
1865MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
1866MODULE_AUTHOR("NXP Semiconductor VietNam");
1867MODULE_AUTHOR("Imagination Technologies Ltd");
1868MODULE_LICENSE("GPL v2");
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