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Commit | Line | Data |
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f95f3850 WN |
1 | /* |
2 | * Synopsys DesignWare Multimedia Card Interface driver | |
3 | * (Based on NXP driver for lpc 31xx) | |
4 | * | |
5 | * Copyright (C) 2009 NXP Semiconductors | |
6 | * Copyright (C) 2009, 2010 Imagination Technologies Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/blkdev.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/debugfs.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
f95f3850 WN |
25 | #include <linux/seq_file.h> |
26 | #include <linux/slab.h> | |
27 | #include <linux/stat.h> | |
28 | #include <linux/delay.h> | |
29 | #include <linux/irq.h> | |
b24c8b26 | 30 | #include <linux/mmc/card.h> |
f95f3850 WN |
31 | #include <linux/mmc/host.h> |
32 | #include <linux/mmc/mmc.h> | |
01730558 | 33 | #include <linux/mmc/sd.h> |
90c2143a | 34 | #include <linux/mmc/sdio.h> |
f95f3850 WN |
35 | #include <linux/mmc/dw_mmc.h> |
36 | #include <linux/bitops.h> | |
c07946a3 | 37 | #include <linux/regulator/consumer.h> |
c91eab4b | 38 | #include <linux/of.h> |
55a6ceb2 | 39 | #include <linux/of_gpio.h> |
bf626e55 | 40 | #include <linux/mmc/slot-gpio.h> |
f95f3850 WN |
41 | |
42 | #include "dw_mmc.h" | |
43 | ||
44 | /* Common flag combinations */ | |
3f7eec62 | 45 | #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \ |
f95f3850 WN |
46 | SDMMC_INT_HTO | SDMMC_INT_SBE | \ |
47 | SDMMC_INT_EBE) | |
48 | #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ | |
49 | SDMMC_INT_RESP_ERR) | |
50 | #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ | |
51 | DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) | |
52 | #define DW_MCI_SEND_STATUS 1 | |
53 | #define DW_MCI_RECV_STATUS 2 | |
54 | #define DW_MCI_DMA_THRESHOLD 16 | |
55 | ||
1f44a2a5 SJ |
56 | #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */ |
57 | #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */ | |
58 | ||
f95f3850 | 59 | #ifdef CONFIG_MMC_DW_IDMAC |
fc79a4d6 JS |
60 | #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \ |
61 | SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \ | |
62 | SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \ | |
63 | SDMMC_IDMAC_INT_TI) | |
64 | ||
69d99fdc PT |
65 | struct idmac_desc_64addr { |
66 | u32 des0; /* Control Descriptor */ | |
67 | ||
68 | u32 des1; /* Reserved */ | |
69 | ||
70 | u32 des2; /*Buffer sizes */ | |
71 | #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \ | |
6687c42f BD |
72 | ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \ |
73 | ((cpu_to_le32(s)) & cpu_to_le32(0x1fff))) | |
69d99fdc PT |
74 | |
75 | u32 des3; /* Reserved */ | |
76 | ||
77 | u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/ | |
78 | u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/ | |
79 | ||
80 | u32 des6; /* Lower 32-bits of Next Descriptor Address */ | |
81 | u32 des7; /* Upper 32-bits of Next Descriptor Address */ | |
82 | }; | |
83 | ||
f95f3850 | 84 | struct idmac_desc { |
6687c42f | 85 | __le32 des0; /* Control Descriptor */ |
f95f3850 WN |
86 | #define IDMAC_DES0_DIC BIT(1) |
87 | #define IDMAC_DES0_LD BIT(2) | |
88 | #define IDMAC_DES0_FD BIT(3) | |
89 | #define IDMAC_DES0_CH BIT(4) | |
90 | #define IDMAC_DES0_ER BIT(5) | |
91 | #define IDMAC_DES0_CES BIT(30) | |
92 | #define IDMAC_DES0_OWN BIT(31) | |
93 | ||
6687c42f | 94 | __le32 des1; /* Buffer sizes */ |
f95f3850 | 95 | #define IDMAC_SET_BUFFER1_SIZE(d, s) \ |
9b7bbe10 | 96 | ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) |
f95f3850 | 97 | |
6687c42f | 98 | __le32 des2; /* buffer 1 physical address */ |
f95f3850 | 99 | |
6687c42f | 100 | __le32 des3; /* buffer 2 physical address */ |
f95f3850 WN |
101 | }; |
102 | #endif /* CONFIG_MMC_DW_IDMAC */ | |
103 | ||
3a33a94c | 104 | static bool dw_mci_reset(struct dw_mci *host); |
536f6b91 | 105 | static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset); |
0bdbd0e8 | 106 | static int dw_mci_card_busy(struct mmc_host *mmc); |
31bff450 | 107 | |
f95f3850 WN |
108 | #if defined(CONFIG_DEBUG_FS) |
109 | static int dw_mci_req_show(struct seq_file *s, void *v) | |
110 | { | |
111 | struct dw_mci_slot *slot = s->private; | |
112 | struct mmc_request *mrq; | |
113 | struct mmc_command *cmd; | |
114 | struct mmc_command *stop; | |
115 | struct mmc_data *data; | |
116 | ||
117 | /* Make sure we get a consistent snapshot */ | |
118 | spin_lock_bh(&slot->host->lock); | |
119 | mrq = slot->mrq; | |
120 | ||
121 | if (mrq) { | |
122 | cmd = mrq->cmd; | |
123 | data = mrq->data; | |
124 | stop = mrq->stop; | |
125 | ||
126 | if (cmd) | |
127 | seq_printf(s, | |
128 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
129 | cmd->opcode, cmd->arg, cmd->flags, | |
130 | cmd->resp[0], cmd->resp[1], cmd->resp[2], | |
131 | cmd->resp[2], cmd->error); | |
132 | if (data) | |
133 | seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", | |
134 | data->bytes_xfered, data->blocks, | |
135 | data->blksz, data->flags, data->error); | |
136 | if (stop) | |
137 | seq_printf(s, | |
138 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
139 | stop->opcode, stop->arg, stop->flags, | |
140 | stop->resp[0], stop->resp[1], stop->resp[2], | |
141 | stop->resp[2], stop->error); | |
142 | } | |
143 | ||
144 | spin_unlock_bh(&slot->host->lock); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | static int dw_mci_req_open(struct inode *inode, struct file *file) | |
150 | { | |
151 | return single_open(file, dw_mci_req_show, inode->i_private); | |
152 | } | |
153 | ||
154 | static const struct file_operations dw_mci_req_fops = { | |
155 | .owner = THIS_MODULE, | |
156 | .open = dw_mci_req_open, | |
157 | .read = seq_read, | |
158 | .llseek = seq_lseek, | |
159 | .release = single_release, | |
160 | }; | |
161 | ||
162 | static int dw_mci_regs_show(struct seq_file *s, void *v) | |
163 | { | |
164 | seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); | |
165 | seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); | |
166 | seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); | |
167 | seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); | |
168 | seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); | |
169 | seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
174 | static int dw_mci_regs_open(struct inode *inode, struct file *file) | |
175 | { | |
176 | return single_open(file, dw_mci_regs_show, inode->i_private); | |
177 | } | |
178 | ||
179 | static const struct file_operations dw_mci_regs_fops = { | |
180 | .owner = THIS_MODULE, | |
181 | .open = dw_mci_regs_open, | |
182 | .read = seq_read, | |
183 | .llseek = seq_lseek, | |
184 | .release = single_release, | |
185 | }; | |
186 | ||
187 | static void dw_mci_init_debugfs(struct dw_mci_slot *slot) | |
188 | { | |
189 | struct mmc_host *mmc = slot->mmc; | |
190 | struct dw_mci *host = slot->host; | |
191 | struct dentry *root; | |
192 | struct dentry *node; | |
193 | ||
194 | root = mmc->debugfs_root; | |
195 | if (!root) | |
196 | return; | |
197 | ||
198 | node = debugfs_create_file("regs", S_IRUSR, root, host, | |
199 | &dw_mci_regs_fops); | |
200 | if (!node) | |
201 | goto err; | |
202 | ||
203 | node = debugfs_create_file("req", S_IRUSR, root, slot, | |
204 | &dw_mci_req_fops); | |
205 | if (!node) | |
206 | goto err; | |
207 | ||
208 | node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); | |
209 | if (!node) | |
210 | goto err; | |
211 | ||
212 | node = debugfs_create_x32("pending_events", S_IRUSR, root, | |
213 | (u32 *)&host->pending_events); | |
214 | if (!node) | |
215 | goto err; | |
216 | ||
217 | node = debugfs_create_x32("completed_events", S_IRUSR, root, | |
218 | (u32 *)&host->completed_events); | |
219 | if (!node) | |
220 | goto err; | |
221 | ||
222 | return; | |
223 | ||
224 | err: | |
225 | dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); | |
226 | } | |
227 | #endif /* defined(CONFIG_DEBUG_FS) */ | |
228 | ||
01730558 DA |
229 | static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg); |
230 | ||
f95f3850 WN |
231 | static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) |
232 | { | |
233 | struct mmc_data *data; | |
800d78bf | 234 | struct dw_mci_slot *slot = mmc_priv(mmc); |
01730558 | 235 | struct dw_mci *host = slot->host; |
e95baf13 | 236 | const struct dw_mci_drv_data *drv_data = slot->host->drv_data; |
f95f3850 WN |
237 | u32 cmdr; |
238 | cmd->error = -EINPROGRESS; | |
239 | ||
240 | cmdr = cmd->opcode; | |
241 | ||
90c2143a SJ |
242 | if (cmd->opcode == MMC_STOP_TRANSMISSION || |
243 | cmd->opcode == MMC_GO_IDLE_STATE || | |
244 | cmd->opcode == MMC_GO_INACTIVE_STATE || | |
245 | (cmd->opcode == SD_IO_RW_DIRECT && | |
246 | ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) | |
f95f3850 | 247 | cmdr |= SDMMC_CMD_STOP; |
4a1b27ad JC |
248 | else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) |
249 | cmdr |= SDMMC_CMD_PRV_DAT_WAIT; | |
f95f3850 | 250 | |
01730558 DA |
251 | if (cmd->opcode == SD_SWITCH_VOLTAGE) { |
252 | u32 clk_en_a; | |
253 | ||
254 | /* Special bit makes CMD11 not die */ | |
255 | cmdr |= SDMMC_CMD_VOLT_SWITCH; | |
256 | ||
257 | /* Change state to continue to handle CMD11 weirdness */ | |
258 | WARN_ON(slot->host->state != STATE_SENDING_CMD); | |
259 | slot->host->state = STATE_SENDING_CMD11; | |
260 | ||
261 | /* | |
262 | * We need to disable low power mode (automatic clock stop) | |
263 | * while doing voltage switch so we don't confuse the card, | |
264 | * since stopping the clock is a specific part of the UHS | |
265 | * voltage change dance. | |
266 | * | |
267 | * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be | |
268 | * unconditionally turned back on in dw_mci_setup_bus() if it's | |
269 | * ever called with a non-zero clock. That shouldn't happen | |
270 | * until the voltage change is all done. | |
271 | */ | |
272 | clk_en_a = mci_readl(host, CLKENA); | |
273 | clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); | |
274 | mci_writel(host, CLKENA, clk_en_a); | |
275 | mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | | |
276 | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
277 | } | |
278 | ||
f95f3850 WN |
279 | if (cmd->flags & MMC_RSP_PRESENT) { |
280 | /* We expect a response, so set this bit */ | |
281 | cmdr |= SDMMC_CMD_RESP_EXP; | |
282 | if (cmd->flags & MMC_RSP_136) | |
283 | cmdr |= SDMMC_CMD_RESP_LONG; | |
284 | } | |
285 | ||
286 | if (cmd->flags & MMC_RSP_CRC) | |
287 | cmdr |= SDMMC_CMD_RESP_CRC; | |
288 | ||
289 | data = cmd->data; | |
290 | if (data) { | |
291 | cmdr |= SDMMC_CMD_DAT_EXP; | |
292 | if (data->flags & MMC_DATA_STREAM) | |
293 | cmdr |= SDMMC_CMD_STRM_MODE; | |
294 | if (data->flags & MMC_DATA_WRITE) | |
295 | cmdr |= SDMMC_CMD_DAT_WR; | |
296 | } | |
297 | ||
cb27a843 JH |
298 | if (drv_data && drv_data->prepare_command) |
299 | drv_data->prepare_command(slot->host, &cmdr); | |
800d78bf | 300 | |
f95f3850 WN |
301 | return cmdr; |
302 | } | |
303 | ||
90c2143a SJ |
304 | static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd) |
305 | { | |
306 | struct mmc_command *stop; | |
307 | u32 cmdr; | |
308 | ||
309 | if (!cmd->data) | |
310 | return 0; | |
311 | ||
312 | stop = &host->stop_abort; | |
313 | cmdr = cmd->opcode; | |
314 | memset(stop, 0, sizeof(struct mmc_command)); | |
315 | ||
316 | if (cmdr == MMC_READ_SINGLE_BLOCK || | |
317 | cmdr == MMC_READ_MULTIPLE_BLOCK || | |
318 | cmdr == MMC_WRITE_BLOCK || | |
6c2c6506 UH |
319 | cmdr == MMC_WRITE_MULTIPLE_BLOCK || |
320 | cmdr == MMC_SEND_TUNING_BLOCK || | |
321 | cmdr == MMC_SEND_TUNING_BLOCK_HS200) { | |
90c2143a SJ |
322 | stop->opcode = MMC_STOP_TRANSMISSION; |
323 | stop->arg = 0; | |
324 | stop->flags = MMC_RSP_R1B | MMC_CMD_AC; | |
325 | } else if (cmdr == SD_IO_RW_EXTENDED) { | |
326 | stop->opcode = SD_IO_RW_DIRECT; | |
327 | stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | | |
328 | ((cmd->arg >> 28) & 0x7); | |
329 | stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; | |
330 | } else { | |
331 | return 0; | |
332 | } | |
333 | ||
334 | cmdr = stop->opcode | SDMMC_CMD_STOP | | |
335 | SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP; | |
336 | ||
337 | return cmdr; | |
338 | } | |
339 | ||
0bdbd0e8 DA |
340 | static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags) |
341 | { | |
342 | unsigned long timeout = jiffies + msecs_to_jiffies(500); | |
343 | ||
344 | /* | |
345 | * Databook says that before issuing a new data transfer command | |
346 | * we need to check to see if the card is busy. Data transfer commands | |
347 | * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that. | |
348 | * | |
349 | * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is | |
350 | * expected. | |
351 | */ | |
352 | if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) && | |
353 | !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) { | |
354 | while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) { | |
355 | if (time_after(jiffies, timeout)) { | |
356 | /* Command will fail; we'll pass error then */ | |
357 | dev_err(host->dev, "Busy; trying anyway\n"); | |
358 | break; | |
359 | } | |
360 | udelay(10); | |
361 | } | |
362 | } | |
363 | } | |
364 | ||
f95f3850 WN |
365 | static void dw_mci_start_command(struct dw_mci *host, |
366 | struct mmc_command *cmd, u32 cmd_flags) | |
367 | { | |
368 | host->cmd = cmd; | |
4a90920c | 369 | dev_vdbg(host->dev, |
f95f3850 WN |
370 | "start command: ARGR=0x%08x CMDR=0x%08x\n", |
371 | cmd->arg, cmd_flags); | |
372 | ||
373 | mci_writel(host, CMDARG, cmd->arg); | |
374 | wmb(); | |
0bdbd0e8 | 375 | dw_mci_wait_while_busy(host, cmd_flags); |
f95f3850 WN |
376 | |
377 | mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); | |
378 | } | |
379 | ||
90c2143a | 380 | static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data) |
f95f3850 | 381 | { |
90c2143a SJ |
382 | struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort; |
383 | dw_mci_start_command(host, stop, host->stop_cmdr); | |
f95f3850 WN |
384 | } |
385 | ||
386 | /* DMA interface functions */ | |
387 | static void dw_mci_stop_dma(struct dw_mci *host) | |
388 | { | |
03e8cb53 | 389 | if (host->using_dma) { |
f95f3850 WN |
390 | host->dma_ops->stop(host); |
391 | host->dma_ops->cleanup(host); | |
f95f3850 | 392 | } |
aa50f259 SJ |
393 | |
394 | /* Data transfer was stopped by the interrupt handler */ | |
395 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
f95f3850 WN |
396 | } |
397 | ||
9aa51408 SJ |
398 | static int dw_mci_get_dma_dir(struct mmc_data *data) |
399 | { | |
400 | if (data->flags & MMC_DATA_WRITE) | |
401 | return DMA_TO_DEVICE; | |
402 | else | |
403 | return DMA_FROM_DEVICE; | |
404 | } | |
405 | ||
9beee912 | 406 | #ifdef CONFIG_MMC_DW_IDMAC |
f95f3850 WN |
407 | static void dw_mci_dma_cleanup(struct dw_mci *host) |
408 | { | |
409 | struct mmc_data *data = host->data; | |
410 | ||
411 | if (data) | |
9aa51408 | 412 | if (!data->host_cookie) |
4a90920c | 413 | dma_unmap_sg(host->dev, |
9aa51408 SJ |
414 | data->sg, |
415 | data->sg_len, | |
416 | dw_mci_get_dma_dir(data)); | |
f95f3850 WN |
417 | } |
418 | ||
5ce9d961 SJ |
419 | static void dw_mci_idmac_reset(struct dw_mci *host) |
420 | { | |
421 | u32 bmod = mci_readl(host, BMOD); | |
422 | /* Software reset of DMA */ | |
423 | bmod |= SDMMC_IDMAC_SWRESET; | |
424 | mci_writel(host, BMOD, bmod); | |
425 | } | |
426 | ||
f95f3850 WN |
427 | static void dw_mci_idmac_stop_dma(struct dw_mci *host) |
428 | { | |
429 | u32 temp; | |
430 | ||
431 | /* Disable and reset the IDMAC interface */ | |
432 | temp = mci_readl(host, CTRL); | |
433 | temp &= ~SDMMC_CTRL_USE_IDMAC; | |
434 | temp |= SDMMC_CTRL_DMA_RESET; | |
435 | mci_writel(host, CTRL, temp); | |
436 | ||
437 | /* Stop the IDMAC running */ | |
438 | temp = mci_readl(host, BMOD); | |
a5289a43 | 439 | temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); |
5ce9d961 | 440 | temp |= SDMMC_IDMAC_SWRESET; |
f95f3850 WN |
441 | mci_writel(host, BMOD, temp); |
442 | } | |
443 | ||
444 | static void dw_mci_idmac_complete_dma(struct dw_mci *host) | |
445 | { | |
446 | struct mmc_data *data = host->data; | |
447 | ||
4a90920c | 448 | dev_vdbg(host->dev, "DMA complete\n"); |
f95f3850 WN |
449 | |
450 | host->dma_ops->cleanup(host); | |
451 | ||
452 | /* | |
453 | * If the card was removed, data will be NULL. No point in trying to | |
454 | * send the stop command or waiting for NBUSY in this case. | |
455 | */ | |
456 | if (data) { | |
457 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
458 | tasklet_schedule(&host->tasklet); | |
459 | } | |
460 | } | |
461 | ||
462 | static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, | |
463 | unsigned int sg_len) | |
464 | { | |
465 | int i; | |
69d99fdc PT |
466 | if (host->dma_64bit_address == 1) { |
467 | struct idmac_desc_64addr *desc = host->sg_cpu; | |
468 | ||
469 | for (i = 0; i < sg_len; i++, desc++) { | |
470 | unsigned int length = sg_dma_len(&data->sg[i]); | |
471 | u64 mem_addr = sg_dma_address(&data->sg[i]); | |
f95f3850 | 472 | |
69d99fdc PT |
473 | /* |
474 | * Set the OWN bit and disable interrupts for this | |
475 | * descriptor | |
476 | */ | |
477 | desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | | |
478 | IDMAC_DES0_CH; | |
479 | /* Buffer length */ | |
480 | IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length); | |
481 | ||
482 | /* Physical address to DMA to/from */ | |
483 | desc->des4 = mem_addr & 0xffffffff; | |
484 | desc->des5 = mem_addr >> 32; | |
485 | } | |
f95f3850 | 486 | |
69d99fdc PT |
487 | /* Set first descriptor */ |
488 | desc = host->sg_cpu; | |
489 | desc->des0 |= IDMAC_DES0_FD; | |
f95f3850 | 490 | |
69d99fdc PT |
491 | /* Set last descriptor */ |
492 | desc = host->sg_cpu + (i - 1) * | |
493 | sizeof(struct idmac_desc_64addr); | |
494 | desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); | |
495 | desc->des0 |= IDMAC_DES0_LD; | |
f95f3850 | 496 | |
69d99fdc PT |
497 | } else { |
498 | struct idmac_desc *desc = host->sg_cpu; | |
499 | ||
500 | for (i = 0; i < sg_len; i++, desc++) { | |
501 | unsigned int length = sg_dma_len(&data->sg[i]); | |
502 | u32 mem_addr = sg_dma_address(&data->sg[i]); | |
503 | ||
504 | /* | |
505 | * Set the OWN bit and disable interrupts for this | |
506 | * descriptor | |
507 | */ | |
6687c42f BD |
508 | desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | |
509 | IDMAC_DES0_DIC | IDMAC_DES0_CH); | |
69d99fdc PT |
510 | /* Buffer length */ |
511 | IDMAC_SET_BUFFER1_SIZE(desc, length); | |
f95f3850 | 512 | |
69d99fdc | 513 | /* Physical address to DMA to/from */ |
6687c42f | 514 | desc->des2 = cpu_to_le32(mem_addr); |
69d99fdc PT |
515 | } |
516 | ||
517 | /* Set first descriptor */ | |
518 | desc = host->sg_cpu; | |
6687c42f | 519 | desc->des0 |= cpu_to_le32(IDMAC_DES0_FD); |
f95f3850 | 520 | |
69d99fdc PT |
521 | /* Set last descriptor */ |
522 | desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); | |
6687c42f BD |
523 | desc->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | IDMAC_DES0_DIC)); |
524 | desc->des0 |= cpu_to_le32(IDMAC_DES0_LD); | |
69d99fdc | 525 | } |
f95f3850 WN |
526 | |
527 | wmb(); | |
528 | } | |
529 | ||
530 | static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) | |
531 | { | |
532 | u32 temp; | |
533 | ||
534 | dw_mci_translate_sglist(host, host->data, sg_len); | |
535 | ||
536f6b91 SR |
536 | /* Make sure to reset DMA in case we did PIO before this */ |
537 | dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET); | |
538 | dw_mci_idmac_reset(host); | |
539 | ||
f95f3850 WN |
540 | /* Select IDMAC interface */ |
541 | temp = mci_readl(host, CTRL); | |
542 | temp |= SDMMC_CTRL_USE_IDMAC; | |
543 | mci_writel(host, CTRL, temp); | |
544 | ||
545 | wmb(); | |
546 | ||
547 | /* Enable the IDMAC */ | |
548 | temp = mci_readl(host, BMOD); | |
a5289a43 | 549 | temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; |
f95f3850 WN |
550 | mci_writel(host, BMOD, temp); |
551 | ||
552 | /* Start it running */ | |
553 | mci_writel(host, PLDMND, 1); | |
554 | } | |
555 | ||
556 | static int dw_mci_idmac_init(struct dw_mci *host) | |
557 | { | |
897b69e7 | 558 | int i; |
f95f3850 | 559 | |
69d99fdc PT |
560 | if (host->dma_64bit_address == 1) { |
561 | struct idmac_desc_64addr *p; | |
562 | /* Number of descriptors in the ring buffer */ | |
563 | host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr); | |
564 | ||
565 | /* Forward link the descriptor list */ | |
566 | for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; | |
567 | i++, p++) { | |
568 | p->des6 = (host->sg_dma + | |
569 | (sizeof(struct idmac_desc_64addr) * | |
570 | (i + 1))) & 0xffffffff; | |
571 | ||
572 | p->des7 = (u64)(host->sg_dma + | |
573 | (sizeof(struct idmac_desc_64addr) * | |
574 | (i + 1))) >> 32; | |
575 | /* Initialize reserved and buffer size fields to "0" */ | |
576 | p->des1 = 0; | |
577 | p->des2 = 0; | |
578 | p->des3 = 0; | |
579 | } | |
f95f3850 | 580 | |
69d99fdc PT |
581 | /* Set the last descriptor as the end-of-ring descriptor */ |
582 | p->des6 = host->sg_dma & 0xffffffff; | |
583 | p->des7 = (u64)host->sg_dma >> 32; | |
584 | p->des0 = IDMAC_DES0_ER; | |
f95f3850 | 585 | |
69d99fdc PT |
586 | } else { |
587 | struct idmac_desc *p; | |
588 | /* Number of descriptors in the ring buffer */ | |
589 | host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); | |
590 | ||
591 | /* Forward link the descriptor list */ | |
592 | for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) | |
6687c42f BD |
593 | p->des3 = cpu_to_le32(host->sg_dma + |
594 | (sizeof(struct idmac_desc) * (i + 1))); | |
69d99fdc PT |
595 | |
596 | /* Set the last descriptor as the end-of-ring descriptor */ | |
6687c42f BD |
597 | p->des3 = cpu_to_le32(host->sg_dma); |
598 | p->des0 = cpu_to_le32(IDMAC_DES0_ER); | |
69d99fdc | 599 | } |
f95f3850 | 600 | |
5ce9d961 | 601 | dw_mci_idmac_reset(host); |
141a712a | 602 | |
69d99fdc PT |
603 | if (host->dma_64bit_address == 1) { |
604 | /* Mask out interrupts - get Tx & Rx complete only */ | |
605 | mci_writel(host, IDSTS64, IDMAC_INT_CLR); | |
606 | mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI | | |
607 | SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); | |
608 | ||
609 | /* Set the descriptor base address */ | |
610 | mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); | |
611 | mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); | |
612 | ||
613 | } else { | |
614 | /* Mask out interrupts - get Tx & Rx complete only */ | |
615 | mci_writel(host, IDSTS, IDMAC_INT_CLR); | |
616 | mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | | |
617 | SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI); | |
618 | ||
619 | /* Set the descriptor base address */ | |
620 | mci_writel(host, DBADDR, host->sg_dma); | |
621 | } | |
f95f3850 | 622 | |
f95f3850 WN |
623 | return 0; |
624 | } | |
625 | ||
8e2b36ea | 626 | static const struct dw_mci_dma_ops dw_mci_idmac_ops = { |
885c3e80 SJ |
627 | .init = dw_mci_idmac_init, |
628 | .start = dw_mci_idmac_start_dma, | |
629 | .stop = dw_mci_idmac_stop_dma, | |
630 | .complete = dw_mci_idmac_complete_dma, | |
631 | .cleanup = dw_mci_dma_cleanup, | |
632 | }; | |
633 | #endif /* CONFIG_MMC_DW_IDMAC */ | |
634 | ||
9aa51408 SJ |
635 | static int dw_mci_pre_dma_transfer(struct dw_mci *host, |
636 | struct mmc_data *data, | |
637 | bool next) | |
f95f3850 WN |
638 | { |
639 | struct scatterlist *sg; | |
9aa51408 | 640 | unsigned int i, sg_len; |
03e8cb53 | 641 | |
9aa51408 SJ |
642 | if (!next && data->host_cookie) |
643 | return data->host_cookie; | |
f95f3850 WN |
644 | |
645 | /* | |
646 | * We don't do DMA on "complex" transfers, i.e. with | |
647 | * non-word-aligned buffers or lengths. Also, we don't bother | |
648 | * with all the DMA setup overhead for short transfers. | |
649 | */ | |
650 | if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) | |
651 | return -EINVAL; | |
9aa51408 | 652 | |
f95f3850 WN |
653 | if (data->blksz & 3) |
654 | return -EINVAL; | |
655 | ||
656 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
657 | if (sg->offset & 3 || sg->length & 3) | |
658 | return -EINVAL; | |
659 | } | |
660 | ||
4a90920c | 661 | sg_len = dma_map_sg(host->dev, |
9aa51408 SJ |
662 | data->sg, |
663 | data->sg_len, | |
664 | dw_mci_get_dma_dir(data)); | |
665 | if (sg_len == 0) | |
666 | return -EINVAL; | |
03e8cb53 | 667 | |
9aa51408 SJ |
668 | if (next) |
669 | data->host_cookie = sg_len; | |
f95f3850 | 670 | |
9aa51408 SJ |
671 | return sg_len; |
672 | } | |
673 | ||
9aa51408 SJ |
674 | static void dw_mci_pre_req(struct mmc_host *mmc, |
675 | struct mmc_request *mrq, | |
676 | bool is_first_req) | |
677 | { | |
678 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
679 | struct mmc_data *data = mrq->data; | |
680 | ||
681 | if (!slot->host->use_dma || !data) | |
682 | return; | |
683 | ||
684 | if (data->host_cookie) { | |
685 | data->host_cookie = 0; | |
686 | return; | |
687 | } | |
688 | ||
689 | if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0) | |
690 | data->host_cookie = 0; | |
691 | } | |
692 | ||
693 | static void dw_mci_post_req(struct mmc_host *mmc, | |
694 | struct mmc_request *mrq, | |
695 | int err) | |
696 | { | |
697 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
698 | struct mmc_data *data = mrq->data; | |
699 | ||
700 | if (!slot->host->use_dma || !data) | |
701 | return; | |
702 | ||
703 | if (data->host_cookie) | |
4a90920c | 704 | dma_unmap_sg(slot->host->dev, |
9aa51408 SJ |
705 | data->sg, |
706 | data->sg_len, | |
707 | dw_mci_get_dma_dir(data)); | |
708 | data->host_cookie = 0; | |
709 | } | |
710 | ||
52426899 SJ |
711 | static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data) |
712 | { | |
713 | #ifdef CONFIG_MMC_DW_IDMAC | |
714 | unsigned int blksz = data->blksz; | |
715 | const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256}; | |
716 | u32 fifo_width = 1 << host->data_shift; | |
717 | u32 blksz_depth = blksz / fifo_width, fifoth_val; | |
718 | u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers; | |
719 | int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1; | |
720 | ||
721 | tx_wmark = (host->fifo_depth) / 2; | |
722 | tx_wmark_invers = host->fifo_depth - tx_wmark; | |
723 | ||
724 | /* | |
725 | * MSIZE is '1', | |
726 | * if blksz is not a multiple of the FIFO width | |
727 | */ | |
728 | if (blksz % fifo_width) { | |
729 | msize = 0; | |
730 | rx_wmark = 1; | |
731 | goto done; | |
732 | } | |
733 | ||
734 | do { | |
735 | if (!((blksz_depth % mszs[idx]) || | |
736 | (tx_wmark_invers % mszs[idx]))) { | |
737 | msize = idx; | |
738 | rx_wmark = mszs[idx] - 1; | |
739 | break; | |
740 | } | |
741 | } while (--idx > 0); | |
742 | /* | |
743 | * If idx is '0', it won't be tried | |
744 | * Thus, initial values are uesed | |
745 | */ | |
746 | done: | |
747 | fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark); | |
748 | mci_writel(host, FIFOTH, fifoth_val); | |
749 | #endif | |
750 | } | |
751 | ||
f1d2736c SJ |
752 | static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data) |
753 | { | |
754 | unsigned int blksz = data->blksz; | |
755 | u32 blksz_depth, fifo_depth; | |
756 | u16 thld_size; | |
757 | ||
758 | WARN_ON(!(data->flags & MMC_DATA_READ)); | |
759 | ||
66dfd101 JH |
760 | /* |
761 | * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is | |
762 | * in the FIFO region, so we really shouldn't access it). | |
763 | */ | |
764 | if (host->verid < DW_MMC_240A) | |
765 | return; | |
766 | ||
f1d2736c | 767 | if (host->timing != MMC_TIMING_MMC_HS200 && |
488b8d63 | 768 | host->timing != MMC_TIMING_MMC_HS400 && |
f1d2736c SJ |
769 | host->timing != MMC_TIMING_UHS_SDR104) |
770 | goto disable; | |
771 | ||
772 | blksz_depth = blksz / (1 << host->data_shift); | |
773 | fifo_depth = host->fifo_depth; | |
774 | ||
775 | if (blksz_depth > fifo_depth) | |
776 | goto disable; | |
777 | ||
778 | /* | |
779 | * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz' | |
780 | * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz | |
781 | * Currently just choose blksz. | |
782 | */ | |
783 | thld_size = blksz; | |
784 | mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1)); | |
785 | return; | |
786 | ||
787 | disable: | |
788 | mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0)); | |
789 | } | |
790 | ||
9aa51408 SJ |
791 | static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) |
792 | { | |
f8c58c11 | 793 | unsigned long irqflags; |
9aa51408 SJ |
794 | int sg_len; |
795 | u32 temp; | |
796 | ||
797 | host->using_dma = 0; | |
798 | ||
799 | /* If we don't have a channel, we can't do DMA */ | |
800 | if (!host->use_dma) | |
801 | return -ENODEV; | |
802 | ||
803 | sg_len = dw_mci_pre_dma_transfer(host, data, 0); | |
a99aa9b9 SJ |
804 | if (sg_len < 0) { |
805 | host->dma_ops->stop(host); | |
9aa51408 | 806 | return sg_len; |
a99aa9b9 | 807 | } |
9aa51408 SJ |
808 | |
809 | host->using_dma = 1; | |
f95f3850 | 810 | |
4a90920c | 811 | dev_vdbg(host->dev, |
f95f3850 WN |
812 | "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", |
813 | (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, | |
814 | sg_len); | |
815 | ||
52426899 SJ |
816 | /* |
817 | * Decide the MSIZE and RX/TX Watermark. | |
818 | * If current block size is same with previous size, | |
819 | * no need to update fifoth. | |
820 | */ | |
821 | if (host->prev_blksz != data->blksz) | |
822 | dw_mci_adjust_fifoth(host, data); | |
823 | ||
f95f3850 WN |
824 | /* Enable the DMA interface */ |
825 | temp = mci_readl(host, CTRL); | |
826 | temp |= SDMMC_CTRL_DMA_ENABLE; | |
827 | mci_writel(host, CTRL, temp); | |
828 | ||
829 | /* Disable RX/TX IRQs, let DMA handle it */ | |
f8c58c11 | 830 | spin_lock_irqsave(&host->irq_lock, irqflags); |
f95f3850 WN |
831 | temp = mci_readl(host, INTMASK); |
832 | temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); | |
833 | mci_writel(host, INTMASK, temp); | |
f8c58c11 | 834 | spin_unlock_irqrestore(&host->irq_lock, irqflags); |
f95f3850 WN |
835 | |
836 | host->dma_ops->start(host, sg_len); | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
841 | static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) | |
842 | { | |
f8c58c11 | 843 | unsigned long irqflags; |
f95f3850 WN |
844 | u32 temp; |
845 | ||
846 | data->error = -EINPROGRESS; | |
847 | ||
848 | WARN_ON(host->data); | |
849 | host->sg = NULL; | |
850 | host->data = data; | |
851 | ||
f1d2736c | 852 | if (data->flags & MMC_DATA_READ) { |
55c5efbc | 853 | host->dir_status = DW_MCI_RECV_STATUS; |
f1d2736c SJ |
854 | dw_mci_ctrl_rd_thld(host, data); |
855 | } else { | |
55c5efbc | 856 | host->dir_status = DW_MCI_SEND_STATUS; |
f1d2736c | 857 | } |
55c5efbc | 858 | |
f95f3850 | 859 | if (dw_mci_submit_data_dma(host, data)) { |
f9c2a0dc SJ |
860 | int flags = SG_MITER_ATOMIC; |
861 | if (host->data->flags & MMC_DATA_READ) | |
862 | flags |= SG_MITER_TO_SG; | |
863 | else | |
864 | flags |= SG_MITER_FROM_SG; | |
865 | ||
866 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
f95f3850 | 867 | host->sg = data->sg; |
34b664a2 JH |
868 | host->part_buf_start = 0; |
869 | host->part_buf_count = 0; | |
f95f3850 | 870 | |
b40af3aa | 871 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); |
f8c58c11 DA |
872 | |
873 | spin_lock_irqsave(&host->irq_lock, irqflags); | |
f95f3850 WN |
874 | temp = mci_readl(host, INTMASK); |
875 | temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; | |
876 | mci_writel(host, INTMASK, temp); | |
f8c58c11 | 877 | spin_unlock_irqrestore(&host->irq_lock, irqflags); |
f95f3850 WN |
878 | |
879 | temp = mci_readl(host, CTRL); | |
880 | temp &= ~SDMMC_CTRL_DMA_ENABLE; | |
881 | mci_writel(host, CTRL, temp); | |
52426899 SJ |
882 | |
883 | /* | |
884 | * Use the initial fifoth_val for PIO mode. | |
885 | * If next issued data may be transfered by DMA mode, | |
886 | * prev_blksz should be invalidated. | |
887 | */ | |
888 | mci_writel(host, FIFOTH, host->fifoth_val); | |
889 | host->prev_blksz = 0; | |
890 | } else { | |
891 | /* | |
892 | * Keep the current block size. | |
893 | * It will be used to decide whether to update | |
894 | * fifoth register next time. | |
895 | */ | |
896 | host->prev_blksz = data->blksz; | |
f95f3850 WN |
897 | } |
898 | } | |
899 | ||
900 | static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) | |
901 | { | |
902 | struct dw_mci *host = slot->host; | |
903 | unsigned long timeout = jiffies + msecs_to_jiffies(500); | |
904 | unsigned int cmd_status = 0; | |
905 | ||
906 | mci_writel(host, CMDARG, arg); | |
907 | wmb(); | |
0bdbd0e8 | 908 | dw_mci_wait_while_busy(host, cmd); |
f95f3850 WN |
909 | mci_writel(host, CMD, SDMMC_CMD_START | cmd); |
910 | ||
911 | while (time_before(jiffies, timeout)) { | |
912 | cmd_status = mci_readl(host, CMD); | |
913 | if (!(cmd_status & SDMMC_CMD_START)) | |
914 | return; | |
915 | } | |
916 | dev_err(&slot->mmc->class_dev, | |
917 | "Timeout sending command (cmd %#x arg %#x status %#x)\n", | |
918 | cmd, arg, cmd_status); | |
919 | } | |
920 | ||
ab269128 | 921 | static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit) |
f95f3850 WN |
922 | { |
923 | struct dw_mci *host = slot->host; | |
fdf492a1 | 924 | unsigned int clock = slot->clock; |
f95f3850 | 925 | u32 div; |
9623b5b9 | 926 | u32 clk_en_a; |
01730558 DA |
927 | u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT; |
928 | ||
929 | /* We must continue to set bit 28 in CMD until the change is complete */ | |
930 | if (host->state == STATE_WAITING_CMD11_DONE) | |
931 | sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH; | |
f95f3850 | 932 | |
fdf492a1 DA |
933 | if (!clock) { |
934 | mci_writel(host, CLKENA, 0); | |
01730558 | 935 | mci_send_cmd(slot, sdmmc_cmd_bits, 0); |
fdf492a1 DA |
936 | } else if (clock != host->current_speed || force_clkinit) { |
937 | div = host->bus_hz / clock; | |
938 | if (host->bus_hz % clock && host->bus_hz > clock) | |
f95f3850 WN |
939 | /* |
940 | * move the + 1 after the divide to prevent | |
941 | * over-clocking the card. | |
942 | */ | |
e419990b SJ |
943 | div += 1; |
944 | ||
fdf492a1 | 945 | div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; |
f95f3850 | 946 | |
fdf492a1 DA |
947 | if ((clock << div) != slot->__clk_old || force_clkinit) |
948 | dev_info(&slot->mmc->class_dev, | |
949 | "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n", | |
950 | slot->id, host->bus_hz, clock, | |
951 | div ? ((host->bus_hz / div) >> 1) : | |
952 | host->bus_hz, div); | |
f95f3850 WN |
953 | |
954 | /* disable clock */ | |
955 | mci_writel(host, CLKENA, 0); | |
956 | mci_writel(host, CLKSRC, 0); | |
957 | ||
958 | /* inform CIU */ | |
01730558 | 959 | mci_send_cmd(slot, sdmmc_cmd_bits, 0); |
f95f3850 WN |
960 | |
961 | /* set clock to desired speed */ | |
962 | mci_writel(host, CLKDIV, div); | |
963 | ||
964 | /* inform CIU */ | |
01730558 | 965 | mci_send_cmd(slot, sdmmc_cmd_bits, 0); |
f95f3850 | 966 | |
9623b5b9 DA |
967 | /* enable clock; only low power if no SDIO */ |
968 | clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; | |
b24c8b26 | 969 | if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) |
9623b5b9 DA |
970 | clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; |
971 | mci_writel(host, CLKENA, clk_en_a); | |
f95f3850 WN |
972 | |
973 | /* inform CIU */ | |
01730558 | 974 | mci_send_cmd(slot, sdmmc_cmd_bits, 0); |
f95f3850 | 975 | |
fdf492a1 DA |
976 | /* keep the clock with reflecting clock dividor */ |
977 | slot->__clk_old = clock << div; | |
f95f3850 WN |
978 | } |
979 | ||
fdf492a1 DA |
980 | host->current_speed = clock; |
981 | ||
f95f3850 | 982 | /* Set the current slot bus width */ |
1d56c453 | 983 | mci_writel(host, CTYPE, (slot->ctype << slot->id)); |
f95f3850 WN |
984 | } |
985 | ||
053b3ce6 SJ |
986 | static void __dw_mci_start_request(struct dw_mci *host, |
987 | struct dw_mci_slot *slot, | |
988 | struct mmc_command *cmd) | |
f95f3850 WN |
989 | { |
990 | struct mmc_request *mrq; | |
f95f3850 WN |
991 | struct mmc_data *data; |
992 | u32 cmdflags; | |
993 | ||
994 | mrq = slot->mrq; | |
f95f3850 | 995 | |
f95f3850 WN |
996 | host->cur_slot = slot; |
997 | host->mrq = mrq; | |
998 | ||
999 | host->pending_events = 0; | |
1000 | host->completed_events = 0; | |
e352c813 | 1001 | host->cmd_status = 0; |
f95f3850 | 1002 | host->data_status = 0; |
e352c813 | 1003 | host->dir_status = 0; |
f95f3850 | 1004 | |
053b3ce6 | 1005 | data = cmd->data; |
f95f3850 | 1006 | if (data) { |
f16afa88 | 1007 | mci_writel(host, TMOUT, 0xFFFFFFFF); |
f95f3850 WN |
1008 | mci_writel(host, BYTCNT, data->blksz*data->blocks); |
1009 | mci_writel(host, BLKSIZ, data->blksz); | |
1010 | } | |
1011 | ||
f95f3850 WN |
1012 | cmdflags = dw_mci_prepare_command(slot->mmc, cmd); |
1013 | ||
1014 | /* this is the first command, send the initialization clock */ | |
1015 | if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) | |
1016 | cmdflags |= SDMMC_CMD_INIT; | |
1017 | ||
1018 | if (data) { | |
1019 | dw_mci_submit_data(host, data); | |
1020 | wmb(); | |
1021 | } | |
1022 | ||
1023 | dw_mci_start_command(host, cmd, cmdflags); | |
1024 | ||
5c935165 DA |
1025 | if (cmd->opcode == SD_SWITCH_VOLTAGE) { |
1026 | /* | |
1027 | * Databook says to fail after 2ms w/ no response; give an | |
1028 | * extra jiffy just in case we're about to roll over. | |
1029 | */ | |
1030 | mod_timer(&host->cmd11_timer, | |
1031 | jiffies + msecs_to_jiffies(2) + 1); | |
1032 | } | |
1033 | ||
f95f3850 WN |
1034 | if (mrq->stop) |
1035 | host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); | |
90c2143a SJ |
1036 | else |
1037 | host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); | |
f95f3850 WN |
1038 | } |
1039 | ||
053b3ce6 SJ |
1040 | static void dw_mci_start_request(struct dw_mci *host, |
1041 | struct dw_mci_slot *slot) | |
1042 | { | |
1043 | struct mmc_request *mrq = slot->mrq; | |
1044 | struct mmc_command *cmd; | |
1045 | ||
1046 | cmd = mrq->sbc ? mrq->sbc : mrq->cmd; | |
1047 | __dw_mci_start_request(host, slot, cmd); | |
1048 | } | |
1049 | ||
7456caae | 1050 | /* must be called with host->lock held */ |
f95f3850 WN |
1051 | static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, |
1052 | struct mmc_request *mrq) | |
1053 | { | |
1054 | dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", | |
1055 | host->state); | |
1056 | ||
f95f3850 WN |
1057 | slot->mrq = mrq; |
1058 | ||
01730558 DA |
1059 | if (host->state == STATE_WAITING_CMD11_DONE) { |
1060 | dev_warn(&slot->mmc->class_dev, | |
1061 | "Voltage change didn't complete\n"); | |
1062 | /* | |
1063 | * this case isn't expected to happen, so we can | |
1064 | * either crash here or just try to continue on | |
1065 | * in the closest possible state | |
1066 | */ | |
1067 | host->state = STATE_IDLE; | |
1068 | } | |
1069 | ||
f95f3850 WN |
1070 | if (host->state == STATE_IDLE) { |
1071 | host->state = STATE_SENDING_CMD; | |
1072 | dw_mci_start_request(host, slot); | |
1073 | } else { | |
1074 | list_add_tail(&slot->queue_node, &host->queue); | |
1075 | } | |
f95f3850 WN |
1076 | } |
1077 | ||
1078 | static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1079 | { | |
1080 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
1081 | struct dw_mci *host = slot->host; | |
1082 | ||
1083 | WARN_ON(slot->mrq); | |
1084 | ||
7456caae JH |
1085 | /* |
1086 | * The check for card presence and queueing of the request must be | |
1087 | * atomic, otherwise the card could be removed in between and the | |
1088 | * request wouldn't fail until another card was inserted. | |
1089 | */ | |
1090 | spin_lock_bh(&host->lock); | |
1091 | ||
f95f3850 | 1092 | if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { |
7456caae | 1093 | spin_unlock_bh(&host->lock); |
f95f3850 WN |
1094 | mrq->cmd->error = -ENOMEDIUM; |
1095 | mmc_request_done(mmc, mrq); | |
1096 | return; | |
1097 | } | |
1098 | ||
f95f3850 | 1099 | dw_mci_queue_request(host, slot, mrq); |
7456caae JH |
1100 | |
1101 | spin_unlock_bh(&host->lock); | |
f95f3850 WN |
1102 | } |
1103 | ||
1104 | static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1105 | { | |
1106 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
e95baf13 | 1107 | const struct dw_mci_drv_data *drv_data = slot->host->drv_data; |
41babf75 | 1108 | u32 regs; |
51da2240 | 1109 | int ret; |
f95f3850 | 1110 | |
f95f3850 | 1111 | switch (ios->bus_width) { |
f95f3850 WN |
1112 | case MMC_BUS_WIDTH_4: |
1113 | slot->ctype = SDMMC_CTYPE_4BIT; | |
1114 | break; | |
c9b2a06f JC |
1115 | case MMC_BUS_WIDTH_8: |
1116 | slot->ctype = SDMMC_CTYPE_8BIT; | |
1117 | break; | |
b2f7cb45 JC |
1118 | default: |
1119 | /* set default 1 bit mode */ | |
1120 | slot->ctype = SDMMC_CTYPE_1BIT; | |
f95f3850 WN |
1121 | } |
1122 | ||
3f514291 SJ |
1123 | regs = mci_readl(slot->host, UHS_REG); |
1124 | ||
41babf75 | 1125 | /* DDR mode set */ |
80113132 SJ |
1126 | if (ios->timing == MMC_TIMING_MMC_DDR52 || |
1127 | ios->timing == MMC_TIMING_MMC_HS400) | |
c69042a5 | 1128 | regs |= ((0x1 << slot->id) << 16); |
3f514291 | 1129 | else |
c69042a5 | 1130 | regs &= ~((0x1 << slot->id) << 16); |
3f514291 SJ |
1131 | |
1132 | mci_writel(slot->host, UHS_REG, regs); | |
f1d2736c | 1133 | slot->host->timing = ios->timing; |
41babf75 | 1134 | |
fdf492a1 DA |
1135 | /* |
1136 | * Use mirror of ios->clock to prevent race with mmc | |
1137 | * core ios update when finding the minimum. | |
1138 | */ | |
1139 | slot->clock = ios->clock; | |
f95f3850 | 1140 | |
cb27a843 JH |
1141 | if (drv_data && drv_data->set_ios) |
1142 | drv_data->set_ios(slot->host, ios); | |
800d78bf | 1143 | |
f95f3850 WN |
1144 | switch (ios->power_mode) { |
1145 | case MMC_POWER_UP: | |
51da2240 YC |
1146 | if (!IS_ERR(mmc->supply.vmmc)) { |
1147 | ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, | |
1148 | ios->vdd); | |
1149 | if (ret) { | |
1150 | dev_err(slot->host->dev, | |
1151 | "failed to enable vmmc regulator\n"); | |
1152 | /*return, if failed turn on vmmc*/ | |
1153 | return; | |
1154 | } | |
1155 | } | |
29d0d161 DA |
1156 | set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); |
1157 | regs = mci_readl(slot->host, PWREN); | |
1158 | regs |= (1 << slot->id); | |
1159 | mci_writel(slot->host, PWREN, regs); | |
1160 | break; | |
1161 | case MMC_POWER_ON: | |
d1f1dd86 DA |
1162 | if (!slot->host->vqmmc_enabled) { |
1163 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
1164 | ret = regulator_enable(mmc->supply.vqmmc); | |
1165 | if (ret < 0) | |
1166 | dev_err(slot->host->dev, | |
1167 | "failed to enable vqmmc\n"); | |
1168 | else | |
1169 | slot->host->vqmmc_enabled = true; | |
1170 | ||
1171 | } else { | |
1172 | /* Keep track so we don't reset again */ | |
51da2240 | 1173 | slot->host->vqmmc_enabled = true; |
d1f1dd86 DA |
1174 | } |
1175 | ||
1176 | /* Reset our state machine after powering on */ | |
1177 | dw_mci_ctrl_reset(slot->host, | |
1178 | SDMMC_CTRL_ALL_RESET_FLAGS); | |
51da2240 | 1179 | } |
655babbd DA |
1180 | |
1181 | /* Adjust clock / bus width after power is up */ | |
1182 | dw_mci_setup_bus(slot, false); | |
1183 | ||
e6f34e2f JH |
1184 | break; |
1185 | case MMC_POWER_OFF: | |
655babbd DA |
1186 | /* Turn clock off before power goes down */ |
1187 | dw_mci_setup_bus(slot, false); | |
1188 | ||
51da2240 YC |
1189 | if (!IS_ERR(mmc->supply.vmmc)) |
1190 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
1191 | ||
d1f1dd86 | 1192 | if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) |
51da2240 | 1193 | regulator_disable(mmc->supply.vqmmc); |
d1f1dd86 | 1194 | slot->host->vqmmc_enabled = false; |
51da2240 | 1195 | |
4366dcc5 JC |
1196 | regs = mci_readl(slot->host, PWREN); |
1197 | regs &= ~(1 << slot->id); | |
1198 | mci_writel(slot->host, PWREN, regs); | |
f95f3850 WN |
1199 | break; |
1200 | default: | |
1201 | break; | |
1202 | } | |
655babbd DA |
1203 | |
1204 | if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) | |
1205 | slot->host->state = STATE_IDLE; | |
f95f3850 WN |
1206 | } |
1207 | ||
01730558 DA |
1208 | static int dw_mci_card_busy(struct mmc_host *mmc) |
1209 | { | |
1210 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
1211 | u32 status; | |
1212 | ||
1213 | /* | |
1214 | * Check the busy bit which is low when DAT[3:0] | |
1215 | * (the data lines) are 0000 | |
1216 | */ | |
1217 | status = mci_readl(slot->host, STATUS); | |
1218 | ||
1219 | return !!(status & SDMMC_STATUS_BUSY); | |
1220 | } | |
1221 | ||
1222 | static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) | |
1223 | { | |
1224 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
1225 | struct dw_mci *host = slot->host; | |
1226 | u32 uhs; | |
1227 | u32 v18 = SDMMC_UHS_18V << slot->id; | |
1228 | int min_uv, max_uv; | |
1229 | int ret; | |
1230 | ||
1231 | /* | |
1232 | * Program the voltage. Note that some instances of dw_mmc may use | |
1233 | * the UHS_REG for this. For other instances (like exynos) the UHS_REG | |
1234 | * does no harm but you need to set the regulator directly. Try both. | |
1235 | */ | |
1236 | uhs = mci_readl(host, UHS_REG); | |
1237 | if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) { | |
1238 | min_uv = 2700000; | |
1239 | max_uv = 3600000; | |
1240 | uhs &= ~v18; | |
1241 | } else { | |
1242 | min_uv = 1700000; | |
1243 | max_uv = 1950000; | |
1244 | uhs |= v18; | |
1245 | } | |
1246 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
1247 | ret = regulator_set_voltage(mmc->supply.vqmmc, min_uv, max_uv); | |
1248 | ||
1249 | if (ret) { | |
b19caf37 | 1250 | dev_dbg(&mmc->class_dev, |
01730558 DA |
1251 | "Regulator set error %d: %d - %d\n", |
1252 | ret, min_uv, max_uv); | |
1253 | return ret; | |
1254 | } | |
1255 | } | |
1256 | mci_writel(host, UHS_REG, uhs); | |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
f95f3850 WN |
1261 | static int dw_mci_get_ro(struct mmc_host *mmc) |
1262 | { | |
1263 | int read_only; | |
1264 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
9795a846 | 1265 | int gpio_ro = mmc_gpio_get_ro(mmc); |
f95f3850 WN |
1266 | |
1267 | /* Use platform get_ro function, else try on board write protect */ | |
26375b5c JC |
1268 | if ((slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT) || |
1269 | (slot->host->quirks & DW_MCI_QUIRK_NO_WRITE_PROTECT)) | |
b4967aa5 | 1270 | read_only = 0; |
9795a846 JC |
1271 | else if (!IS_ERR_VALUE(gpio_ro)) |
1272 | read_only = gpio_ro; | |
f95f3850 WN |
1273 | else |
1274 | read_only = | |
1275 | mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; | |
1276 | ||
1277 | dev_dbg(&mmc->class_dev, "card is %s\n", | |
1278 | read_only ? "read-only" : "read-write"); | |
1279 | ||
1280 | return read_only; | |
1281 | } | |
1282 | ||
1283 | static int dw_mci_get_cd(struct mmc_host *mmc) | |
1284 | { | |
1285 | int present; | |
1286 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
1287 | struct dw_mci_board *brd = slot->host->pdata; | |
7cf347bd ZG |
1288 | struct dw_mci *host = slot->host; |
1289 | int gpio_cd = mmc_gpio_get_cd(mmc); | |
f95f3850 WN |
1290 | |
1291 | /* Use platform get_cd function, else try onboard card detect */ | |
fc3d7720 JC |
1292 | if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) |
1293 | present = 1; | |
bf626e55 | 1294 | else if (!IS_ERR_VALUE(gpio_cd)) |
7cf347bd | 1295 | present = gpio_cd; |
f95f3850 WN |
1296 | else |
1297 | present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) | |
1298 | == 0 ? 1 : 0; | |
1299 | ||
7cf347bd | 1300 | spin_lock_bh(&host->lock); |
bf626e55 ZG |
1301 | if (present) { |
1302 | set_bit(DW_MMC_CARD_PRESENT, &slot->flags); | |
f95f3850 | 1303 | dev_dbg(&mmc->class_dev, "card is present\n"); |
bf626e55 ZG |
1304 | } else { |
1305 | clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); | |
f95f3850 | 1306 | dev_dbg(&mmc->class_dev, "card is not present\n"); |
bf626e55 | 1307 | } |
7cf347bd | 1308 | spin_unlock_bh(&host->lock); |
f95f3850 WN |
1309 | |
1310 | return present; | |
1311 | } | |
1312 | ||
b24c8b26 | 1313 | static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card) |
9623b5b9 | 1314 | { |
b24c8b26 | 1315 | struct dw_mci_slot *slot = mmc_priv(mmc); |
9623b5b9 | 1316 | struct dw_mci *host = slot->host; |
9623b5b9 | 1317 | |
b24c8b26 DA |
1318 | /* |
1319 | * Low power mode will stop the card clock when idle. According to the | |
1320 | * description of the CLKENA register we should disable low power mode | |
1321 | * for SDIO cards if we need SDIO interrupts to work. | |
1322 | */ | |
1323 | if (mmc->caps & MMC_CAP_SDIO_IRQ) { | |
1324 | const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; | |
1325 | u32 clk_en_a_old; | |
1326 | u32 clk_en_a; | |
9623b5b9 | 1327 | |
b24c8b26 DA |
1328 | clk_en_a_old = mci_readl(host, CLKENA); |
1329 | ||
1330 | if (card->type == MMC_TYPE_SDIO || | |
1331 | card->type == MMC_TYPE_SD_COMBO) { | |
1332 | set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); | |
1333 | clk_en_a = clk_en_a_old & ~clken_low_pwr; | |
1334 | } else { | |
1335 | clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); | |
1336 | clk_en_a = clk_en_a_old | clken_low_pwr; | |
1337 | } | |
1338 | ||
1339 | if (clk_en_a != clk_en_a_old) { | |
1340 | mci_writel(host, CLKENA, clk_en_a); | |
1341 | mci_send_cmd(slot, SDMMC_CMD_UPD_CLK | | |
1342 | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
1343 | } | |
9623b5b9 DA |
1344 | } |
1345 | } | |
1346 | ||
1a5c8e1f SH |
1347 | static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) |
1348 | { | |
1349 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
1350 | struct dw_mci *host = slot->host; | |
f8c58c11 | 1351 | unsigned long irqflags; |
1a5c8e1f SH |
1352 | u32 int_mask; |
1353 | ||
f8c58c11 DA |
1354 | spin_lock_irqsave(&host->irq_lock, irqflags); |
1355 | ||
1a5c8e1f SH |
1356 | /* Enable/disable Slot Specific SDIO interrupt */ |
1357 | int_mask = mci_readl(host, INTMASK); | |
b24c8b26 DA |
1358 | if (enb) |
1359 | int_mask |= SDMMC_INT_SDIO(slot->sdio_id); | |
1360 | else | |
1361 | int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); | |
1362 | mci_writel(host, INTMASK, int_mask); | |
f8c58c11 DA |
1363 | |
1364 | spin_unlock_irqrestore(&host->irq_lock, irqflags); | |
1a5c8e1f SH |
1365 | } |
1366 | ||
0976f16d SJ |
1367 | static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
1368 | { | |
1369 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
1370 | struct dw_mci *host = slot->host; | |
1371 | const struct dw_mci_drv_data *drv_data = host->drv_data; | |
0976f16d SJ |
1372 | int err = -ENOSYS; |
1373 | ||
0976f16d | 1374 | if (drv_data && drv_data->execute_tuning) |
6c2c6506 | 1375 | err = drv_data->execute_tuning(slot); |
0976f16d SJ |
1376 | return err; |
1377 | } | |
1378 | ||
c22f5e1b | 1379 | static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) |
80113132 SJ |
1380 | { |
1381 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
1382 | struct dw_mci *host = slot->host; | |
1383 | const struct dw_mci_drv_data *drv_data = host->drv_data; | |
1384 | ||
1385 | if (drv_data && drv_data->prepare_hs400_tuning) | |
1386 | return drv_data->prepare_hs400_tuning(host, ios); | |
1387 | ||
1388 | return 0; | |
1389 | } | |
1390 | ||
f95f3850 | 1391 | static const struct mmc_host_ops dw_mci_ops = { |
1a5c8e1f | 1392 | .request = dw_mci_request, |
9aa51408 SJ |
1393 | .pre_req = dw_mci_pre_req, |
1394 | .post_req = dw_mci_post_req, | |
1a5c8e1f SH |
1395 | .set_ios = dw_mci_set_ios, |
1396 | .get_ro = dw_mci_get_ro, | |
1397 | .get_cd = dw_mci_get_cd, | |
1398 | .enable_sdio_irq = dw_mci_enable_sdio_irq, | |
0976f16d | 1399 | .execute_tuning = dw_mci_execute_tuning, |
01730558 DA |
1400 | .card_busy = dw_mci_card_busy, |
1401 | .start_signal_voltage_switch = dw_mci_switch_voltage, | |
b24c8b26 | 1402 | .init_card = dw_mci_init_card, |
80113132 | 1403 | .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning, |
f95f3850 WN |
1404 | }; |
1405 | ||
1406 | static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) | |
1407 | __releases(&host->lock) | |
1408 | __acquires(&host->lock) | |
1409 | { | |
1410 | struct dw_mci_slot *slot; | |
1411 | struct mmc_host *prev_mmc = host->cur_slot->mmc; | |
1412 | ||
1413 | WARN_ON(host->cmd || host->data); | |
1414 | ||
1415 | host->cur_slot->mrq = NULL; | |
1416 | host->mrq = NULL; | |
1417 | if (!list_empty(&host->queue)) { | |
1418 | slot = list_entry(host->queue.next, | |
1419 | struct dw_mci_slot, queue_node); | |
1420 | list_del(&slot->queue_node); | |
4a90920c | 1421 | dev_vdbg(host->dev, "list not empty: %s is next\n", |
f95f3850 WN |
1422 | mmc_hostname(slot->mmc)); |
1423 | host->state = STATE_SENDING_CMD; | |
1424 | dw_mci_start_request(host, slot); | |
1425 | } else { | |
4a90920c | 1426 | dev_vdbg(host->dev, "list empty\n"); |
01730558 DA |
1427 | |
1428 | if (host->state == STATE_SENDING_CMD11) | |
1429 | host->state = STATE_WAITING_CMD11_DONE; | |
1430 | else | |
1431 | host->state = STATE_IDLE; | |
f95f3850 WN |
1432 | } |
1433 | ||
1434 | spin_unlock(&host->lock); | |
1435 | mmc_request_done(prev_mmc, mrq); | |
1436 | spin_lock(&host->lock); | |
1437 | } | |
1438 | ||
e352c813 | 1439 | static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) |
f95f3850 WN |
1440 | { |
1441 | u32 status = host->cmd_status; | |
1442 | ||
1443 | host->cmd_status = 0; | |
1444 | ||
1445 | /* Read the response from the card (up to 16 bytes) */ | |
1446 | if (cmd->flags & MMC_RSP_PRESENT) { | |
1447 | if (cmd->flags & MMC_RSP_136) { | |
1448 | cmd->resp[3] = mci_readl(host, RESP0); | |
1449 | cmd->resp[2] = mci_readl(host, RESP1); | |
1450 | cmd->resp[1] = mci_readl(host, RESP2); | |
1451 | cmd->resp[0] = mci_readl(host, RESP3); | |
1452 | } else { | |
1453 | cmd->resp[0] = mci_readl(host, RESP0); | |
1454 | cmd->resp[1] = 0; | |
1455 | cmd->resp[2] = 0; | |
1456 | cmd->resp[3] = 0; | |
1457 | } | |
1458 | } | |
1459 | ||
1460 | if (status & SDMMC_INT_RTO) | |
1461 | cmd->error = -ETIMEDOUT; | |
1462 | else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) | |
1463 | cmd->error = -EILSEQ; | |
1464 | else if (status & SDMMC_INT_RESP_ERR) | |
1465 | cmd->error = -EIO; | |
1466 | else | |
1467 | cmd->error = 0; | |
1468 | ||
1469 | if (cmd->error) { | |
1470 | /* newer ip versions need a delay between retries */ | |
1471 | if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) | |
1472 | mdelay(20); | |
f95f3850 | 1473 | } |
e352c813 SJ |
1474 | |
1475 | return cmd->error; | |
1476 | } | |
1477 | ||
1478 | static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data) | |
1479 | { | |
31bff450 | 1480 | u32 status = host->data_status; |
e352c813 SJ |
1481 | |
1482 | if (status & DW_MCI_DATA_ERROR_FLAGS) { | |
1483 | if (status & SDMMC_INT_DRTO) { | |
1484 | data->error = -ETIMEDOUT; | |
1485 | } else if (status & SDMMC_INT_DCRC) { | |
1486 | data->error = -EILSEQ; | |
1487 | } else if (status & SDMMC_INT_EBE) { | |
1488 | if (host->dir_status == | |
1489 | DW_MCI_SEND_STATUS) { | |
1490 | /* | |
1491 | * No data CRC status was returned. | |
1492 | * The number of bytes transferred | |
1493 | * will be exaggerated in PIO mode. | |
1494 | */ | |
1495 | data->bytes_xfered = 0; | |
1496 | data->error = -ETIMEDOUT; | |
1497 | } else if (host->dir_status == | |
1498 | DW_MCI_RECV_STATUS) { | |
1499 | data->error = -EIO; | |
1500 | } | |
1501 | } else { | |
1502 | /* SDMMC_INT_SBE is included */ | |
1503 | data->error = -EIO; | |
1504 | } | |
1505 | ||
e6cc0123 | 1506 | dev_dbg(host->dev, "data error, status 0x%08x\n", status); |
e352c813 SJ |
1507 | |
1508 | /* | |
1509 | * After an error, there may be data lingering | |
31bff450 | 1510 | * in the FIFO |
e352c813 | 1511 | */ |
3a33a94c | 1512 | dw_mci_reset(host); |
e352c813 SJ |
1513 | } else { |
1514 | data->bytes_xfered = data->blocks * data->blksz; | |
1515 | data->error = 0; | |
1516 | } | |
1517 | ||
1518 | return data->error; | |
f95f3850 WN |
1519 | } |
1520 | ||
1521 | static void dw_mci_tasklet_func(unsigned long priv) | |
1522 | { | |
1523 | struct dw_mci *host = (struct dw_mci *)priv; | |
1524 | struct mmc_data *data; | |
1525 | struct mmc_command *cmd; | |
e352c813 | 1526 | struct mmc_request *mrq; |
f95f3850 WN |
1527 | enum dw_mci_state state; |
1528 | enum dw_mci_state prev_state; | |
e352c813 | 1529 | unsigned int err; |
f95f3850 WN |
1530 | |
1531 | spin_lock(&host->lock); | |
1532 | ||
1533 | state = host->state; | |
1534 | data = host->data; | |
e352c813 | 1535 | mrq = host->mrq; |
f95f3850 WN |
1536 | |
1537 | do { | |
1538 | prev_state = state; | |
1539 | ||
1540 | switch (state) { | |
1541 | case STATE_IDLE: | |
01730558 | 1542 | case STATE_WAITING_CMD11_DONE: |
f95f3850 WN |
1543 | break; |
1544 | ||
01730558 | 1545 | case STATE_SENDING_CMD11: |
f95f3850 WN |
1546 | case STATE_SENDING_CMD: |
1547 | if (!test_and_clear_bit(EVENT_CMD_COMPLETE, | |
1548 | &host->pending_events)) | |
1549 | break; | |
1550 | ||
1551 | cmd = host->cmd; | |
1552 | host->cmd = NULL; | |
1553 | set_bit(EVENT_CMD_COMPLETE, &host->completed_events); | |
e352c813 SJ |
1554 | err = dw_mci_command_complete(host, cmd); |
1555 | if (cmd == mrq->sbc && !err) { | |
053b3ce6 SJ |
1556 | prev_state = state = STATE_SENDING_CMD; |
1557 | __dw_mci_start_request(host, host->cur_slot, | |
e352c813 | 1558 | mrq->cmd); |
053b3ce6 SJ |
1559 | goto unlock; |
1560 | } | |
1561 | ||
e352c813 | 1562 | if (cmd->data && err) { |
71abb133 | 1563 | dw_mci_stop_dma(host); |
90c2143a SJ |
1564 | send_stop_abort(host, data); |
1565 | state = STATE_SENDING_STOP; | |
1566 | break; | |
71abb133 SJ |
1567 | } |
1568 | ||
e352c813 SJ |
1569 | if (!cmd->data || err) { |
1570 | dw_mci_request_end(host, mrq); | |
f95f3850 WN |
1571 | goto unlock; |
1572 | } | |
1573 | ||
1574 | prev_state = state = STATE_SENDING_DATA; | |
1575 | /* fall through */ | |
1576 | ||
1577 | case STATE_SENDING_DATA: | |
2aa35465 DA |
1578 | /* |
1579 | * We could get a data error and never a transfer | |
1580 | * complete so we'd better check for it here. | |
1581 | * | |
1582 | * Note that we don't really care if we also got a | |
1583 | * transfer complete; stopping the DMA and sending an | |
1584 | * abort won't hurt. | |
1585 | */ | |
f95f3850 WN |
1586 | if (test_and_clear_bit(EVENT_DATA_ERROR, |
1587 | &host->pending_events)) { | |
1588 | dw_mci_stop_dma(host); | |
bdb9a90b | 1589 | if (data->stop || |
1590 | !(host->data_status & (SDMMC_INT_DRTO | | |
1591 | SDMMC_INT_EBE))) | |
1592 | send_stop_abort(host, data); | |
f95f3850 WN |
1593 | state = STATE_DATA_ERROR; |
1594 | break; | |
1595 | } | |
1596 | ||
1597 | if (!test_and_clear_bit(EVENT_XFER_COMPLETE, | |
1598 | &host->pending_events)) | |
1599 | break; | |
1600 | ||
1601 | set_bit(EVENT_XFER_COMPLETE, &host->completed_events); | |
2aa35465 DA |
1602 | |
1603 | /* | |
1604 | * Handle an EVENT_DATA_ERROR that might have shown up | |
1605 | * before the transfer completed. This might not have | |
1606 | * been caught by the check above because the interrupt | |
1607 | * could have gone off between the previous check and | |
1608 | * the check for transfer complete. | |
1609 | * | |
1610 | * Technically this ought not be needed assuming we | |
1611 | * get a DATA_COMPLETE eventually (we'll notice the | |
1612 | * error and end the request), but it shouldn't hurt. | |
1613 | * | |
1614 | * This has the advantage of sending the stop command. | |
1615 | */ | |
1616 | if (test_and_clear_bit(EVENT_DATA_ERROR, | |
1617 | &host->pending_events)) { | |
1618 | dw_mci_stop_dma(host); | |
bdb9a90b | 1619 | if (data->stop || |
1620 | !(host->data_status & (SDMMC_INT_DRTO | | |
1621 | SDMMC_INT_EBE))) | |
1622 | send_stop_abort(host, data); | |
2aa35465 DA |
1623 | state = STATE_DATA_ERROR; |
1624 | break; | |
1625 | } | |
f95f3850 | 1626 | prev_state = state = STATE_DATA_BUSY; |
2aa35465 | 1627 | |
f95f3850 WN |
1628 | /* fall through */ |
1629 | ||
1630 | case STATE_DATA_BUSY: | |
1631 | if (!test_and_clear_bit(EVENT_DATA_COMPLETE, | |
1632 | &host->pending_events)) | |
1633 | break; | |
1634 | ||
1635 | host->data = NULL; | |
1636 | set_bit(EVENT_DATA_COMPLETE, &host->completed_events); | |
e352c813 SJ |
1637 | err = dw_mci_data_complete(host, data); |
1638 | ||
1639 | if (!err) { | |
1640 | if (!data->stop || mrq->sbc) { | |
17c8bc85 | 1641 | if (mrq->sbc && data->stop) |
e352c813 SJ |
1642 | data->stop->error = 0; |
1643 | dw_mci_request_end(host, mrq); | |
1644 | goto unlock; | |
f95f3850 | 1645 | } |
f95f3850 | 1646 | |
e352c813 SJ |
1647 | /* stop command for open-ended transfer*/ |
1648 | if (data->stop) | |
1649 | send_stop_abort(host, data); | |
2aa35465 DA |
1650 | } else { |
1651 | /* | |
1652 | * If we don't have a command complete now we'll | |
1653 | * never get one since we just reset everything; | |
1654 | * better end the request. | |
1655 | * | |
1656 | * If we do have a command complete we'll fall | |
1657 | * through to the SENDING_STOP command and | |
1658 | * everything will be peachy keen. | |
1659 | */ | |
1660 | if (!test_bit(EVENT_CMD_COMPLETE, | |
1661 | &host->pending_events)) { | |
1662 | host->cmd = NULL; | |
1663 | dw_mci_request_end(host, mrq); | |
1664 | goto unlock; | |
1665 | } | |
053b3ce6 SJ |
1666 | } |
1667 | ||
e352c813 SJ |
1668 | /* |
1669 | * If err has non-zero, | |
1670 | * stop-abort command has been already issued. | |
1671 | */ | |
f95f3850 | 1672 | prev_state = state = STATE_SENDING_STOP; |
e352c813 | 1673 | |
f95f3850 WN |
1674 | /* fall through */ |
1675 | ||
1676 | case STATE_SENDING_STOP: | |
1677 | if (!test_and_clear_bit(EVENT_CMD_COMPLETE, | |
1678 | &host->pending_events)) | |
1679 | break; | |
1680 | ||
71abb133 | 1681 | /* CMD error in data command */ |
31bff450 | 1682 | if (mrq->cmd->error && mrq->data) |
3a33a94c | 1683 | dw_mci_reset(host); |
71abb133 | 1684 | |
f95f3850 | 1685 | host->cmd = NULL; |
71abb133 | 1686 | host->data = NULL; |
90c2143a | 1687 | |
e352c813 SJ |
1688 | if (mrq->stop) |
1689 | dw_mci_command_complete(host, mrq->stop); | |
90c2143a SJ |
1690 | else |
1691 | host->cmd_status = 0; | |
1692 | ||
e352c813 | 1693 | dw_mci_request_end(host, mrq); |
f95f3850 WN |
1694 | goto unlock; |
1695 | ||
1696 | case STATE_DATA_ERROR: | |
1697 | if (!test_and_clear_bit(EVENT_XFER_COMPLETE, | |
1698 | &host->pending_events)) | |
1699 | break; | |
1700 | ||
1701 | state = STATE_DATA_BUSY; | |
1702 | break; | |
1703 | } | |
1704 | } while (state != prev_state); | |
1705 | ||
1706 | host->state = state; | |
1707 | unlock: | |
1708 | spin_unlock(&host->lock); | |
1709 | ||
1710 | } | |
1711 | ||
34b664a2 JH |
1712 | /* push final bytes to part_buf, only use during push */ |
1713 | static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
f95f3850 | 1714 | { |
34b664a2 JH |
1715 | memcpy((void *)&host->part_buf, buf, cnt); |
1716 | host->part_buf_count = cnt; | |
1717 | } | |
f95f3850 | 1718 | |
34b664a2 JH |
1719 | /* append bytes to part_buf, only use during push */ |
1720 | static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
1721 | { | |
1722 | cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); | |
1723 | memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); | |
1724 | host->part_buf_count += cnt; | |
1725 | return cnt; | |
1726 | } | |
f95f3850 | 1727 | |
34b664a2 JH |
1728 | /* pull first bytes from part_buf, only use during pull */ |
1729 | static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
1730 | { | |
1731 | cnt = min(cnt, (int)host->part_buf_count); | |
1732 | if (cnt) { | |
1733 | memcpy(buf, (void *)&host->part_buf + host->part_buf_start, | |
1734 | cnt); | |
1735 | host->part_buf_count -= cnt; | |
1736 | host->part_buf_start += cnt; | |
f95f3850 | 1737 | } |
34b664a2 | 1738 | return cnt; |
f95f3850 WN |
1739 | } |
1740 | ||
34b664a2 JH |
1741 | /* pull final bytes from the part_buf, assuming it's just been filled */ |
1742 | static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) | |
f95f3850 | 1743 | { |
34b664a2 JH |
1744 | memcpy(buf, &host->part_buf, cnt); |
1745 | host->part_buf_start = cnt; | |
1746 | host->part_buf_count = (1 << host->data_shift) - cnt; | |
1747 | } | |
f95f3850 | 1748 | |
34b664a2 JH |
1749 | static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) |
1750 | { | |
cfbeb59c MC |
1751 | struct mmc_data *data = host->data; |
1752 | int init_cnt = cnt; | |
1753 | ||
34b664a2 JH |
1754 | /* try and push anything in the part_buf */ |
1755 | if (unlikely(host->part_buf_count)) { | |
1756 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1757 | buf += len; | |
1758 | cnt -= len; | |
cfbeb59c | 1759 | if (host->part_buf_count == 2) { |
76184ac1 | 1760 | mci_fifo_writew(host->fifo_reg, host->part_buf16); |
34b664a2 JH |
1761 | host->part_buf_count = 0; |
1762 | } | |
1763 | } | |
1764 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1765 | if (unlikely((unsigned long)buf & 0x1)) { | |
1766 | while (cnt >= 2) { | |
1767 | u16 aligned_buf[64]; | |
1768 | int len = min(cnt & -2, (int)sizeof(aligned_buf)); | |
1769 | int items = len >> 1; | |
1770 | int i; | |
1771 | /* memcpy from input buffer into aligned buffer */ | |
1772 | memcpy(aligned_buf, buf, len); | |
1773 | buf += len; | |
1774 | cnt -= len; | |
1775 | /* push data from aligned buffer into fifo */ | |
1776 | for (i = 0; i < items; ++i) | |
76184ac1 | 1777 | mci_fifo_writew(host->fifo_reg, aligned_buf[i]); |
34b664a2 JH |
1778 | } |
1779 | } else | |
1780 | #endif | |
1781 | { | |
1782 | u16 *pdata = buf; | |
1783 | for (; cnt >= 2; cnt -= 2) | |
76184ac1 | 1784 | mci_fifo_writew(host->fifo_reg, *pdata++); |
34b664a2 JH |
1785 | buf = pdata; |
1786 | } | |
1787 | /* put anything remaining in the part_buf */ | |
1788 | if (cnt) { | |
1789 | dw_mci_set_part_bytes(host, buf, cnt); | |
cfbeb59c MC |
1790 | /* Push data if we have reached the expected data length */ |
1791 | if ((data->bytes_xfered + init_cnt) == | |
1792 | (data->blksz * data->blocks)) | |
76184ac1 | 1793 | mci_fifo_writew(host->fifo_reg, host->part_buf16); |
34b664a2 JH |
1794 | } |
1795 | } | |
f95f3850 | 1796 | |
34b664a2 JH |
1797 | static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) |
1798 | { | |
1799 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1800 | if (unlikely((unsigned long)buf & 0x1)) { | |
1801 | while (cnt >= 2) { | |
1802 | /* pull data from fifo into aligned buffer */ | |
1803 | u16 aligned_buf[64]; | |
1804 | int len = min(cnt & -2, (int)sizeof(aligned_buf)); | |
1805 | int items = len >> 1; | |
1806 | int i; | |
1807 | for (i = 0; i < items; ++i) | |
76184ac1 | 1808 | aligned_buf[i] = mci_fifo_readw(host->fifo_reg); |
34b664a2 JH |
1809 | /* memcpy from aligned buffer into output buffer */ |
1810 | memcpy(buf, aligned_buf, len); | |
1811 | buf += len; | |
1812 | cnt -= len; | |
1813 | } | |
1814 | } else | |
1815 | #endif | |
1816 | { | |
1817 | u16 *pdata = buf; | |
1818 | for (; cnt >= 2; cnt -= 2) | |
76184ac1 | 1819 | *pdata++ = mci_fifo_readw(host->fifo_reg); |
34b664a2 JH |
1820 | buf = pdata; |
1821 | } | |
1822 | if (cnt) { | |
76184ac1 | 1823 | host->part_buf16 = mci_fifo_readw(host->fifo_reg); |
34b664a2 | 1824 | dw_mci_pull_final_bytes(host, buf, cnt); |
f95f3850 WN |
1825 | } |
1826 | } | |
1827 | ||
1828 | static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) | |
1829 | { | |
cfbeb59c MC |
1830 | struct mmc_data *data = host->data; |
1831 | int init_cnt = cnt; | |
1832 | ||
34b664a2 JH |
1833 | /* try and push anything in the part_buf */ |
1834 | if (unlikely(host->part_buf_count)) { | |
1835 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1836 | buf += len; | |
1837 | cnt -= len; | |
cfbeb59c | 1838 | if (host->part_buf_count == 4) { |
76184ac1 | 1839 | mci_fifo_writel(host->fifo_reg, host->part_buf32); |
34b664a2 JH |
1840 | host->part_buf_count = 0; |
1841 | } | |
1842 | } | |
1843 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1844 | if (unlikely((unsigned long)buf & 0x3)) { | |
1845 | while (cnt >= 4) { | |
1846 | u32 aligned_buf[32]; | |
1847 | int len = min(cnt & -4, (int)sizeof(aligned_buf)); | |
1848 | int items = len >> 2; | |
1849 | int i; | |
1850 | /* memcpy from input buffer into aligned buffer */ | |
1851 | memcpy(aligned_buf, buf, len); | |
1852 | buf += len; | |
1853 | cnt -= len; | |
1854 | /* push data from aligned buffer into fifo */ | |
1855 | for (i = 0; i < items; ++i) | |
76184ac1 | 1856 | mci_fifo_writel(host->fifo_reg, aligned_buf[i]); |
34b664a2 JH |
1857 | } |
1858 | } else | |
1859 | #endif | |
1860 | { | |
1861 | u32 *pdata = buf; | |
1862 | for (; cnt >= 4; cnt -= 4) | |
76184ac1 | 1863 | mci_fifo_writel(host->fifo_reg, *pdata++); |
34b664a2 JH |
1864 | buf = pdata; |
1865 | } | |
1866 | /* put anything remaining in the part_buf */ | |
1867 | if (cnt) { | |
1868 | dw_mci_set_part_bytes(host, buf, cnt); | |
cfbeb59c MC |
1869 | /* Push data if we have reached the expected data length */ |
1870 | if ((data->bytes_xfered + init_cnt) == | |
1871 | (data->blksz * data->blocks)) | |
76184ac1 | 1872 | mci_fifo_writel(host->fifo_reg, host->part_buf32); |
f95f3850 WN |
1873 | } |
1874 | } | |
1875 | ||
1876 | static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) | |
1877 | { | |
34b664a2 JH |
1878 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
1879 | if (unlikely((unsigned long)buf & 0x3)) { | |
1880 | while (cnt >= 4) { | |
1881 | /* pull data from fifo into aligned buffer */ | |
1882 | u32 aligned_buf[32]; | |
1883 | int len = min(cnt & -4, (int)sizeof(aligned_buf)); | |
1884 | int items = len >> 2; | |
1885 | int i; | |
1886 | for (i = 0; i < items; ++i) | |
76184ac1 | 1887 | aligned_buf[i] = mci_fifo_readl(host->fifo_reg); |
34b664a2 JH |
1888 | /* memcpy from aligned buffer into output buffer */ |
1889 | memcpy(buf, aligned_buf, len); | |
1890 | buf += len; | |
1891 | cnt -= len; | |
1892 | } | |
1893 | } else | |
1894 | #endif | |
1895 | { | |
1896 | u32 *pdata = buf; | |
1897 | for (; cnt >= 4; cnt -= 4) | |
76184ac1 | 1898 | *pdata++ = mci_fifo_readl(host->fifo_reg); |
34b664a2 JH |
1899 | buf = pdata; |
1900 | } | |
1901 | if (cnt) { | |
76184ac1 | 1902 | host->part_buf32 = mci_fifo_readl(host->fifo_reg); |
34b664a2 | 1903 | dw_mci_pull_final_bytes(host, buf, cnt); |
f95f3850 WN |
1904 | } |
1905 | } | |
1906 | ||
1907 | static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) | |
1908 | { | |
cfbeb59c MC |
1909 | struct mmc_data *data = host->data; |
1910 | int init_cnt = cnt; | |
1911 | ||
34b664a2 JH |
1912 | /* try and push anything in the part_buf */ |
1913 | if (unlikely(host->part_buf_count)) { | |
1914 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1915 | buf += len; | |
1916 | cnt -= len; | |
c09fbd74 | 1917 | |
cfbeb59c | 1918 | if (host->part_buf_count == 8) { |
76184ac1 | 1919 | mci_fifo_writeq(host->fifo_reg, host->part_buf); |
34b664a2 JH |
1920 | host->part_buf_count = 0; |
1921 | } | |
1922 | } | |
1923 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1924 | if (unlikely((unsigned long)buf & 0x7)) { | |
1925 | while (cnt >= 8) { | |
1926 | u64 aligned_buf[16]; | |
1927 | int len = min(cnt & -8, (int)sizeof(aligned_buf)); | |
1928 | int items = len >> 3; | |
1929 | int i; | |
1930 | /* memcpy from input buffer into aligned buffer */ | |
1931 | memcpy(aligned_buf, buf, len); | |
1932 | buf += len; | |
1933 | cnt -= len; | |
1934 | /* push data from aligned buffer into fifo */ | |
1935 | for (i = 0; i < items; ++i) | |
76184ac1 | 1936 | mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); |
34b664a2 JH |
1937 | } |
1938 | } else | |
1939 | #endif | |
1940 | { | |
1941 | u64 *pdata = buf; | |
1942 | for (; cnt >= 8; cnt -= 8) | |
76184ac1 | 1943 | mci_fifo_writeq(host->fifo_reg, *pdata++); |
34b664a2 JH |
1944 | buf = pdata; |
1945 | } | |
1946 | /* put anything remaining in the part_buf */ | |
1947 | if (cnt) { | |
1948 | dw_mci_set_part_bytes(host, buf, cnt); | |
cfbeb59c MC |
1949 | /* Push data if we have reached the expected data length */ |
1950 | if ((data->bytes_xfered + init_cnt) == | |
1951 | (data->blksz * data->blocks)) | |
76184ac1 | 1952 | mci_fifo_writeq(host->fifo_reg, host->part_buf); |
f95f3850 WN |
1953 | } |
1954 | } | |
1955 | ||
1956 | static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) | |
1957 | { | |
34b664a2 JH |
1958 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
1959 | if (unlikely((unsigned long)buf & 0x7)) { | |
1960 | while (cnt >= 8) { | |
1961 | /* pull data from fifo into aligned buffer */ | |
1962 | u64 aligned_buf[16]; | |
1963 | int len = min(cnt & -8, (int)sizeof(aligned_buf)); | |
1964 | int items = len >> 3; | |
1965 | int i; | |
1966 | for (i = 0; i < items; ++i) | |
76184ac1 BD |
1967 | aligned_buf[i] = mci_fifo_readq(host->fifo_reg); |
1968 | ||
34b664a2 JH |
1969 | /* memcpy from aligned buffer into output buffer */ |
1970 | memcpy(buf, aligned_buf, len); | |
1971 | buf += len; | |
1972 | cnt -= len; | |
1973 | } | |
1974 | } else | |
1975 | #endif | |
1976 | { | |
1977 | u64 *pdata = buf; | |
1978 | for (; cnt >= 8; cnt -= 8) | |
76184ac1 | 1979 | *pdata++ = mci_fifo_readq(host->fifo_reg); |
34b664a2 JH |
1980 | buf = pdata; |
1981 | } | |
1982 | if (cnt) { | |
76184ac1 | 1983 | host->part_buf = mci_fifo_readq(host->fifo_reg); |
34b664a2 JH |
1984 | dw_mci_pull_final_bytes(host, buf, cnt); |
1985 | } | |
1986 | } | |
f95f3850 | 1987 | |
34b664a2 JH |
1988 | static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) |
1989 | { | |
1990 | int len; | |
f95f3850 | 1991 | |
34b664a2 JH |
1992 | /* get remaining partial bytes */ |
1993 | len = dw_mci_pull_part_bytes(host, buf, cnt); | |
1994 | if (unlikely(len == cnt)) | |
1995 | return; | |
1996 | buf += len; | |
1997 | cnt -= len; | |
1998 | ||
1999 | /* get the rest of the data */ | |
2000 | host->pull_data(host, buf, cnt); | |
f95f3850 WN |
2001 | } |
2002 | ||
87a74d39 | 2003 | static void dw_mci_read_data_pio(struct dw_mci *host, bool dto) |
f95f3850 | 2004 | { |
f9c2a0dc SJ |
2005 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
2006 | void *buf; | |
2007 | unsigned int offset; | |
f95f3850 WN |
2008 | struct mmc_data *data = host->data; |
2009 | int shift = host->data_shift; | |
2010 | u32 status; | |
3e4b0d8b | 2011 | unsigned int len; |
f9c2a0dc | 2012 | unsigned int remain, fcnt; |
f95f3850 WN |
2013 | |
2014 | do { | |
f9c2a0dc SJ |
2015 | if (!sg_miter_next(sg_miter)) |
2016 | goto done; | |
2017 | ||
4225fc85 | 2018 | host->sg = sg_miter->piter.sg; |
f9c2a0dc SJ |
2019 | buf = sg_miter->addr; |
2020 | remain = sg_miter->length; | |
2021 | offset = 0; | |
2022 | ||
2023 | do { | |
2024 | fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS)) | |
2025 | << shift) + host->part_buf_count; | |
2026 | len = min(remain, fcnt); | |
2027 | if (!len) | |
2028 | break; | |
34b664a2 | 2029 | dw_mci_pull_data(host, (void *)(buf + offset), len); |
3e4b0d8b | 2030 | data->bytes_xfered += len; |
f95f3850 | 2031 | offset += len; |
f9c2a0dc SJ |
2032 | remain -= len; |
2033 | } while (remain); | |
f95f3850 | 2034 | |
e74f3a9c | 2035 | sg_miter->consumed = offset; |
f95f3850 WN |
2036 | status = mci_readl(host, MINTSTS); |
2037 | mci_writel(host, RINTSTS, SDMMC_INT_RXDR); | |
87a74d39 KK |
2038 | /* if the RXDR is ready read again */ |
2039 | } while ((status & SDMMC_INT_RXDR) || | |
2040 | (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS)))); | |
f9c2a0dc SJ |
2041 | |
2042 | if (!remain) { | |
2043 | if (!sg_miter_next(sg_miter)) | |
2044 | goto done; | |
2045 | sg_miter->consumed = 0; | |
2046 | } | |
2047 | sg_miter_stop(sg_miter); | |
f95f3850 WN |
2048 | return; |
2049 | ||
2050 | done: | |
f9c2a0dc SJ |
2051 | sg_miter_stop(sg_miter); |
2052 | host->sg = NULL; | |
f95f3850 WN |
2053 | smp_wmb(); |
2054 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
2055 | } | |
2056 | ||
2057 | static void dw_mci_write_data_pio(struct dw_mci *host) | |
2058 | { | |
f9c2a0dc SJ |
2059 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
2060 | void *buf; | |
2061 | unsigned int offset; | |
f95f3850 WN |
2062 | struct mmc_data *data = host->data; |
2063 | int shift = host->data_shift; | |
2064 | u32 status; | |
3e4b0d8b | 2065 | unsigned int len; |
f9c2a0dc SJ |
2066 | unsigned int fifo_depth = host->fifo_depth; |
2067 | unsigned int remain, fcnt; | |
f95f3850 WN |
2068 | |
2069 | do { | |
f9c2a0dc SJ |
2070 | if (!sg_miter_next(sg_miter)) |
2071 | goto done; | |
2072 | ||
4225fc85 | 2073 | host->sg = sg_miter->piter.sg; |
f9c2a0dc SJ |
2074 | buf = sg_miter->addr; |
2075 | remain = sg_miter->length; | |
2076 | offset = 0; | |
2077 | ||
2078 | do { | |
2079 | fcnt = ((fifo_depth - | |
2080 | SDMMC_GET_FCNT(mci_readl(host, STATUS))) | |
2081 | << shift) - host->part_buf_count; | |
2082 | len = min(remain, fcnt); | |
2083 | if (!len) | |
2084 | break; | |
f95f3850 | 2085 | host->push_data(host, (void *)(buf + offset), len); |
3e4b0d8b | 2086 | data->bytes_xfered += len; |
f95f3850 | 2087 | offset += len; |
f9c2a0dc SJ |
2088 | remain -= len; |
2089 | } while (remain); | |
f95f3850 | 2090 | |
e74f3a9c | 2091 | sg_miter->consumed = offset; |
f95f3850 WN |
2092 | status = mci_readl(host, MINTSTS); |
2093 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR); | |
f95f3850 | 2094 | } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ |
f9c2a0dc SJ |
2095 | |
2096 | if (!remain) { | |
2097 | if (!sg_miter_next(sg_miter)) | |
2098 | goto done; | |
2099 | sg_miter->consumed = 0; | |
2100 | } | |
2101 | sg_miter_stop(sg_miter); | |
f95f3850 WN |
2102 | return; |
2103 | ||
2104 | done: | |
f9c2a0dc SJ |
2105 | sg_miter_stop(sg_miter); |
2106 | host->sg = NULL; | |
f95f3850 WN |
2107 | smp_wmb(); |
2108 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
2109 | } | |
2110 | ||
2111 | static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) | |
2112 | { | |
2113 | if (!host->cmd_status) | |
2114 | host->cmd_status = status; | |
2115 | ||
2116 | smp_wmb(); | |
2117 | ||
2118 | set_bit(EVENT_CMD_COMPLETE, &host->pending_events); | |
2119 | tasklet_schedule(&host->tasklet); | |
2120 | } | |
2121 | ||
6130e7a9 DA |
2122 | static void dw_mci_handle_cd(struct dw_mci *host) |
2123 | { | |
2124 | int i; | |
2125 | ||
2126 | for (i = 0; i < host->num_slots; i++) { | |
2127 | struct dw_mci_slot *slot = host->slot[i]; | |
2128 | ||
2129 | if (!slot) | |
2130 | continue; | |
2131 | ||
2132 | if (slot->mmc->ops->card_event) | |
2133 | slot->mmc->ops->card_event(slot->mmc); | |
2134 | mmc_detect_change(slot->mmc, | |
2135 | msecs_to_jiffies(host->pdata->detect_delay_ms)); | |
2136 | } | |
2137 | } | |
2138 | ||
f95f3850 WN |
2139 | static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) |
2140 | { | |
2141 | struct dw_mci *host = dev_id; | |
182c9081 | 2142 | u32 pending; |
1a5c8e1f | 2143 | int i; |
f95f3850 | 2144 | |
1fb5f68a MC |
2145 | pending = mci_readl(host, MINTSTS); /* read-only mask reg */ |
2146 | ||
476d79f1 DA |
2147 | /* |
2148 | * DTO fix - version 2.10a and below, and only if internal DMA | |
2149 | * is configured. | |
2150 | */ | |
2151 | if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { | |
2152 | if (!pending && | |
2153 | ((mci_readl(host, STATUS) >> 17) & 0x1fff)) | |
2154 | pending |= SDMMC_INT_DATA_OVER; | |
2155 | } | |
f95f3850 | 2156 | |
476d79f1 | 2157 | if (pending) { |
01730558 DA |
2158 | /* Check volt switch first, since it can look like an error */ |
2159 | if ((host->state == STATE_SENDING_CMD11) && | |
2160 | (pending & SDMMC_INT_VOLT_SWITCH)) { | |
5c935165 DA |
2161 | del_timer(&host->cmd11_timer); |
2162 | ||
01730558 DA |
2163 | mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH); |
2164 | pending &= ~SDMMC_INT_VOLT_SWITCH; | |
2165 | dw_mci_cmd_interrupt(host, pending); | |
2166 | } | |
2167 | ||
f95f3850 WN |
2168 | if (pending & DW_MCI_CMD_ERROR_FLAGS) { |
2169 | mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); | |
182c9081 | 2170 | host->cmd_status = pending; |
f95f3850 WN |
2171 | smp_wmb(); |
2172 | set_bit(EVENT_CMD_COMPLETE, &host->pending_events); | |
f95f3850 WN |
2173 | } |
2174 | ||
2175 | if (pending & DW_MCI_DATA_ERROR_FLAGS) { | |
2176 | /* if there is an error report DATA_ERROR */ | |
2177 | mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); | |
182c9081 | 2178 | host->data_status = pending; |
f95f3850 WN |
2179 | smp_wmb(); |
2180 | set_bit(EVENT_DATA_ERROR, &host->pending_events); | |
9b2026a1 | 2181 | tasklet_schedule(&host->tasklet); |
f95f3850 WN |
2182 | } |
2183 | ||
2184 | if (pending & SDMMC_INT_DATA_OVER) { | |
2185 | mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); | |
2186 | if (!host->data_status) | |
182c9081 | 2187 | host->data_status = pending; |
f95f3850 WN |
2188 | smp_wmb(); |
2189 | if (host->dir_status == DW_MCI_RECV_STATUS) { | |
2190 | if (host->sg != NULL) | |
87a74d39 | 2191 | dw_mci_read_data_pio(host, true); |
f95f3850 WN |
2192 | } |
2193 | set_bit(EVENT_DATA_COMPLETE, &host->pending_events); | |
2194 | tasklet_schedule(&host->tasklet); | |
2195 | } | |
2196 | ||
2197 | if (pending & SDMMC_INT_RXDR) { | |
2198 | mci_writel(host, RINTSTS, SDMMC_INT_RXDR); | |
b40af3aa | 2199 | if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) |
87a74d39 | 2200 | dw_mci_read_data_pio(host, false); |
f95f3850 WN |
2201 | } |
2202 | ||
2203 | if (pending & SDMMC_INT_TXDR) { | |
2204 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR); | |
b40af3aa | 2205 | if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) |
f95f3850 WN |
2206 | dw_mci_write_data_pio(host); |
2207 | } | |
2208 | ||
2209 | if (pending & SDMMC_INT_CMD_DONE) { | |
2210 | mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); | |
182c9081 | 2211 | dw_mci_cmd_interrupt(host, pending); |
f95f3850 WN |
2212 | } |
2213 | ||
2214 | if (pending & SDMMC_INT_CD) { | |
2215 | mci_writel(host, RINTSTS, SDMMC_INT_CD); | |
6130e7a9 | 2216 | dw_mci_handle_cd(host); |
f95f3850 WN |
2217 | } |
2218 | ||
1a5c8e1f SH |
2219 | /* Handle SDIO Interrupts */ |
2220 | for (i = 0; i < host->num_slots; i++) { | |
2221 | struct dw_mci_slot *slot = host->slot[i]; | |
ed2540ef DA |
2222 | |
2223 | if (!slot) | |
2224 | continue; | |
2225 | ||
76756234 AK |
2226 | if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { |
2227 | mci_writel(host, RINTSTS, | |
2228 | SDMMC_INT_SDIO(slot->sdio_id)); | |
1a5c8e1f SH |
2229 | mmc_signal_sdio_irq(slot->mmc); |
2230 | } | |
2231 | } | |
2232 | ||
1fb5f68a | 2233 | } |
f95f3850 WN |
2234 | |
2235 | #ifdef CONFIG_MMC_DW_IDMAC | |
2236 | /* Handle DMA interrupts */ | |
69d99fdc PT |
2237 | if (host->dma_64bit_address == 1) { |
2238 | pending = mci_readl(host, IDSTS64); | |
2239 | if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { | |
2240 | mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI | | |
2241 | SDMMC_IDMAC_INT_RI); | |
2242 | mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI); | |
2243 | host->dma_ops->complete(host); | |
2244 | } | |
2245 | } else { | |
2246 | pending = mci_readl(host, IDSTS); | |
2247 | if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { | |
2248 | mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | | |
2249 | SDMMC_IDMAC_INT_RI); | |
2250 | mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); | |
2251 | host->dma_ops->complete(host); | |
2252 | } | |
f95f3850 WN |
2253 | } |
2254 | #endif | |
2255 | ||
2256 | return IRQ_HANDLED; | |
2257 | } | |
2258 | ||
c91eab4b TA |
2259 | #ifdef CONFIG_OF |
2260 | /* given a slot id, find out the device node representing that slot */ | |
2261 | static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot) | |
2262 | { | |
2263 | struct device_node *np; | |
2264 | const __be32 *addr; | |
2265 | int len; | |
2266 | ||
2267 | if (!dev || !dev->of_node) | |
2268 | return NULL; | |
2269 | ||
2270 | for_each_child_of_node(dev->of_node, np) { | |
2271 | addr = of_get_property(np, "reg", &len); | |
2272 | if (!addr || (len < sizeof(int))) | |
2273 | continue; | |
2274 | if (be32_to_cpup(addr) == slot) | |
2275 | return np; | |
2276 | } | |
2277 | return NULL; | |
2278 | } | |
2279 | ||
a70aaa64 DA |
2280 | static struct dw_mci_of_slot_quirks { |
2281 | char *quirk; | |
2282 | int id; | |
2283 | } of_slot_quirks[] = { | |
2284 | { | |
2285 | .quirk = "disable-wp", | |
2286 | .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT, | |
2287 | }, | |
2288 | }; | |
2289 | ||
2290 | static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) | |
2291 | { | |
2292 | struct device_node *np = dw_mci_of_find_slot_node(dev, slot); | |
2293 | int quirks = 0; | |
2294 | int idx; | |
2295 | ||
2296 | /* get quirks */ | |
2297 | for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++) | |
26375b5c JC |
2298 | if (of_get_property(np, of_slot_quirks[idx].quirk, NULL)) { |
2299 | dev_warn(dev, "Slot quirk %s is deprecated\n", | |
2300 | of_slot_quirks[idx].quirk); | |
a70aaa64 | 2301 | quirks |= of_slot_quirks[idx].id; |
26375b5c | 2302 | } |
a70aaa64 DA |
2303 | |
2304 | return quirks; | |
2305 | } | |
c91eab4b | 2306 | #else /* CONFIG_OF */ |
a70aaa64 DA |
2307 | static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot) |
2308 | { | |
2309 | return 0; | |
2310 | } | |
c91eab4b TA |
2311 | #endif /* CONFIG_OF */ |
2312 | ||
36c179a9 | 2313 | static int dw_mci_init_slot(struct dw_mci *host, unsigned int id) |
f95f3850 WN |
2314 | { |
2315 | struct mmc_host *mmc; | |
2316 | struct dw_mci_slot *slot; | |
e95baf13 | 2317 | const struct dw_mci_drv_data *drv_data = host->drv_data; |
800d78bf | 2318 | int ctrl_id, ret; |
1f44a2a5 | 2319 | u32 freq[2]; |
f95f3850 | 2320 | |
4a90920c | 2321 | mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); |
f95f3850 WN |
2322 | if (!mmc) |
2323 | return -ENOMEM; | |
2324 | ||
2325 | slot = mmc_priv(mmc); | |
2326 | slot->id = id; | |
76756234 | 2327 | slot->sdio_id = host->sdio_id0 + id; |
f95f3850 WN |
2328 | slot->mmc = mmc; |
2329 | slot->host = host; | |
c91eab4b | 2330 | host->slot[id] = slot; |
f95f3850 | 2331 | |
a70aaa64 DA |
2332 | slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id); |
2333 | ||
f95f3850 | 2334 | mmc->ops = &dw_mci_ops; |
1f44a2a5 SJ |
2335 | if (of_property_read_u32_array(host->dev->of_node, |
2336 | "clock-freq-min-max", freq, 2)) { | |
2337 | mmc->f_min = DW_MCI_FREQ_MIN; | |
2338 | mmc->f_max = DW_MCI_FREQ_MAX; | |
2339 | } else { | |
2340 | mmc->f_min = freq[0]; | |
2341 | mmc->f_max = freq[1]; | |
2342 | } | |
f95f3850 | 2343 | |
51da2240 YC |
2344 | /*if there are external regulators, get them*/ |
2345 | ret = mmc_regulator_get_supply(mmc); | |
2346 | if (ret == -EPROBE_DEFER) | |
3cf890fc | 2347 | goto err_host_allocated; |
51da2240 YC |
2348 | |
2349 | if (!mmc->ocr_avail) | |
2350 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
f95f3850 | 2351 | |
fc3d7720 JC |
2352 | if (host->pdata->caps) |
2353 | mmc->caps = host->pdata->caps; | |
fc3d7720 | 2354 | |
ab269128 AK |
2355 | if (host->pdata->pm_caps) |
2356 | mmc->pm_caps = host->pdata->pm_caps; | |
2357 | ||
800d78bf TA |
2358 | if (host->dev->of_node) { |
2359 | ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); | |
2360 | if (ctrl_id < 0) | |
2361 | ctrl_id = 0; | |
2362 | } else { | |
2363 | ctrl_id = to_platform_device(host->dev)->id; | |
2364 | } | |
cb27a843 JH |
2365 | if (drv_data && drv_data->caps) |
2366 | mmc->caps |= drv_data->caps[ctrl_id]; | |
800d78bf | 2367 | |
4f408cc6 SJ |
2368 | if (host->pdata->caps2) |
2369 | mmc->caps2 = host->pdata->caps2; | |
4f408cc6 | 2370 | |
3cf890fc DA |
2371 | ret = mmc_of_parse(mmc); |
2372 | if (ret) | |
2373 | goto err_host_allocated; | |
f95f3850 | 2374 | |
f95f3850 WN |
2375 | if (host->pdata->blk_settings) { |
2376 | mmc->max_segs = host->pdata->blk_settings->max_segs; | |
2377 | mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; | |
2378 | mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; | |
2379 | mmc->max_req_size = host->pdata->blk_settings->max_req_size; | |
2380 | mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; | |
2381 | } else { | |
2382 | /* Useful defaults if platform data is unset. */ | |
a39e5746 JC |
2383 | #ifdef CONFIG_MMC_DW_IDMAC |
2384 | mmc->max_segs = host->ring_size; | |
2385 | mmc->max_blk_size = 65536; | |
a39e5746 | 2386 | mmc->max_seg_size = 0x1000; |
1a25b1b4 SJ |
2387 | mmc->max_req_size = mmc->max_seg_size * host->ring_size; |
2388 | mmc->max_blk_count = mmc->max_req_size / 512; | |
a39e5746 | 2389 | #else |
f95f3850 WN |
2390 | mmc->max_segs = 64; |
2391 | mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ | |
2392 | mmc->max_blk_count = 512; | |
2393 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
2394 | mmc->max_seg_size = mmc->max_req_size; | |
f95f3850 | 2395 | #endif /* CONFIG_MMC_DW_IDMAC */ |
a39e5746 | 2396 | } |
f95f3850 | 2397 | |
ae0eb348 JC |
2398 | if (dw_mci_get_cd(mmc)) |
2399 | set_bit(DW_MMC_CARD_PRESENT, &slot->flags); | |
2400 | else | |
2401 | clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); | |
2402 | ||
0cea529d JC |
2403 | ret = mmc_add_host(mmc); |
2404 | if (ret) | |
3cf890fc | 2405 | goto err_host_allocated; |
f95f3850 WN |
2406 | |
2407 | #if defined(CONFIG_DEBUG_FS) | |
2408 | dw_mci_init_debugfs(slot); | |
2409 | #endif | |
2410 | ||
f95f3850 | 2411 | return 0; |
800d78bf | 2412 | |
3cf890fc | 2413 | err_host_allocated: |
800d78bf | 2414 | mmc_free_host(mmc); |
51da2240 | 2415 | return ret; |
f95f3850 WN |
2416 | } |
2417 | ||
2418 | static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) | |
2419 | { | |
f95f3850 WN |
2420 | /* Debugfs stuff is cleaned up by mmc core */ |
2421 | mmc_remove_host(slot->mmc); | |
2422 | slot->host->slot[id] = NULL; | |
2423 | mmc_free_host(slot->mmc); | |
2424 | } | |
2425 | ||
2426 | static void dw_mci_init_dma(struct dw_mci *host) | |
2427 | { | |
69d99fdc PT |
2428 | int addr_config; |
2429 | /* Check ADDR_CONFIG bit in HCON to find IDMAC address bus width */ | |
2430 | addr_config = (mci_readl(host, HCON) >> 27) & 0x01; | |
2431 | ||
2432 | if (addr_config == 1) { | |
2433 | /* host supports IDMAC in 64-bit address mode */ | |
2434 | host->dma_64bit_address = 1; | |
2435 | dev_info(host->dev, "IDMAC supports 64-bit address mode.\n"); | |
2436 | if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) | |
2437 | dma_set_coherent_mask(host->dev, DMA_BIT_MASK(64)); | |
2438 | } else { | |
2439 | /* host supports IDMAC in 32-bit address mode */ | |
2440 | host->dma_64bit_address = 0; | |
2441 | dev_info(host->dev, "IDMAC supports 32-bit address mode.\n"); | |
2442 | } | |
2443 | ||
f95f3850 | 2444 | /* Alloc memory for sg translation */ |
780f22af | 2445 | host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE, |
f95f3850 WN |
2446 | &host->sg_dma, GFP_KERNEL); |
2447 | if (!host->sg_cpu) { | |
4a90920c | 2448 | dev_err(host->dev, "%s: could not alloc DMA memory\n", |
f95f3850 WN |
2449 | __func__); |
2450 | goto no_dma; | |
2451 | } | |
2452 | ||
2453 | /* Determine which DMA interface to use */ | |
2454 | #ifdef CONFIG_MMC_DW_IDMAC | |
2455 | host->dma_ops = &dw_mci_idmac_ops; | |
00956ea3 | 2456 | dev_info(host->dev, "Using internal DMA controller.\n"); |
f95f3850 WN |
2457 | #endif |
2458 | ||
2459 | if (!host->dma_ops) | |
2460 | goto no_dma; | |
2461 | ||
e1631f98 JC |
2462 | if (host->dma_ops->init && host->dma_ops->start && |
2463 | host->dma_ops->stop && host->dma_ops->cleanup) { | |
f95f3850 | 2464 | if (host->dma_ops->init(host)) { |
4a90920c | 2465 | dev_err(host->dev, "%s: Unable to initialize " |
f95f3850 WN |
2466 | "DMA Controller.\n", __func__); |
2467 | goto no_dma; | |
2468 | } | |
2469 | } else { | |
4a90920c | 2470 | dev_err(host->dev, "DMA initialization not found.\n"); |
f95f3850 WN |
2471 | goto no_dma; |
2472 | } | |
2473 | ||
2474 | host->use_dma = 1; | |
2475 | return; | |
2476 | ||
2477 | no_dma: | |
4a90920c | 2478 | dev_info(host->dev, "Using PIO mode.\n"); |
f95f3850 WN |
2479 | host->use_dma = 0; |
2480 | return; | |
2481 | } | |
2482 | ||
31bff450 | 2483 | static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset) |
f95f3850 WN |
2484 | { |
2485 | unsigned long timeout = jiffies + msecs_to_jiffies(500); | |
31bff450 | 2486 | u32 ctrl; |
f95f3850 | 2487 | |
31bff450 SJ |
2488 | ctrl = mci_readl(host, CTRL); |
2489 | ctrl |= reset; | |
2490 | mci_writel(host, CTRL, ctrl); | |
f95f3850 WN |
2491 | |
2492 | /* wait till resets clear */ | |
2493 | do { | |
2494 | ctrl = mci_readl(host, CTRL); | |
31bff450 | 2495 | if (!(ctrl & reset)) |
f95f3850 WN |
2496 | return true; |
2497 | } while (time_before(jiffies, timeout)); | |
2498 | ||
31bff450 SJ |
2499 | dev_err(host->dev, |
2500 | "Timeout resetting block (ctrl reset %#x)\n", | |
2501 | ctrl & reset); | |
f95f3850 WN |
2502 | |
2503 | return false; | |
2504 | } | |
2505 | ||
3a33a94c | 2506 | static bool dw_mci_reset(struct dw_mci *host) |
31bff450 | 2507 | { |
3a33a94c SR |
2508 | u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET; |
2509 | bool ret = false; | |
2510 | ||
31bff450 SJ |
2511 | /* |
2512 | * Reseting generates a block interrupt, hence setting | |
2513 | * the scatter-gather pointer to NULL. | |
2514 | */ | |
2515 | if (host->sg) { | |
2516 | sg_miter_stop(&host->sg_miter); | |
2517 | host->sg = NULL; | |
2518 | } | |
2519 | ||
3a33a94c SR |
2520 | if (host->use_dma) |
2521 | flags |= SDMMC_CTRL_DMA_RESET; | |
31bff450 | 2522 | |
3a33a94c SR |
2523 | if (dw_mci_ctrl_reset(host, flags)) { |
2524 | /* | |
2525 | * In all cases we clear the RAWINTS register to clear any | |
2526 | * interrupts. | |
2527 | */ | |
2528 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2529 | ||
2530 | /* if using dma we wait for dma_req to clear */ | |
2531 | if (host->use_dma) { | |
2532 | unsigned long timeout = jiffies + msecs_to_jiffies(500); | |
2533 | u32 status; | |
2534 | do { | |
2535 | status = mci_readl(host, STATUS); | |
2536 | if (!(status & SDMMC_STATUS_DMA_REQ)) | |
2537 | break; | |
2538 | cpu_relax(); | |
2539 | } while (time_before(jiffies, timeout)); | |
2540 | ||
2541 | if (status & SDMMC_STATUS_DMA_REQ) { | |
2542 | dev_err(host->dev, | |
2543 | "%s: Timeout waiting for dma_req to " | |
2544 | "clear during reset\n", __func__); | |
2545 | goto ciu_out; | |
2546 | } | |
2547 | ||
2548 | /* when using DMA next we reset the fifo again */ | |
2549 | if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET)) | |
2550 | goto ciu_out; | |
2551 | } | |
2552 | } else { | |
2553 | /* if the controller reset bit did clear, then set clock regs */ | |
2554 | if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { | |
2555 | dev_err(host->dev, "%s: fifo/dma reset bits didn't " | |
2556 | "clear but ciu was reset, doing clock update\n", | |
2557 | __func__); | |
2558 | goto ciu_out; | |
2559 | } | |
2560 | } | |
2561 | ||
2562 | #if IS_ENABLED(CONFIG_MMC_DW_IDMAC) | |
2563 | /* It is also recommended that we reset and reprogram idmac */ | |
2564 | dw_mci_idmac_reset(host); | |
2565 | #endif | |
2566 | ||
2567 | ret = true; | |
2568 | ||
2569 | ciu_out: | |
2570 | /* After a CTRL reset we need to have CIU set clock registers */ | |
2571 | mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0); | |
2572 | ||
2573 | return ret; | |
31bff450 SJ |
2574 | } |
2575 | ||
5c935165 DA |
2576 | static void dw_mci_cmd11_timer(unsigned long arg) |
2577 | { | |
2578 | struct dw_mci *host = (struct dw_mci *)arg; | |
2579 | ||
2580 | if (host->state != STATE_SENDING_CMD11) | |
2581 | dev_info(host->dev, "Unexpected CMD11 timeout\n"); | |
2582 | ||
2583 | host->cmd_status = SDMMC_INT_RTO; | |
2584 | set_bit(EVENT_CMD_COMPLETE, &host->pending_events); | |
2585 | tasklet_schedule(&host->tasklet); | |
2586 | } | |
2587 | ||
c91eab4b TA |
2588 | #ifdef CONFIG_OF |
2589 | static struct dw_mci_of_quirks { | |
2590 | char *quirk; | |
2591 | int id; | |
2592 | } of_quirks[] = { | |
2593 | { | |
c91eab4b TA |
2594 | .quirk = "broken-cd", |
2595 | .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION, | |
26375b5c JC |
2596 | }, { |
2597 | .quirk = "disable-wp", | |
2598 | .id = DW_MCI_QUIRK_NO_WRITE_PROTECT, | |
c91eab4b TA |
2599 | }, |
2600 | }; | |
2601 | ||
2602 | static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) | |
2603 | { | |
2604 | struct dw_mci_board *pdata; | |
2605 | struct device *dev = host->dev; | |
2606 | struct device_node *np = dev->of_node; | |
e95baf13 | 2607 | const struct dw_mci_drv_data *drv_data = host->drv_data; |
800d78bf | 2608 | int idx, ret; |
3c6d89ea | 2609 | u32 clock_frequency; |
c91eab4b TA |
2610 | |
2611 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
bf3707ea | 2612 | if (!pdata) |
c91eab4b | 2613 | return ERR_PTR(-ENOMEM); |
c91eab4b TA |
2614 | |
2615 | /* find out number of slots supported */ | |
2616 | if (of_property_read_u32(dev->of_node, "num-slots", | |
2617 | &pdata->num_slots)) { | |
2618 | dev_info(dev, "num-slots property not found, " | |
2619 | "assuming 1 slot is available\n"); | |
2620 | pdata->num_slots = 1; | |
2621 | } | |
2622 | ||
2623 | /* get quirks */ | |
2624 | for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++) | |
2625 | if (of_get_property(np, of_quirks[idx].quirk, NULL)) | |
2626 | pdata->quirks |= of_quirks[idx].id; | |
2627 | ||
2628 | if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth)) | |
2629 | dev_info(dev, "fifo-depth property not found, using " | |
2630 | "value of FIFOTH register as default\n"); | |
2631 | ||
2632 | of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms); | |
2633 | ||
3c6d89ea DA |
2634 | if (!of_property_read_u32(np, "clock-frequency", &clock_frequency)) |
2635 | pdata->bus_hz = clock_frequency; | |
2636 | ||
cb27a843 JH |
2637 | if (drv_data && drv_data->parse_dt) { |
2638 | ret = drv_data->parse_dt(host); | |
800d78bf TA |
2639 | if (ret) |
2640 | return ERR_PTR(ret); | |
2641 | } | |
2642 | ||
10b49841 SJ |
2643 | if (of_find_property(np, "supports-highspeed", NULL)) |
2644 | pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; | |
2645 | ||
c91eab4b TA |
2646 | return pdata; |
2647 | } | |
2648 | ||
2649 | #else /* CONFIG_OF */ | |
2650 | static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host) | |
2651 | { | |
2652 | return ERR_PTR(-EINVAL); | |
2653 | } | |
2654 | #endif /* CONFIG_OF */ | |
2655 | ||
fa0c3283 DA |
2656 | static void dw_mci_enable_cd(struct dw_mci *host) |
2657 | { | |
2658 | struct dw_mci_board *brd = host->pdata; | |
2659 | unsigned long irqflags; | |
2660 | u32 temp; | |
2661 | int i; | |
2662 | ||
2663 | /* No need for CD if broken card detection */ | |
2664 | if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) | |
2665 | return; | |
2666 | ||
2667 | /* No need for CD if all slots have a non-error GPIO */ | |
2668 | for (i = 0; i < host->num_slots; i++) { | |
2669 | struct dw_mci_slot *slot = host->slot[i]; | |
2670 | ||
2671 | if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc))) | |
2672 | break; | |
2673 | } | |
2674 | if (i == host->num_slots) | |
2675 | return; | |
2676 | ||
2677 | spin_lock_irqsave(&host->irq_lock, irqflags); | |
2678 | temp = mci_readl(host, INTMASK); | |
2679 | temp |= SDMMC_INT_CD; | |
2680 | mci_writel(host, INTMASK, temp); | |
2681 | spin_unlock_irqrestore(&host->irq_lock, irqflags); | |
2682 | } | |
2683 | ||
62ca8034 | 2684 | int dw_mci_probe(struct dw_mci *host) |
f95f3850 | 2685 | { |
e95baf13 | 2686 | const struct dw_mci_drv_data *drv_data = host->drv_data; |
62ca8034 | 2687 | int width, i, ret = 0; |
f95f3850 | 2688 | u32 fifo_size; |
1c2215b7 | 2689 | int init_slots = 0; |
f95f3850 | 2690 | |
c91eab4b TA |
2691 | if (!host->pdata) { |
2692 | host->pdata = dw_mci_parse_dt(host); | |
2693 | if (IS_ERR(host->pdata)) { | |
2694 | dev_err(host->dev, "platform data not available\n"); | |
2695 | return -EINVAL; | |
2696 | } | |
f95f3850 WN |
2697 | } |
2698 | ||
907abd51 | 2699 | if (host->pdata->num_slots > 1) { |
4a90920c | 2700 | dev_err(host->dev, |
907abd51 | 2701 | "Platform data must supply num_slots.\n"); |
62ca8034 | 2702 | return -ENODEV; |
f95f3850 WN |
2703 | } |
2704 | ||
780f22af | 2705 | host->biu_clk = devm_clk_get(host->dev, "biu"); |
f90a0612 TA |
2706 | if (IS_ERR(host->biu_clk)) { |
2707 | dev_dbg(host->dev, "biu clock not available\n"); | |
2708 | } else { | |
2709 | ret = clk_prepare_enable(host->biu_clk); | |
2710 | if (ret) { | |
2711 | dev_err(host->dev, "failed to enable biu clock\n"); | |
f90a0612 TA |
2712 | return ret; |
2713 | } | |
2714 | } | |
2715 | ||
780f22af | 2716 | host->ciu_clk = devm_clk_get(host->dev, "ciu"); |
f90a0612 TA |
2717 | if (IS_ERR(host->ciu_clk)) { |
2718 | dev_dbg(host->dev, "ciu clock not available\n"); | |
3c6d89ea | 2719 | host->bus_hz = host->pdata->bus_hz; |
f90a0612 TA |
2720 | } else { |
2721 | ret = clk_prepare_enable(host->ciu_clk); | |
2722 | if (ret) { | |
2723 | dev_err(host->dev, "failed to enable ciu clock\n"); | |
f90a0612 TA |
2724 | goto err_clk_biu; |
2725 | } | |
f90a0612 | 2726 | |
3c6d89ea DA |
2727 | if (host->pdata->bus_hz) { |
2728 | ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); | |
2729 | if (ret) | |
2730 | dev_warn(host->dev, | |
612de4c1 | 2731 | "Unable to set bus rate to %uHz\n", |
3c6d89ea DA |
2732 | host->pdata->bus_hz); |
2733 | } | |
f90a0612 | 2734 | host->bus_hz = clk_get_rate(host->ciu_clk); |
3c6d89ea | 2735 | } |
f90a0612 | 2736 | |
612de4c1 JC |
2737 | if (!host->bus_hz) { |
2738 | dev_err(host->dev, | |
2739 | "Platform data must supply bus speed\n"); | |
2740 | ret = -ENODEV; | |
2741 | goto err_clk_ciu; | |
2742 | } | |
2743 | ||
002f0d5c YK |
2744 | if (drv_data && drv_data->init) { |
2745 | ret = drv_data->init(host); | |
2746 | if (ret) { | |
2747 | dev_err(host->dev, | |
2748 | "implementation specific init failed\n"); | |
2749 | goto err_clk_ciu; | |
2750 | } | |
2751 | } | |
2752 | ||
cb27a843 JH |
2753 | if (drv_data && drv_data->setup_clock) { |
2754 | ret = drv_data->setup_clock(host); | |
800d78bf TA |
2755 | if (ret) { |
2756 | dev_err(host->dev, | |
2757 | "implementation specific clock setup failed\n"); | |
2758 | goto err_clk_ciu; | |
2759 | } | |
2760 | } | |
2761 | ||
5c935165 DA |
2762 | setup_timer(&host->cmd11_timer, |
2763 | dw_mci_cmd11_timer, (unsigned long)host); | |
2764 | ||
62ca8034 | 2765 | host->quirks = host->pdata->quirks; |
f95f3850 WN |
2766 | |
2767 | spin_lock_init(&host->lock); | |
f8c58c11 | 2768 | spin_lock_init(&host->irq_lock); |
f95f3850 WN |
2769 | INIT_LIST_HEAD(&host->queue); |
2770 | ||
f95f3850 WN |
2771 | /* |
2772 | * Get the host data width - this assumes that HCON has been set with | |
2773 | * the correct values. | |
2774 | */ | |
2775 | i = (mci_readl(host, HCON) >> 7) & 0x7; | |
2776 | if (!i) { | |
2777 | host->push_data = dw_mci_push_data16; | |
2778 | host->pull_data = dw_mci_pull_data16; | |
2779 | width = 16; | |
2780 | host->data_shift = 1; | |
2781 | } else if (i == 2) { | |
2782 | host->push_data = dw_mci_push_data64; | |
2783 | host->pull_data = dw_mci_pull_data64; | |
2784 | width = 64; | |
2785 | host->data_shift = 3; | |
2786 | } else { | |
2787 | /* Check for a reserved value, and warn if it is */ | |
2788 | WARN((i != 1), | |
2789 | "HCON reports a reserved host data width!\n" | |
2790 | "Defaulting to 32-bit access.\n"); | |
2791 | host->push_data = dw_mci_push_data32; | |
2792 | host->pull_data = dw_mci_pull_data32; | |
2793 | width = 32; | |
2794 | host->data_shift = 2; | |
2795 | } | |
2796 | ||
2797 | /* Reset all blocks */ | |
3a33a94c | 2798 | if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) |
141a712a SJ |
2799 | return -ENODEV; |
2800 | ||
2801 | host->dma_ops = host->pdata->dma_ops; | |
2802 | dw_mci_init_dma(host); | |
f95f3850 WN |
2803 | |
2804 | /* Clear the interrupts for the host controller */ | |
2805 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2806 | mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ | |
2807 | ||
2808 | /* Put in max timeout */ | |
2809 | mci_writel(host, TMOUT, 0xFFFFFFFF); | |
2810 | ||
2811 | /* | |
2812 | * FIFO threshold settings RxMark = fifo_size / 2 - 1, | |
2813 | * Tx Mark = fifo_size / 2 DMA Size = 8 | |
2814 | */ | |
b86d8253 JH |
2815 | if (!host->pdata->fifo_depth) { |
2816 | /* | |
2817 | * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may | |
2818 | * have been overwritten by the bootloader, just like we're | |
2819 | * about to do, so if you know the value for your hardware, you | |
2820 | * should put it in the platform data. | |
2821 | */ | |
2822 | fifo_size = mci_readl(host, FIFOTH); | |
8234e869 | 2823 | fifo_size = 1 + ((fifo_size >> 16) & 0xfff); |
b86d8253 JH |
2824 | } else { |
2825 | fifo_size = host->pdata->fifo_depth; | |
2826 | } | |
2827 | host->fifo_depth = fifo_size; | |
52426899 SJ |
2828 | host->fifoth_val = |
2829 | SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); | |
e61cf118 | 2830 | mci_writel(host, FIFOTH, host->fifoth_val); |
f95f3850 WN |
2831 | |
2832 | /* disable clock to CIU */ | |
2833 | mci_writel(host, CLKENA, 0); | |
2834 | mci_writel(host, CLKSRC, 0); | |
2835 | ||
63008768 JH |
2836 | /* |
2837 | * In 2.40a spec, Data offset is changed. | |
2838 | * Need to check the version-id and set data-offset for DATA register. | |
2839 | */ | |
2840 | host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); | |
2841 | dev_info(host->dev, "Version ID is %04x\n", host->verid); | |
2842 | ||
2843 | if (host->verid < DW_MMC_240A) | |
76184ac1 | 2844 | host->fifo_reg = host->regs + DATA_OFFSET; |
63008768 | 2845 | else |
76184ac1 | 2846 | host->fifo_reg = host->regs + DATA_240A_OFFSET; |
63008768 | 2847 | |
f95f3850 | 2848 | tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); |
780f22af SJ |
2849 | ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, |
2850 | host->irq_flags, "dw-mci", host); | |
f95f3850 | 2851 | if (ret) |
6130e7a9 | 2852 | goto err_dmaunmap; |
f95f3850 | 2853 | |
f95f3850 WN |
2854 | if (host->pdata->num_slots) |
2855 | host->num_slots = host->pdata->num_slots; | |
2856 | else | |
2857 | host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; | |
2858 | ||
2da1d7f2 | 2859 | /* |
fa0c3283 | 2860 | * Enable interrupts for command done, data over, data empty, |
2da1d7f2 YC |
2861 | * receive ready and error such as transmit, receive timeout, crc error |
2862 | */ | |
2863 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2864 | mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | | |
2865 | SDMMC_INT_TXDR | SDMMC_INT_RXDR | | |
fa0c3283 | 2866 | DW_MCI_ERROR_FLAGS); |
2da1d7f2 YC |
2867 | mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ |
2868 | ||
2869 | dev_info(host->dev, "DW MMC controller at irq %d, " | |
2870 | "%d bit host data width, " | |
2871 | "%u deep fifo\n", | |
2872 | host->irq, width, fifo_size); | |
2873 | ||
f95f3850 WN |
2874 | /* We need at least one slot to succeed */ |
2875 | for (i = 0; i < host->num_slots; i++) { | |
2876 | ret = dw_mci_init_slot(host, i); | |
1c2215b7 TA |
2877 | if (ret) |
2878 | dev_dbg(host->dev, "slot %d init failed\n", i); | |
2879 | else | |
2880 | init_slots++; | |
2881 | } | |
2882 | ||
2883 | if (init_slots) { | |
2884 | dev_info(host->dev, "%d slots initialized\n", init_slots); | |
2885 | } else { | |
2886 | dev_dbg(host->dev, "attempted to initialize %d slots, " | |
2887 | "but failed on all\n", host->num_slots); | |
6130e7a9 | 2888 | goto err_dmaunmap; |
f95f3850 WN |
2889 | } |
2890 | ||
b793f658 DA |
2891 | /* Now that slots are all setup, we can enable card detect */ |
2892 | dw_mci_enable_cd(host); | |
2893 | ||
f95f3850 | 2894 | if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) |
4a90920c | 2895 | dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n"); |
f95f3850 WN |
2896 | |
2897 | return 0; | |
2898 | ||
f95f3850 WN |
2899 | err_dmaunmap: |
2900 | if (host->use_dma && host->dma_ops->exit) | |
2901 | host->dma_ops->exit(host); | |
f90a0612 TA |
2902 | |
2903 | err_clk_ciu: | |
780f22af | 2904 | if (!IS_ERR(host->ciu_clk)) |
f90a0612 | 2905 | clk_disable_unprepare(host->ciu_clk); |
780f22af | 2906 | |
f90a0612 | 2907 | err_clk_biu: |
780f22af | 2908 | if (!IS_ERR(host->biu_clk)) |
f90a0612 | 2909 | clk_disable_unprepare(host->biu_clk); |
780f22af | 2910 | |
f95f3850 WN |
2911 | return ret; |
2912 | } | |
62ca8034 | 2913 | EXPORT_SYMBOL(dw_mci_probe); |
f95f3850 | 2914 | |
62ca8034 | 2915 | void dw_mci_remove(struct dw_mci *host) |
f95f3850 | 2916 | { |
f95f3850 WN |
2917 | int i; |
2918 | ||
2919 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2920 | mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ | |
2921 | ||
f95f3850 | 2922 | for (i = 0; i < host->num_slots; i++) { |
4a90920c | 2923 | dev_dbg(host->dev, "remove slot %d\n", i); |
f95f3850 WN |
2924 | if (host->slot[i]) |
2925 | dw_mci_cleanup_slot(host->slot[i], i); | |
2926 | } | |
2927 | ||
2928 | /* disable clock to CIU */ | |
2929 | mci_writel(host, CLKENA, 0); | |
2930 | mci_writel(host, CLKSRC, 0); | |
2931 | ||
f95f3850 WN |
2932 | if (host->use_dma && host->dma_ops->exit) |
2933 | host->dma_ops->exit(host); | |
2934 | ||
f90a0612 TA |
2935 | if (!IS_ERR(host->ciu_clk)) |
2936 | clk_disable_unprepare(host->ciu_clk); | |
780f22af | 2937 | |
f90a0612 TA |
2938 | if (!IS_ERR(host->biu_clk)) |
2939 | clk_disable_unprepare(host->biu_clk); | |
f95f3850 | 2940 | } |
62ca8034 SH |
2941 | EXPORT_SYMBOL(dw_mci_remove); |
2942 | ||
2943 | ||
f95f3850 | 2944 | |
6fe8890d | 2945 | #ifdef CONFIG_PM_SLEEP |
f95f3850 WN |
2946 | /* |
2947 | * TODO: we should probably disable the clock to the card in the suspend path. | |
2948 | */ | |
62ca8034 | 2949 | int dw_mci_suspend(struct dw_mci *host) |
f95f3850 | 2950 | { |
f95f3850 WN |
2951 | return 0; |
2952 | } | |
62ca8034 | 2953 | EXPORT_SYMBOL(dw_mci_suspend); |
f95f3850 | 2954 | |
62ca8034 | 2955 | int dw_mci_resume(struct dw_mci *host) |
f95f3850 WN |
2956 | { |
2957 | int i, ret; | |
f95f3850 | 2958 | |
3a33a94c | 2959 | if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) { |
e61cf118 JC |
2960 | ret = -ENODEV; |
2961 | return ret; | |
2962 | } | |
2963 | ||
3bfe619d | 2964 | if (host->use_dma && host->dma_ops->init) |
141a712a SJ |
2965 | host->dma_ops->init(host); |
2966 | ||
52426899 SJ |
2967 | /* |
2968 | * Restore the initial value at FIFOTH register | |
2969 | * And Invalidate the prev_blksz with zero | |
2970 | */ | |
e61cf118 | 2971 | mci_writel(host, FIFOTH, host->fifoth_val); |
52426899 | 2972 | host->prev_blksz = 0; |
e61cf118 | 2973 | |
2eb2944f DA |
2974 | /* Put in max timeout */ |
2975 | mci_writel(host, TMOUT, 0xFFFFFFFF); | |
2976 | ||
e61cf118 JC |
2977 | mci_writel(host, RINTSTS, 0xFFFFFFFF); |
2978 | mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | | |
2979 | SDMMC_INT_TXDR | SDMMC_INT_RXDR | | |
fa0c3283 | 2980 | DW_MCI_ERROR_FLAGS); |
e61cf118 JC |
2981 | mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); |
2982 | ||
f95f3850 WN |
2983 | for (i = 0; i < host->num_slots; i++) { |
2984 | struct dw_mci_slot *slot = host->slot[i]; | |
2985 | if (!slot) | |
2986 | continue; | |
ab269128 AK |
2987 | if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) { |
2988 | dw_mci_set_ios(slot->mmc, &slot->mmc->ios); | |
2989 | dw_mci_setup_bus(slot, true); | |
2990 | } | |
f95f3850 | 2991 | } |
fa0c3283 DA |
2992 | |
2993 | /* Now that slots are all setup, we can enable card detect */ | |
2994 | dw_mci_enable_cd(host); | |
2995 | ||
f95f3850 WN |
2996 | return 0; |
2997 | } | |
62ca8034 | 2998 | EXPORT_SYMBOL(dw_mci_resume); |
6fe8890d JC |
2999 | #endif /* CONFIG_PM_SLEEP */ |
3000 | ||
f95f3850 WN |
3001 | static int __init dw_mci_init(void) |
3002 | { | |
8e1c4e4d | 3003 | pr_info("Synopsys Designware Multimedia Card Interface Driver\n"); |
62ca8034 | 3004 | return 0; |
f95f3850 WN |
3005 | } |
3006 | ||
3007 | static void __exit dw_mci_exit(void) | |
3008 | { | |
f95f3850 WN |
3009 | } |
3010 | ||
3011 | module_init(dw_mci_init); | |
3012 | module_exit(dw_mci_exit); | |
3013 | ||
3014 | MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); | |
3015 | MODULE_AUTHOR("NXP Semiconductor VietNam"); | |
3016 | MODULE_AUTHOR("Imagination Technologies Ltd"); | |
3017 | MODULE_LICENSE("GPL v2"); |