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mmc: dw_mmc: Cleanup the DTO timer like the CTO one
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
b6d2d81c 22#include <linux/iopoll.h>
f95f3850
WN		 23#include <linux/ioport.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
a6db2c86 26#include <linux/pm_runtime.h>
f95f3850
WN		 27#include <linux/seq_file.h>
28#include <linux/slab.h>
29#include <linux/stat.h>
30#include <linux/delay.h>
31#include <linux/irq.h>
b24c8b26 32#include <linux/mmc/card.h>
f95f3850
WN		 33#include <linux/mmc/host.h>
34#include <linux/mmc/mmc.h>
01730558 35#include <linux/mmc/sd.h>
90c2143a 36#include <linux/mmc/sdio.h>
f95f3850 37#include <linux/bitops.h>
c07946a3 38#include <linux/regulator/consumer.h>
c91eab4b 39#include <linux/of.h>
55a6ceb2 40#include <linux/of_gpio.h>
bf626e55 41#include <linux/mmc/slot-gpio.h>
f95f3850
WN		 42
43#include "dw_mmc.h"
44
45/* Common flag combinations */
3f7eec62 46#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
f95f3850 47 SDMMC_INT_HTO | SDMMC_INT_SBE | \
7a3c5677 48 SDMMC_INT_EBE | SDMMC_INT_HLE)
f95f3850 49#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
7a3c5677 50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
f95f3850 51#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
7a3c5677 52 DW_MCI_CMD_ERROR_FLAGS)
f95f3850
WN		 53#define DW_MCI_SEND_STATUS 1
54#define DW_MCI_RECV_STATUS 2
55#define DW_MCI_DMA_THRESHOLD 16
56
1f44a2a5 57#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
72e83577 58#define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
1f44a2a5 59
fc79a4d6
JS		 60#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
cc190d4c
SL		 65#define DESC_RING_BUF_SZ PAGE_SIZE
66
69d99fdc
PT		 67struct idmac_desc_64addr {
68 u32 des0; /* Control Descriptor */
b6d2d81c
SL		 69#define IDMAC_OWN_CLR64(x) \
70 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
69d99fdc
PT		 71
72 u32 des1; /* Reserved */
73
74 u32 des2; /*Buffer sizes */
75#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
6687c42f
BD		 76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
69d99fdc
PT		 78
79 u32 des3; /* Reserved */
80
81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
83
84 u32 des6; /* Lower 32-bits of Next Descriptor Address */
85 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86};
87
f95f3850 88struct idmac_desc {
6687c42f 89 __le32 des0; /* Control Descriptor */
f95f3850
WN		 90#define IDMAC_DES0_DIC BIT(1)
91#define IDMAC_DES0_LD BIT(2)
92#define IDMAC_DES0_FD BIT(3)
93#define IDMAC_DES0_CH BIT(4)
94#define IDMAC_DES0_ER BIT(5)
95#define IDMAC_DES0_CES BIT(30)
96#define IDMAC_DES0_OWN BIT(31)
97
6687c42f 98 __le32 des1; /* Buffer sizes */
f95f3850 99#define IDMAC_SET_BUFFER1_SIZE(d, s) \
e5306c3a 100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
f95f3850 101
6687c42f 102 __le32 des2; /* buffer 1 physical address */
f95f3850 103
6687c42f 104 __le32 des3; /* buffer 2 physical address */
f95f3850 105};
5959b32e
AB		 106
107/* Each descriptor can transfer up to 4KB of data in chained mode */
108#define DW_MCI_DESC_DATA_LENGTH 0x1000
f95f3850 109
f95f3850
WN		 110#if defined(CONFIG_DEBUG_FS)
111static int dw_mci_req_show(struct seq_file *s, void *v)
112{
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
118
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
121 mrq = slot->mrq;
122
123 if (mrq) {
124 cmd = mrq->cmd;
125 data = mrq->data;
126 stop = mrq->stop;
127
128 if (cmd)
129 seq_printf(s,
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
134 if (data)
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
138 if (stop)
139 seq_printf(s,
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
144 }
145
146 spin_unlock_bh(&slot->host->lock);
147
148 return 0;
149}
150
151static int dw_mci_req_open(struct inode *inode, struct file *file)
152{
153 return single_open(file, dw_mci_req_show, inode->i_private);
154}
155
156static const struct file_operations dw_mci_req_fops = {
157 .owner = THIS_MODULE,
158 .open = dw_mci_req_open,
159 .read = seq_read,
160 .llseek = seq_lseek,
161 .release = single_release,
162};
163
164static int dw_mci_regs_show(struct seq_file *s, void *v)
165{
21657ebd
JC		 166 struct dw_mci *host = s->private;
167
168 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
169 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
170 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
171 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
172 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
173 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
f95f3850
WN		 174
175 return 0;
176}
177
178static int dw_mci_regs_open(struct inode *inode, struct file *file)
179{
180 return single_open(file, dw_mci_regs_show, inode->i_private);
181}
182
183static const struct file_operations dw_mci_regs_fops = {
184 .owner = THIS_MODULE,
185 .open = dw_mci_regs_open,
186 .read = seq_read,
187 .llseek = seq_lseek,
188 .release = single_release,
189};
190
191static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
192{
193 struct mmc_host *mmc = slot->mmc;
194 struct dw_mci *host = slot->host;
195 struct dentry *root;
196 struct dentry *node;
197
198 root = mmc->debugfs_root;
199 if (!root)
200 return;
201
202 node = debugfs_create_file("regs", S_IRUSR, root, host,
203 &dw_mci_regs_fops);
204 if (!node)
205 goto err;
206
207 node = debugfs_create_file("req", S_IRUSR, root, slot,
208 &dw_mci_req_fops);
209 if (!node)
210 goto err;
211
212 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
213 if (!node)
214 goto err;
215
216 node = debugfs_create_x32("pending_events", S_IRUSR, root,
217 (u32 *)&host->pending_events);
218 if (!node)
219 goto err;
220
221 node = debugfs_create_x32("completed_events", S_IRUSR, root,
222 (u32 *)&host->completed_events);
223 if (!node)
224 goto err;
225
226 return;
227
228err:
229 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
230}
231#endif /* defined(CONFIG_DEBUG_FS) */
232
8e6db1f6
SL		 233static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
234{
235 u32 ctrl;
236
237 ctrl = mci_readl(host, CTRL);
238 ctrl |= reset;
239 mci_writel(host, CTRL, ctrl);
240
241 /* wait till resets clear */
242 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
243 !(ctrl & reset),
244 1, 500 * USEC_PER_MSEC)) {
245 dev_err(host->dev,
246 "Timeout resetting block (ctrl reset %#x)\n",
247 ctrl & reset);
248 return false;
249 }
250
251 return true;
252}
01730558 253
4dba18de
SL		 254static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
255{
256 u32 status;
257
258 /*
259 * Databook says that before issuing a new data transfer command
260 * we need to check to see if the card is busy. Data transfer commands
261 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
262 *
263 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
264 * expected.
265 */
266 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
267 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
268 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
269 status,
270 !(status & SDMMC_STATUS_BUSY),
271 10, 500 * USEC_PER_MSEC))
272 dev_err(host->dev, "Busy; trying anyway\n");
273 }
274}
275
276static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
277{
278 struct dw_mci *host = slot->host;
279 unsigned int cmd_status = 0;
280
281 mci_writel(host, CMDARG, arg);
282 wmb(); /* drain writebuffer */
283 dw_mci_wait_while_busy(host, cmd);
284 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
285
286 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
287 !(cmd_status & SDMMC_CMD_START),
288 1, 500 * USEC_PER_MSEC))
289 dev_err(&slot->mmc->class_dev,
290 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
291 cmd, arg, cmd_status);
292}
293
f95f3850
WN		 294static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
295{
800d78bf 296 struct dw_mci_slot *slot = mmc_priv(mmc);
01730558 297 struct dw_mci *host = slot->host;
f95f3850 298 u32 cmdr;
f95f3850 299
0e3a22c0 300 cmd->error = -EINPROGRESS;
f95f3850
WN		 301 cmdr = cmd->opcode;
302
90c2143a
SJ		 303 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
304 cmd->opcode == MMC_GO_IDLE_STATE ||
305 cmd->opcode == MMC_GO_INACTIVE_STATE ||
306 (cmd->opcode == SD_IO_RW_DIRECT &&
307 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
f95f3850 308 cmdr |= SDMMC_CMD_STOP;
4a1b27ad
JC		 309 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
310 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
f95f3850 311
01730558
DA		 312 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
313 u32 clk_en_a;
314
315 /* Special bit makes CMD11 not die */
316 cmdr |= SDMMC_CMD_VOLT_SWITCH;
317
318 /* Change state to continue to handle CMD11 weirdness */
319 WARN_ON(slot->host->state != STATE_SENDING_CMD);
320 slot->host->state = STATE_SENDING_CMD11;
321
322 /*
323 * We need to disable low power mode (automatic clock stop)
324 * while doing voltage switch so we don't confuse the card,
325 * since stopping the clock is a specific part of the UHS
326 * voltage change dance.
327 *
328 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
329 * unconditionally turned back on in dw_mci_setup_bus() if it's
330 * ever called with a non-zero clock. That shouldn't happen
331 * until the voltage change is all done.
332 */
333 clk_en_a = mci_readl(host, CLKENA);
334 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
335 mci_writel(host, CLKENA, clk_en_a);
336 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
337 SDMMC_CMD_PRV_DAT_WAIT, 0);
338 }
339
f95f3850
WN		 340 if (cmd->flags & MMC_RSP_PRESENT) {
341 /* We expect a response, so set this bit */
342 cmdr |= SDMMC_CMD_RESP_EXP;
343 if (cmd->flags & MMC_RSP_136)
344 cmdr |= SDMMC_CMD_RESP_LONG;
345 }
346
347 if (cmd->flags & MMC_RSP_CRC)
348 cmdr |= SDMMC_CMD_RESP_CRC;
349
0349c085 350 if (cmd->data) {
f95f3850 351 cmdr |= SDMMC_CMD_DAT_EXP;
0349c085 352 if (cmd->data->flags & MMC_DATA_WRITE)
f95f3850
WN		 353 cmdr |= SDMMC_CMD_DAT_WR;
354 }
355
aaaaeb7a
JC		 356 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
357 cmdr |= SDMMC_CMD_USE_HOLD_REG;
800d78bf 358
f95f3850
WN		 359 return cmdr;
360}
361
90c2143a
SJ		 362static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
363{
364 struct mmc_command *stop;
365 u32 cmdr;
366
367 if (!cmd->data)
368 return 0;
369
370 stop = &host->stop_abort;
371 cmdr = cmd->opcode;
372 memset(stop, 0, sizeof(struct mmc_command));
373
374 if (cmdr == MMC_READ_SINGLE_BLOCK ||
375 cmdr == MMC_READ_MULTIPLE_BLOCK ||
376 cmdr == MMC_WRITE_BLOCK ||
6c2c6506
UH		 377 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
378 cmdr == MMC_SEND_TUNING_BLOCK ||
379 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
90c2143a
SJ		 380 stop->opcode = MMC_STOP_TRANSMISSION;
381 stop->arg = 0;
382 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
383 } else if (cmdr == SD_IO_RW_EXTENDED) {
384 stop->opcode = SD_IO_RW_DIRECT;
385 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
386 ((cmd->arg >> 28) & 0x7);
387 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
388 } else {
389 return 0;
390 }
391
392 cmdr = stop->opcode | SDMMC_CMD_STOP |
393 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
394
42f989c0 395 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
8c005b40
JC		 396 cmdr |= SDMMC_CMD_USE_HOLD_REG;
397
90c2143a
SJ		 398 return cmdr;
399}
400
03de1921
AK		 401static inline void dw_mci_set_cto(struct dw_mci *host)
402{
403 unsigned int cto_clks;
4c2357f5 404 unsigned int cto_div;
03de1921 405 unsigned int cto_ms;
8892b705 406 unsigned long irqflags;
03de1921
AK		 407
408 cto_clks = mci_readl(host, TMOUT) & 0xff;
4c2357f5
DA		 409 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
410 if (cto_div == 0)
411 cto_div = 1;
412 cto_ms = DIV_ROUND_UP(MSEC_PER_SEC * cto_clks * cto_div, host->bus_hz);
03de1921
AK		 413
414 /* add a bit spare time */
415 cto_ms += 10;
416
8892b705
DA		 417 /*
418 * The durations we're working with are fairly short so we have to be
419 * extra careful about synchronization here. Specifically in hardware a
420 * command timeout is _at most_ 5.1 ms, so that means we expect an
421 * interrupt (either command done or timeout) to come rather quickly
422 * after the mci_writel. ...but just in case we have a long interrupt
423 * latency let's add a bit of paranoia.
424 *
425 * In general we'll assume that at least an interrupt will be asserted
426 * in hardware by the time the cto_timer runs. ...and if it hasn't
427 * been asserted in hardware by that time then we'll assume it'll never
428 * come.
429 */
430 spin_lock_irqsave(&host->irq_lock, irqflags);
431 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
432 mod_timer(&host->cto_timer,
433 jiffies + msecs_to_jiffies(cto_ms) + 1);
434 spin_unlock_irqrestore(&host->irq_lock, irqflags);
03de1921
AK		 435}
436
f95f3850
WN		 437static void dw_mci_start_command(struct dw_mci *host,
438 struct mmc_command *cmd, u32 cmd_flags)
439{
440 host->cmd = cmd;
4a90920c 441 dev_vdbg(host->dev,
f95f3850
WN		 442 "start command: ARGR=0x%08x CMDR=0x%08x\n",
443 cmd->arg, cmd_flags);
444
445 mci_writel(host, CMDARG, cmd->arg);
0e3a22c0 446 wmb(); /* drain writebuffer */
0bdbd0e8 447 dw_mci_wait_while_busy(host, cmd_flags);
f95f3850 448
8892b705
DA		 449 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
450
03de1921
AK		 451 /* response expected command only */
452 if (cmd_flags & SDMMC_CMD_RESP_EXP)
453 dw_mci_set_cto(host);
f95f3850
WN		 454}
455
90c2143a 456static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
f95f3850 457{
e13c3c08 458 struct mmc_command *stop = &host->stop_abort;
0e3a22c0 459
90c2143a 460 dw_mci_start_command(host, stop, host->stop_cmdr);
f95f3850
WN		 461}
462
463/* DMA interface functions */
464static void dw_mci_stop_dma(struct dw_mci *host)
465{
03e8cb53 466 if (host->using_dma) {
f95f3850
WN		 467 host->dma_ops->stop(host);
468 host->dma_ops->cleanup(host);
f95f3850 469 }
aa50f259
SJ		 470
471 /* Data transfer was stopped by the interrupt handler */
472 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
f95f3850
WN		 473}
474
f95f3850
WN		 475static void dw_mci_dma_cleanup(struct dw_mci *host)
476{
477 struct mmc_data *data = host->data;
478
a4cc7eb4
JC		 479 if (data && data->host_cookie == COOKIE_MAPPED) {
480 dma_unmap_sg(host->dev,
481 data->sg,
482 data->sg_len,
feeef096 483 mmc_get_dma_dir(data));
a4cc7eb4
JC		 484 data->host_cookie = COOKIE_UNMAPPED;
485 }
f95f3850
WN		 486}
487
5ce9d961
SJ		 488static void dw_mci_idmac_reset(struct dw_mci *host)
489{
490 u32 bmod = mci_readl(host, BMOD);
491 /* Software reset of DMA */
492 bmod |= SDMMC_IDMAC_SWRESET;
493 mci_writel(host, BMOD, bmod);
494}
495
f95f3850
WN		 496static void dw_mci_idmac_stop_dma(struct dw_mci *host)
497{
498 u32 temp;
499
500 /* Disable and reset the IDMAC interface */
501 temp = mci_readl(host, CTRL);
502 temp &= ~SDMMC_CTRL_USE_IDMAC;
503 temp |= SDMMC_CTRL_DMA_RESET;
504 mci_writel(host, CTRL, temp);
505
506 /* Stop the IDMAC running */
507 temp = mci_readl(host, BMOD);
a5289a43 508 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
5ce9d961 509 temp |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 510 mci_writel(host, BMOD, temp);
511}
512
3fc7eaef 513static void dw_mci_dmac_complete_dma(void *arg)
f95f3850 514{
3fc7eaef 515 struct dw_mci *host = arg;
f95f3850
WN		 516 struct mmc_data *data = host->data;
517
4a90920c 518 dev_vdbg(host->dev, "DMA complete\n");
f95f3850 519
3fc7eaef
SL		 520 if ((host->use_dma == TRANS_MODE_EDMAC) &&
521 data && (data->flags & MMC_DATA_READ))
522 /* Invalidate cache after read */
42f989c0 523 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
3fc7eaef
SL		 524 data->sg,
525 data->sg_len,
526 DMA_FROM_DEVICE);
527
f95f3850
WN		 528 host->dma_ops->cleanup(host);
529
530 /*
531 * If the card was removed, data will be NULL. No point in trying to
532 * send the stop command or waiting for NBUSY in this case.
533 */
534 if (data) {
535 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
536 tasklet_schedule(&host->tasklet);
537 }
538}
539
3b2a067b
SL		 540static int dw_mci_idmac_init(struct dw_mci *host)
541{
542 int i;
543
544 if (host->dma_64bit_address == 1) {
545 struct idmac_desc_64addr *p;
546 /* Number of descriptors in the ring buffer */
cc190d4c
SL		 547 host->ring_size =
548 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
3b2a067b
SL		 549
550 /* Forward link the descriptor list */
551 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
552 i++, p++) {
553 p->des6 = (host->sg_dma +
554 (sizeof(struct idmac_desc_64addr) *
555 (i + 1))) & 0xffffffff;
556
557 p->des7 = (u64)(host->sg_dma +
558 (sizeof(struct idmac_desc_64addr) *
559 (i + 1))) >> 32;
560 /* Initialize reserved and buffer size fields to "0" */
561 p->des1 = 0;
562 p->des2 = 0;
563 p->des3 = 0;
564 }
565
566 /* Set the last descriptor as the end-of-ring descriptor */
567 p->des6 = host->sg_dma & 0xffffffff;
568 p->des7 = (u64)host->sg_dma >> 32;
569 p->des0 = IDMAC_DES0_ER;
570
571 } else {
572 struct idmac_desc *p;
573 /* Number of descriptors in the ring buffer */
cc190d4c
SL		 574 host->ring_size =
575 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
3b2a067b
SL		 576
577 /* Forward link the descriptor list */
578 for (i = 0, p = host->sg_cpu;
579 i < host->ring_size - 1;
580 i++, p++) {
581 p->des3 = cpu_to_le32(host->sg_dma +
582 (sizeof(struct idmac_desc) * (i + 1)));
583 p->des1 = 0;
584 }
585
586 /* Set the last descriptor as the end-of-ring descriptor */
587 p->des3 = cpu_to_le32(host->sg_dma);
588 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
589 }
590
591 dw_mci_idmac_reset(host);
592
593 if (host->dma_64bit_address == 1) {
594 /* Mask out interrupts - get Tx & Rx complete only */
595 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
596 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
597 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
598
599 /* Set the descriptor base address */
600 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
601 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
602
603 } else {
604 /* Mask out interrupts - get Tx & Rx complete only */
605 mci_writel(host, IDSTS, IDMAC_INT_CLR);
606 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
607 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
608
609 /* Set the descriptor base address */
610 mci_writel(host, DBADDR, host->sg_dma);
611 }
612
613 return 0;
614}
615
616static inline int dw_mci_prepare_desc64(struct dw_mci *host,
ec0baaa6
SL		 617 struct mmc_data *data,
618 unsigned int sg_len)
f95f3850 619{
5959b32e 620 unsigned int desc_len;
ec0baaa6 621 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
b6d2d81c 622 u32 val;
f95f3850 623 int i;
0e3a22c0 624
ec0baaa6 625 desc_first = desc_last = desc = host->sg_cpu;
5959b32e 626
ec0baaa6
SL		 627 for (i = 0; i < sg_len; i++) {
628 unsigned int length = sg_dma_len(&data->sg[i]);
69d99fdc 629
ec0baaa6 630 u64 mem_addr = sg_dma_address(&data->sg[i]);
0e3a22c0 631
ec0baaa6
SL		 632 for ( ; length ; desc++) {
633 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
634 length : DW_MCI_DESC_DATA_LENGTH;
f95f3850 635
ec0baaa6 636 length -= desc_len;
5959b32e 637
3b2a067b
SL		 638 /*
639 * Wait for the former clear OWN bit operation
640 * of IDMAC to make sure that this descriptor
641 * isn't still owned by IDMAC as IDMAC's write
642 * ops and CPU's read ops are asynchronous.
643 */
b6d2d81c
SL		 644 if (readl_poll_timeout_atomic(&desc->des0, val,
645 !(val & IDMAC_DES0_OWN),
646 10, 100 * USEC_PER_MSEC))
647 goto err_own_bit;
3b2a067b 648
ec0baaa6
SL		 649 /*
650 * Set the OWN bit and disable interrupts
651 * for this descriptor
652 */
653 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
654 IDMAC_DES0_CH;
5959b32e 655
ec0baaa6
SL		 656 /* Buffer length */
657 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
5959b32e 658
ec0baaa6
SL		 659 /* Physical address to DMA to/from */
660 desc->des4 = mem_addr & 0xffffffff;
661 desc->des5 = mem_addr >> 32;
5959b32e 662
ec0baaa6
SL		 663 /* Update physical address for the next desc */
664 mem_addr += desc_len;
5959b32e 665
ec0baaa6
SL		 666 /* Save pointer to the last descriptor */
667 desc_last = desc;
69d99fdc 668 }
ec0baaa6 669 }
f95f3850 670
ec0baaa6
SL		 671 /* Set first descriptor */
672 desc_first->des0 |= IDMAC_DES0_FD;
f95f3850 673
ec0baaa6
SL		 674 /* Set last descriptor */
675 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
676 desc_last->des0 |= IDMAC_DES0_LD;
3b2a067b
SL		 677
678 return 0;
679err_own_bit:
680 /* restore the descriptor chain as it's polluted */
26be9d70 681 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
cc190d4c 682 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
3b2a067b
SL		 683 dw_mci_idmac_init(host);
684 return -EINVAL;
ec0baaa6 685}
5959b32e 686
69d99fdc 687
3b2a067b 688static inline int dw_mci_prepare_desc32(struct dw_mci *host,
ec0baaa6
SL		 689 struct mmc_data *data,
690 unsigned int sg_len)
691{
692 unsigned int desc_len;
693 struct idmac_desc *desc_first, *desc_last, *desc;
b6d2d81c 694 u32 val;
ec0baaa6 695 int i;
0e3a22c0 696
ec0baaa6 697 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 698
ec0baaa6
SL		 699 for (i = 0; i < sg_len; i++) {
700 unsigned int length = sg_dma_len(&data->sg[i]);
5959b32e 701
ec0baaa6 702 u32 mem_addr = sg_dma_address(&data->sg[i]);
5959b32e 703
ec0baaa6
SL		 704 for ( ; length ; desc++) {
705 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
706 length : DW_MCI_DESC_DATA_LENGTH;
5959b32e 707
ec0baaa6 708 length -= desc_len;
f95f3850 709
3b2a067b
SL		 710 /*
711 * Wait for the former clear OWN bit operation
712 * of IDMAC to make sure that this descriptor
713 * isn't still owned by IDMAC as IDMAC's write
714 * ops and CPU's read ops are asynchronous.
715 */
b6d2d81c
SL		 716 if (readl_poll_timeout_atomic(&desc->des0, val,
717 IDMAC_OWN_CLR64(val),
718 10,
719 100 * USEC_PER_MSEC))
720 goto err_own_bit;
3b2a067b 721
ec0baaa6
SL		 722 /*
723 * Set the OWN bit and disable interrupts
724 * for this descriptor
725 */
726 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
727 IDMAC_DES0_DIC |
728 IDMAC_DES0_CH);
5959b32e 729
ec0baaa6
SL		 730 /* Buffer length */
731 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
5959b32e 732
ec0baaa6
SL		 733 /* Physical address to DMA to/from */
734 desc->des2 = cpu_to_le32(mem_addr);
69d99fdc 735
ec0baaa6
SL		 736 /* Update physical address for the next desc */
737 mem_addr += desc_len;
f95f3850 738
ec0baaa6
SL		 739 /* Save pointer to the last descriptor */
740 desc_last = desc;
741 }
69d99fdc 742 }
f95f3850 743
ec0baaa6
SL		 744 /* Set first descriptor */
745 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
746
747 /* Set last descriptor */
748 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
749 IDMAC_DES0_DIC));
750 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
3b2a067b
SL		 751
752 return 0;
753err_own_bit:
754 /* restore the descriptor chain as it's polluted */
26be9d70 755 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
cc190d4c 756 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
3b2a067b
SL		 757 dw_mci_idmac_init(host);
758 return -EINVAL;
f95f3850
WN		 759}
760
3fc7eaef 761static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
f95f3850
WN		 762{
763 u32 temp;
3b2a067b 764 int ret;
f95f3850 765
ec0baaa6 766 if (host->dma_64bit_address == 1)
3b2a067b 767 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
ec0baaa6 768 else
3b2a067b
SL		 769 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
770
771 if (ret)
772 goto out;
ec0baaa6
SL		 773
774 /* drain writebuffer */
775 wmb();
f95f3850 776
536f6b91
SR		 777 /* Make sure to reset DMA in case we did PIO before this */
778 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
779 dw_mci_idmac_reset(host);
780
f95f3850
WN		 781 /* Select IDMAC interface */
782 temp = mci_readl(host, CTRL);
783 temp |= SDMMC_CTRL_USE_IDMAC;
784 mci_writel(host, CTRL, temp);
785
0e3a22c0 786 /* drain writebuffer */
f95f3850
WN		 787 wmb();
788
789 /* Enable the IDMAC */
790 temp = mci_readl(host, BMOD);
a5289a43 791 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 792 mci_writel(host, BMOD, temp);
793
794 /* Start it running */
795 mci_writel(host, PLDMND, 1);
3fc7eaef 796
3b2a067b
SL		 797out:
798 return ret;
f95f3850
WN		 799}
800
8e2b36ea 801static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 802 .init = dw_mci_idmac_init,
803 .start = dw_mci_idmac_start_dma,
804 .stop = dw_mci_idmac_stop_dma,
3fc7eaef
SL		 805 .complete = dw_mci_dmac_complete_dma,
806 .cleanup = dw_mci_dma_cleanup,
807};
808
809static void dw_mci_edmac_stop_dma(struct dw_mci *host)
810{
ab925a31 811 dmaengine_terminate_async(host->dms->ch);
3fc7eaef
SL		 812}
813
814static int dw_mci_edmac_start_dma(struct dw_mci *host,
815 unsigned int sg_len)
816{
817 struct dma_slave_config cfg;
818 struct dma_async_tx_descriptor *desc = NULL;
819 struct scatterlist *sgl = host->data->sg;
27d70d36 820 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
3fc7eaef
SL		 821 u32 sg_elems = host->data->sg_len;
822 u32 fifoth_val;
823 u32 fifo_offset = host->fifo_reg - host->regs;
824 int ret = 0;
825
826 /* Set external dma config: burst size, burst width */
260b3164 827 cfg.dst_addr = host->phy_regs + fifo_offset;
3fc7eaef
SL		 828 cfg.src_addr = cfg.dst_addr;
829 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
830 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
831
832 /* Match burst msize with external dma config */
833 fifoth_val = mci_readl(host, FIFOTH);
834 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
835 cfg.src_maxburst = cfg.dst_maxburst;
836
837 if (host->data->flags & MMC_DATA_WRITE)
838 cfg.direction = DMA_MEM_TO_DEV;
839 else
840 cfg.direction = DMA_DEV_TO_MEM;
841
842 ret = dmaengine_slave_config(host->dms->ch, &cfg);
843 if (ret) {
844 dev_err(host->dev, "Failed to config edmac.\n");
845 return -EBUSY;
846 }
847
848 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
849 sg_len, cfg.direction,
850 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
851 if (!desc) {
852 dev_err(host->dev, "Can't prepare slave sg.\n");
853 return -EBUSY;
854 }
855
856 /* Set dw_mci_dmac_complete_dma as callback */
857 desc->callback = dw_mci_dmac_complete_dma;
858 desc->callback_param = (void *)host;
859 dmaengine_submit(desc);
860
861 /* Flush cache before write */
862 if (host->data->flags & MMC_DATA_WRITE)
42f989c0 863 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
3fc7eaef
SL		 864 sg_elems, DMA_TO_DEVICE);
865
866 dma_async_issue_pending(host->dms->ch);
867
868 return 0;
869}
870
871static int dw_mci_edmac_init(struct dw_mci *host)
872{
873 /* Request external dma channel */
874 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
875 if (!host->dms)
876 return -ENOMEM;
877
878 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
879 if (!host->dms->ch) {
4539d36e 880 dev_err(host->dev, "Failed to get external DMA channel.\n");
3fc7eaef
SL		 881 kfree(host->dms);
882 host->dms = NULL;
883 return -ENXIO;
884 }
885
886 return 0;
887}
888
889static void dw_mci_edmac_exit(struct dw_mci *host)
890{
891 if (host->dms) {
892 if (host->dms->ch) {
893 dma_release_channel(host->dms->ch);
894 host->dms->ch = NULL;
895 }
896 kfree(host->dms);
897 host->dms = NULL;
898 }
899}
900
901static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
902 .init = dw_mci_edmac_init,
903 .exit = dw_mci_edmac_exit,
904 .start = dw_mci_edmac_start_dma,
905 .stop = dw_mci_edmac_stop_dma,
906 .complete = dw_mci_dmac_complete_dma,
885c3e80
SJ		 907 .cleanup = dw_mci_dma_cleanup,
908};
885c3e80 909
9aa51408
SJ		 910static int dw_mci_pre_dma_transfer(struct dw_mci *host,
911 struct mmc_data *data,
a4cc7eb4 912 int cookie)
f95f3850
WN		 913{
914 struct scatterlist *sg;
9aa51408 915 unsigned int i, sg_len;
03e8cb53 916
a4cc7eb4
JC		 917 if (data->host_cookie == COOKIE_PRE_MAPPED)
918 return data->sg_len;
f95f3850
WN		 919
920 /*
921 * We don't do DMA on "complex" transfers, i.e. with
922 * non-word-aligned buffers or lengths. Also, we don't bother
923 * with all the DMA setup overhead for short transfers.
924 */
925 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
926 return -EINVAL;
9aa51408 927
f95f3850
WN		 928 if (data->blksz & 3)
929 return -EINVAL;
930
931 for_each_sg(data->sg, sg, data->sg_len, i) {
932 if (sg->offset & 3 || sg->length & 3)
933 return -EINVAL;
934 }
935
4a90920c 936 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 937 data->sg,
938 data->sg_len,
feeef096 939 mmc_get_dma_dir(data));
9aa51408
SJ		 940 if (sg_len == 0)
941 return -EINVAL;
03e8cb53 942
a4cc7eb4 943 data->host_cookie = cookie;
f95f3850 944
9aa51408
SJ		 945 return sg_len;
946}
947
9aa51408 948static void dw_mci_pre_req(struct mmc_host *mmc,
d3c6aac3 949 struct mmc_request *mrq)
9aa51408
SJ		 950{
951 struct dw_mci_slot *slot = mmc_priv(mmc);
952 struct mmc_data *data = mrq->data;
953
954 if (!slot->host->use_dma || !data)
955 return;
956
a4cc7eb4
JC		 957 /* This data might be unmapped at this time */
958 data->host_cookie = COOKIE_UNMAPPED;
9aa51408 959
a4cc7eb4
JC		 960 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
961 COOKIE_PRE_MAPPED) < 0)
962 data->host_cookie = COOKIE_UNMAPPED;
9aa51408
SJ		 963}
964
965static void dw_mci_post_req(struct mmc_host *mmc,
966 struct mmc_request *mrq,
967 int err)
968{
969 struct dw_mci_slot *slot = mmc_priv(mmc);
970 struct mmc_data *data = mrq->data;
971
972 if (!slot->host->use_dma || !data)
973 return;
974
a4cc7eb4 975 if (data->host_cookie != COOKIE_UNMAPPED)
4a90920c 976 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 977 data->sg,
978 data->sg_len,
feeef096 979 mmc_get_dma_dir(data));
a4cc7eb4 980 data->host_cookie = COOKIE_UNMAPPED;
9aa51408
SJ		 981}
982
671fa142
SL		 983static int dw_mci_get_cd(struct mmc_host *mmc)
984{
985 int present;
986 struct dw_mci_slot *slot = mmc_priv(mmc);
987 struct dw_mci *host = slot->host;
988 int gpio_cd = mmc_gpio_get_cd(mmc);
989
990 /* Use platform get_cd function, else try onboard card detect */
991 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
992 || !mmc_card_is_removable(mmc))) {
993 present = 1;
994
995 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
996 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
997 dev_info(&mmc->class_dev,
998 "card is polling.\n");
999 } else {
1000 dev_info(&mmc->class_dev,
1001 "card is non-removable.\n");
1002 }
1003 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1004 }
1005
1006 return present;
1007 } else if (gpio_cd >= 0)
1008 present = gpio_cd;
1009 else
1010 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1011 == 0 ? 1 : 0;
1012
1013 spin_lock_bh(&host->lock);
1014 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1015 dev_dbg(&mmc->class_dev, "card is present\n");
1016 else if (!present &&
1017 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1018 dev_dbg(&mmc->class_dev, "card is not present\n");
1019 spin_unlock_bh(&host->lock);
1020
1021 return present;
1022}
1023
52426899
SJ		 1024static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
1025{
52426899 1026 unsigned int blksz = data->blksz;
27d70d36 1027 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
52426899
SJ		 1028 u32 fifo_width = 1 << host->data_shift;
1029 u32 blksz_depth = blksz / fifo_width, fifoth_val;
1030 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
0e3a22c0 1031 int idx = ARRAY_SIZE(mszs) - 1;
52426899 1032
3fc7eaef
SL		 1033 /* pio should ship this scenario */
1034 if (!host->use_dma)
1035 return;
1036
52426899
SJ		 1037 tx_wmark = (host->fifo_depth) / 2;
1038 tx_wmark_invers = host->fifo_depth - tx_wmark;
1039
1040 /*
1041 * MSIZE is '1',
1042 * if blksz is not a multiple of the FIFO width
1043 */
20753569 1044 if (blksz % fifo_width)
52426899 1045 goto done;
52426899
SJ		 1046
1047 do {
1048 if (!((blksz_depth % mszs[idx]) ||
1049 (tx_wmark_invers % mszs[idx]))) {
1050 msize = idx;
1051 rx_wmark = mszs[idx] - 1;
1052 break;
1053 }
1054 } while (--idx > 0);
1055 /*
1056 * If idx is '0', it won't be tried
1057 * Thus, initial values are uesed
1058 */
1059done:
1060 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1061 mci_writel(host, FIFOTH, fifoth_val);
52426899
SJ		 1062}
1063
7e4bf1bc 1064static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
f1d2736c
SJ		 1065{
1066 unsigned int blksz = data->blksz;
1067 u32 blksz_depth, fifo_depth;
1068 u16 thld_size;
7e4bf1bc 1069 u8 enable;
f1d2736c 1070
66dfd101
JH		 1071 /*
1072 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1073 * in the FIFO region, so we really shouldn't access it).
1074 */
7e4bf1bc
JC		 1075 if (host->verid < DW_MMC_240A ||
1076 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1077 return;
1078
1079 /*
1080 * Card write Threshold is introduced since 2.80a
1081 * It's used when HS400 mode is enabled.
1082 */
1083 if (data->flags & MMC_DATA_WRITE &&
1084 !(host->timing != MMC_TIMING_MMC_HS400))
66dfd101
JH		 1085 return;
1086
7e4bf1bc
JC		 1087 if (data->flags & MMC_DATA_WRITE)
1088 enable = SDMMC_CARD_WR_THR_EN;
1089 else
1090 enable = SDMMC_CARD_RD_THR_EN;
1091
f1d2736c
SJ		 1092 if (host->timing != MMC_TIMING_MMC_HS200 &&
1093 host->timing != MMC_TIMING_UHS_SDR104)
1094 goto disable;
1095
1096 blksz_depth = blksz / (1 << host->data_shift);
1097 fifo_depth = host->fifo_depth;
1098
1099 if (blksz_depth > fifo_depth)
1100 goto disable;
1101
1102 /*
1103 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1104 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1105 * Currently just choose blksz.
1106 */
1107 thld_size = blksz;
7e4bf1bc 1108 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
f1d2736c
SJ		 1109 return;
1110
1111disable:
7e4bf1bc 1112 mci_writel(host, CDTHRCTL, 0);
f1d2736c
SJ		 1113}
1114
9aa51408
SJ		 1115static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1116{
f8c58c11 1117 unsigned long irqflags;
9aa51408
SJ		 1118 int sg_len;
1119 u32 temp;
1120
1121 host->using_dma = 0;
1122
1123 /* If we don't have a channel, we can't do DMA */
1124 if (!host->use_dma)
1125 return -ENODEV;
1126
a4cc7eb4 1127 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
a99aa9b9
SJ		 1128 if (sg_len < 0) {
1129 host->dma_ops->stop(host);
9aa51408 1130 return sg_len;
a99aa9b9 1131 }
9aa51408
SJ		 1132
1133 host->using_dma = 1;
f95f3850 1134
3fc7eaef
SL		 1135 if (host->use_dma == TRANS_MODE_IDMAC)
1136 dev_vdbg(host->dev,
1137 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1138 (unsigned long)host->sg_cpu,
1139 (unsigned long)host->sg_dma,
1140 sg_len);
f95f3850 1141
52426899
SJ		 1142 /*
1143 * Decide the MSIZE and RX/TX Watermark.
1144 * If current block size is same with previous size,
1145 * no need to update fifoth.
1146 */
1147 if (host->prev_blksz != data->blksz)
1148 dw_mci_adjust_fifoth(host, data);
1149
f95f3850
WN		 1150 /* Enable the DMA interface */
1151 temp = mci_readl(host, CTRL);
1152 temp |= SDMMC_CTRL_DMA_ENABLE;
1153 mci_writel(host, CTRL, temp);
1154
1155 /* Disable RX/TX IRQs, let DMA handle it */
f8c58c11 1156 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1157 temp = mci_readl(host, INTMASK);
1158 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1159 mci_writel(host, INTMASK, temp);
f8c58c11 1160 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850 1161
3fc7eaef 1162 if (host->dma_ops->start(host, sg_len)) {
647f80a1 1163 host->dma_ops->stop(host);
d12d0cb1
SL		 1164 /* We can't do DMA, try PIO for this one */
1165 dev_dbg(host->dev,
1166 "%s: fall back to PIO mode for current transfer\n",
1167 __func__);
3fc7eaef
SL		 1168 return -ENODEV;
1169 }
f95f3850
WN		 1170
1171 return 0;
1172}
1173
1174static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1175{
f8c58c11 1176 unsigned long irqflags;
0e3a22c0 1177 int flags = SG_MITER_ATOMIC;
f95f3850
WN		 1178 u32 temp;
1179
1180 data->error = -EINPROGRESS;
1181
1182 WARN_ON(host->data);
1183 host->sg = NULL;
1184 host->data = data;
1185
7e4bf1bc 1186 if (data->flags & MMC_DATA_READ)
55c5efbc 1187 host->dir_status = DW_MCI_RECV_STATUS;
7e4bf1bc 1188 else
55c5efbc 1189 host->dir_status = DW_MCI_SEND_STATUS;
7e4bf1bc
JC		 1190
1191 dw_mci_ctrl_thld(host, data);
55c5efbc 1192
f95f3850 1193 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 1194 if (host->data->flags & MMC_DATA_READ)
1195 flags |= SG_MITER_TO_SG;
1196 else
1197 flags |= SG_MITER_FROM_SG;
1198
1199 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 1200 host->sg = data->sg;
34b664a2
JH		 1201 host->part_buf_start = 0;
1202 host->part_buf_count = 0;
f95f3850 1203
b40af3aa 1204 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f8c58c11
DA		 1205
1206 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1207 temp = mci_readl(host, INTMASK);
1208 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1209 mci_writel(host, INTMASK, temp);
f8c58c11 1210 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 1211
1212 temp = mci_readl(host, CTRL);
1213 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1214 mci_writel(host, CTRL, temp);
52426899
SJ		 1215
1216 /*
d6fced83
JN		 1217 * Use the initial fifoth_val for PIO mode. If wm_algined
1218 * is set, we set watermark same as data size.
52426899
SJ		 1219 * If next issued data may be transfered by DMA mode,
1220 * prev_blksz should be invalidated.
1221 */
d6fced83
JN		 1222 if (host->wm_aligned)
1223 dw_mci_adjust_fifoth(host, data);
1224 else
1225 mci_writel(host, FIFOTH, host->fifoth_val);
52426899
SJ		 1226 host->prev_blksz = 0;
1227 } else {
1228 /*
1229 * Keep the current block size.
1230 * It will be used to decide whether to update
1231 * fifoth register next time.
1232 */
1233 host->prev_blksz = data->blksz;
f95f3850
WN		 1234 }
1235}
1236
ab269128 1237static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 1238{
1239 struct dw_mci *host = slot->host;
fdf492a1 1240 unsigned int clock = slot->clock;
f95f3850 1241 u32 div;
9623b5b9 1242 u32 clk_en_a;
01730558
DA		 1243 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1244
1245 /* We must continue to set bit 28 in CMD until the change is complete */
1246 if (host->state == STATE_WAITING_CMD11_DONE)
1247 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
f95f3850 1248
fdf492a1
DA		 1249 if (!clock) {
1250 mci_writel(host, CLKENA, 0);
01730558 1251 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
fdf492a1
DA		 1252 } else if (clock != host->current_speed || force_clkinit) {
1253 div = host->bus_hz / clock;
1254 if (host->bus_hz % clock && host->bus_hz > clock)
f95f3850
WN		 1255 /*
1256 * move the + 1 after the divide to prevent
1257 * over-clocking the card.
1258 */
e419990b
SJ		 1259 div += 1;
1260
fdf492a1 1261 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850 1262
e6cd7a8e
JC		 1263 if ((clock != slot->__clk_old &&
1264 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1265 force_clkinit) {
ce69e2fe
SL		 1266 /* Silent the verbose log if calling from PM context */
1267 if (!force_clkinit)
1268 dev_info(&slot->mmc->class_dev,
1269 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1270 slot->id, host->bus_hz, clock,
1271 div ? ((host->bus_hz / div) >> 1) :
1272 host->bus_hz, div);
f95f3850 1273
e6cd7a8e
JC		 1274 /*
1275 * If card is polling, display the message only
1276 * one time at boot time.
1277 */
1278 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1279 slot->mmc->f_min == clock)
1280 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1281 }
1282
f95f3850
WN		 1283 /* disable clock */
1284 mci_writel(host, CLKENA, 0);
1285 mci_writel(host, CLKSRC, 0);
1286
1287 /* inform CIU */
01730558 1288 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850
WN		 1289
1290 /* set clock to desired speed */
1291 mci_writel(host, CLKDIV, div);
1292
1293 /* inform CIU */
01730558 1294 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1295
9623b5b9
DA		 1296 /* enable clock; only low power if no SDIO */
1297 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
b24c8b26 1298 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
9623b5b9
DA		 1299 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1300 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 1301
1302 /* inform CIU */
01730558 1303 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
005d675a
JC		 1304
1305 /* keep the last clock value that was requested from core */
1306 slot->__clk_old = clock;
f95f3850
WN		 1307 }
1308
fdf492a1
DA		 1309 host->current_speed = clock;
1310
f95f3850 1311 /* Set the current slot bus width */
1d56c453 1312 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 1313}
1314
053b3ce6
SJ		 1315static void __dw_mci_start_request(struct dw_mci *host,
1316 struct dw_mci_slot *slot,
1317 struct mmc_command *cmd)
f95f3850
WN		 1318{
1319 struct mmc_request *mrq;
f95f3850
WN		 1320 struct mmc_data *data;
1321 u32 cmdflags;
1322
1323 mrq = slot->mrq;
f95f3850 1324
f95f3850
WN		 1325 host->mrq = mrq;
1326
1327 host->pending_events = 0;
1328 host->completed_events = 0;
e352c813 1329 host->cmd_status = 0;
f95f3850 1330 host->data_status = 0;
e352c813 1331 host->dir_status = 0;
f95f3850 1332
053b3ce6 1333 data = cmd->data;
f95f3850 1334 if (data) {
f16afa88 1335 mci_writel(host, TMOUT, 0xFFFFFFFF);
f95f3850
WN		 1336 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1337 mci_writel(host, BLKSIZ, data->blksz);
1338 }
1339
f95f3850
WN		 1340 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1341
1342 /* this is the first command, send the initialization clock */
1343 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1344 cmdflags |= SDMMC_CMD_INIT;
1345
1346 if (data) {
1347 dw_mci_submit_data(host, data);
0e3a22c0 1348 wmb(); /* drain writebuffer */
f95f3850
WN		 1349 }
1350
1351 dw_mci_start_command(host, cmd, cmdflags);
1352
5c935165 1353 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
49ba0302
DA		 1354 unsigned long irqflags;
1355
5c935165 1356 /*
8886a6fd
DA		 1357 * Databook says to fail after 2ms w/ no response, but evidence
1358 * shows that sometimes the cmd11 interrupt takes over 130ms.
1359 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1360 * is just about to roll over.
49ba0302
DA		 1361 *
1362 * We do this whole thing under spinlock and only if the
1363 * command hasn't already completed (indicating the the irq
1364 * already ran so we don't want the timeout).
5c935165 1365 */
49ba0302
DA		 1366 spin_lock_irqsave(&host->irq_lock, irqflags);
1367 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1368 mod_timer(&host->cmd11_timer,
1369 jiffies + msecs_to_jiffies(500) + 1);
1370 spin_unlock_irqrestore(&host->irq_lock, irqflags);
5c935165
DA		 1371 }
1372
e13c3c08 1373 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
f95f3850
WN		 1374}
1375
053b3ce6
SJ		 1376static void dw_mci_start_request(struct dw_mci *host,
1377 struct dw_mci_slot *slot)
1378{
1379 struct mmc_request *mrq = slot->mrq;
1380 struct mmc_command *cmd;
1381
1382 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1383 __dw_mci_start_request(host, slot, cmd);
1384}
1385
7456caae 1386/* must be called with host->lock held */
f95f3850
WN		 1387static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1388 struct mmc_request *mrq)
1389{
1390 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1391 host->state);
1392
f95f3850
WN		 1393 slot->mrq = mrq;
1394
01730558
DA		 1395 if (host->state == STATE_WAITING_CMD11_DONE) {
1396 dev_warn(&slot->mmc->class_dev,
1397 "Voltage change didn't complete\n");
1398 /*
1399 * this case isn't expected to happen, so we can
1400 * either crash here or just try to continue on
1401 * in the closest possible state
1402 */
1403 host->state = STATE_IDLE;
1404 }
1405
f95f3850
WN		 1406 if (host->state == STATE_IDLE) {
1407 host->state = STATE_SENDING_CMD;
1408 dw_mci_start_request(host, slot);
1409 } else {
1410 list_add_tail(&slot->queue_node, &host->queue);
1411 }
f95f3850
WN		 1412}
1413
1414static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1415{
1416 struct dw_mci_slot *slot = mmc_priv(mmc);
1417 struct dw_mci *host = slot->host;
1418
1419 WARN_ON(slot->mrq);
1420
7456caae
JH		 1421 /*
1422 * The check for card presence and queueing of the request must be
1423 * atomic, otherwise the card could be removed in between and the
1424 * request wouldn't fail until another card was inserted.
1425 */
7456caae 1426
56f6911c 1427 if (!dw_mci_get_cd(mmc)) {
f95f3850
WN		 1428 mrq->cmd->error = -ENOMEDIUM;
1429 mmc_request_done(mmc, mrq);
1430 return;
1431 }
1432
56f6911c
SL		 1433 spin_lock_bh(&host->lock);
1434
f95f3850 1435 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 1436
1437 spin_unlock_bh(&host->lock);
f95f3850
WN		 1438}
1439
1440static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1441{
1442 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 1443 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 1444 u32 regs;
51da2240 1445 int ret;
f95f3850 1446
f95f3850 1447 switch (ios->bus_width) {
f95f3850
WN		 1448 case MMC_BUS_WIDTH_4:
1449 slot->ctype = SDMMC_CTYPE_4BIT;
1450 break;
c9b2a06f
JC		 1451 case MMC_BUS_WIDTH_8:
1452 slot->ctype = SDMMC_CTYPE_8BIT;
1453 break;
b2f7cb45
JC		 1454 default:
1455 /* set default 1 bit mode */
1456 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 1457 }
1458
3f514291
SJ		 1459 regs = mci_readl(slot->host, UHS_REG);
1460
41babf75 1461 /* DDR mode set */
80113132 1462 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
7cc8d580 1463 ios->timing == MMC_TIMING_UHS_DDR50 ||
80113132 1464 ios->timing == MMC_TIMING_MMC_HS400)
c69042a5 1465 regs |= ((0x1 << slot->id) << 16);
3f514291 1466 else
c69042a5 1467 regs &= ~((0x1 << slot->id) << 16);
3f514291
SJ		 1468
1469 mci_writel(slot->host, UHS_REG, regs);
f1d2736c 1470 slot->host->timing = ios->timing;
41babf75 1471
fdf492a1
DA		 1472 /*
1473 * Use mirror of ios->clock to prevent race with mmc
1474 * core ios update when finding the minimum.
1475 */
1476 slot->clock = ios->clock;
f95f3850 1477
cb27a843
JH		 1478 if (drv_data && drv_data->set_ios)
1479 drv_data->set_ios(slot->host, ios);
800d78bf 1480
f95f3850
WN		 1481 switch (ios->power_mode) {
1482 case MMC_POWER_UP:
51da2240
YC		 1483 if (!IS_ERR(mmc->supply.vmmc)) {
1484 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1485 ios->vdd);
1486 if (ret) {
1487 dev_err(slot->host->dev,
1488 "failed to enable vmmc regulator\n");
1489 /*return, if failed turn on vmmc*/
1490 return;
1491 }
1492 }
29d0d161
DA		 1493 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1494 regs = mci_readl(slot->host, PWREN);
1495 regs |= (1 << slot->id);
1496 mci_writel(slot->host, PWREN, regs);
1497 break;
1498 case MMC_POWER_ON:
d1f1dd86
DA		 1499 if (!slot->host->vqmmc_enabled) {
1500 if (!IS_ERR(mmc->supply.vqmmc)) {
1501 ret = regulator_enable(mmc->supply.vqmmc);
1502 if (ret < 0)
1503 dev_err(slot->host->dev,
1504 "failed to enable vqmmc\n");
1505 else
1506 slot->host->vqmmc_enabled = true;
1507
1508 } else {
1509 /* Keep track so we don't reset again */
51da2240 1510 slot->host->vqmmc_enabled = true;
d1f1dd86
DA		 1511 }
1512
1513 /* Reset our state machine after powering on */
1514 dw_mci_ctrl_reset(slot->host,
1515 SDMMC_CTRL_ALL_RESET_FLAGS);
51da2240 1516 }
655babbd
DA		 1517
1518 /* Adjust clock / bus width after power is up */
1519 dw_mci_setup_bus(slot, false);
1520
e6f34e2f
JH		 1521 break;
1522 case MMC_POWER_OFF:
655babbd
DA		 1523 /* Turn clock off before power goes down */
1524 dw_mci_setup_bus(slot, false);
1525
51da2240
YC		 1526 if (!IS_ERR(mmc->supply.vmmc))
1527 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1528
d1f1dd86 1529 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
51da2240 1530 regulator_disable(mmc->supply.vqmmc);
d1f1dd86 1531 slot->host->vqmmc_enabled = false;
51da2240 1532
4366dcc5
JC		 1533 regs = mci_readl(slot->host, PWREN);
1534 regs &= ~(1 << slot->id);
1535 mci_writel(slot->host, PWREN, regs);
f95f3850
WN		 1536 break;
1537 default:
1538 break;
1539 }
655babbd
DA		 1540
1541 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1542 slot->host->state = STATE_IDLE;
f95f3850
WN		 1543}
1544
01730558
DA		 1545static int dw_mci_card_busy(struct mmc_host *mmc)
1546{
1547 struct dw_mci_slot *slot = mmc_priv(mmc);
1548 u32 status;
1549
1550 /*
1551 * Check the busy bit which is low when DAT[3:0]
1552 * (the data lines) are 0000
1553 */
1554 status = mci_readl(slot->host, STATUS);
1555
1556 return !!(status & SDMMC_STATUS_BUSY);
1557}
1558
1559static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1560{
1561 struct dw_mci_slot *slot = mmc_priv(mmc);
1562 struct dw_mci *host = slot->host;
8f7849c4 1563 const struct dw_mci_drv_data *drv_data = host->drv_data;
01730558
DA		 1564 u32 uhs;
1565 u32 v18 = SDMMC_UHS_18V << slot->id;
01730558
DA		 1566 int ret;
1567
8f7849c4
ZG		 1568 if (drv_data && drv_data->switch_voltage)
1569 return drv_data->switch_voltage(mmc, ios);
1570
01730558
DA		 1571 /*
1572 * Program the voltage. Note that some instances of dw_mmc may use
1573 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1574 * does no harm but you need to set the regulator directly. Try both.
1575 */
1576 uhs = mci_readl(host, UHS_REG);
e0848f5d 1577 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
01730558 1578 uhs &= ~v18;
e0848f5d 1579 else
01730558 1580 uhs |= v18;
e0848f5d 1581
01730558 1582 if (!IS_ERR(mmc->supply.vqmmc)) {
e0848f5d 1583 ret = mmc_regulator_set_vqmmc(mmc, ios);
01730558
DA		 1584
1585 if (ret) {
b19caf37 1586 dev_dbg(&mmc->class_dev,
e0848f5d
DA		 1587 "Regulator set error %d - %s V\n",
1588 ret, uhs & v18 ? "1.8" : "3.3");
01730558
DA		 1589 return ret;
1590 }
1591 }
1592 mci_writel(host, UHS_REG, uhs);
1593
1594 return 0;
1595}
1596
f95f3850
WN		 1597static int dw_mci_get_ro(struct mmc_host *mmc)
1598{
1599 int read_only;
1600 struct dw_mci_slot *slot = mmc_priv(mmc);
9795a846 1601 int gpio_ro = mmc_gpio_get_ro(mmc);
f95f3850
WN		 1602
1603 /* Use platform get_ro function, else try on board write protect */
287980e4 1604 if (gpio_ro >= 0)
9795a846 1605 read_only = gpio_ro;
f95f3850
WN		 1606 else
1607 read_only =
1608 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1609
1610 dev_dbg(&mmc->class_dev, "card is %s\n",
1611 read_only ? "read-only" : "read-write");
1612
1613 return read_only;
1614}
1615
935a665e
SL		 1616static void dw_mci_hw_reset(struct mmc_host *mmc)
1617{
1618 struct dw_mci_slot *slot = mmc_priv(mmc);
1619 struct dw_mci *host = slot->host;
1620 int reset;
1621
1622 if (host->use_dma == TRANS_MODE_IDMAC)
1623 dw_mci_idmac_reset(host);
1624
1625 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1626 SDMMC_CTRL_FIFO_RESET))
1627 return;
1628
1629 /*
1630 * According to eMMC spec, card reset procedure:
1631 * tRstW >= 1us: RST_n pulse width
1632 * tRSCA >= 200us: RST_n to Command time
1633 * tRSTH >= 1us: RST_n high period
1634 */
1635 reset = mci_readl(host, RST_N);
1636 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1637 mci_writel(host, RST_N, reset);
1638 usleep_range(1, 2);
1639 reset |= SDMMC_RST_HWACTIVE << slot->id;
1640 mci_writel(host, RST_N, reset);
1641 usleep_range(200, 300);
1642}
1643
b24c8b26 1644static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
9623b5b9 1645{
b24c8b26 1646 struct dw_mci_slot *slot = mmc_priv(mmc);
9623b5b9 1647 struct dw_mci *host = slot->host;
9623b5b9 1648
b24c8b26
DA		 1649 /*
1650 * Low power mode will stop the card clock when idle. According to the
1651 * description of the CLKENA register we should disable low power mode
1652 * for SDIO cards if we need SDIO interrupts to work.
1653 */
1654 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1655 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1656 u32 clk_en_a_old;
1657 u32 clk_en_a;
9623b5b9 1658
b24c8b26
DA		 1659 clk_en_a_old = mci_readl(host, CLKENA);
1660
1661 if (card->type == MMC_TYPE_SDIO ||
1662 card->type == MMC_TYPE_SD_COMBO) {
0eebf9b9 1663 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
b24c8b26
DA		 1664 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1665 } else {
0eebf9b9 1666 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
b24c8b26
DA		 1667 clk_en_a = clk_en_a_old | clken_low_pwr;
1668 }
1669
1670 if (clk_en_a != clk_en_a_old) {
1671 mci_writel(host, CLKENA, clk_en_a);
1672 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1673 SDMMC_CMD_PRV_DAT_WAIT, 0);
1674 }
9623b5b9
DA		 1675 }
1676}
1677
32dba737 1678static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1a5c8e1f 1679{
1a5c8e1f 1680 struct dw_mci *host = slot->host;
f8c58c11 1681 unsigned long irqflags;
1a5c8e1f
SH		 1682 u32 int_mask;
1683
f8c58c11
DA		 1684 spin_lock_irqsave(&host->irq_lock, irqflags);
1685
1a5c8e1f
SH		 1686 /* Enable/disable Slot Specific SDIO interrupt */
1687 int_mask = mci_readl(host, INTMASK);
b24c8b26
DA		 1688 if (enb)
1689 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1690 else
1691 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1692 mci_writel(host, INTMASK, int_mask);
f8c58c11
DA		 1693
1694 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1a5c8e1f
SH		 1695}
1696
32dba737
UH		 1697static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1698{
1699 struct dw_mci_slot *slot = mmc_priv(mmc);
ca8971ca 1700 struct dw_mci *host = slot->host;
32dba737
UH		 1701
1702 __dw_mci_enable_sdio_irq(slot, enb);
ca8971ca
UH		 1703
1704 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1705 if (enb)
1706 pm_runtime_get_noresume(host->dev);
1707 else
1708 pm_runtime_put_noidle(host->dev);
32dba737
UH		 1709}
1710
1711static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1712{
1713 struct dw_mci_slot *slot = mmc_priv(mmc);
1714
1715 __dw_mci_enable_sdio_irq(slot, 1);
1716}
1717
0976f16d
SJ		 1718static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1719{
1720 struct dw_mci_slot *slot = mmc_priv(mmc);
1721 struct dw_mci *host = slot->host;
1722 const struct dw_mci_drv_data *drv_data = host->drv_data;
0e3a22c0 1723 int err = -EINVAL;
0976f16d 1724
0976f16d 1725 if (drv_data && drv_data->execute_tuning)
9979dbe5 1726 err = drv_data->execute_tuning(slot, opcode);
0976f16d
SJ		 1727 return err;
1728}
1729
0e3a22c0
SL		 1730static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1731 struct mmc_ios *ios)
80113132
SJ		 1732{
1733 struct dw_mci_slot *slot = mmc_priv(mmc);
1734 struct dw_mci *host = slot->host;
1735 const struct dw_mci_drv_data *drv_data = host->drv_data;
1736
1737 if (drv_data && drv_data->prepare_hs400_tuning)
1738 return drv_data->prepare_hs400_tuning(host, ios);
1739
1740 return 0;
1741}
1742
4e7392b2
SL		 1743static bool dw_mci_reset(struct dw_mci *host)
1744{
1745 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1746 bool ret = false;
bc2dcc1a 1747 u32 status = 0;
4e7392b2
SL		 1748
1749 /*
1750 * Resetting generates a block interrupt, hence setting
1751 * the scatter-gather pointer to NULL.
1752 */
1753 if (host->sg) {
1754 sg_miter_stop(&host->sg_miter);
1755 host->sg = NULL;
1756 }
1757
1758 if (host->use_dma)
1759 flags |= SDMMC_CTRL_DMA_RESET;
1760
1761 if (dw_mci_ctrl_reset(host, flags)) {
1762 /*
bc2dcc1a
SL		 1763 * In all cases we clear the RAWINTS
1764 * register to clear any interrupts.
4e7392b2
SL		 1765 */
1766 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1767
bc2dcc1a
SL		 1768 if (!host->use_dma) {
1769 ret = true;
1770 goto ciu_out;
1771 }
4e7392b2 1772
bc2dcc1a
SL		 1773 /* Wait for dma_req to be cleared */
1774 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1775 status,
1776 !(status & SDMMC_STATUS_DMA_REQ),
1777 1, 500 * USEC_PER_MSEC)) {
1778 dev_err(host->dev,
1779 "%s: Timeout waiting for dma_req to be cleared\n",
1780 __func__);
1781 goto ciu_out;
4e7392b2 1782 }
bc2dcc1a
SL		 1783
1784 /* when using DMA next we reset the fifo again */
1785 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1786 goto ciu_out;
4e7392b2
SL		 1787 } else {
1788 /* if the controller reset bit did clear, then set clock regs */
1789 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1790 dev_err(host->dev,
1791 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1792 __func__);
1793 goto ciu_out;
1794 }
1795 }
1796
1797 if (host->use_dma == TRANS_MODE_IDMAC)
1798 /* It is also recommended that we reset and reprogram idmac */
1799 dw_mci_idmac_reset(host);
1800
1801 ret = true;
1802
1803ciu_out:
1804 /* After a CTRL reset we need to have CIU set clock registers */
42f989c0 1805 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
4e7392b2
SL		 1806
1807 return ret;
1808}
1809
f95f3850 1810static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 1811 .request = dw_mci_request,
9aa51408
SJ		 1812 .pre_req = dw_mci_pre_req,
1813 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 1814 .set_ios = dw_mci_set_ios,
1815 .get_ro = dw_mci_get_ro,
1816 .get_cd = dw_mci_get_cd,
935a665e 1817 .hw_reset = dw_mci_hw_reset,
1a5c8e1f 1818 .enable_sdio_irq = dw_mci_enable_sdio_irq,
32dba737 1819 .ack_sdio_irq = dw_mci_ack_sdio_irq,
0976f16d 1820 .execute_tuning = dw_mci_execute_tuning,
01730558
DA		 1821 .card_busy = dw_mci_card_busy,
1822 .start_signal_voltage_switch = dw_mci_switch_voltage,
b24c8b26 1823 .init_card = dw_mci_init_card,
80113132 1824 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
f95f3850
WN		 1825};
1826
1827static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1828 __releases(&host->lock)
1829 __acquires(&host->lock)
1830{
1831 struct dw_mci_slot *slot;
42f989c0 1832 struct mmc_host *prev_mmc = host->slot->mmc;
f95f3850
WN		 1833
1834 WARN_ON(host->cmd || host->data);
1835
42f989c0 1836 host->slot->mrq = NULL;
f95f3850
WN		 1837 host->mrq = NULL;
1838 if (!list_empty(&host->queue)) {
1839 slot = list_entry(host->queue.next,
1840 struct dw_mci_slot, queue_node);
1841 list_del(&slot->queue_node);
4a90920c 1842 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 1843 mmc_hostname(slot->mmc));
1844 host->state = STATE_SENDING_CMD;
1845 dw_mci_start_request(host, slot);
1846 } else {
4a90920c 1847 dev_vdbg(host->dev, "list empty\n");
01730558
DA		 1848
1849 if (host->state == STATE_SENDING_CMD11)
1850 host->state = STATE_WAITING_CMD11_DONE;
1851 else
1852 host->state = STATE_IDLE;
f95f3850
WN		 1853 }
1854
1855 spin_unlock(&host->lock);
1856 mmc_request_done(prev_mmc, mrq);
1857 spin_lock(&host->lock);
1858}
1859
e352c813 1860static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
f95f3850
WN		 1861{
1862 u32 status = host->cmd_status;
1863
1864 host->cmd_status = 0;
1865
1866 /* Read the response from the card (up to 16 bytes) */
1867 if (cmd->flags & MMC_RSP_PRESENT) {
1868 if (cmd->flags & MMC_RSP_136) {
1869 cmd->resp[3] = mci_readl(host, RESP0);
1870 cmd->resp[2] = mci_readl(host, RESP1);
1871 cmd->resp[1] = mci_readl(host, RESP2);
1872 cmd->resp[0] = mci_readl(host, RESP3);
1873 } else {
1874 cmd->resp[0] = mci_readl(host, RESP0);
1875 cmd->resp[1] = 0;
1876 cmd->resp[2] = 0;
1877 cmd->resp[3] = 0;
1878 }
1879 }
1880
1881 if (status & SDMMC_INT_RTO)
1882 cmd->error = -ETIMEDOUT;
1883 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1884 cmd->error = -EILSEQ;
1885 else if (status & SDMMC_INT_RESP_ERR)
1886 cmd->error = -EIO;
1887 else
1888 cmd->error = 0;
1889
e352c813
SJ		 1890 return cmd->error;
1891}
1892
1893static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1894{
31bff450 1895 u32 status = host->data_status;
e352c813
SJ		 1896
1897 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1898 if (status & SDMMC_INT_DRTO) {
1899 data->error = -ETIMEDOUT;
1900 } else if (status & SDMMC_INT_DCRC) {
1901 data->error = -EILSEQ;
1902 } else if (status & SDMMC_INT_EBE) {
1903 if (host->dir_status ==
1904 DW_MCI_SEND_STATUS) {
1905 /*
1906 * No data CRC status was returned.
1907 * The number of bytes transferred
1908 * will be exaggerated in PIO mode.
1909 */
1910 data->bytes_xfered = 0;
1911 data->error = -ETIMEDOUT;
1912 } else if (host->dir_status ==
1913 DW_MCI_RECV_STATUS) {
e7a1dec1 1914 data->error = -EILSEQ;
e352c813
SJ		 1915 }
1916 } else {
1917 /* SDMMC_INT_SBE is included */
e7a1dec1 1918 data->error = -EILSEQ;
e352c813
SJ		 1919 }
1920
e6cc0123 1921 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
e352c813
SJ		 1922
1923 /*
1924 * After an error, there may be data lingering
31bff450 1925 * in the FIFO
e352c813 1926 */
3a33a94c 1927 dw_mci_reset(host);
e352c813
SJ		 1928 } else {
1929 data->bytes_xfered = data->blocks * data->blksz;
1930 data->error = 0;
1931 }
1932
1933 return data->error;
f95f3850
WN		 1934}
1935
57e10486
AK		 1936static void dw_mci_set_drto(struct dw_mci *host)
1937{
1938 unsigned int drto_clks;
9d9491a7 1939 unsigned int drto_div;
57e10486 1940 unsigned int drto_ms;
93c23ae3 1941 unsigned long irqflags;
57e10486
AK		 1942
1943 drto_clks = mci_readl(host, TMOUT) >> 8;
9d9491a7
DA		 1944 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1945 if (drto_div == 0)
1946 drto_div = 1;
1947 drto_ms = DIV_ROUND_UP(MSEC_PER_SEC * drto_clks * drto_div,
1948 host->bus_hz);
57e10486
AK		 1949
1950 /* add a bit spare time */
1951 drto_ms += 10;
1952
93c23ae3
DA		 1953 spin_lock_irqsave(&host->irq_lock, irqflags);
1954 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1955 mod_timer(&host->dto_timer,
1956 jiffies + msecs_to_jiffies(drto_ms));
1957 spin_unlock_irqrestore(&host->irq_lock, irqflags);
57e10486
AK		 1958}
1959
8892b705
DA		 1960static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1961{
1962 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1963 return false;
1964
1965 /*
1966 * Really be certain that the timer has stopped. This is a bit of
1967 * paranoia and could only really happen if we had really bad
1968 * interrupt latency and the interrupt routine and timeout were
1969 * running concurrently so that the del_timer() in the interrupt
1970 * handler couldn't run.
1971 */
1972 WARN_ON(del_timer_sync(&host->cto_timer));
1973 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1974
1975 return true;
1976}
1977
93c23ae3
DA		 1978static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
1979{
1980 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1981 return false;
1982
1983 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
1984 WARN_ON(del_timer_sync(&host->dto_timer));
1985 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1986
1987 return true;
1988}
1989
f95f3850
WN		 1990static void dw_mci_tasklet_func(unsigned long priv)
1991{
1992 struct dw_mci *host = (struct dw_mci *)priv;
1993 struct mmc_data *data;
1994 struct mmc_command *cmd;
e352c813 1995 struct mmc_request *mrq;
f95f3850
WN		 1996 enum dw_mci_state state;
1997 enum dw_mci_state prev_state;
e352c813 1998 unsigned int err;
f95f3850
WN		 1999
2000 spin_lock(&host->lock);
2001
2002 state = host->state;
2003 data = host->data;
e352c813 2004 mrq = host->mrq;
f95f3850
WN		 2005
2006 do {
2007 prev_state = state;
2008
2009 switch (state) {
2010 case STATE_IDLE:
01730558 2011 case STATE_WAITING_CMD11_DONE:
f95f3850
WN		 2012 break;
2013
01730558 2014 case STATE_SENDING_CMD11:
f95f3850 2015 case STATE_SENDING_CMD:
8892b705 2016 if (!dw_mci_clear_pending_cmd_complete(host))
f95f3850
WN		 2017 break;
2018
2019 cmd = host->cmd;
2020 host->cmd = NULL;
2021 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
e352c813
SJ		 2022 err = dw_mci_command_complete(host, cmd);
2023 if (cmd == mrq->sbc && !err) {
053b3ce6 2024 prev_state = state = STATE_SENDING_CMD;
42f989c0 2025 __dw_mci_start_request(host, host->slot,
e352c813 2026 mrq->cmd);
053b3ce6
SJ		 2027 goto unlock;
2028 }
2029
e352c813 2030 if (cmd->data && err) {
46d17952
DA		 2031 /*
2032 * During UHS tuning sequence, sending the stop
2033 * command after the response CRC error would
2034 * throw the system into a confused state
2035 * causing all future tuning phases to report
2036 * failure.
2037 *
2038 * In such case controller will move into a data
2039 * transfer state after a response error or
2040 * response CRC error. Let's let that finish
2041 * before trying to send a stop, so we'll go to
2042 * STATE_SENDING_DATA.
2043 *
2044 * Although letting the data transfer take place
2045 * will waste a bit of time (we already know
2046 * the command was bad), it can't cause any
2047 * errors since it's possible it would have
2048 * taken place anyway if this tasklet got
2049 * delayed. Allowing the transfer to take place
2050 * avoids races and keeps things simple.
2051 */
2052 if ((err != -ETIMEDOUT) &&
2053 (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
2054 state = STATE_SENDING_DATA;
2055 continue;
2056 }
2057
71abb133 2058 dw_mci_stop_dma(host);
90c2143a
SJ		 2059 send_stop_abort(host, data);
2060 state = STATE_SENDING_STOP;
2061 break;
71abb133
SJ		 2062 }
2063
e352c813
SJ		 2064 if (!cmd->data || err) {
2065 dw_mci_request_end(host, mrq);
f95f3850
WN		 2066 goto unlock;
2067 }
2068
2069 prev_state = state = STATE_SENDING_DATA;
2070 /* fall through */
2071
2072 case STATE_SENDING_DATA:
2aa35465
DA		 2073 /*
2074 * We could get a data error and never a transfer
2075 * complete so we'd better check for it here.
2076 *
2077 * Note that we don't really care if we also got a
2078 * transfer complete; stopping the DMA and sending an
2079 * abort won't hurt.
2080 */
f95f3850
WN		 2081 if (test_and_clear_bit(EVENT_DATA_ERROR,
2082 &host->pending_events)) {
2083 dw_mci_stop_dma(host);
e13c3c08 2084 if (!(host->data_status & (SDMMC_INT_DRTO |
bdb9a90b 2085 SDMMC_INT_EBE)))
2086 send_stop_abort(host, data);
f95f3850
WN		 2087 state = STATE_DATA_ERROR;
2088 break;
2089 }
2090
2091 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
57e10486
AK		 2092 &host->pending_events)) {
2093 /*
2094 * If all data-related interrupts don't come
2095 * within the given time in reading data state.
2096 */
16a34574 2097 if (host->dir_status == DW_MCI_RECV_STATUS)
57e10486 2098 dw_mci_set_drto(host);
f95f3850 2099 break;
57e10486 2100 }
f95f3850
WN		 2101
2102 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2aa35465
DA		 2103
2104 /*
2105 * Handle an EVENT_DATA_ERROR that might have shown up
2106 * before the transfer completed. This might not have
2107 * been caught by the check above because the interrupt
2108 * could have gone off between the previous check and
2109 * the check for transfer complete.
2110 *
2111 * Technically this ought not be needed assuming we
2112 * get a DATA_COMPLETE eventually (we'll notice the
2113 * error and end the request), but it shouldn't hurt.
2114 *
2115 * This has the advantage of sending the stop command.
2116 */
2117 if (test_and_clear_bit(EVENT_DATA_ERROR,
2118 &host->pending_events)) {
2119 dw_mci_stop_dma(host);
e13c3c08 2120 if (!(host->data_status & (SDMMC_INT_DRTO |
bdb9a90b 2121 SDMMC_INT_EBE)))
2122 send_stop_abort(host, data);
2aa35465
DA		 2123 state = STATE_DATA_ERROR;
2124 break;
2125 }
f95f3850 2126 prev_state = state = STATE_DATA_BUSY;
2aa35465 2127
f95f3850
WN		 2128 /* fall through */
2129
2130 case STATE_DATA_BUSY:
93c23ae3 2131 if (!dw_mci_clear_pending_data_complete(host)) {
57e10486
AK		 2132 /*
2133 * If data error interrupt comes but data over
2134 * interrupt doesn't come within the given time.
2135 * in reading data state.
2136 */
16a34574 2137 if (host->dir_status == DW_MCI_RECV_STATUS)
57e10486 2138 dw_mci_set_drto(host);
f95f3850 2139 break;
57e10486 2140 }
f95f3850
WN		 2141
2142 host->data = NULL;
2143 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
e352c813
SJ		 2144 err = dw_mci_data_complete(host, data);
2145
2146 if (!err) {
2147 if (!data->stop || mrq->sbc) {
17c8bc85 2148 if (mrq->sbc && data->stop)
e352c813
SJ		 2149 data->stop->error = 0;
2150 dw_mci_request_end(host, mrq);
2151 goto unlock;
f95f3850 2152 }
f95f3850 2153
e352c813
SJ		 2154 /* stop command for open-ended transfer*/
2155 if (data->stop)
2156 send_stop_abort(host, data);
2aa35465
DA		 2157 } else {
2158 /*
2159 * If we don't have a command complete now we'll
2160 * never get one since we just reset everything;
2161 * better end the request.
2162 *
2163 * If we do have a command complete we'll fall
2164 * through to the SENDING_STOP command and
2165 * everything will be peachy keen.
2166 */
2167 if (!test_bit(EVENT_CMD_COMPLETE,
2168 &host->pending_events)) {
2169 host->cmd = NULL;
2170 dw_mci_request_end(host, mrq);
2171 goto unlock;
2172 }
053b3ce6
SJ		 2173 }
2174
e352c813
SJ		 2175 /*
2176 * If err has non-zero,
2177 * stop-abort command has been already issued.
2178 */
f95f3850 2179 prev_state = state = STATE_SENDING_STOP;
e352c813 2180
f95f3850
WN		 2181 /* fall through */
2182
2183 case STATE_SENDING_STOP:
8892b705 2184 if (!dw_mci_clear_pending_cmd_complete(host))
f95f3850
WN		 2185 break;
2186
71abb133 2187 /* CMD error in data command */
31bff450 2188 if (mrq->cmd->error && mrq->data)
3a33a94c 2189 dw_mci_reset(host);
71abb133 2190
f95f3850 2191 host->cmd = NULL;
71abb133 2192 host->data = NULL;
90c2143a 2193
e13c3c08 2194 if (!mrq->sbc && mrq->stop)
e352c813 2195 dw_mci_command_complete(host, mrq->stop);
90c2143a
SJ		 2196 else
2197 host->cmd_status = 0;
2198
e352c813 2199 dw_mci_request_end(host, mrq);
f95f3850
WN		 2200 goto unlock;
2201
2202 case STATE_DATA_ERROR:
2203 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2204 &host->pending_events))
2205 break;
2206
2207 state = STATE_DATA_BUSY;
2208 break;
2209 }
2210 } while (state != prev_state);
2211
2212 host->state = state;
2213unlock:
2214 spin_unlock(&host->lock);
2215
2216}
2217
34b664a2
JH		 2218/* push final bytes to part_buf, only use during push */
2219static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 2220{
34b664a2
JH		 2221 memcpy((void *)&host->part_buf, buf, cnt);
2222 host->part_buf_count = cnt;
2223}
f95f3850 2224
34b664a2
JH		 2225/* append bytes to part_buf, only use during push */
2226static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2227{
2228 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2229 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2230 host->part_buf_count += cnt;
2231 return cnt;
2232}
f95f3850 2233
34b664a2
JH		 2234/* pull first bytes from part_buf, only use during pull */
2235static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2236{
0e3a22c0 2237 cnt = min_t(int, cnt, host->part_buf_count);
34b664a2
JH		 2238 if (cnt) {
2239 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2240 cnt);
2241 host->part_buf_count -= cnt;
2242 host->part_buf_start += cnt;
f95f3850 2243 }
34b664a2 2244 return cnt;
f95f3850
WN		 2245}
2246
34b664a2
JH		 2247/* pull final bytes from the part_buf, assuming it's just been filled */
2248static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 2249{
34b664a2
JH		 2250 memcpy(buf, &host->part_buf, cnt);
2251 host->part_buf_start = cnt;
2252 host->part_buf_count = (1 << host->data_shift) - cnt;
2253}
f95f3850 2254
34b664a2
JH		 2255static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2256{
cfbeb59c
MC		 2257 struct mmc_data *data = host->data;
2258 int init_cnt = cnt;
2259
34b664a2
JH		 2260 /* try and push anything in the part_buf */
2261 if (unlikely(host->part_buf_count)) {
2262 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2263
34b664a2
JH		 2264 buf += len;
2265 cnt -= len;
cfbeb59c 2266 if (host->part_buf_count == 2) {
76184ac1 2267 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 2268 host->part_buf_count = 0;
2269 }
2270 }
2271#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2272 if (unlikely((unsigned long)buf & 0x1)) {
2273 while (cnt >= 2) {
2274 u16 aligned_buf[64];
2275 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2276 int items = len >> 1;
2277 int i;
2278 /* memcpy from input buffer into aligned buffer */
2279 memcpy(aligned_buf, buf, len);
2280 buf += len;
2281 cnt -= len;
2282 /* push data from aligned buffer into fifo */
2283 for (i = 0; i < items; ++i)
76184ac1 2284 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2285 }
2286 } else
2287#endif
2288 {
2289 u16 *pdata = buf;
0e3a22c0 2290
34b664a2 2291 for (; cnt >= 2; cnt -= 2)
76184ac1 2292 mci_fifo_writew(host->fifo_reg, *pdata++);
34b664a2
JH		 2293 buf = pdata;
2294 }
2295 /* put anything remaining in the part_buf */
2296 if (cnt) {
2297 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2298 /* Push data if we have reached the expected data length */
2299 if ((data->bytes_xfered + init_cnt) ==
2300 (data->blksz * data->blocks))
76184ac1 2301 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 2302 }
2303}
f95f3850 2304
34b664a2
JH		 2305static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2306{
2307#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2308 if (unlikely((unsigned long)buf & 0x1)) {
2309 while (cnt >= 2) {
2310 /* pull data from fifo into aligned buffer */
2311 u16 aligned_buf[64];
2312 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2313 int items = len >> 1;
2314 int i;
0e3a22c0 2315
34b664a2 2316 for (i = 0; i < items; ++i)
76184ac1 2317 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2318 /* memcpy from aligned buffer into output buffer */
2319 memcpy(buf, aligned_buf, len);
2320 buf += len;
2321 cnt -= len;
2322 }
2323 } else
2324#endif
2325 {
2326 u16 *pdata = buf;
0e3a22c0 2327
34b664a2 2328 for (; cnt >= 2; cnt -= 2)
76184ac1 2329 *pdata++ = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2330 buf = pdata;
2331 }
2332 if (cnt) {
76184ac1 2333 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
34b664a2 2334 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2335 }
2336}
2337
2338static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2339{
cfbeb59c
MC		 2340 struct mmc_data *data = host->data;
2341 int init_cnt = cnt;
2342
34b664a2
JH		 2343 /* try and push anything in the part_buf */
2344 if (unlikely(host->part_buf_count)) {
2345 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2346
34b664a2
JH		 2347 buf += len;
2348 cnt -= len;
cfbeb59c 2349 if (host->part_buf_count == 4) {
76184ac1 2350 mci_fifo_writel(host->fifo_reg, host->part_buf32);
34b664a2
JH		 2351 host->part_buf_count = 0;
2352 }
2353 }
2354#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2355 if (unlikely((unsigned long)buf & 0x3)) {
2356 while (cnt >= 4) {
2357 u32 aligned_buf[32];
2358 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2359 int items = len >> 2;
2360 int i;
2361 /* memcpy from input buffer into aligned buffer */
2362 memcpy(aligned_buf, buf, len);
2363 buf += len;
2364 cnt -= len;
2365 /* push data from aligned buffer into fifo */
2366 for (i = 0; i < items; ++i)
76184ac1 2367 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2368 }
2369 } else
2370#endif
2371 {
2372 u32 *pdata = buf;
0e3a22c0 2373
34b664a2 2374 for (; cnt >= 4; cnt -= 4)
76184ac1 2375 mci_fifo_writel(host->fifo_reg, *pdata++);
34b664a2
JH		 2376 buf = pdata;
2377 }
2378 /* put anything remaining in the part_buf */
2379 if (cnt) {
2380 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2381 /* Push data if we have reached the expected data length */
2382 if ((data->bytes_xfered + init_cnt) ==
2383 (data->blksz * data->blocks))
76184ac1 2384 mci_fifo_writel(host->fifo_reg, host->part_buf32);
f95f3850
WN		 2385 }
2386}
2387
2388static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2389{
34b664a2
JH		 2390#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2391 if (unlikely((unsigned long)buf & 0x3)) {
2392 while (cnt >= 4) {
2393 /* pull data from fifo into aligned buffer */
2394 u32 aligned_buf[32];
2395 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2396 int items = len >> 2;
2397 int i;
0e3a22c0 2398
34b664a2 2399 for (i = 0; i < items; ++i)
76184ac1 2400 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2401 /* memcpy from aligned buffer into output buffer */
2402 memcpy(buf, aligned_buf, len);
2403 buf += len;
2404 cnt -= len;
2405 }
2406 } else
2407#endif
2408 {
2409 u32 *pdata = buf;
0e3a22c0 2410
34b664a2 2411 for (; cnt >= 4; cnt -= 4)
76184ac1 2412 *pdata++ = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2413 buf = pdata;
2414 }
2415 if (cnt) {
76184ac1 2416 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
34b664a2 2417 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2418 }
2419}
2420
2421static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2422{
cfbeb59c
MC		 2423 struct mmc_data *data = host->data;
2424 int init_cnt = cnt;
2425
34b664a2
JH		 2426 /* try and push anything in the part_buf */
2427 if (unlikely(host->part_buf_count)) {
2428 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2429
34b664a2
JH		 2430 buf += len;
2431 cnt -= len;
c09fbd74 2432
cfbeb59c 2433 if (host->part_buf_count == 8) {
76184ac1 2434 mci_fifo_writeq(host->fifo_reg, host->part_buf);
34b664a2
JH		 2435 host->part_buf_count = 0;
2436 }
2437 }
2438#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2439 if (unlikely((unsigned long)buf & 0x7)) {
2440 while (cnt >= 8) {
2441 u64 aligned_buf[16];
2442 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2443 int items = len >> 3;
2444 int i;
2445 /* memcpy from input buffer into aligned buffer */
2446 memcpy(aligned_buf, buf, len);
2447 buf += len;
2448 cnt -= len;
2449 /* push data from aligned buffer into fifo */
2450 for (i = 0; i < items; ++i)
76184ac1 2451 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2452 }
2453 } else
2454#endif
2455 {
2456 u64 *pdata = buf;
0e3a22c0 2457
34b664a2 2458 for (; cnt >= 8; cnt -= 8)
76184ac1 2459 mci_fifo_writeq(host->fifo_reg, *pdata++);
34b664a2
JH		 2460 buf = pdata;
2461 }
2462 /* put anything remaining in the part_buf */
2463 if (cnt) {
2464 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2465 /* Push data if we have reached the expected data length */
2466 if ((data->bytes_xfered + init_cnt) ==
2467 (data->blksz * data->blocks))
76184ac1 2468 mci_fifo_writeq(host->fifo_reg, host->part_buf);
f95f3850
WN		 2469 }
2470}
2471
2472static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2473{
34b664a2
JH		 2474#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2475 if (unlikely((unsigned long)buf & 0x7)) {
2476 while (cnt >= 8) {
2477 /* pull data from fifo into aligned buffer */
2478 u64 aligned_buf[16];
2479 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2480 int items = len >> 3;
2481 int i;
0e3a22c0 2482
34b664a2 2483 for (i = 0; i < items; ++i)
76184ac1
BD		 2484 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2485
34b664a2
JH		 2486 /* memcpy from aligned buffer into output buffer */
2487 memcpy(buf, aligned_buf, len);
2488 buf += len;
2489 cnt -= len;
2490 }
2491 } else
2492#endif
2493 {
2494 u64 *pdata = buf;
0e3a22c0 2495
34b664a2 2496 for (; cnt >= 8; cnt -= 8)
76184ac1 2497 *pdata++ = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2498 buf = pdata;
2499 }
2500 if (cnt) {
76184ac1 2501 host->part_buf = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2502 dw_mci_pull_final_bytes(host, buf, cnt);
2503 }
2504}
f95f3850 2505
34b664a2
JH		 2506static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2507{
2508 int len;
f95f3850 2509
34b664a2
JH		 2510 /* get remaining partial bytes */
2511 len = dw_mci_pull_part_bytes(host, buf, cnt);
2512 if (unlikely(len == cnt))
2513 return;
2514 buf += len;
2515 cnt -= len;
2516
2517 /* get the rest of the data */
2518 host->pull_data(host, buf, cnt);
f95f3850
WN		 2519}
2520
87a74d39 2521static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
f95f3850 2522{
f9c2a0dc
SJ		 2523 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2524 void *buf;
2525 unsigned int offset;
f95f3850
WN		 2526 struct mmc_data *data = host->data;
2527 int shift = host->data_shift;
2528 u32 status;
3e4b0d8b 2529 unsigned int len;
f9c2a0dc 2530 unsigned int remain, fcnt;
f95f3850
WN		 2531
2532 do {
f9c2a0dc
SJ		 2533 if (!sg_miter_next(sg_miter))
2534 goto done;
2535
4225fc85 2536 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2537 buf = sg_miter->addr;
2538 remain = sg_miter->length;
2539 offset = 0;
2540
2541 do {
2542 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2543 << shift) + host->part_buf_count;
2544 len = min(remain, fcnt);
2545 if (!len)
2546 break;
34b664a2 2547 dw_mci_pull_data(host, (void *)(buf + offset), len);
3e4b0d8b 2548 data->bytes_xfered += len;
f95f3850 2549 offset += len;
f9c2a0dc
SJ		 2550 remain -= len;
2551 } while (remain);
f95f3850 2552
e74f3a9c 2553 sg_miter->consumed = offset;
f95f3850
WN		 2554 status = mci_readl(host, MINTSTS);
2555 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
87a74d39
KK		 2556 /* if the RXDR is ready read again */
2557 } while ((status & SDMMC_INT_RXDR) ||
2558 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
f9c2a0dc
SJ		 2559
2560 if (!remain) {
2561 if (!sg_miter_next(sg_miter))
2562 goto done;
2563 sg_miter->consumed = 0;
2564 }
2565 sg_miter_stop(sg_miter);
f95f3850
WN		 2566 return;
2567
2568done:
f9c2a0dc
SJ		 2569 sg_miter_stop(sg_miter);
2570 host->sg = NULL;
0e3a22c0 2571 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2572 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2573}
2574
2575static void dw_mci_write_data_pio(struct dw_mci *host)
2576{
f9c2a0dc
SJ		 2577 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2578 void *buf;
2579 unsigned int offset;
f95f3850
WN		 2580 struct mmc_data *data = host->data;
2581 int shift = host->data_shift;
2582 u32 status;
3e4b0d8b 2583 unsigned int len;
f9c2a0dc
SJ		 2584 unsigned int fifo_depth = host->fifo_depth;
2585 unsigned int remain, fcnt;
f95f3850
WN		 2586
2587 do {
f9c2a0dc
SJ		 2588 if (!sg_miter_next(sg_miter))
2589 goto done;
2590
4225fc85 2591 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2592 buf = sg_miter->addr;
2593 remain = sg_miter->length;
2594 offset = 0;
2595
2596 do {
2597 fcnt = ((fifo_depth -
2598 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2599 << shift) - host->part_buf_count;
2600 len = min(remain, fcnt);
2601 if (!len)
2602 break;
f95f3850 2603 host->push_data(host, (void *)(buf + offset), len);
3e4b0d8b 2604 data->bytes_xfered += len;
f95f3850 2605 offset += len;
f9c2a0dc
SJ		 2606 remain -= len;
2607 } while (remain);
f95f3850 2608
e74f3a9c 2609 sg_miter->consumed = offset;
f95f3850
WN		 2610 status = mci_readl(host, MINTSTS);
2611 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 2612 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f9c2a0dc
SJ		 2613
2614 if (!remain) {
2615 if (!sg_miter_next(sg_miter))
2616 goto done;
2617 sg_miter->consumed = 0;
2618 }
2619 sg_miter_stop(sg_miter);
f95f3850
WN		 2620 return;
2621
2622done:
f9c2a0dc
SJ		 2623 sg_miter_stop(sg_miter);
2624 host->sg = NULL;
0e3a22c0 2625 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2626 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2627}
2628
2629static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2630{
0363b12d
DA		 2631 del_timer(&host->cto_timer);
2632
f95f3850
WN		 2633 if (!host->cmd_status)
2634 host->cmd_status = status;
2635
0e3a22c0 2636 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2637
2638 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2639 tasklet_schedule(&host->tasklet);
2640}
2641
6130e7a9
DA		 2642static void dw_mci_handle_cd(struct dw_mci *host)
2643{
b23475fa 2644 struct dw_mci_slot *slot = host->slot;
6130e7a9 2645
58870241
JC		 2646 if (slot->mmc->ops->card_event)
2647 slot->mmc->ops->card_event(slot->mmc);
2648 mmc_detect_change(slot->mmc,
2649 msecs_to_jiffies(host->pdata->detect_delay_ms));
6130e7a9
DA		 2650}
2651
f95f3850
WN		 2652static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2653{
2654 struct dw_mci *host = dev_id;
182c9081 2655 u32 pending;
b23475fa 2656 struct dw_mci_slot *slot = host->slot;
8892b705 2657 unsigned long irqflags;
f95f3850 2658
1fb5f68a
MC		 2659 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2660
476d79f1 2661 if (pending) {
01730558
DA		 2662 /* Check volt switch first, since it can look like an error */
2663 if ((host->state == STATE_SENDING_CMD11) &&
2664 (pending & SDMMC_INT_VOLT_SWITCH)) {
2665 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2666 pending &= ~SDMMC_INT_VOLT_SWITCH;
49ba0302
DA		 2667
2668 /*
2669 * Hold the lock; we know cmd11_timer can't be kicked
2670 * off after the lock is released, so safe to delete.
2671 */
2672 spin_lock_irqsave(&host->irq_lock, irqflags);
01730558 2673 dw_mci_cmd_interrupt(host, pending);
49ba0302
DA		 2674 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2675
2676 del_timer(&host->cmd11_timer);
01730558
DA		 2677 }
2678
f95f3850 2679 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
8892b705
DA		 2680 spin_lock_irqsave(&host->irq_lock, irqflags);
2681
03de1921 2682 del_timer(&host->cto_timer);
f95f3850 2683 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 2684 host->cmd_status = pending;
0e3a22c0 2685 smp_wmb(); /* drain writebuffer */
f95f3850 2686 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
8892b705
DA		 2687
2688 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 2689 }
2690
2691 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2692 /* if there is an error report DATA_ERROR */
2693 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 2694 host->data_status = pending;
0e3a22c0 2695 smp_wmb(); /* drain writebuffer */
f95f3850 2696 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 2697 tasklet_schedule(&host->tasklet);
f95f3850
WN		 2698 }
2699
2700 if (pending & SDMMC_INT_DATA_OVER) {
93c23ae3
DA		 2701 spin_lock_irqsave(&host->irq_lock, irqflags);
2702
16a34574 2703 del_timer(&host->dto_timer);
57e10486 2704
f95f3850
WN		 2705 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2706 if (!host->data_status)
182c9081 2707 host->data_status = pending;
0e3a22c0 2708 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2709 if (host->dir_status == DW_MCI_RECV_STATUS) {
2710 if (host->sg != NULL)
87a74d39 2711 dw_mci_read_data_pio(host, true);
f95f3850
WN		 2712 }
2713 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2714 tasklet_schedule(&host->tasklet);
93c23ae3
DA		 2715
2716 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 2717 }
2718
2719 if (pending & SDMMC_INT_RXDR) {
2720 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 2721 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
87a74d39 2722 dw_mci_read_data_pio(host, false);
f95f3850
WN		 2723 }
2724
2725 if (pending & SDMMC_INT_TXDR) {
2726 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 2727 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 2728 dw_mci_write_data_pio(host);
2729 }
2730
2731 if (pending & SDMMC_INT_CMD_DONE) {
8892b705
DA		 2732 spin_lock_irqsave(&host->irq_lock, irqflags);
2733
f95f3850 2734 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 2735 dw_mci_cmd_interrupt(host, pending);
8892b705
DA		 2736
2737 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 2738 }
2739
2740 if (pending & SDMMC_INT_CD) {
2741 mci_writel(host, RINTSTS, SDMMC_INT_CD);
6130e7a9 2742 dw_mci_handle_cd(host);
f95f3850
WN		 2743 }
2744
58870241
JC		 2745 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2746 mci_writel(host, RINTSTS,
2747 SDMMC_INT_SDIO(slot->sdio_id));
2748 __dw_mci_enable_sdio_irq(slot, 0);
2749 sdio_signal_irq(slot->mmc);
1a5c8e1f
SH		 2750 }
2751
1fb5f68a 2752 }
f95f3850 2753
3fc7eaef
SL		 2754 if (host->use_dma != TRANS_MODE_IDMAC)
2755 return IRQ_HANDLED;
2756
2757 /* Handle IDMA interrupts */
69d99fdc
PT		 2758 if (host->dma_64bit_address == 1) {
2759 pending = mci_readl(host, IDSTS64);
2760 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2761 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2762 SDMMC_IDMAC_INT_RI);
2763 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
faecf411
SL		 2764 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2765 host->dma_ops->complete((void *)host);
69d99fdc
PT		 2766 }
2767 } else {
2768 pending = mci_readl(host, IDSTS);
2769 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2770 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2771 SDMMC_IDMAC_INT_RI);
2772 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
faecf411
SL		 2773 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2774 host->dma_ops->complete((void *)host);
69d99fdc 2775 }
f95f3850 2776 }
f95f3850
WN		 2777
2778 return IRQ_HANDLED;
2779}
2780
e4a65ef7 2781static int dw_mci_init_slot(struct dw_mci *host)
f95f3850
WN		 2782{
2783 struct mmc_host *mmc;
2784 struct dw_mci_slot *slot;
e95baf13 2785 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2786 int ctrl_id, ret;
1f44a2a5 2787 u32 freq[2];
f95f3850 2788
4a90920c 2789 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 2790 if (!mmc)
2791 return -ENOMEM;
2792
2793 slot = mmc_priv(mmc);
e4a65ef7
JC		 2794 slot->id = 0;
2795 slot->sdio_id = host->sdio_id0 + slot->id;
f95f3850
WN		 2796 slot->mmc = mmc;
2797 slot->host = host;
b23475fa 2798 host->slot = slot;
f95f3850
WN		 2799
2800 mmc->ops = &dw_mci_ops;
852ff5fe
DW		 2801 if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2802 freq, 2)) {
1f44a2a5
SJ		 2803 mmc->f_min = DW_MCI_FREQ_MIN;
2804 mmc->f_max = DW_MCI_FREQ_MAX;
2805 } else {
b023030f
JC		 2806 dev_info(host->dev,
2807 "'clock-freq-min-max' property was deprecated.\n");
1f44a2a5
SJ		 2808 mmc->f_min = freq[0];
2809 mmc->f_max = freq[1];
2810 }
f95f3850 2811
51da2240
YC		 2812 /*if there are external regulators, get them*/
2813 ret = mmc_regulator_get_supply(mmc);
0f3a47b8 2814 if (ret)
3cf890fc 2815 goto err_host_allocated;
51da2240
YC		 2816
2817 if (!mmc->ocr_avail)
2818 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
f95f3850 2819
fc3d7720
JC		 2820 if (host->pdata->caps)
2821 mmc->caps = host->pdata->caps;
fc3d7720 2822
6024e166
JC		 2823 /*
2824 * Support MMC_CAP_ERASE by default.
2825 * It needs to use trim/discard/erase commands.
2826 */
2827 mmc->caps |= MMC_CAP_ERASE;
2828
ab269128
AK		 2829 if (host->pdata->pm_caps)
2830 mmc->pm_caps = host->pdata->pm_caps;
2831
800d78bf
TA		 2832 if (host->dev->of_node) {
2833 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2834 if (ctrl_id < 0)
2835 ctrl_id = 0;
2836 } else {
2837 ctrl_id = to_platform_device(host->dev)->id;
2838 }
cb27a843
JH		 2839 if (drv_data && drv_data->caps)
2840 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 2841
4f408cc6
SJ		 2842 if (host->pdata->caps2)
2843 mmc->caps2 = host->pdata->caps2;
4f408cc6 2844
3cf890fc
DA		 2845 ret = mmc_of_parse(mmc);
2846 if (ret)
2847 goto err_host_allocated;
f95f3850 2848
32dba737
UH		 2849 /* Process SDIO IRQs through the sdio_irq_work. */
2850 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2851 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2852
2b708df2 2853 /* Useful defaults if platform data is unset. */
3fc7eaef 2854 if (host->use_dma == TRANS_MODE_IDMAC) {
2b708df2 2855 mmc->max_segs = host->ring_size;
225faf87 2856 mmc->max_blk_size = 65535;
2b708df2
JC		 2857 mmc->max_seg_size = 0x1000;
2858 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2859 mmc->max_blk_count = mmc->max_req_size / 512;
3fc7eaef
SL		 2860 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2861 mmc->max_segs = 64;
225faf87 2862 mmc->max_blk_size = 65535;
3fc7eaef
SL		 2863 mmc->max_blk_count = 65535;
2864 mmc->max_req_size =
2865 mmc->max_blk_size * mmc->max_blk_count;
2866 mmc->max_seg_size = mmc->max_req_size;
f95f3850 2867 } else {
3fc7eaef 2868 /* TRANS_MODE_PIO */
2b708df2 2869 mmc->max_segs = 64;
225faf87 2870 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2b708df2
JC		 2871 mmc->max_blk_count = 512;
2872 mmc->max_req_size = mmc->max_blk_size *
2873 mmc->max_blk_count;
2874 mmc->max_seg_size = mmc->max_req_size;
a39e5746 2875 }
f95f3850 2876
c0834a58 2877 dw_mci_get_cd(mmc);
ae0eb348 2878
0cea529d
JC		 2879 ret = mmc_add_host(mmc);
2880 if (ret)
3cf890fc 2881 goto err_host_allocated;
f95f3850
WN		 2882
2883#if defined(CONFIG_DEBUG_FS)
2884 dw_mci_init_debugfs(slot);
2885#endif
2886
f95f3850 2887 return 0;
800d78bf 2888
3cf890fc 2889err_host_allocated:
800d78bf 2890 mmc_free_host(mmc);
51da2240 2891 return ret;
f95f3850
WN		 2892}
2893
e4a65ef7 2894static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
f95f3850 2895{
f95f3850
WN		 2896 /* Debugfs stuff is cleaned up by mmc core */
2897 mmc_remove_host(slot->mmc);
b23475fa 2898 slot->host->slot = NULL;
f95f3850
WN		 2899 mmc_free_host(slot->mmc);
2900}
2901
2902static void dw_mci_init_dma(struct dw_mci *host)
2903{
69d99fdc 2904 int addr_config;
3fc7eaef 2905 struct device *dev = host->dev;
69d99fdc 2906
3fc7eaef
SL		 2907 /*
2908 * Check tansfer mode from HCON[17:16]
2909 * Clear the ambiguous description of dw_mmc databook:
2910 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2911 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2912 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2913 * 2b'11: Non DW DMA Interface -> pio only
2914 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2915 * simpler request/acknowledge handshake mechanism and both of them
2916 * are regarded as external dma master for dw_mmc.
2917 */
2918 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2919 if (host->use_dma == DMA_INTERFACE_IDMA) {
2920 host->use_dma = TRANS_MODE_IDMAC;
2921 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2922 host->use_dma == DMA_INTERFACE_GDMA) {
2923 host->use_dma = TRANS_MODE_EDMAC;
2924 } else {
f95f3850
WN		 2925 goto no_dma;
2926 }
2927
2928 /* Determine which DMA interface to use */
3fc7eaef
SL		 2929 if (host->use_dma == TRANS_MODE_IDMAC) {
2930 /*
2931 * Check ADDR_CONFIG bit in HCON to find
2932 * IDMAC address bus width
2933 */
70692752 2934 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
3fc7eaef
SL		 2935
2936 if (addr_config == 1) {
2937 /* host supports IDMAC in 64-bit address mode */
2938 host->dma_64bit_address = 1;
2939 dev_info(host->dev,
2940 "IDMAC supports 64-bit address mode.\n");
2941 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2942 dma_set_coherent_mask(host->dev,
2943 DMA_BIT_MASK(64));
2944 } else {
2945 /* host supports IDMAC in 32-bit address mode */
2946 host->dma_64bit_address = 0;
2947 dev_info(host->dev,
2948 "IDMAC supports 32-bit address mode.\n");
2949 }
f95f3850 2950
3fc7eaef 2951 /* Alloc memory for sg translation */
cc190d4c
SL		 2952 host->sg_cpu = dmam_alloc_coherent(host->dev,
2953 DESC_RING_BUF_SZ,
3fc7eaef
SL		 2954 &host->sg_dma, GFP_KERNEL);
2955 if (!host->sg_cpu) {
2956 dev_err(host->dev,
2957 "%s: could not alloc DMA memory\n",
2958 __func__);
2959 goto no_dma;
2960 }
2961
2962 host->dma_ops = &dw_mci_idmac_ops;
2963 dev_info(host->dev, "Using internal DMA controller.\n");
2964 } else {
2965 /* TRANS_MODE_EDMAC: check dma bindings again */
852ff5fe
DW		 2966 if ((device_property_read_string_array(dev, "dma-names",
2967 NULL, 0) < 0) ||
2968 !device_property_present(dev, "dmas")) {
3fc7eaef
SL		 2969 goto no_dma;
2970 }
2971 host->dma_ops = &dw_mci_edmac_ops;
2972 dev_info(host->dev, "Using external DMA controller.\n");
2973 }
f95f3850 2974
e1631f98
JC		 2975 if (host->dma_ops->init && host->dma_ops->start &&
2976 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 2977 if (host->dma_ops->init(host)) {
0e3a22c0
SL		 2978 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2979 __func__);
f95f3850
WN		 2980 goto no_dma;
2981 }
2982 } else {
4a90920c 2983 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 2984 goto no_dma;
2985 }
2986
f95f3850
WN		 2987 return;
2988
2989no_dma:
4a90920c 2990 dev_info(host->dev, "Using PIO mode.\n");
3fc7eaef 2991 host->use_dma = TRANS_MODE_PIO;
f95f3850
WN		 2992}
2993
5c935165
DA		 2994static void dw_mci_cmd11_timer(unsigned long arg)
2995{
2996 struct dw_mci *host = (struct dw_mci *)arg;
2997
fd674198
DA		 2998 if (host->state != STATE_SENDING_CMD11) {
2999 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
3000 return;
3001 }
5c935165
DA		 3002
3003 host->cmd_status = SDMMC_INT_RTO;
3004 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3005 tasklet_schedule(&host->tasklet);
3006}
3007
03de1921
AK		 3008static void dw_mci_cto_timer(unsigned long arg)
3009{
3010 struct dw_mci *host = (struct dw_mci *)arg;
8892b705
DA		 3011 unsigned long irqflags;
3012 u32 pending;
03de1921 3013
8892b705 3014 spin_lock_irqsave(&host->irq_lock, irqflags);
03de1921 3015
8892b705
DA		 3016 /*
3017 * If somehow we have very bad interrupt latency it's remotely possible
3018 * that the timer could fire while the interrupt is still pending or
3019 * while the interrupt is midway through running. Let's be paranoid
3020 * and detect those two cases. Note that this is paranoia is somewhat
3021 * justified because in this function we don't actually cancel the
3022 * pending command in the controller--we just assume it will never come.
3023 */
3024 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3025 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3026 /* The interrupt should fire; no need to act but we can warn */
3027 dev_warn(host->dev, "Unexpected interrupt latency\n");
3028 goto exit;
3029 }
3030 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3031 /* Presumably interrupt handler couldn't delete the timer */
3032 dev_warn(host->dev, "CTO timeout when already completed\n");
3033 goto exit;
3034 }
3035
3036 /*
3037 * Continued paranoia to make sure we're in the state we expect.
3038 * This paranoia isn't really justified but it seems good to be safe.
3039 */
03de1921
AK		 3040 switch (host->state) {
3041 case STATE_SENDING_CMD11:
3042 case STATE_SENDING_CMD:
3043 case STATE_SENDING_STOP:
3044 /*
3045 * If CMD_DONE interrupt does NOT come in sending command
3046 * state, we should notify the driver to terminate current
3047 * transfer and report a command timeout to the core.
3048 */
3049 host->cmd_status = SDMMC_INT_RTO;
3050 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3051 tasklet_schedule(&host->tasklet);
3052 break;
3053 default:
3054 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3055 host->state);
3056 break;
3057 }
8892b705
DA		 3058
3059exit:
3060 spin_unlock_irqrestore(&host->irq_lock, irqflags);
03de1921
AK		 3061}
3062
57e10486
AK		 3063static void dw_mci_dto_timer(unsigned long arg)
3064{
3065 struct dw_mci *host = (struct dw_mci *)arg;
93c23ae3
DA		 3066 unsigned long irqflags;
3067 u32 pending;
3068
3069 spin_lock_irqsave(&host->irq_lock, irqflags);
57e10486 3070
93c23ae3
DA		 3071 /*
3072 * The DTO timer is much longer than the CTO timer, so it's even less
3073 * likely that we'll these cases, but it pays to be paranoid.
3074 */
3075 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3076 if (pending & SDMMC_INT_DATA_OVER) {
3077 /* The interrupt should fire; no need to act but we can warn */
3078 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3079 goto exit;
3080 }
3081 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3082 /* Presumably interrupt handler couldn't delete the timer */
3083 dev_warn(host->dev, "DTO timeout when already completed\n");
3084 goto exit;
3085 }
3086
3087 /*
3088 * Continued paranoia to make sure we're in the state we expect.
3089 * This paranoia isn't really justified but it seems good to be safe.
3090 */
57e10486
AK		 3091 switch (host->state) {
3092 case STATE_SENDING_DATA:
3093 case STATE_DATA_BUSY:
3094 /*
3095 * If DTO interrupt does NOT come in sending data state,
3096 * we should notify the driver to terminate current transfer
3097 * and report a data timeout to the core.
3098 */
3099 host->data_status = SDMMC_INT_DRTO;
3100 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3101 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3102 tasklet_schedule(&host->tasklet);
3103 break;
3104 default:
93c23ae3
DA		 3105 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3106 host->state);
57e10486
AK		 3107 break;
3108 }
93c23ae3
DA		 3109
3110exit:
3111 spin_unlock_irqrestore(&host->irq_lock, irqflags);
57e10486
AK		 3112}
3113
c91eab4b 3114#ifdef CONFIG_OF
c91eab4b
TA		 3115static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3116{
3117 struct dw_mci_board *pdata;
3118 struct device *dev = host->dev;
e95baf13 3119 const struct dw_mci_drv_data *drv_data = host->drv_data;
e8cc37b8 3120 int ret;
3c6d89ea 3121 u32 clock_frequency;
c91eab4b
TA		 3122
3123 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
bf3707ea 3124 if (!pdata)
c91eab4b 3125 return ERR_PTR(-ENOMEM);
c91eab4b 3126
d6786fef 3127 /* find reset controller when exist */
a93d6f31 3128 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
d6786fef
GX		 3129 if (IS_ERR(pdata->rstc)) {
3130 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
3131 return ERR_PTR(-EPROBE_DEFER);
3132 }
3133
c91eab4b 3134 /* find out number of slots supported */
16f5df8b 3135 if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots))
d30a8f7b 3136 dev_info(dev, "'num-slots' was deprecated.\n");
c91eab4b 3137
852ff5fe 3138 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
0e3a22c0
SL		 3139 dev_info(dev,
3140 "fifo-depth property not found, using value of FIFOTH register as default\n");
c91eab4b 3141
852ff5fe
DW		 3142 device_property_read_u32(dev, "card-detect-delay",
3143 &pdata->detect_delay_ms);
c91eab4b 3144
852ff5fe 3145 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
a0361c1a 3146
852ff5fe 3147 if (device_property_present(dev, "fifo-watermark-aligned"))
d6fced83
JN		 3148 host->wm_aligned = true;
3149
852ff5fe 3150 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3c6d89ea
DA		 3151 pdata->bus_hz = clock_frequency;
3152
cb27a843
JH		 3153 if (drv_data && drv_data->parse_dt) {
3154 ret = drv_data->parse_dt(host);
800d78bf
TA		 3155 if (ret)
3156 return ERR_PTR(ret);
3157 }
3158
c91eab4b
TA		 3159 return pdata;
3160}
3161
3162#else /* CONFIG_OF */
3163static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3164{
3165 return ERR_PTR(-EINVAL);
3166}
3167#endif /* CONFIG_OF */
3168
fa0c3283
DA		 3169static void dw_mci_enable_cd(struct dw_mci *host)
3170{
fa0c3283
DA		 3171 unsigned long irqflags;
3172 u32 temp;
fa0c3283 3173
e8cc37b8
SL		 3174 /*
3175 * No need for CD if all slots have a non-error GPIO
3176 * as well as broken card detection is found.
3177 */
e47c0b96 3178 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
fa0c3283
DA		 3179 return;
3180
e47c0b96 3181 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
58870241
JC		 3182 spin_lock_irqsave(&host->irq_lock, irqflags);
3183 temp = mci_readl(host, INTMASK);
3184 temp |= SDMMC_INT_CD;
3185 mci_writel(host, INTMASK, temp);
3186 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3187 }
fa0c3283
DA		 3188}
3189
62ca8034 3190int dw_mci_probe(struct dw_mci *host)
f95f3850 3191{
e95baf13 3192 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 3193 int width, i, ret = 0;
f95f3850
WN		 3194 u32 fifo_size;
3195
c91eab4b
TA		 3196 if (!host->pdata) {
3197 host->pdata = dw_mci_parse_dt(host);
d6786fef
GX		 3198 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3199 return -EPROBE_DEFER;
3200 } else if (IS_ERR(host->pdata)) {
c91eab4b
TA		 3201 dev_err(host->dev, "platform data not available\n");
3202 return -EINVAL;
3203 }
f95f3850
WN		 3204 }
3205
780f22af 3206 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 3207 if (IS_ERR(host->biu_clk)) {
3208 dev_dbg(host->dev, "biu clock not available\n");
3209 } else {
3210 ret = clk_prepare_enable(host->biu_clk);
3211 if (ret) {
3212 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 3213 return ret;
3214 }
3215 }
3216
780f22af 3217 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 3218 if (IS_ERR(host->ciu_clk)) {
3219 dev_dbg(host->dev, "ciu clock not available\n");
3c6d89ea 3220 host->bus_hz = host->pdata->bus_hz;
f90a0612
TA		 3221 } else {
3222 ret = clk_prepare_enable(host->ciu_clk);
3223 if (ret) {
3224 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 3225 goto err_clk_biu;
3226 }
f90a0612 3227
3c6d89ea
DA		 3228 if (host->pdata->bus_hz) {
3229 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3230 if (ret)
3231 dev_warn(host->dev,
612de4c1 3232 "Unable to set bus rate to %uHz\n",
3c6d89ea
DA		 3233 host->pdata->bus_hz);
3234 }
f90a0612 3235 host->bus_hz = clk_get_rate(host->ciu_clk);
3c6d89ea 3236 }
f90a0612 3237
612de4c1
JC		 3238 if (!host->bus_hz) {
3239 dev_err(host->dev,
3240 "Platform data must supply bus speed\n");
3241 ret = -ENODEV;
3242 goto err_clk_ciu;
3243 }
3244
941e372d 3245 if (!IS_ERR(host->pdata->rstc)) {
3246 reset_control_assert(host->pdata->rstc);
3247 usleep_range(10, 50);
3248 reset_control_deassert(host->pdata->rstc);
3249 }
3250
002f0d5c
YK		 3251 if (drv_data && drv_data->init) {
3252 ret = drv_data->init(host);
3253 if (ret) {
3254 dev_err(host->dev,
3255 "implementation specific init failed\n");
3256 goto err_clk_ciu;
3257 }
3258 }
3259
5c935165
DA		 3260 setup_timer(&host->cmd11_timer,
3261 dw_mci_cmd11_timer, (unsigned long)host);
3262
03de1921
AK		 3263 setup_timer(&host->cto_timer,
3264 dw_mci_cto_timer, (unsigned long)host);
3265
16a34574
JC		 3266 setup_timer(&host->dto_timer,
3267 dw_mci_dto_timer, (unsigned long)host);
57e10486 3268
f95f3850 3269 spin_lock_init(&host->lock);
f8c58c11 3270 spin_lock_init(&host->irq_lock);
f95f3850
WN		 3271 INIT_LIST_HEAD(&host->queue);
3272
f95f3850
WN		 3273 /*
3274 * Get the host data width - this assumes that HCON has been set with
3275 * the correct values.
3276 */
70692752 3277 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
f95f3850
WN		 3278 if (!i) {
3279 host->push_data = dw_mci_push_data16;
3280 host->pull_data = dw_mci_pull_data16;
3281 width = 16;
3282 host->data_shift = 1;
3283 } else if (i == 2) {
3284 host->push_data = dw_mci_push_data64;
3285 host->pull_data = dw_mci_pull_data64;
3286 width = 64;
3287 host->data_shift = 3;
3288 } else {
3289 /* Check for a reserved value, and warn if it is */
3290 WARN((i != 1),
3291 "HCON reports a reserved host data width!\n"
3292 "Defaulting to 32-bit access.\n");
3293 host->push_data = dw_mci_push_data32;
3294 host->pull_data = dw_mci_pull_data32;
3295 width = 32;
3296 host->data_shift = 2;
3297 }
3298
3299 /* Reset all blocks */
3744415c
SL		 3300 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3301 ret = -ENODEV;
3302 goto err_clk_ciu;
3303 }
141a712a
SJ		 3304
3305 host->dma_ops = host->pdata->dma_ops;
3306 dw_mci_init_dma(host);
f95f3850
WN		 3307
3308 /* Clear the interrupts for the host controller */
3309 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3310 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3311
3312 /* Put in max timeout */
3313 mci_writel(host, TMOUT, 0xFFFFFFFF);
3314
3315 /*
3316 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3317 * Tx Mark = fifo_size / 2 DMA Size = 8
3318 */
b86d8253
JH		 3319 if (!host->pdata->fifo_depth) {
3320 /*
3321 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3322 * have been overwritten by the bootloader, just like we're
3323 * about to do, so if you know the value for your hardware, you
3324 * should put it in the platform data.
3325 */
3326 fifo_size = mci_readl(host, FIFOTH);
8234e869 3327 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 3328 } else {
3329 fifo_size = host->pdata->fifo_depth;
3330 }
3331 host->fifo_depth = fifo_size;
52426899
SJ		 3332 host->fifoth_val =
3333 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
e61cf118 3334 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 3335
3336 /* disable clock to CIU */
3337 mci_writel(host, CLKENA, 0);
3338 mci_writel(host, CLKSRC, 0);
3339
63008768
JH		 3340 /*
3341 * In 2.40a spec, Data offset is changed.
3342 * Need to check the version-id and set data-offset for DATA register.
3343 */
3344 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3345 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3346
a0361c1a
JN		 3347 if (host->data_addr_override)
3348 host->fifo_reg = host->regs + host->data_addr_override;
3349 else if (host->verid < DW_MMC_240A)
76184ac1 3350 host->fifo_reg = host->regs + DATA_OFFSET;
63008768 3351 else
76184ac1 3352 host->fifo_reg = host->regs + DATA_240A_OFFSET;
63008768 3353
f95f3850 3354 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
780f22af
SJ		 3355 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3356 host->irq_flags, "dw-mci", host);
f95f3850 3357 if (ret)
6130e7a9 3358 goto err_dmaunmap;
f95f3850 3359
2da1d7f2 3360 /*
fa0c3283 3361 * Enable interrupts for command done, data over, data empty,
2da1d7f2
YC		 3362 * receive ready and error such as transmit, receive timeout, crc error
3363 */
2da1d7f2
YC		 3364 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3365 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3366 DW_MCI_ERROR_FLAGS);
0e3a22c0
SL		 3367 /* Enable mci interrupt */
3368 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2da1d7f2 3369
0e3a22c0
SL		 3370 dev_info(host->dev,
3371 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
2da1d7f2
YC		 3372 host->irq, width, fifo_size);
3373
f95f3850 3374 /* We need at least one slot to succeed */
e4a65ef7 3375 ret = dw_mci_init_slot(host);
58870241
JC		 3376 if (ret) {
3377 dev_dbg(host->dev, "slot %d init failed\n", i);
6130e7a9 3378 goto err_dmaunmap;
f95f3850
WN		 3379 }
3380
b793f658
DA		 3381 /* Now that slots are all setup, we can enable card detect */
3382 dw_mci_enable_cd(host);
3383
f95f3850
WN		 3384 return 0;
3385
f95f3850
WN		 3386err_dmaunmap:
3387 if (host->use_dma && host->dma_ops->exit)
3388 host->dma_ops->exit(host);
f90a0612 3389
d6786fef
GX		 3390 if (!IS_ERR(host->pdata->rstc))
3391 reset_control_assert(host->pdata->rstc);
3392
f90a0612 3393err_clk_ciu:
7037f3be 3394 clk_disable_unprepare(host->ciu_clk);
780f22af 3395
f90a0612 3396err_clk_biu:
7037f3be 3397 clk_disable_unprepare(host->biu_clk);
780f22af 3398
f95f3850
WN		 3399 return ret;
3400}
62ca8034 3401EXPORT_SYMBOL(dw_mci_probe);
f95f3850 3402
62ca8034 3403void dw_mci_remove(struct dw_mci *host)
f95f3850 3404{
e4a65ef7 3405 dev_dbg(host->dev, "remove slot\n");
b23475fa 3406 if (host->slot)
e4a65ef7 3407 dw_mci_cleanup_slot(host->slot);
f95f3850 3408
048fd7e6
PT		 3409 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3410 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3411
f95f3850
WN		 3412 /* disable clock to CIU */
3413 mci_writel(host, CLKENA, 0);
3414 mci_writel(host, CLKSRC, 0);
3415
f95f3850
WN		 3416 if (host->use_dma && host->dma_ops->exit)
3417 host->dma_ops->exit(host);
3418
d6786fef
GX		 3419 if (!IS_ERR(host->pdata->rstc))
3420 reset_control_assert(host->pdata->rstc);
3421
7037f3be
JC		 3422 clk_disable_unprepare(host->ciu_clk);
3423 clk_disable_unprepare(host->biu_clk);
f95f3850 3424}
62ca8034
SH		 3425EXPORT_SYMBOL(dw_mci_remove);
3426
3427
f95f3850 3428
e9ed8835 3429#ifdef CONFIG_PM
ed24e1ff 3430int dw_mci_runtime_suspend(struct device *dev)
f95f3850 3431{
ed24e1ff
SL		 3432 struct dw_mci *host = dev_get_drvdata(dev);
3433
3fc7eaef
SL		 3434 if (host->use_dma && host->dma_ops->exit)
3435 host->dma_ops->exit(host);
3436
ed24e1ff
SL		 3437 clk_disable_unprepare(host->ciu_clk);
3438
42f989c0
JC		 3439 if (host->slot &&
3440 (mmc_can_gpio_cd(host->slot->mmc) ||
3441 !mmc_card_is_removable(host->slot->mmc)))
ed24e1ff
SL		 3442 clk_disable_unprepare(host->biu_clk);
3443
f95f3850
WN		 3444 return 0;
3445}
ed24e1ff 3446EXPORT_SYMBOL(dw_mci_runtime_suspend);
f95f3850 3447
ed24e1ff 3448int dw_mci_runtime_resume(struct device *dev)
f95f3850 3449{
b23475fa 3450 int ret = 0;
ed24e1ff 3451 struct dw_mci *host = dev_get_drvdata(dev);
f95f3850 3452
42f989c0
JC		 3453 if (host->slot &&
3454 (mmc_can_gpio_cd(host->slot->mmc) ||
3455 !mmc_card_is_removable(host->slot->mmc))) {
ed24e1ff
SL		 3456 ret = clk_prepare_enable(host->biu_clk);
3457 if (ret)
3458 return ret;
e61cf118
JC		 3459 }
3460
ed24e1ff
SL		 3461 ret = clk_prepare_enable(host->ciu_clk);
3462 if (ret)
df9bcc2b
JS		 3463 goto err;
3464
3465 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3466 clk_disable_unprepare(host->ciu_clk);
3467 ret = -ENODEV;
3468 goto err;
3469 }
ed24e1ff 3470
3bfe619d 3471 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 3472 host->dma_ops->init(host);
3473
52426899
SJ		 3474 /*
3475 * Restore the initial value at FIFOTH register
3476 * And Invalidate the prev_blksz with zero
3477 */
ed24e1ff
SL		 3478 mci_writel(host, FIFOTH, host->fifoth_val);
3479 host->prev_blksz = 0;
e61cf118 3480
2eb2944f
DA		 3481 /* Put in max timeout */
3482 mci_writel(host, TMOUT, 0xFFFFFFFF);
3483
e61cf118
JC		 3484 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3485 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3486 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3487 DW_MCI_ERROR_FLAGS);
e61cf118
JC		 3488 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3489
0e3a22c0 3490
e47c0b96
JC		 3491 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3492 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
e9748e03 3493
58870241 3494 /* Force setup bus to guarantee available clock output */
e47c0b96 3495 dw_mci_setup_bus(host->slot, true);
fa0c3283
DA		 3496
3497 /* Now that slots are all setup, we can enable card detect */
3498 dw_mci_enable_cd(host);
3499
df9bcc2b
JS		 3500 return 0;
3501
3502err:
42f989c0
JC		 3503 if (host->slot &&
3504 (mmc_can_gpio_cd(host->slot->mmc) ||
3505 !mmc_card_is_removable(host->slot->mmc)))
df9bcc2b
JS		 3506 clk_disable_unprepare(host->biu_clk);
3507
ed24e1ff 3508 return ret;
e9ed8835
SL		 3509}
3510EXPORT_SYMBOL(dw_mci_runtime_resume);
3511#endif /* CONFIG_PM */
6fe8890d 3512
f95f3850
WN		 3513static int __init dw_mci_init(void)
3514{
8e1c4e4d 3515 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
62ca8034 3516 return 0;
f95f3850
WN		 3517}
3518
3519static void __exit dw_mci_exit(void)
3520{
f95f3850
WN		 3521}
3522
3523module_init(dw_mci_init);
3524module_exit(dw_mci_exit);
3525
3526MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3527MODULE_AUTHOR("NXP Semiconductor VietNam");
3528MODULE_AUTHOR("Imagination Technologies Ltd");
3529MODULE_LICENSE("GPL v2");
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