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mmc: dw_mmc: fix the CardThreshold boundary at CardThrCtl register
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
b24c8b26 30#include <linux/mmc/card.h>
f95f3850
WN		 31#include <linux/mmc/host.h>
32#include <linux/mmc/mmc.h>
01730558 33#include <linux/mmc/sd.h>
90c2143a 34#include <linux/mmc/sdio.h>
f95f3850
WN		 35#include <linux/mmc/dw_mmc.h>
36#include <linux/bitops.h>
c07946a3 37#include <linux/regulator/consumer.h>
c91eab4b 38#include <linux/of.h>
55a6ceb2 39#include <linux/of_gpio.h>
bf626e55 40#include <linux/mmc/slot-gpio.h>
f95f3850
WN		 41
42#include "dw_mmc.h"
43
44/* Common flag combinations */
3f7eec62 45#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
f95f3850
WN		 46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52#define DW_MCI_SEND_STATUS 1
53#define DW_MCI_RECV_STATUS 2
54#define DW_MCI_DMA_THRESHOLD 16
55
1f44a2a5
SJ		 56#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
fc79a4d6
JS		 59#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
62 SDMMC_IDMAC_INT_TI)
63
69d99fdc
PT		 64struct idmac_desc_64addr {
65 u32 des0; /* Control Descriptor */
66
67 u32 des1; /* Reserved */
68
69 u32 des2; /*Buffer sizes */
70#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
6687c42f
BD		 71 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
72 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
69d99fdc
PT		 73
74 u32 des3; /* Reserved */
75
76 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
77 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
78
79 u32 des6; /* Lower 32-bits of Next Descriptor Address */
80 u32 des7; /* Upper 32-bits of Next Descriptor Address */
81};
82
f95f3850 83struct idmac_desc {
6687c42f 84 __le32 des0; /* Control Descriptor */
f95f3850
WN		 85#define IDMAC_DES0_DIC BIT(1)
86#define IDMAC_DES0_LD BIT(2)
87#define IDMAC_DES0_FD BIT(3)
88#define IDMAC_DES0_CH BIT(4)
89#define IDMAC_DES0_ER BIT(5)
90#define IDMAC_DES0_CES BIT(30)
91#define IDMAC_DES0_OWN BIT(31)
92
6687c42f 93 __le32 des1; /* Buffer sizes */
f95f3850 94#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 95 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850 96
6687c42f 97 __le32 des2; /* buffer 1 physical address */
f95f3850 98
6687c42f 99 __le32 des3; /* buffer 2 physical address */
f95f3850 100};
5959b32e
AB		 101
102/* Each descriptor can transfer up to 4KB of data in chained mode */
103#define DW_MCI_DESC_DATA_LENGTH 0x1000
f95f3850 104
3a33a94c 105static bool dw_mci_reset(struct dw_mci *host);
536f6b91 106static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
0bdbd0e8 107static int dw_mci_card_busy(struct mmc_host *mmc);
31bff450 108
f95f3850
WN		 109#if defined(CONFIG_DEBUG_FS)
110static int dw_mci_req_show(struct seq_file *s, void *v)
111{
112 struct dw_mci_slot *slot = s->private;
113 struct mmc_request *mrq;
114 struct mmc_command *cmd;
115 struct mmc_command *stop;
116 struct mmc_data *data;
117
118 /* Make sure we get a consistent snapshot */
119 spin_lock_bh(&slot->host->lock);
120 mrq = slot->mrq;
121
122 if (mrq) {
123 cmd = mrq->cmd;
124 data = mrq->data;
125 stop = mrq->stop;
126
127 if (cmd)
128 seq_printf(s,
129 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
130 cmd->opcode, cmd->arg, cmd->flags,
131 cmd->resp[0], cmd->resp[1], cmd->resp[2],
132 cmd->resp[2], cmd->error);
133 if (data)
134 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
135 data->bytes_xfered, data->blocks,
136 data->blksz, data->flags, data->error);
137 if (stop)
138 seq_printf(s,
139 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
140 stop->opcode, stop->arg, stop->flags,
141 stop->resp[0], stop->resp[1], stop->resp[2],
142 stop->resp[2], stop->error);
143 }
144
145 spin_unlock_bh(&slot->host->lock);
146
147 return 0;
148}
149
150static int dw_mci_req_open(struct inode *inode, struct file *file)
151{
152 return single_open(file, dw_mci_req_show, inode->i_private);
153}
154
155static const struct file_operations dw_mci_req_fops = {
156 .owner = THIS_MODULE,
157 .open = dw_mci_req_open,
158 .read = seq_read,
159 .llseek = seq_lseek,
160 .release = single_release,
161};
162
163static int dw_mci_regs_show(struct seq_file *s, void *v)
164{
165 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
166 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
167 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
168 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
169 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
170 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
171
172 return 0;
173}
174
175static int dw_mci_regs_open(struct inode *inode, struct file *file)
176{
177 return single_open(file, dw_mci_regs_show, inode->i_private);
178}
179
180static const struct file_operations dw_mci_regs_fops = {
181 .owner = THIS_MODULE,
182 .open = dw_mci_regs_open,
183 .read = seq_read,
184 .llseek = seq_lseek,
185 .release = single_release,
186};
187
188static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
189{
190 struct mmc_host *mmc = slot->mmc;
191 struct dw_mci *host = slot->host;
192 struct dentry *root;
193 struct dentry *node;
194
195 root = mmc->debugfs_root;
196 if (!root)
197 return;
198
199 node = debugfs_create_file("regs", S_IRUSR, root, host,
200 &dw_mci_regs_fops);
201 if (!node)
202 goto err;
203
204 node = debugfs_create_file("req", S_IRUSR, root, slot,
205 &dw_mci_req_fops);
206 if (!node)
207 goto err;
208
209 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
210 if (!node)
211 goto err;
212
213 node = debugfs_create_x32("pending_events", S_IRUSR, root,
214 (u32 *)&host->pending_events);
215 if (!node)
216 goto err;
217
218 node = debugfs_create_x32("completed_events", S_IRUSR, root,
219 (u32 *)&host->completed_events);
220 if (!node)
221 goto err;
222
223 return;
224
225err:
226 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
227}
228#endif /* defined(CONFIG_DEBUG_FS) */
229
01730558
DA		 230static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
231
f95f3850
WN		 232static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
233{
234 struct mmc_data *data;
800d78bf 235 struct dw_mci_slot *slot = mmc_priv(mmc);
01730558 236 struct dw_mci *host = slot->host;
e95baf13 237 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
f95f3850 238 u32 cmdr;
f95f3850 239
0e3a22c0 240 cmd->error = -EINPROGRESS;
f95f3850
WN		 241 cmdr = cmd->opcode;
242
90c2143a
SJ		 243 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
244 cmd->opcode == MMC_GO_IDLE_STATE ||
245 cmd->opcode == MMC_GO_INACTIVE_STATE ||
246 (cmd->opcode == SD_IO_RW_DIRECT &&
247 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
f95f3850 248 cmdr |= SDMMC_CMD_STOP;
4a1b27ad
JC		 249 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
250 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
f95f3850 251
01730558
DA		 252 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
253 u32 clk_en_a;
254
255 /* Special bit makes CMD11 not die */
256 cmdr |= SDMMC_CMD_VOLT_SWITCH;
257
258 /* Change state to continue to handle CMD11 weirdness */
259 WARN_ON(slot->host->state != STATE_SENDING_CMD);
260 slot->host->state = STATE_SENDING_CMD11;
261
262 /*
263 * We need to disable low power mode (automatic clock stop)
264 * while doing voltage switch so we don't confuse the card,
265 * since stopping the clock is a specific part of the UHS
266 * voltage change dance.
267 *
268 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
269 * unconditionally turned back on in dw_mci_setup_bus() if it's
270 * ever called with a non-zero clock. That shouldn't happen
271 * until the voltage change is all done.
272 */
273 clk_en_a = mci_readl(host, CLKENA);
274 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
275 mci_writel(host, CLKENA, clk_en_a);
276 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
277 SDMMC_CMD_PRV_DAT_WAIT, 0);
278 }
279
f95f3850
WN		 280 if (cmd->flags & MMC_RSP_PRESENT) {
281 /* We expect a response, so set this bit */
282 cmdr |= SDMMC_CMD_RESP_EXP;
283 if (cmd->flags & MMC_RSP_136)
284 cmdr |= SDMMC_CMD_RESP_LONG;
285 }
286
287 if (cmd->flags & MMC_RSP_CRC)
288 cmdr |= SDMMC_CMD_RESP_CRC;
289
290 data = cmd->data;
291 if (data) {
292 cmdr |= SDMMC_CMD_DAT_EXP;
293 if (data->flags & MMC_DATA_STREAM)
294 cmdr |= SDMMC_CMD_STRM_MODE;
295 if (data->flags & MMC_DATA_WRITE)
296 cmdr |= SDMMC_CMD_DAT_WR;
297 }
298
cb27a843
JH		 299 if (drv_data && drv_data->prepare_command)
300 drv_data->prepare_command(slot->host, &cmdr);
800d78bf 301
f95f3850
WN		 302 return cmdr;
303}
304
90c2143a
SJ		 305static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
306{
307 struct mmc_command *stop;
308 u32 cmdr;
309
310 if (!cmd->data)
311 return 0;
312
313 stop = &host->stop_abort;
314 cmdr = cmd->opcode;
315 memset(stop, 0, sizeof(struct mmc_command));
316
317 if (cmdr == MMC_READ_SINGLE_BLOCK ||
318 cmdr == MMC_READ_MULTIPLE_BLOCK ||
319 cmdr == MMC_WRITE_BLOCK ||
6c2c6506
UH		 320 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
321 cmdr == MMC_SEND_TUNING_BLOCK ||
322 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
90c2143a
SJ		 323 stop->opcode = MMC_STOP_TRANSMISSION;
324 stop->arg = 0;
325 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
326 } else if (cmdr == SD_IO_RW_EXTENDED) {
327 stop->opcode = SD_IO_RW_DIRECT;
328 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
329 ((cmd->arg >> 28) & 0x7);
330 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
331 } else {
332 return 0;
333 }
334
335 cmdr = stop->opcode | SDMMC_CMD_STOP |
336 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
337
338 return cmdr;
339}
340
0bdbd0e8
DA		 341static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
342{
343 unsigned long timeout = jiffies + msecs_to_jiffies(500);
344
345 /*
346 * Databook says that before issuing a new data transfer command
347 * we need to check to see if the card is busy. Data transfer commands
348 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
349 *
350 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
351 * expected.
352 */
353 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
354 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
355 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
356 if (time_after(jiffies, timeout)) {
357 /* Command will fail; we'll pass error then */
358 dev_err(host->dev, "Busy; trying anyway\n");
359 break;
360 }
361 udelay(10);
362 }
363 }
364}
365
f95f3850
WN		 366static void dw_mci_start_command(struct dw_mci *host,
367 struct mmc_command *cmd, u32 cmd_flags)
368{
369 host->cmd = cmd;
4a90920c 370 dev_vdbg(host->dev,
f95f3850
WN		 371 "start command: ARGR=0x%08x CMDR=0x%08x\n",
372 cmd->arg, cmd_flags);
373
374 mci_writel(host, CMDARG, cmd->arg);
0e3a22c0 375 wmb(); /* drain writebuffer */
0bdbd0e8 376 dw_mci_wait_while_busy(host, cmd_flags);
f95f3850
WN		 377
378 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
379}
380
90c2143a 381static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
f95f3850 382{
90c2143a 383 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
0e3a22c0 384
90c2143a 385 dw_mci_start_command(host, stop, host->stop_cmdr);
f95f3850
WN		 386}
387
388/* DMA interface functions */
389static void dw_mci_stop_dma(struct dw_mci *host)
390{
03e8cb53 391 if (host->using_dma) {
f95f3850
WN		 392 host->dma_ops->stop(host);
393 host->dma_ops->cleanup(host);
f95f3850 394 }
aa50f259
SJ		 395
396 /* Data transfer was stopped by the interrupt handler */
397 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
f95f3850
WN		 398}
399
9aa51408
SJ		 400static int dw_mci_get_dma_dir(struct mmc_data *data)
401{
402 if (data->flags & MMC_DATA_WRITE)
403 return DMA_TO_DEVICE;
404 else
405 return DMA_FROM_DEVICE;
406}
407
f95f3850
WN		 408static void dw_mci_dma_cleanup(struct dw_mci *host)
409{
410 struct mmc_data *data = host->data;
411
412 if (data)
9aa51408 413 if (!data->host_cookie)
4a90920c 414 dma_unmap_sg(host->dev,
9aa51408
SJ		 415 data->sg,
416 data->sg_len,
417 dw_mci_get_dma_dir(data));
f95f3850
WN		 418}
419
5ce9d961
SJ		 420static void dw_mci_idmac_reset(struct dw_mci *host)
421{
422 u32 bmod = mci_readl(host, BMOD);
423 /* Software reset of DMA */
424 bmod |= SDMMC_IDMAC_SWRESET;
425 mci_writel(host, BMOD, bmod);
426}
427
f95f3850
WN		 428static void dw_mci_idmac_stop_dma(struct dw_mci *host)
429{
430 u32 temp;
431
432 /* Disable and reset the IDMAC interface */
433 temp = mci_readl(host, CTRL);
434 temp &= ~SDMMC_CTRL_USE_IDMAC;
435 temp |= SDMMC_CTRL_DMA_RESET;
436 mci_writel(host, CTRL, temp);
437
438 /* Stop the IDMAC running */
439 temp = mci_readl(host, BMOD);
a5289a43 440 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
5ce9d961 441 temp |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 442 mci_writel(host, BMOD, temp);
443}
444
3fc7eaef 445static void dw_mci_dmac_complete_dma(void *arg)
f95f3850 446{
3fc7eaef 447 struct dw_mci *host = arg;
f95f3850
WN		 448 struct mmc_data *data = host->data;
449
4a90920c 450 dev_vdbg(host->dev, "DMA complete\n");
f95f3850 451
3fc7eaef
SL		 452 if ((host->use_dma == TRANS_MODE_EDMAC) &&
453 data && (data->flags & MMC_DATA_READ))
454 /* Invalidate cache after read */
455 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
456 data->sg,
457 data->sg_len,
458 DMA_FROM_DEVICE);
459
f95f3850
WN		 460 host->dma_ops->cleanup(host);
461
462 /*
463 * If the card was removed, data will be NULL. No point in trying to
464 * send the stop command or waiting for NBUSY in this case.
465 */
466 if (data) {
467 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
468 tasklet_schedule(&host->tasklet);
469 }
470}
471
472static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
473 unsigned int sg_len)
474{
5959b32e 475 unsigned int desc_len;
f95f3850 476 int i;
0e3a22c0 477
69d99fdc 478 if (host->dma_64bit_address == 1) {
5959b32e
AB		 479 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
480
481 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 482
5959b32e 483 for (i = 0; i < sg_len; i++) {
69d99fdc 484 unsigned int length = sg_dma_len(&data->sg[i]);
0e3a22c0 485
69d99fdc 486 u64 mem_addr = sg_dma_address(&data->sg[i]);
f95f3850 487
5959b32e
AB		 488 for ( ; length ; desc++) {
489 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
490 length : DW_MCI_DESC_DATA_LENGTH;
491
492 length -= desc_len;
493
494 /*
495 * Set the OWN bit and disable interrupts
496 * for this descriptor
497 */
498 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
499 IDMAC_DES0_CH;
500
501 /* Buffer length */
502 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
503
504 /* Physical address to DMA to/from */
505 desc->des4 = mem_addr & 0xffffffff;
506 desc->des5 = mem_addr >> 32;
507
508 /* Update physical address for the next desc */
509 mem_addr += desc_len;
510
511 /* Save pointer to the last descriptor */
512 desc_last = desc;
513 }
69d99fdc 514 }
f95f3850 515
69d99fdc 516 /* Set first descriptor */
5959b32e 517 desc_first->des0 |= IDMAC_DES0_FD;
f95f3850 518
69d99fdc 519 /* Set last descriptor */
5959b32e
AB		 520 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
521 desc_last->des0 |= IDMAC_DES0_LD;
f95f3850 522
69d99fdc 523 } else {
5959b32e
AB		 524 struct idmac_desc *desc_first, *desc_last, *desc;
525
526 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 527
5959b32e 528 for (i = 0; i < sg_len; i++) {
69d99fdc 529 unsigned int length = sg_dma_len(&data->sg[i]);
0e3a22c0 530
69d99fdc
PT		 531 u32 mem_addr = sg_dma_address(&data->sg[i]);
532
5959b32e
AB		 533 for ( ; length ; desc++) {
534 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
535 length : DW_MCI_DESC_DATA_LENGTH;
536
537 length -= desc_len;
538
539 /*
540 * Set the OWN bit and disable interrupts
541 * for this descriptor
542 */
543 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
544 IDMAC_DES0_DIC |
545 IDMAC_DES0_CH);
546
547 /* Buffer length */
548 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
f95f3850 549
5959b32e
AB		 550 /* Physical address to DMA to/from */
551 desc->des2 = cpu_to_le32(mem_addr);
552
553 /* Update physical address for the next desc */
554 mem_addr += desc_len;
555
556 /* Save pointer to the last descriptor */
557 desc_last = desc;
558 }
69d99fdc
PT		 559 }
560
561 /* Set first descriptor */
5959b32e 562 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
f95f3850 563
69d99fdc 564 /* Set last descriptor */
5959b32e
AB		 565 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
566 IDMAC_DES0_DIC));
567 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
69d99fdc 568 }
f95f3850 569
0e3a22c0 570 wmb(); /* drain writebuffer */
f95f3850
WN		 571}
572
3fc7eaef 573static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
f95f3850
WN		 574{
575 u32 temp;
576
577 dw_mci_translate_sglist(host, host->data, sg_len);
578
536f6b91
SR		 579 /* Make sure to reset DMA in case we did PIO before this */
580 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
581 dw_mci_idmac_reset(host);
582
f95f3850
WN		 583 /* Select IDMAC interface */
584 temp = mci_readl(host, CTRL);
585 temp |= SDMMC_CTRL_USE_IDMAC;
586 mci_writel(host, CTRL, temp);
587
0e3a22c0 588 /* drain writebuffer */
f95f3850
WN		 589 wmb();
590
591 /* Enable the IDMAC */
592 temp = mci_readl(host, BMOD);
a5289a43 593 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 594 mci_writel(host, BMOD, temp);
595
596 /* Start it running */
597 mci_writel(host, PLDMND, 1);
3fc7eaef
SL		 598
599 return 0;
f95f3850
WN		 600}
601
602static int dw_mci_idmac_init(struct dw_mci *host)
603{
897b69e7 604 int i;
f95f3850 605
69d99fdc
PT		 606 if (host->dma_64bit_address == 1) {
607 struct idmac_desc_64addr *p;
608 /* Number of descriptors in the ring buffer */
609 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
610
611 /* Forward link the descriptor list */
612 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
613 i++, p++) {
614 p->des6 = (host->sg_dma +
615 (sizeof(struct idmac_desc_64addr) *
616 (i + 1))) & 0xffffffff;
617
618 p->des7 = (u64)(host->sg_dma +
619 (sizeof(struct idmac_desc_64addr) *
620 (i + 1))) >> 32;
621 /* Initialize reserved and buffer size fields to "0" */
622 p->des1 = 0;
623 p->des2 = 0;
624 p->des3 = 0;
625 }
f95f3850 626
69d99fdc
PT		 627 /* Set the last descriptor as the end-of-ring descriptor */
628 p->des6 = host->sg_dma & 0xffffffff;
629 p->des7 = (u64)host->sg_dma >> 32;
630 p->des0 = IDMAC_DES0_ER;
f95f3850 631
69d99fdc
PT		 632 } else {
633 struct idmac_desc *p;
634 /* Number of descriptors in the ring buffer */
635 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
636
637 /* Forward link the descriptor list */
0e3a22c0
SL		 638 for (i = 0, p = host->sg_cpu;
639 i < host->ring_size - 1;
640 i++, p++) {
6687c42f
BD		 641 p->des3 = cpu_to_le32(host->sg_dma +
642 (sizeof(struct idmac_desc) * (i + 1)));
4b244724
ZG		 643 p->des1 = 0;
644 }
69d99fdc
PT		 645
646 /* Set the last descriptor as the end-of-ring descriptor */
6687c42f
BD		 647 p->des3 = cpu_to_le32(host->sg_dma);
648 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
69d99fdc 649 }
f95f3850 650
5ce9d961 651 dw_mci_idmac_reset(host);
141a712a 652
69d99fdc
PT		 653 if (host->dma_64bit_address == 1) {
654 /* Mask out interrupts - get Tx & Rx complete only */
655 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
656 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
657 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
658
659 /* Set the descriptor base address */
660 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
661 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
662
663 } else {
664 /* Mask out interrupts - get Tx & Rx complete only */
665 mci_writel(host, IDSTS, IDMAC_INT_CLR);
666 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
667 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
668
669 /* Set the descriptor base address */
670 mci_writel(host, DBADDR, host->sg_dma);
671 }
f95f3850 672
f95f3850
WN		 673 return 0;
674}
675
8e2b36ea 676static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 677 .init = dw_mci_idmac_init,
678 .start = dw_mci_idmac_start_dma,
679 .stop = dw_mci_idmac_stop_dma,
3fc7eaef
SL		 680 .complete = dw_mci_dmac_complete_dma,
681 .cleanup = dw_mci_dma_cleanup,
682};
683
684static void dw_mci_edmac_stop_dma(struct dw_mci *host)
685{
686 dmaengine_terminate_all(host->dms->ch);
687}
688
689static int dw_mci_edmac_start_dma(struct dw_mci *host,
690 unsigned int sg_len)
691{
692 struct dma_slave_config cfg;
693 struct dma_async_tx_descriptor *desc = NULL;
694 struct scatterlist *sgl = host->data->sg;
695 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
696 u32 sg_elems = host->data->sg_len;
697 u32 fifoth_val;
698 u32 fifo_offset = host->fifo_reg - host->regs;
699 int ret = 0;
700
701 /* Set external dma config: burst size, burst width */
702 cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset);
703 cfg.src_addr = cfg.dst_addr;
704 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
705 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
706
707 /* Match burst msize with external dma config */
708 fifoth_val = mci_readl(host, FIFOTH);
709 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
710 cfg.src_maxburst = cfg.dst_maxburst;
711
712 if (host->data->flags & MMC_DATA_WRITE)
713 cfg.direction = DMA_MEM_TO_DEV;
714 else
715 cfg.direction = DMA_DEV_TO_MEM;
716
717 ret = dmaengine_slave_config(host->dms->ch, &cfg);
718 if (ret) {
719 dev_err(host->dev, "Failed to config edmac.\n");
720 return -EBUSY;
721 }
722
723 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
724 sg_len, cfg.direction,
725 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
726 if (!desc) {
727 dev_err(host->dev, "Can't prepare slave sg.\n");
728 return -EBUSY;
729 }
730
731 /* Set dw_mci_dmac_complete_dma as callback */
732 desc->callback = dw_mci_dmac_complete_dma;
733 desc->callback_param = (void *)host;
734 dmaengine_submit(desc);
735
736 /* Flush cache before write */
737 if (host->data->flags & MMC_DATA_WRITE)
738 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
739 sg_elems, DMA_TO_DEVICE);
740
741 dma_async_issue_pending(host->dms->ch);
742
743 return 0;
744}
745
746static int dw_mci_edmac_init(struct dw_mci *host)
747{
748 /* Request external dma channel */
749 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
750 if (!host->dms)
751 return -ENOMEM;
752
753 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
754 if (!host->dms->ch) {
4539d36e 755 dev_err(host->dev, "Failed to get external DMA channel.\n");
3fc7eaef
SL		 756 kfree(host->dms);
757 host->dms = NULL;
758 return -ENXIO;
759 }
760
761 return 0;
762}
763
764static void dw_mci_edmac_exit(struct dw_mci *host)
765{
766 if (host->dms) {
767 if (host->dms->ch) {
768 dma_release_channel(host->dms->ch);
769 host->dms->ch = NULL;
770 }
771 kfree(host->dms);
772 host->dms = NULL;
773 }
774}
775
776static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
777 .init = dw_mci_edmac_init,
778 .exit = dw_mci_edmac_exit,
779 .start = dw_mci_edmac_start_dma,
780 .stop = dw_mci_edmac_stop_dma,
781 .complete = dw_mci_dmac_complete_dma,
885c3e80
SJ		 782 .cleanup = dw_mci_dma_cleanup,
783};
885c3e80 784
9aa51408
SJ		 785static int dw_mci_pre_dma_transfer(struct dw_mci *host,
786 struct mmc_data *data,
787 bool next)
f95f3850
WN		 788{
789 struct scatterlist *sg;
9aa51408 790 unsigned int i, sg_len;
03e8cb53 791
9aa51408
SJ		 792 if (!next && data->host_cookie)
793 return data->host_cookie;
f95f3850
WN		 794
795 /*
796 * We don't do DMA on "complex" transfers, i.e. with
797 * non-word-aligned buffers or lengths. Also, we don't bother
798 * with all the DMA setup overhead for short transfers.
799 */
800 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
801 return -EINVAL;
9aa51408 802
f95f3850
WN		 803 if (data->blksz & 3)
804 return -EINVAL;
805
806 for_each_sg(data->sg, sg, data->sg_len, i) {
807 if (sg->offset & 3 || sg->length & 3)
808 return -EINVAL;
809 }
810
4a90920c 811 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 812 data->sg,
813 data->sg_len,
814 dw_mci_get_dma_dir(data));
815 if (sg_len == 0)
816 return -EINVAL;
03e8cb53 817
9aa51408
SJ		 818 if (next)
819 data->host_cookie = sg_len;
f95f3850 820
9aa51408
SJ		 821 return sg_len;
822}
823
9aa51408
SJ		 824static void dw_mci_pre_req(struct mmc_host *mmc,
825 struct mmc_request *mrq,
826 bool is_first_req)
827{
828 struct dw_mci_slot *slot = mmc_priv(mmc);
829 struct mmc_data *data = mrq->data;
830
831 if (!slot->host->use_dma || !data)
832 return;
833
834 if (data->host_cookie) {
835 data->host_cookie = 0;
836 return;
837 }
838
839 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
840 data->host_cookie = 0;
841}
842
843static void dw_mci_post_req(struct mmc_host *mmc,
844 struct mmc_request *mrq,
845 int err)
846{
847 struct dw_mci_slot *slot = mmc_priv(mmc);
848 struct mmc_data *data = mrq->data;
849
850 if (!slot->host->use_dma || !data)
851 return;
852
853 if (data->host_cookie)
4a90920c 854 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 855 data->sg,
856 data->sg_len,
857 dw_mci_get_dma_dir(data));
858 data->host_cookie = 0;
859}
860
52426899
SJ		 861static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
862{
52426899
SJ		 863 unsigned int blksz = data->blksz;
864 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
865 u32 fifo_width = 1 << host->data_shift;
866 u32 blksz_depth = blksz / fifo_width, fifoth_val;
867 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
0e3a22c0 868 int idx = ARRAY_SIZE(mszs) - 1;
52426899 869
3fc7eaef
SL		 870 /* pio should ship this scenario */
871 if (!host->use_dma)
872 return;
873
52426899
SJ		 874 tx_wmark = (host->fifo_depth) / 2;
875 tx_wmark_invers = host->fifo_depth - tx_wmark;
876
877 /*
878 * MSIZE is '1',
879 * if blksz is not a multiple of the FIFO width
880 */
881 if (blksz % fifo_width) {
882 msize = 0;
883 rx_wmark = 1;
884 goto done;
885 }
886
887 do {
888 if (!((blksz_depth % mszs[idx]) ||
889 (tx_wmark_invers % mszs[idx]))) {
890 msize = idx;
891 rx_wmark = mszs[idx] - 1;
892 break;
893 }
894 } while (--idx > 0);
895 /*
896 * If idx is '0', it won't be tried
897 * Thus, initial values are uesed
898 */
899done:
900 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
901 mci_writel(host, FIFOTH, fifoth_val);
52426899
SJ		 902}
903
f1d2736c
SJ		 904static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
905{
906 unsigned int blksz = data->blksz;
907 u32 blksz_depth, fifo_depth;
908 u16 thld_size;
909
910 WARN_ON(!(data->flags & MMC_DATA_READ));
911
66dfd101
JH		 912 /*
913 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
914 * in the FIFO region, so we really shouldn't access it).
915 */
916 if (host->verid < DW_MMC_240A)
917 return;
918
f1d2736c 919 if (host->timing != MMC_TIMING_MMC_HS200 &&
488b8d63 920 host->timing != MMC_TIMING_MMC_HS400 &&
f1d2736c
SJ		 921 host->timing != MMC_TIMING_UHS_SDR104)
922 goto disable;
923
924 blksz_depth = blksz / (1 << host->data_shift);
925 fifo_depth = host->fifo_depth;
926
927 if (blksz_depth > fifo_depth)
928 goto disable;
929
930 /*
931 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
932 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
933 * Currently just choose blksz.
934 */
935 thld_size = blksz;
936 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
937 return;
938
939disable:
940 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
941}
942
9aa51408
SJ		 943static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
944{
f8c58c11 945 unsigned long irqflags;
9aa51408
SJ		 946 int sg_len;
947 u32 temp;
948
949 host->using_dma = 0;
950
951 /* If we don't have a channel, we can't do DMA */
952 if (!host->use_dma)
953 return -ENODEV;
954
955 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 956 if (sg_len < 0) {
957 host->dma_ops->stop(host);
9aa51408 958 return sg_len;
a99aa9b9 959 }
9aa51408
SJ		 960
961 host->using_dma = 1;
f95f3850 962
3fc7eaef
SL		 963 if (host->use_dma == TRANS_MODE_IDMAC)
964 dev_vdbg(host->dev,
965 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
966 (unsigned long)host->sg_cpu,
967 (unsigned long)host->sg_dma,
968 sg_len);
f95f3850 969
52426899
SJ		 970 /*
971 * Decide the MSIZE and RX/TX Watermark.
972 * If current block size is same with previous size,
973 * no need to update fifoth.
974 */
975 if (host->prev_blksz != data->blksz)
976 dw_mci_adjust_fifoth(host, data);
977
f95f3850
WN		 978 /* Enable the DMA interface */
979 temp = mci_readl(host, CTRL);
980 temp |= SDMMC_CTRL_DMA_ENABLE;
981 mci_writel(host, CTRL, temp);
982
983 /* Disable RX/TX IRQs, let DMA handle it */
f8c58c11 984 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 985 temp = mci_readl(host, INTMASK);
986 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
987 mci_writel(host, INTMASK, temp);
f8c58c11 988 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850 989
3fc7eaef
SL		 990 if (host->dma_ops->start(host, sg_len)) {
991 /* We can't do DMA */
992 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
993 return -ENODEV;
994 }
f95f3850
WN		 995
996 return 0;
997}
998
999static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1000{
f8c58c11 1001 unsigned long irqflags;
0e3a22c0 1002 int flags = SG_MITER_ATOMIC;
f95f3850
WN		 1003 u32 temp;
1004
1005 data->error = -EINPROGRESS;
1006
1007 WARN_ON(host->data);
1008 host->sg = NULL;
1009 host->data = data;
1010
f1d2736c 1011 if (data->flags & MMC_DATA_READ) {
55c5efbc 1012 host->dir_status = DW_MCI_RECV_STATUS;
f1d2736c
SJ		 1013 dw_mci_ctrl_rd_thld(host, data);
1014 } else {
55c5efbc 1015 host->dir_status = DW_MCI_SEND_STATUS;
f1d2736c 1016 }
55c5efbc 1017
f95f3850 1018 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 1019 if (host->data->flags & MMC_DATA_READ)
1020 flags |= SG_MITER_TO_SG;
1021 else
1022 flags |= SG_MITER_FROM_SG;
1023
1024 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 1025 host->sg = data->sg;
34b664a2
JH		 1026 host->part_buf_start = 0;
1027 host->part_buf_count = 0;
f95f3850 1028
b40af3aa 1029 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f8c58c11
DA		 1030
1031 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1032 temp = mci_readl(host, INTMASK);
1033 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1034 mci_writel(host, INTMASK, temp);
f8c58c11 1035 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 1036
1037 temp = mci_readl(host, CTRL);
1038 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1039 mci_writel(host, CTRL, temp);
52426899
SJ		 1040
1041 /*
1042 * Use the initial fifoth_val for PIO mode.
1043 * If next issued data may be transfered by DMA mode,
1044 * prev_blksz should be invalidated.
1045 */
1046 mci_writel(host, FIFOTH, host->fifoth_val);
1047 host->prev_blksz = 0;
1048 } else {
1049 /*
1050 * Keep the current block size.
1051 * It will be used to decide whether to update
1052 * fifoth register next time.
1053 */
1054 host->prev_blksz = data->blksz;
f95f3850
WN		 1055 }
1056}
1057
1058static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1059{
1060 struct dw_mci *host = slot->host;
1061 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1062 unsigned int cmd_status = 0;
1063
1064 mci_writel(host, CMDARG, arg);
0e3a22c0 1065 wmb(); /* drain writebuffer */
0bdbd0e8 1066 dw_mci_wait_while_busy(host, cmd);
f95f3850
WN		 1067 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1068
1069 while (time_before(jiffies, timeout)) {
1070 cmd_status = mci_readl(host, CMD);
1071 if (!(cmd_status & SDMMC_CMD_START))
1072 return;
1073 }
1074 dev_err(&slot->mmc->class_dev,
1075 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1076 cmd, arg, cmd_status);
1077}
1078
ab269128 1079static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 1080{
1081 struct dw_mci *host = slot->host;
fdf492a1 1082 unsigned int clock = slot->clock;
f95f3850 1083 u32 div;
9623b5b9 1084 u32 clk_en_a;
01730558
DA		 1085 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1086
1087 /* We must continue to set bit 28 in CMD until the change is complete */
1088 if (host->state == STATE_WAITING_CMD11_DONE)
1089 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
f95f3850 1090
fdf492a1
DA		 1091 if (!clock) {
1092 mci_writel(host, CLKENA, 0);
01730558 1093 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
fdf492a1
DA		 1094 } else if (clock != host->current_speed || force_clkinit) {
1095 div = host->bus_hz / clock;
1096 if (host->bus_hz % clock && host->bus_hz > clock)
f95f3850
WN		 1097 /*
1098 * move the + 1 after the divide to prevent
1099 * over-clocking the card.
1100 */
e419990b
SJ		 1101 div += 1;
1102
fdf492a1 1103 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850 1104
fdf492a1
DA		 1105 if ((clock << div) != slot->__clk_old || force_clkinit)
1106 dev_info(&slot->mmc->class_dev,
1107 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1108 slot->id, host->bus_hz, clock,
1109 div ? ((host->bus_hz / div) >> 1) :
1110 host->bus_hz, div);
f95f3850
WN		 1111
1112 /* disable clock */
1113 mci_writel(host, CLKENA, 0);
1114 mci_writel(host, CLKSRC, 0);
1115
1116 /* inform CIU */
01730558 1117 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850
WN		 1118
1119 /* set clock to desired speed */
1120 mci_writel(host, CLKDIV, div);
1121
1122 /* inform CIU */
01730558 1123 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1124
9623b5b9
DA		 1125 /* enable clock; only low power if no SDIO */
1126 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
b24c8b26 1127 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
9623b5b9
DA		 1128 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1129 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 1130
1131 /* inform CIU */
01730558 1132 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1133
fdf492a1
DA		 1134 /* keep the clock with reflecting clock dividor */
1135 slot->__clk_old = clock << div;
f95f3850
WN		 1136 }
1137
fdf492a1
DA		 1138 host->current_speed = clock;
1139
f95f3850 1140 /* Set the current slot bus width */
1d56c453 1141 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 1142}
1143
053b3ce6
SJ		 1144static void __dw_mci_start_request(struct dw_mci *host,
1145 struct dw_mci_slot *slot,
1146 struct mmc_command *cmd)
f95f3850
WN		 1147{
1148 struct mmc_request *mrq;
f95f3850
WN		 1149 struct mmc_data *data;
1150 u32 cmdflags;
1151
1152 mrq = slot->mrq;
f95f3850 1153
f95f3850
WN		 1154 host->cur_slot = slot;
1155 host->mrq = mrq;
1156
1157 host->pending_events = 0;
1158 host->completed_events = 0;
e352c813 1159 host->cmd_status = 0;
f95f3850 1160 host->data_status = 0;
e352c813 1161 host->dir_status = 0;
f95f3850 1162
053b3ce6 1163 data = cmd->data;
f95f3850 1164 if (data) {
f16afa88 1165 mci_writel(host, TMOUT, 0xFFFFFFFF);
f95f3850
WN		 1166 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1167 mci_writel(host, BLKSIZ, data->blksz);
1168 }
1169
f95f3850
WN		 1170 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1171
1172 /* this is the first command, send the initialization clock */
1173 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1174 cmdflags |= SDMMC_CMD_INIT;
1175
1176 if (data) {
1177 dw_mci_submit_data(host, data);
0e3a22c0 1178 wmb(); /* drain writebuffer */
f95f3850
WN		 1179 }
1180
1181 dw_mci_start_command(host, cmd, cmdflags);
1182
5c935165 1183 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
49ba0302
DA		 1184 unsigned long irqflags;
1185
5c935165 1186 /*
8886a6fd
DA		 1187 * Databook says to fail after 2ms w/ no response, but evidence
1188 * shows that sometimes the cmd11 interrupt takes over 130ms.
1189 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1190 * is just about to roll over.
49ba0302
DA		 1191 *
1192 * We do this whole thing under spinlock and only if the
1193 * command hasn't already completed (indicating the the irq
1194 * already ran so we don't want the timeout).
5c935165 1195 */
49ba0302
DA		 1196 spin_lock_irqsave(&host->irq_lock, irqflags);
1197 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1198 mod_timer(&host->cmd11_timer,
1199 jiffies + msecs_to_jiffies(500) + 1);
1200 spin_unlock_irqrestore(&host->irq_lock, irqflags);
5c935165
DA		 1201 }
1202
f95f3850
WN		 1203 if (mrq->stop)
1204 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
90c2143a
SJ		 1205 else
1206 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
f95f3850
WN		 1207}
1208
053b3ce6
SJ		 1209static void dw_mci_start_request(struct dw_mci *host,
1210 struct dw_mci_slot *slot)
1211{
1212 struct mmc_request *mrq = slot->mrq;
1213 struct mmc_command *cmd;
1214
1215 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1216 __dw_mci_start_request(host, slot, cmd);
1217}
1218
7456caae 1219/* must be called with host->lock held */
f95f3850
WN		 1220static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1221 struct mmc_request *mrq)
1222{
1223 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1224 host->state);
1225
f95f3850
WN		 1226 slot->mrq = mrq;
1227
01730558
DA		 1228 if (host->state == STATE_WAITING_CMD11_DONE) {
1229 dev_warn(&slot->mmc->class_dev,
1230 "Voltage change didn't complete\n");
1231 /*
1232 * this case isn't expected to happen, so we can
1233 * either crash here or just try to continue on
1234 * in the closest possible state
1235 */
1236 host->state = STATE_IDLE;
1237 }
1238
f95f3850
WN		 1239 if (host->state == STATE_IDLE) {
1240 host->state = STATE_SENDING_CMD;
1241 dw_mci_start_request(host, slot);
1242 } else {
1243 list_add_tail(&slot->queue_node, &host->queue);
1244 }
f95f3850
WN		 1245}
1246
1247static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1248{
1249 struct dw_mci_slot *slot = mmc_priv(mmc);
1250 struct dw_mci *host = slot->host;
1251
1252 WARN_ON(slot->mrq);
1253
7456caae
JH		 1254 /*
1255 * The check for card presence and queueing of the request must be
1256 * atomic, otherwise the card could be removed in between and the
1257 * request wouldn't fail until another card was inserted.
1258 */
1259 spin_lock_bh(&host->lock);
1260
f95f3850 1261 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 1262 spin_unlock_bh(&host->lock);
f95f3850
WN		 1263 mrq->cmd->error = -ENOMEDIUM;
1264 mmc_request_done(mmc, mrq);
1265 return;
1266 }
1267
f95f3850 1268 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 1269
1270 spin_unlock_bh(&host->lock);
f95f3850
WN		 1271}
1272
1273static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1274{
1275 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 1276 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 1277 u32 regs;
51da2240 1278 int ret;
f95f3850 1279
f95f3850 1280 switch (ios->bus_width) {
f95f3850
WN		 1281 case MMC_BUS_WIDTH_4:
1282 slot->ctype = SDMMC_CTYPE_4BIT;
1283 break;
c9b2a06f
JC		 1284 case MMC_BUS_WIDTH_8:
1285 slot->ctype = SDMMC_CTYPE_8BIT;
1286 break;
b2f7cb45
JC		 1287 default:
1288 /* set default 1 bit mode */
1289 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 1290 }
1291
3f514291
SJ		 1292 regs = mci_readl(slot->host, UHS_REG);
1293
41babf75 1294 /* DDR mode set */
80113132
SJ		 1295 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1296 ios->timing == MMC_TIMING_MMC_HS400)
c69042a5 1297 regs |= ((0x1 << slot->id) << 16);
3f514291 1298 else
c69042a5 1299 regs &= ~((0x1 << slot->id) << 16);
3f514291
SJ		 1300
1301 mci_writel(slot->host, UHS_REG, regs);
f1d2736c 1302 slot->host->timing = ios->timing;
41babf75 1303
fdf492a1
DA		 1304 /*
1305 * Use mirror of ios->clock to prevent race with mmc
1306 * core ios update when finding the minimum.
1307 */
1308 slot->clock = ios->clock;
f95f3850 1309
cb27a843
JH		 1310 if (drv_data && drv_data->set_ios)
1311 drv_data->set_ios(slot->host, ios);
800d78bf 1312
f95f3850
WN		 1313 switch (ios->power_mode) {
1314 case MMC_POWER_UP:
51da2240
YC		 1315 if (!IS_ERR(mmc->supply.vmmc)) {
1316 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1317 ios->vdd);
1318 if (ret) {
1319 dev_err(slot->host->dev,
1320 "failed to enable vmmc regulator\n");
1321 /*return, if failed turn on vmmc*/
1322 return;
1323 }
1324 }
29d0d161
DA		 1325 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1326 regs = mci_readl(slot->host, PWREN);
1327 regs |= (1 << slot->id);
1328 mci_writel(slot->host, PWREN, regs);
1329 break;
1330 case MMC_POWER_ON:
d1f1dd86
DA		 1331 if (!slot->host->vqmmc_enabled) {
1332 if (!IS_ERR(mmc->supply.vqmmc)) {
1333 ret = regulator_enable(mmc->supply.vqmmc);
1334 if (ret < 0)
1335 dev_err(slot->host->dev,
1336 "failed to enable vqmmc\n");
1337 else
1338 slot->host->vqmmc_enabled = true;
1339
1340 } else {
1341 /* Keep track so we don't reset again */
51da2240 1342 slot->host->vqmmc_enabled = true;
d1f1dd86
DA		 1343 }
1344
1345 /* Reset our state machine after powering on */
1346 dw_mci_ctrl_reset(slot->host,
1347 SDMMC_CTRL_ALL_RESET_FLAGS);
51da2240 1348 }
655babbd
DA		 1349
1350 /* Adjust clock / bus width after power is up */
1351 dw_mci_setup_bus(slot, false);
1352
e6f34e2f
JH		 1353 break;
1354 case MMC_POWER_OFF:
655babbd
DA		 1355 /* Turn clock off before power goes down */
1356 dw_mci_setup_bus(slot, false);
1357
51da2240
YC		 1358 if (!IS_ERR(mmc->supply.vmmc))
1359 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1360
d1f1dd86 1361 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
51da2240 1362 regulator_disable(mmc->supply.vqmmc);
d1f1dd86 1363 slot->host->vqmmc_enabled = false;
51da2240 1364
4366dcc5
JC		 1365 regs = mci_readl(slot->host, PWREN);
1366 regs &= ~(1 << slot->id);
1367 mci_writel(slot->host, PWREN, regs);
f95f3850
WN		 1368 break;
1369 default:
1370 break;
1371 }
655babbd
DA		 1372
1373 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1374 slot->host->state = STATE_IDLE;
f95f3850
WN		 1375}
1376
01730558
DA		 1377static int dw_mci_card_busy(struct mmc_host *mmc)
1378{
1379 struct dw_mci_slot *slot = mmc_priv(mmc);
1380 u32 status;
1381
1382 /*
1383 * Check the busy bit which is low when DAT[3:0]
1384 * (the data lines) are 0000
1385 */
1386 status = mci_readl(slot->host, STATUS);
1387
1388 return !!(status & SDMMC_STATUS_BUSY);
1389}
1390
1391static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1392{
1393 struct dw_mci_slot *slot = mmc_priv(mmc);
1394 struct dw_mci *host = slot->host;
8f7849c4 1395 const struct dw_mci_drv_data *drv_data = host->drv_data;
01730558
DA		 1396 u32 uhs;
1397 u32 v18 = SDMMC_UHS_18V << slot->id;
01730558
DA		 1398 int ret;
1399
8f7849c4
ZG		 1400 if (drv_data && drv_data->switch_voltage)
1401 return drv_data->switch_voltage(mmc, ios);
1402
01730558
DA		 1403 /*
1404 * Program the voltage. Note that some instances of dw_mmc may use
1405 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1406 * does no harm but you need to set the regulator directly. Try both.
1407 */
1408 uhs = mci_readl(host, UHS_REG);
e0848f5d 1409 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
01730558 1410 uhs &= ~v18;
e0848f5d 1411 else
01730558 1412 uhs |= v18;
e0848f5d 1413
01730558 1414 if (!IS_ERR(mmc->supply.vqmmc)) {
e0848f5d 1415 ret = mmc_regulator_set_vqmmc(mmc, ios);
01730558
DA		 1416
1417 if (ret) {
b19caf37 1418 dev_dbg(&mmc->class_dev,
e0848f5d
DA		 1419 "Regulator set error %d - %s V\n",
1420 ret, uhs & v18 ? "1.8" : "3.3");
01730558
DA		 1421 return ret;
1422 }
1423 }
1424 mci_writel(host, UHS_REG, uhs);
1425
1426 return 0;
1427}
1428
f95f3850
WN		 1429static int dw_mci_get_ro(struct mmc_host *mmc)
1430{
1431 int read_only;
1432 struct dw_mci_slot *slot = mmc_priv(mmc);
9795a846 1433 int gpio_ro = mmc_gpio_get_ro(mmc);
f95f3850
WN		 1434
1435 /* Use platform get_ro function, else try on board write protect */
eff8f2f5 1436 if (!IS_ERR_VALUE(gpio_ro))
9795a846 1437 read_only = gpio_ro;
f95f3850
WN		 1438 else
1439 read_only =
1440 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1441
1442 dev_dbg(&mmc->class_dev, "card is %s\n",
1443 read_only ? "read-only" : "read-write");
1444
1445 return read_only;
1446}
1447
1448static int dw_mci_get_cd(struct mmc_host *mmc)
1449{
1450 int present;
1451 struct dw_mci_slot *slot = mmc_priv(mmc);
1452 struct dw_mci_board *brd = slot->host->pdata;
7cf347bd
ZG		 1453 struct dw_mci *host = slot->host;
1454 int gpio_cd = mmc_gpio_get_cd(mmc);
f95f3850
WN		 1455
1456 /* Use platform get_cd function, else try onboard card detect */
4de3bf66
ZG		 1457 if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1458 (mmc->caps & MMC_CAP_NONREMOVABLE))
fc3d7720 1459 present = 1;
bf626e55 1460 else if (!IS_ERR_VALUE(gpio_cd))
7cf347bd 1461 present = gpio_cd;
f95f3850
WN		 1462 else
1463 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1464 == 0 ? 1 : 0;
1465
7cf347bd 1466 spin_lock_bh(&host->lock);
bf626e55
ZG		 1467 if (present) {
1468 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1469 dev_dbg(&mmc->class_dev, "card is present\n");
bf626e55
ZG		 1470 } else {
1471 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1472 dev_dbg(&mmc->class_dev, "card is not present\n");
bf626e55 1473 }
7cf347bd 1474 spin_unlock_bh(&host->lock);
f95f3850
WN		 1475
1476 return present;
1477}
1478
b24c8b26 1479static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
9623b5b9 1480{
b24c8b26 1481 struct dw_mci_slot *slot = mmc_priv(mmc);
9623b5b9 1482 struct dw_mci *host = slot->host;
9623b5b9 1483
b24c8b26
DA		 1484 /*
1485 * Low power mode will stop the card clock when idle. According to the
1486 * description of the CLKENA register we should disable low power mode
1487 * for SDIO cards if we need SDIO interrupts to work.
1488 */
1489 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1490 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1491 u32 clk_en_a_old;
1492 u32 clk_en_a;
9623b5b9 1493
b24c8b26
DA		 1494 clk_en_a_old = mci_readl(host, CLKENA);
1495
1496 if (card->type == MMC_TYPE_SDIO ||
1497 card->type == MMC_TYPE_SD_COMBO) {
1498 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1499 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1500 } else {
1501 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1502 clk_en_a = clk_en_a_old | clken_low_pwr;
1503 }
1504
1505 if (clk_en_a != clk_en_a_old) {
1506 mci_writel(host, CLKENA, clk_en_a);
1507 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1508 SDMMC_CMD_PRV_DAT_WAIT, 0);
1509 }
9623b5b9
DA		 1510 }
1511}
1512
1a5c8e1f
SH		 1513static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1514{
1515 struct dw_mci_slot *slot = mmc_priv(mmc);
1516 struct dw_mci *host = slot->host;
f8c58c11 1517 unsigned long irqflags;
1a5c8e1f
SH		 1518 u32 int_mask;
1519
f8c58c11
DA		 1520 spin_lock_irqsave(&host->irq_lock, irqflags);
1521
1a5c8e1f
SH		 1522 /* Enable/disable Slot Specific SDIO interrupt */
1523 int_mask = mci_readl(host, INTMASK);
b24c8b26
DA		 1524 if (enb)
1525 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1526 else
1527 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1528 mci_writel(host, INTMASK, int_mask);
f8c58c11
DA		 1529
1530 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1a5c8e1f
SH		 1531}
1532
0976f16d
SJ		 1533static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1534{
1535 struct dw_mci_slot *slot = mmc_priv(mmc);
1536 struct dw_mci *host = slot->host;
1537 const struct dw_mci_drv_data *drv_data = host->drv_data;
0e3a22c0 1538 int err = -EINVAL;
0976f16d 1539
0976f16d 1540 if (drv_data && drv_data->execute_tuning)
9979dbe5 1541 err = drv_data->execute_tuning(slot, opcode);
0976f16d
SJ		 1542 return err;
1543}
1544
0e3a22c0
SL		 1545static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1546 struct mmc_ios *ios)
80113132
SJ		 1547{
1548 struct dw_mci_slot *slot = mmc_priv(mmc);
1549 struct dw_mci *host = slot->host;
1550 const struct dw_mci_drv_data *drv_data = host->drv_data;
1551
1552 if (drv_data && drv_data->prepare_hs400_tuning)
1553 return drv_data->prepare_hs400_tuning(host, ios);
1554
1555 return 0;
1556}
1557
f95f3850 1558static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 1559 .request = dw_mci_request,
9aa51408
SJ		 1560 .pre_req = dw_mci_pre_req,
1561 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 1562 .set_ios = dw_mci_set_ios,
1563 .get_ro = dw_mci_get_ro,
1564 .get_cd = dw_mci_get_cd,
1565 .enable_sdio_irq = dw_mci_enable_sdio_irq,
0976f16d 1566 .execute_tuning = dw_mci_execute_tuning,
01730558
DA		 1567 .card_busy = dw_mci_card_busy,
1568 .start_signal_voltage_switch = dw_mci_switch_voltage,
b24c8b26 1569 .init_card = dw_mci_init_card,
80113132 1570 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
f95f3850
WN		 1571};
1572
1573static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1574 __releases(&host->lock)
1575 __acquires(&host->lock)
1576{
1577 struct dw_mci_slot *slot;
1578 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1579
1580 WARN_ON(host->cmd || host->data);
1581
1582 host->cur_slot->mrq = NULL;
1583 host->mrq = NULL;
1584 if (!list_empty(&host->queue)) {
1585 slot = list_entry(host->queue.next,
1586 struct dw_mci_slot, queue_node);
1587 list_del(&slot->queue_node);
4a90920c 1588 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 1589 mmc_hostname(slot->mmc));
1590 host->state = STATE_SENDING_CMD;
1591 dw_mci_start_request(host, slot);
1592 } else {
4a90920c 1593 dev_vdbg(host->dev, "list empty\n");
01730558
DA		 1594
1595 if (host->state == STATE_SENDING_CMD11)
1596 host->state = STATE_WAITING_CMD11_DONE;
1597 else
1598 host->state = STATE_IDLE;
f95f3850
WN		 1599 }
1600
1601 spin_unlock(&host->lock);
1602 mmc_request_done(prev_mmc, mrq);
1603 spin_lock(&host->lock);
1604}
1605
e352c813 1606static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
f95f3850
WN		 1607{
1608 u32 status = host->cmd_status;
1609
1610 host->cmd_status = 0;
1611
1612 /* Read the response from the card (up to 16 bytes) */
1613 if (cmd->flags & MMC_RSP_PRESENT) {
1614 if (cmd->flags & MMC_RSP_136) {
1615 cmd->resp[3] = mci_readl(host, RESP0);
1616 cmd->resp[2] = mci_readl(host, RESP1);
1617 cmd->resp[1] = mci_readl(host, RESP2);
1618 cmd->resp[0] = mci_readl(host, RESP3);
1619 } else {
1620 cmd->resp[0] = mci_readl(host, RESP0);
1621 cmd->resp[1] = 0;
1622 cmd->resp[2] = 0;
1623 cmd->resp[3] = 0;
1624 }
1625 }
1626
1627 if (status & SDMMC_INT_RTO)
1628 cmd->error = -ETIMEDOUT;
1629 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1630 cmd->error = -EILSEQ;
1631 else if (status & SDMMC_INT_RESP_ERR)
1632 cmd->error = -EIO;
1633 else
1634 cmd->error = 0;
1635
1636 if (cmd->error) {
1637 /* newer ip versions need a delay between retries */
1638 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1639 mdelay(20);
f95f3850 1640 }
e352c813
SJ		 1641
1642 return cmd->error;
1643}
1644
1645static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1646{
31bff450 1647 u32 status = host->data_status;
e352c813
SJ		 1648
1649 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1650 if (status & SDMMC_INT_DRTO) {
1651 data->error = -ETIMEDOUT;
1652 } else if (status & SDMMC_INT_DCRC) {
1653 data->error = -EILSEQ;
1654 } else if (status & SDMMC_INT_EBE) {
1655 if (host->dir_status ==
1656 DW_MCI_SEND_STATUS) {
1657 /*
1658 * No data CRC status was returned.
1659 * The number of bytes transferred
1660 * will be exaggerated in PIO mode.
1661 */
1662 data->bytes_xfered = 0;
1663 data->error = -ETIMEDOUT;
1664 } else if (host->dir_status ==
1665 DW_MCI_RECV_STATUS) {
1666 data->error = -EIO;
1667 }
1668 } else {
1669 /* SDMMC_INT_SBE is included */
1670 data->error = -EIO;
1671 }
1672
e6cc0123 1673 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
e352c813
SJ		 1674
1675 /*
1676 * After an error, there may be data lingering
31bff450 1677 * in the FIFO
e352c813 1678 */
3a33a94c 1679 dw_mci_reset(host);
e352c813
SJ		 1680 } else {
1681 data->bytes_xfered = data->blocks * data->blksz;
1682 data->error = 0;
1683 }
1684
1685 return data->error;
f95f3850
WN		 1686}
1687
57e10486
AK		 1688static void dw_mci_set_drto(struct dw_mci *host)
1689{
1690 unsigned int drto_clks;
1691 unsigned int drto_ms;
1692
1693 drto_clks = mci_readl(host, TMOUT) >> 8;
1694 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1695
1696 /* add a bit spare time */
1697 drto_ms += 10;
1698
1699 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1700}
1701
f95f3850
WN		 1702static void dw_mci_tasklet_func(unsigned long priv)
1703{
1704 struct dw_mci *host = (struct dw_mci *)priv;
1705 struct mmc_data *data;
1706 struct mmc_command *cmd;
e352c813 1707 struct mmc_request *mrq;
f95f3850
WN		 1708 enum dw_mci_state state;
1709 enum dw_mci_state prev_state;
e352c813 1710 unsigned int err;
f95f3850
WN		 1711
1712 spin_lock(&host->lock);
1713
1714 state = host->state;
1715 data = host->data;
e352c813 1716 mrq = host->mrq;
f95f3850
WN		 1717
1718 do {
1719 prev_state = state;
1720
1721 switch (state) {
1722 case STATE_IDLE:
01730558 1723 case STATE_WAITING_CMD11_DONE:
f95f3850
WN		 1724 break;
1725
01730558 1726 case STATE_SENDING_CMD11:
f95f3850
WN		 1727 case STATE_SENDING_CMD:
1728 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1729 &host->pending_events))
1730 break;
1731
1732 cmd = host->cmd;
1733 host->cmd = NULL;
1734 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
e352c813
SJ		 1735 err = dw_mci_command_complete(host, cmd);
1736 if (cmd == mrq->sbc && !err) {
053b3ce6
SJ		 1737 prev_state = state = STATE_SENDING_CMD;
1738 __dw_mci_start_request(host, host->cur_slot,
e352c813 1739 mrq->cmd);
053b3ce6
SJ		 1740 goto unlock;
1741 }
1742
e352c813 1743 if (cmd->data && err) {
71abb133 1744 dw_mci_stop_dma(host);
90c2143a
SJ		 1745 send_stop_abort(host, data);
1746 state = STATE_SENDING_STOP;
1747 break;
71abb133
SJ		 1748 }
1749
e352c813
SJ		 1750 if (!cmd->data || err) {
1751 dw_mci_request_end(host, mrq);
f95f3850
WN		 1752 goto unlock;
1753 }
1754
1755 prev_state = state = STATE_SENDING_DATA;
1756 /* fall through */
1757
1758 case STATE_SENDING_DATA:
2aa35465
DA		 1759 /*
1760 * We could get a data error and never a transfer
1761 * complete so we'd better check for it here.
1762 *
1763 * Note that we don't really care if we also got a
1764 * transfer complete; stopping the DMA and sending an
1765 * abort won't hurt.
1766 */
f95f3850
WN		 1767 if (test_and_clear_bit(EVENT_DATA_ERROR,
1768 &host->pending_events)) {
1769 dw_mci_stop_dma(host);
bdb9a90b 1770 if (data->stop ||
1771 !(host->data_status & (SDMMC_INT_DRTO |
1772 SDMMC_INT_EBE)))
1773 send_stop_abort(host, data);
f95f3850
WN		 1774 state = STATE_DATA_ERROR;
1775 break;
1776 }
1777
1778 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
57e10486
AK		 1779 &host->pending_events)) {
1780 /*
1781 * If all data-related interrupts don't come
1782 * within the given time in reading data state.
1783 */
1784 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1785 (host->dir_status == DW_MCI_RECV_STATUS))
1786 dw_mci_set_drto(host);
f95f3850 1787 break;
57e10486 1788 }
f95f3850
WN		 1789
1790 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2aa35465
DA		 1791
1792 /*
1793 * Handle an EVENT_DATA_ERROR that might have shown up
1794 * before the transfer completed. This might not have
1795 * been caught by the check above because the interrupt
1796 * could have gone off between the previous check and
1797 * the check for transfer complete.
1798 *
1799 * Technically this ought not be needed assuming we
1800 * get a DATA_COMPLETE eventually (we'll notice the
1801 * error and end the request), but it shouldn't hurt.
1802 *
1803 * This has the advantage of sending the stop command.
1804 */
1805 if (test_and_clear_bit(EVENT_DATA_ERROR,
1806 &host->pending_events)) {
1807 dw_mci_stop_dma(host);
bdb9a90b 1808 if (data->stop ||
1809 !(host->data_status & (SDMMC_INT_DRTO |
1810 SDMMC_INT_EBE)))
1811 send_stop_abort(host, data);
2aa35465
DA		 1812 state = STATE_DATA_ERROR;
1813 break;
1814 }
f95f3850 1815 prev_state = state = STATE_DATA_BUSY;
2aa35465 1816
f95f3850
WN		 1817 /* fall through */
1818
1819 case STATE_DATA_BUSY:
1820 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
57e10486
AK		 1821 &host->pending_events)) {
1822 /*
1823 * If data error interrupt comes but data over
1824 * interrupt doesn't come within the given time.
1825 * in reading data state.
1826 */
1827 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1828 (host->dir_status == DW_MCI_RECV_STATUS))
1829 dw_mci_set_drto(host);
f95f3850 1830 break;
57e10486 1831 }
f95f3850
WN		 1832
1833 host->data = NULL;
1834 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
e352c813
SJ		 1835 err = dw_mci_data_complete(host, data);
1836
1837 if (!err) {
1838 if (!data->stop || mrq->sbc) {
17c8bc85 1839 if (mrq->sbc && data->stop)
e352c813
SJ		 1840 data->stop->error = 0;
1841 dw_mci_request_end(host, mrq);
1842 goto unlock;
f95f3850 1843 }
f95f3850 1844
e352c813
SJ		 1845 /* stop command for open-ended transfer*/
1846 if (data->stop)
1847 send_stop_abort(host, data);
2aa35465
DA		 1848 } else {
1849 /*
1850 * If we don't have a command complete now we'll
1851 * never get one since we just reset everything;
1852 * better end the request.
1853 *
1854 * If we do have a command complete we'll fall
1855 * through to the SENDING_STOP command and
1856 * everything will be peachy keen.
1857 */
1858 if (!test_bit(EVENT_CMD_COMPLETE,
1859 &host->pending_events)) {
1860 host->cmd = NULL;
1861 dw_mci_request_end(host, mrq);
1862 goto unlock;
1863 }
053b3ce6
SJ		 1864 }
1865
e352c813
SJ		 1866 /*
1867 * If err has non-zero,
1868 * stop-abort command has been already issued.
1869 */
f95f3850 1870 prev_state = state = STATE_SENDING_STOP;
e352c813 1871
f95f3850
WN		 1872 /* fall through */
1873
1874 case STATE_SENDING_STOP:
1875 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1876 &host->pending_events))
1877 break;
1878
71abb133 1879 /* CMD error in data command */
31bff450 1880 if (mrq->cmd->error && mrq->data)
3a33a94c 1881 dw_mci_reset(host);
71abb133 1882
f95f3850 1883 host->cmd = NULL;
71abb133 1884 host->data = NULL;
90c2143a 1885
e352c813
SJ		 1886 if (mrq->stop)
1887 dw_mci_command_complete(host, mrq->stop);
90c2143a
SJ		 1888 else
1889 host->cmd_status = 0;
1890
e352c813 1891 dw_mci_request_end(host, mrq);
f95f3850
WN		 1892 goto unlock;
1893
1894 case STATE_DATA_ERROR:
1895 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1896 &host->pending_events))
1897 break;
1898
1899 state = STATE_DATA_BUSY;
1900 break;
1901 }
1902 } while (state != prev_state);
1903
1904 host->state = state;
1905unlock:
1906 spin_unlock(&host->lock);
1907
1908}
1909
34b664a2
JH		 1910/* push final bytes to part_buf, only use during push */
1911static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1912{
34b664a2
JH		 1913 memcpy((void *)&host->part_buf, buf, cnt);
1914 host->part_buf_count = cnt;
1915}
f95f3850 1916
34b664a2
JH		 1917/* append bytes to part_buf, only use during push */
1918static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1919{
1920 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1921 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1922 host->part_buf_count += cnt;
1923 return cnt;
1924}
f95f3850 1925
34b664a2
JH		 1926/* pull first bytes from part_buf, only use during pull */
1927static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1928{
0e3a22c0 1929 cnt = min_t(int, cnt, host->part_buf_count);
34b664a2
JH		 1930 if (cnt) {
1931 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1932 cnt);
1933 host->part_buf_count -= cnt;
1934 host->part_buf_start += cnt;
f95f3850 1935 }
34b664a2 1936 return cnt;
f95f3850
WN		 1937}
1938
34b664a2
JH		 1939/* pull final bytes from the part_buf, assuming it's just been filled */
1940static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1941{
34b664a2
JH		 1942 memcpy(buf, &host->part_buf, cnt);
1943 host->part_buf_start = cnt;
1944 host->part_buf_count = (1 << host->data_shift) - cnt;
1945}
f95f3850 1946
34b664a2
JH		 1947static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1948{
cfbeb59c
MC		 1949 struct mmc_data *data = host->data;
1950 int init_cnt = cnt;
1951
34b664a2
JH		 1952 /* try and push anything in the part_buf */
1953 if (unlikely(host->part_buf_count)) {
1954 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 1955
34b664a2
JH		 1956 buf += len;
1957 cnt -= len;
cfbeb59c 1958 if (host->part_buf_count == 2) {
76184ac1 1959 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 1960 host->part_buf_count = 0;
1961 }
1962 }
1963#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1964 if (unlikely((unsigned long)buf & 0x1)) {
1965 while (cnt >= 2) {
1966 u16 aligned_buf[64];
1967 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1968 int items = len >> 1;
1969 int i;
1970 /* memcpy from input buffer into aligned buffer */
1971 memcpy(aligned_buf, buf, len);
1972 buf += len;
1973 cnt -= len;
1974 /* push data from aligned buffer into fifo */
1975 for (i = 0; i < items; ++i)
76184ac1 1976 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 1977 }
1978 } else
1979#endif
1980 {
1981 u16 *pdata = buf;
0e3a22c0 1982
34b664a2 1983 for (; cnt >= 2; cnt -= 2)
76184ac1 1984 mci_fifo_writew(host->fifo_reg, *pdata++);
34b664a2
JH		 1985 buf = pdata;
1986 }
1987 /* put anything remaining in the part_buf */
1988 if (cnt) {
1989 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 1990 /* Push data if we have reached the expected data length */
1991 if ((data->bytes_xfered + init_cnt) ==
1992 (data->blksz * data->blocks))
76184ac1 1993 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 1994 }
1995}
f95f3850 1996
34b664a2
JH		 1997static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1998{
1999#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2000 if (unlikely((unsigned long)buf & 0x1)) {
2001 while (cnt >= 2) {
2002 /* pull data from fifo into aligned buffer */
2003 u16 aligned_buf[64];
2004 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2005 int items = len >> 1;
2006 int i;
0e3a22c0 2007
34b664a2 2008 for (i = 0; i < items; ++i)
76184ac1 2009 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2010 /* memcpy from aligned buffer into output buffer */
2011 memcpy(buf, aligned_buf, len);
2012 buf += len;
2013 cnt -= len;
2014 }
2015 } else
2016#endif
2017 {
2018 u16 *pdata = buf;
0e3a22c0 2019
34b664a2 2020 for (; cnt >= 2; cnt -= 2)
76184ac1 2021 *pdata++ = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2022 buf = pdata;
2023 }
2024 if (cnt) {
76184ac1 2025 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
34b664a2 2026 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2027 }
2028}
2029
2030static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2031{
cfbeb59c
MC		 2032 struct mmc_data *data = host->data;
2033 int init_cnt = cnt;
2034
34b664a2
JH		 2035 /* try and push anything in the part_buf */
2036 if (unlikely(host->part_buf_count)) {
2037 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2038
34b664a2
JH		 2039 buf += len;
2040 cnt -= len;
cfbeb59c 2041 if (host->part_buf_count == 4) {
76184ac1 2042 mci_fifo_writel(host->fifo_reg, host->part_buf32);
34b664a2
JH		 2043 host->part_buf_count = 0;
2044 }
2045 }
2046#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2047 if (unlikely((unsigned long)buf & 0x3)) {
2048 while (cnt >= 4) {
2049 u32 aligned_buf[32];
2050 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2051 int items = len >> 2;
2052 int i;
2053 /* memcpy from input buffer into aligned buffer */
2054 memcpy(aligned_buf, buf, len);
2055 buf += len;
2056 cnt -= len;
2057 /* push data from aligned buffer into fifo */
2058 for (i = 0; i < items; ++i)
76184ac1 2059 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2060 }
2061 } else
2062#endif
2063 {
2064 u32 *pdata = buf;
0e3a22c0 2065
34b664a2 2066 for (; cnt >= 4; cnt -= 4)
76184ac1 2067 mci_fifo_writel(host->fifo_reg, *pdata++);
34b664a2
JH		 2068 buf = pdata;
2069 }
2070 /* put anything remaining in the part_buf */
2071 if (cnt) {
2072 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2073 /* Push data if we have reached the expected data length */
2074 if ((data->bytes_xfered + init_cnt) ==
2075 (data->blksz * data->blocks))
76184ac1 2076 mci_fifo_writel(host->fifo_reg, host->part_buf32);
f95f3850
WN		 2077 }
2078}
2079
2080static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2081{
34b664a2
JH		 2082#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2083 if (unlikely((unsigned long)buf & 0x3)) {
2084 while (cnt >= 4) {
2085 /* pull data from fifo into aligned buffer */
2086 u32 aligned_buf[32];
2087 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2088 int items = len >> 2;
2089 int i;
0e3a22c0 2090
34b664a2 2091 for (i = 0; i < items; ++i)
76184ac1 2092 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2093 /* memcpy from aligned buffer into output buffer */
2094 memcpy(buf, aligned_buf, len);
2095 buf += len;
2096 cnt -= len;
2097 }
2098 } else
2099#endif
2100 {
2101 u32 *pdata = buf;
0e3a22c0 2102
34b664a2 2103 for (; cnt >= 4; cnt -= 4)
76184ac1 2104 *pdata++ = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2105 buf = pdata;
2106 }
2107 if (cnt) {
76184ac1 2108 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
34b664a2 2109 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2110 }
2111}
2112
2113static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2114{
cfbeb59c
MC		 2115 struct mmc_data *data = host->data;
2116 int init_cnt = cnt;
2117
34b664a2
JH		 2118 /* try and push anything in the part_buf */
2119 if (unlikely(host->part_buf_count)) {
2120 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2121
34b664a2
JH		 2122 buf += len;
2123 cnt -= len;
c09fbd74 2124
cfbeb59c 2125 if (host->part_buf_count == 8) {
76184ac1 2126 mci_fifo_writeq(host->fifo_reg, host->part_buf);
34b664a2
JH		 2127 host->part_buf_count = 0;
2128 }
2129 }
2130#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2131 if (unlikely((unsigned long)buf & 0x7)) {
2132 while (cnt >= 8) {
2133 u64 aligned_buf[16];
2134 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2135 int items = len >> 3;
2136 int i;
2137 /* memcpy from input buffer into aligned buffer */
2138 memcpy(aligned_buf, buf, len);
2139 buf += len;
2140 cnt -= len;
2141 /* push data from aligned buffer into fifo */
2142 for (i = 0; i < items; ++i)
76184ac1 2143 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2144 }
2145 } else
2146#endif
2147 {
2148 u64 *pdata = buf;
0e3a22c0 2149
34b664a2 2150 for (; cnt >= 8; cnt -= 8)
76184ac1 2151 mci_fifo_writeq(host->fifo_reg, *pdata++);
34b664a2
JH		 2152 buf = pdata;
2153 }
2154 /* put anything remaining in the part_buf */
2155 if (cnt) {
2156 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2157 /* Push data if we have reached the expected data length */
2158 if ((data->bytes_xfered + init_cnt) ==
2159 (data->blksz * data->blocks))
76184ac1 2160 mci_fifo_writeq(host->fifo_reg, host->part_buf);
f95f3850
WN		 2161 }
2162}
2163
2164static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2165{
34b664a2
JH		 2166#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2167 if (unlikely((unsigned long)buf & 0x7)) {
2168 while (cnt >= 8) {
2169 /* pull data from fifo into aligned buffer */
2170 u64 aligned_buf[16];
2171 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2172 int items = len >> 3;
2173 int i;
0e3a22c0 2174
34b664a2 2175 for (i = 0; i < items; ++i)
76184ac1
BD		 2176 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2177
34b664a2
JH		 2178 /* memcpy from aligned buffer into output buffer */
2179 memcpy(buf, aligned_buf, len);
2180 buf += len;
2181 cnt -= len;
2182 }
2183 } else
2184#endif
2185 {
2186 u64 *pdata = buf;
0e3a22c0 2187
34b664a2 2188 for (; cnt >= 8; cnt -= 8)
76184ac1 2189 *pdata++ = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2190 buf = pdata;
2191 }
2192 if (cnt) {
76184ac1 2193 host->part_buf = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2194 dw_mci_pull_final_bytes(host, buf, cnt);
2195 }
2196}
f95f3850 2197
34b664a2
JH		 2198static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2199{
2200 int len;
f95f3850 2201
34b664a2
JH		 2202 /* get remaining partial bytes */
2203 len = dw_mci_pull_part_bytes(host, buf, cnt);
2204 if (unlikely(len == cnt))
2205 return;
2206 buf += len;
2207 cnt -= len;
2208
2209 /* get the rest of the data */
2210 host->pull_data(host, buf, cnt);
f95f3850
WN		 2211}
2212
87a74d39 2213static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
f95f3850 2214{
f9c2a0dc
SJ		 2215 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2216 void *buf;
2217 unsigned int offset;
f95f3850
WN		 2218 struct mmc_data *data = host->data;
2219 int shift = host->data_shift;
2220 u32 status;
3e4b0d8b 2221 unsigned int len;
f9c2a0dc 2222 unsigned int remain, fcnt;
f95f3850
WN		 2223
2224 do {
f9c2a0dc
SJ		 2225 if (!sg_miter_next(sg_miter))
2226 goto done;
2227
4225fc85 2228 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2229 buf = sg_miter->addr;
2230 remain = sg_miter->length;
2231 offset = 0;
2232
2233 do {
2234 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2235 << shift) + host->part_buf_count;
2236 len = min(remain, fcnt);
2237 if (!len)
2238 break;
34b664a2 2239 dw_mci_pull_data(host, (void *)(buf + offset), len);
3e4b0d8b 2240 data->bytes_xfered += len;
f95f3850 2241 offset += len;
f9c2a0dc
SJ		 2242 remain -= len;
2243 } while (remain);
f95f3850 2244
e74f3a9c 2245 sg_miter->consumed = offset;
f95f3850
WN		 2246 status = mci_readl(host, MINTSTS);
2247 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
87a74d39
KK		 2248 /* if the RXDR is ready read again */
2249 } while ((status & SDMMC_INT_RXDR) ||
2250 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
f9c2a0dc
SJ		 2251
2252 if (!remain) {
2253 if (!sg_miter_next(sg_miter))
2254 goto done;
2255 sg_miter->consumed = 0;
2256 }
2257 sg_miter_stop(sg_miter);
f95f3850
WN		 2258 return;
2259
2260done:
f9c2a0dc
SJ		 2261 sg_miter_stop(sg_miter);
2262 host->sg = NULL;
0e3a22c0 2263 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2264 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2265}
2266
2267static void dw_mci_write_data_pio(struct dw_mci *host)
2268{
f9c2a0dc
SJ		 2269 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2270 void *buf;
2271 unsigned int offset;
f95f3850
WN		 2272 struct mmc_data *data = host->data;
2273 int shift = host->data_shift;
2274 u32 status;
3e4b0d8b 2275 unsigned int len;
f9c2a0dc
SJ		 2276 unsigned int fifo_depth = host->fifo_depth;
2277 unsigned int remain, fcnt;
f95f3850
WN		 2278
2279 do {
f9c2a0dc
SJ		 2280 if (!sg_miter_next(sg_miter))
2281 goto done;
2282
4225fc85 2283 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2284 buf = sg_miter->addr;
2285 remain = sg_miter->length;
2286 offset = 0;
2287
2288 do {
2289 fcnt = ((fifo_depth -
2290 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2291 << shift) - host->part_buf_count;
2292 len = min(remain, fcnt);
2293 if (!len)
2294 break;
f95f3850 2295 host->push_data(host, (void *)(buf + offset), len);
3e4b0d8b 2296 data->bytes_xfered += len;
f95f3850 2297 offset += len;
f9c2a0dc
SJ		 2298 remain -= len;
2299 } while (remain);
f95f3850 2300
e74f3a9c 2301 sg_miter->consumed = offset;
f95f3850
WN		 2302 status = mci_readl(host, MINTSTS);
2303 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 2304 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f9c2a0dc
SJ		 2305
2306 if (!remain) {
2307 if (!sg_miter_next(sg_miter))
2308 goto done;
2309 sg_miter->consumed = 0;
2310 }
2311 sg_miter_stop(sg_miter);
f95f3850
WN		 2312 return;
2313
2314done:
f9c2a0dc
SJ		 2315 sg_miter_stop(sg_miter);
2316 host->sg = NULL;
0e3a22c0 2317 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2318 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2319}
2320
2321static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2322{
2323 if (!host->cmd_status)
2324 host->cmd_status = status;
2325
0e3a22c0 2326 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2327
2328 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2329 tasklet_schedule(&host->tasklet);
2330}
2331
6130e7a9
DA		 2332static void dw_mci_handle_cd(struct dw_mci *host)
2333{
2334 int i;
2335
2336 for (i = 0; i < host->num_slots; i++) {
2337 struct dw_mci_slot *slot = host->slot[i];
2338
2339 if (!slot)
2340 continue;
2341
2342 if (slot->mmc->ops->card_event)
2343 slot->mmc->ops->card_event(slot->mmc);
2344 mmc_detect_change(slot->mmc,
2345 msecs_to_jiffies(host->pdata->detect_delay_ms));
2346 }
2347}
2348
f95f3850
WN		 2349static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2350{
2351 struct dw_mci *host = dev_id;
182c9081 2352 u32 pending;
1a5c8e1f 2353 int i;
f95f3850 2354
1fb5f68a
MC		 2355 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2356
476d79f1
DA		 2357 /*
2358 * DTO fix - version 2.10a and below, and only if internal DMA
2359 * is configured.
2360 */
2361 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2362 if (!pending &&
2363 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2364 pending |= SDMMC_INT_DATA_OVER;
2365 }
f95f3850 2366
476d79f1 2367 if (pending) {
01730558
DA		 2368 /* Check volt switch first, since it can look like an error */
2369 if ((host->state == STATE_SENDING_CMD11) &&
2370 (pending & SDMMC_INT_VOLT_SWITCH)) {
49ba0302 2371 unsigned long irqflags;
5c935165 2372
01730558
DA		 2373 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2374 pending &= ~SDMMC_INT_VOLT_SWITCH;
49ba0302
DA		 2375
2376 /*
2377 * Hold the lock; we know cmd11_timer can't be kicked
2378 * off after the lock is released, so safe to delete.
2379 */
2380 spin_lock_irqsave(&host->irq_lock, irqflags);
01730558 2381 dw_mci_cmd_interrupt(host, pending);
49ba0302
DA		 2382 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2383
2384 del_timer(&host->cmd11_timer);
01730558
DA		 2385 }
2386
f95f3850
WN		 2387 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2388 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 2389 host->cmd_status = pending;
0e3a22c0 2390 smp_wmb(); /* drain writebuffer */
f95f3850 2391 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 2392 }
2393
2394 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2395 /* if there is an error report DATA_ERROR */
2396 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 2397 host->data_status = pending;
0e3a22c0 2398 smp_wmb(); /* drain writebuffer */
f95f3850 2399 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 2400 tasklet_schedule(&host->tasklet);
f95f3850
WN		 2401 }
2402
2403 if (pending & SDMMC_INT_DATA_OVER) {
57e10486
AK		 2404 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
2405 del_timer(&host->dto_timer);
2406
f95f3850
WN		 2407 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2408 if (!host->data_status)
182c9081 2409 host->data_status = pending;
0e3a22c0 2410 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2411 if (host->dir_status == DW_MCI_RECV_STATUS) {
2412 if (host->sg != NULL)
87a74d39 2413 dw_mci_read_data_pio(host, true);
f95f3850
WN		 2414 }
2415 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2416 tasklet_schedule(&host->tasklet);
2417 }
2418
2419 if (pending & SDMMC_INT_RXDR) {
2420 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 2421 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
87a74d39 2422 dw_mci_read_data_pio(host, false);
f95f3850
WN		 2423 }
2424
2425 if (pending & SDMMC_INT_TXDR) {
2426 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 2427 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 2428 dw_mci_write_data_pio(host);
2429 }
2430
2431 if (pending & SDMMC_INT_CMD_DONE) {
2432 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 2433 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 2434 }
2435
2436 if (pending & SDMMC_INT_CD) {
2437 mci_writel(host, RINTSTS, SDMMC_INT_CD);
6130e7a9 2438 dw_mci_handle_cd(host);
f95f3850
WN		 2439 }
2440
1a5c8e1f
SH		 2441 /* Handle SDIO Interrupts */
2442 for (i = 0; i < host->num_slots; i++) {
2443 struct dw_mci_slot *slot = host->slot[i];
ed2540ef
DA		 2444
2445 if (!slot)
2446 continue;
2447
76756234
AK		 2448 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2449 mci_writel(host, RINTSTS,
2450 SDMMC_INT_SDIO(slot->sdio_id));
1a5c8e1f
SH		 2451 mmc_signal_sdio_irq(slot->mmc);
2452 }
2453 }
2454
1fb5f68a 2455 }
f95f3850 2456
3fc7eaef
SL		 2457 if (host->use_dma != TRANS_MODE_IDMAC)
2458 return IRQ_HANDLED;
2459
2460 /* Handle IDMA interrupts */
69d99fdc
PT		 2461 if (host->dma_64bit_address == 1) {
2462 pending = mci_readl(host, IDSTS64);
2463 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2464 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2465 SDMMC_IDMAC_INT_RI);
2466 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
3fc7eaef 2467 host->dma_ops->complete((void *)host);
69d99fdc
PT		 2468 }
2469 } else {
2470 pending = mci_readl(host, IDSTS);
2471 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2472 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2473 SDMMC_IDMAC_INT_RI);
2474 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3fc7eaef 2475 host->dma_ops->complete((void *)host);
69d99fdc 2476 }
f95f3850 2477 }
f95f3850
WN		 2478
2479 return IRQ_HANDLED;
2480}
2481
c91eab4b 2482#ifdef CONFIG_OF
eff8f2f5
LPC		 2483/* given a slot, find out the device node representing that slot */
2484static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
c91eab4b 2485{
eff8f2f5 2486 struct device *dev = slot->mmc->parent;
c91eab4b
TA		 2487 struct device_node *np;
2488 const __be32 *addr;
2489 int len;
2490
2491 if (!dev || !dev->of_node)
2492 return NULL;
2493
2494 for_each_child_of_node(dev->of_node, np) {
2495 addr = of_get_property(np, "reg", &len);
2496 if (!addr || (len < sizeof(int)))
2497 continue;
eff8f2f5 2498 if (be32_to_cpup(addr) == slot->id)
c91eab4b
TA		 2499 return np;
2500 }
2501 return NULL;
2502}
2503
eff8f2f5 2504static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
a70aaa64 2505{
eff8f2f5 2506 struct device_node *np = dw_mci_of_find_slot_node(slot);
a70aaa64 2507
eff8f2f5
LPC		 2508 if (!np)
2509 return;
a70aaa64 2510
eff8f2f5
LPC		 2511 if (of_property_read_bool(np, "disable-wp")) {
2512 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2513 dev_warn(slot->mmc->parent,
2514 "Slot quirk 'disable-wp' is deprecated\n");
2515 }
a70aaa64 2516}
c91eab4b 2517#else /* CONFIG_OF */
eff8f2f5 2518static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
a70aaa64 2519{
a70aaa64 2520}
c91eab4b
TA		 2521#endif /* CONFIG_OF */
2522
36c179a9 2523static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 2524{
2525 struct mmc_host *mmc;
2526 struct dw_mci_slot *slot;
e95baf13 2527 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2528 int ctrl_id, ret;
1f44a2a5 2529 u32 freq[2];
f95f3850 2530
4a90920c 2531 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 2532 if (!mmc)
2533 return -ENOMEM;
2534
2535 slot = mmc_priv(mmc);
2536 slot->id = id;
76756234 2537 slot->sdio_id = host->sdio_id0 + id;
f95f3850
WN		 2538 slot->mmc = mmc;
2539 slot->host = host;
c91eab4b 2540 host->slot[id] = slot;
f95f3850
WN		 2541
2542 mmc->ops = &dw_mci_ops;
1f44a2a5
SJ		 2543 if (of_property_read_u32_array(host->dev->of_node,
2544 "clock-freq-min-max", freq, 2)) {
2545 mmc->f_min = DW_MCI_FREQ_MIN;
2546 mmc->f_max = DW_MCI_FREQ_MAX;
2547 } else {
2548 mmc->f_min = freq[0];
2549 mmc->f_max = freq[1];
2550 }
f95f3850 2551
51da2240
YC		 2552 /*if there are external regulators, get them*/
2553 ret = mmc_regulator_get_supply(mmc);
2554 if (ret == -EPROBE_DEFER)
3cf890fc 2555 goto err_host_allocated;
51da2240
YC		 2556
2557 if (!mmc->ocr_avail)
2558 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
f95f3850 2559
fc3d7720
JC		 2560 if (host->pdata->caps)
2561 mmc->caps = host->pdata->caps;
fc3d7720 2562
ab269128
AK		 2563 if (host->pdata->pm_caps)
2564 mmc->pm_caps = host->pdata->pm_caps;
2565
800d78bf
TA		 2566 if (host->dev->of_node) {
2567 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2568 if (ctrl_id < 0)
2569 ctrl_id = 0;
2570 } else {
2571 ctrl_id = to_platform_device(host->dev)->id;
2572 }
cb27a843
JH		 2573 if (drv_data && drv_data->caps)
2574 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 2575
4f408cc6
SJ		 2576 if (host->pdata->caps2)
2577 mmc->caps2 = host->pdata->caps2;
4f408cc6 2578
eff8f2f5
LPC		 2579 dw_mci_slot_of_parse(slot);
2580
3cf890fc
DA		 2581 ret = mmc_of_parse(mmc);
2582 if (ret)
2583 goto err_host_allocated;
f95f3850 2584
2b708df2 2585 /* Useful defaults if platform data is unset. */
3fc7eaef 2586 if (host->use_dma == TRANS_MODE_IDMAC) {
2b708df2
JC		 2587 mmc->max_segs = host->ring_size;
2588 mmc->max_blk_size = 65536;
2589 mmc->max_seg_size = 0x1000;
2590 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2591 mmc->max_blk_count = mmc->max_req_size / 512;
3fc7eaef
SL		 2592 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2593 mmc->max_segs = 64;
2594 mmc->max_blk_size = 65536;
2595 mmc->max_blk_count = 65535;
2596 mmc->max_req_size =
2597 mmc->max_blk_size * mmc->max_blk_count;
2598 mmc->max_seg_size = mmc->max_req_size;
f95f3850 2599 } else {
3fc7eaef 2600 /* TRANS_MODE_PIO */
2b708df2
JC		 2601 mmc->max_segs = 64;
2602 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2603 mmc->max_blk_count = 512;
2604 mmc->max_req_size = mmc->max_blk_size *
2605 mmc->max_blk_count;
2606 mmc->max_seg_size = mmc->max_req_size;
a39e5746 2607 }
f95f3850 2608
ae0eb348
JC		 2609 if (dw_mci_get_cd(mmc))
2610 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2611 else
2612 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2613
0cea529d
JC		 2614 ret = mmc_add_host(mmc);
2615 if (ret)
3cf890fc 2616 goto err_host_allocated;
f95f3850
WN		 2617
2618#if defined(CONFIG_DEBUG_FS)
2619 dw_mci_init_debugfs(slot);
2620#endif
2621
f95f3850 2622 return 0;
800d78bf 2623
3cf890fc 2624err_host_allocated:
800d78bf 2625 mmc_free_host(mmc);
51da2240 2626 return ret;
f95f3850
WN		 2627}
2628
2629static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2630{
f95f3850
WN		 2631 /* Debugfs stuff is cleaned up by mmc core */
2632 mmc_remove_host(slot->mmc);
2633 slot->host->slot[id] = NULL;
2634 mmc_free_host(slot->mmc);
2635}
2636
2637static void dw_mci_init_dma(struct dw_mci *host)
2638{
69d99fdc 2639 int addr_config;
3fc7eaef
SL		 2640 struct device *dev = host->dev;
2641 struct device_node *np = dev->of_node;
69d99fdc 2642
3fc7eaef
SL		 2643 /*
2644 * Check tansfer mode from HCON[17:16]
2645 * Clear the ambiguous description of dw_mmc databook:
2646 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2647 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2648 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2649 * 2b'11: Non DW DMA Interface -> pio only
2650 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2651 * simpler request/acknowledge handshake mechanism and both of them
2652 * are regarded as external dma master for dw_mmc.
2653 */
2654 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2655 if (host->use_dma == DMA_INTERFACE_IDMA) {
2656 host->use_dma = TRANS_MODE_IDMAC;
2657 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2658 host->use_dma == DMA_INTERFACE_GDMA) {
2659 host->use_dma = TRANS_MODE_EDMAC;
2660 } else {
f95f3850
WN		 2661 goto no_dma;
2662 }
2663
2664 /* Determine which DMA interface to use */
3fc7eaef
SL		 2665 if (host->use_dma == TRANS_MODE_IDMAC) {
2666 /*
2667 * Check ADDR_CONFIG bit in HCON to find
2668 * IDMAC address bus width
2669 */
70692752 2670 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
3fc7eaef
SL		 2671
2672 if (addr_config == 1) {
2673 /* host supports IDMAC in 64-bit address mode */
2674 host->dma_64bit_address = 1;
2675 dev_info(host->dev,
2676 "IDMAC supports 64-bit address mode.\n");
2677 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2678 dma_set_coherent_mask(host->dev,
2679 DMA_BIT_MASK(64));
2680 } else {
2681 /* host supports IDMAC in 32-bit address mode */
2682 host->dma_64bit_address = 0;
2683 dev_info(host->dev,
2684 "IDMAC supports 32-bit address mode.\n");
2685 }
f95f3850 2686
3fc7eaef
SL		 2687 /* Alloc memory for sg translation */
2688 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2689 &host->sg_dma, GFP_KERNEL);
2690 if (!host->sg_cpu) {
2691 dev_err(host->dev,
2692 "%s: could not alloc DMA memory\n",
2693 __func__);
2694 goto no_dma;
2695 }
2696
2697 host->dma_ops = &dw_mci_idmac_ops;
2698 dev_info(host->dev, "Using internal DMA controller.\n");
2699 } else {
2700 /* TRANS_MODE_EDMAC: check dma bindings again */
2701 if ((of_property_count_strings(np, "dma-names") < 0) ||
2702 (!of_find_property(np, "dmas", NULL))) {
2703 goto no_dma;
2704 }
2705 host->dma_ops = &dw_mci_edmac_ops;
2706 dev_info(host->dev, "Using external DMA controller.\n");
2707 }
f95f3850 2708
e1631f98
JC		 2709 if (host->dma_ops->init && host->dma_ops->start &&
2710 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 2711 if (host->dma_ops->init(host)) {
0e3a22c0
SL		 2712 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2713 __func__);
f95f3850
WN		 2714 goto no_dma;
2715 }
2716 } else {
4a90920c 2717 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 2718 goto no_dma;
2719 }
2720
f95f3850
WN		 2721 return;
2722
2723no_dma:
4a90920c 2724 dev_info(host->dev, "Using PIO mode.\n");
3fc7eaef 2725 host->use_dma = TRANS_MODE_PIO;
f95f3850
WN		 2726}
2727
31bff450 2728static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
f95f3850
WN		 2729{
2730 unsigned long timeout = jiffies + msecs_to_jiffies(500);
31bff450 2731 u32 ctrl;
f95f3850 2732
31bff450
SJ		 2733 ctrl = mci_readl(host, CTRL);
2734 ctrl |= reset;
2735 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 2736
2737 /* wait till resets clear */
2738 do {
2739 ctrl = mci_readl(host, CTRL);
31bff450 2740 if (!(ctrl & reset))
f95f3850
WN		 2741 return true;
2742 } while (time_before(jiffies, timeout));
2743
31bff450
SJ		 2744 dev_err(host->dev,
2745 "Timeout resetting block (ctrl reset %#x)\n",
2746 ctrl & reset);
f95f3850
WN		 2747
2748 return false;
2749}
2750
3a33a94c 2751static bool dw_mci_reset(struct dw_mci *host)
31bff450 2752{
3a33a94c
SR		 2753 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2754 bool ret = false;
2755
31bff450
SJ		 2756 /*
2757 * Reseting generates a block interrupt, hence setting
2758 * the scatter-gather pointer to NULL.
2759 */
2760 if (host->sg) {
2761 sg_miter_stop(&host->sg_miter);
2762 host->sg = NULL;
2763 }
2764
3a33a94c
SR		 2765 if (host->use_dma)
2766 flags |= SDMMC_CTRL_DMA_RESET;
31bff450 2767
3a33a94c
SR		 2768 if (dw_mci_ctrl_reset(host, flags)) {
2769 /*
2770 * In all cases we clear the RAWINTS register to clear any
2771 * interrupts.
2772 */
2773 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2774
2775 /* if using dma we wait for dma_req to clear */
2776 if (host->use_dma) {
2777 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2778 u32 status;
0e3a22c0 2779
3a33a94c
SR		 2780 do {
2781 status = mci_readl(host, STATUS);
2782 if (!(status & SDMMC_STATUS_DMA_REQ))
2783 break;
2784 cpu_relax();
2785 } while (time_before(jiffies, timeout));
2786
2787 if (status & SDMMC_STATUS_DMA_REQ) {
2788 dev_err(host->dev,
0e3a22c0
SL		 2789 "%s: Timeout waiting for dma_req to clear during reset\n",
2790 __func__);
3a33a94c
SR		 2791 goto ciu_out;
2792 }
2793
2794 /* when using DMA next we reset the fifo again */
2795 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2796 goto ciu_out;
2797 }
2798 } else {
2799 /* if the controller reset bit did clear, then set clock regs */
2800 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
0e3a22c0
SL		 2801 dev_err(host->dev,
2802 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
3a33a94c
SR		 2803 __func__);
2804 goto ciu_out;
2805 }
2806 }
2807
3fc7eaef
SL		 2808 if (host->use_dma == TRANS_MODE_IDMAC)
2809 /* It is also recommended that we reset and reprogram idmac */
2810 dw_mci_idmac_reset(host);
3a33a94c
SR		 2811
2812 ret = true;
2813
2814ciu_out:
2815 /* After a CTRL reset we need to have CIU set clock registers */
2816 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2817
2818 return ret;
31bff450
SJ		 2819}
2820
5c935165
DA		 2821static void dw_mci_cmd11_timer(unsigned long arg)
2822{
2823 struct dw_mci *host = (struct dw_mci *)arg;
2824
fd674198
DA		 2825 if (host->state != STATE_SENDING_CMD11) {
2826 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2827 return;
2828 }
5c935165
DA		 2829
2830 host->cmd_status = SDMMC_INT_RTO;
2831 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2832 tasklet_schedule(&host->tasklet);
2833}
2834
57e10486
AK		 2835static void dw_mci_dto_timer(unsigned long arg)
2836{
2837 struct dw_mci *host = (struct dw_mci *)arg;
2838
2839 switch (host->state) {
2840 case STATE_SENDING_DATA:
2841 case STATE_DATA_BUSY:
2842 /*
2843 * If DTO interrupt does NOT come in sending data state,
2844 * we should notify the driver to terminate current transfer
2845 * and report a data timeout to the core.
2846 */
2847 host->data_status = SDMMC_INT_DRTO;
2848 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2849 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2850 tasklet_schedule(&host->tasklet);
2851 break;
2852 default:
2853 break;
2854 }
2855}
2856
c91eab4b
TA		 2857#ifdef CONFIG_OF
2858static struct dw_mci_of_quirks {
2859 char *quirk;
2860 int id;
2861} of_quirks[] = {
2862 {
c91eab4b
TA		 2863 .quirk = "broken-cd",
2864 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2865 },
2866};
2867
2868static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2869{
2870 struct dw_mci_board *pdata;
2871 struct device *dev = host->dev;
2872 struct device_node *np = dev->of_node;
e95baf13 2873 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2874 int idx, ret;
3c6d89ea 2875 u32 clock_frequency;
c91eab4b
TA		 2876
2877 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
bf3707ea 2878 if (!pdata)
c91eab4b 2879 return ERR_PTR(-ENOMEM);
c91eab4b
TA		 2880
2881 /* find out number of slots supported */
2882 if (of_property_read_u32(dev->of_node, "num-slots",
2883 &pdata->num_slots)) {
0e3a22c0
SL		 2884 dev_info(dev,
2885 "num-slots property not found, assuming 1 slot is available\n");
c91eab4b
TA		 2886 pdata->num_slots = 1;
2887 }
2888
2889 /* get quirks */
2890 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2891 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2892 pdata->quirks |= of_quirks[idx].id;
2893
2894 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
0e3a22c0
SL		 2895 dev_info(dev,
2896 "fifo-depth property not found, using value of FIFOTH register as default\n");
c91eab4b
TA		 2897
2898 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2899
3c6d89ea
DA		 2900 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2901 pdata->bus_hz = clock_frequency;
2902
cb27a843
JH		 2903 if (drv_data && drv_data->parse_dt) {
2904 ret = drv_data->parse_dt(host);
800d78bf
TA		 2905 if (ret)
2906 return ERR_PTR(ret);
2907 }
2908
40a7a463
JC		 2909 if (of_find_property(np, "supports-highspeed", NULL)) {
2910 dev_info(dev, "supports-highspeed property is deprecated.\n");
10b49841 2911 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
40a7a463 2912 }
10b49841 2913
c91eab4b
TA		 2914 return pdata;
2915}
2916
2917#else /* CONFIG_OF */
2918static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2919{
2920 return ERR_PTR(-EINVAL);
2921}
2922#endif /* CONFIG_OF */
2923
fa0c3283
DA		 2924static void dw_mci_enable_cd(struct dw_mci *host)
2925{
2926 struct dw_mci_board *brd = host->pdata;
2927 unsigned long irqflags;
2928 u32 temp;
2929 int i;
2930
2931 /* No need for CD if broken card detection */
2932 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2933 return;
2934
2935 /* No need for CD if all slots have a non-error GPIO */
2936 for (i = 0; i < host->num_slots; i++) {
2937 struct dw_mci_slot *slot = host->slot[i];
2938
2939 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2940 break;
2941 }
2942 if (i == host->num_slots)
2943 return;
2944
2945 spin_lock_irqsave(&host->irq_lock, irqflags);
2946 temp = mci_readl(host, INTMASK);
2947 temp |= SDMMC_INT_CD;
2948 mci_writel(host, INTMASK, temp);
2949 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2950}
2951
62ca8034 2952int dw_mci_probe(struct dw_mci *host)
f95f3850 2953{
e95baf13 2954 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 2955 int width, i, ret = 0;
f95f3850 2956 u32 fifo_size;
1c2215b7 2957 int init_slots = 0;
f95f3850 2958
c91eab4b
TA		 2959 if (!host->pdata) {
2960 host->pdata = dw_mci_parse_dt(host);
2961 if (IS_ERR(host->pdata)) {
2962 dev_err(host->dev, "platform data not available\n");
2963 return -EINVAL;
2964 }
f95f3850
WN		 2965 }
2966
9e747b7e 2967 if (host->pdata->num_slots < 1) {
4a90920c 2968 dev_err(host->dev,
907abd51 2969 "Platform data must supply num_slots.\n");
62ca8034 2970 return -ENODEV;
f95f3850
WN		 2971 }
2972
780f22af 2973 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 2974 if (IS_ERR(host->biu_clk)) {
2975 dev_dbg(host->dev, "biu clock not available\n");
2976 } else {
2977 ret = clk_prepare_enable(host->biu_clk);
2978 if (ret) {
2979 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 2980 return ret;
2981 }
2982 }
2983
780f22af 2984 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 2985 if (IS_ERR(host->ciu_clk)) {
2986 dev_dbg(host->dev, "ciu clock not available\n");
3c6d89ea 2987 host->bus_hz = host->pdata->bus_hz;
f90a0612
TA		 2988 } else {
2989 ret = clk_prepare_enable(host->ciu_clk);
2990 if (ret) {
2991 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 2992 goto err_clk_biu;
2993 }
f90a0612 2994
3c6d89ea
DA		 2995 if (host->pdata->bus_hz) {
2996 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2997 if (ret)
2998 dev_warn(host->dev,
612de4c1 2999 "Unable to set bus rate to %uHz\n",
3c6d89ea
DA		 3000 host->pdata->bus_hz);
3001 }
f90a0612 3002 host->bus_hz = clk_get_rate(host->ciu_clk);
3c6d89ea 3003 }
f90a0612 3004
612de4c1
JC		 3005 if (!host->bus_hz) {
3006 dev_err(host->dev,
3007 "Platform data must supply bus speed\n");
3008 ret = -ENODEV;
3009 goto err_clk_ciu;
3010 }
3011
002f0d5c
YK		 3012 if (drv_data && drv_data->init) {
3013 ret = drv_data->init(host);
3014 if (ret) {
3015 dev_err(host->dev,
3016 "implementation specific init failed\n");
3017 goto err_clk_ciu;
3018 }
3019 }
3020
cb27a843
JH		 3021 if (drv_data && drv_data->setup_clock) {
3022 ret = drv_data->setup_clock(host);
800d78bf
TA		 3023 if (ret) {
3024 dev_err(host->dev,
3025 "implementation specific clock setup failed\n");
3026 goto err_clk_ciu;
3027 }
3028 }
3029
5c935165
DA		 3030 setup_timer(&host->cmd11_timer,
3031 dw_mci_cmd11_timer, (unsigned long)host);
3032
62ca8034 3033 host->quirks = host->pdata->quirks;
f95f3850 3034
57e10486
AK		 3035 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3036 setup_timer(&host->dto_timer,
3037 dw_mci_dto_timer, (unsigned long)host);
3038
f95f3850 3039 spin_lock_init(&host->lock);
f8c58c11 3040 spin_lock_init(&host->irq_lock);
f95f3850
WN		 3041 INIT_LIST_HEAD(&host->queue);
3042
f95f3850
WN		 3043 /*
3044 * Get the host data width - this assumes that HCON has been set with
3045 * the correct values.
3046 */
70692752 3047 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
f95f3850
WN		 3048 if (!i) {
3049 host->push_data = dw_mci_push_data16;
3050 host->pull_data = dw_mci_pull_data16;
3051 width = 16;
3052 host->data_shift = 1;
3053 } else if (i == 2) {
3054 host->push_data = dw_mci_push_data64;
3055 host->pull_data = dw_mci_pull_data64;
3056 width = 64;
3057 host->data_shift = 3;
3058 } else {
3059 /* Check for a reserved value, and warn if it is */
3060 WARN((i != 1),
3061 "HCON reports a reserved host data width!\n"
3062 "Defaulting to 32-bit access.\n");
3063 host->push_data = dw_mci_push_data32;
3064 host->pull_data = dw_mci_pull_data32;
3065 width = 32;
3066 host->data_shift = 2;
3067 }
3068
3069 /* Reset all blocks */
3a33a94c 3070 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
141a712a
SJ		 3071 return -ENODEV;
3072
3073 host->dma_ops = host->pdata->dma_ops;
3074 dw_mci_init_dma(host);
f95f3850
WN		 3075
3076 /* Clear the interrupts for the host controller */
3077 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3078 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3079
3080 /* Put in max timeout */
3081 mci_writel(host, TMOUT, 0xFFFFFFFF);
3082
3083 /*
3084 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3085 * Tx Mark = fifo_size / 2 DMA Size = 8
3086 */
b86d8253
JH		 3087 if (!host->pdata->fifo_depth) {
3088 /*
3089 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3090 * have been overwritten by the bootloader, just like we're
3091 * about to do, so if you know the value for your hardware, you
3092 * should put it in the platform data.
3093 */
3094 fifo_size = mci_readl(host, FIFOTH);
8234e869 3095 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 3096 } else {
3097 fifo_size = host->pdata->fifo_depth;
3098 }
3099 host->fifo_depth = fifo_size;
52426899
SJ		 3100 host->fifoth_val =
3101 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
e61cf118 3102 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 3103
3104 /* disable clock to CIU */
3105 mci_writel(host, CLKENA, 0);
3106 mci_writel(host, CLKSRC, 0);
3107
63008768
JH		 3108 /*
3109 * In 2.40a spec, Data offset is changed.
3110 * Need to check the version-id and set data-offset for DATA register.
3111 */
3112 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3113 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3114
3115 if (host->verid < DW_MMC_240A)
76184ac1 3116 host->fifo_reg = host->regs + DATA_OFFSET;
63008768 3117 else
76184ac1 3118 host->fifo_reg = host->regs + DATA_240A_OFFSET;
63008768 3119
f95f3850 3120 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
780f22af
SJ		 3121 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3122 host->irq_flags, "dw-mci", host);
f95f3850 3123 if (ret)
6130e7a9 3124 goto err_dmaunmap;
f95f3850 3125
f95f3850
WN		 3126 if (host->pdata->num_slots)
3127 host->num_slots = host->pdata->num_slots;
3128 else
70692752 3129 host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
f95f3850 3130
2da1d7f2 3131 /*
fa0c3283 3132 * Enable interrupts for command done, data over, data empty,
2da1d7f2
YC		 3133 * receive ready and error such as transmit, receive timeout, crc error
3134 */
3135 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3136 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3137 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3138 DW_MCI_ERROR_FLAGS);
0e3a22c0
SL		 3139 /* Enable mci interrupt */
3140 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2da1d7f2 3141
0e3a22c0
SL		 3142 dev_info(host->dev,
3143 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
2da1d7f2
YC		 3144 host->irq, width, fifo_size);
3145
f95f3850
WN		 3146 /* We need at least one slot to succeed */
3147 for (i = 0; i < host->num_slots; i++) {
3148 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 3149 if (ret)
3150 dev_dbg(host->dev, "slot %d init failed\n", i);
3151 else
3152 init_slots++;
3153 }
3154
3155 if (init_slots) {
3156 dev_info(host->dev, "%d slots initialized\n", init_slots);
3157 } else {
0e3a22c0
SL		 3158 dev_dbg(host->dev,
3159 "attempted to initialize %d slots, but failed on all\n",
3160 host->num_slots);
6130e7a9 3161 goto err_dmaunmap;
f95f3850
WN		 3162 }
3163
b793f658
DA		 3164 /* Now that slots are all setup, we can enable card detect */
3165 dw_mci_enable_cd(host);
3166
f95f3850 3167 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4a90920c 3168 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
f95f3850
WN		 3169
3170 return 0;
3171
f95f3850
WN		 3172err_dmaunmap:
3173 if (host->use_dma && host->dma_ops->exit)
3174 host->dma_ops->exit(host);
f90a0612
TA		 3175
3176err_clk_ciu:
780f22af 3177 if (!IS_ERR(host->ciu_clk))
f90a0612 3178 clk_disable_unprepare(host->ciu_clk);
780f22af 3179
f90a0612 3180err_clk_biu:
780f22af 3181 if (!IS_ERR(host->biu_clk))
f90a0612 3182 clk_disable_unprepare(host->biu_clk);
780f22af 3183
f95f3850
WN		 3184 return ret;
3185}
62ca8034 3186EXPORT_SYMBOL(dw_mci_probe);
f95f3850 3187
62ca8034 3188void dw_mci_remove(struct dw_mci *host)
f95f3850 3189{
f95f3850
WN		 3190 int i;
3191
f95f3850 3192 for (i = 0; i < host->num_slots; i++) {
4a90920c 3193 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 3194 if (host->slot[i])
3195 dw_mci_cleanup_slot(host->slot[i], i);
3196 }
3197
048fd7e6
PT		 3198 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3199 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3200
f95f3850
WN		 3201 /* disable clock to CIU */
3202 mci_writel(host, CLKENA, 0);
3203 mci_writel(host, CLKSRC, 0);
3204
f95f3850
WN		 3205 if (host->use_dma && host->dma_ops->exit)
3206 host->dma_ops->exit(host);
3207
f90a0612
TA		 3208 if (!IS_ERR(host->ciu_clk))
3209 clk_disable_unprepare(host->ciu_clk);
780f22af 3210
f90a0612
TA		 3211 if (!IS_ERR(host->biu_clk))
3212 clk_disable_unprepare(host->biu_clk);
f95f3850 3213}
62ca8034
SH		 3214EXPORT_SYMBOL(dw_mci_remove);
3215
3216
f95f3850 3217
6fe8890d 3218#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 3219/*
3220 * TODO: we should probably disable the clock to the card in the suspend path.
3221 */
62ca8034 3222int dw_mci_suspend(struct dw_mci *host)
f95f3850 3223{
3fc7eaef
SL		 3224 if (host->use_dma && host->dma_ops->exit)
3225 host->dma_ops->exit(host);
3226
f95f3850
WN		 3227 return 0;
3228}
62ca8034 3229EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 3230
62ca8034 3231int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 3232{
3233 int i, ret;
f95f3850 3234
3a33a94c 3235 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
e61cf118
JC		 3236 ret = -ENODEV;
3237 return ret;
3238 }
3239
3bfe619d 3240 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 3241 host->dma_ops->init(host);
3242
52426899
SJ		 3243 /*
3244 * Restore the initial value at FIFOTH register
3245 * And Invalidate the prev_blksz with zero
3246 */
e61cf118 3247 mci_writel(host, FIFOTH, host->fifoth_val);
52426899 3248 host->prev_blksz = 0;
e61cf118 3249
2eb2944f
DA		 3250 /* Put in max timeout */
3251 mci_writel(host, TMOUT, 0xFFFFFFFF);
3252
e61cf118
JC		 3253 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3254 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3255 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3256 DW_MCI_ERROR_FLAGS);
e61cf118
JC		 3257 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3258
f95f3850
WN		 3259 for (i = 0; i < host->num_slots; i++) {
3260 struct dw_mci_slot *slot = host->slot[i];
0e3a22c0 3261
f95f3850
WN		 3262 if (!slot)
3263 continue;
ab269128
AK		 3264 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3265 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3266 dw_mci_setup_bus(slot, true);
3267 }
f95f3850 3268 }
fa0c3283
DA		 3269
3270 /* Now that slots are all setup, we can enable card detect */
3271 dw_mci_enable_cd(host);
3272
f95f3850
WN		 3273 return 0;
3274}
62ca8034 3275EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 3276#endif /* CONFIG_PM_SLEEP */
3277
f95f3850
WN		 3278static int __init dw_mci_init(void)
3279{
8e1c4e4d 3280 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
62ca8034 3281 return 0;
f95f3850
WN		 3282}
3283
3284static void __exit dw_mci_exit(void)
3285{
f95f3850
WN		 3286}
3287
3288module_init(dw_mci_init);
3289module_exit(dw_mci_exit);
3290
3291MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3292MODULE_AUTHOR("NXP Semiconductor VietNam");
3293MODULE_AUTHOR("Imagination Technologies Ltd");
3294MODULE_LICENSE("GPL v2");
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