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Commit | Line | Data |
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f95f3850 WN |
1 | /* |
2 | * Synopsys DesignWare Multimedia Card Interface driver | |
3 | * (Based on NXP driver for lpc 31xx) | |
4 | * | |
5 | * Copyright (C) 2009 NXP Semiconductors | |
6 | * Copyright (C) 2009, 2010 Imagination Technologies Ltd. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/blkdev.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/debugfs.h> | |
17 | #include <linux/device.h> | |
18 | #include <linux/dma-mapping.h> | |
19 | #include <linux/err.h> | |
20 | #include <linux/init.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/platform_device.h> | |
25 | #include <linux/scatterlist.h> | |
26 | #include <linux/seq_file.h> | |
27 | #include <linux/slab.h> | |
28 | #include <linux/stat.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/irq.h> | |
31 | #include <linux/mmc/host.h> | |
32 | #include <linux/mmc/mmc.h> | |
33 | #include <linux/mmc/dw_mmc.h> | |
34 | #include <linux/bitops.h> | |
c07946a3 | 35 | #include <linux/regulator/consumer.h> |
1791b13e | 36 | #include <linux/workqueue.h> |
f95f3850 WN |
37 | |
38 | #include "dw_mmc.h" | |
39 | ||
40 | /* Common flag combinations */ | |
41 | #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \ | |
42 | SDMMC_INT_HTO | SDMMC_INT_SBE | \ | |
43 | SDMMC_INT_EBE) | |
44 | #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \ | |
45 | SDMMC_INT_RESP_ERR) | |
46 | #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \ | |
47 | DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE) | |
48 | #define DW_MCI_SEND_STATUS 1 | |
49 | #define DW_MCI_RECV_STATUS 2 | |
50 | #define DW_MCI_DMA_THRESHOLD 16 | |
51 | ||
52 | #ifdef CONFIG_MMC_DW_IDMAC | |
53 | struct idmac_desc { | |
54 | u32 des0; /* Control Descriptor */ | |
55 | #define IDMAC_DES0_DIC BIT(1) | |
56 | #define IDMAC_DES0_LD BIT(2) | |
57 | #define IDMAC_DES0_FD BIT(3) | |
58 | #define IDMAC_DES0_CH BIT(4) | |
59 | #define IDMAC_DES0_ER BIT(5) | |
60 | #define IDMAC_DES0_CES BIT(30) | |
61 | #define IDMAC_DES0_OWN BIT(31) | |
62 | ||
63 | u32 des1; /* Buffer sizes */ | |
64 | #define IDMAC_SET_BUFFER1_SIZE(d, s) \ | |
9b7bbe10 | 65 | ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff)) |
f95f3850 WN |
66 | |
67 | u32 des2; /* buffer 1 physical address */ | |
68 | ||
69 | u32 des3; /* buffer 2 physical address */ | |
70 | }; | |
71 | #endif /* CONFIG_MMC_DW_IDMAC */ | |
72 | ||
73 | /** | |
74 | * struct dw_mci_slot - MMC slot state | |
75 | * @mmc: The mmc_host representing this slot. | |
76 | * @host: The MMC controller this slot is using. | |
77 | * @ctype: Card type for this slot. | |
78 | * @mrq: mmc_request currently being processed or waiting to be | |
79 | * processed, or NULL when the slot is idle. | |
80 | * @queue_node: List node for placing this node in the @queue list of | |
81 | * &struct dw_mci. | |
82 | * @clock: Clock rate configured by set_ios(). Protected by host->lock. | |
83 | * @flags: Random state bits associated with the slot. | |
84 | * @id: Number of this slot. | |
85 | * @last_detect_state: Most recently observed card detect state. | |
86 | */ | |
87 | struct dw_mci_slot { | |
88 | struct mmc_host *mmc; | |
89 | struct dw_mci *host; | |
90 | ||
91 | u32 ctype; | |
92 | ||
93 | struct mmc_request *mrq; | |
94 | struct list_head queue_node; | |
95 | ||
96 | unsigned int clock; | |
97 | unsigned long flags; | |
98 | #define DW_MMC_CARD_PRESENT 0 | |
99 | #define DW_MMC_CARD_NEED_INIT 1 | |
100 | int id; | |
101 | int last_detect_state; | |
102 | }; | |
103 | ||
1791b13e JH |
104 | static struct workqueue_struct *dw_mci_card_workqueue; |
105 | ||
f95f3850 WN |
106 | #if defined(CONFIG_DEBUG_FS) |
107 | static int dw_mci_req_show(struct seq_file *s, void *v) | |
108 | { | |
109 | struct dw_mci_slot *slot = s->private; | |
110 | struct mmc_request *mrq; | |
111 | struct mmc_command *cmd; | |
112 | struct mmc_command *stop; | |
113 | struct mmc_data *data; | |
114 | ||
115 | /* Make sure we get a consistent snapshot */ | |
116 | spin_lock_bh(&slot->host->lock); | |
117 | mrq = slot->mrq; | |
118 | ||
119 | if (mrq) { | |
120 | cmd = mrq->cmd; | |
121 | data = mrq->data; | |
122 | stop = mrq->stop; | |
123 | ||
124 | if (cmd) | |
125 | seq_printf(s, | |
126 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
127 | cmd->opcode, cmd->arg, cmd->flags, | |
128 | cmd->resp[0], cmd->resp[1], cmd->resp[2], | |
129 | cmd->resp[2], cmd->error); | |
130 | if (data) | |
131 | seq_printf(s, "DATA %u / %u * %u flg %x err %d\n", | |
132 | data->bytes_xfered, data->blocks, | |
133 | data->blksz, data->flags, data->error); | |
134 | if (stop) | |
135 | seq_printf(s, | |
136 | "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n", | |
137 | stop->opcode, stop->arg, stop->flags, | |
138 | stop->resp[0], stop->resp[1], stop->resp[2], | |
139 | stop->resp[2], stop->error); | |
140 | } | |
141 | ||
142 | spin_unlock_bh(&slot->host->lock); | |
143 | ||
144 | return 0; | |
145 | } | |
146 | ||
147 | static int dw_mci_req_open(struct inode *inode, struct file *file) | |
148 | { | |
149 | return single_open(file, dw_mci_req_show, inode->i_private); | |
150 | } | |
151 | ||
152 | static const struct file_operations dw_mci_req_fops = { | |
153 | .owner = THIS_MODULE, | |
154 | .open = dw_mci_req_open, | |
155 | .read = seq_read, | |
156 | .llseek = seq_lseek, | |
157 | .release = single_release, | |
158 | }; | |
159 | ||
160 | static int dw_mci_regs_show(struct seq_file *s, void *v) | |
161 | { | |
162 | seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS); | |
163 | seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS); | |
164 | seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD); | |
165 | seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL); | |
166 | seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK); | |
167 | seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA); | |
168 | ||
169 | return 0; | |
170 | } | |
171 | ||
172 | static int dw_mci_regs_open(struct inode *inode, struct file *file) | |
173 | { | |
174 | return single_open(file, dw_mci_regs_show, inode->i_private); | |
175 | } | |
176 | ||
177 | static const struct file_operations dw_mci_regs_fops = { | |
178 | .owner = THIS_MODULE, | |
179 | .open = dw_mci_regs_open, | |
180 | .read = seq_read, | |
181 | .llseek = seq_lseek, | |
182 | .release = single_release, | |
183 | }; | |
184 | ||
185 | static void dw_mci_init_debugfs(struct dw_mci_slot *slot) | |
186 | { | |
187 | struct mmc_host *mmc = slot->mmc; | |
188 | struct dw_mci *host = slot->host; | |
189 | struct dentry *root; | |
190 | struct dentry *node; | |
191 | ||
192 | root = mmc->debugfs_root; | |
193 | if (!root) | |
194 | return; | |
195 | ||
196 | node = debugfs_create_file("regs", S_IRUSR, root, host, | |
197 | &dw_mci_regs_fops); | |
198 | if (!node) | |
199 | goto err; | |
200 | ||
201 | node = debugfs_create_file("req", S_IRUSR, root, slot, | |
202 | &dw_mci_req_fops); | |
203 | if (!node) | |
204 | goto err; | |
205 | ||
206 | node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state); | |
207 | if (!node) | |
208 | goto err; | |
209 | ||
210 | node = debugfs_create_x32("pending_events", S_IRUSR, root, | |
211 | (u32 *)&host->pending_events); | |
212 | if (!node) | |
213 | goto err; | |
214 | ||
215 | node = debugfs_create_x32("completed_events", S_IRUSR, root, | |
216 | (u32 *)&host->completed_events); | |
217 | if (!node) | |
218 | goto err; | |
219 | ||
220 | return; | |
221 | ||
222 | err: | |
223 | dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); | |
224 | } | |
225 | #endif /* defined(CONFIG_DEBUG_FS) */ | |
226 | ||
227 | static void dw_mci_set_timeout(struct dw_mci *host) | |
228 | { | |
229 | /* timeout (maximum) */ | |
230 | mci_writel(host, TMOUT, 0xffffffff); | |
231 | } | |
232 | ||
233 | static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd) | |
234 | { | |
235 | struct mmc_data *data; | |
236 | u32 cmdr; | |
237 | cmd->error = -EINPROGRESS; | |
238 | ||
239 | cmdr = cmd->opcode; | |
240 | ||
241 | if (cmdr == MMC_STOP_TRANSMISSION) | |
242 | cmdr |= SDMMC_CMD_STOP; | |
243 | else | |
244 | cmdr |= SDMMC_CMD_PRV_DAT_WAIT; | |
245 | ||
246 | if (cmd->flags & MMC_RSP_PRESENT) { | |
247 | /* We expect a response, so set this bit */ | |
248 | cmdr |= SDMMC_CMD_RESP_EXP; | |
249 | if (cmd->flags & MMC_RSP_136) | |
250 | cmdr |= SDMMC_CMD_RESP_LONG; | |
251 | } | |
252 | ||
253 | if (cmd->flags & MMC_RSP_CRC) | |
254 | cmdr |= SDMMC_CMD_RESP_CRC; | |
255 | ||
256 | data = cmd->data; | |
257 | if (data) { | |
258 | cmdr |= SDMMC_CMD_DAT_EXP; | |
259 | if (data->flags & MMC_DATA_STREAM) | |
260 | cmdr |= SDMMC_CMD_STRM_MODE; | |
261 | if (data->flags & MMC_DATA_WRITE) | |
262 | cmdr |= SDMMC_CMD_DAT_WR; | |
263 | } | |
264 | ||
265 | return cmdr; | |
266 | } | |
267 | ||
268 | static void dw_mci_start_command(struct dw_mci *host, | |
269 | struct mmc_command *cmd, u32 cmd_flags) | |
270 | { | |
271 | host->cmd = cmd; | |
272 | dev_vdbg(&host->pdev->dev, | |
273 | "start command: ARGR=0x%08x CMDR=0x%08x\n", | |
274 | cmd->arg, cmd_flags); | |
275 | ||
276 | mci_writel(host, CMDARG, cmd->arg); | |
277 | wmb(); | |
278 | ||
279 | mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START); | |
280 | } | |
281 | ||
282 | static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data) | |
283 | { | |
284 | dw_mci_start_command(host, data->stop, host->stop_cmdr); | |
285 | } | |
286 | ||
287 | /* DMA interface functions */ | |
288 | static void dw_mci_stop_dma(struct dw_mci *host) | |
289 | { | |
03e8cb53 | 290 | if (host->using_dma) { |
f95f3850 WN |
291 | host->dma_ops->stop(host); |
292 | host->dma_ops->cleanup(host); | |
293 | } else { | |
294 | /* Data transfer was stopped by the interrupt handler */ | |
295 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
296 | } | |
297 | } | |
298 | ||
299 | #ifdef CONFIG_MMC_DW_IDMAC | |
300 | static void dw_mci_dma_cleanup(struct dw_mci *host) | |
301 | { | |
302 | struct mmc_data *data = host->data; | |
303 | ||
304 | if (data) | |
305 | dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, | |
306 | ((data->flags & MMC_DATA_WRITE) | |
307 | ? DMA_TO_DEVICE : DMA_FROM_DEVICE)); | |
308 | } | |
309 | ||
310 | static void dw_mci_idmac_stop_dma(struct dw_mci *host) | |
311 | { | |
312 | u32 temp; | |
313 | ||
314 | /* Disable and reset the IDMAC interface */ | |
315 | temp = mci_readl(host, CTRL); | |
316 | temp &= ~SDMMC_CTRL_USE_IDMAC; | |
317 | temp |= SDMMC_CTRL_DMA_RESET; | |
318 | mci_writel(host, CTRL, temp); | |
319 | ||
320 | /* Stop the IDMAC running */ | |
321 | temp = mci_readl(host, BMOD); | |
a5289a43 | 322 | temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB); |
f95f3850 WN |
323 | mci_writel(host, BMOD, temp); |
324 | } | |
325 | ||
326 | static void dw_mci_idmac_complete_dma(struct dw_mci *host) | |
327 | { | |
328 | struct mmc_data *data = host->data; | |
329 | ||
330 | dev_vdbg(&host->pdev->dev, "DMA complete\n"); | |
331 | ||
332 | host->dma_ops->cleanup(host); | |
333 | ||
334 | /* | |
335 | * If the card was removed, data will be NULL. No point in trying to | |
336 | * send the stop command or waiting for NBUSY in this case. | |
337 | */ | |
338 | if (data) { | |
339 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
340 | tasklet_schedule(&host->tasklet); | |
341 | } | |
342 | } | |
343 | ||
344 | static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data, | |
345 | unsigned int sg_len) | |
346 | { | |
347 | int i; | |
348 | struct idmac_desc *desc = host->sg_cpu; | |
349 | ||
350 | for (i = 0; i < sg_len; i++, desc++) { | |
351 | unsigned int length = sg_dma_len(&data->sg[i]); | |
352 | u32 mem_addr = sg_dma_address(&data->sg[i]); | |
353 | ||
354 | /* Set the OWN bit and disable interrupts for this descriptor */ | |
355 | desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH; | |
356 | ||
357 | /* Buffer length */ | |
358 | IDMAC_SET_BUFFER1_SIZE(desc, length); | |
359 | ||
360 | /* Physical address to DMA to/from */ | |
361 | desc->des2 = mem_addr; | |
362 | } | |
363 | ||
364 | /* Set first descriptor */ | |
365 | desc = host->sg_cpu; | |
366 | desc->des0 |= IDMAC_DES0_FD; | |
367 | ||
368 | /* Set last descriptor */ | |
369 | desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc); | |
370 | desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); | |
371 | desc->des0 |= IDMAC_DES0_LD; | |
372 | ||
373 | wmb(); | |
374 | } | |
375 | ||
376 | static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len) | |
377 | { | |
378 | u32 temp; | |
379 | ||
380 | dw_mci_translate_sglist(host, host->data, sg_len); | |
381 | ||
382 | /* Select IDMAC interface */ | |
383 | temp = mci_readl(host, CTRL); | |
384 | temp |= SDMMC_CTRL_USE_IDMAC; | |
385 | mci_writel(host, CTRL, temp); | |
386 | ||
387 | wmb(); | |
388 | ||
389 | /* Enable the IDMAC */ | |
390 | temp = mci_readl(host, BMOD); | |
a5289a43 | 391 | temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB; |
f95f3850 WN |
392 | mci_writel(host, BMOD, temp); |
393 | ||
394 | /* Start it running */ | |
395 | mci_writel(host, PLDMND, 1); | |
396 | } | |
397 | ||
398 | static int dw_mci_idmac_init(struct dw_mci *host) | |
399 | { | |
400 | struct idmac_desc *p; | |
401 | int i; | |
402 | ||
403 | /* Number of descriptors in the ring buffer */ | |
404 | host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc); | |
405 | ||
406 | /* Forward link the descriptor list */ | |
407 | for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++) | |
408 | p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1)); | |
409 | ||
410 | /* Set the last descriptor as the end-of-ring descriptor */ | |
411 | p->des3 = host->sg_dma; | |
412 | p->des0 = IDMAC_DES0_ER; | |
413 | ||
414 | /* Mask out interrupts - get Tx & Rx complete only */ | |
415 | mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI | | |
416 | SDMMC_IDMAC_INT_TI); | |
417 | ||
418 | /* Set the descriptor base address */ | |
419 | mci_writel(host, DBADDR, host->sg_dma); | |
420 | return 0; | |
421 | } | |
422 | ||
423 | static struct dw_mci_dma_ops dw_mci_idmac_ops = { | |
424 | .init = dw_mci_idmac_init, | |
425 | .start = dw_mci_idmac_start_dma, | |
426 | .stop = dw_mci_idmac_stop_dma, | |
427 | .complete = dw_mci_idmac_complete_dma, | |
428 | .cleanup = dw_mci_dma_cleanup, | |
429 | }; | |
430 | #endif /* CONFIG_MMC_DW_IDMAC */ | |
431 | ||
432 | static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data) | |
433 | { | |
434 | struct scatterlist *sg; | |
435 | unsigned int i, direction, sg_len; | |
436 | u32 temp; | |
437 | ||
03e8cb53 JH |
438 | host->using_dma = 0; |
439 | ||
f95f3850 WN |
440 | /* If we don't have a channel, we can't do DMA */ |
441 | if (!host->use_dma) | |
442 | return -ENODEV; | |
443 | ||
444 | /* | |
445 | * We don't do DMA on "complex" transfers, i.e. with | |
446 | * non-word-aligned buffers or lengths. Also, we don't bother | |
447 | * with all the DMA setup overhead for short transfers. | |
448 | */ | |
449 | if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) | |
450 | return -EINVAL; | |
451 | if (data->blksz & 3) | |
452 | return -EINVAL; | |
453 | ||
454 | for_each_sg(data->sg, sg, data->sg_len, i) { | |
455 | if (sg->offset & 3 || sg->length & 3) | |
456 | return -EINVAL; | |
457 | } | |
458 | ||
03e8cb53 JH |
459 | host->using_dma = 1; |
460 | ||
f95f3850 WN |
461 | if (data->flags & MMC_DATA_READ) |
462 | direction = DMA_FROM_DEVICE; | |
463 | else | |
464 | direction = DMA_TO_DEVICE; | |
465 | ||
466 | sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, | |
467 | direction); | |
468 | ||
469 | dev_vdbg(&host->pdev->dev, | |
470 | "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n", | |
471 | (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma, | |
472 | sg_len); | |
473 | ||
474 | /* Enable the DMA interface */ | |
475 | temp = mci_readl(host, CTRL); | |
476 | temp |= SDMMC_CTRL_DMA_ENABLE; | |
477 | mci_writel(host, CTRL, temp); | |
478 | ||
479 | /* Disable RX/TX IRQs, let DMA handle it */ | |
480 | temp = mci_readl(host, INTMASK); | |
481 | temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR); | |
482 | mci_writel(host, INTMASK, temp); | |
483 | ||
484 | host->dma_ops->start(host, sg_len); | |
485 | ||
486 | return 0; | |
487 | } | |
488 | ||
489 | static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data) | |
490 | { | |
491 | u32 temp; | |
492 | ||
493 | data->error = -EINPROGRESS; | |
494 | ||
495 | WARN_ON(host->data); | |
496 | host->sg = NULL; | |
497 | host->data = data; | |
498 | ||
55c5efbc JH |
499 | if (data->flags & MMC_DATA_READ) |
500 | host->dir_status = DW_MCI_RECV_STATUS; | |
501 | else | |
502 | host->dir_status = DW_MCI_SEND_STATUS; | |
503 | ||
f95f3850 WN |
504 | if (dw_mci_submit_data_dma(host, data)) { |
505 | host->sg = data->sg; | |
506 | host->pio_offset = 0; | |
34b664a2 JH |
507 | host->part_buf_start = 0; |
508 | host->part_buf_count = 0; | |
f95f3850 | 509 | |
b40af3aa | 510 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR); |
f95f3850 WN |
511 | temp = mci_readl(host, INTMASK); |
512 | temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR; | |
513 | mci_writel(host, INTMASK, temp); | |
514 | ||
515 | temp = mci_readl(host, CTRL); | |
516 | temp &= ~SDMMC_CTRL_DMA_ENABLE; | |
517 | mci_writel(host, CTRL, temp); | |
518 | } | |
519 | } | |
520 | ||
521 | static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg) | |
522 | { | |
523 | struct dw_mci *host = slot->host; | |
524 | unsigned long timeout = jiffies + msecs_to_jiffies(500); | |
525 | unsigned int cmd_status = 0; | |
526 | ||
527 | mci_writel(host, CMDARG, arg); | |
528 | wmb(); | |
529 | mci_writel(host, CMD, SDMMC_CMD_START | cmd); | |
530 | ||
531 | while (time_before(jiffies, timeout)) { | |
532 | cmd_status = mci_readl(host, CMD); | |
533 | if (!(cmd_status & SDMMC_CMD_START)) | |
534 | return; | |
535 | } | |
536 | dev_err(&slot->mmc->class_dev, | |
537 | "Timeout sending command (cmd %#x arg %#x status %#x)\n", | |
538 | cmd, arg, cmd_status); | |
539 | } | |
540 | ||
541 | static void dw_mci_setup_bus(struct dw_mci_slot *slot) | |
542 | { | |
543 | struct dw_mci *host = slot->host; | |
544 | u32 div; | |
545 | ||
546 | if (slot->clock != host->current_speed) { | |
547 | if (host->bus_hz % slot->clock) | |
548 | /* | |
549 | * move the + 1 after the divide to prevent | |
550 | * over-clocking the card. | |
551 | */ | |
552 | div = ((host->bus_hz / slot->clock) >> 1) + 1; | |
553 | else | |
554 | div = (host->bus_hz / slot->clock) >> 1; | |
555 | ||
556 | dev_info(&slot->mmc->class_dev, | |
557 | "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ" | |
558 | " div = %d)\n", slot->id, host->bus_hz, slot->clock, | |
559 | div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div); | |
560 | ||
561 | /* disable clock */ | |
562 | mci_writel(host, CLKENA, 0); | |
563 | mci_writel(host, CLKSRC, 0); | |
564 | ||
565 | /* inform CIU */ | |
566 | mci_send_cmd(slot, | |
567 | SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
568 | ||
569 | /* set clock to desired speed */ | |
570 | mci_writel(host, CLKDIV, div); | |
571 | ||
572 | /* inform CIU */ | |
573 | mci_send_cmd(slot, | |
574 | SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
575 | ||
576 | /* enable clock */ | |
aadb9f41 WN |
577 | mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE | |
578 | SDMMC_CLKEN_LOW_PWR); | |
f95f3850 WN |
579 | |
580 | /* inform CIU */ | |
581 | mci_send_cmd(slot, | |
582 | SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0); | |
583 | ||
584 | host->current_speed = slot->clock; | |
585 | } | |
586 | ||
587 | /* Set the current slot bus width */ | |
1d56c453 | 588 | mci_writel(host, CTYPE, (slot->ctype << slot->id)); |
f95f3850 WN |
589 | } |
590 | ||
591 | static void dw_mci_start_request(struct dw_mci *host, | |
592 | struct dw_mci_slot *slot) | |
593 | { | |
594 | struct mmc_request *mrq; | |
595 | struct mmc_command *cmd; | |
596 | struct mmc_data *data; | |
597 | u32 cmdflags; | |
598 | ||
599 | mrq = slot->mrq; | |
600 | if (host->pdata->select_slot) | |
601 | host->pdata->select_slot(slot->id); | |
602 | ||
603 | /* Slot specific timing and width adjustment */ | |
604 | dw_mci_setup_bus(slot); | |
605 | ||
606 | host->cur_slot = slot; | |
607 | host->mrq = mrq; | |
608 | ||
609 | host->pending_events = 0; | |
610 | host->completed_events = 0; | |
611 | host->data_status = 0; | |
612 | ||
613 | data = mrq->data; | |
614 | if (data) { | |
615 | dw_mci_set_timeout(host); | |
616 | mci_writel(host, BYTCNT, data->blksz*data->blocks); | |
617 | mci_writel(host, BLKSIZ, data->blksz); | |
618 | } | |
619 | ||
620 | cmd = mrq->cmd; | |
621 | cmdflags = dw_mci_prepare_command(slot->mmc, cmd); | |
622 | ||
623 | /* this is the first command, send the initialization clock */ | |
624 | if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) | |
625 | cmdflags |= SDMMC_CMD_INIT; | |
626 | ||
627 | if (data) { | |
628 | dw_mci_submit_data(host, data); | |
629 | wmb(); | |
630 | } | |
631 | ||
632 | dw_mci_start_command(host, cmd, cmdflags); | |
633 | ||
634 | if (mrq->stop) | |
635 | host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop); | |
636 | } | |
637 | ||
7456caae | 638 | /* must be called with host->lock held */ |
f95f3850 WN |
639 | static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot, |
640 | struct mmc_request *mrq) | |
641 | { | |
642 | dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", | |
643 | host->state); | |
644 | ||
f95f3850 WN |
645 | slot->mrq = mrq; |
646 | ||
647 | if (host->state == STATE_IDLE) { | |
648 | host->state = STATE_SENDING_CMD; | |
649 | dw_mci_start_request(host, slot); | |
650 | } else { | |
651 | list_add_tail(&slot->queue_node, &host->queue); | |
652 | } | |
f95f3850 WN |
653 | } |
654 | ||
655 | static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
656 | { | |
657 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
658 | struct dw_mci *host = slot->host; | |
659 | ||
660 | WARN_ON(slot->mrq); | |
661 | ||
7456caae JH |
662 | /* |
663 | * The check for card presence and queueing of the request must be | |
664 | * atomic, otherwise the card could be removed in between and the | |
665 | * request wouldn't fail until another card was inserted. | |
666 | */ | |
667 | spin_lock_bh(&host->lock); | |
668 | ||
f95f3850 | 669 | if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { |
7456caae | 670 | spin_unlock_bh(&host->lock); |
f95f3850 WN |
671 | mrq->cmd->error = -ENOMEDIUM; |
672 | mmc_request_done(mmc, mrq); | |
673 | return; | |
674 | } | |
675 | ||
f95f3850 | 676 | dw_mci_queue_request(host, slot, mrq); |
7456caae JH |
677 | |
678 | spin_unlock_bh(&host->lock); | |
f95f3850 WN |
679 | } |
680 | ||
681 | static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
682 | { | |
683 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
41babf75 | 684 | u32 regs; |
f95f3850 WN |
685 | |
686 | /* set default 1 bit mode */ | |
687 | slot->ctype = SDMMC_CTYPE_1BIT; | |
688 | ||
689 | switch (ios->bus_width) { | |
690 | case MMC_BUS_WIDTH_1: | |
691 | slot->ctype = SDMMC_CTYPE_1BIT; | |
692 | break; | |
693 | case MMC_BUS_WIDTH_4: | |
694 | slot->ctype = SDMMC_CTYPE_4BIT; | |
695 | break; | |
c9b2a06f JC |
696 | case MMC_BUS_WIDTH_8: |
697 | slot->ctype = SDMMC_CTYPE_8BIT; | |
698 | break; | |
f95f3850 WN |
699 | } |
700 | ||
41babf75 | 701 | /* DDR mode set */ |
6daa7778 | 702 | if (ios->timing == MMC_TIMING_UHS_DDR50) { |
41babf75 JC |
703 | regs = mci_readl(slot->host, UHS_REG); |
704 | regs |= (0x1 << slot->id) << 16; | |
705 | mci_writel(slot->host, UHS_REG, regs); | |
706 | } | |
707 | ||
f95f3850 WN |
708 | if (ios->clock) { |
709 | /* | |
710 | * Use mirror of ios->clock to prevent race with mmc | |
711 | * core ios update when finding the minimum. | |
712 | */ | |
713 | slot->clock = ios->clock; | |
714 | } | |
715 | ||
716 | switch (ios->power_mode) { | |
717 | case MMC_POWER_UP: | |
718 | set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); | |
719 | break; | |
720 | default: | |
721 | break; | |
722 | } | |
723 | } | |
724 | ||
725 | static int dw_mci_get_ro(struct mmc_host *mmc) | |
726 | { | |
727 | int read_only; | |
728 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
729 | struct dw_mci_board *brd = slot->host->pdata; | |
730 | ||
731 | /* Use platform get_ro function, else try on board write protect */ | |
732 | if (brd->get_ro) | |
733 | read_only = brd->get_ro(slot->id); | |
734 | else | |
735 | read_only = | |
736 | mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; | |
737 | ||
738 | dev_dbg(&mmc->class_dev, "card is %s\n", | |
739 | read_only ? "read-only" : "read-write"); | |
740 | ||
741 | return read_only; | |
742 | } | |
743 | ||
744 | static int dw_mci_get_cd(struct mmc_host *mmc) | |
745 | { | |
746 | int present; | |
747 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
748 | struct dw_mci_board *brd = slot->host->pdata; | |
749 | ||
750 | /* Use platform get_cd function, else try onboard card detect */ | |
fc3d7720 JC |
751 | if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) |
752 | present = 1; | |
753 | else if (brd->get_cd) | |
f95f3850 WN |
754 | present = !brd->get_cd(slot->id); |
755 | else | |
756 | present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) | |
757 | == 0 ? 1 : 0; | |
758 | ||
759 | if (present) | |
760 | dev_dbg(&mmc->class_dev, "card is present\n"); | |
761 | else | |
762 | dev_dbg(&mmc->class_dev, "card is not present\n"); | |
763 | ||
764 | return present; | |
765 | } | |
766 | ||
1a5c8e1f SH |
767 | static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb) |
768 | { | |
769 | struct dw_mci_slot *slot = mmc_priv(mmc); | |
770 | struct dw_mci *host = slot->host; | |
771 | u32 int_mask; | |
772 | ||
773 | /* Enable/disable Slot Specific SDIO interrupt */ | |
774 | int_mask = mci_readl(host, INTMASK); | |
775 | if (enb) { | |
776 | mci_writel(host, INTMASK, | |
777 | (int_mask | (1 << SDMMC_INT_SDIO(slot->id)))); | |
778 | } else { | |
779 | mci_writel(host, INTMASK, | |
780 | (int_mask & ~(1 << SDMMC_INT_SDIO(slot->id)))); | |
781 | } | |
782 | } | |
783 | ||
f95f3850 | 784 | static const struct mmc_host_ops dw_mci_ops = { |
1a5c8e1f SH |
785 | .request = dw_mci_request, |
786 | .set_ios = dw_mci_set_ios, | |
787 | .get_ro = dw_mci_get_ro, | |
788 | .get_cd = dw_mci_get_cd, | |
789 | .enable_sdio_irq = dw_mci_enable_sdio_irq, | |
f95f3850 WN |
790 | }; |
791 | ||
792 | static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq) | |
793 | __releases(&host->lock) | |
794 | __acquires(&host->lock) | |
795 | { | |
796 | struct dw_mci_slot *slot; | |
797 | struct mmc_host *prev_mmc = host->cur_slot->mmc; | |
798 | ||
799 | WARN_ON(host->cmd || host->data); | |
800 | ||
801 | host->cur_slot->mrq = NULL; | |
802 | host->mrq = NULL; | |
803 | if (!list_empty(&host->queue)) { | |
804 | slot = list_entry(host->queue.next, | |
805 | struct dw_mci_slot, queue_node); | |
806 | list_del(&slot->queue_node); | |
807 | dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n", | |
808 | mmc_hostname(slot->mmc)); | |
809 | host->state = STATE_SENDING_CMD; | |
810 | dw_mci_start_request(host, slot); | |
811 | } else { | |
812 | dev_vdbg(&host->pdev->dev, "list empty\n"); | |
813 | host->state = STATE_IDLE; | |
814 | } | |
815 | ||
816 | spin_unlock(&host->lock); | |
817 | mmc_request_done(prev_mmc, mrq); | |
818 | spin_lock(&host->lock); | |
819 | } | |
820 | ||
821 | static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd) | |
822 | { | |
823 | u32 status = host->cmd_status; | |
824 | ||
825 | host->cmd_status = 0; | |
826 | ||
827 | /* Read the response from the card (up to 16 bytes) */ | |
828 | if (cmd->flags & MMC_RSP_PRESENT) { | |
829 | if (cmd->flags & MMC_RSP_136) { | |
830 | cmd->resp[3] = mci_readl(host, RESP0); | |
831 | cmd->resp[2] = mci_readl(host, RESP1); | |
832 | cmd->resp[1] = mci_readl(host, RESP2); | |
833 | cmd->resp[0] = mci_readl(host, RESP3); | |
834 | } else { | |
835 | cmd->resp[0] = mci_readl(host, RESP0); | |
836 | cmd->resp[1] = 0; | |
837 | cmd->resp[2] = 0; | |
838 | cmd->resp[3] = 0; | |
839 | } | |
840 | } | |
841 | ||
842 | if (status & SDMMC_INT_RTO) | |
843 | cmd->error = -ETIMEDOUT; | |
844 | else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) | |
845 | cmd->error = -EILSEQ; | |
846 | else if (status & SDMMC_INT_RESP_ERR) | |
847 | cmd->error = -EIO; | |
848 | else | |
849 | cmd->error = 0; | |
850 | ||
851 | if (cmd->error) { | |
852 | /* newer ip versions need a delay between retries */ | |
853 | if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY) | |
854 | mdelay(20); | |
855 | ||
856 | if (cmd->data) { | |
857 | host->data = NULL; | |
858 | dw_mci_stop_dma(host); | |
859 | } | |
860 | } | |
861 | } | |
862 | ||
863 | static void dw_mci_tasklet_func(unsigned long priv) | |
864 | { | |
865 | struct dw_mci *host = (struct dw_mci *)priv; | |
866 | struct mmc_data *data; | |
867 | struct mmc_command *cmd; | |
868 | enum dw_mci_state state; | |
869 | enum dw_mci_state prev_state; | |
94dd5b33 | 870 | u32 status, ctrl; |
f95f3850 WN |
871 | |
872 | spin_lock(&host->lock); | |
873 | ||
874 | state = host->state; | |
875 | data = host->data; | |
876 | ||
877 | do { | |
878 | prev_state = state; | |
879 | ||
880 | switch (state) { | |
881 | case STATE_IDLE: | |
882 | break; | |
883 | ||
884 | case STATE_SENDING_CMD: | |
885 | if (!test_and_clear_bit(EVENT_CMD_COMPLETE, | |
886 | &host->pending_events)) | |
887 | break; | |
888 | ||
889 | cmd = host->cmd; | |
890 | host->cmd = NULL; | |
891 | set_bit(EVENT_CMD_COMPLETE, &host->completed_events); | |
892 | dw_mci_command_complete(host, host->mrq->cmd); | |
893 | if (!host->mrq->data || cmd->error) { | |
894 | dw_mci_request_end(host, host->mrq); | |
895 | goto unlock; | |
896 | } | |
897 | ||
898 | prev_state = state = STATE_SENDING_DATA; | |
899 | /* fall through */ | |
900 | ||
901 | case STATE_SENDING_DATA: | |
902 | if (test_and_clear_bit(EVENT_DATA_ERROR, | |
903 | &host->pending_events)) { | |
904 | dw_mci_stop_dma(host); | |
905 | if (data->stop) | |
906 | send_stop_cmd(host, data); | |
907 | state = STATE_DATA_ERROR; | |
908 | break; | |
909 | } | |
910 | ||
911 | if (!test_and_clear_bit(EVENT_XFER_COMPLETE, | |
912 | &host->pending_events)) | |
913 | break; | |
914 | ||
915 | set_bit(EVENT_XFER_COMPLETE, &host->completed_events); | |
916 | prev_state = state = STATE_DATA_BUSY; | |
917 | /* fall through */ | |
918 | ||
919 | case STATE_DATA_BUSY: | |
920 | if (!test_and_clear_bit(EVENT_DATA_COMPLETE, | |
921 | &host->pending_events)) | |
922 | break; | |
923 | ||
924 | host->data = NULL; | |
925 | set_bit(EVENT_DATA_COMPLETE, &host->completed_events); | |
926 | status = host->data_status; | |
927 | ||
928 | if (status & DW_MCI_DATA_ERROR_FLAGS) { | |
929 | if (status & SDMMC_INT_DTO) { | |
f95f3850 WN |
930 | data->error = -ETIMEDOUT; |
931 | } else if (status & SDMMC_INT_DCRC) { | |
f95f3850 | 932 | data->error = -EILSEQ; |
55c5efbc JH |
933 | } else if (status & SDMMC_INT_EBE && |
934 | host->dir_status == | |
935 | DW_MCI_SEND_STATUS) { | |
936 | /* | |
937 | * No data CRC status was returned. | |
938 | * The number of bytes transferred will | |
939 | * be exaggerated in PIO mode. | |
940 | */ | |
941 | data->bytes_xfered = 0; | |
942 | data->error = -ETIMEDOUT; | |
f95f3850 WN |
943 | } else { |
944 | dev_err(&host->pdev->dev, | |
945 | "data FIFO error " | |
946 | "(status=%08x)\n", | |
947 | status); | |
948 | data->error = -EIO; | |
949 | } | |
94dd5b33 JH |
950 | /* |
951 | * After an error, there may be data lingering | |
952 | * in the FIFO, so reset it - doing so | |
953 | * generates a block interrupt, hence setting | |
954 | * the scatter-gather pointer to NULL. | |
955 | */ | |
956 | host->sg = NULL; | |
957 | ctrl = mci_readl(host, CTRL); | |
958 | ctrl |= SDMMC_CTRL_FIFO_RESET; | |
959 | mci_writel(host, CTRL, ctrl); | |
f95f3850 WN |
960 | } else { |
961 | data->bytes_xfered = data->blocks * data->blksz; | |
962 | data->error = 0; | |
963 | } | |
964 | ||
965 | if (!data->stop) { | |
966 | dw_mci_request_end(host, host->mrq); | |
967 | goto unlock; | |
968 | } | |
969 | ||
970 | prev_state = state = STATE_SENDING_STOP; | |
971 | if (!data->error) | |
972 | send_stop_cmd(host, data); | |
973 | /* fall through */ | |
974 | ||
975 | case STATE_SENDING_STOP: | |
976 | if (!test_and_clear_bit(EVENT_CMD_COMPLETE, | |
977 | &host->pending_events)) | |
978 | break; | |
979 | ||
980 | host->cmd = NULL; | |
981 | dw_mci_command_complete(host, host->mrq->stop); | |
982 | dw_mci_request_end(host, host->mrq); | |
983 | goto unlock; | |
984 | ||
985 | case STATE_DATA_ERROR: | |
986 | if (!test_and_clear_bit(EVENT_XFER_COMPLETE, | |
987 | &host->pending_events)) | |
988 | break; | |
989 | ||
990 | state = STATE_DATA_BUSY; | |
991 | break; | |
992 | } | |
993 | } while (state != prev_state); | |
994 | ||
995 | host->state = state; | |
996 | unlock: | |
997 | spin_unlock(&host->lock); | |
998 | ||
999 | } | |
1000 | ||
34b664a2 JH |
1001 | /* push final bytes to part_buf, only use during push */ |
1002 | static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
f95f3850 | 1003 | { |
34b664a2 JH |
1004 | memcpy((void *)&host->part_buf, buf, cnt); |
1005 | host->part_buf_count = cnt; | |
1006 | } | |
f95f3850 | 1007 | |
34b664a2 JH |
1008 | /* append bytes to part_buf, only use during push */ |
1009 | static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
1010 | { | |
1011 | cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); | |
1012 | memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); | |
1013 | host->part_buf_count += cnt; | |
1014 | return cnt; | |
1015 | } | |
f95f3850 | 1016 | |
34b664a2 JH |
1017 | /* pull first bytes from part_buf, only use during pull */ |
1018 | static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt) | |
1019 | { | |
1020 | cnt = min(cnt, (int)host->part_buf_count); | |
1021 | if (cnt) { | |
1022 | memcpy(buf, (void *)&host->part_buf + host->part_buf_start, | |
1023 | cnt); | |
1024 | host->part_buf_count -= cnt; | |
1025 | host->part_buf_start += cnt; | |
f95f3850 | 1026 | } |
34b664a2 | 1027 | return cnt; |
f95f3850 WN |
1028 | } |
1029 | ||
34b664a2 JH |
1030 | /* pull final bytes from the part_buf, assuming it's just been filled */ |
1031 | static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt) | |
f95f3850 | 1032 | { |
34b664a2 JH |
1033 | memcpy(buf, &host->part_buf, cnt); |
1034 | host->part_buf_start = cnt; | |
1035 | host->part_buf_count = (1 << host->data_shift) - cnt; | |
1036 | } | |
f95f3850 | 1037 | |
34b664a2 JH |
1038 | static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt) |
1039 | { | |
1040 | /* try and push anything in the part_buf */ | |
1041 | if (unlikely(host->part_buf_count)) { | |
1042 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1043 | buf += len; | |
1044 | cnt -= len; | |
1045 | if (!sg_next(host->sg) || host->part_buf_count == 2) { | |
4e0a5adf JC |
1046 | mci_writew(host, DATA(host->data_offset), |
1047 | host->part_buf16); | |
34b664a2 JH |
1048 | host->part_buf_count = 0; |
1049 | } | |
1050 | } | |
1051 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1052 | if (unlikely((unsigned long)buf & 0x1)) { | |
1053 | while (cnt >= 2) { | |
1054 | u16 aligned_buf[64]; | |
1055 | int len = min(cnt & -2, (int)sizeof(aligned_buf)); | |
1056 | int items = len >> 1; | |
1057 | int i; | |
1058 | /* memcpy from input buffer into aligned buffer */ | |
1059 | memcpy(aligned_buf, buf, len); | |
1060 | buf += len; | |
1061 | cnt -= len; | |
1062 | /* push data from aligned buffer into fifo */ | |
1063 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1064 | mci_writew(host, DATA(host->data_offset), |
1065 | aligned_buf[i]); | |
34b664a2 JH |
1066 | } |
1067 | } else | |
1068 | #endif | |
1069 | { | |
1070 | u16 *pdata = buf; | |
1071 | for (; cnt >= 2; cnt -= 2) | |
4e0a5adf | 1072 | mci_writew(host, DATA(host->data_offset), *pdata++); |
34b664a2 JH |
1073 | buf = pdata; |
1074 | } | |
1075 | /* put anything remaining in the part_buf */ | |
1076 | if (cnt) { | |
1077 | dw_mci_set_part_bytes(host, buf, cnt); | |
1078 | if (!sg_next(host->sg)) | |
4e0a5adf JC |
1079 | mci_writew(host, DATA(host->data_offset), |
1080 | host->part_buf16); | |
34b664a2 JH |
1081 | } |
1082 | } | |
f95f3850 | 1083 | |
34b664a2 JH |
1084 | static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt) |
1085 | { | |
1086 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1087 | if (unlikely((unsigned long)buf & 0x1)) { | |
1088 | while (cnt >= 2) { | |
1089 | /* pull data from fifo into aligned buffer */ | |
1090 | u16 aligned_buf[64]; | |
1091 | int len = min(cnt & -2, (int)sizeof(aligned_buf)); | |
1092 | int items = len >> 1; | |
1093 | int i; | |
1094 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1095 | aligned_buf[i] = mci_readw(host, |
1096 | DATA(host->data_offset)); | |
34b664a2 JH |
1097 | /* memcpy from aligned buffer into output buffer */ |
1098 | memcpy(buf, aligned_buf, len); | |
1099 | buf += len; | |
1100 | cnt -= len; | |
1101 | } | |
1102 | } else | |
1103 | #endif | |
1104 | { | |
1105 | u16 *pdata = buf; | |
1106 | for (; cnt >= 2; cnt -= 2) | |
4e0a5adf | 1107 | *pdata++ = mci_readw(host, DATA(host->data_offset)); |
34b664a2 JH |
1108 | buf = pdata; |
1109 | } | |
1110 | if (cnt) { | |
4e0a5adf | 1111 | host->part_buf16 = mci_readw(host, DATA(host->data_offset)); |
34b664a2 | 1112 | dw_mci_pull_final_bytes(host, buf, cnt); |
f95f3850 WN |
1113 | } |
1114 | } | |
1115 | ||
1116 | static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt) | |
1117 | { | |
34b664a2 JH |
1118 | /* try and push anything in the part_buf */ |
1119 | if (unlikely(host->part_buf_count)) { | |
1120 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1121 | buf += len; | |
1122 | cnt -= len; | |
1123 | if (!sg_next(host->sg) || host->part_buf_count == 4) { | |
4e0a5adf JC |
1124 | mci_writel(host, DATA(host->data_offset), |
1125 | host->part_buf32); | |
34b664a2 JH |
1126 | host->part_buf_count = 0; |
1127 | } | |
1128 | } | |
1129 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1130 | if (unlikely((unsigned long)buf & 0x3)) { | |
1131 | while (cnt >= 4) { | |
1132 | u32 aligned_buf[32]; | |
1133 | int len = min(cnt & -4, (int)sizeof(aligned_buf)); | |
1134 | int items = len >> 2; | |
1135 | int i; | |
1136 | /* memcpy from input buffer into aligned buffer */ | |
1137 | memcpy(aligned_buf, buf, len); | |
1138 | buf += len; | |
1139 | cnt -= len; | |
1140 | /* push data from aligned buffer into fifo */ | |
1141 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1142 | mci_writel(host, DATA(host->data_offset), |
1143 | aligned_buf[i]); | |
34b664a2 JH |
1144 | } |
1145 | } else | |
1146 | #endif | |
1147 | { | |
1148 | u32 *pdata = buf; | |
1149 | for (; cnt >= 4; cnt -= 4) | |
4e0a5adf | 1150 | mci_writel(host, DATA(host->data_offset), *pdata++); |
34b664a2 JH |
1151 | buf = pdata; |
1152 | } | |
1153 | /* put anything remaining in the part_buf */ | |
1154 | if (cnt) { | |
1155 | dw_mci_set_part_bytes(host, buf, cnt); | |
1156 | if (!sg_next(host->sg)) | |
4e0a5adf JC |
1157 | mci_writel(host, DATA(host->data_offset), |
1158 | host->part_buf32); | |
f95f3850 WN |
1159 | } |
1160 | } | |
1161 | ||
1162 | static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt) | |
1163 | { | |
34b664a2 JH |
1164 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
1165 | if (unlikely((unsigned long)buf & 0x3)) { | |
1166 | while (cnt >= 4) { | |
1167 | /* pull data from fifo into aligned buffer */ | |
1168 | u32 aligned_buf[32]; | |
1169 | int len = min(cnt & -4, (int)sizeof(aligned_buf)); | |
1170 | int items = len >> 2; | |
1171 | int i; | |
1172 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1173 | aligned_buf[i] = mci_readl(host, |
1174 | DATA(host->data_offset)); | |
34b664a2 JH |
1175 | /* memcpy from aligned buffer into output buffer */ |
1176 | memcpy(buf, aligned_buf, len); | |
1177 | buf += len; | |
1178 | cnt -= len; | |
1179 | } | |
1180 | } else | |
1181 | #endif | |
1182 | { | |
1183 | u32 *pdata = buf; | |
1184 | for (; cnt >= 4; cnt -= 4) | |
4e0a5adf | 1185 | *pdata++ = mci_readl(host, DATA(host->data_offset)); |
34b664a2 JH |
1186 | buf = pdata; |
1187 | } | |
1188 | if (cnt) { | |
4e0a5adf | 1189 | host->part_buf32 = mci_readl(host, DATA(host->data_offset)); |
34b664a2 | 1190 | dw_mci_pull_final_bytes(host, buf, cnt); |
f95f3850 WN |
1191 | } |
1192 | } | |
1193 | ||
1194 | static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt) | |
1195 | { | |
34b664a2 JH |
1196 | /* try and push anything in the part_buf */ |
1197 | if (unlikely(host->part_buf_count)) { | |
1198 | int len = dw_mci_push_part_bytes(host, buf, cnt); | |
1199 | buf += len; | |
1200 | cnt -= len; | |
1201 | if (!sg_next(host->sg) || host->part_buf_count == 8) { | |
4e0a5adf JC |
1202 | mci_writew(host, DATA(host->data_offset), |
1203 | host->part_buf); | |
34b664a2 JH |
1204 | host->part_buf_count = 0; |
1205 | } | |
1206 | } | |
1207 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS | |
1208 | if (unlikely((unsigned long)buf & 0x7)) { | |
1209 | while (cnt >= 8) { | |
1210 | u64 aligned_buf[16]; | |
1211 | int len = min(cnt & -8, (int)sizeof(aligned_buf)); | |
1212 | int items = len >> 3; | |
1213 | int i; | |
1214 | /* memcpy from input buffer into aligned buffer */ | |
1215 | memcpy(aligned_buf, buf, len); | |
1216 | buf += len; | |
1217 | cnt -= len; | |
1218 | /* push data from aligned buffer into fifo */ | |
1219 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1220 | mci_writeq(host, DATA(host->data_offset), |
1221 | aligned_buf[i]); | |
34b664a2 JH |
1222 | } |
1223 | } else | |
1224 | #endif | |
1225 | { | |
1226 | u64 *pdata = buf; | |
1227 | for (; cnt >= 8; cnt -= 8) | |
4e0a5adf | 1228 | mci_writeq(host, DATA(host->data_offset), *pdata++); |
34b664a2 JH |
1229 | buf = pdata; |
1230 | } | |
1231 | /* put anything remaining in the part_buf */ | |
1232 | if (cnt) { | |
1233 | dw_mci_set_part_bytes(host, buf, cnt); | |
1234 | if (!sg_next(host->sg)) | |
4e0a5adf JC |
1235 | mci_writeq(host, DATA(host->data_offset), |
1236 | host->part_buf); | |
f95f3850 WN |
1237 | } |
1238 | } | |
1239 | ||
1240 | static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt) | |
1241 | { | |
34b664a2 JH |
1242 | #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS |
1243 | if (unlikely((unsigned long)buf & 0x7)) { | |
1244 | while (cnt >= 8) { | |
1245 | /* pull data from fifo into aligned buffer */ | |
1246 | u64 aligned_buf[16]; | |
1247 | int len = min(cnt & -8, (int)sizeof(aligned_buf)); | |
1248 | int items = len >> 3; | |
1249 | int i; | |
1250 | for (i = 0; i < items; ++i) | |
4e0a5adf JC |
1251 | aligned_buf[i] = mci_readq(host, |
1252 | DATA(host->data_offset)); | |
34b664a2 JH |
1253 | /* memcpy from aligned buffer into output buffer */ |
1254 | memcpy(buf, aligned_buf, len); | |
1255 | buf += len; | |
1256 | cnt -= len; | |
1257 | } | |
1258 | } else | |
1259 | #endif | |
1260 | { | |
1261 | u64 *pdata = buf; | |
1262 | for (; cnt >= 8; cnt -= 8) | |
4e0a5adf | 1263 | *pdata++ = mci_readq(host, DATA(host->data_offset)); |
34b664a2 JH |
1264 | buf = pdata; |
1265 | } | |
1266 | if (cnt) { | |
4e0a5adf | 1267 | host->part_buf = mci_readq(host, DATA(host->data_offset)); |
34b664a2 JH |
1268 | dw_mci_pull_final_bytes(host, buf, cnt); |
1269 | } | |
1270 | } | |
f95f3850 | 1271 | |
34b664a2 JH |
1272 | static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt) |
1273 | { | |
1274 | int len; | |
f95f3850 | 1275 | |
34b664a2 JH |
1276 | /* get remaining partial bytes */ |
1277 | len = dw_mci_pull_part_bytes(host, buf, cnt); | |
1278 | if (unlikely(len == cnt)) | |
1279 | return; | |
1280 | buf += len; | |
1281 | cnt -= len; | |
1282 | ||
1283 | /* get the rest of the data */ | |
1284 | host->pull_data(host, buf, cnt); | |
f95f3850 WN |
1285 | } |
1286 | ||
1287 | static void dw_mci_read_data_pio(struct dw_mci *host) | |
1288 | { | |
1289 | struct scatterlist *sg = host->sg; | |
1290 | void *buf = sg_virt(sg); | |
1291 | unsigned int offset = host->pio_offset; | |
1292 | struct mmc_data *data = host->data; | |
1293 | int shift = host->data_shift; | |
1294 | u32 status; | |
ba6a902d | 1295 | unsigned int nbytes = 0, len; |
f95f3850 WN |
1296 | |
1297 | do { | |
34b664a2 JH |
1298 | len = host->part_buf_count + |
1299 | (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift); | |
f95f3850 | 1300 | if (offset + len <= sg->length) { |
34b664a2 | 1301 | dw_mci_pull_data(host, (void *)(buf + offset), len); |
f95f3850 WN |
1302 | |
1303 | offset += len; | |
1304 | nbytes += len; | |
1305 | ||
1306 | if (offset == sg->length) { | |
1307 | flush_dcache_page(sg_page(sg)); | |
1308 | host->sg = sg = sg_next(sg); | |
1309 | if (!sg) | |
1310 | goto done; | |
1311 | ||
1312 | offset = 0; | |
1313 | buf = sg_virt(sg); | |
1314 | } | |
1315 | } else { | |
1316 | unsigned int remaining = sg->length - offset; | |
34b664a2 JH |
1317 | dw_mci_pull_data(host, (void *)(buf + offset), |
1318 | remaining); | |
f95f3850 WN |
1319 | nbytes += remaining; |
1320 | ||
1321 | flush_dcache_page(sg_page(sg)); | |
1322 | host->sg = sg = sg_next(sg); | |
1323 | if (!sg) | |
1324 | goto done; | |
1325 | ||
1326 | offset = len - remaining; | |
1327 | buf = sg_virt(sg); | |
34b664a2 | 1328 | dw_mci_pull_data(host, buf, offset); |
f95f3850 WN |
1329 | nbytes += offset; |
1330 | } | |
1331 | ||
1332 | status = mci_readl(host, MINTSTS); | |
1333 | mci_writel(host, RINTSTS, SDMMC_INT_RXDR); | |
1334 | if (status & DW_MCI_DATA_ERROR_FLAGS) { | |
1335 | host->data_status = status; | |
1336 | data->bytes_xfered += nbytes; | |
1337 | smp_wmb(); | |
1338 | ||
1339 | set_bit(EVENT_DATA_ERROR, &host->pending_events); | |
1340 | ||
1341 | tasklet_schedule(&host->tasklet); | |
1342 | return; | |
1343 | } | |
f95f3850 | 1344 | } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/ |
f95f3850 WN |
1345 | host->pio_offset = offset; |
1346 | data->bytes_xfered += nbytes; | |
1347 | return; | |
1348 | ||
1349 | done: | |
1350 | data->bytes_xfered += nbytes; | |
1351 | smp_wmb(); | |
1352 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
1353 | } | |
1354 | ||
1355 | static void dw_mci_write_data_pio(struct dw_mci *host) | |
1356 | { | |
1357 | struct scatterlist *sg = host->sg; | |
1358 | void *buf = sg_virt(sg); | |
1359 | unsigned int offset = host->pio_offset; | |
1360 | struct mmc_data *data = host->data; | |
1361 | int shift = host->data_shift; | |
1362 | u32 status; | |
1363 | unsigned int nbytes = 0, len; | |
1364 | ||
1365 | do { | |
34b664a2 JH |
1366 | len = ((host->fifo_depth - |
1367 | SDMMC_GET_FCNT(mci_readl(host, STATUS))) << shift) | |
1368 | - host->part_buf_count; | |
f95f3850 WN |
1369 | if (offset + len <= sg->length) { |
1370 | host->push_data(host, (void *)(buf + offset), len); | |
1371 | ||
1372 | offset += len; | |
1373 | nbytes += len; | |
1374 | if (offset == sg->length) { | |
1375 | host->sg = sg = sg_next(sg); | |
1376 | if (!sg) | |
1377 | goto done; | |
1378 | ||
1379 | offset = 0; | |
1380 | buf = sg_virt(sg); | |
1381 | } | |
1382 | } else { | |
1383 | unsigned int remaining = sg->length - offset; | |
1384 | ||
1385 | host->push_data(host, (void *)(buf + offset), | |
1386 | remaining); | |
1387 | nbytes += remaining; | |
1388 | ||
1389 | host->sg = sg = sg_next(sg); | |
1390 | if (!sg) | |
1391 | goto done; | |
1392 | ||
1393 | offset = len - remaining; | |
1394 | buf = sg_virt(sg); | |
1395 | host->push_data(host, (void *)buf, offset); | |
1396 | nbytes += offset; | |
1397 | } | |
1398 | ||
1399 | status = mci_readl(host, MINTSTS); | |
1400 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR); | |
1401 | if (status & DW_MCI_DATA_ERROR_FLAGS) { | |
1402 | host->data_status = status; | |
1403 | data->bytes_xfered += nbytes; | |
1404 | ||
1405 | smp_wmb(); | |
1406 | ||
1407 | set_bit(EVENT_DATA_ERROR, &host->pending_events); | |
1408 | ||
1409 | tasklet_schedule(&host->tasklet); | |
1410 | return; | |
1411 | } | |
1412 | } while (status & SDMMC_INT_TXDR); /* if TXDR write again */ | |
f95f3850 WN |
1413 | host->pio_offset = offset; |
1414 | data->bytes_xfered += nbytes; | |
f95f3850 WN |
1415 | return; |
1416 | ||
1417 | done: | |
1418 | data->bytes_xfered += nbytes; | |
1419 | smp_wmb(); | |
1420 | set_bit(EVENT_XFER_COMPLETE, &host->pending_events); | |
1421 | } | |
1422 | ||
1423 | static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status) | |
1424 | { | |
1425 | if (!host->cmd_status) | |
1426 | host->cmd_status = status; | |
1427 | ||
1428 | smp_wmb(); | |
1429 | ||
1430 | set_bit(EVENT_CMD_COMPLETE, &host->pending_events); | |
1431 | tasklet_schedule(&host->tasklet); | |
1432 | } | |
1433 | ||
1434 | static irqreturn_t dw_mci_interrupt(int irq, void *dev_id) | |
1435 | { | |
1436 | struct dw_mci *host = dev_id; | |
1437 | u32 status, pending; | |
1438 | unsigned int pass_count = 0; | |
1a5c8e1f | 1439 | int i; |
f95f3850 WN |
1440 | |
1441 | do { | |
1442 | status = mci_readl(host, RINTSTS); | |
1443 | pending = mci_readl(host, MINTSTS); /* read-only mask reg */ | |
1444 | ||
1445 | /* | |
1446 | * DTO fix - version 2.10a and below, and only if internal DMA | |
1447 | * is configured. | |
1448 | */ | |
1449 | if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) { | |
1450 | if (!pending && | |
1451 | ((mci_readl(host, STATUS) >> 17) & 0x1fff)) | |
1452 | pending |= SDMMC_INT_DATA_OVER; | |
1453 | } | |
1454 | ||
1455 | if (!pending) | |
1456 | break; | |
1457 | ||
1458 | if (pending & DW_MCI_CMD_ERROR_FLAGS) { | |
1459 | mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS); | |
1460 | host->cmd_status = status; | |
1461 | smp_wmb(); | |
1462 | set_bit(EVENT_CMD_COMPLETE, &host->pending_events); | |
f95f3850 WN |
1463 | } |
1464 | ||
1465 | if (pending & DW_MCI_DATA_ERROR_FLAGS) { | |
1466 | /* if there is an error report DATA_ERROR */ | |
1467 | mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS); | |
1468 | host->data_status = status; | |
1469 | smp_wmb(); | |
1470 | set_bit(EVENT_DATA_ERROR, &host->pending_events); | |
6e83e10d SJ |
1471 | if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC | |
1472 | SDMMC_INT_SBE | SDMMC_INT_EBE))) | |
1473 | tasklet_schedule(&host->tasklet); | |
f95f3850 WN |
1474 | } |
1475 | ||
1476 | if (pending & SDMMC_INT_DATA_OVER) { | |
1477 | mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER); | |
1478 | if (!host->data_status) | |
1479 | host->data_status = status; | |
1480 | smp_wmb(); | |
1481 | if (host->dir_status == DW_MCI_RECV_STATUS) { | |
1482 | if (host->sg != NULL) | |
1483 | dw_mci_read_data_pio(host); | |
1484 | } | |
1485 | set_bit(EVENT_DATA_COMPLETE, &host->pending_events); | |
1486 | tasklet_schedule(&host->tasklet); | |
1487 | } | |
1488 | ||
1489 | if (pending & SDMMC_INT_RXDR) { | |
1490 | mci_writel(host, RINTSTS, SDMMC_INT_RXDR); | |
b40af3aa | 1491 | if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) |
f95f3850 WN |
1492 | dw_mci_read_data_pio(host); |
1493 | } | |
1494 | ||
1495 | if (pending & SDMMC_INT_TXDR) { | |
1496 | mci_writel(host, RINTSTS, SDMMC_INT_TXDR); | |
b40af3aa | 1497 | if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) |
f95f3850 WN |
1498 | dw_mci_write_data_pio(host); |
1499 | } | |
1500 | ||
1501 | if (pending & SDMMC_INT_CMD_DONE) { | |
1502 | mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE); | |
1503 | dw_mci_cmd_interrupt(host, status); | |
1504 | } | |
1505 | ||
1506 | if (pending & SDMMC_INT_CD) { | |
1507 | mci_writel(host, RINTSTS, SDMMC_INT_CD); | |
1791b13e | 1508 | queue_work(dw_mci_card_workqueue, &host->card_work); |
f95f3850 WN |
1509 | } |
1510 | ||
1a5c8e1f SH |
1511 | /* Handle SDIO Interrupts */ |
1512 | for (i = 0; i < host->num_slots; i++) { | |
1513 | struct dw_mci_slot *slot = host->slot[i]; | |
1514 | if (pending & SDMMC_INT_SDIO(i)) { | |
1515 | mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i)); | |
1516 | mmc_signal_sdio_irq(slot->mmc); | |
1517 | } | |
1518 | } | |
1519 | ||
f95f3850 WN |
1520 | } while (pass_count++ < 5); |
1521 | ||
1522 | #ifdef CONFIG_MMC_DW_IDMAC | |
1523 | /* Handle DMA interrupts */ | |
1524 | pending = mci_readl(host, IDSTS); | |
1525 | if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) { | |
1526 | mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI); | |
1527 | mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI); | |
1528 | set_bit(EVENT_DATA_COMPLETE, &host->pending_events); | |
1529 | host->dma_ops->complete(host); | |
1530 | } | |
1531 | #endif | |
1532 | ||
1533 | return IRQ_HANDLED; | |
1534 | } | |
1535 | ||
1791b13e | 1536 | static void dw_mci_work_routine_card(struct work_struct *work) |
f95f3850 | 1537 | { |
1791b13e | 1538 | struct dw_mci *host = container_of(work, struct dw_mci, card_work); |
f95f3850 WN |
1539 | int i; |
1540 | ||
1541 | for (i = 0; i < host->num_slots; i++) { | |
1542 | struct dw_mci_slot *slot = host->slot[i]; | |
1543 | struct mmc_host *mmc = slot->mmc; | |
1544 | struct mmc_request *mrq; | |
1545 | int present; | |
1546 | u32 ctrl; | |
1547 | ||
1548 | present = dw_mci_get_cd(mmc); | |
1549 | while (present != slot->last_detect_state) { | |
f95f3850 WN |
1550 | dev_dbg(&slot->mmc->class_dev, "card %s\n", |
1551 | present ? "inserted" : "removed"); | |
1552 | ||
1791b13e JH |
1553 | /* Power up slot (before spin_lock, may sleep) */ |
1554 | if (present != 0 && host->pdata->setpower) | |
1555 | host->pdata->setpower(slot->id, mmc->ocr_avail); | |
1556 | ||
1557 | spin_lock_bh(&host->lock); | |
1558 | ||
f95f3850 WN |
1559 | /* Card change detected */ |
1560 | slot->last_detect_state = present; | |
1561 | ||
1791b13e JH |
1562 | /* Mark card as present if applicable */ |
1563 | if (present != 0) | |
f95f3850 | 1564 | set_bit(DW_MMC_CARD_PRESENT, &slot->flags); |
f95f3850 WN |
1565 | |
1566 | /* Clean up queue if present */ | |
1567 | mrq = slot->mrq; | |
1568 | if (mrq) { | |
1569 | if (mrq == host->mrq) { | |
1570 | host->data = NULL; | |
1571 | host->cmd = NULL; | |
1572 | ||
1573 | switch (host->state) { | |
1574 | case STATE_IDLE: | |
1575 | break; | |
1576 | case STATE_SENDING_CMD: | |
1577 | mrq->cmd->error = -ENOMEDIUM; | |
1578 | if (!mrq->data) | |
1579 | break; | |
1580 | /* fall through */ | |
1581 | case STATE_SENDING_DATA: | |
1582 | mrq->data->error = -ENOMEDIUM; | |
1583 | dw_mci_stop_dma(host); | |
1584 | break; | |
1585 | case STATE_DATA_BUSY: | |
1586 | case STATE_DATA_ERROR: | |
1587 | if (mrq->data->error == -EINPROGRESS) | |
1588 | mrq->data->error = -ENOMEDIUM; | |
1589 | if (!mrq->stop) | |
1590 | break; | |
1591 | /* fall through */ | |
1592 | case STATE_SENDING_STOP: | |
1593 | mrq->stop->error = -ENOMEDIUM; | |
1594 | break; | |
1595 | } | |
1596 | ||
1597 | dw_mci_request_end(host, mrq); | |
1598 | } else { | |
1599 | list_del(&slot->queue_node); | |
1600 | mrq->cmd->error = -ENOMEDIUM; | |
1601 | if (mrq->data) | |
1602 | mrq->data->error = -ENOMEDIUM; | |
1603 | if (mrq->stop) | |
1604 | mrq->stop->error = -ENOMEDIUM; | |
1605 | ||
1606 | spin_unlock(&host->lock); | |
1607 | mmc_request_done(slot->mmc, mrq); | |
1608 | spin_lock(&host->lock); | |
1609 | } | |
1610 | } | |
1611 | ||
1612 | /* Power down slot */ | |
1613 | if (present == 0) { | |
f95f3850 WN |
1614 | clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); |
1615 | ||
1616 | /* | |
1617 | * Clear down the FIFO - doing so generates a | |
1618 | * block interrupt, hence setting the | |
1619 | * scatter-gather pointer to NULL. | |
1620 | */ | |
1621 | host->sg = NULL; | |
1622 | ||
1623 | ctrl = mci_readl(host, CTRL); | |
1624 | ctrl |= SDMMC_CTRL_FIFO_RESET; | |
1625 | mci_writel(host, CTRL, ctrl); | |
1626 | ||
1627 | #ifdef CONFIG_MMC_DW_IDMAC | |
1628 | ctrl = mci_readl(host, BMOD); | |
1629 | ctrl |= 0x01; /* Software reset of DMA */ | |
1630 | mci_writel(host, BMOD, ctrl); | |
1631 | #endif | |
1632 | ||
1633 | } | |
1634 | ||
1791b13e JH |
1635 | spin_unlock_bh(&host->lock); |
1636 | ||
1637 | /* Power down slot (after spin_unlock, may sleep) */ | |
1638 | if (present == 0 && host->pdata->setpower) | |
1639 | host->pdata->setpower(slot->id, 0); | |
1640 | ||
f95f3850 WN |
1641 | present = dw_mci_get_cd(mmc); |
1642 | } | |
1643 | ||
1644 | mmc_detect_change(slot->mmc, | |
1645 | msecs_to_jiffies(host->pdata->detect_delay_ms)); | |
1646 | } | |
1647 | } | |
1648 | ||
1649 | static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id) | |
1650 | { | |
1651 | struct mmc_host *mmc; | |
1652 | struct dw_mci_slot *slot; | |
1653 | ||
1654 | mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev); | |
1655 | if (!mmc) | |
1656 | return -ENOMEM; | |
1657 | ||
1658 | slot = mmc_priv(mmc); | |
1659 | slot->id = id; | |
1660 | slot->mmc = mmc; | |
1661 | slot->host = host; | |
1662 | ||
1663 | mmc->ops = &dw_mci_ops; | |
1664 | mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510); | |
1665 | mmc->f_max = host->bus_hz; | |
1666 | ||
1667 | if (host->pdata->get_ocr) | |
1668 | mmc->ocr_avail = host->pdata->get_ocr(id); | |
1669 | else | |
1670 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
1671 | ||
1672 | /* | |
1673 | * Start with slot power disabled, it will be enabled when a card | |
1674 | * is detected. | |
1675 | */ | |
1676 | if (host->pdata->setpower) | |
1677 | host->pdata->setpower(id, 0); | |
1678 | ||
fc3d7720 JC |
1679 | if (host->pdata->caps) |
1680 | mmc->caps = host->pdata->caps; | |
1681 | else | |
1682 | mmc->caps = 0; | |
1683 | ||
f95f3850 WN |
1684 | if (host->pdata->get_bus_wd) |
1685 | if (host->pdata->get_bus_wd(slot->id) >= 4) | |
1686 | mmc->caps |= MMC_CAP_4_BIT_DATA; | |
1687 | ||
1688 | if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED) | |
6daa7778 | 1689 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
f95f3850 WN |
1690 | |
1691 | #ifdef CONFIG_MMC_DW_IDMAC | |
1692 | mmc->max_segs = host->ring_size; | |
1693 | mmc->max_blk_size = 65536; | |
1694 | mmc->max_blk_count = host->ring_size; | |
1695 | mmc->max_seg_size = 0x1000; | |
1696 | mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count; | |
1697 | #else | |
1698 | if (host->pdata->blk_settings) { | |
1699 | mmc->max_segs = host->pdata->blk_settings->max_segs; | |
1700 | mmc->max_blk_size = host->pdata->blk_settings->max_blk_size; | |
1701 | mmc->max_blk_count = host->pdata->blk_settings->max_blk_count; | |
1702 | mmc->max_req_size = host->pdata->blk_settings->max_req_size; | |
1703 | mmc->max_seg_size = host->pdata->blk_settings->max_seg_size; | |
1704 | } else { | |
1705 | /* Useful defaults if platform data is unset. */ | |
1706 | mmc->max_segs = 64; | |
1707 | mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */ | |
1708 | mmc->max_blk_count = 512; | |
1709 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1710 | mmc->max_seg_size = mmc->max_req_size; | |
1711 | } | |
1712 | #endif /* CONFIG_MMC_DW_IDMAC */ | |
1713 | ||
c07946a3 JC |
1714 | host->vmmc = regulator_get(mmc_dev(mmc), "vmmc"); |
1715 | if (IS_ERR(host->vmmc)) { | |
a3c76eb9 | 1716 | pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc)); |
c07946a3 JC |
1717 | host->vmmc = NULL; |
1718 | } else | |
1719 | regulator_enable(host->vmmc); | |
1720 | ||
f95f3850 WN |
1721 | if (dw_mci_get_cd(mmc)) |
1722 | set_bit(DW_MMC_CARD_PRESENT, &slot->flags); | |
1723 | else | |
1724 | clear_bit(DW_MMC_CARD_PRESENT, &slot->flags); | |
1725 | ||
1726 | host->slot[id] = slot; | |
1727 | mmc_add_host(mmc); | |
1728 | ||
1729 | #if defined(CONFIG_DEBUG_FS) | |
1730 | dw_mci_init_debugfs(slot); | |
1731 | #endif | |
1732 | ||
1733 | /* Card initially undetected */ | |
1734 | slot->last_detect_state = 0; | |
1735 | ||
dd6c4b98 WN |
1736 | /* |
1737 | * Card may have been plugged in prior to boot so we | |
1738 | * need to run the detect tasklet | |
1739 | */ | |
1791b13e | 1740 | queue_work(dw_mci_card_workqueue, &host->card_work); |
dd6c4b98 | 1741 | |
f95f3850 WN |
1742 | return 0; |
1743 | } | |
1744 | ||
1745 | static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id) | |
1746 | { | |
1747 | /* Shutdown detect IRQ */ | |
1748 | if (slot->host->pdata->exit) | |
1749 | slot->host->pdata->exit(id); | |
1750 | ||
1751 | /* Debugfs stuff is cleaned up by mmc core */ | |
1752 | mmc_remove_host(slot->mmc); | |
1753 | slot->host->slot[id] = NULL; | |
1754 | mmc_free_host(slot->mmc); | |
1755 | } | |
1756 | ||
1757 | static void dw_mci_init_dma(struct dw_mci *host) | |
1758 | { | |
1759 | /* Alloc memory for sg translation */ | |
1760 | host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE, | |
1761 | &host->sg_dma, GFP_KERNEL); | |
1762 | if (!host->sg_cpu) { | |
1763 | dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n", | |
1764 | __func__); | |
1765 | goto no_dma; | |
1766 | } | |
1767 | ||
1768 | /* Determine which DMA interface to use */ | |
1769 | #ifdef CONFIG_MMC_DW_IDMAC | |
1770 | host->dma_ops = &dw_mci_idmac_ops; | |
1771 | dev_info(&host->pdev->dev, "Using internal DMA controller.\n"); | |
1772 | #endif | |
1773 | ||
1774 | if (!host->dma_ops) | |
1775 | goto no_dma; | |
1776 | ||
1777 | if (host->dma_ops->init) { | |
1778 | if (host->dma_ops->init(host)) { | |
1779 | dev_err(&host->pdev->dev, "%s: Unable to initialize " | |
1780 | "DMA Controller.\n", __func__); | |
1781 | goto no_dma; | |
1782 | } | |
1783 | } else { | |
1784 | dev_err(&host->pdev->dev, "DMA initialization not found.\n"); | |
1785 | goto no_dma; | |
1786 | } | |
1787 | ||
1788 | host->use_dma = 1; | |
1789 | return; | |
1790 | ||
1791 | no_dma: | |
1792 | dev_info(&host->pdev->dev, "Using PIO mode.\n"); | |
1793 | host->use_dma = 0; | |
1794 | return; | |
1795 | } | |
1796 | ||
1797 | static bool mci_wait_reset(struct device *dev, struct dw_mci *host) | |
1798 | { | |
1799 | unsigned long timeout = jiffies + msecs_to_jiffies(500); | |
1800 | unsigned int ctrl; | |
1801 | ||
1802 | mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | | |
1803 | SDMMC_CTRL_DMA_RESET)); | |
1804 | ||
1805 | /* wait till resets clear */ | |
1806 | do { | |
1807 | ctrl = mci_readl(host, CTRL); | |
1808 | if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | | |
1809 | SDMMC_CTRL_DMA_RESET))) | |
1810 | return true; | |
1811 | } while (time_before(jiffies, timeout)); | |
1812 | ||
1813 | dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl); | |
1814 | ||
1815 | return false; | |
1816 | } | |
1817 | ||
1818 | static int dw_mci_probe(struct platform_device *pdev) | |
1819 | { | |
1820 | struct dw_mci *host; | |
1821 | struct resource *regs; | |
1822 | struct dw_mci_board *pdata; | |
1823 | int irq, ret, i, width; | |
1824 | u32 fifo_size; | |
1825 | ||
1826 | regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1827 | if (!regs) | |
1828 | return -ENXIO; | |
1829 | ||
1830 | irq = platform_get_irq(pdev, 0); | |
1831 | if (irq < 0) | |
1832 | return irq; | |
1833 | ||
1834 | host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL); | |
1835 | if (!host) | |
1836 | return -ENOMEM; | |
1837 | ||
1838 | host->pdev = pdev; | |
1839 | host->pdata = pdata = pdev->dev.platform_data; | |
1840 | if (!pdata || !pdata->init) { | |
1841 | dev_err(&pdev->dev, | |
1842 | "Platform data must supply init function\n"); | |
1843 | ret = -ENODEV; | |
1844 | goto err_freehost; | |
1845 | } | |
1846 | ||
1847 | if (!pdata->select_slot && pdata->num_slots > 1) { | |
1848 | dev_err(&pdev->dev, | |
1849 | "Platform data must supply select_slot function\n"); | |
1850 | ret = -ENODEV; | |
1851 | goto err_freehost; | |
1852 | } | |
1853 | ||
1854 | if (!pdata->bus_hz) { | |
1855 | dev_err(&pdev->dev, | |
1856 | "Platform data must supply bus speed\n"); | |
1857 | ret = -ENODEV; | |
1858 | goto err_freehost; | |
1859 | } | |
1860 | ||
1861 | host->bus_hz = pdata->bus_hz; | |
1862 | host->quirks = pdata->quirks; | |
1863 | ||
1864 | spin_lock_init(&host->lock); | |
1865 | INIT_LIST_HEAD(&host->queue); | |
1866 | ||
1867 | ret = -ENOMEM; | |
28f65c11 | 1868 | host->regs = ioremap(regs->start, resource_size(regs)); |
f95f3850 WN |
1869 | if (!host->regs) |
1870 | goto err_freehost; | |
1871 | ||
1872 | host->dma_ops = pdata->dma_ops; | |
1873 | dw_mci_init_dma(host); | |
1874 | ||
1875 | /* | |
1876 | * Get the host data width - this assumes that HCON has been set with | |
1877 | * the correct values. | |
1878 | */ | |
1879 | i = (mci_readl(host, HCON) >> 7) & 0x7; | |
1880 | if (!i) { | |
1881 | host->push_data = dw_mci_push_data16; | |
1882 | host->pull_data = dw_mci_pull_data16; | |
1883 | width = 16; | |
1884 | host->data_shift = 1; | |
1885 | } else if (i == 2) { | |
1886 | host->push_data = dw_mci_push_data64; | |
1887 | host->pull_data = dw_mci_pull_data64; | |
1888 | width = 64; | |
1889 | host->data_shift = 3; | |
1890 | } else { | |
1891 | /* Check for a reserved value, and warn if it is */ | |
1892 | WARN((i != 1), | |
1893 | "HCON reports a reserved host data width!\n" | |
1894 | "Defaulting to 32-bit access.\n"); | |
1895 | host->push_data = dw_mci_push_data32; | |
1896 | host->pull_data = dw_mci_pull_data32; | |
1897 | width = 32; | |
1898 | host->data_shift = 2; | |
1899 | } | |
1900 | ||
1901 | /* Reset all blocks */ | |
1902 | if (!mci_wait_reset(&pdev->dev, host)) { | |
1903 | ret = -ENODEV; | |
1904 | goto err_dmaunmap; | |
1905 | } | |
1906 | ||
1907 | /* Clear the interrupts for the host controller */ | |
1908 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
1909 | mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ | |
1910 | ||
1911 | /* Put in max timeout */ | |
1912 | mci_writel(host, TMOUT, 0xFFFFFFFF); | |
1913 | ||
1914 | /* | |
1915 | * FIFO threshold settings RxMark = fifo_size / 2 - 1, | |
1916 | * Tx Mark = fifo_size / 2 DMA Size = 8 | |
1917 | */ | |
b86d8253 JH |
1918 | if (!host->pdata->fifo_depth) { |
1919 | /* | |
1920 | * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may | |
1921 | * have been overwritten by the bootloader, just like we're | |
1922 | * about to do, so if you know the value for your hardware, you | |
1923 | * should put it in the platform data. | |
1924 | */ | |
1925 | fifo_size = mci_readl(host, FIFOTH); | |
1926 | fifo_size = 1 + ((fifo_size >> 16) & 0x7ff); | |
1927 | } else { | |
1928 | fifo_size = host->pdata->fifo_depth; | |
1929 | } | |
1930 | host->fifo_depth = fifo_size; | |
e61cf118 JC |
1931 | host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) | |
1932 | ((fifo_size/2) << 0)); | |
1933 | mci_writel(host, FIFOTH, host->fifoth_val); | |
f95f3850 WN |
1934 | |
1935 | /* disable clock to CIU */ | |
1936 | mci_writel(host, CLKENA, 0); | |
1937 | mci_writel(host, CLKSRC, 0); | |
1938 | ||
1939 | tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host); | |
1791b13e JH |
1940 | dw_mci_card_workqueue = alloc_workqueue("dw-mci-card", |
1941 | WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1); | |
1942 | if (!dw_mci_card_workqueue) | |
1943 | goto err_dmaunmap; | |
1944 | INIT_WORK(&host->card_work, dw_mci_work_routine_card); | |
f95f3850 WN |
1945 | |
1946 | ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host); | |
1947 | if (ret) | |
1791b13e | 1948 | goto err_workqueue; |
f95f3850 WN |
1949 | |
1950 | platform_set_drvdata(pdev, host); | |
1951 | ||
1952 | if (host->pdata->num_slots) | |
1953 | host->num_slots = host->pdata->num_slots; | |
1954 | else | |
1955 | host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1; | |
1956 | ||
1957 | /* We need at least one slot to succeed */ | |
1958 | for (i = 0; i < host->num_slots; i++) { | |
1959 | ret = dw_mci_init_slot(host, i); | |
1960 | if (ret) { | |
1961 | ret = -ENODEV; | |
1962 | goto err_init_slot; | |
1963 | } | |
1964 | } | |
1965 | ||
4e0a5adf JC |
1966 | /* |
1967 | * In 2.40a spec, Data offset is changed. | |
1968 | * Need to check the version-id and set data-offset for DATA register. | |
1969 | */ | |
1970 | host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); | |
1971 | dev_info(&pdev->dev, "Version ID is %04x\n", host->verid); | |
1972 | ||
1973 | if (host->verid < DW_MMC_240A) | |
1974 | host->data_offset = DATA_OFFSET; | |
1975 | else | |
1976 | host->data_offset = DATA_240A_OFFSET; | |
1977 | ||
f95f3850 WN |
1978 | /* |
1979 | * Enable interrupts for command done, data over, data empty, card det, | |
1980 | * receive ready and error such as transmit, receive timeout, crc error | |
1981 | */ | |
1982 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
1983 | mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | | |
1984 | SDMMC_INT_TXDR | SDMMC_INT_RXDR | | |
1985 | DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); | |
1986 | mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */ | |
1987 | ||
1988 | dev_info(&pdev->dev, "DW MMC controller at irq %d, " | |
b86d8253 JH |
1989 | "%d bit host data width, " |
1990 | "%u deep fifo\n", | |
1991 | irq, width, fifo_size); | |
f95f3850 WN |
1992 | if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) |
1993 | dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n"); | |
1994 | ||
1995 | return 0; | |
1996 | ||
1997 | err_init_slot: | |
1998 | /* De-init any initialized slots */ | |
1999 | while (i > 0) { | |
2000 | if (host->slot[i]) | |
2001 | dw_mci_cleanup_slot(host->slot[i], i); | |
2002 | i--; | |
2003 | } | |
2004 | free_irq(irq, host); | |
2005 | ||
1791b13e JH |
2006 | err_workqueue: |
2007 | destroy_workqueue(dw_mci_card_workqueue); | |
2008 | ||
f95f3850 WN |
2009 | err_dmaunmap: |
2010 | if (host->use_dma && host->dma_ops->exit) | |
2011 | host->dma_ops->exit(host); | |
2012 | dma_free_coherent(&host->pdev->dev, PAGE_SIZE, | |
2013 | host->sg_cpu, host->sg_dma); | |
2014 | iounmap(host->regs); | |
2015 | ||
c07946a3 JC |
2016 | if (host->vmmc) { |
2017 | regulator_disable(host->vmmc); | |
2018 | regulator_put(host->vmmc); | |
2019 | } | |
2020 | ||
2021 | ||
f95f3850 WN |
2022 | err_freehost: |
2023 | kfree(host); | |
2024 | return ret; | |
2025 | } | |
2026 | ||
2027 | static int __exit dw_mci_remove(struct platform_device *pdev) | |
2028 | { | |
2029 | struct dw_mci *host = platform_get_drvdata(pdev); | |
2030 | int i; | |
2031 | ||
2032 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2033 | mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */ | |
2034 | ||
2035 | platform_set_drvdata(pdev, NULL); | |
2036 | ||
2037 | for (i = 0; i < host->num_slots; i++) { | |
2038 | dev_dbg(&pdev->dev, "remove slot %d\n", i); | |
2039 | if (host->slot[i]) | |
2040 | dw_mci_cleanup_slot(host->slot[i], i); | |
2041 | } | |
2042 | ||
2043 | /* disable clock to CIU */ | |
2044 | mci_writel(host, CLKENA, 0); | |
2045 | mci_writel(host, CLKSRC, 0); | |
2046 | ||
2047 | free_irq(platform_get_irq(pdev, 0), host); | |
1791b13e | 2048 | destroy_workqueue(dw_mci_card_workqueue); |
f95f3850 WN |
2049 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
2050 | ||
2051 | if (host->use_dma && host->dma_ops->exit) | |
2052 | host->dma_ops->exit(host); | |
2053 | ||
c07946a3 JC |
2054 | if (host->vmmc) { |
2055 | regulator_disable(host->vmmc); | |
2056 | regulator_put(host->vmmc); | |
2057 | } | |
2058 | ||
f95f3850 WN |
2059 | iounmap(host->regs); |
2060 | ||
2061 | kfree(host); | |
2062 | return 0; | |
2063 | } | |
2064 | ||
2065 | #ifdef CONFIG_PM | |
2066 | /* | |
2067 | * TODO: we should probably disable the clock to the card in the suspend path. | |
2068 | */ | |
2069 | static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg) | |
2070 | { | |
2071 | int i, ret; | |
2072 | struct dw_mci *host = platform_get_drvdata(pdev); | |
2073 | ||
2074 | for (i = 0; i < host->num_slots; i++) { | |
2075 | struct dw_mci_slot *slot = host->slot[i]; | |
2076 | if (!slot) | |
2077 | continue; | |
2078 | ret = mmc_suspend_host(slot->mmc); | |
2079 | if (ret < 0) { | |
2080 | while (--i >= 0) { | |
2081 | slot = host->slot[i]; | |
2082 | if (slot) | |
2083 | mmc_resume_host(host->slot[i]->mmc); | |
2084 | } | |
2085 | return ret; | |
2086 | } | |
2087 | } | |
2088 | ||
c07946a3 JC |
2089 | if (host->vmmc) |
2090 | regulator_disable(host->vmmc); | |
2091 | ||
f95f3850 WN |
2092 | return 0; |
2093 | } | |
2094 | ||
2095 | static int dw_mci_resume(struct platform_device *pdev) | |
2096 | { | |
2097 | int i, ret; | |
2098 | struct dw_mci *host = platform_get_drvdata(pdev); | |
2099 | ||
1d6c4e0a JC |
2100 | if (host->vmmc) |
2101 | regulator_enable(host->vmmc); | |
2102 | ||
e61cf118 JC |
2103 | if (host->dma_ops->init) |
2104 | host->dma_ops->init(host); | |
2105 | ||
2106 | if (!mci_wait_reset(&pdev->dev, host)) { | |
2107 | ret = -ENODEV; | |
2108 | return ret; | |
2109 | } | |
2110 | ||
2111 | /* Restore the old value at FIFOTH register */ | |
2112 | mci_writel(host, FIFOTH, host->fifoth_val); | |
2113 | ||
2114 | mci_writel(host, RINTSTS, 0xFFFFFFFF); | |
2115 | mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER | | |
2116 | SDMMC_INT_TXDR | SDMMC_INT_RXDR | | |
2117 | DW_MCI_ERROR_FLAGS | SDMMC_INT_CD); | |
2118 | mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); | |
2119 | ||
f95f3850 WN |
2120 | for (i = 0; i < host->num_slots; i++) { |
2121 | struct dw_mci_slot *slot = host->slot[i]; | |
2122 | if (!slot) | |
2123 | continue; | |
2124 | ret = mmc_resume_host(host->slot[i]->mmc); | |
2125 | if (ret < 0) | |
2126 | return ret; | |
2127 | } | |
2128 | ||
2129 | return 0; | |
2130 | } | |
2131 | #else | |
2132 | #define dw_mci_suspend NULL | |
2133 | #define dw_mci_resume NULL | |
2134 | #endif /* CONFIG_PM */ | |
2135 | ||
2136 | static struct platform_driver dw_mci_driver = { | |
2137 | .remove = __exit_p(dw_mci_remove), | |
2138 | .suspend = dw_mci_suspend, | |
2139 | .resume = dw_mci_resume, | |
2140 | .driver = { | |
2141 | .name = "dw_mmc", | |
2142 | }, | |
2143 | }; | |
2144 | ||
2145 | static int __init dw_mci_init(void) | |
2146 | { | |
2147 | return platform_driver_probe(&dw_mci_driver, dw_mci_probe); | |
2148 | } | |
2149 | ||
2150 | static void __exit dw_mci_exit(void) | |
2151 | { | |
2152 | platform_driver_unregister(&dw_mci_driver); | |
2153 | } | |
2154 | ||
2155 | module_init(dw_mci_init); | |
2156 | module_exit(dw_mci_exit); | |
2157 | ||
2158 | MODULE_DESCRIPTION("DW Multimedia Card Interface driver"); | |
2159 | MODULE_AUTHOR("NXP Semiconductor VietNam"); | |
2160 | MODULE_AUTHOR("Imagination Technologies Ltd"); | |
2161 | MODULE_LICENSE("GPL v2"); |