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mmc: dw_mmc: remove the prepare_command hook
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
b24c8b26 30#include <linux/mmc/card.h>
f95f3850
WN		 31#include <linux/mmc/host.h>
32#include <linux/mmc/mmc.h>
01730558 33#include <linux/mmc/sd.h>
90c2143a 34#include <linux/mmc/sdio.h>
f95f3850
WN		 35#include <linux/mmc/dw_mmc.h>
36#include <linux/bitops.h>
c07946a3 37#include <linux/regulator/consumer.h>
c91eab4b 38#include <linux/of.h>
55a6ceb2 39#include <linux/of_gpio.h>
bf626e55 40#include <linux/mmc/slot-gpio.h>
f95f3850
WN		 41
42#include "dw_mmc.h"
43
44/* Common flag combinations */
3f7eec62 45#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
f95f3850
WN		 46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52#define DW_MCI_SEND_STATUS 1
53#define DW_MCI_RECV_STATUS 2
54#define DW_MCI_DMA_THRESHOLD 16
55
1f44a2a5
SJ		 56#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
fc79a4d6
JS		 59#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
62 SDMMC_IDMAC_INT_TI)
63
69d99fdc
PT		 64struct idmac_desc_64addr {
65 u32 des0; /* Control Descriptor */
66
67 u32 des1; /* Reserved */
68
69 u32 des2; /*Buffer sizes */
70#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
6687c42f
BD		 71 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
72 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
69d99fdc
PT		 73
74 u32 des3; /* Reserved */
75
76 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
77 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
78
79 u32 des6; /* Lower 32-bits of Next Descriptor Address */
80 u32 des7; /* Upper 32-bits of Next Descriptor Address */
81};
82
f95f3850 83struct idmac_desc {
6687c42f 84 __le32 des0; /* Control Descriptor */
f95f3850
WN		 85#define IDMAC_DES0_DIC BIT(1)
86#define IDMAC_DES0_LD BIT(2)
87#define IDMAC_DES0_FD BIT(3)
88#define IDMAC_DES0_CH BIT(4)
89#define IDMAC_DES0_ER BIT(5)
90#define IDMAC_DES0_CES BIT(30)
91#define IDMAC_DES0_OWN BIT(31)
92
6687c42f 93 __le32 des1; /* Buffer sizes */
f95f3850 94#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 95 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850 96
6687c42f 97 __le32 des2; /* buffer 1 physical address */
f95f3850 98
6687c42f 99 __le32 des3; /* buffer 2 physical address */
f95f3850 100};
5959b32e
AB		 101
102/* Each descriptor can transfer up to 4KB of data in chained mode */
103#define DW_MCI_DESC_DATA_LENGTH 0x1000
f95f3850 104
3a33a94c 105static bool dw_mci_reset(struct dw_mci *host);
536f6b91 106static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
0bdbd0e8 107static int dw_mci_card_busy(struct mmc_host *mmc);
31bff450 108
f95f3850
WN		 109#if defined(CONFIG_DEBUG_FS)
110static int dw_mci_req_show(struct seq_file *s, void *v)
111{
112 struct dw_mci_slot *slot = s->private;
113 struct mmc_request *mrq;
114 struct mmc_command *cmd;
115 struct mmc_command *stop;
116 struct mmc_data *data;
117
118 /* Make sure we get a consistent snapshot */
119 spin_lock_bh(&slot->host->lock);
120 mrq = slot->mrq;
121
122 if (mrq) {
123 cmd = mrq->cmd;
124 data = mrq->data;
125 stop = mrq->stop;
126
127 if (cmd)
128 seq_printf(s,
129 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
130 cmd->opcode, cmd->arg, cmd->flags,
131 cmd->resp[0], cmd->resp[1], cmd->resp[2],
132 cmd->resp[2], cmd->error);
133 if (data)
134 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
135 data->bytes_xfered, data->blocks,
136 data->blksz, data->flags, data->error);
137 if (stop)
138 seq_printf(s,
139 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
140 stop->opcode, stop->arg, stop->flags,
141 stop->resp[0], stop->resp[1], stop->resp[2],
142 stop->resp[2], stop->error);
143 }
144
145 spin_unlock_bh(&slot->host->lock);
146
147 return 0;
148}
149
150static int dw_mci_req_open(struct inode *inode, struct file *file)
151{
152 return single_open(file, dw_mci_req_show, inode->i_private);
153}
154
155static const struct file_operations dw_mci_req_fops = {
156 .owner = THIS_MODULE,
157 .open = dw_mci_req_open,
158 .read = seq_read,
159 .llseek = seq_lseek,
160 .release = single_release,
161};
162
163static int dw_mci_regs_show(struct seq_file *s, void *v)
164{
165 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
166 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
167 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
168 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
169 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
170 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
171
172 return 0;
173}
174
175static int dw_mci_regs_open(struct inode *inode, struct file *file)
176{
177 return single_open(file, dw_mci_regs_show, inode->i_private);
178}
179
180static const struct file_operations dw_mci_regs_fops = {
181 .owner = THIS_MODULE,
182 .open = dw_mci_regs_open,
183 .read = seq_read,
184 .llseek = seq_lseek,
185 .release = single_release,
186};
187
188static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
189{
190 struct mmc_host *mmc = slot->mmc;
191 struct dw_mci *host = slot->host;
192 struct dentry *root;
193 struct dentry *node;
194
195 root = mmc->debugfs_root;
196 if (!root)
197 return;
198
199 node = debugfs_create_file("regs", S_IRUSR, root, host,
200 &dw_mci_regs_fops);
201 if (!node)
202 goto err;
203
204 node = debugfs_create_file("req", S_IRUSR, root, slot,
205 &dw_mci_req_fops);
206 if (!node)
207 goto err;
208
209 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
210 if (!node)
211 goto err;
212
213 node = debugfs_create_x32("pending_events", S_IRUSR, root,
214 (u32 *)&host->pending_events);
215 if (!node)
216 goto err;
217
218 node = debugfs_create_x32("completed_events", S_IRUSR, root,
219 (u32 *)&host->completed_events);
220 if (!node)
221 goto err;
222
223 return;
224
225err:
226 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
227}
228#endif /* defined(CONFIG_DEBUG_FS) */
229
01730558
DA		 230static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
231
f95f3850
WN		 232static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
233{
234 struct mmc_data *data;
800d78bf 235 struct dw_mci_slot *slot = mmc_priv(mmc);
01730558 236 struct dw_mci *host = slot->host;
f95f3850 237 u32 cmdr;
f95f3850 238
0e3a22c0 239 cmd->error = -EINPROGRESS;
f95f3850
WN		 240 cmdr = cmd->opcode;
241
90c2143a
SJ		 242 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
243 cmd->opcode == MMC_GO_IDLE_STATE ||
244 cmd->opcode == MMC_GO_INACTIVE_STATE ||
245 (cmd->opcode == SD_IO_RW_DIRECT &&
246 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
f95f3850 247 cmdr |= SDMMC_CMD_STOP;
4a1b27ad
JC		 248 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
249 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
f95f3850 250
01730558
DA		 251 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
252 u32 clk_en_a;
253
254 /* Special bit makes CMD11 not die */
255 cmdr |= SDMMC_CMD_VOLT_SWITCH;
256
257 /* Change state to continue to handle CMD11 weirdness */
258 WARN_ON(slot->host->state != STATE_SENDING_CMD);
259 slot->host->state = STATE_SENDING_CMD11;
260
261 /*
262 * We need to disable low power mode (automatic clock stop)
263 * while doing voltage switch so we don't confuse the card,
264 * since stopping the clock is a specific part of the UHS
265 * voltage change dance.
266 *
267 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
268 * unconditionally turned back on in dw_mci_setup_bus() if it's
269 * ever called with a non-zero clock. That shouldn't happen
270 * until the voltage change is all done.
271 */
272 clk_en_a = mci_readl(host, CLKENA);
273 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
274 mci_writel(host, CLKENA, clk_en_a);
275 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
276 SDMMC_CMD_PRV_DAT_WAIT, 0);
277 }
278
f95f3850
WN		 279 if (cmd->flags & MMC_RSP_PRESENT) {
280 /* We expect a response, so set this bit */
281 cmdr |= SDMMC_CMD_RESP_EXP;
282 if (cmd->flags & MMC_RSP_136)
283 cmdr |= SDMMC_CMD_RESP_LONG;
284 }
285
286 if (cmd->flags & MMC_RSP_CRC)
287 cmdr |= SDMMC_CMD_RESP_CRC;
288
289 data = cmd->data;
290 if (data) {
291 cmdr |= SDMMC_CMD_DAT_EXP;
f95f3850
WN		 292 if (data->flags & MMC_DATA_WRITE)
293 cmdr |= SDMMC_CMD_DAT_WR;
294 }
295
aaaaeb7a
JC		 296 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
297 cmdr |= SDMMC_CMD_USE_HOLD_REG;
800d78bf 298
f95f3850
WN		 299 return cmdr;
300}
301
90c2143a
SJ		 302static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
303{
304 struct mmc_command *stop;
305 u32 cmdr;
306
307 if (!cmd->data)
308 return 0;
309
310 stop = &host->stop_abort;
311 cmdr = cmd->opcode;
312 memset(stop, 0, sizeof(struct mmc_command));
313
314 if (cmdr == MMC_READ_SINGLE_BLOCK ||
315 cmdr == MMC_READ_MULTIPLE_BLOCK ||
316 cmdr == MMC_WRITE_BLOCK ||
6c2c6506
UH		 317 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
318 cmdr == MMC_SEND_TUNING_BLOCK ||
319 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
90c2143a
SJ		 320 stop->opcode = MMC_STOP_TRANSMISSION;
321 stop->arg = 0;
322 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
323 } else if (cmdr == SD_IO_RW_EXTENDED) {
324 stop->opcode = SD_IO_RW_DIRECT;
325 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
326 ((cmd->arg >> 28) & 0x7);
327 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
328 } else {
329 return 0;
330 }
331
332 cmdr = stop->opcode | SDMMC_CMD_STOP |
333 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
334
335 return cmdr;
336}
337
0bdbd0e8
DA		 338static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
339{
340 unsigned long timeout = jiffies + msecs_to_jiffies(500);
341
342 /*
343 * Databook says that before issuing a new data transfer command
344 * we need to check to see if the card is busy. Data transfer commands
345 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
346 *
347 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
348 * expected.
349 */
350 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
351 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
352 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
353 if (time_after(jiffies, timeout)) {
354 /* Command will fail; we'll pass error then */
355 dev_err(host->dev, "Busy; trying anyway\n");
356 break;
357 }
358 udelay(10);
359 }
360 }
361}
362
f95f3850
WN		 363static void dw_mci_start_command(struct dw_mci *host,
364 struct mmc_command *cmd, u32 cmd_flags)
365{
366 host->cmd = cmd;
4a90920c 367 dev_vdbg(host->dev,
f95f3850
WN		 368 "start command: ARGR=0x%08x CMDR=0x%08x\n",
369 cmd->arg, cmd_flags);
370
371 mci_writel(host, CMDARG, cmd->arg);
0e3a22c0 372 wmb(); /* drain writebuffer */
0bdbd0e8 373 dw_mci_wait_while_busy(host, cmd_flags);
f95f3850
WN		 374
375 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
376}
377
90c2143a 378static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
f95f3850 379{
90c2143a 380 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
0e3a22c0 381
90c2143a 382 dw_mci_start_command(host, stop, host->stop_cmdr);
f95f3850
WN		 383}
384
385/* DMA interface functions */
386static void dw_mci_stop_dma(struct dw_mci *host)
387{
03e8cb53 388 if (host->using_dma) {
f95f3850
WN		 389 host->dma_ops->stop(host);
390 host->dma_ops->cleanup(host);
f95f3850 391 }
aa50f259
SJ		 392
393 /* Data transfer was stopped by the interrupt handler */
394 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
f95f3850
WN		 395}
396
9aa51408
SJ		 397static int dw_mci_get_dma_dir(struct mmc_data *data)
398{
399 if (data->flags & MMC_DATA_WRITE)
400 return DMA_TO_DEVICE;
401 else
402 return DMA_FROM_DEVICE;
403}
404
f95f3850
WN		 405static void dw_mci_dma_cleanup(struct dw_mci *host)
406{
407 struct mmc_data *data = host->data;
408
409 if (data)
9aa51408 410 if (!data->host_cookie)
4a90920c 411 dma_unmap_sg(host->dev,
9aa51408
SJ		 412 data->sg,
413 data->sg_len,
414 dw_mci_get_dma_dir(data));
f95f3850
WN		 415}
416
5ce9d961
SJ		 417static void dw_mci_idmac_reset(struct dw_mci *host)
418{
419 u32 bmod = mci_readl(host, BMOD);
420 /* Software reset of DMA */
421 bmod |= SDMMC_IDMAC_SWRESET;
422 mci_writel(host, BMOD, bmod);
423}
424
f95f3850
WN		 425static void dw_mci_idmac_stop_dma(struct dw_mci *host)
426{
427 u32 temp;
428
429 /* Disable and reset the IDMAC interface */
430 temp = mci_readl(host, CTRL);
431 temp &= ~SDMMC_CTRL_USE_IDMAC;
432 temp |= SDMMC_CTRL_DMA_RESET;
433 mci_writel(host, CTRL, temp);
434
435 /* Stop the IDMAC running */
436 temp = mci_readl(host, BMOD);
a5289a43 437 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
5ce9d961 438 temp |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 439 mci_writel(host, BMOD, temp);
440}
441
3fc7eaef 442static void dw_mci_dmac_complete_dma(void *arg)
f95f3850 443{
3fc7eaef 444 struct dw_mci *host = arg;
f95f3850
WN		 445 struct mmc_data *data = host->data;
446
4a90920c 447 dev_vdbg(host->dev, "DMA complete\n");
f95f3850 448
3fc7eaef
SL		 449 if ((host->use_dma == TRANS_MODE_EDMAC) &&
450 data && (data->flags & MMC_DATA_READ))
451 /* Invalidate cache after read */
452 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
453 data->sg,
454 data->sg_len,
455 DMA_FROM_DEVICE);
456
f95f3850
WN		 457 host->dma_ops->cleanup(host);
458
459 /*
460 * If the card was removed, data will be NULL. No point in trying to
461 * send the stop command or waiting for NBUSY in this case.
462 */
463 if (data) {
464 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
465 tasklet_schedule(&host->tasklet);
466 }
467}
468
469static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
470 unsigned int sg_len)
471{
5959b32e 472 unsigned int desc_len;
f95f3850 473 int i;
0e3a22c0 474
69d99fdc 475 if (host->dma_64bit_address == 1) {
5959b32e
AB		 476 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
477
478 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 479
5959b32e 480 for (i = 0; i < sg_len; i++) {
69d99fdc 481 unsigned int length = sg_dma_len(&data->sg[i]);
0e3a22c0 482
69d99fdc 483 u64 mem_addr = sg_dma_address(&data->sg[i]);
f95f3850 484
5959b32e
AB		 485 for ( ; length ; desc++) {
486 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
487 length : DW_MCI_DESC_DATA_LENGTH;
488
489 length -= desc_len;
490
491 /*
492 * Set the OWN bit and disable interrupts
493 * for this descriptor
494 */
495 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
496 IDMAC_DES0_CH;
497
498 /* Buffer length */
499 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
500
501 /* Physical address to DMA to/from */
502 desc->des4 = mem_addr & 0xffffffff;
503 desc->des5 = mem_addr >> 32;
504
505 /* Update physical address for the next desc */
506 mem_addr += desc_len;
507
508 /* Save pointer to the last descriptor */
509 desc_last = desc;
510 }
69d99fdc 511 }
f95f3850 512
69d99fdc 513 /* Set first descriptor */
5959b32e 514 desc_first->des0 |= IDMAC_DES0_FD;
f95f3850 515
69d99fdc 516 /* Set last descriptor */
5959b32e
AB		 517 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
518 desc_last->des0 |= IDMAC_DES0_LD;
f95f3850 519
69d99fdc 520 } else {
5959b32e
AB		 521 struct idmac_desc *desc_first, *desc_last, *desc;
522
523 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 524
5959b32e 525 for (i = 0; i < sg_len; i++) {
69d99fdc 526 unsigned int length = sg_dma_len(&data->sg[i]);
0e3a22c0 527
69d99fdc
PT		 528 u32 mem_addr = sg_dma_address(&data->sg[i]);
529
5959b32e
AB		 530 for ( ; length ; desc++) {
531 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
532 length : DW_MCI_DESC_DATA_LENGTH;
533
534 length -= desc_len;
535
536 /*
537 * Set the OWN bit and disable interrupts
538 * for this descriptor
539 */
540 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
541 IDMAC_DES0_DIC |
542 IDMAC_DES0_CH);
543
544 /* Buffer length */
545 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
f95f3850 546
5959b32e
AB		 547 /* Physical address to DMA to/from */
548 desc->des2 = cpu_to_le32(mem_addr);
549
550 /* Update physical address for the next desc */
551 mem_addr += desc_len;
552
553 /* Save pointer to the last descriptor */
554 desc_last = desc;
555 }
69d99fdc
PT		 556 }
557
558 /* Set first descriptor */
5959b32e 559 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
f95f3850 560
69d99fdc 561 /* Set last descriptor */
5959b32e
AB		 562 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
563 IDMAC_DES0_DIC));
564 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
69d99fdc 565 }
f95f3850 566
0e3a22c0 567 wmb(); /* drain writebuffer */
f95f3850
WN		 568}
569
3fc7eaef 570static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
f95f3850
WN		 571{
572 u32 temp;
573
574 dw_mci_translate_sglist(host, host->data, sg_len);
575
536f6b91
SR		 576 /* Make sure to reset DMA in case we did PIO before this */
577 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
578 dw_mci_idmac_reset(host);
579
f95f3850
WN		 580 /* Select IDMAC interface */
581 temp = mci_readl(host, CTRL);
582 temp |= SDMMC_CTRL_USE_IDMAC;
583 mci_writel(host, CTRL, temp);
584
0e3a22c0 585 /* drain writebuffer */
f95f3850
WN		 586 wmb();
587
588 /* Enable the IDMAC */
589 temp = mci_readl(host, BMOD);
a5289a43 590 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 591 mci_writel(host, BMOD, temp);
592
593 /* Start it running */
594 mci_writel(host, PLDMND, 1);
3fc7eaef
SL		 595
596 return 0;
f95f3850
WN		 597}
598
599static int dw_mci_idmac_init(struct dw_mci *host)
600{
897b69e7 601 int i;
f95f3850 602
69d99fdc
PT		 603 if (host->dma_64bit_address == 1) {
604 struct idmac_desc_64addr *p;
605 /* Number of descriptors in the ring buffer */
606 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
607
608 /* Forward link the descriptor list */
609 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
610 i++, p++) {
611 p->des6 = (host->sg_dma +
612 (sizeof(struct idmac_desc_64addr) *
613 (i + 1))) & 0xffffffff;
614
615 p->des7 = (u64)(host->sg_dma +
616 (sizeof(struct idmac_desc_64addr) *
617 (i + 1))) >> 32;
618 /* Initialize reserved and buffer size fields to "0" */
619 p->des1 = 0;
620 p->des2 = 0;
621 p->des3 = 0;
622 }
f95f3850 623
69d99fdc
PT		 624 /* Set the last descriptor as the end-of-ring descriptor */
625 p->des6 = host->sg_dma & 0xffffffff;
626 p->des7 = (u64)host->sg_dma >> 32;
627 p->des0 = IDMAC_DES0_ER;
f95f3850 628
69d99fdc
PT		 629 } else {
630 struct idmac_desc *p;
631 /* Number of descriptors in the ring buffer */
632 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
633
634 /* Forward link the descriptor list */
0e3a22c0
SL		 635 for (i = 0, p = host->sg_cpu;
636 i < host->ring_size - 1;
637 i++, p++) {
6687c42f
BD		 638 p->des3 = cpu_to_le32(host->sg_dma +
639 (sizeof(struct idmac_desc) * (i + 1)));
4b244724
ZG		 640 p->des1 = 0;
641 }
69d99fdc
PT		 642
643 /* Set the last descriptor as the end-of-ring descriptor */
6687c42f
BD		 644 p->des3 = cpu_to_le32(host->sg_dma);
645 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
69d99fdc 646 }
f95f3850 647
5ce9d961 648 dw_mci_idmac_reset(host);
141a712a 649
69d99fdc
PT		 650 if (host->dma_64bit_address == 1) {
651 /* Mask out interrupts - get Tx & Rx complete only */
652 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
653 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
654 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
655
656 /* Set the descriptor base address */
657 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
658 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
659
660 } else {
661 /* Mask out interrupts - get Tx & Rx complete only */
662 mci_writel(host, IDSTS, IDMAC_INT_CLR);
663 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
664 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
665
666 /* Set the descriptor base address */
667 mci_writel(host, DBADDR, host->sg_dma);
668 }
f95f3850 669
f95f3850
WN		 670 return 0;
671}
672
8e2b36ea 673static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 674 .init = dw_mci_idmac_init,
675 .start = dw_mci_idmac_start_dma,
676 .stop = dw_mci_idmac_stop_dma,
3fc7eaef
SL		 677 .complete = dw_mci_dmac_complete_dma,
678 .cleanup = dw_mci_dma_cleanup,
679};
680
681static void dw_mci_edmac_stop_dma(struct dw_mci *host)
682{
683 dmaengine_terminate_all(host->dms->ch);
684}
685
686static int dw_mci_edmac_start_dma(struct dw_mci *host,
687 unsigned int sg_len)
688{
689 struct dma_slave_config cfg;
690 struct dma_async_tx_descriptor *desc = NULL;
691 struct scatterlist *sgl = host->data->sg;
692 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
693 u32 sg_elems = host->data->sg_len;
694 u32 fifoth_val;
695 u32 fifo_offset = host->fifo_reg - host->regs;
696 int ret = 0;
697
698 /* Set external dma config: burst size, burst width */
260b3164 699 cfg.dst_addr = host->phy_regs + fifo_offset;
3fc7eaef
SL		 700 cfg.src_addr = cfg.dst_addr;
701 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
702 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
703
704 /* Match burst msize with external dma config */
705 fifoth_val = mci_readl(host, FIFOTH);
706 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
707 cfg.src_maxburst = cfg.dst_maxburst;
708
709 if (host->data->flags & MMC_DATA_WRITE)
710 cfg.direction = DMA_MEM_TO_DEV;
711 else
712 cfg.direction = DMA_DEV_TO_MEM;
713
714 ret = dmaengine_slave_config(host->dms->ch, &cfg);
715 if (ret) {
716 dev_err(host->dev, "Failed to config edmac.\n");
717 return -EBUSY;
718 }
719
720 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
721 sg_len, cfg.direction,
722 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
723 if (!desc) {
724 dev_err(host->dev, "Can't prepare slave sg.\n");
725 return -EBUSY;
726 }
727
728 /* Set dw_mci_dmac_complete_dma as callback */
729 desc->callback = dw_mci_dmac_complete_dma;
730 desc->callback_param = (void *)host;
731 dmaengine_submit(desc);
732
733 /* Flush cache before write */
734 if (host->data->flags & MMC_DATA_WRITE)
735 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
736 sg_elems, DMA_TO_DEVICE);
737
738 dma_async_issue_pending(host->dms->ch);
739
740 return 0;
741}
742
743static int dw_mci_edmac_init(struct dw_mci *host)
744{
745 /* Request external dma channel */
746 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
747 if (!host->dms)
748 return -ENOMEM;
749
750 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
751 if (!host->dms->ch) {
4539d36e 752 dev_err(host->dev, "Failed to get external DMA channel.\n");
3fc7eaef
SL		 753 kfree(host->dms);
754 host->dms = NULL;
755 return -ENXIO;
756 }
757
758 return 0;
759}
760
761static void dw_mci_edmac_exit(struct dw_mci *host)
762{
763 if (host->dms) {
764 if (host->dms->ch) {
765 dma_release_channel(host->dms->ch);
766 host->dms->ch = NULL;
767 }
768 kfree(host->dms);
769 host->dms = NULL;
770 }
771}
772
773static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
774 .init = dw_mci_edmac_init,
775 .exit = dw_mci_edmac_exit,
776 .start = dw_mci_edmac_start_dma,
777 .stop = dw_mci_edmac_stop_dma,
778 .complete = dw_mci_dmac_complete_dma,
885c3e80
SJ		 779 .cleanup = dw_mci_dma_cleanup,
780};
885c3e80 781
9aa51408
SJ		 782static int dw_mci_pre_dma_transfer(struct dw_mci *host,
783 struct mmc_data *data,
784 bool next)
f95f3850
WN		 785{
786 struct scatterlist *sg;
9aa51408 787 unsigned int i, sg_len;
03e8cb53 788
9aa51408
SJ		 789 if (!next && data->host_cookie)
790 return data->host_cookie;
f95f3850
WN		 791
792 /*
793 * We don't do DMA on "complex" transfers, i.e. with
794 * non-word-aligned buffers or lengths. Also, we don't bother
795 * with all the DMA setup overhead for short transfers.
796 */
797 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
798 return -EINVAL;
9aa51408 799
f95f3850
WN		 800 if (data->blksz & 3)
801 return -EINVAL;
802
803 for_each_sg(data->sg, sg, data->sg_len, i) {
804 if (sg->offset & 3 || sg->length & 3)
805 return -EINVAL;
806 }
807
4a90920c 808 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 809 data->sg,
810 data->sg_len,
811 dw_mci_get_dma_dir(data));
812 if (sg_len == 0)
813 return -EINVAL;
03e8cb53 814
9aa51408
SJ		 815 if (next)
816 data->host_cookie = sg_len;
f95f3850 817
9aa51408
SJ		 818 return sg_len;
819}
820
9aa51408
SJ		 821static void dw_mci_pre_req(struct mmc_host *mmc,
822 struct mmc_request *mrq,
823 bool is_first_req)
824{
825 struct dw_mci_slot *slot = mmc_priv(mmc);
826 struct mmc_data *data = mrq->data;
827
828 if (!slot->host->use_dma || !data)
829 return;
830
831 if (data->host_cookie) {
832 data->host_cookie = 0;
833 return;
834 }
835
836 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
837 data->host_cookie = 0;
838}
839
840static void dw_mci_post_req(struct mmc_host *mmc,
841 struct mmc_request *mrq,
842 int err)
843{
844 struct dw_mci_slot *slot = mmc_priv(mmc);
845 struct mmc_data *data = mrq->data;
846
847 if (!slot->host->use_dma || !data)
848 return;
849
850 if (data->host_cookie)
4a90920c 851 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 852 data->sg,
853 data->sg_len,
854 dw_mci_get_dma_dir(data));
855 data->host_cookie = 0;
856}
857
52426899
SJ		 858static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
859{
52426899
SJ		 860 unsigned int blksz = data->blksz;
861 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
862 u32 fifo_width = 1 << host->data_shift;
863 u32 blksz_depth = blksz / fifo_width, fifoth_val;
864 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
0e3a22c0 865 int idx = ARRAY_SIZE(mszs) - 1;
52426899 866
3fc7eaef
SL		 867 /* pio should ship this scenario */
868 if (!host->use_dma)
869 return;
870
52426899
SJ		 871 tx_wmark = (host->fifo_depth) / 2;
872 tx_wmark_invers = host->fifo_depth - tx_wmark;
873
874 /*
875 * MSIZE is '1',
876 * if blksz is not a multiple of the FIFO width
877 */
878 if (blksz % fifo_width) {
879 msize = 0;
880 rx_wmark = 1;
881 goto done;
882 }
883
884 do {
885 if (!((blksz_depth % mszs[idx]) ||
886 (tx_wmark_invers % mszs[idx]))) {
887 msize = idx;
888 rx_wmark = mszs[idx] - 1;
889 break;
890 }
891 } while (--idx > 0);
892 /*
893 * If idx is '0', it won't be tried
894 * Thus, initial values are uesed
895 */
896done:
897 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
898 mci_writel(host, FIFOTH, fifoth_val);
52426899
SJ		 899}
900
f1d2736c
SJ		 901static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
902{
903 unsigned int blksz = data->blksz;
904 u32 blksz_depth, fifo_depth;
905 u16 thld_size;
906
907 WARN_ON(!(data->flags & MMC_DATA_READ));
908
66dfd101
JH		 909 /*
910 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
911 * in the FIFO region, so we really shouldn't access it).
912 */
913 if (host->verid < DW_MMC_240A)
914 return;
915
f1d2736c 916 if (host->timing != MMC_TIMING_MMC_HS200 &&
488b8d63 917 host->timing != MMC_TIMING_MMC_HS400 &&
f1d2736c
SJ		 918 host->timing != MMC_TIMING_UHS_SDR104)
919 goto disable;
920
921 blksz_depth = blksz / (1 << host->data_shift);
922 fifo_depth = host->fifo_depth;
923
924 if (blksz_depth > fifo_depth)
925 goto disable;
926
927 /*
928 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
929 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
930 * Currently just choose blksz.
931 */
932 thld_size = blksz;
933 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
934 return;
935
936disable:
937 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
938}
939
9aa51408
SJ		 940static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
941{
f8c58c11 942 unsigned long irqflags;
9aa51408
SJ		 943 int sg_len;
944 u32 temp;
945
946 host->using_dma = 0;
947
948 /* If we don't have a channel, we can't do DMA */
949 if (!host->use_dma)
950 return -ENODEV;
951
952 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 953 if (sg_len < 0) {
954 host->dma_ops->stop(host);
9aa51408 955 return sg_len;
a99aa9b9 956 }
9aa51408
SJ		 957
958 host->using_dma = 1;
f95f3850 959
3fc7eaef
SL		 960 if (host->use_dma == TRANS_MODE_IDMAC)
961 dev_vdbg(host->dev,
962 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
963 (unsigned long)host->sg_cpu,
964 (unsigned long)host->sg_dma,
965 sg_len);
f95f3850 966
52426899
SJ		 967 /*
968 * Decide the MSIZE and RX/TX Watermark.
969 * If current block size is same with previous size,
970 * no need to update fifoth.
971 */
972 if (host->prev_blksz != data->blksz)
973 dw_mci_adjust_fifoth(host, data);
974
f95f3850
WN		 975 /* Enable the DMA interface */
976 temp = mci_readl(host, CTRL);
977 temp |= SDMMC_CTRL_DMA_ENABLE;
978 mci_writel(host, CTRL, temp);
979
980 /* Disable RX/TX IRQs, let DMA handle it */
f8c58c11 981 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 982 temp = mci_readl(host, INTMASK);
983 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
984 mci_writel(host, INTMASK, temp);
f8c58c11 985 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850 986
3fc7eaef
SL		 987 if (host->dma_ops->start(host, sg_len)) {
988 /* We can't do DMA */
989 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
990 return -ENODEV;
991 }
f95f3850
WN		 992
993 return 0;
994}
995
996static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
997{
f8c58c11 998 unsigned long irqflags;
0e3a22c0 999 int flags = SG_MITER_ATOMIC;
f95f3850
WN		 1000 u32 temp;
1001
1002 data->error = -EINPROGRESS;
1003
1004 WARN_ON(host->data);
1005 host->sg = NULL;
1006 host->data = data;
1007
f1d2736c 1008 if (data->flags & MMC_DATA_READ) {
55c5efbc 1009 host->dir_status = DW_MCI_RECV_STATUS;
f1d2736c
SJ		 1010 dw_mci_ctrl_rd_thld(host, data);
1011 } else {
55c5efbc 1012 host->dir_status = DW_MCI_SEND_STATUS;
f1d2736c 1013 }
55c5efbc 1014
f95f3850 1015 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 1016 if (host->data->flags & MMC_DATA_READ)
1017 flags |= SG_MITER_TO_SG;
1018 else
1019 flags |= SG_MITER_FROM_SG;
1020
1021 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 1022 host->sg = data->sg;
34b664a2
JH		 1023 host->part_buf_start = 0;
1024 host->part_buf_count = 0;
f95f3850 1025
b40af3aa 1026 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f8c58c11
DA		 1027
1028 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1029 temp = mci_readl(host, INTMASK);
1030 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1031 mci_writel(host, INTMASK, temp);
f8c58c11 1032 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 1033
1034 temp = mci_readl(host, CTRL);
1035 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1036 mci_writel(host, CTRL, temp);
52426899
SJ		 1037
1038 /*
1039 * Use the initial fifoth_val for PIO mode.
1040 * If next issued data may be transfered by DMA mode,
1041 * prev_blksz should be invalidated.
1042 */
1043 mci_writel(host, FIFOTH, host->fifoth_val);
1044 host->prev_blksz = 0;
1045 } else {
1046 /*
1047 * Keep the current block size.
1048 * It will be used to decide whether to update
1049 * fifoth register next time.
1050 */
1051 host->prev_blksz = data->blksz;
f95f3850
WN		 1052 }
1053}
1054
1055static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1056{
1057 struct dw_mci *host = slot->host;
1058 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1059 unsigned int cmd_status = 0;
1060
1061 mci_writel(host, CMDARG, arg);
0e3a22c0 1062 wmb(); /* drain writebuffer */
0bdbd0e8 1063 dw_mci_wait_while_busy(host, cmd);
f95f3850
WN		 1064 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1065
1066 while (time_before(jiffies, timeout)) {
1067 cmd_status = mci_readl(host, CMD);
1068 if (!(cmd_status & SDMMC_CMD_START))
1069 return;
1070 }
1071 dev_err(&slot->mmc->class_dev,
1072 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1073 cmd, arg, cmd_status);
1074}
1075
ab269128 1076static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 1077{
1078 struct dw_mci *host = slot->host;
fdf492a1 1079 unsigned int clock = slot->clock;
f95f3850 1080 u32 div;
9623b5b9 1081 u32 clk_en_a;
01730558
DA		 1082 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1083
1084 /* We must continue to set bit 28 in CMD until the change is complete */
1085 if (host->state == STATE_WAITING_CMD11_DONE)
1086 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
f95f3850 1087
fdf492a1
DA		 1088 if (!clock) {
1089 mci_writel(host, CLKENA, 0);
01730558 1090 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
fdf492a1
DA		 1091 } else if (clock != host->current_speed || force_clkinit) {
1092 div = host->bus_hz / clock;
1093 if (host->bus_hz % clock && host->bus_hz > clock)
f95f3850
WN		 1094 /*
1095 * move the + 1 after the divide to prevent
1096 * over-clocking the card.
1097 */
e419990b
SJ		 1098 div += 1;
1099
fdf492a1 1100 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850 1101
fdf492a1
DA		 1102 if ((clock << div) != slot->__clk_old || force_clkinit)
1103 dev_info(&slot->mmc->class_dev,
1104 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1105 slot->id, host->bus_hz, clock,
1106 div ? ((host->bus_hz / div) >> 1) :
1107 host->bus_hz, div);
f95f3850
WN		 1108
1109 /* disable clock */
1110 mci_writel(host, CLKENA, 0);
1111 mci_writel(host, CLKSRC, 0);
1112
1113 /* inform CIU */
01730558 1114 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850
WN		 1115
1116 /* set clock to desired speed */
1117 mci_writel(host, CLKDIV, div);
1118
1119 /* inform CIU */
01730558 1120 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1121
9623b5b9
DA		 1122 /* enable clock; only low power if no SDIO */
1123 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
b24c8b26 1124 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
9623b5b9
DA		 1125 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1126 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 1127
1128 /* inform CIU */
01730558 1129 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1130
fdf492a1
DA		 1131 /* keep the clock with reflecting clock dividor */
1132 slot->__clk_old = clock << div;
f95f3850
WN		 1133 }
1134
fdf492a1
DA		 1135 host->current_speed = clock;
1136
f95f3850 1137 /* Set the current slot bus width */
1d56c453 1138 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 1139}
1140
053b3ce6
SJ		 1141static void __dw_mci_start_request(struct dw_mci *host,
1142 struct dw_mci_slot *slot,
1143 struct mmc_command *cmd)
f95f3850
WN		 1144{
1145 struct mmc_request *mrq;
f95f3850
WN		 1146 struct mmc_data *data;
1147 u32 cmdflags;
1148
1149 mrq = slot->mrq;
f95f3850 1150
f95f3850
WN		 1151 host->cur_slot = slot;
1152 host->mrq = mrq;
1153
1154 host->pending_events = 0;
1155 host->completed_events = 0;
e352c813 1156 host->cmd_status = 0;
f95f3850 1157 host->data_status = 0;
e352c813 1158 host->dir_status = 0;
f95f3850 1159
053b3ce6 1160 data = cmd->data;
f95f3850 1161 if (data) {
f16afa88 1162 mci_writel(host, TMOUT, 0xFFFFFFFF);
f95f3850
WN		 1163 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1164 mci_writel(host, BLKSIZ, data->blksz);
1165 }
1166
f95f3850
WN		 1167 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1168
1169 /* this is the first command, send the initialization clock */
1170 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1171 cmdflags |= SDMMC_CMD_INIT;
1172
1173 if (data) {
1174 dw_mci_submit_data(host, data);
0e3a22c0 1175 wmb(); /* drain writebuffer */
f95f3850
WN		 1176 }
1177
1178 dw_mci_start_command(host, cmd, cmdflags);
1179
5c935165 1180 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
49ba0302
DA		 1181 unsigned long irqflags;
1182
5c935165 1183 /*
8886a6fd
DA		 1184 * Databook says to fail after 2ms w/ no response, but evidence
1185 * shows that sometimes the cmd11 interrupt takes over 130ms.
1186 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1187 * is just about to roll over.
49ba0302
DA		 1188 *
1189 * We do this whole thing under spinlock and only if the
1190 * command hasn't already completed (indicating the the irq
1191 * already ran so we don't want the timeout).
5c935165 1192 */
49ba0302
DA		 1193 spin_lock_irqsave(&host->irq_lock, irqflags);
1194 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1195 mod_timer(&host->cmd11_timer,
1196 jiffies + msecs_to_jiffies(500) + 1);
1197 spin_unlock_irqrestore(&host->irq_lock, irqflags);
5c935165
DA		 1198 }
1199
f95f3850
WN		 1200 if (mrq->stop)
1201 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
90c2143a
SJ		 1202 else
1203 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
f95f3850
WN		 1204}
1205
053b3ce6
SJ		 1206static void dw_mci_start_request(struct dw_mci *host,
1207 struct dw_mci_slot *slot)
1208{
1209 struct mmc_request *mrq = slot->mrq;
1210 struct mmc_command *cmd;
1211
1212 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1213 __dw_mci_start_request(host, slot, cmd);
1214}
1215
7456caae 1216/* must be called with host->lock held */
f95f3850
WN		 1217static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1218 struct mmc_request *mrq)
1219{
1220 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1221 host->state);
1222
f95f3850
WN		 1223 slot->mrq = mrq;
1224
01730558
DA		 1225 if (host->state == STATE_WAITING_CMD11_DONE) {
1226 dev_warn(&slot->mmc->class_dev,
1227 "Voltage change didn't complete\n");
1228 /*
1229 * this case isn't expected to happen, so we can
1230 * either crash here or just try to continue on
1231 * in the closest possible state
1232 */
1233 host->state = STATE_IDLE;
1234 }
1235
f95f3850
WN		 1236 if (host->state == STATE_IDLE) {
1237 host->state = STATE_SENDING_CMD;
1238 dw_mci_start_request(host, slot);
1239 } else {
1240 list_add_tail(&slot->queue_node, &host->queue);
1241 }
f95f3850
WN		 1242}
1243
1244static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1245{
1246 struct dw_mci_slot *slot = mmc_priv(mmc);
1247 struct dw_mci *host = slot->host;
1248
1249 WARN_ON(slot->mrq);
1250
7456caae
JH		 1251 /*
1252 * The check for card presence and queueing of the request must be
1253 * atomic, otherwise the card could be removed in between and the
1254 * request wouldn't fail until another card was inserted.
1255 */
1256 spin_lock_bh(&host->lock);
1257
f95f3850 1258 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 1259 spin_unlock_bh(&host->lock);
f95f3850
WN		 1260 mrq->cmd->error = -ENOMEDIUM;
1261 mmc_request_done(mmc, mrq);
1262 return;
1263 }
1264
f95f3850 1265 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 1266
1267 spin_unlock_bh(&host->lock);
f95f3850
WN		 1268}
1269
1270static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1271{
1272 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 1273 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 1274 u32 regs;
51da2240 1275 int ret;
f95f3850 1276
f95f3850 1277 switch (ios->bus_width) {
f95f3850
WN		 1278 case MMC_BUS_WIDTH_4:
1279 slot->ctype = SDMMC_CTYPE_4BIT;
1280 break;
c9b2a06f
JC		 1281 case MMC_BUS_WIDTH_8:
1282 slot->ctype = SDMMC_CTYPE_8BIT;
1283 break;
b2f7cb45
JC		 1284 default:
1285 /* set default 1 bit mode */
1286 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 1287 }
1288
3f514291
SJ		 1289 regs = mci_readl(slot->host, UHS_REG);
1290
41babf75 1291 /* DDR mode set */
80113132 1292 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
7cc8d580 1293 ios->timing == MMC_TIMING_UHS_DDR50 ||
80113132 1294 ios->timing == MMC_TIMING_MMC_HS400)
c69042a5 1295 regs |= ((0x1 << slot->id) << 16);
3f514291 1296 else
c69042a5 1297 regs &= ~((0x1 << slot->id) << 16);
3f514291
SJ		 1298
1299 mci_writel(slot->host, UHS_REG, regs);
f1d2736c 1300 slot->host->timing = ios->timing;
41babf75 1301
fdf492a1
DA		 1302 /*
1303 * Use mirror of ios->clock to prevent race with mmc
1304 * core ios update when finding the minimum.
1305 */
1306 slot->clock = ios->clock;
f95f3850 1307
cb27a843
JH		 1308 if (drv_data && drv_data->set_ios)
1309 drv_data->set_ios(slot->host, ios);
800d78bf 1310
f95f3850
WN		 1311 switch (ios->power_mode) {
1312 case MMC_POWER_UP:
51da2240
YC		 1313 if (!IS_ERR(mmc->supply.vmmc)) {
1314 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1315 ios->vdd);
1316 if (ret) {
1317 dev_err(slot->host->dev,
1318 "failed to enable vmmc regulator\n");
1319 /*return, if failed turn on vmmc*/
1320 return;
1321 }
1322 }
29d0d161
DA		 1323 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1324 regs = mci_readl(slot->host, PWREN);
1325 regs |= (1 << slot->id);
1326 mci_writel(slot->host, PWREN, regs);
1327 break;
1328 case MMC_POWER_ON:
d1f1dd86
DA		 1329 if (!slot->host->vqmmc_enabled) {
1330 if (!IS_ERR(mmc->supply.vqmmc)) {
1331 ret = regulator_enable(mmc->supply.vqmmc);
1332 if (ret < 0)
1333 dev_err(slot->host->dev,
1334 "failed to enable vqmmc\n");
1335 else
1336 slot->host->vqmmc_enabled = true;
1337
1338 } else {
1339 /* Keep track so we don't reset again */
51da2240 1340 slot->host->vqmmc_enabled = true;
d1f1dd86
DA		 1341 }
1342
1343 /* Reset our state machine after powering on */
1344 dw_mci_ctrl_reset(slot->host,
1345 SDMMC_CTRL_ALL_RESET_FLAGS);
51da2240 1346 }
655babbd
DA		 1347
1348 /* Adjust clock / bus width after power is up */
1349 dw_mci_setup_bus(slot, false);
1350
e6f34e2f
JH		 1351 break;
1352 case MMC_POWER_OFF:
655babbd
DA		 1353 /* Turn clock off before power goes down */
1354 dw_mci_setup_bus(slot, false);
1355
51da2240
YC		 1356 if (!IS_ERR(mmc->supply.vmmc))
1357 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1358
d1f1dd86 1359 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
51da2240 1360 regulator_disable(mmc->supply.vqmmc);
d1f1dd86 1361 slot->host->vqmmc_enabled = false;
51da2240 1362
4366dcc5
JC		 1363 regs = mci_readl(slot->host, PWREN);
1364 regs &= ~(1 << slot->id);
1365 mci_writel(slot->host, PWREN, regs);
f95f3850
WN		 1366 break;
1367 default:
1368 break;
1369 }
655babbd
DA		 1370
1371 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1372 slot->host->state = STATE_IDLE;
f95f3850
WN		 1373}
1374
01730558
DA		 1375static int dw_mci_card_busy(struct mmc_host *mmc)
1376{
1377 struct dw_mci_slot *slot = mmc_priv(mmc);
1378 u32 status;
1379
1380 /*
1381 * Check the busy bit which is low when DAT[3:0]
1382 * (the data lines) are 0000
1383 */
1384 status = mci_readl(slot->host, STATUS);
1385
1386 return !!(status & SDMMC_STATUS_BUSY);
1387}
1388
1389static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1390{
1391 struct dw_mci_slot *slot = mmc_priv(mmc);
1392 struct dw_mci *host = slot->host;
8f7849c4 1393 const struct dw_mci_drv_data *drv_data = host->drv_data;
01730558
DA		 1394 u32 uhs;
1395 u32 v18 = SDMMC_UHS_18V << slot->id;
01730558
DA		 1396 int ret;
1397
8f7849c4
ZG		 1398 if (drv_data && drv_data->switch_voltage)
1399 return drv_data->switch_voltage(mmc, ios);
1400
01730558
DA		 1401 /*
1402 * Program the voltage. Note that some instances of dw_mmc may use
1403 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1404 * does no harm but you need to set the regulator directly. Try both.
1405 */
1406 uhs = mci_readl(host, UHS_REG);
e0848f5d 1407 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
01730558 1408 uhs &= ~v18;
e0848f5d 1409 else
01730558 1410 uhs |= v18;
e0848f5d 1411
01730558 1412 if (!IS_ERR(mmc->supply.vqmmc)) {
e0848f5d 1413 ret = mmc_regulator_set_vqmmc(mmc, ios);
01730558
DA		 1414
1415 if (ret) {
b19caf37 1416 dev_dbg(&mmc->class_dev,
e0848f5d
DA		 1417 "Regulator set error %d - %s V\n",
1418 ret, uhs & v18 ? "1.8" : "3.3");
01730558
DA		 1419 return ret;
1420 }
1421 }
1422 mci_writel(host, UHS_REG, uhs);
1423
1424 return 0;
1425}
1426
f95f3850
WN		 1427static int dw_mci_get_ro(struct mmc_host *mmc)
1428{
1429 int read_only;
1430 struct dw_mci_slot *slot = mmc_priv(mmc);
9795a846 1431 int gpio_ro = mmc_gpio_get_ro(mmc);
f95f3850
WN		 1432
1433 /* Use platform get_ro function, else try on board write protect */
eff8f2f5 1434 if (!IS_ERR_VALUE(gpio_ro))
9795a846 1435 read_only = gpio_ro;
f95f3850
WN		 1436 else
1437 read_only =
1438 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1439
1440 dev_dbg(&mmc->class_dev, "card is %s\n",
1441 read_only ? "read-only" : "read-write");
1442
1443 return read_only;
1444}
1445
1446static int dw_mci_get_cd(struct mmc_host *mmc)
1447{
1448 int present;
1449 struct dw_mci_slot *slot = mmc_priv(mmc);
1450 struct dw_mci_board *brd = slot->host->pdata;
7cf347bd
ZG		 1451 struct dw_mci *host = slot->host;
1452 int gpio_cd = mmc_gpio_get_cd(mmc);
f95f3850
WN		 1453
1454 /* Use platform get_cd function, else try onboard card detect */
4de3bf66
ZG		 1455 if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1456 (mmc->caps & MMC_CAP_NONREMOVABLE))
fc3d7720 1457 present = 1;
bf626e55 1458 else if (!IS_ERR_VALUE(gpio_cd))
7cf347bd 1459 present = gpio_cd;
f95f3850
WN		 1460 else
1461 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1462 == 0 ? 1 : 0;
1463
7cf347bd 1464 spin_lock_bh(&host->lock);
bf626e55
ZG		 1465 if (present) {
1466 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1467 dev_dbg(&mmc->class_dev, "card is present\n");
bf626e55
ZG		 1468 } else {
1469 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1470 dev_dbg(&mmc->class_dev, "card is not present\n");
bf626e55 1471 }
7cf347bd 1472 spin_unlock_bh(&host->lock);
f95f3850
WN		 1473
1474 return present;
1475}
1476
b24c8b26 1477static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
9623b5b9 1478{
b24c8b26 1479 struct dw_mci_slot *slot = mmc_priv(mmc);
9623b5b9 1480 struct dw_mci *host = slot->host;
9623b5b9 1481
b24c8b26
DA		 1482 /*
1483 * Low power mode will stop the card clock when idle. According to the
1484 * description of the CLKENA register we should disable low power mode
1485 * for SDIO cards if we need SDIO interrupts to work.
1486 */
1487 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1488 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1489 u32 clk_en_a_old;
1490 u32 clk_en_a;
9623b5b9 1491
b24c8b26
DA		 1492 clk_en_a_old = mci_readl(host, CLKENA);
1493
1494 if (card->type == MMC_TYPE_SDIO ||
1495 card->type == MMC_TYPE_SD_COMBO) {
1496 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1497 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1498 } else {
1499 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1500 clk_en_a = clk_en_a_old | clken_low_pwr;
1501 }
1502
1503 if (clk_en_a != clk_en_a_old) {
1504 mci_writel(host, CLKENA, clk_en_a);
1505 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1506 SDMMC_CMD_PRV_DAT_WAIT, 0);
1507 }
9623b5b9
DA		 1508 }
1509}
1510
1a5c8e1f
SH		 1511static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1512{
1513 struct dw_mci_slot *slot = mmc_priv(mmc);
1514 struct dw_mci *host = slot->host;
f8c58c11 1515 unsigned long irqflags;
1a5c8e1f
SH		 1516 u32 int_mask;
1517
f8c58c11
DA		 1518 spin_lock_irqsave(&host->irq_lock, irqflags);
1519
1a5c8e1f
SH		 1520 /* Enable/disable Slot Specific SDIO interrupt */
1521 int_mask = mci_readl(host, INTMASK);
b24c8b26
DA		 1522 if (enb)
1523 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1524 else
1525 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1526 mci_writel(host, INTMASK, int_mask);
f8c58c11
DA		 1527
1528 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1a5c8e1f
SH		 1529}
1530
0976f16d
SJ		 1531static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1532{
1533 struct dw_mci_slot *slot = mmc_priv(mmc);
1534 struct dw_mci *host = slot->host;
1535 const struct dw_mci_drv_data *drv_data = host->drv_data;
0e3a22c0 1536 int err = -EINVAL;
0976f16d 1537
0976f16d 1538 if (drv_data && drv_data->execute_tuning)
9979dbe5 1539 err = drv_data->execute_tuning(slot, opcode);
0976f16d
SJ		 1540 return err;
1541}
1542
0e3a22c0
SL		 1543static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1544 struct mmc_ios *ios)
80113132
SJ		 1545{
1546 struct dw_mci_slot *slot = mmc_priv(mmc);
1547 struct dw_mci *host = slot->host;
1548 const struct dw_mci_drv_data *drv_data = host->drv_data;
1549
1550 if (drv_data && drv_data->prepare_hs400_tuning)
1551 return drv_data->prepare_hs400_tuning(host, ios);
1552
1553 return 0;
1554}
1555
f95f3850 1556static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 1557 .request = dw_mci_request,
9aa51408
SJ		 1558 .pre_req = dw_mci_pre_req,
1559 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 1560 .set_ios = dw_mci_set_ios,
1561 .get_ro = dw_mci_get_ro,
1562 .get_cd = dw_mci_get_cd,
1563 .enable_sdio_irq = dw_mci_enable_sdio_irq,
0976f16d 1564 .execute_tuning = dw_mci_execute_tuning,
01730558
DA		 1565 .card_busy = dw_mci_card_busy,
1566 .start_signal_voltage_switch = dw_mci_switch_voltage,
b24c8b26 1567 .init_card = dw_mci_init_card,
80113132 1568 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
f95f3850
WN		 1569};
1570
1571static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1572 __releases(&host->lock)
1573 __acquires(&host->lock)
1574{
1575 struct dw_mci_slot *slot;
1576 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1577
1578 WARN_ON(host->cmd || host->data);
1579
1580 host->cur_slot->mrq = NULL;
1581 host->mrq = NULL;
1582 if (!list_empty(&host->queue)) {
1583 slot = list_entry(host->queue.next,
1584 struct dw_mci_slot, queue_node);
1585 list_del(&slot->queue_node);
4a90920c 1586 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 1587 mmc_hostname(slot->mmc));
1588 host->state = STATE_SENDING_CMD;
1589 dw_mci_start_request(host, slot);
1590 } else {
4a90920c 1591 dev_vdbg(host->dev, "list empty\n");
01730558
DA		 1592
1593 if (host->state == STATE_SENDING_CMD11)
1594 host->state = STATE_WAITING_CMD11_DONE;
1595 else
1596 host->state = STATE_IDLE;
f95f3850
WN		 1597 }
1598
1599 spin_unlock(&host->lock);
1600 mmc_request_done(prev_mmc, mrq);
1601 spin_lock(&host->lock);
1602}
1603
e352c813 1604static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
f95f3850
WN		 1605{
1606 u32 status = host->cmd_status;
1607
1608 host->cmd_status = 0;
1609
1610 /* Read the response from the card (up to 16 bytes) */
1611 if (cmd->flags & MMC_RSP_PRESENT) {
1612 if (cmd->flags & MMC_RSP_136) {
1613 cmd->resp[3] = mci_readl(host, RESP0);
1614 cmd->resp[2] = mci_readl(host, RESP1);
1615 cmd->resp[1] = mci_readl(host, RESP2);
1616 cmd->resp[0] = mci_readl(host, RESP3);
1617 } else {
1618 cmd->resp[0] = mci_readl(host, RESP0);
1619 cmd->resp[1] = 0;
1620 cmd->resp[2] = 0;
1621 cmd->resp[3] = 0;
1622 }
1623 }
1624
1625 if (status & SDMMC_INT_RTO)
1626 cmd->error = -ETIMEDOUT;
1627 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1628 cmd->error = -EILSEQ;
1629 else if (status & SDMMC_INT_RESP_ERR)
1630 cmd->error = -EIO;
1631 else
1632 cmd->error = 0;
1633
e352c813
SJ		 1634 return cmd->error;
1635}
1636
1637static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1638{
31bff450 1639 u32 status = host->data_status;
e352c813
SJ		 1640
1641 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1642 if (status & SDMMC_INT_DRTO) {
1643 data->error = -ETIMEDOUT;
1644 } else if (status & SDMMC_INT_DCRC) {
1645 data->error = -EILSEQ;
1646 } else if (status & SDMMC_INT_EBE) {
1647 if (host->dir_status ==
1648 DW_MCI_SEND_STATUS) {
1649 /*
1650 * No data CRC status was returned.
1651 * The number of bytes transferred
1652 * will be exaggerated in PIO mode.
1653 */
1654 data->bytes_xfered = 0;
1655 data->error = -ETIMEDOUT;
1656 } else if (host->dir_status ==
1657 DW_MCI_RECV_STATUS) {
1658 data->error = -EIO;
1659 }
1660 } else {
1661 /* SDMMC_INT_SBE is included */
1662 data->error = -EIO;
1663 }
1664
e6cc0123 1665 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
e352c813
SJ		 1666
1667 /*
1668 * After an error, there may be data lingering
31bff450 1669 * in the FIFO
e352c813 1670 */
3a33a94c 1671 dw_mci_reset(host);
e352c813
SJ		 1672 } else {
1673 data->bytes_xfered = data->blocks * data->blksz;
1674 data->error = 0;
1675 }
1676
1677 return data->error;
f95f3850
WN		 1678}
1679
57e10486
AK		 1680static void dw_mci_set_drto(struct dw_mci *host)
1681{
1682 unsigned int drto_clks;
1683 unsigned int drto_ms;
1684
1685 drto_clks = mci_readl(host, TMOUT) >> 8;
1686 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1687
1688 /* add a bit spare time */
1689 drto_ms += 10;
1690
1691 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1692}
1693
f95f3850
WN		 1694static void dw_mci_tasklet_func(unsigned long priv)
1695{
1696 struct dw_mci *host = (struct dw_mci *)priv;
1697 struct mmc_data *data;
1698 struct mmc_command *cmd;
e352c813 1699 struct mmc_request *mrq;
f95f3850
WN		 1700 enum dw_mci_state state;
1701 enum dw_mci_state prev_state;
e352c813 1702 unsigned int err;
f95f3850
WN		 1703
1704 spin_lock(&host->lock);
1705
1706 state = host->state;
1707 data = host->data;
e352c813 1708 mrq = host->mrq;
f95f3850
WN		 1709
1710 do {
1711 prev_state = state;
1712
1713 switch (state) {
1714 case STATE_IDLE:
01730558 1715 case STATE_WAITING_CMD11_DONE:
f95f3850
WN		 1716 break;
1717
01730558 1718 case STATE_SENDING_CMD11:
f95f3850
WN		 1719 case STATE_SENDING_CMD:
1720 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1721 &host->pending_events))
1722 break;
1723
1724 cmd = host->cmd;
1725 host->cmd = NULL;
1726 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
e352c813
SJ		 1727 err = dw_mci_command_complete(host, cmd);
1728 if (cmd == mrq->sbc && !err) {
053b3ce6
SJ		 1729 prev_state = state = STATE_SENDING_CMD;
1730 __dw_mci_start_request(host, host->cur_slot,
e352c813 1731 mrq->cmd);
053b3ce6
SJ		 1732 goto unlock;
1733 }
1734
e352c813 1735 if (cmd->data && err) {
71abb133 1736 dw_mci_stop_dma(host);
90c2143a
SJ		 1737 send_stop_abort(host, data);
1738 state = STATE_SENDING_STOP;
1739 break;
71abb133
SJ		 1740 }
1741
e352c813
SJ		 1742 if (!cmd->data || err) {
1743 dw_mci_request_end(host, mrq);
f95f3850
WN		 1744 goto unlock;
1745 }
1746
1747 prev_state = state = STATE_SENDING_DATA;
1748 /* fall through */
1749
1750 case STATE_SENDING_DATA:
2aa35465
DA		 1751 /*
1752 * We could get a data error and never a transfer
1753 * complete so we'd better check for it here.
1754 *
1755 * Note that we don't really care if we also got a
1756 * transfer complete; stopping the DMA and sending an
1757 * abort won't hurt.
1758 */
f95f3850
WN		 1759 if (test_and_clear_bit(EVENT_DATA_ERROR,
1760 &host->pending_events)) {
1761 dw_mci_stop_dma(host);
bdb9a90b 1762 if (data->stop ||
1763 !(host->data_status & (SDMMC_INT_DRTO |
1764 SDMMC_INT_EBE)))
1765 send_stop_abort(host, data);
f95f3850
WN		 1766 state = STATE_DATA_ERROR;
1767 break;
1768 }
1769
1770 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
57e10486
AK		 1771 &host->pending_events)) {
1772 /*
1773 * If all data-related interrupts don't come
1774 * within the given time in reading data state.
1775 */
1776 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1777 (host->dir_status == DW_MCI_RECV_STATUS))
1778 dw_mci_set_drto(host);
f95f3850 1779 break;
57e10486 1780 }
f95f3850
WN		 1781
1782 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2aa35465
DA		 1783
1784 /*
1785 * Handle an EVENT_DATA_ERROR that might have shown up
1786 * before the transfer completed. This might not have
1787 * been caught by the check above because the interrupt
1788 * could have gone off between the previous check and
1789 * the check for transfer complete.
1790 *
1791 * Technically this ought not be needed assuming we
1792 * get a DATA_COMPLETE eventually (we'll notice the
1793 * error and end the request), but it shouldn't hurt.
1794 *
1795 * This has the advantage of sending the stop command.
1796 */
1797 if (test_and_clear_bit(EVENT_DATA_ERROR,
1798 &host->pending_events)) {
1799 dw_mci_stop_dma(host);
bdb9a90b 1800 if (data->stop ||
1801 !(host->data_status & (SDMMC_INT_DRTO |
1802 SDMMC_INT_EBE)))
1803 send_stop_abort(host, data);
2aa35465
DA		 1804 state = STATE_DATA_ERROR;
1805 break;
1806 }
f95f3850 1807 prev_state = state = STATE_DATA_BUSY;
2aa35465 1808
f95f3850
WN		 1809 /* fall through */
1810
1811 case STATE_DATA_BUSY:
1812 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
57e10486
AK		 1813 &host->pending_events)) {
1814 /*
1815 * If data error interrupt comes but data over
1816 * interrupt doesn't come within the given time.
1817 * in reading data state.
1818 */
1819 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1820 (host->dir_status == DW_MCI_RECV_STATUS))
1821 dw_mci_set_drto(host);
f95f3850 1822 break;
57e10486 1823 }
f95f3850
WN		 1824
1825 host->data = NULL;
1826 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
e352c813
SJ		 1827 err = dw_mci_data_complete(host, data);
1828
1829 if (!err) {
1830 if (!data->stop || mrq->sbc) {
17c8bc85 1831 if (mrq->sbc && data->stop)
e352c813
SJ		 1832 data->stop->error = 0;
1833 dw_mci_request_end(host, mrq);
1834 goto unlock;
f95f3850 1835 }
f95f3850 1836
e352c813
SJ		 1837 /* stop command for open-ended transfer*/
1838 if (data->stop)
1839 send_stop_abort(host, data);
2aa35465
DA		 1840 } else {
1841 /*
1842 * If we don't have a command complete now we'll
1843 * never get one since we just reset everything;
1844 * better end the request.
1845 *
1846 * If we do have a command complete we'll fall
1847 * through to the SENDING_STOP command and
1848 * everything will be peachy keen.
1849 */
1850 if (!test_bit(EVENT_CMD_COMPLETE,
1851 &host->pending_events)) {
1852 host->cmd = NULL;
1853 dw_mci_request_end(host, mrq);
1854 goto unlock;
1855 }
053b3ce6
SJ		 1856 }
1857
e352c813
SJ		 1858 /*
1859 * If err has non-zero,
1860 * stop-abort command has been already issued.
1861 */
f95f3850 1862 prev_state = state = STATE_SENDING_STOP;
e352c813 1863
f95f3850
WN		 1864 /* fall through */
1865
1866 case STATE_SENDING_STOP:
1867 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1868 &host->pending_events))
1869 break;
1870
71abb133 1871 /* CMD error in data command */
31bff450 1872 if (mrq->cmd->error && mrq->data)
3a33a94c 1873 dw_mci_reset(host);
71abb133 1874
f95f3850 1875 host->cmd = NULL;
71abb133 1876 host->data = NULL;
90c2143a 1877
e352c813
SJ		 1878 if (mrq->stop)
1879 dw_mci_command_complete(host, mrq->stop);
90c2143a
SJ		 1880 else
1881 host->cmd_status = 0;
1882
e352c813 1883 dw_mci_request_end(host, mrq);
f95f3850
WN		 1884 goto unlock;
1885
1886 case STATE_DATA_ERROR:
1887 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1888 &host->pending_events))
1889 break;
1890
1891 state = STATE_DATA_BUSY;
1892 break;
1893 }
1894 } while (state != prev_state);
1895
1896 host->state = state;
1897unlock:
1898 spin_unlock(&host->lock);
1899
1900}
1901
34b664a2
JH		 1902/* push final bytes to part_buf, only use during push */
1903static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1904{
34b664a2
JH		 1905 memcpy((void *)&host->part_buf, buf, cnt);
1906 host->part_buf_count = cnt;
1907}
f95f3850 1908
34b664a2
JH		 1909/* append bytes to part_buf, only use during push */
1910static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1911{
1912 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1913 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1914 host->part_buf_count += cnt;
1915 return cnt;
1916}
f95f3850 1917
34b664a2
JH		 1918/* pull first bytes from part_buf, only use during pull */
1919static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1920{
0e3a22c0 1921 cnt = min_t(int, cnt, host->part_buf_count);
34b664a2
JH		 1922 if (cnt) {
1923 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1924 cnt);
1925 host->part_buf_count -= cnt;
1926 host->part_buf_start += cnt;
f95f3850 1927 }
34b664a2 1928 return cnt;
f95f3850
WN		 1929}
1930
34b664a2
JH		 1931/* pull final bytes from the part_buf, assuming it's just been filled */
1932static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1933{
34b664a2
JH		 1934 memcpy(buf, &host->part_buf, cnt);
1935 host->part_buf_start = cnt;
1936 host->part_buf_count = (1 << host->data_shift) - cnt;
1937}
f95f3850 1938
34b664a2
JH		 1939static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1940{
cfbeb59c
MC		 1941 struct mmc_data *data = host->data;
1942 int init_cnt = cnt;
1943
34b664a2
JH		 1944 /* try and push anything in the part_buf */
1945 if (unlikely(host->part_buf_count)) {
1946 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 1947
34b664a2
JH		 1948 buf += len;
1949 cnt -= len;
cfbeb59c 1950 if (host->part_buf_count == 2) {
76184ac1 1951 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 1952 host->part_buf_count = 0;
1953 }
1954 }
1955#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1956 if (unlikely((unsigned long)buf & 0x1)) {
1957 while (cnt >= 2) {
1958 u16 aligned_buf[64];
1959 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1960 int items = len >> 1;
1961 int i;
1962 /* memcpy from input buffer into aligned buffer */
1963 memcpy(aligned_buf, buf, len);
1964 buf += len;
1965 cnt -= len;
1966 /* push data from aligned buffer into fifo */
1967 for (i = 0; i < items; ++i)
76184ac1 1968 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 1969 }
1970 } else
1971#endif
1972 {
1973 u16 *pdata = buf;
0e3a22c0 1974
34b664a2 1975 for (; cnt >= 2; cnt -= 2)
76184ac1 1976 mci_fifo_writew(host->fifo_reg, *pdata++);
34b664a2
JH		 1977 buf = pdata;
1978 }
1979 /* put anything remaining in the part_buf */
1980 if (cnt) {
1981 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 1982 /* Push data if we have reached the expected data length */
1983 if ((data->bytes_xfered + init_cnt) ==
1984 (data->blksz * data->blocks))
76184ac1 1985 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 1986 }
1987}
f95f3850 1988
34b664a2
JH		 1989static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1990{
1991#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1992 if (unlikely((unsigned long)buf & 0x1)) {
1993 while (cnt >= 2) {
1994 /* pull data from fifo into aligned buffer */
1995 u16 aligned_buf[64];
1996 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1997 int items = len >> 1;
1998 int i;
0e3a22c0 1999
34b664a2 2000 for (i = 0; i < items; ++i)
76184ac1 2001 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2002 /* memcpy from aligned buffer into output buffer */
2003 memcpy(buf, aligned_buf, len);
2004 buf += len;
2005 cnt -= len;
2006 }
2007 } else
2008#endif
2009 {
2010 u16 *pdata = buf;
0e3a22c0 2011
34b664a2 2012 for (; cnt >= 2; cnt -= 2)
76184ac1 2013 *pdata++ = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2014 buf = pdata;
2015 }
2016 if (cnt) {
76184ac1 2017 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
34b664a2 2018 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2019 }
2020}
2021
2022static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2023{
cfbeb59c
MC		 2024 struct mmc_data *data = host->data;
2025 int init_cnt = cnt;
2026
34b664a2
JH		 2027 /* try and push anything in the part_buf */
2028 if (unlikely(host->part_buf_count)) {
2029 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2030
34b664a2
JH		 2031 buf += len;
2032 cnt -= len;
cfbeb59c 2033 if (host->part_buf_count == 4) {
76184ac1 2034 mci_fifo_writel(host->fifo_reg, host->part_buf32);
34b664a2
JH		 2035 host->part_buf_count = 0;
2036 }
2037 }
2038#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2039 if (unlikely((unsigned long)buf & 0x3)) {
2040 while (cnt >= 4) {
2041 u32 aligned_buf[32];
2042 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2043 int items = len >> 2;
2044 int i;
2045 /* memcpy from input buffer into aligned buffer */
2046 memcpy(aligned_buf, buf, len);
2047 buf += len;
2048 cnt -= len;
2049 /* push data from aligned buffer into fifo */
2050 for (i = 0; i < items; ++i)
76184ac1 2051 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2052 }
2053 } else
2054#endif
2055 {
2056 u32 *pdata = buf;
0e3a22c0 2057
34b664a2 2058 for (; cnt >= 4; cnt -= 4)
76184ac1 2059 mci_fifo_writel(host->fifo_reg, *pdata++);
34b664a2
JH		 2060 buf = pdata;
2061 }
2062 /* put anything remaining in the part_buf */
2063 if (cnt) {
2064 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2065 /* Push data if we have reached the expected data length */
2066 if ((data->bytes_xfered + init_cnt) ==
2067 (data->blksz * data->blocks))
76184ac1 2068 mci_fifo_writel(host->fifo_reg, host->part_buf32);
f95f3850
WN		 2069 }
2070}
2071
2072static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2073{
34b664a2
JH		 2074#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2075 if (unlikely((unsigned long)buf & 0x3)) {
2076 while (cnt >= 4) {
2077 /* pull data from fifo into aligned buffer */
2078 u32 aligned_buf[32];
2079 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2080 int items = len >> 2;
2081 int i;
0e3a22c0 2082
34b664a2 2083 for (i = 0; i < items; ++i)
76184ac1 2084 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2085 /* memcpy from aligned buffer into output buffer */
2086 memcpy(buf, aligned_buf, len);
2087 buf += len;
2088 cnt -= len;
2089 }
2090 } else
2091#endif
2092 {
2093 u32 *pdata = buf;
0e3a22c0 2094
34b664a2 2095 for (; cnt >= 4; cnt -= 4)
76184ac1 2096 *pdata++ = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2097 buf = pdata;
2098 }
2099 if (cnt) {
76184ac1 2100 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
34b664a2 2101 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2102 }
2103}
2104
2105static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2106{
cfbeb59c
MC		 2107 struct mmc_data *data = host->data;
2108 int init_cnt = cnt;
2109
34b664a2
JH		 2110 /* try and push anything in the part_buf */
2111 if (unlikely(host->part_buf_count)) {
2112 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2113
34b664a2
JH		 2114 buf += len;
2115 cnt -= len;
c09fbd74 2116
cfbeb59c 2117 if (host->part_buf_count == 8) {
76184ac1 2118 mci_fifo_writeq(host->fifo_reg, host->part_buf);
34b664a2
JH		 2119 host->part_buf_count = 0;
2120 }
2121 }
2122#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2123 if (unlikely((unsigned long)buf & 0x7)) {
2124 while (cnt >= 8) {
2125 u64 aligned_buf[16];
2126 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2127 int items = len >> 3;
2128 int i;
2129 /* memcpy from input buffer into aligned buffer */
2130 memcpy(aligned_buf, buf, len);
2131 buf += len;
2132 cnt -= len;
2133 /* push data from aligned buffer into fifo */
2134 for (i = 0; i < items; ++i)
76184ac1 2135 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2136 }
2137 } else
2138#endif
2139 {
2140 u64 *pdata = buf;
0e3a22c0 2141
34b664a2 2142 for (; cnt >= 8; cnt -= 8)
76184ac1 2143 mci_fifo_writeq(host->fifo_reg, *pdata++);
34b664a2
JH		 2144 buf = pdata;
2145 }
2146 /* put anything remaining in the part_buf */
2147 if (cnt) {
2148 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2149 /* Push data if we have reached the expected data length */
2150 if ((data->bytes_xfered + init_cnt) ==
2151 (data->blksz * data->blocks))
76184ac1 2152 mci_fifo_writeq(host->fifo_reg, host->part_buf);
f95f3850
WN		 2153 }
2154}
2155
2156static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2157{
34b664a2
JH		 2158#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2159 if (unlikely((unsigned long)buf & 0x7)) {
2160 while (cnt >= 8) {
2161 /* pull data from fifo into aligned buffer */
2162 u64 aligned_buf[16];
2163 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2164 int items = len >> 3;
2165 int i;
0e3a22c0 2166
34b664a2 2167 for (i = 0; i < items; ++i)
76184ac1
BD		 2168 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2169
34b664a2
JH		 2170 /* memcpy from aligned buffer into output buffer */
2171 memcpy(buf, aligned_buf, len);
2172 buf += len;
2173 cnt -= len;
2174 }
2175 } else
2176#endif
2177 {
2178 u64 *pdata = buf;
0e3a22c0 2179
34b664a2 2180 for (; cnt >= 8; cnt -= 8)
76184ac1 2181 *pdata++ = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2182 buf = pdata;
2183 }
2184 if (cnt) {
76184ac1 2185 host->part_buf = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2186 dw_mci_pull_final_bytes(host, buf, cnt);
2187 }
2188}
f95f3850 2189
34b664a2
JH		 2190static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2191{
2192 int len;
f95f3850 2193
34b664a2
JH		 2194 /* get remaining partial bytes */
2195 len = dw_mci_pull_part_bytes(host, buf, cnt);
2196 if (unlikely(len == cnt))
2197 return;
2198 buf += len;
2199 cnt -= len;
2200
2201 /* get the rest of the data */
2202 host->pull_data(host, buf, cnt);
f95f3850
WN		 2203}
2204
87a74d39 2205static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
f95f3850 2206{
f9c2a0dc
SJ		 2207 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2208 void *buf;
2209 unsigned int offset;
f95f3850
WN		 2210 struct mmc_data *data = host->data;
2211 int shift = host->data_shift;
2212 u32 status;
3e4b0d8b 2213 unsigned int len;
f9c2a0dc 2214 unsigned int remain, fcnt;
f95f3850
WN		 2215
2216 do {
f9c2a0dc
SJ		 2217 if (!sg_miter_next(sg_miter))
2218 goto done;
2219
4225fc85 2220 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2221 buf = sg_miter->addr;
2222 remain = sg_miter->length;
2223 offset = 0;
2224
2225 do {
2226 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2227 << shift) + host->part_buf_count;
2228 len = min(remain, fcnt);
2229 if (!len)
2230 break;
34b664a2 2231 dw_mci_pull_data(host, (void *)(buf + offset), len);
3e4b0d8b 2232 data->bytes_xfered += len;
f95f3850 2233 offset += len;
f9c2a0dc
SJ		 2234 remain -= len;
2235 } while (remain);
f95f3850 2236
e74f3a9c 2237 sg_miter->consumed = offset;
f95f3850
WN		 2238 status = mci_readl(host, MINTSTS);
2239 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
87a74d39
KK		 2240 /* if the RXDR is ready read again */
2241 } while ((status & SDMMC_INT_RXDR) ||
2242 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
f9c2a0dc
SJ		 2243
2244 if (!remain) {
2245 if (!sg_miter_next(sg_miter))
2246 goto done;
2247 sg_miter->consumed = 0;
2248 }
2249 sg_miter_stop(sg_miter);
f95f3850
WN		 2250 return;
2251
2252done:
f9c2a0dc
SJ		 2253 sg_miter_stop(sg_miter);
2254 host->sg = NULL;
0e3a22c0 2255 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2256 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2257}
2258
2259static void dw_mci_write_data_pio(struct dw_mci *host)
2260{
f9c2a0dc
SJ		 2261 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2262 void *buf;
2263 unsigned int offset;
f95f3850
WN		 2264 struct mmc_data *data = host->data;
2265 int shift = host->data_shift;
2266 u32 status;
3e4b0d8b 2267 unsigned int len;
f9c2a0dc
SJ		 2268 unsigned int fifo_depth = host->fifo_depth;
2269 unsigned int remain, fcnt;
f95f3850
WN		 2270
2271 do {
f9c2a0dc
SJ		 2272 if (!sg_miter_next(sg_miter))
2273 goto done;
2274
4225fc85 2275 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2276 buf = sg_miter->addr;
2277 remain = sg_miter->length;
2278 offset = 0;
2279
2280 do {
2281 fcnt = ((fifo_depth -
2282 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2283 << shift) - host->part_buf_count;
2284 len = min(remain, fcnt);
2285 if (!len)
2286 break;
f95f3850 2287 host->push_data(host, (void *)(buf + offset), len);
3e4b0d8b 2288 data->bytes_xfered += len;
f95f3850 2289 offset += len;
f9c2a0dc
SJ		 2290 remain -= len;
2291 } while (remain);
f95f3850 2292
e74f3a9c 2293 sg_miter->consumed = offset;
f95f3850
WN		 2294 status = mci_readl(host, MINTSTS);
2295 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 2296 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f9c2a0dc
SJ		 2297
2298 if (!remain) {
2299 if (!sg_miter_next(sg_miter))
2300 goto done;
2301 sg_miter->consumed = 0;
2302 }
2303 sg_miter_stop(sg_miter);
f95f3850
WN		 2304 return;
2305
2306done:
f9c2a0dc
SJ		 2307 sg_miter_stop(sg_miter);
2308 host->sg = NULL;
0e3a22c0 2309 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2310 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2311}
2312
2313static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2314{
2315 if (!host->cmd_status)
2316 host->cmd_status = status;
2317
0e3a22c0 2318 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2319
2320 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2321 tasklet_schedule(&host->tasklet);
2322}
2323
6130e7a9
DA		 2324static void dw_mci_handle_cd(struct dw_mci *host)
2325{
2326 int i;
2327
2328 for (i = 0; i < host->num_slots; i++) {
2329 struct dw_mci_slot *slot = host->slot[i];
2330
2331 if (!slot)
2332 continue;
2333
2334 if (slot->mmc->ops->card_event)
2335 slot->mmc->ops->card_event(slot->mmc);
2336 mmc_detect_change(slot->mmc,
2337 msecs_to_jiffies(host->pdata->detect_delay_ms));
2338 }
2339}
2340
f95f3850
WN		 2341static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2342{
2343 struct dw_mci *host = dev_id;
182c9081 2344 u32 pending;
1a5c8e1f 2345 int i;
f95f3850 2346
1fb5f68a
MC		 2347 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2348
476d79f1 2349 if (pending) {
01730558
DA		 2350 /* Check volt switch first, since it can look like an error */
2351 if ((host->state == STATE_SENDING_CMD11) &&
2352 (pending & SDMMC_INT_VOLT_SWITCH)) {
49ba0302 2353 unsigned long irqflags;
5c935165 2354
01730558
DA		 2355 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2356 pending &= ~SDMMC_INT_VOLT_SWITCH;
49ba0302
DA		 2357
2358 /*
2359 * Hold the lock; we know cmd11_timer can't be kicked
2360 * off after the lock is released, so safe to delete.
2361 */
2362 spin_lock_irqsave(&host->irq_lock, irqflags);
01730558 2363 dw_mci_cmd_interrupt(host, pending);
49ba0302
DA		 2364 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2365
2366 del_timer(&host->cmd11_timer);
01730558
DA		 2367 }
2368
f95f3850
WN		 2369 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2370 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 2371 host->cmd_status = pending;
0e3a22c0 2372 smp_wmb(); /* drain writebuffer */
f95f3850 2373 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 2374 }
2375
2376 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2377 /* if there is an error report DATA_ERROR */
2378 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 2379 host->data_status = pending;
0e3a22c0 2380 smp_wmb(); /* drain writebuffer */
f95f3850 2381 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 2382 tasklet_schedule(&host->tasklet);
f95f3850
WN		 2383 }
2384
2385 if (pending & SDMMC_INT_DATA_OVER) {
57e10486
AK		 2386 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
2387 del_timer(&host->dto_timer);
2388
f95f3850
WN		 2389 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2390 if (!host->data_status)
182c9081 2391 host->data_status = pending;
0e3a22c0 2392 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2393 if (host->dir_status == DW_MCI_RECV_STATUS) {
2394 if (host->sg != NULL)
87a74d39 2395 dw_mci_read_data_pio(host, true);
f95f3850
WN		 2396 }
2397 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2398 tasklet_schedule(&host->tasklet);
2399 }
2400
2401 if (pending & SDMMC_INT_RXDR) {
2402 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 2403 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
87a74d39 2404 dw_mci_read_data_pio(host, false);
f95f3850
WN		 2405 }
2406
2407 if (pending & SDMMC_INT_TXDR) {
2408 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 2409 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 2410 dw_mci_write_data_pio(host);
2411 }
2412
2413 if (pending & SDMMC_INT_CMD_DONE) {
2414 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 2415 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 2416 }
2417
2418 if (pending & SDMMC_INT_CD) {
2419 mci_writel(host, RINTSTS, SDMMC_INT_CD);
6130e7a9 2420 dw_mci_handle_cd(host);
f95f3850
WN		 2421 }
2422
1a5c8e1f
SH		 2423 /* Handle SDIO Interrupts */
2424 for (i = 0; i < host->num_slots; i++) {
2425 struct dw_mci_slot *slot = host->slot[i];
ed2540ef
DA		 2426
2427 if (!slot)
2428 continue;
2429
76756234
AK		 2430 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2431 mci_writel(host, RINTSTS,
2432 SDMMC_INT_SDIO(slot->sdio_id));
1a5c8e1f
SH		 2433 mmc_signal_sdio_irq(slot->mmc);
2434 }
2435 }
2436
1fb5f68a 2437 }
f95f3850 2438
3fc7eaef
SL		 2439 if (host->use_dma != TRANS_MODE_IDMAC)
2440 return IRQ_HANDLED;
2441
2442 /* Handle IDMA interrupts */
69d99fdc
PT		 2443 if (host->dma_64bit_address == 1) {
2444 pending = mci_readl(host, IDSTS64);
2445 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2446 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2447 SDMMC_IDMAC_INT_RI);
2448 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
3fc7eaef 2449 host->dma_ops->complete((void *)host);
69d99fdc
PT		 2450 }
2451 } else {
2452 pending = mci_readl(host, IDSTS);
2453 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2454 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2455 SDMMC_IDMAC_INT_RI);
2456 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3fc7eaef 2457 host->dma_ops->complete((void *)host);
69d99fdc 2458 }
f95f3850 2459 }
f95f3850
WN		 2460
2461 return IRQ_HANDLED;
2462}
2463
c91eab4b 2464#ifdef CONFIG_OF
eff8f2f5
LPC		 2465/* given a slot, find out the device node representing that slot */
2466static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
c91eab4b 2467{
eff8f2f5 2468 struct device *dev = slot->mmc->parent;
c91eab4b
TA		 2469 struct device_node *np;
2470 const __be32 *addr;
2471 int len;
2472
2473 if (!dev || !dev->of_node)
2474 return NULL;
2475
2476 for_each_child_of_node(dev->of_node, np) {
2477 addr = of_get_property(np, "reg", &len);
2478 if (!addr || (len < sizeof(int)))
2479 continue;
eff8f2f5 2480 if (be32_to_cpup(addr) == slot->id)
c91eab4b
TA		 2481 return np;
2482 }
2483 return NULL;
2484}
2485
eff8f2f5 2486static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
a70aaa64 2487{
eff8f2f5 2488 struct device_node *np = dw_mci_of_find_slot_node(slot);
a70aaa64 2489
eff8f2f5
LPC		 2490 if (!np)
2491 return;
a70aaa64 2492
eff8f2f5
LPC		 2493 if (of_property_read_bool(np, "disable-wp")) {
2494 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2495 dev_warn(slot->mmc->parent,
2496 "Slot quirk 'disable-wp' is deprecated\n");
2497 }
a70aaa64 2498}
c91eab4b 2499#else /* CONFIG_OF */
eff8f2f5 2500static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
a70aaa64 2501{
a70aaa64 2502}
c91eab4b
TA		 2503#endif /* CONFIG_OF */
2504
36c179a9 2505static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 2506{
2507 struct mmc_host *mmc;
2508 struct dw_mci_slot *slot;
e95baf13 2509 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2510 int ctrl_id, ret;
1f44a2a5 2511 u32 freq[2];
f95f3850 2512
4a90920c 2513 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 2514 if (!mmc)
2515 return -ENOMEM;
2516
2517 slot = mmc_priv(mmc);
2518 slot->id = id;
76756234 2519 slot->sdio_id = host->sdio_id0 + id;
f95f3850
WN		 2520 slot->mmc = mmc;
2521 slot->host = host;
c91eab4b 2522 host->slot[id] = slot;
f95f3850
WN		 2523
2524 mmc->ops = &dw_mci_ops;
1f44a2a5
SJ		 2525 if (of_property_read_u32_array(host->dev->of_node,
2526 "clock-freq-min-max", freq, 2)) {
2527 mmc->f_min = DW_MCI_FREQ_MIN;
2528 mmc->f_max = DW_MCI_FREQ_MAX;
2529 } else {
2530 mmc->f_min = freq[0];
2531 mmc->f_max = freq[1];
2532 }
f95f3850 2533
51da2240
YC		 2534 /*if there are external regulators, get them*/
2535 ret = mmc_regulator_get_supply(mmc);
2536 if (ret == -EPROBE_DEFER)
3cf890fc 2537 goto err_host_allocated;
51da2240
YC		 2538
2539 if (!mmc->ocr_avail)
2540 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
f95f3850 2541
fc3d7720
JC		 2542 if (host->pdata->caps)
2543 mmc->caps = host->pdata->caps;
fc3d7720 2544
ab269128
AK		 2545 if (host->pdata->pm_caps)
2546 mmc->pm_caps = host->pdata->pm_caps;
2547
800d78bf
TA		 2548 if (host->dev->of_node) {
2549 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2550 if (ctrl_id < 0)
2551 ctrl_id = 0;
2552 } else {
2553 ctrl_id = to_platform_device(host->dev)->id;
2554 }
cb27a843
JH		 2555 if (drv_data && drv_data->caps)
2556 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 2557
4f408cc6
SJ		 2558 if (host->pdata->caps2)
2559 mmc->caps2 = host->pdata->caps2;
4f408cc6 2560
eff8f2f5
LPC		 2561 dw_mci_slot_of_parse(slot);
2562
3cf890fc
DA		 2563 ret = mmc_of_parse(mmc);
2564 if (ret)
2565 goto err_host_allocated;
f95f3850 2566
2b708df2 2567 /* Useful defaults if platform data is unset. */
3fc7eaef 2568 if (host->use_dma == TRANS_MODE_IDMAC) {
2b708df2
JC		 2569 mmc->max_segs = host->ring_size;
2570 mmc->max_blk_size = 65536;
2571 mmc->max_seg_size = 0x1000;
2572 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2573 mmc->max_blk_count = mmc->max_req_size / 512;
3fc7eaef
SL		 2574 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2575 mmc->max_segs = 64;
2576 mmc->max_blk_size = 65536;
2577 mmc->max_blk_count = 65535;
2578 mmc->max_req_size =
2579 mmc->max_blk_size * mmc->max_blk_count;
2580 mmc->max_seg_size = mmc->max_req_size;
f95f3850 2581 } else {
3fc7eaef 2582 /* TRANS_MODE_PIO */
2b708df2
JC		 2583 mmc->max_segs = 64;
2584 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2585 mmc->max_blk_count = 512;
2586 mmc->max_req_size = mmc->max_blk_size *
2587 mmc->max_blk_count;
2588 mmc->max_seg_size = mmc->max_req_size;
a39e5746 2589 }
f95f3850 2590
ae0eb348
JC		 2591 if (dw_mci_get_cd(mmc))
2592 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2593 else
2594 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2595
0cea529d
JC		 2596 ret = mmc_add_host(mmc);
2597 if (ret)
3cf890fc 2598 goto err_host_allocated;
f95f3850
WN		 2599
2600#if defined(CONFIG_DEBUG_FS)
2601 dw_mci_init_debugfs(slot);
2602#endif
2603
f95f3850 2604 return 0;
800d78bf 2605
3cf890fc 2606err_host_allocated:
800d78bf 2607 mmc_free_host(mmc);
51da2240 2608 return ret;
f95f3850
WN		 2609}
2610
2611static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2612{
f95f3850
WN		 2613 /* Debugfs stuff is cleaned up by mmc core */
2614 mmc_remove_host(slot->mmc);
2615 slot->host->slot[id] = NULL;
2616 mmc_free_host(slot->mmc);
2617}
2618
2619static void dw_mci_init_dma(struct dw_mci *host)
2620{
69d99fdc 2621 int addr_config;
3fc7eaef
SL		 2622 struct device *dev = host->dev;
2623 struct device_node *np = dev->of_node;
69d99fdc 2624
3fc7eaef
SL		 2625 /*
2626 * Check tansfer mode from HCON[17:16]
2627 * Clear the ambiguous description of dw_mmc databook:
2628 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2629 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2630 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2631 * 2b'11: Non DW DMA Interface -> pio only
2632 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2633 * simpler request/acknowledge handshake mechanism and both of them
2634 * are regarded as external dma master for dw_mmc.
2635 */
2636 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2637 if (host->use_dma == DMA_INTERFACE_IDMA) {
2638 host->use_dma = TRANS_MODE_IDMAC;
2639 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2640 host->use_dma == DMA_INTERFACE_GDMA) {
2641 host->use_dma = TRANS_MODE_EDMAC;
2642 } else {
f95f3850
WN		 2643 goto no_dma;
2644 }
2645
2646 /* Determine which DMA interface to use */
3fc7eaef
SL		 2647 if (host->use_dma == TRANS_MODE_IDMAC) {
2648 /*
2649 * Check ADDR_CONFIG bit in HCON to find
2650 * IDMAC address bus width
2651 */
70692752 2652 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
3fc7eaef
SL		 2653
2654 if (addr_config == 1) {
2655 /* host supports IDMAC in 64-bit address mode */
2656 host->dma_64bit_address = 1;
2657 dev_info(host->dev,
2658 "IDMAC supports 64-bit address mode.\n");
2659 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2660 dma_set_coherent_mask(host->dev,
2661 DMA_BIT_MASK(64));
2662 } else {
2663 /* host supports IDMAC in 32-bit address mode */
2664 host->dma_64bit_address = 0;
2665 dev_info(host->dev,
2666 "IDMAC supports 32-bit address mode.\n");
2667 }
f95f3850 2668
3fc7eaef
SL		 2669 /* Alloc memory for sg translation */
2670 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2671 &host->sg_dma, GFP_KERNEL);
2672 if (!host->sg_cpu) {
2673 dev_err(host->dev,
2674 "%s: could not alloc DMA memory\n",
2675 __func__);
2676 goto no_dma;
2677 }
2678
2679 host->dma_ops = &dw_mci_idmac_ops;
2680 dev_info(host->dev, "Using internal DMA controller.\n");
2681 } else {
2682 /* TRANS_MODE_EDMAC: check dma bindings again */
2683 if ((of_property_count_strings(np, "dma-names") < 0) ||
2684 (!of_find_property(np, "dmas", NULL))) {
2685 goto no_dma;
2686 }
2687 host->dma_ops = &dw_mci_edmac_ops;
2688 dev_info(host->dev, "Using external DMA controller.\n");
2689 }
f95f3850 2690
e1631f98
JC		 2691 if (host->dma_ops->init && host->dma_ops->start &&
2692 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 2693 if (host->dma_ops->init(host)) {
0e3a22c0
SL		 2694 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2695 __func__);
f95f3850
WN		 2696 goto no_dma;
2697 }
2698 } else {
4a90920c 2699 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 2700 goto no_dma;
2701 }
2702
f95f3850
WN		 2703 return;
2704
2705no_dma:
4a90920c 2706 dev_info(host->dev, "Using PIO mode.\n");
3fc7eaef 2707 host->use_dma = TRANS_MODE_PIO;
f95f3850
WN		 2708}
2709
31bff450 2710static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
f95f3850
WN		 2711{
2712 unsigned long timeout = jiffies + msecs_to_jiffies(500);
31bff450 2713 u32 ctrl;
f95f3850 2714
31bff450
SJ		 2715 ctrl = mci_readl(host, CTRL);
2716 ctrl |= reset;
2717 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 2718
2719 /* wait till resets clear */
2720 do {
2721 ctrl = mci_readl(host, CTRL);
31bff450 2722 if (!(ctrl & reset))
f95f3850
WN		 2723 return true;
2724 } while (time_before(jiffies, timeout));
2725
31bff450
SJ		 2726 dev_err(host->dev,
2727 "Timeout resetting block (ctrl reset %#x)\n",
2728 ctrl & reset);
f95f3850
WN		 2729
2730 return false;
2731}
2732
3a33a94c 2733static bool dw_mci_reset(struct dw_mci *host)
31bff450 2734{
3a33a94c
SR		 2735 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2736 bool ret = false;
2737
31bff450
SJ		 2738 /*
2739 * Reseting generates a block interrupt, hence setting
2740 * the scatter-gather pointer to NULL.
2741 */
2742 if (host->sg) {
2743 sg_miter_stop(&host->sg_miter);
2744 host->sg = NULL;
2745 }
2746
3a33a94c
SR		 2747 if (host->use_dma)
2748 flags |= SDMMC_CTRL_DMA_RESET;
31bff450 2749
3a33a94c
SR		 2750 if (dw_mci_ctrl_reset(host, flags)) {
2751 /*
2752 * In all cases we clear the RAWINTS register to clear any
2753 * interrupts.
2754 */
2755 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2756
2757 /* if using dma we wait for dma_req to clear */
2758 if (host->use_dma) {
2759 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2760 u32 status;
0e3a22c0 2761
3a33a94c
SR		 2762 do {
2763 status = mci_readl(host, STATUS);
2764 if (!(status & SDMMC_STATUS_DMA_REQ))
2765 break;
2766 cpu_relax();
2767 } while (time_before(jiffies, timeout));
2768
2769 if (status & SDMMC_STATUS_DMA_REQ) {
2770 dev_err(host->dev,
0e3a22c0
SL		 2771 "%s: Timeout waiting for dma_req to clear during reset\n",
2772 __func__);
3a33a94c
SR		 2773 goto ciu_out;
2774 }
2775
2776 /* when using DMA next we reset the fifo again */
2777 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2778 goto ciu_out;
2779 }
2780 } else {
2781 /* if the controller reset bit did clear, then set clock regs */
2782 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
0e3a22c0
SL		 2783 dev_err(host->dev,
2784 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
3a33a94c
SR		 2785 __func__);
2786 goto ciu_out;
2787 }
2788 }
2789
3fc7eaef
SL		 2790 if (host->use_dma == TRANS_MODE_IDMAC)
2791 /* It is also recommended that we reset and reprogram idmac */
2792 dw_mci_idmac_reset(host);
3a33a94c
SR		 2793
2794 ret = true;
2795
2796ciu_out:
2797 /* After a CTRL reset we need to have CIU set clock registers */
2798 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2799
2800 return ret;
31bff450
SJ		 2801}
2802
5c935165
DA		 2803static void dw_mci_cmd11_timer(unsigned long arg)
2804{
2805 struct dw_mci *host = (struct dw_mci *)arg;
2806
fd674198
DA		 2807 if (host->state != STATE_SENDING_CMD11) {
2808 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2809 return;
2810 }
5c935165
DA		 2811
2812 host->cmd_status = SDMMC_INT_RTO;
2813 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2814 tasklet_schedule(&host->tasklet);
2815}
2816
57e10486
AK		 2817static void dw_mci_dto_timer(unsigned long arg)
2818{
2819 struct dw_mci *host = (struct dw_mci *)arg;
2820
2821 switch (host->state) {
2822 case STATE_SENDING_DATA:
2823 case STATE_DATA_BUSY:
2824 /*
2825 * If DTO interrupt does NOT come in sending data state,
2826 * we should notify the driver to terminate current transfer
2827 * and report a data timeout to the core.
2828 */
2829 host->data_status = SDMMC_INT_DRTO;
2830 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2831 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2832 tasklet_schedule(&host->tasklet);
2833 break;
2834 default:
2835 break;
2836 }
2837}
2838
c91eab4b
TA		 2839#ifdef CONFIG_OF
2840static struct dw_mci_of_quirks {
2841 char *quirk;
2842 int id;
2843} of_quirks[] = {
2844 {
c91eab4b
TA		 2845 .quirk = "broken-cd",
2846 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2847 },
2848};
2849
2850static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2851{
2852 struct dw_mci_board *pdata;
2853 struct device *dev = host->dev;
2854 struct device_node *np = dev->of_node;
e95baf13 2855 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2856 int idx, ret;
3c6d89ea 2857 u32 clock_frequency;
c91eab4b
TA		 2858
2859 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
bf3707ea 2860 if (!pdata)
c91eab4b 2861 return ERR_PTR(-ENOMEM);
c91eab4b
TA		 2862
2863 /* find out number of slots supported */
2864 if (of_property_read_u32(dev->of_node, "num-slots",
2865 &pdata->num_slots)) {
0e3a22c0
SL		 2866 dev_info(dev,
2867 "num-slots property not found, assuming 1 slot is available\n");
c91eab4b
TA		 2868 pdata->num_slots = 1;
2869 }
2870
2871 /* get quirks */
2872 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2873 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2874 pdata->quirks |= of_quirks[idx].id;
2875
2876 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
0e3a22c0
SL		 2877 dev_info(dev,
2878 "fifo-depth property not found, using value of FIFOTH register as default\n");
c91eab4b
TA		 2879
2880 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2881
3c6d89ea
DA		 2882 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2883 pdata->bus_hz = clock_frequency;
2884
cb27a843
JH		 2885 if (drv_data && drv_data->parse_dt) {
2886 ret = drv_data->parse_dt(host);
800d78bf
TA		 2887 if (ret)
2888 return ERR_PTR(ret);
2889 }
2890
40a7a463
JC		 2891 if (of_find_property(np, "supports-highspeed", NULL)) {
2892 dev_info(dev, "supports-highspeed property is deprecated.\n");
10b49841 2893 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
40a7a463 2894 }
10b49841 2895
c91eab4b
TA		 2896 return pdata;
2897}
2898
2899#else /* CONFIG_OF */
2900static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2901{
2902 return ERR_PTR(-EINVAL);
2903}
2904#endif /* CONFIG_OF */
2905
fa0c3283
DA		 2906static void dw_mci_enable_cd(struct dw_mci *host)
2907{
2908 struct dw_mci_board *brd = host->pdata;
2909 unsigned long irqflags;
2910 u32 temp;
2911 int i;
2912
2913 /* No need for CD if broken card detection */
2914 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2915 return;
2916
2917 /* No need for CD if all slots have a non-error GPIO */
2918 for (i = 0; i < host->num_slots; i++) {
2919 struct dw_mci_slot *slot = host->slot[i];
2920
2921 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2922 break;
2923 }
2924 if (i == host->num_slots)
2925 return;
2926
2927 spin_lock_irqsave(&host->irq_lock, irqflags);
2928 temp = mci_readl(host, INTMASK);
2929 temp |= SDMMC_INT_CD;
2930 mci_writel(host, INTMASK, temp);
2931 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2932}
2933
62ca8034 2934int dw_mci_probe(struct dw_mci *host)
f95f3850 2935{
e95baf13 2936 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 2937 int width, i, ret = 0;
f95f3850 2938 u32 fifo_size;
1c2215b7 2939 int init_slots = 0;
f95f3850 2940
c91eab4b
TA		 2941 if (!host->pdata) {
2942 host->pdata = dw_mci_parse_dt(host);
2943 if (IS_ERR(host->pdata)) {
2944 dev_err(host->dev, "platform data not available\n");
2945 return -EINVAL;
2946 }
f95f3850
WN		 2947 }
2948
9e747b7e 2949 if (host->pdata->num_slots < 1) {
4a90920c 2950 dev_err(host->dev,
907abd51 2951 "Platform data must supply num_slots.\n");
62ca8034 2952 return -ENODEV;
f95f3850
WN		 2953 }
2954
780f22af 2955 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 2956 if (IS_ERR(host->biu_clk)) {
2957 dev_dbg(host->dev, "biu clock not available\n");
2958 } else {
2959 ret = clk_prepare_enable(host->biu_clk);
2960 if (ret) {
2961 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 2962 return ret;
2963 }
2964 }
2965
780f22af 2966 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 2967 if (IS_ERR(host->ciu_clk)) {
2968 dev_dbg(host->dev, "ciu clock not available\n");
3c6d89ea 2969 host->bus_hz = host->pdata->bus_hz;
f90a0612
TA		 2970 } else {
2971 ret = clk_prepare_enable(host->ciu_clk);
2972 if (ret) {
2973 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 2974 goto err_clk_biu;
2975 }
f90a0612 2976
3c6d89ea
DA		 2977 if (host->pdata->bus_hz) {
2978 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2979 if (ret)
2980 dev_warn(host->dev,
612de4c1 2981 "Unable to set bus rate to %uHz\n",
3c6d89ea
DA		 2982 host->pdata->bus_hz);
2983 }
f90a0612 2984 host->bus_hz = clk_get_rate(host->ciu_clk);
3c6d89ea 2985 }
f90a0612 2986
612de4c1
JC		 2987 if (!host->bus_hz) {
2988 dev_err(host->dev,
2989 "Platform data must supply bus speed\n");
2990 ret = -ENODEV;
2991 goto err_clk_ciu;
2992 }
2993
002f0d5c
YK		 2994 if (drv_data && drv_data->init) {
2995 ret = drv_data->init(host);
2996 if (ret) {
2997 dev_err(host->dev,
2998 "implementation specific init failed\n");
2999 goto err_clk_ciu;
3000 }
3001 }
3002
cb27a843
JH		 3003 if (drv_data && drv_data->setup_clock) {
3004 ret = drv_data->setup_clock(host);
800d78bf
TA		 3005 if (ret) {
3006 dev_err(host->dev,
3007 "implementation specific clock setup failed\n");
3008 goto err_clk_ciu;
3009 }
3010 }
3011
5c935165
DA		 3012 setup_timer(&host->cmd11_timer,
3013 dw_mci_cmd11_timer, (unsigned long)host);
3014
62ca8034 3015 host->quirks = host->pdata->quirks;
f95f3850 3016
57e10486
AK		 3017 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3018 setup_timer(&host->dto_timer,
3019 dw_mci_dto_timer, (unsigned long)host);
3020
f95f3850 3021 spin_lock_init(&host->lock);
f8c58c11 3022 spin_lock_init(&host->irq_lock);
f95f3850
WN		 3023 INIT_LIST_HEAD(&host->queue);
3024
f95f3850
WN		 3025 /*
3026 * Get the host data width - this assumes that HCON has been set with
3027 * the correct values.
3028 */
70692752 3029 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
f95f3850
WN		 3030 if (!i) {
3031 host->push_data = dw_mci_push_data16;
3032 host->pull_data = dw_mci_pull_data16;
3033 width = 16;
3034 host->data_shift = 1;
3035 } else if (i == 2) {
3036 host->push_data = dw_mci_push_data64;
3037 host->pull_data = dw_mci_pull_data64;
3038 width = 64;
3039 host->data_shift = 3;
3040 } else {
3041 /* Check for a reserved value, and warn if it is */
3042 WARN((i != 1),
3043 "HCON reports a reserved host data width!\n"
3044 "Defaulting to 32-bit access.\n");
3045 host->push_data = dw_mci_push_data32;
3046 host->pull_data = dw_mci_pull_data32;
3047 width = 32;
3048 host->data_shift = 2;
3049 }
3050
3051 /* Reset all blocks */
3a33a94c 3052 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
141a712a
SJ		 3053 return -ENODEV;
3054
3055 host->dma_ops = host->pdata->dma_ops;
3056 dw_mci_init_dma(host);
f95f3850
WN		 3057
3058 /* Clear the interrupts for the host controller */
3059 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3060 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3061
3062 /* Put in max timeout */
3063 mci_writel(host, TMOUT, 0xFFFFFFFF);
3064
3065 /*
3066 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3067 * Tx Mark = fifo_size / 2 DMA Size = 8
3068 */
b86d8253
JH		 3069 if (!host->pdata->fifo_depth) {
3070 /*
3071 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3072 * have been overwritten by the bootloader, just like we're
3073 * about to do, so if you know the value for your hardware, you
3074 * should put it in the platform data.
3075 */
3076 fifo_size = mci_readl(host, FIFOTH);
8234e869 3077 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 3078 } else {
3079 fifo_size = host->pdata->fifo_depth;
3080 }
3081 host->fifo_depth = fifo_size;
52426899
SJ		 3082 host->fifoth_val =
3083 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
e61cf118 3084 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 3085
3086 /* disable clock to CIU */
3087 mci_writel(host, CLKENA, 0);
3088 mci_writel(host, CLKSRC, 0);
3089
63008768
JH		 3090 /*
3091 * In 2.40a spec, Data offset is changed.
3092 * Need to check the version-id and set data-offset for DATA register.
3093 */
3094 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3095 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3096
3097 if (host->verid < DW_MMC_240A)
76184ac1 3098 host->fifo_reg = host->regs + DATA_OFFSET;
63008768 3099 else
76184ac1 3100 host->fifo_reg = host->regs + DATA_240A_OFFSET;
63008768 3101
f95f3850 3102 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
780f22af
SJ		 3103 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3104 host->irq_flags, "dw-mci", host);
f95f3850 3105 if (ret)
6130e7a9 3106 goto err_dmaunmap;
f95f3850 3107
f95f3850
WN		 3108 if (host->pdata->num_slots)
3109 host->num_slots = host->pdata->num_slots;
3110 else
70692752 3111 host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
f95f3850 3112
2da1d7f2 3113 /*
fa0c3283 3114 * Enable interrupts for command done, data over, data empty,
2da1d7f2
YC		 3115 * receive ready and error such as transmit, receive timeout, crc error
3116 */
3117 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3118 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3119 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3120 DW_MCI_ERROR_FLAGS);
0e3a22c0
SL		 3121 /* Enable mci interrupt */
3122 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2da1d7f2 3123
0e3a22c0
SL		 3124 dev_info(host->dev,
3125 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
2da1d7f2
YC		 3126 host->irq, width, fifo_size);
3127
f95f3850
WN		 3128 /* We need at least one slot to succeed */
3129 for (i = 0; i < host->num_slots; i++) {
3130 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 3131 if (ret)
3132 dev_dbg(host->dev, "slot %d init failed\n", i);
3133 else
3134 init_slots++;
3135 }
3136
3137 if (init_slots) {
3138 dev_info(host->dev, "%d slots initialized\n", init_slots);
3139 } else {
0e3a22c0
SL		 3140 dev_dbg(host->dev,
3141 "attempted to initialize %d slots, but failed on all\n",
3142 host->num_slots);
6130e7a9 3143 goto err_dmaunmap;
f95f3850
WN		 3144 }
3145
b793f658
DA		 3146 /* Now that slots are all setup, we can enable card detect */
3147 dw_mci_enable_cd(host);
3148
f95f3850
WN		 3149 return 0;
3150
f95f3850
WN		 3151err_dmaunmap:
3152 if (host->use_dma && host->dma_ops->exit)
3153 host->dma_ops->exit(host);
f90a0612
TA		 3154
3155err_clk_ciu:
780f22af 3156 if (!IS_ERR(host->ciu_clk))
f90a0612 3157 clk_disable_unprepare(host->ciu_clk);
780f22af 3158
f90a0612 3159err_clk_biu:
780f22af 3160 if (!IS_ERR(host->biu_clk))
f90a0612 3161 clk_disable_unprepare(host->biu_clk);
780f22af 3162
f95f3850
WN		 3163 return ret;
3164}
62ca8034 3165EXPORT_SYMBOL(dw_mci_probe);
f95f3850 3166
62ca8034 3167void dw_mci_remove(struct dw_mci *host)
f95f3850 3168{
f95f3850
WN		 3169 int i;
3170
f95f3850 3171 for (i = 0; i < host->num_slots; i++) {
4a90920c 3172 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 3173 if (host->slot[i])
3174 dw_mci_cleanup_slot(host->slot[i], i);
3175 }
3176
048fd7e6
PT		 3177 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3178 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3179
f95f3850
WN		 3180 /* disable clock to CIU */
3181 mci_writel(host, CLKENA, 0);
3182 mci_writel(host, CLKSRC, 0);
3183
f95f3850
WN		 3184 if (host->use_dma && host->dma_ops->exit)
3185 host->dma_ops->exit(host);
3186
f90a0612
TA		 3187 if (!IS_ERR(host->ciu_clk))
3188 clk_disable_unprepare(host->ciu_clk);
780f22af 3189
f90a0612
TA		 3190 if (!IS_ERR(host->biu_clk))
3191 clk_disable_unprepare(host->biu_clk);
f95f3850 3192}
62ca8034
SH		 3193EXPORT_SYMBOL(dw_mci_remove);
3194
3195
f95f3850 3196
6fe8890d 3197#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 3198/*
3199 * TODO: we should probably disable the clock to the card in the suspend path.
3200 */
62ca8034 3201int dw_mci_suspend(struct dw_mci *host)
f95f3850 3202{
3fc7eaef
SL		 3203 if (host->use_dma && host->dma_ops->exit)
3204 host->dma_ops->exit(host);
3205
f95f3850
WN		 3206 return 0;
3207}
62ca8034 3208EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 3209
62ca8034 3210int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 3211{
3212 int i, ret;
f95f3850 3213
3a33a94c 3214 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
e61cf118
JC		 3215 ret = -ENODEV;
3216 return ret;
3217 }
3218
3bfe619d 3219 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 3220 host->dma_ops->init(host);
3221
52426899
SJ		 3222 /*
3223 * Restore the initial value at FIFOTH register
3224 * And Invalidate the prev_blksz with zero
3225 */
e61cf118 3226 mci_writel(host, FIFOTH, host->fifoth_val);
52426899 3227 host->prev_blksz = 0;
e61cf118 3228
2eb2944f
DA		 3229 /* Put in max timeout */
3230 mci_writel(host, TMOUT, 0xFFFFFFFF);
3231
e61cf118
JC		 3232 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3233 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3234 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3235 DW_MCI_ERROR_FLAGS);
e61cf118
JC		 3236 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3237
f95f3850
WN		 3238 for (i = 0; i < host->num_slots; i++) {
3239 struct dw_mci_slot *slot = host->slot[i];
0e3a22c0 3240
f95f3850
WN		 3241 if (!slot)
3242 continue;
ab269128
AK		 3243 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3244 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3245 dw_mci_setup_bus(slot, true);
3246 }
f95f3850 3247 }
fa0c3283
DA		 3248
3249 /* Now that slots are all setup, we can enable card detect */
3250 dw_mci_enable_cd(host);
3251
f95f3850
WN		 3252 return 0;
3253}
62ca8034 3254EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 3255#endif /* CONFIG_PM_SLEEP */
3256
f95f3850
WN		 3257static int __init dw_mci_init(void)
3258{
8e1c4e4d 3259 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
62ca8034 3260 return 0;
f95f3850
WN		 3261}
3262
3263static void __exit dw_mci_exit(void)
3264{
f95f3850
WN		 3265}
3266
3267module_init(dw_mci_init);
3268module_exit(dw_mci_exit);
3269
3270MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3271MODULE_AUTHOR("NXP Semiconductor VietNam");
3272MODULE_AUTHOR("Imagination Technologies Ltd");
3273MODULE_LICENSE("GPL v2");
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