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mmc: dw_mmc: clear TXDR/RXDR ints before enabling
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/scatterlist.h>
26#include <linux/seq_file.h>
27#include <linux/slab.h>
28#include <linux/stat.h>
29#include <linux/delay.h>
30#include <linux/irq.h>
31#include <linux/mmc/host.h>
32#include <linux/mmc/mmc.h>
33#include <linux/mmc/dw_mmc.h>
34#include <linux/bitops.h>
c07946a3 35#include <linux/regulator/consumer.h>
f95f3850
WN		 36
37#include "dw_mmc.h"
38
39/* Common flag combinations */
40#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
41 SDMMC_INT_HTO | SDMMC_INT_SBE | \
42 SDMMC_INT_EBE)
43#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
44 SDMMC_INT_RESP_ERR)
45#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
46 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
47#define DW_MCI_SEND_STATUS 1
48#define DW_MCI_RECV_STATUS 2
49#define DW_MCI_DMA_THRESHOLD 16
50
51#ifdef CONFIG_MMC_DW_IDMAC
52struct idmac_desc {
53 u32 des0; /* Control Descriptor */
54#define IDMAC_DES0_DIC BIT(1)
55#define IDMAC_DES0_LD BIT(2)
56#define IDMAC_DES0_FD BIT(3)
57#define IDMAC_DES0_CH BIT(4)
58#define IDMAC_DES0_ER BIT(5)
59#define IDMAC_DES0_CES BIT(30)
60#define IDMAC_DES0_OWN BIT(31)
61
62 u32 des1; /* Buffer sizes */
63#define IDMAC_SET_BUFFER1_SIZE(d, s) \
64 ((d)->des1 = ((d)->des1 & 0x03ffc000) | ((s) & 0x3fff))
65
66 u32 des2; /* buffer 1 physical address */
67
68 u32 des3; /* buffer 2 physical address */
69};
70#endif /* CONFIG_MMC_DW_IDMAC */
71
72/**
73 * struct dw_mci_slot - MMC slot state
74 * @mmc: The mmc_host representing this slot.
75 * @host: The MMC controller this slot is using.
76 * @ctype: Card type for this slot.
77 * @mrq: mmc_request currently being processed or waiting to be
78 * processed, or NULL when the slot is idle.
79 * @queue_node: List node for placing this node in the @queue list of
80 * &struct dw_mci.
81 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
82 * @flags: Random state bits associated with the slot.
83 * @id: Number of this slot.
84 * @last_detect_state: Most recently observed card detect state.
85 */
86struct dw_mci_slot {
87 struct mmc_host *mmc;
88 struct dw_mci *host;
89
90 u32 ctype;
91
92 struct mmc_request *mrq;
93 struct list_head queue_node;
94
95 unsigned int clock;
96 unsigned long flags;
97#define DW_MMC_CARD_PRESENT 0
98#define DW_MMC_CARD_NEED_INIT 1
99 int id;
100 int last_detect_state;
101};
102
103#if defined(CONFIG_DEBUG_FS)
104static int dw_mci_req_show(struct seq_file *s, void *v)
105{
106 struct dw_mci_slot *slot = s->private;
107 struct mmc_request *mrq;
108 struct mmc_command *cmd;
109 struct mmc_command *stop;
110 struct mmc_data *data;
111
112 /* Make sure we get a consistent snapshot */
113 spin_lock_bh(&slot->host->lock);
114 mrq = slot->mrq;
115
116 if (mrq) {
117 cmd = mrq->cmd;
118 data = mrq->data;
119 stop = mrq->stop;
120
121 if (cmd)
122 seq_printf(s,
123 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
124 cmd->opcode, cmd->arg, cmd->flags,
125 cmd->resp[0], cmd->resp[1], cmd->resp[2],
126 cmd->resp[2], cmd->error);
127 if (data)
128 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
129 data->bytes_xfered, data->blocks,
130 data->blksz, data->flags, data->error);
131 if (stop)
132 seq_printf(s,
133 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
134 stop->opcode, stop->arg, stop->flags,
135 stop->resp[0], stop->resp[1], stop->resp[2],
136 stop->resp[2], stop->error);
137 }
138
139 spin_unlock_bh(&slot->host->lock);
140
141 return 0;
142}
143
144static int dw_mci_req_open(struct inode *inode, struct file *file)
145{
146 return single_open(file, dw_mci_req_show, inode->i_private);
147}
148
149static const struct file_operations dw_mci_req_fops = {
150 .owner = THIS_MODULE,
151 .open = dw_mci_req_open,
152 .read = seq_read,
153 .llseek = seq_lseek,
154 .release = single_release,
155};
156
157static int dw_mci_regs_show(struct seq_file *s, void *v)
158{
159 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
160 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
161 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
162 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
163 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
164 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
165
166 return 0;
167}
168
169static int dw_mci_regs_open(struct inode *inode, struct file *file)
170{
171 return single_open(file, dw_mci_regs_show, inode->i_private);
172}
173
174static const struct file_operations dw_mci_regs_fops = {
175 .owner = THIS_MODULE,
176 .open = dw_mci_regs_open,
177 .read = seq_read,
178 .llseek = seq_lseek,
179 .release = single_release,
180};
181
182static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
183{
184 struct mmc_host *mmc = slot->mmc;
185 struct dw_mci *host = slot->host;
186 struct dentry *root;
187 struct dentry *node;
188
189 root = mmc->debugfs_root;
190 if (!root)
191 return;
192
193 node = debugfs_create_file("regs", S_IRUSR, root, host,
194 &dw_mci_regs_fops);
195 if (!node)
196 goto err;
197
198 node = debugfs_create_file("req", S_IRUSR, root, slot,
199 &dw_mci_req_fops);
200 if (!node)
201 goto err;
202
203 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
204 if (!node)
205 goto err;
206
207 node = debugfs_create_x32("pending_events", S_IRUSR, root,
208 (u32 *)&host->pending_events);
209 if (!node)
210 goto err;
211
212 node = debugfs_create_x32("completed_events", S_IRUSR, root,
213 (u32 *)&host->completed_events);
214 if (!node)
215 goto err;
216
217 return;
218
219err:
220 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
221}
222#endif /* defined(CONFIG_DEBUG_FS) */
223
224static void dw_mci_set_timeout(struct dw_mci *host)
225{
226 /* timeout (maximum) */
227 mci_writel(host, TMOUT, 0xffffffff);
228}
229
230static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
231{
232 struct mmc_data *data;
233 u32 cmdr;
234 cmd->error = -EINPROGRESS;
235
236 cmdr = cmd->opcode;
237
238 if (cmdr == MMC_STOP_TRANSMISSION)
239 cmdr |= SDMMC_CMD_STOP;
240 else
241 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
242
243 if (cmd->flags & MMC_RSP_PRESENT) {
244 /* We expect a response, so set this bit */
245 cmdr |= SDMMC_CMD_RESP_EXP;
246 if (cmd->flags & MMC_RSP_136)
247 cmdr |= SDMMC_CMD_RESP_LONG;
248 }
249
250 if (cmd->flags & MMC_RSP_CRC)
251 cmdr |= SDMMC_CMD_RESP_CRC;
252
253 data = cmd->data;
254 if (data) {
255 cmdr |= SDMMC_CMD_DAT_EXP;
256 if (data->flags & MMC_DATA_STREAM)
257 cmdr |= SDMMC_CMD_STRM_MODE;
258 if (data->flags & MMC_DATA_WRITE)
259 cmdr |= SDMMC_CMD_DAT_WR;
260 }
261
262 return cmdr;
263}
264
265static void dw_mci_start_command(struct dw_mci *host,
266 struct mmc_command *cmd, u32 cmd_flags)
267{
268 host->cmd = cmd;
269 dev_vdbg(&host->pdev->dev,
270 "start command: ARGR=0x%08x CMDR=0x%08x\n",
271 cmd->arg, cmd_flags);
272
273 mci_writel(host, CMDARG, cmd->arg);
274 wmb();
275
276 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
277}
278
279static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
280{
281 dw_mci_start_command(host, data->stop, host->stop_cmdr);
282}
283
284/* DMA interface functions */
285static void dw_mci_stop_dma(struct dw_mci *host)
286{
287 if (host->use_dma) {
288 host->dma_ops->stop(host);
289 host->dma_ops->cleanup(host);
290 } else {
291 /* Data transfer was stopped by the interrupt handler */
292 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
293 }
294}
295
296#ifdef CONFIG_MMC_DW_IDMAC
297static void dw_mci_dma_cleanup(struct dw_mci *host)
298{
299 struct mmc_data *data = host->data;
300
301 if (data)
302 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
303 ((data->flags & MMC_DATA_WRITE)
304 ? DMA_TO_DEVICE : DMA_FROM_DEVICE));
305}
306
307static void dw_mci_idmac_stop_dma(struct dw_mci *host)
308{
309 u32 temp;
310
311 /* Disable and reset the IDMAC interface */
312 temp = mci_readl(host, CTRL);
313 temp &= ~SDMMC_CTRL_USE_IDMAC;
314 temp |= SDMMC_CTRL_DMA_RESET;
315 mci_writel(host, CTRL, temp);
316
317 /* Stop the IDMAC running */
318 temp = mci_readl(host, BMOD);
a5289a43 319 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
f95f3850
WN		 320 mci_writel(host, BMOD, temp);
321}
322
323static void dw_mci_idmac_complete_dma(struct dw_mci *host)
324{
325 struct mmc_data *data = host->data;
326
327 dev_vdbg(&host->pdev->dev, "DMA complete\n");
328
329 host->dma_ops->cleanup(host);
330
331 /*
332 * If the card was removed, data will be NULL. No point in trying to
333 * send the stop command or waiting for NBUSY in this case.
334 */
335 if (data) {
336 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
337 tasklet_schedule(&host->tasklet);
338 }
339}
340
341static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
342 unsigned int sg_len)
343{
344 int i;
345 struct idmac_desc *desc = host->sg_cpu;
346
347 for (i = 0; i < sg_len; i++, desc++) {
348 unsigned int length = sg_dma_len(&data->sg[i]);
349 u32 mem_addr = sg_dma_address(&data->sg[i]);
350
351 /* Set the OWN bit and disable interrupts for this descriptor */
352 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
353
354 /* Buffer length */
355 IDMAC_SET_BUFFER1_SIZE(desc, length);
356
357 /* Physical address to DMA to/from */
358 desc->des2 = mem_addr;
359 }
360
361 /* Set first descriptor */
362 desc = host->sg_cpu;
363 desc->des0 |= IDMAC_DES0_FD;
364
365 /* Set last descriptor */
366 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
367 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
368 desc->des0 |= IDMAC_DES0_LD;
369
370 wmb();
371}
372
373static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
374{
375 u32 temp;
376
377 dw_mci_translate_sglist(host, host->data, sg_len);
378
379 /* Select IDMAC interface */
380 temp = mci_readl(host, CTRL);
381 temp |= SDMMC_CTRL_USE_IDMAC;
382 mci_writel(host, CTRL, temp);
383
384 wmb();
385
386 /* Enable the IDMAC */
387 temp = mci_readl(host, BMOD);
a5289a43 388 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 389 mci_writel(host, BMOD, temp);
390
391 /* Start it running */
392 mci_writel(host, PLDMND, 1);
393}
394
395static int dw_mci_idmac_init(struct dw_mci *host)
396{
397 struct idmac_desc *p;
398 int i;
399
400 /* Number of descriptors in the ring buffer */
401 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
402
403 /* Forward link the descriptor list */
404 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
405 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
406
407 /* Set the last descriptor as the end-of-ring descriptor */
408 p->des3 = host->sg_dma;
409 p->des0 = IDMAC_DES0_ER;
410
411 /* Mask out interrupts - get Tx & Rx complete only */
412 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
413 SDMMC_IDMAC_INT_TI);
414
415 /* Set the descriptor base address */
416 mci_writel(host, DBADDR, host->sg_dma);
417 return 0;
418}
419
420static struct dw_mci_dma_ops dw_mci_idmac_ops = {
421 .init = dw_mci_idmac_init,
422 .start = dw_mci_idmac_start_dma,
423 .stop = dw_mci_idmac_stop_dma,
424 .complete = dw_mci_idmac_complete_dma,
425 .cleanup = dw_mci_dma_cleanup,
426};
427#endif /* CONFIG_MMC_DW_IDMAC */
428
429static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
430{
431 struct scatterlist *sg;
432 unsigned int i, direction, sg_len;
433 u32 temp;
434
435 /* If we don't have a channel, we can't do DMA */
436 if (!host->use_dma)
437 return -ENODEV;
438
439 /*
440 * We don't do DMA on "complex" transfers, i.e. with
441 * non-word-aligned buffers or lengths. Also, we don't bother
442 * with all the DMA setup overhead for short transfers.
443 */
444 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
445 return -EINVAL;
446 if (data->blksz & 3)
447 return -EINVAL;
448
449 for_each_sg(data->sg, sg, data->sg_len, i) {
450 if (sg->offset & 3 || sg->length & 3)
451 return -EINVAL;
452 }
453
454 if (data->flags & MMC_DATA_READ)
455 direction = DMA_FROM_DEVICE;
456 else
457 direction = DMA_TO_DEVICE;
458
459 sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
460 direction);
461
462 dev_vdbg(&host->pdev->dev,
463 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
464 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
465 sg_len);
466
467 /* Enable the DMA interface */
468 temp = mci_readl(host, CTRL);
469 temp |= SDMMC_CTRL_DMA_ENABLE;
470 mci_writel(host, CTRL, temp);
471
472 /* Disable RX/TX IRQs, let DMA handle it */
473 temp = mci_readl(host, INTMASK);
474 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
475 mci_writel(host, INTMASK, temp);
476
477 host->dma_ops->start(host, sg_len);
478
479 return 0;
480}
481
482static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
483{
484 u32 temp;
485
486 data->error = -EINPROGRESS;
487
488 WARN_ON(host->data);
489 host->sg = NULL;
490 host->data = data;
491
492 if (dw_mci_submit_data_dma(host, data)) {
493 host->sg = data->sg;
494 host->pio_offset = 0;
495 if (data->flags & MMC_DATA_READ)
496 host->dir_status = DW_MCI_RECV_STATUS;
497 else
498 host->dir_status = DW_MCI_SEND_STATUS;
499
b40af3aa 500 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 501 temp = mci_readl(host, INTMASK);
502 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
503 mci_writel(host, INTMASK, temp);
504
505 temp = mci_readl(host, CTRL);
506 temp &= ~SDMMC_CTRL_DMA_ENABLE;
507 mci_writel(host, CTRL, temp);
508 }
509}
510
511static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
512{
513 struct dw_mci *host = slot->host;
514 unsigned long timeout = jiffies + msecs_to_jiffies(500);
515 unsigned int cmd_status = 0;
516
517 mci_writel(host, CMDARG, arg);
518 wmb();
519 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
520
521 while (time_before(jiffies, timeout)) {
522 cmd_status = mci_readl(host, CMD);
523 if (!(cmd_status & SDMMC_CMD_START))
524 return;
525 }
526 dev_err(&slot->mmc->class_dev,
527 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
528 cmd, arg, cmd_status);
529}
530
531static void dw_mci_setup_bus(struct dw_mci_slot *slot)
532{
533 struct dw_mci *host = slot->host;
534 u32 div;
535
536 if (slot->clock != host->current_speed) {
537 if (host->bus_hz % slot->clock)
538 /*
539 * move the + 1 after the divide to prevent
540 * over-clocking the card.
541 */
542 div = ((host->bus_hz / slot->clock) >> 1) + 1;
543 else
544 div = (host->bus_hz / slot->clock) >> 1;
545
546 dev_info(&slot->mmc->class_dev,
547 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
548 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
549 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
550
551 /* disable clock */
552 mci_writel(host, CLKENA, 0);
553 mci_writel(host, CLKSRC, 0);
554
555 /* inform CIU */
556 mci_send_cmd(slot,
557 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
558
559 /* set clock to desired speed */
560 mci_writel(host, CLKDIV, div);
561
562 /* inform CIU */
563 mci_send_cmd(slot,
564 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
565
566 /* enable clock */
aadb9f41
WN		 567 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
568 SDMMC_CLKEN_LOW_PWR);
f95f3850
WN		 569
570 /* inform CIU */
571 mci_send_cmd(slot,
572 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
573
574 host->current_speed = slot->clock;
575 }
576
577 /* Set the current slot bus width */
1d56c453 578 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 579}
580
581static void dw_mci_start_request(struct dw_mci *host,
582 struct dw_mci_slot *slot)
583{
584 struct mmc_request *mrq;
585 struct mmc_command *cmd;
586 struct mmc_data *data;
587 u32 cmdflags;
588
589 mrq = slot->mrq;
590 if (host->pdata->select_slot)
591 host->pdata->select_slot(slot->id);
592
593 /* Slot specific timing and width adjustment */
594 dw_mci_setup_bus(slot);
595
596 host->cur_slot = slot;
597 host->mrq = mrq;
598
599 host->pending_events = 0;
600 host->completed_events = 0;
601 host->data_status = 0;
602
603 data = mrq->data;
604 if (data) {
605 dw_mci_set_timeout(host);
606 mci_writel(host, BYTCNT, data->blksz*data->blocks);
607 mci_writel(host, BLKSIZ, data->blksz);
608 }
609
610 cmd = mrq->cmd;
611 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
612
613 /* this is the first command, send the initialization clock */
614 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
615 cmdflags |= SDMMC_CMD_INIT;
616
617 if (data) {
618 dw_mci_submit_data(host, data);
619 wmb();
620 }
621
622 dw_mci_start_command(host, cmd, cmdflags);
623
624 if (mrq->stop)
625 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
626}
627
628static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
629 struct mmc_request *mrq)
630{
631 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
632 host->state);
633
634 spin_lock_bh(&host->lock);
635 slot->mrq = mrq;
636
637 if (host->state == STATE_IDLE) {
638 host->state = STATE_SENDING_CMD;
639 dw_mci_start_request(host, slot);
640 } else {
641 list_add_tail(&slot->queue_node, &host->queue);
642 }
643
644 spin_unlock_bh(&host->lock);
645}
646
647static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
648{
649 struct dw_mci_slot *slot = mmc_priv(mmc);
650 struct dw_mci *host = slot->host;
651
652 WARN_ON(slot->mrq);
653
654 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
655 mrq->cmd->error = -ENOMEDIUM;
656 mmc_request_done(mmc, mrq);
657 return;
658 }
659
660 /* We don't support multiple blocks of weird lengths. */
661 dw_mci_queue_request(host, slot, mrq);
662}
663
664static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
665{
666 struct dw_mci_slot *slot = mmc_priv(mmc);
41babf75 667 u32 regs;
f95f3850
WN		 668
669 /* set default 1 bit mode */
670 slot->ctype = SDMMC_CTYPE_1BIT;
671
672 switch (ios->bus_width) {
673 case MMC_BUS_WIDTH_1:
674 slot->ctype = SDMMC_CTYPE_1BIT;
675 break;
676 case MMC_BUS_WIDTH_4:
677 slot->ctype = SDMMC_CTYPE_4BIT;
678 break;
c9b2a06f
JC		 679 case MMC_BUS_WIDTH_8:
680 slot->ctype = SDMMC_CTYPE_8BIT;
681 break;
f95f3850
WN		 682 }
683
41babf75
JC		 684 /* DDR mode set */
685 if (ios->ddr) {
686 regs = mci_readl(slot->host, UHS_REG);
687 regs |= (0x1 << slot->id) << 16;
688 mci_writel(slot->host, UHS_REG, regs);
689 }
690
f95f3850
WN		 691 if (ios->clock) {
692 /*
693 * Use mirror of ios->clock to prevent race with mmc
694 * core ios update when finding the minimum.
695 */
696 slot->clock = ios->clock;
697 }
698
699 switch (ios->power_mode) {
700 case MMC_POWER_UP:
701 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
702 break;
703 default:
704 break;
705 }
706}
707
708static int dw_mci_get_ro(struct mmc_host *mmc)
709{
710 int read_only;
711 struct dw_mci_slot *slot = mmc_priv(mmc);
712 struct dw_mci_board *brd = slot->host->pdata;
713
714 /* Use platform get_ro function, else try on board write protect */
715 if (brd->get_ro)
716 read_only = brd->get_ro(slot->id);
717 else
718 read_only =
719 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
720
721 dev_dbg(&mmc->class_dev, "card is %s\n",
722 read_only ? "read-only" : "read-write");
723
724 return read_only;
725}
726
727static int dw_mci_get_cd(struct mmc_host *mmc)
728{
729 int present;
730 struct dw_mci_slot *slot = mmc_priv(mmc);
731 struct dw_mci_board *brd = slot->host->pdata;
732
733 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 734 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
735 present = 1;
736 else if (brd->get_cd)
f95f3850
WN		 737 present = !brd->get_cd(slot->id);
738 else
739 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
740 == 0 ? 1 : 0;
741
742 if (present)
743 dev_dbg(&mmc->class_dev, "card is present\n");
744 else
745 dev_dbg(&mmc->class_dev, "card is not present\n");
746
747 return present;
748}
749
750static const struct mmc_host_ops dw_mci_ops = {
751 .request = dw_mci_request,
752 .set_ios = dw_mci_set_ios,
753 .get_ro = dw_mci_get_ro,
754 .get_cd = dw_mci_get_cd,
755};
756
757static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
758 __releases(&host->lock)
759 __acquires(&host->lock)
760{
761 struct dw_mci_slot *slot;
762 struct mmc_host *prev_mmc = host->cur_slot->mmc;
763
764 WARN_ON(host->cmd || host->data);
765
766 host->cur_slot->mrq = NULL;
767 host->mrq = NULL;
768 if (!list_empty(&host->queue)) {
769 slot = list_entry(host->queue.next,
770 struct dw_mci_slot, queue_node);
771 list_del(&slot->queue_node);
772 dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
773 mmc_hostname(slot->mmc));
774 host->state = STATE_SENDING_CMD;
775 dw_mci_start_request(host, slot);
776 } else {
777 dev_vdbg(&host->pdev->dev, "list empty\n");
778 host->state = STATE_IDLE;
779 }
780
781 spin_unlock(&host->lock);
782 mmc_request_done(prev_mmc, mrq);
783 spin_lock(&host->lock);
784}
785
786static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
787{
788 u32 status = host->cmd_status;
789
790 host->cmd_status = 0;
791
792 /* Read the response from the card (up to 16 bytes) */
793 if (cmd->flags & MMC_RSP_PRESENT) {
794 if (cmd->flags & MMC_RSP_136) {
795 cmd->resp[3] = mci_readl(host, RESP0);
796 cmd->resp[2] = mci_readl(host, RESP1);
797 cmd->resp[1] = mci_readl(host, RESP2);
798 cmd->resp[0] = mci_readl(host, RESP3);
799 } else {
800 cmd->resp[0] = mci_readl(host, RESP0);
801 cmd->resp[1] = 0;
802 cmd->resp[2] = 0;
803 cmd->resp[3] = 0;
804 }
805 }
806
807 if (status & SDMMC_INT_RTO)
808 cmd->error = -ETIMEDOUT;
809 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
810 cmd->error = -EILSEQ;
811 else if (status & SDMMC_INT_RESP_ERR)
812 cmd->error = -EIO;
813 else
814 cmd->error = 0;
815
816 if (cmd->error) {
817 /* newer ip versions need a delay between retries */
818 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
819 mdelay(20);
820
821 if (cmd->data) {
822 host->data = NULL;
823 dw_mci_stop_dma(host);
824 }
825 }
826}
827
828static void dw_mci_tasklet_func(unsigned long priv)
829{
830 struct dw_mci *host = (struct dw_mci *)priv;
831 struct mmc_data *data;
832 struct mmc_command *cmd;
833 enum dw_mci_state state;
834 enum dw_mci_state prev_state;
835 u32 status;
836
837 spin_lock(&host->lock);
838
839 state = host->state;
840 data = host->data;
841
842 do {
843 prev_state = state;
844
845 switch (state) {
846 case STATE_IDLE:
847 break;
848
849 case STATE_SENDING_CMD:
850 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
851 &host->pending_events))
852 break;
853
854 cmd = host->cmd;
855 host->cmd = NULL;
856 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
857 dw_mci_command_complete(host, host->mrq->cmd);
858 if (!host->mrq->data || cmd->error) {
859 dw_mci_request_end(host, host->mrq);
860 goto unlock;
861 }
862
863 prev_state = state = STATE_SENDING_DATA;
864 /* fall through */
865
866 case STATE_SENDING_DATA:
867 if (test_and_clear_bit(EVENT_DATA_ERROR,
868 &host->pending_events)) {
869 dw_mci_stop_dma(host);
870 if (data->stop)
871 send_stop_cmd(host, data);
872 state = STATE_DATA_ERROR;
873 break;
874 }
875
876 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
877 &host->pending_events))
878 break;
879
880 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
881 prev_state = state = STATE_DATA_BUSY;
882 /* fall through */
883
884 case STATE_DATA_BUSY:
885 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
886 &host->pending_events))
887 break;
888
889 host->data = NULL;
890 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
891 status = host->data_status;
892
893 if (status & DW_MCI_DATA_ERROR_FLAGS) {
894 if (status & SDMMC_INT_DTO) {
895 dev_err(&host->pdev->dev,
896 "data timeout error\n");
897 data->error = -ETIMEDOUT;
898 } else if (status & SDMMC_INT_DCRC) {
899 dev_err(&host->pdev->dev,
900 "data CRC error\n");
901 data->error = -EILSEQ;
902 } else {
903 dev_err(&host->pdev->dev,
904 "data FIFO error "
905 "(status=%08x)\n",
906 status);
907 data->error = -EIO;
908 }
909 } else {
910 data->bytes_xfered = data->blocks * data->blksz;
911 data->error = 0;
912 }
913
914 if (!data->stop) {
915 dw_mci_request_end(host, host->mrq);
916 goto unlock;
917 }
918
919 prev_state = state = STATE_SENDING_STOP;
920 if (!data->error)
921 send_stop_cmd(host, data);
922 /* fall through */
923
924 case STATE_SENDING_STOP:
925 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
926 &host->pending_events))
927 break;
928
929 host->cmd = NULL;
930 dw_mci_command_complete(host, host->mrq->stop);
931 dw_mci_request_end(host, host->mrq);
932 goto unlock;
933
934 case STATE_DATA_ERROR:
935 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
936 &host->pending_events))
937 break;
938
939 state = STATE_DATA_BUSY;
940 break;
941 }
942 } while (state != prev_state);
943
944 host->state = state;
945unlock:
946 spin_unlock(&host->lock);
947
948}
949
950static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
951{
952 u16 *pdata = (u16 *)buf;
953
954 WARN_ON(cnt % 2 != 0);
955
956 cnt = cnt >> 1;
957 while (cnt > 0) {
958 mci_writew(host, DATA, *pdata++);
959 cnt--;
960 }
961}
962
963static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
964{
965 u16 *pdata = (u16 *)buf;
966
967 WARN_ON(cnt % 2 != 0);
968
969 cnt = cnt >> 1;
970 while (cnt > 0) {
971 *pdata++ = mci_readw(host, DATA);
972 cnt--;
973 }
974}
975
976static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
977{
978 u32 *pdata = (u32 *)buf;
979
980 WARN_ON(cnt % 4 != 0);
981 WARN_ON((unsigned long)pdata & 0x3);
982
983 cnt = cnt >> 2;
984 while (cnt > 0) {
985 mci_writel(host, DATA, *pdata++);
986 cnt--;
987 }
988}
989
990static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
991{
992 u32 *pdata = (u32 *)buf;
993
994 WARN_ON(cnt % 4 != 0);
995 WARN_ON((unsigned long)pdata & 0x3);
996
997 cnt = cnt >> 2;
998 while (cnt > 0) {
999 *pdata++ = mci_readl(host, DATA);
1000 cnt--;
1001 }
1002}
1003
1004static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1005{
1006 u64 *pdata = (u64 *)buf;
1007
1008 WARN_ON(cnt % 8 != 0);
1009
1010 cnt = cnt >> 3;
1011 while (cnt > 0) {
1012 mci_writeq(host, DATA, *pdata++);
1013 cnt--;
1014 }
1015}
1016
1017static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1018{
1019 u64 *pdata = (u64 *)buf;
1020
1021 WARN_ON(cnt % 8 != 0);
1022
1023 cnt = cnt >> 3;
1024 while (cnt > 0) {
1025 *pdata++ = mci_readq(host, DATA);
1026 cnt--;
1027 }
1028}
1029
1030static void dw_mci_read_data_pio(struct dw_mci *host)
1031{
1032 struct scatterlist *sg = host->sg;
1033 void *buf = sg_virt(sg);
1034 unsigned int offset = host->pio_offset;
1035 struct mmc_data *data = host->data;
1036 int shift = host->data_shift;
1037 u32 status;
ba6a902d 1038 unsigned int nbytes = 0, len;
f95f3850
WN		 1039
1040 do {
1041 len = SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift;
f95f3850
WN		 1042 if (offset + len <= sg->length) {
1043 host->pull_data(host, (void *)(buf + offset), len);
1044
1045 offset += len;
1046 nbytes += len;
1047
1048 if (offset == sg->length) {
1049 flush_dcache_page(sg_page(sg));
1050 host->sg = sg = sg_next(sg);
1051 if (!sg)
1052 goto done;
1053
1054 offset = 0;
1055 buf = sg_virt(sg);
1056 }
1057 } else {
1058 unsigned int remaining = sg->length - offset;
1059 host->pull_data(host, (void *)(buf + offset),
1060 remaining);
1061 nbytes += remaining;
1062
1063 flush_dcache_page(sg_page(sg));
1064 host->sg = sg = sg_next(sg);
1065 if (!sg)
1066 goto done;
1067
1068 offset = len - remaining;
1069 buf = sg_virt(sg);
1070 host->pull_data(host, buf, offset);
1071 nbytes += offset;
1072 }
1073
1074 status = mci_readl(host, MINTSTS);
1075 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1076 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1077 host->data_status = status;
1078 data->bytes_xfered += nbytes;
1079 smp_wmb();
1080
1081 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1082
1083 tasklet_schedule(&host->tasklet);
1084 return;
1085 }
f95f3850
WN		 1086 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
1087 len = SDMMC_GET_FCNT(mci_readl(host, STATUS));
1088 host->pio_offset = offset;
1089 data->bytes_xfered += nbytes;
1090 return;
1091
1092done:
1093 data->bytes_xfered += nbytes;
1094 smp_wmb();
1095 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1096}
1097
1098static void dw_mci_write_data_pio(struct dw_mci *host)
1099{
1100 struct scatterlist *sg = host->sg;
1101 void *buf = sg_virt(sg);
1102 unsigned int offset = host->pio_offset;
1103 struct mmc_data *data = host->data;
1104 int shift = host->data_shift;
1105 u32 status;
1106 unsigned int nbytes = 0, len;
1107
1108 do {
1109 len = SDMMC_FIFO_SZ -
1110 (SDMMC_GET_FCNT(mci_readl(host, STATUS)) << shift);
1111 if (offset + len <= sg->length) {
1112 host->push_data(host, (void *)(buf + offset), len);
1113
1114 offset += len;
1115 nbytes += len;
1116 if (offset == sg->length) {
1117 host->sg = sg = sg_next(sg);
1118 if (!sg)
1119 goto done;
1120
1121 offset = 0;
1122 buf = sg_virt(sg);
1123 }
1124 } else {
1125 unsigned int remaining = sg->length - offset;
1126
1127 host->push_data(host, (void *)(buf + offset),
1128 remaining);
1129 nbytes += remaining;
1130
1131 host->sg = sg = sg_next(sg);
1132 if (!sg)
1133 goto done;
1134
1135 offset = len - remaining;
1136 buf = sg_virt(sg);
1137 host->push_data(host, (void *)buf, offset);
1138 nbytes += offset;
1139 }
1140
1141 status = mci_readl(host, MINTSTS);
1142 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1143 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1144 host->data_status = status;
1145 data->bytes_xfered += nbytes;
1146
1147 smp_wmb();
1148
1149 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1150
1151 tasklet_schedule(&host->tasklet);
1152 return;
1153 }
1154 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
1155
1156 host->pio_offset = offset;
1157 data->bytes_xfered += nbytes;
1158
1159 return;
1160
1161done:
1162 data->bytes_xfered += nbytes;
1163 smp_wmb();
1164 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1165}
1166
1167static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1168{
1169 if (!host->cmd_status)
1170 host->cmd_status = status;
1171
1172 smp_wmb();
1173
1174 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1175 tasklet_schedule(&host->tasklet);
1176}
1177
1178static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1179{
1180 struct dw_mci *host = dev_id;
1181 u32 status, pending;
1182 unsigned int pass_count = 0;
1183
1184 do {
1185 status = mci_readl(host, RINTSTS);
1186 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1187
1188 /*
1189 * DTO fix - version 2.10a and below, and only if internal DMA
1190 * is configured.
1191 */
1192 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1193 if (!pending &&
1194 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1195 pending |= SDMMC_INT_DATA_OVER;
1196 }
1197
1198 if (!pending)
1199 break;
1200
1201 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1202 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1203 host->cmd_status = status;
1204 smp_wmb();
1205 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1206 }
1207
1208 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1209 /* if there is an error report DATA_ERROR */
1210 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1211 host->data_status = status;
1212 smp_wmb();
1213 set_bit(EVENT_DATA_ERROR, &host->pending_events);
6e83e10d
SJ		 1214 if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1215 SDMMC_INT_SBE | SDMMC_INT_EBE)))
1216 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1217 }
1218
1219 if (pending & SDMMC_INT_DATA_OVER) {
1220 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1221 if (!host->data_status)
1222 host->data_status = status;
1223 smp_wmb();
1224 if (host->dir_status == DW_MCI_RECV_STATUS) {
1225 if (host->sg != NULL)
1226 dw_mci_read_data_pio(host);
1227 }
1228 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1229 tasklet_schedule(&host->tasklet);
1230 }
1231
1232 if (pending & SDMMC_INT_RXDR) {
1233 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 1234 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
f95f3850
WN		 1235 dw_mci_read_data_pio(host);
1236 }
1237
1238 if (pending & SDMMC_INT_TXDR) {
1239 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 1240 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 1241 dw_mci_write_data_pio(host);
1242 }
1243
1244 if (pending & SDMMC_INT_CMD_DONE) {
1245 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1246 dw_mci_cmd_interrupt(host, status);
1247 }
1248
1249 if (pending & SDMMC_INT_CD) {
1250 mci_writel(host, RINTSTS, SDMMC_INT_CD);
1251 tasklet_schedule(&host->card_tasklet);
1252 }
1253
1254 } while (pass_count++ < 5);
1255
1256#ifdef CONFIG_MMC_DW_IDMAC
1257 /* Handle DMA interrupts */
1258 pending = mci_readl(host, IDSTS);
1259 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1260 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1261 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1262 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1263 host->dma_ops->complete(host);
1264 }
1265#endif
1266
1267 return IRQ_HANDLED;
1268}
1269
1270static void dw_mci_tasklet_card(unsigned long data)
1271{
1272 struct dw_mci *host = (struct dw_mci *)data;
1273 int i;
1274
1275 for (i = 0; i < host->num_slots; i++) {
1276 struct dw_mci_slot *slot = host->slot[i];
1277 struct mmc_host *mmc = slot->mmc;
1278 struct mmc_request *mrq;
1279 int present;
1280 u32 ctrl;
1281
1282 present = dw_mci_get_cd(mmc);
1283 while (present != slot->last_detect_state) {
1284 spin_lock(&host->lock);
1285
1286 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1287 present ? "inserted" : "removed");
1288
1289 /* Card change detected */
1290 slot->last_detect_state = present;
1291
1292 /* Power up slot */
1293 if (present != 0) {
1294 if (host->pdata->setpower)
1295 host->pdata->setpower(slot->id,
1296 mmc->ocr_avail);
1297
1298 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1299 }
1300
1301 /* Clean up queue if present */
1302 mrq = slot->mrq;
1303 if (mrq) {
1304 if (mrq == host->mrq) {
1305 host->data = NULL;
1306 host->cmd = NULL;
1307
1308 switch (host->state) {
1309 case STATE_IDLE:
1310 break;
1311 case STATE_SENDING_CMD:
1312 mrq->cmd->error = -ENOMEDIUM;
1313 if (!mrq->data)
1314 break;
1315 /* fall through */
1316 case STATE_SENDING_DATA:
1317 mrq->data->error = -ENOMEDIUM;
1318 dw_mci_stop_dma(host);
1319 break;
1320 case STATE_DATA_BUSY:
1321 case STATE_DATA_ERROR:
1322 if (mrq->data->error == -EINPROGRESS)
1323 mrq->data->error = -ENOMEDIUM;
1324 if (!mrq->stop)
1325 break;
1326 /* fall through */
1327 case STATE_SENDING_STOP:
1328 mrq->stop->error = -ENOMEDIUM;
1329 break;
1330 }
1331
1332 dw_mci_request_end(host, mrq);
1333 } else {
1334 list_del(&slot->queue_node);
1335 mrq->cmd->error = -ENOMEDIUM;
1336 if (mrq->data)
1337 mrq->data->error = -ENOMEDIUM;
1338 if (mrq->stop)
1339 mrq->stop->error = -ENOMEDIUM;
1340
1341 spin_unlock(&host->lock);
1342 mmc_request_done(slot->mmc, mrq);
1343 spin_lock(&host->lock);
1344 }
1345 }
1346
1347 /* Power down slot */
1348 if (present == 0) {
1349 if (host->pdata->setpower)
1350 host->pdata->setpower(slot->id, 0);
1351 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1352
1353 /*
1354 * Clear down the FIFO - doing so generates a
1355 * block interrupt, hence setting the
1356 * scatter-gather pointer to NULL.
1357 */
1358 host->sg = NULL;
1359
1360 ctrl = mci_readl(host, CTRL);
1361 ctrl |= SDMMC_CTRL_FIFO_RESET;
1362 mci_writel(host, CTRL, ctrl);
1363
1364#ifdef CONFIG_MMC_DW_IDMAC
1365 ctrl = mci_readl(host, BMOD);
1366 ctrl |= 0x01; /* Software reset of DMA */
1367 mci_writel(host, BMOD, ctrl);
1368#endif
1369
1370 }
1371
1372 spin_unlock(&host->lock);
1373 present = dw_mci_get_cd(mmc);
1374 }
1375
1376 mmc_detect_change(slot->mmc,
1377 msecs_to_jiffies(host->pdata->detect_delay_ms));
1378 }
1379}
1380
1381static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1382{
1383 struct mmc_host *mmc;
1384 struct dw_mci_slot *slot;
1385
1386 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->pdev->dev);
1387 if (!mmc)
1388 return -ENOMEM;
1389
1390 slot = mmc_priv(mmc);
1391 slot->id = id;
1392 slot->mmc = mmc;
1393 slot->host = host;
1394
1395 mmc->ops = &dw_mci_ops;
1396 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1397 mmc->f_max = host->bus_hz;
1398
1399 if (host->pdata->get_ocr)
1400 mmc->ocr_avail = host->pdata->get_ocr(id);
1401 else
1402 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1403
1404 /*
1405 * Start with slot power disabled, it will be enabled when a card
1406 * is detected.
1407 */
1408 if (host->pdata->setpower)
1409 host->pdata->setpower(id, 0);
1410
fc3d7720
JC		 1411 if (host->pdata->caps)
1412 mmc->caps = host->pdata->caps;
1413 else
1414 mmc->caps = 0;
1415
f95f3850
WN		 1416 if (host->pdata->get_bus_wd)
1417 if (host->pdata->get_bus_wd(slot->id) >= 4)
1418 mmc->caps |= MMC_CAP_4_BIT_DATA;
1419
1420 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
1421 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1422
1423#ifdef CONFIG_MMC_DW_IDMAC
1424 mmc->max_segs = host->ring_size;
1425 mmc->max_blk_size = 65536;
1426 mmc->max_blk_count = host->ring_size;
1427 mmc->max_seg_size = 0x1000;
1428 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1429#else
1430 if (host->pdata->blk_settings) {
1431 mmc->max_segs = host->pdata->blk_settings->max_segs;
1432 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1433 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1434 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1435 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1436 } else {
1437 /* Useful defaults if platform data is unset. */
1438 mmc->max_segs = 64;
1439 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1440 mmc->max_blk_count = 512;
1441 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1442 mmc->max_seg_size = mmc->max_req_size;
1443 }
1444#endif /* CONFIG_MMC_DW_IDMAC */
1445
c07946a3
JC		 1446 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1447 if (IS_ERR(host->vmmc)) {
1448 printk(KERN_INFO "%s: no vmmc regulator found\n", mmc_hostname(mmc));
1449 host->vmmc = NULL;
1450 } else
1451 regulator_enable(host->vmmc);
1452
f95f3850
WN		 1453 if (dw_mci_get_cd(mmc))
1454 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1455 else
1456 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1457
1458 host->slot[id] = slot;
1459 mmc_add_host(mmc);
1460
1461#if defined(CONFIG_DEBUG_FS)
1462 dw_mci_init_debugfs(slot);
1463#endif
1464
1465 /* Card initially undetected */
1466 slot->last_detect_state = 0;
1467
dd6c4b98
WN		 1468 /*
1469 * Card may have been plugged in prior to boot so we
1470 * need to run the detect tasklet
1471 */
1472 tasklet_schedule(&host->card_tasklet);
1473
f95f3850
WN		 1474 return 0;
1475}
1476
1477static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1478{
1479 /* Shutdown detect IRQ */
1480 if (slot->host->pdata->exit)
1481 slot->host->pdata->exit(id);
1482
1483 /* Debugfs stuff is cleaned up by mmc core */
1484 mmc_remove_host(slot->mmc);
1485 slot->host->slot[id] = NULL;
1486 mmc_free_host(slot->mmc);
1487}
1488
1489static void dw_mci_init_dma(struct dw_mci *host)
1490{
1491 /* Alloc memory for sg translation */
1492 host->sg_cpu = dma_alloc_coherent(&host->pdev->dev, PAGE_SIZE,
1493 &host->sg_dma, GFP_KERNEL);
1494 if (!host->sg_cpu) {
1495 dev_err(&host->pdev->dev, "%s: could not alloc DMA memory\n",
1496 __func__);
1497 goto no_dma;
1498 }
1499
1500 /* Determine which DMA interface to use */
1501#ifdef CONFIG_MMC_DW_IDMAC
1502 host->dma_ops = &dw_mci_idmac_ops;
1503 dev_info(&host->pdev->dev, "Using internal DMA controller.\n");
1504#endif
1505
1506 if (!host->dma_ops)
1507 goto no_dma;
1508
1509 if (host->dma_ops->init) {
1510 if (host->dma_ops->init(host)) {
1511 dev_err(&host->pdev->dev, "%s: Unable to initialize "
1512 "DMA Controller.\n", __func__);
1513 goto no_dma;
1514 }
1515 } else {
1516 dev_err(&host->pdev->dev, "DMA initialization not found.\n");
1517 goto no_dma;
1518 }
1519
1520 host->use_dma = 1;
1521 return;
1522
1523no_dma:
1524 dev_info(&host->pdev->dev, "Using PIO mode.\n");
1525 host->use_dma = 0;
1526 return;
1527}
1528
1529static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1530{
1531 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1532 unsigned int ctrl;
1533
1534 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1535 SDMMC_CTRL_DMA_RESET));
1536
1537 /* wait till resets clear */
1538 do {
1539 ctrl = mci_readl(host, CTRL);
1540 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1541 SDMMC_CTRL_DMA_RESET)))
1542 return true;
1543 } while (time_before(jiffies, timeout));
1544
1545 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1546
1547 return false;
1548}
1549
1550static int dw_mci_probe(struct platform_device *pdev)
1551{
1552 struct dw_mci *host;
1553 struct resource *regs;
1554 struct dw_mci_board *pdata;
1555 int irq, ret, i, width;
1556 u32 fifo_size;
1557
1558 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1559 if (!regs)
1560 return -ENXIO;
1561
1562 irq = platform_get_irq(pdev, 0);
1563 if (irq < 0)
1564 return irq;
1565
1566 host = kzalloc(sizeof(struct dw_mci), GFP_KERNEL);
1567 if (!host)
1568 return -ENOMEM;
1569
1570 host->pdev = pdev;
1571 host->pdata = pdata = pdev->dev.platform_data;
1572 if (!pdata || !pdata->init) {
1573 dev_err(&pdev->dev,
1574 "Platform data must supply init function\n");
1575 ret = -ENODEV;
1576 goto err_freehost;
1577 }
1578
1579 if (!pdata->select_slot && pdata->num_slots > 1) {
1580 dev_err(&pdev->dev,
1581 "Platform data must supply select_slot function\n");
1582 ret = -ENODEV;
1583 goto err_freehost;
1584 }
1585
1586 if (!pdata->bus_hz) {
1587 dev_err(&pdev->dev,
1588 "Platform data must supply bus speed\n");
1589 ret = -ENODEV;
1590 goto err_freehost;
1591 }
1592
1593 host->bus_hz = pdata->bus_hz;
1594 host->quirks = pdata->quirks;
1595
1596 spin_lock_init(&host->lock);
1597 INIT_LIST_HEAD(&host->queue);
1598
1599 ret = -ENOMEM;
1600 host->regs = ioremap(regs->start, regs->end - regs->start + 1);
1601 if (!host->regs)
1602 goto err_freehost;
1603
1604 host->dma_ops = pdata->dma_ops;
1605 dw_mci_init_dma(host);
1606
1607 /*
1608 * Get the host data width - this assumes that HCON has been set with
1609 * the correct values.
1610 */
1611 i = (mci_readl(host, HCON) >> 7) & 0x7;
1612 if (!i) {
1613 host->push_data = dw_mci_push_data16;
1614 host->pull_data = dw_mci_pull_data16;
1615 width = 16;
1616 host->data_shift = 1;
1617 } else if (i == 2) {
1618 host->push_data = dw_mci_push_data64;
1619 host->pull_data = dw_mci_pull_data64;
1620 width = 64;
1621 host->data_shift = 3;
1622 } else {
1623 /* Check for a reserved value, and warn if it is */
1624 WARN((i != 1),
1625 "HCON reports a reserved host data width!\n"
1626 "Defaulting to 32-bit access.\n");
1627 host->push_data = dw_mci_push_data32;
1628 host->pull_data = dw_mci_pull_data32;
1629 width = 32;
1630 host->data_shift = 2;
1631 }
1632
1633 /* Reset all blocks */
1634 if (!mci_wait_reset(&pdev->dev, host)) {
1635 ret = -ENODEV;
1636 goto err_dmaunmap;
1637 }
1638
1639 /* Clear the interrupts for the host controller */
1640 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1641 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1642
1643 /* Put in max timeout */
1644 mci_writel(host, TMOUT, 0xFFFFFFFF);
1645
1646 /*
1647 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
1648 * Tx Mark = fifo_size / 2 DMA Size = 8
1649 */
1650 fifo_size = mci_readl(host, FIFOTH);
1651 fifo_size = (fifo_size >> 16) & 0x7ff;
e61cf118
JC		 1652 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
1653 ((fifo_size/2) << 0));
1654 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 1655
1656 /* disable clock to CIU */
1657 mci_writel(host, CLKENA, 0);
1658 mci_writel(host, CLKSRC, 0);
1659
1660 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1661 tasklet_init(&host->card_tasklet,
1662 dw_mci_tasklet_card, (unsigned long)host);
1663
1664 ret = request_irq(irq, dw_mci_interrupt, 0, "dw-mci", host);
1665 if (ret)
1666 goto err_dmaunmap;
1667
1668 platform_set_drvdata(pdev, host);
1669
1670 if (host->pdata->num_slots)
1671 host->num_slots = host->pdata->num_slots;
1672 else
1673 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
1674
1675 /* We need at least one slot to succeed */
1676 for (i = 0; i < host->num_slots; i++) {
1677 ret = dw_mci_init_slot(host, i);
1678 if (ret) {
1679 ret = -ENODEV;
1680 goto err_init_slot;
1681 }
1682 }
1683
1684 /*
1685 * Enable interrupts for command done, data over, data empty, card det,
1686 * receive ready and error such as transmit, receive timeout, crc error
1687 */
1688 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1689 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1690 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1691 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1692 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
1693
1694 dev_info(&pdev->dev, "DW MMC controller at irq %d, "
1695 "%d bit host data width\n", irq, width);
1696 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
1697 dev_info(&pdev->dev, "Internal DMAC interrupt fix enabled.\n");
1698
1699 return 0;
1700
1701err_init_slot:
1702 /* De-init any initialized slots */
1703 while (i > 0) {
1704 if (host->slot[i])
1705 dw_mci_cleanup_slot(host->slot[i], i);
1706 i--;
1707 }
1708 free_irq(irq, host);
1709
1710err_dmaunmap:
1711 if (host->use_dma && host->dma_ops->exit)
1712 host->dma_ops->exit(host);
1713 dma_free_coherent(&host->pdev->dev, PAGE_SIZE,
1714 host->sg_cpu, host->sg_dma);
1715 iounmap(host->regs);
1716
c07946a3
JC		 1717 if (host->vmmc) {
1718 regulator_disable(host->vmmc);
1719 regulator_put(host->vmmc);
1720 }
1721
1722
f95f3850
WN		 1723err_freehost:
1724 kfree(host);
1725 return ret;
1726}
1727
1728static int __exit dw_mci_remove(struct platform_device *pdev)
1729{
1730 struct dw_mci *host = platform_get_drvdata(pdev);
1731 int i;
1732
1733 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1734 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1735
1736 platform_set_drvdata(pdev, NULL);
1737
1738 for (i = 0; i < host->num_slots; i++) {
1739 dev_dbg(&pdev->dev, "remove slot %d\n", i);
1740 if (host->slot[i])
1741 dw_mci_cleanup_slot(host->slot[i], i);
1742 }
1743
1744 /* disable clock to CIU */
1745 mci_writel(host, CLKENA, 0);
1746 mci_writel(host, CLKSRC, 0);
1747
1748 free_irq(platform_get_irq(pdev, 0), host);
1749 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
1750
1751 if (host->use_dma && host->dma_ops->exit)
1752 host->dma_ops->exit(host);
1753
c07946a3
JC		 1754 if (host->vmmc) {
1755 regulator_disable(host->vmmc);
1756 regulator_put(host->vmmc);
1757 }
1758
f95f3850
WN		 1759 iounmap(host->regs);
1760
1761 kfree(host);
1762 return 0;
1763}
1764
1765#ifdef CONFIG_PM
1766/*
1767 * TODO: we should probably disable the clock to the card in the suspend path.
1768 */
1769static int dw_mci_suspend(struct platform_device *pdev, pm_message_t mesg)
1770{
1771 int i, ret;
1772 struct dw_mci *host = platform_get_drvdata(pdev);
1773
1774 for (i = 0; i < host->num_slots; i++) {
1775 struct dw_mci_slot *slot = host->slot[i];
1776 if (!slot)
1777 continue;
1778 ret = mmc_suspend_host(slot->mmc);
1779 if (ret < 0) {
1780 while (--i >= 0) {
1781 slot = host->slot[i];
1782 if (slot)
1783 mmc_resume_host(host->slot[i]->mmc);
1784 }
1785 return ret;
1786 }
1787 }
1788
c07946a3
JC		 1789 if (host->vmmc)
1790 regulator_disable(host->vmmc);
1791
f95f3850
WN		 1792 return 0;
1793}
1794
1795static int dw_mci_resume(struct platform_device *pdev)
1796{
1797 int i, ret;
1798 struct dw_mci *host = platform_get_drvdata(pdev);
1799
1d6c4e0a
JC		 1800 if (host->vmmc)
1801 regulator_enable(host->vmmc);
1802
e61cf118
JC		 1803 if (host->dma_ops->init)
1804 host->dma_ops->init(host);
1805
1806 if (!mci_wait_reset(&pdev->dev, host)) {
1807 ret = -ENODEV;
1808 return ret;
1809 }
1810
1811 /* Restore the old value at FIFOTH register */
1812 mci_writel(host, FIFOTH, host->fifoth_val);
1813
1814 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1815 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
1816 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
1817 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
1818 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
1819
f95f3850
WN		 1820 for (i = 0; i < host->num_slots; i++) {
1821 struct dw_mci_slot *slot = host->slot[i];
1822 if (!slot)
1823 continue;
1824 ret = mmc_resume_host(host->slot[i]->mmc);
1825 if (ret < 0)
1826 return ret;
1827 }
1828
1829 return 0;
1830}
1831#else
1832#define dw_mci_suspend NULL
1833#define dw_mci_resume NULL
1834#endif /* CONFIG_PM */
1835
1836static struct platform_driver dw_mci_driver = {
1837 .remove = __exit_p(dw_mci_remove),
1838 .suspend = dw_mci_suspend,
1839 .resume = dw_mci_resume,
1840 .driver = {
1841 .name = "dw_mmc",
1842 },
1843};
1844
1845static int __init dw_mci_init(void)
1846{
1847 return platform_driver_probe(&dw_mci_driver, dw_mci_probe);
1848}
1849
1850static void __exit dw_mci_exit(void)
1851{
1852 platform_driver_unregister(&dw_mci_driver);
1853}
1854
1855module_init(dw_mci_init);
1856module_exit(dw_mci_exit);
1857
1858MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
1859MODULE_AUTHOR("NXP Semiconductor VietNam");
1860MODULE_AUTHOR("Imagination Technologies Ltd");
1861MODULE_LICENSE("GPL v2");
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