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mmc: mediatek: add implement of ops->hw_reset()
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
b24c8b26 30#include <linux/mmc/card.h>
f95f3850
WN		 31#include <linux/mmc/host.h>
32#include <linux/mmc/mmc.h>
01730558 33#include <linux/mmc/sd.h>
90c2143a 34#include <linux/mmc/sdio.h>
f95f3850
WN		 35#include <linux/mmc/dw_mmc.h>
36#include <linux/bitops.h>
c07946a3 37#include <linux/regulator/consumer.h>
c91eab4b 38#include <linux/of.h>
55a6ceb2 39#include <linux/of_gpio.h>
bf626e55 40#include <linux/mmc/slot-gpio.h>
f95f3850
WN		 41
42#include "dw_mmc.h"
43
44/* Common flag combinations */
3f7eec62 45#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
f95f3850
WN		 46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52#define DW_MCI_SEND_STATUS 1
53#define DW_MCI_RECV_STATUS 2
54#define DW_MCI_DMA_THRESHOLD 16
55
1f44a2a5
SJ		 56#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
fc79a4d6
JS		 59#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
62 SDMMC_IDMAC_INT_TI)
63
69d99fdc
PT		 64struct idmac_desc_64addr {
65 u32 des0; /* Control Descriptor */
66
67 u32 des1; /* Reserved */
68
69 u32 des2; /*Buffer sizes */
70#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
6687c42f
BD		 71 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
72 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
69d99fdc
PT		 73
74 u32 des3; /* Reserved */
75
76 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
77 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
78
79 u32 des6; /* Lower 32-bits of Next Descriptor Address */
80 u32 des7; /* Upper 32-bits of Next Descriptor Address */
81};
82
f95f3850 83struct idmac_desc {
6687c42f 84 __le32 des0; /* Control Descriptor */
f95f3850
WN		 85#define IDMAC_DES0_DIC BIT(1)
86#define IDMAC_DES0_LD BIT(2)
87#define IDMAC_DES0_FD BIT(3)
88#define IDMAC_DES0_CH BIT(4)
89#define IDMAC_DES0_ER BIT(5)
90#define IDMAC_DES0_CES BIT(30)
91#define IDMAC_DES0_OWN BIT(31)
92
6687c42f 93 __le32 des1; /* Buffer sizes */
f95f3850 94#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 95 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850 96
6687c42f 97 __le32 des2; /* buffer 1 physical address */
f95f3850 98
6687c42f 99 __le32 des3; /* buffer 2 physical address */
f95f3850 100};
5959b32e
AB		 101
102/* Each descriptor can transfer up to 4KB of data in chained mode */
103#define DW_MCI_DESC_DATA_LENGTH 0x1000
f95f3850 104
3a33a94c 105static bool dw_mci_reset(struct dw_mci *host);
536f6b91 106static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
0bdbd0e8 107static int dw_mci_card_busy(struct mmc_host *mmc);
31bff450 108
f95f3850
WN		 109#if defined(CONFIG_DEBUG_FS)
110static int dw_mci_req_show(struct seq_file *s, void *v)
111{
112 struct dw_mci_slot *slot = s->private;
113 struct mmc_request *mrq;
114 struct mmc_command *cmd;
115 struct mmc_command *stop;
116 struct mmc_data *data;
117
118 /* Make sure we get a consistent snapshot */
119 spin_lock_bh(&slot->host->lock);
120 mrq = slot->mrq;
121
122 if (mrq) {
123 cmd = mrq->cmd;
124 data = mrq->data;
125 stop = mrq->stop;
126
127 if (cmd)
128 seq_printf(s,
129 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
130 cmd->opcode, cmd->arg, cmd->flags,
131 cmd->resp[0], cmd->resp[1], cmd->resp[2],
132 cmd->resp[2], cmd->error);
133 if (data)
134 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
135 data->bytes_xfered, data->blocks,
136 data->blksz, data->flags, data->error);
137 if (stop)
138 seq_printf(s,
139 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
140 stop->opcode, stop->arg, stop->flags,
141 stop->resp[0], stop->resp[1], stop->resp[2],
142 stop->resp[2], stop->error);
143 }
144
145 spin_unlock_bh(&slot->host->lock);
146
147 return 0;
148}
149
150static int dw_mci_req_open(struct inode *inode, struct file *file)
151{
152 return single_open(file, dw_mci_req_show, inode->i_private);
153}
154
155static const struct file_operations dw_mci_req_fops = {
156 .owner = THIS_MODULE,
157 .open = dw_mci_req_open,
158 .read = seq_read,
159 .llseek = seq_lseek,
160 .release = single_release,
161};
162
163static int dw_mci_regs_show(struct seq_file *s, void *v)
164{
165 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
166 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
167 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
168 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
169 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
170 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
171
172 return 0;
173}
174
175static int dw_mci_regs_open(struct inode *inode, struct file *file)
176{
177 return single_open(file, dw_mci_regs_show, inode->i_private);
178}
179
180static const struct file_operations dw_mci_regs_fops = {
181 .owner = THIS_MODULE,
182 .open = dw_mci_regs_open,
183 .read = seq_read,
184 .llseek = seq_lseek,
185 .release = single_release,
186};
187
188static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
189{
190 struct mmc_host *mmc = slot->mmc;
191 struct dw_mci *host = slot->host;
192 struct dentry *root;
193 struct dentry *node;
194
195 root = mmc->debugfs_root;
196 if (!root)
197 return;
198
199 node = debugfs_create_file("regs", S_IRUSR, root, host,
200 &dw_mci_regs_fops);
201 if (!node)
202 goto err;
203
204 node = debugfs_create_file("req", S_IRUSR, root, slot,
205 &dw_mci_req_fops);
206 if (!node)
207 goto err;
208
209 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
210 if (!node)
211 goto err;
212
213 node = debugfs_create_x32("pending_events", S_IRUSR, root,
214 (u32 *)&host->pending_events);
215 if (!node)
216 goto err;
217
218 node = debugfs_create_x32("completed_events", S_IRUSR, root,
219 (u32 *)&host->completed_events);
220 if (!node)
221 goto err;
222
223 return;
224
225err:
226 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
227}
228#endif /* defined(CONFIG_DEBUG_FS) */
229
01730558
DA		 230static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
231
f95f3850
WN		 232static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
233{
234 struct mmc_data *data;
800d78bf 235 struct dw_mci_slot *slot = mmc_priv(mmc);
01730558 236 struct dw_mci *host = slot->host;
e95baf13 237 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
f95f3850 238 u32 cmdr;
f95f3850 239
0e3a22c0 240 cmd->error = -EINPROGRESS;
f95f3850
WN		 241 cmdr = cmd->opcode;
242
90c2143a
SJ		 243 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
244 cmd->opcode == MMC_GO_IDLE_STATE ||
245 cmd->opcode == MMC_GO_INACTIVE_STATE ||
246 (cmd->opcode == SD_IO_RW_DIRECT &&
247 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
f95f3850 248 cmdr |= SDMMC_CMD_STOP;
4a1b27ad
JC		 249 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
250 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
f95f3850 251
01730558
DA		 252 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
253 u32 clk_en_a;
254
255 /* Special bit makes CMD11 not die */
256 cmdr |= SDMMC_CMD_VOLT_SWITCH;
257
258 /* Change state to continue to handle CMD11 weirdness */
259 WARN_ON(slot->host->state != STATE_SENDING_CMD);
260 slot->host->state = STATE_SENDING_CMD11;
261
262 /*
263 * We need to disable low power mode (automatic clock stop)
264 * while doing voltage switch so we don't confuse the card,
265 * since stopping the clock is a specific part of the UHS
266 * voltage change dance.
267 *
268 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
269 * unconditionally turned back on in dw_mci_setup_bus() if it's
270 * ever called with a non-zero clock. That shouldn't happen
271 * until the voltage change is all done.
272 */
273 clk_en_a = mci_readl(host, CLKENA);
274 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
275 mci_writel(host, CLKENA, clk_en_a);
276 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
277 SDMMC_CMD_PRV_DAT_WAIT, 0);
278 }
279
f95f3850
WN		 280 if (cmd->flags & MMC_RSP_PRESENT) {
281 /* We expect a response, so set this bit */
282 cmdr |= SDMMC_CMD_RESP_EXP;
283 if (cmd->flags & MMC_RSP_136)
284 cmdr |= SDMMC_CMD_RESP_LONG;
285 }
286
287 if (cmd->flags & MMC_RSP_CRC)
288 cmdr |= SDMMC_CMD_RESP_CRC;
289
290 data = cmd->data;
291 if (data) {
292 cmdr |= SDMMC_CMD_DAT_EXP;
293 if (data->flags & MMC_DATA_STREAM)
294 cmdr |= SDMMC_CMD_STRM_MODE;
295 if (data->flags & MMC_DATA_WRITE)
296 cmdr |= SDMMC_CMD_DAT_WR;
297 }
298
cb27a843
JH		 299 if (drv_data && drv_data->prepare_command)
300 drv_data->prepare_command(slot->host, &cmdr);
800d78bf 301
f95f3850
WN		 302 return cmdr;
303}
304
90c2143a
SJ		 305static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
306{
307 struct mmc_command *stop;
308 u32 cmdr;
309
310 if (!cmd->data)
311 return 0;
312
313 stop = &host->stop_abort;
314 cmdr = cmd->opcode;
315 memset(stop, 0, sizeof(struct mmc_command));
316
317 if (cmdr == MMC_READ_SINGLE_BLOCK ||
318 cmdr == MMC_READ_MULTIPLE_BLOCK ||
319 cmdr == MMC_WRITE_BLOCK ||
6c2c6506
UH		 320 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
321 cmdr == MMC_SEND_TUNING_BLOCK ||
322 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
90c2143a
SJ		 323 stop->opcode = MMC_STOP_TRANSMISSION;
324 stop->arg = 0;
325 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
326 } else if (cmdr == SD_IO_RW_EXTENDED) {
327 stop->opcode = SD_IO_RW_DIRECT;
328 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
329 ((cmd->arg >> 28) & 0x7);
330 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
331 } else {
332 return 0;
333 }
334
335 cmdr = stop->opcode | SDMMC_CMD_STOP |
336 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
337
338 return cmdr;
339}
340
0bdbd0e8
DA		 341static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
342{
343 unsigned long timeout = jiffies + msecs_to_jiffies(500);
344
345 /*
346 * Databook says that before issuing a new data transfer command
347 * we need to check to see if the card is busy. Data transfer commands
348 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
349 *
350 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
351 * expected.
352 */
353 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
354 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
355 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
356 if (time_after(jiffies, timeout)) {
357 /* Command will fail; we'll pass error then */
358 dev_err(host->dev, "Busy; trying anyway\n");
359 break;
360 }
361 udelay(10);
362 }
363 }
364}
365
f95f3850
WN		 366static void dw_mci_start_command(struct dw_mci *host,
367 struct mmc_command *cmd, u32 cmd_flags)
368{
369 host->cmd = cmd;
4a90920c 370 dev_vdbg(host->dev,
f95f3850
WN		 371 "start command: ARGR=0x%08x CMDR=0x%08x\n",
372 cmd->arg, cmd_flags);
373
374 mci_writel(host, CMDARG, cmd->arg);
0e3a22c0 375 wmb(); /* drain writebuffer */
0bdbd0e8 376 dw_mci_wait_while_busy(host, cmd_flags);
f95f3850
WN		 377
378 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
379}
380
90c2143a 381static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
f95f3850 382{
90c2143a 383 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
0e3a22c0 384
90c2143a 385 dw_mci_start_command(host, stop, host->stop_cmdr);
f95f3850
WN		 386}
387
388/* DMA interface functions */
389static void dw_mci_stop_dma(struct dw_mci *host)
390{
03e8cb53 391 if (host->using_dma) {
f95f3850
WN		 392 host->dma_ops->stop(host);
393 host->dma_ops->cleanup(host);
f95f3850 394 }
aa50f259
SJ		 395
396 /* Data transfer was stopped by the interrupt handler */
397 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
f95f3850
WN		 398}
399
9aa51408
SJ		 400static int dw_mci_get_dma_dir(struct mmc_data *data)
401{
402 if (data->flags & MMC_DATA_WRITE)
403 return DMA_TO_DEVICE;
404 else
405 return DMA_FROM_DEVICE;
406}
407
f95f3850
WN		 408static void dw_mci_dma_cleanup(struct dw_mci *host)
409{
410 struct mmc_data *data = host->data;
411
412 if (data)
9aa51408 413 if (!data->host_cookie)
4a90920c 414 dma_unmap_sg(host->dev,
9aa51408
SJ		 415 data->sg,
416 data->sg_len,
417 dw_mci_get_dma_dir(data));
f95f3850
WN		 418}
419
5ce9d961
SJ		 420static void dw_mci_idmac_reset(struct dw_mci *host)
421{
422 u32 bmod = mci_readl(host, BMOD);
423 /* Software reset of DMA */
424 bmod |= SDMMC_IDMAC_SWRESET;
425 mci_writel(host, BMOD, bmod);
426}
427
f95f3850
WN		 428static void dw_mci_idmac_stop_dma(struct dw_mci *host)
429{
430 u32 temp;
431
432 /* Disable and reset the IDMAC interface */
433 temp = mci_readl(host, CTRL);
434 temp &= ~SDMMC_CTRL_USE_IDMAC;
435 temp |= SDMMC_CTRL_DMA_RESET;
436 mci_writel(host, CTRL, temp);
437
438 /* Stop the IDMAC running */
439 temp = mci_readl(host, BMOD);
a5289a43 440 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
5ce9d961 441 temp |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 442 mci_writel(host, BMOD, temp);
443}
444
3fc7eaef 445static void dw_mci_dmac_complete_dma(void *arg)
f95f3850 446{
3fc7eaef 447 struct dw_mci *host = arg;
f95f3850
WN		 448 struct mmc_data *data = host->data;
449
4a90920c 450 dev_vdbg(host->dev, "DMA complete\n");
f95f3850 451
3fc7eaef
SL		 452 if ((host->use_dma == TRANS_MODE_EDMAC) &&
453 data && (data->flags & MMC_DATA_READ))
454 /* Invalidate cache after read */
455 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
456 data->sg,
457 data->sg_len,
458 DMA_FROM_DEVICE);
459
f95f3850
WN		 460 host->dma_ops->cleanup(host);
461
462 /*
463 * If the card was removed, data will be NULL. No point in trying to
464 * send the stop command or waiting for NBUSY in this case.
465 */
466 if (data) {
467 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
468 tasklet_schedule(&host->tasklet);
469 }
470}
471
472static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
473 unsigned int sg_len)
474{
5959b32e 475 unsigned int desc_len;
f95f3850 476 int i;
0e3a22c0 477
69d99fdc 478 if (host->dma_64bit_address == 1) {
5959b32e
AB		 479 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
480
481 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 482
5959b32e 483 for (i = 0; i < sg_len; i++) {
69d99fdc 484 unsigned int length = sg_dma_len(&data->sg[i]);
0e3a22c0 485
69d99fdc 486 u64 mem_addr = sg_dma_address(&data->sg[i]);
f95f3850 487
5959b32e
AB		 488 for ( ; length ; desc++) {
489 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
490 length : DW_MCI_DESC_DATA_LENGTH;
491
492 length -= desc_len;
493
494 /*
495 * Set the OWN bit and disable interrupts
496 * for this descriptor
497 */
498 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
499 IDMAC_DES0_CH;
500
501 /* Buffer length */
502 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
503
504 /* Physical address to DMA to/from */
505 desc->des4 = mem_addr & 0xffffffff;
506 desc->des5 = mem_addr >> 32;
507
508 /* Update physical address for the next desc */
509 mem_addr += desc_len;
510
511 /* Save pointer to the last descriptor */
512 desc_last = desc;
513 }
69d99fdc 514 }
f95f3850 515
69d99fdc 516 /* Set first descriptor */
5959b32e 517 desc_first->des0 |= IDMAC_DES0_FD;
f95f3850 518
69d99fdc 519 /* Set last descriptor */
5959b32e
AB		 520 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
521 desc_last->des0 |= IDMAC_DES0_LD;
f95f3850 522
69d99fdc 523 } else {
5959b32e
AB		 524 struct idmac_desc *desc_first, *desc_last, *desc;
525
526 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 527
5959b32e 528 for (i = 0; i < sg_len; i++) {
69d99fdc 529 unsigned int length = sg_dma_len(&data->sg[i]);
0e3a22c0 530
69d99fdc
PT		 531 u32 mem_addr = sg_dma_address(&data->sg[i]);
532
5959b32e
AB		 533 for ( ; length ; desc++) {
534 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
535 length : DW_MCI_DESC_DATA_LENGTH;
536
537 length -= desc_len;
538
539 /*
540 * Set the OWN bit and disable interrupts
541 * for this descriptor
542 */
543 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
544 IDMAC_DES0_DIC |
545 IDMAC_DES0_CH);
546
547 /* Buffer length */
548 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
f95f3850 549
5959b32e
AB		 550 /* Physical address to DMA to/from */
551 desc->des2 = cpu_to_le32(mem_addr);
552
553 /* Update physical address for the next desc */
554 mem_addr += desc_len;
555
556 /* Save pointer to the last descriptor */
557 desc_last = desc;
558 }
69d99fdc
PT		 559 }
560
561 /* Set first descriptor */
5959b32e 562 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
f95f3850 563
69d99fdc 564 /* Set last descriptor */
5959b32e
AB		 565 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
566 IDMAC_DES0_DIC));
567 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
69d99fdc 568 }
f95f3850 569
0e3a22c0 570 wmb(); /* drain writebuffer */
f95f3850
WN		 571}
572
3fc7eaef 573static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
f95f3850
WN		 574{
575 u32 temp;
576
577 dw_mci_translate_sglist(host, host->data, sg_len);
578
536f6b91
SR		 579 /* Make sure to reset DMA in case we did PIO before this */
580 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
581 dw_mci_idmac_reset(host);
582
f95f3850
WN		 583 /* Select IDMAC interface */
584 temp = mci_readl(host, CTRL);
585 temp |= SDMMC_CTRL_USE_IDMAC;
586 mci_writel(host, CTRL, temp);
587
0e3a22c0 588 /* drain writebuffer */
f95f3850
WN		 589 wmb();
590
591 /* Enable the IDMAC */
592 temp = mci_readl(host, BMOD);
a5289a43 593 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 594 mci_writel(host, BMOD, temp);
595
596 /* Start it running */
597 mci_writel(host, PLDMND, 1);
3fc7eaef
SL		 598
599 return 0;
f95f3850
WN		 600}
601
602static int dw_mci_idmac_init(struct dw_mci *host)
603{
897b69e7 604 int i;
f95f3850 605
69d99fdc
PT		 606 if (host->dma_64bit_address == 1) {
607 struct idmac_desc_64addr *p;
608 /* Number of descriptors in the ring buffer */
609 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
610
611 /* Forward link the descriptor list */
612 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
613 i++, p++) {
614 p->des6 = (host->sg_dma +
615 (sizeof(struct idmac_desc_64addr) *
616 (i + 1))) & 0xffffffff;
617
618 p->des7 = (u64)(host->sg_dma +
619 (sizeof(struct idmac_desc_64addr) *
620 (i + 1))) >> 32;
621 /* Initialize reserved and buffer size fields to "0" */
622 p->des1 = 0;
623 p->des2 = 0;
624 p->des3 = 0;
625 }
f95f3850 626
69d99fdc
PT		 627 /* Set the last descriptor as the end-of-ring descriptor */
628 p->des6 = host->sg_dma & 0xffffffff;
629 p->des7 = (u64)host->sg_dma >> 32;
630 p->des0 = IDMAC_DES0_ER;
f95f3850 631
69d99fdc
PT		 632 } else {
633 struct idmac_desc *p;
634 /* Number of descriptors in the ring buffer */
635 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
636
637 /* Forward link the descriptor list */
0e3a22c0
SL		 638 for (i = 0, p = host->sg_cpu;
639 i < host->ring_size - 1;
640 i++, p++) {
6687c42f
BD		 641 p->des3 = cpu_to_le32(host->sg_dma +
642 (sizeof(struct idmac_desc) * (i + 1)));
4b244724
ZG		 643 p->des1 = 0;
644 }
69d99fdc
PT		 645
646 /* Set the last descriptor as the end-of-ring descriptor */
6687c42f
BD		 647 p->des3 = cpu_to_le32(host->sg_dma);
648 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
69d99fdc 649 }
f95f3850 650
5ce9d961 651 dw_mci_idmac_reset(host);
141a712a 652
69d99fdc
PT		 653 if (host->dma_64bit_address == 1) {
654 /* Mask out interrupts - get Tx & Rx complete only */
655 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
656 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
657 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
658
659 /* Set the descriptor base address */
660 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
661 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
662
663 } else {
664 /* Mask out interrupts - get Tx & Rx complete only */
665 mci_writel(host, IDSTS, IDMAC_INT_CLR);
666 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
667 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
668
669 /* Set the descriptor base address */
670 mci_writel(host, DBADDR, host->sg_dma);
671 }
f95f3850 672
f95f3850
WN		 673 return 0;
674}
675
8e2b36ea 676static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 677 .init = dw_mci_idmac_init,
678 .start = dw_mci_idmac_start_dma,
679 .stop = dw_mci_idmac_stop_dma,
3fc7eaef
SL		 680 .complete = dw_mci_dmac_complete_dma,
681 .cleanup = dw_mci_dma_cleanup,
682};
683
684static void dw_mci_edmac_stop_dma(struct dw_mci *host)
685{
686 dmaengine_terminate_all(host->dms->ch);
687}
688
689static int dw_mci_edmac_start_dma(struct dw_mci *host,
690 unsigned int sg_len)
691{
692 struct dma_slave_config cfg;
693 struct dma_async_tx_descriptor *desc = NULL;
694 struct scatterlist *sgl = host->data->sg;
695 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
696 u32 sg_elems = host->data->sg_len;
697 u32 fifoth_val;
698 u32 fifo_offset = host->fifo_reg - host->regs;
699 int ret = 0;
700
701 /* Set external dma config: burst size, burst width */
702 cfg.dst_addr = (dma_addr_t)(host->phy_regs + fifo_offset);
703 cfg.src_addr = cfg.dst_addr;
704 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
705 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
706
707 /* Match burst msize with external dma config */
708 fifoth_val = mci_readl(host, FIFOTH);
709 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
710 cfg.src_maxburst = cfg.dst_maxburst;
711
712 if (host->data->flags & MMC_DATA_WRITE)
713 cfg.direction = DMA_MEM_TO_DEV;
714 else
715 cfg.direction = DMA_DEV_TO_MEM;
716
717 ret = dmaengine_slave_config(host->dms->ch, &cfg);
718 if (ret) {
719 dev_err(host->dev, "Failed to config edmac.\n");
720 return -EBUSY;
721 }
722
723 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
724 sg_len, cfg.direction,
725 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
726 if (!desc) {
727 dev_err(host->dev, "Can't prepare slave sg.\n");
728 return -EBUSY;
729 }
730
731 /* Set dw_mci_dmac_complete_dma as callback */
732 desc->callback = dw_mci_dmac_complete_dma;
733 desc->callback_param = (void *)host;
734 dmaengine_submit(desc);
735
736 /* Flush cache before write */
737 if (host->data->flags & MMC_DATA_WRITE)
738 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
739 sg_elems, DMA_TO_DEVICE);
740
741 dma_async_issue_pending(host->dms->ch);
742
743 return 0;
744}
745
746static int dw_mci_edmac_init(struct dw_mci *host)
747{
748 /* Request external dma channel */
749 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
750 if (!host->dms)
751 return -ENOMEM;
752
753 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
754 if (!host->dms->ch) {
755 dev_err(host->dev,
756 "Failed to get external DMA channel %d\n",
757 host->dms->ch->chan_id);
758 kfree(host->dms);
759 host->dms = NULL;
760 return -ENXIO;
761 }
762
763 return 0;
764}
765
766static void dw_mci_edmac_exit(struct dw_mci *host)
767{
768 if (host->dms) {
769 if (host->dms->ch) {
770 dma_release_channel(host->dms->ch);
771 host->dms->ch = NULL;
772 }
773 kfree(host->dms);
774 host->dms = NULL;
775 }
776}
777
778static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
779 .init = dw_mci_edmac_init,
780 .exit = dw_mci_edmac_exit,
781 .start = dw_mci_edmac_start_dma,
782 .stop = dw_mci_edmac_stop_dma,
783 .complete = dw_mci_dmac_complete_dma,
885c3e80
SJ		 784 .cleanup = dw_mci_dma_cleanup,
785};
885c3e80 786
9aa51408
SJ		 787static int dw_mci_pre_dma_transfer(struct dw_mci *host,
788 struct mmc_data *data,
789 bool next)
f95f3850
WN		 790{
791 struct scatterlist *sg;
9aa51408 792 unsigned int i, sg_len;
03e8cb53 793
9aa51408
SJ		 794 if (!next && data->host_cookie)
795 return data->host_cookie;
f95f3850
WN		 796
797 /*
798 * We don't do DMA on "complex" transfers, i.e. with
799 * non-word-aligned buffers or lengths. Also, we don't bother
800 * with all the DMA setup overhead for short transfers.
801 */
802 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
803 return -EINVAL;
9aa51408 804
f95f3850
WN		 805 if (data->blksz & 3)
806 return -EINVAL;
807
808 for_each_sg(data->sg, sg, data->sg_len, i) {
809 if (sg->offset & 3 || sg->length & 3)
810 return -EINVAL;
811 }
812
4a90920c 813 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 814 data->sg,
815 data->sg_len,
816 dw_mci_get_dma_dir(data));
817 if (sg_len == 0)
818 return -EINVAL;
03e8cb53 819
9aa51408
SJ		 820 if (next)
821 data->host_cookie = sg_len;
f95f3850 822
9aa51408
SJ		 823 return sg_len;
824}
825
9aa51408
SJ		 826static void dw_mci_pre_req(struct mmc_host *mmc,
827 struct mmc_request *mrq,
828 bool is_first_req)
829{
830 struct dw_mci_slot *slot = mmc_priv(mmc);
831 struct mmc_data *data = mrq->data;
832
833 if (!slot->host->use_dma || !data)
834 return;
835
836 if (data->host_cookie) {
837 data->host_cookie = 0;
838 return;
839 }
840
841 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
842 data->host_cookie = 0;
843}
844
845static void dw_mci_post_req(struct mmc_host *mmc,
846 struct mmc_request *mrq,
847 int err)
848{
849 struct dw_mci_slot *slot = mmc_priv(mmc);
850 struct mmc_data *data = mrq->data;
851
852 if (!slot->host->use_dma || !data)
853 return;
854
855 if (data->host_cookie)
4a90920c 856 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 857 data->sg,
858 data->sg_len,
859 dw_mci_get_dma_dir(data));
860 data->host_cookie = 0;
861}
862
52426899
SJ		 863static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
864{
52426899
SJ		 865 unsigned int blksz = data->blksz;
866 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
867 u32 fifo_width = 1 << host->data_shift;
868 u32 blksz_depth = blksz / fifo_width, fifoth_val;
869 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
0e3a22c0 870 int idx = ARRAY_SIZE(mszs) - 1;
52426899 871
3fc7eaef
SL		 872 /* pio should ship this scenario */
873 if (!host->use_dma)
874 return;
875
52426899
SJ		 876 tx_wmark = (host->fifo_depth) / 2;
877 tx_wmark_invers = host->fifo_depth - tx_wmark;
878
879 /*
880 * MSIZE is '1',
881 * if blksz is not a multiple of the FIFO width
882 */
883 if (blksz % fifo_width) {
884 msize = 0;
885 rx_wmark = 1;
886 goto done;
887 }
888
889 do {
890 if (!((blksz_depth % mszs[idx]) ||
891 (tx_wmark_invers % mszs[idx]))) {
892 msize = idx;
893 rx_wmark = mszs[idx] - 1;
894 break;
895 }
896 } while (--idx > 0);
897 /*
898 * If idx is '0', it won't be tried
899 * Thus, initial values are uesed
900 */
901done:
902 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
903 mci_writel(host, FIFOTH, fifoth_val);
52426899
SJ		 904}
905
f1d2736c
SJ		 906static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
907{
908 unsigned int blksz = data->blksz;
909 u32 blksz_depth, fifo_depth;
910 u16 thld_size;
911
912 WARN_ON(!(data->flags & MMC_DATA_READ));
913
66dfd101
JH		 914 /*
915 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
916 * in the FIFO region, so we really shouldn't access it).
917 */
918 if (host->verid < DW_MMC_240A)
919 return;
920
f1d2736c 921 if (host->timing != MMC_TIMING_MMC_HS200 &&
488b8d63 922 host->timing != MMC_TIMING_MMC_HS400 &&
f1d2736c
SJ		 923 host->timing != MMC_TIMING_UHS_SDR104)
924 goto disable;
925
926 blksz_depth = blksz / (1 << host->data_shift);
927 fifo_depth = host->fifo_depth;
928
929 if (blksz_depth > fifo_depth)
930 goto disable;
931
932 /*
933 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
934 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
935 * Currently just choose blksz.
936 */
937 thld_size = blksz;
938 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
939 return;
940
941disable:
942 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
943}
944
9aa51408
SJ		 945static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
946{
f8c58c11 947 unsigned long irqflags;
9aa51408
SJ		 948 int sg_len;
949 u32 temp;
950
951 host->using_dma = 0;
952
953 /* If we don't have a channel, we can't do DMA */
954 if (!host->use_dma)
955 return -ENODEV;
956
957 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 958 if (sg_len < 0) {
959 host->dma_ops->stop(host);
9aa51408 960 return sg_len;
a99aa9b9 961 }
9aa51408
SJ		 962
963 host->using_dma = 1;
f95f3850 964
3fc7eaef
SL		 965 if (host->use_dma == TRANS_MODE_IDMAC)
966 dev_vdbg(host->dev,
967 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
968 (unsigned long)host->sg_cpu,
969 (unsigned long)host->sg_dma,
970 sg_len);
f95f3850 971
52426899
SJ		 972 /*
973 * Decide the MSIZE and RX/TX Watermark.
974 * If current block size is same with previous size,
975 * no need to update fifoth.
976 */
977 if (host->prev_blksz != data->blksz)
978 dw_mci_adjust_fifoth(host, data);
979
f95f3850
WN		 980 /* Enable the DMA interface */
981 temp = mci_readl(host, CTRL);
982 temp |= SDMMC_CTRL_DMA_ENABLE;
983 mci_writel(host, CTRL, temp);
984
985 /* Disable RX/TX IRQs, let DMA handle it */
f8c58c11 986 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 987 temp = mci_readl(host, INTMASK);
988 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
989 mci_writel(host, INTMASK, temp);
f8c58c11 990 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850 991
3fc7eaef
SL		 992 if (host->dma_ops->start(host, sg_len)) {
993 /* We can't do DMA */
994 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
995 return -ENODEV;
996 }
f95f3850
WN		 997
998 return 0;
999}
1000
1001static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1002{
f8c58c11 1003 unsigned long irqflags;
0e3a22c0 1004 int flags = SG_MITER_ATOMIC;
f95f3850
WN		 1005 u32 temp;
1006
1007 data->error = -EINPROGRESS;
1008
1009 WARN_ON(host->data);
1010 host->sg = NULL;
1011 host->data = data;
1012
f1d2736c 1013 if (data->flags & MMC_DATA_READ) {
55c5efbc 1014 host->dir_status = DW_MCI_RECV_STATUS;
f1d2736c
SJ		 1015 dw_mci_ctrl_rd_thld(host, data);
1016 } else {
55c5efbc 1017 host->dir_status = DW_MCI_SEND_STATUS;
f1d2736c 1018 }
55c5efbc 1019
f95f3850 1020 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 1021 if (host->data->flags & MMC_DATA_READ)
1022 flags |= SG_MITER_TO_SG;
1023 else
1024 flags |= SG_MITER_FROM_SG;
1025
1026 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 1027 host->sg = data->sg;
34b664a2
JH		 1028 host->part_buf_start = 0;
1029 host->part_buf_count = 0;
f95f3850 1030
b40af3aa 1031 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f8c58c11
DA		 1032
1033 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1034 temp = mci_readl(host, INTMASK);
1035 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1036 mci_writel(host, INTMASK, temp);
f8c58c11 1037 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 1038
1039 temp = mci_readl(host, CTRL);
1040 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1041 mci_writel(host, CTRL, temp);
52426899
SJ		 1042
1043 /*
1044 * Use the initial fifoth_val for PIO mode.
1045 * If next issued data may be transfered by DMA mode,
1046 * prev_blksz should be invalidated.
1047 */
1048 mci_writel(host, FIFOTH, host->fifoth_val);
1049 host->prev_blksz = 0;
1050 } else {
1051 /*
1052 * Keep the current block size.
1053 * It will be used to decide whether to update
1054 * fifoth register next time.
1055 */
1056 host->prev_blksz = data->blksz;
f95f3850
WN		 1057 }
1058}
1059
1060static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1061{
1062 struct dw_mci *host = slot->host;
1063 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1064 unsigned int cmd_status = 0;
1065
1066 mci_writel(host, CMDARG, arg);
0e3a22c0 1067 wmb(); /* drain writebuffer */
0bdbd0e8 1068 dw_mci_wait_while_busy(host, cmd);
f95f3850
WN		 1069 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1070
1071 while (time_before(jiffies, timeout)) {
1072 cmd_status = mci_readl(host, CMD);
1073 if (!(cmd_status & SDMMC_CMD_START))
1074 return;
1075 }
1076 dev_err(&slot->mmc->class_dev,
1077 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1078 cmd, arg, cmd_status);
1079}
1080
ab269128 1081static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 1082{
1083 struct dw_mci *host = slot->host;
fdf492a1 1084 unsigned int clock = slot->clock;
f95f3850 1085 u32 div;
9623b5b9 1086 u32 clk_en_a;
01730558
DA		 1087 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1088
1089 /* We must continue to set bit 28 in CMD until the change is complete */
1090 if (host->state == STATE_WAITING_CMD11_DONE)
1091 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
f95f3850 1092
fdf492a1
DA		 1093 if (!clock) {
1094 mci_writel(host, CLKENA, 0);
01730558 1095 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
fdf492a1
DA		 1096 } else if (clock != host->current_speed || force_clkinit) {
1097 div = host->bus_hz / clock;
1098 if (host->bus_hz % clock && host->bus_hz > clock)
f95f3850
WN		 1099 /*
1100 * move the + 1 after the divide to prevent
1101 * over-clocking the card.
1102 */
e419990b
SJ		 1103 div += 1;
1104
fdf492a1 1105 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850 1106
fdf492a1
DA		 1107 if ((clock << div) != slot->__clk_old || force_clkinit)
1108 dev_info(&slot->mmc->class_dev,
1109 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1110 slot->id, host->bus_hz, clock,
1111 div ? ((host->bus_hz / div) >> 1) :
1112 host->bus_hz, div);
f95f3850
WN		 1113
1114 /* disable clock */
1115 mci_writel(host, CLKENA, 0);
1116 mci_writel(host, CLKSRC, 0);
1117
1118 /* inform CIU */
01730558 1119 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850
WN		 1120
1121 /* set clock to desired speed */
1122 mci_writel(host, CLKDIV, div);
1123
1124 /* inform CIU */
01730558 1125 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1126
9623b5b9
DA		 1127 /* enable clock; only low power if no SDIO */
1128 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
b24c8b26 1129 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
9623b5b9
DA		 1130 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1131 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 1132
1133 /* inform CIU */
01730558 1134 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1135
fdf492a1
DA		 1136 /* keep the clock with reflecting clock dividor */
1137 slot->__clk_old = clock << div;
f95f3850
WN		 1138 }
1139
fdf492a1
DA		 1140 host->current_speed = clock;
1141
f95f3850 1142 /* Set the current slot bus width */
1d56c453 1143 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 1144}
1145
053b3ce6
SJ		 1146static void __dw_mci_start_request(struct dw_mci *host,
1147 struct dw_mci_slot *slot,
1148 struct mmc_command *cmd)
f95f3850
WN		 1149{
1150 struct mmc_request *mrq;
f95f3850
WN		 1151 struct mmc_data *data;
1152 u32 cmdflags;
1153
1154 mrq = slot->mrq;
f95f3850 1155
f95f3850
WN		 1156 host->cur_slot = slot;
1157 host->mrq = mrq;
1158
1159 host->pending_events = 0;
1160 host->completed_events = 0;
e352c813 1161 host->cmd_status = 0;
f95f3850 1162 host->data_status = 0;
e352c813 1163 host->dir_status = 0;
f95f3850 1164
053b3ce6 1165 data = cmd->data;
f95f3850 1166 if (data) {
f16afa88 1167 mci_writel(host, TMOUT, 0xFFFFFFFF);
f95f3850
WN		 1168 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1169 mci_writel(host, BLKSIZ, data->blksz);
1170 }
1171
f95f3850
WN		 1172 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1173
1174 /* this is the first command, send the initialization clock */
1175 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1176 cmdflags |= SDMMC_CMD_INIT;
1177
1178 if (data) {
1179 dw_mci_submit_data(host, data);
0e3a22c0 1180 wmb(); /* drain writebuffer */
f95f3850
WN		 1181 }
1182
1183 dw_mci_start_command(host, cmd, cmdflags);
1184
5c935165 1185 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
49ba0302
DA		 1186 unsigned long irqflags;
1187
5c935165 1188 /*
8886a6fd
DA		 1189 * Databook says to fail after 2ms w/ no response, but evidence
1190 * shows that sometimes the cmd11 interrupt takes over 130ms.
1191 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1192 * is just about to roll over.
49ba0302
DA		 1193 *
1194 * We do this whole thing under spinlock and only if the
1195 * command hasn't already completed (indicating the the irq
1196 * already ran so we don't want the timeout).
5c935165 1197 */
49ba0302
DA		 1198 spin_lock_irqsave(&host->irq_lock, irqflags);
1199 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1200 mod_timer(&host->cmd11_timer,
1201 jiffies + msecs_to_jiffies(500) + 1);
1202 spin_unlock_irqrestore(&host->irq_lock, irqflags);
5c935165
DA		 1203 }
1204
f95f3850
WN		 1205 if (mrq->stop)
1206 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
90c2143a
SJ		 1207 else
1208 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
f95f3850
WN		 1209}
1210
053b3ce6
SJ		 1211static void dw_mci_start_request(struct dw_mci *host,
1212 struct dw_mci_slot *slot)
1213{
1214 struct mmc_request *mrq = slot->mrq;
1215 struct mmc_command *cmd;
1216
1217 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1218 __dw_mci_start_request(host, slot, cmd);
1219}
1220
7456caae 1221/* must be called with host->lock held */
f95f3850
WN		 1222static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1223 struct mmc_request *mrq)
1224{
1225 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1226 host->state);
1227
f95f3850
WN		 1228 slot->mrq = mrq;
1229
01730558
DA		 1230 if (host->state == STATE_WAITING_CMD11_DONE) {
1231 dev_warn(&slot->mmc->class_dev,
1232 "Voltage change didn't complete\n");
1233 /*
1234 * this case isn't expected to happen, so we can
1235 * either crash here or just try to continue on
1236 * in the closest possible state
1237 */
1238 host->state = STATE_IDLE;
1239 }
1240
f95f3850
WN		 1241 if (host->state == STATE_IDLE) {
1242 host->state = STATE_SENDING_CMD;
1243 dw_mci_start_request(host, slot);
1244 } else {
1245 list_add_tail(&slot->queue_node, &host->queue);
1246 }
f95f3850
WN		 1247}
1248
1249static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1250{
1251 struct dw_mci_slot *slot = mmc_priv(mmc);
1252 struct dw_mci *host = slot->host;
1253
1254 WARN_ON(slot->mrq);
1255
7456caae
JH		 1256 /*
1257 * The check for card presence and queueing of the request must be
1258 * atomic, otherwise the card could be removed in between and the
1259 * request wouldn't fail until another card was inserted.
1260 */
1261 spin_lock_bh(&host->lock);
1262
f95f3850 1263 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 1264 spin_unlock_bh(&host->lock);
f95f3850
WN		 1265 mrq->cmd->error = -ENOMEDIUM;
1266 mmc_request_done(mmc, mrq);
1267 return;
1268 }
1269
f95f3850 1270 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 1271
1272 spin_unlock_bh(&host->lock);
f95f3850
WN		 1273}
1274
1275static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1276{
1277 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 1278 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 1279 u32 regs;
51da2240 1280 int ret;
f95f3850 1281
f95f3850 1282 switch (ios->bus_width) {
f95f3850
WN		 1283 case MMC_BUS_WIDTH_4:
1284 slot->ctype = SDMMC_CTYPE_4BIT;
1285 break;
c9b2a06f
JC		 1286 case MMC_BUS_WIDTH_8:
1287 slot->ctype = SDMMC_CTYPE_8BIT;
1288 break;
b2f7cb45
JC		 1289 default:
1290 /* set default 1 bit mode */
1291 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 1292 }
1293
3f514291
SJ		 1294 regs = mci_readl(slot->host, UHS_REG);
1295
41babf75 1296 /* DDR mode set */
80113132
SJ		 1297 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1298 ios->timing == MMC_TIMING_MMC_HS400)
c69042a5 1299 regs |= ((0x1 << slot->id) << 16);
3f514291 1300 else
c69042a5 1301 regs &= ~((0x1 << slot->id) << 16);
3f514291
SJ		 1302
1303 mci_writel(slot->host, UHS_REG, regs);
f1d2736c 1304 slot->host->timing = ios->timing;
41babf75 1305
fdf492a1
DA		 1306 /*
1307 * Use mirror of ios->clock to prevent race with mmc
1308 * core ios update when finding the minimum.
1309 */
1310 slot->clock = ios->clock;
f95f3850 1311
cb27a843
JH		 1312 if (drv_data && drv_data->set_ios)
1313 drv_data->set_ios(slot->host, ios);
800d78bf 1314
f95f3850
WN		 1315 switch (ios->power_mode) {
1316 case MMC_POWER_UP:
51da2240
YC		 1317 if (!IS_ERR(mmc->supply.vmmc)) {
1318 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1319 ios->vdd);
1320 if (ret) {
1321 dev_err(slot->host->dev,
1322 "failed to enable vmmc regulator\n");
1323 /*return, if failed turn on vmmc*/
1324 return;
1325 }
1326 }
29d0d161
DA		 1327 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1328 regs = mci_readl(slot->host, PWREN);
1329 regs |= (1 << slot->id);
1330 mci_writel(slot->host, PWREN, regs);
1331 break;
1332 case MMC_POWER_ON:
d1f1dd86
DA		 1333 if (!slot->host->vqmmc_enabled) {
1334 if (!IS_ERR(mmc->supply.vqmmc)) {
1335 ret = regulator_enable(mmc->supply.vqmmc);
1336 if (ret < 0)
1337 dev_err(slot->host->dev,
1338 "failed to enable vqmmc\n");
1339 else
1340 slot->host->vqmmc_enabled = true;
1341
1342 } else {
1343 /* Keep track so we don't reset again */
51da2240 1344 slot->host->vqmmc_enabled = true;
d1f1dd86
DA		 1345 }
1346
1347 /* Reset our state machine after powering on */
1348 dw_mci_ctrl_reset(slot->host,
1349 SDMMC_CTRL_ALL_RESET_FLAGS);
51da2240 1350 }
655babbd
DA		 1351
1352 /* Adjust clock / bus width after power is up */
1353 dw_mci_setup_bus(slot, false);
1354
e6f34e2f
JH		 1355 break;
1356 case MMC_POWER_OFF:
655babbd
DA		 1357 /* Turn clock off before power goes down */
1358 dw_mci_setup_bus(slot, false);
1359
51da2240
YC		 1360 if (!IS_ERR(mmc->supply.vmmc))
1361 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1362
d1f1dd86 1363 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
51da2240 1364 regulator_disable(mmc->supply.vqmmc);
d1f1dd86 1365 slot->host->vqmmc_enabled = false;
51da2240 1366
4366dcc5
JC		 1367 regs = mci_readl(slot->host, PWREN);
1368 regs &= ~(1 << slot->id);
1369 mci_writel(slot->host, PWREN, regs);
f95f3850
WN		 1370 break;
1371 default:
1372 break;
1373 }
655babbd
DA		 1374
1375 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1376 slot->host->state = STATE_IDLE;
f95f3850
WN		 1377}
1378
01730558
DA		 1379static int dw_mci_card_busy(struct mmc_host *mmc)
1380{
1381 struct dw_mci_slot *slot = mmc_priv(mmc);
1382 u32 status;
1383
1384 /*
1385 * Check the busy bit which is low when DAT[3:0]
1386 * (the data lines) are 0000
1387 */
1388 status = mci_readl(slot->host, STATUS);
1389
1390 return !!(status & SDMMC_STATUS_BUSY);
1391}
1392
1393static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1394{
1395 struct dw_mci_slot *slot = mmc_priv(mmc);
1396 struct dw_mci *host = slot->host;
8f7849c4 1397 const struct dw_mci_drv_data *drv_data = host->drv_data;
01730558
DA		 1398 u32 uhs;
1399 u32 v18 = SDMMC_UHS_18V << slot->id;
01730558
DA		 1400 int ret;
1401
8f7849c4
ZG		 1402 if (drv_data && drv_data->switch_voltage)
1403 return drv_data->switch_voltage(mmc, ios);
1404
01730558
DA		 1405 /*
1406 * Program the voltage. Note that some instances of dw_mmc may use
1407 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1408 * does no harm but you need to set the regulator directly. Try both.
1409 */
1410 uhs = mci_readl(host, UHS_REG);
e0848f5d 1411 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
01730558 1412 uhs &= ~v18;
e0848f5d 1413 else
01730558 1414 uhs |= v18;
e0848f5d 1415
01730558 1416 if (!IS_ERR(mmc->supply.vqmmc)) {
e0848f5d 1417 ret = mmc_regulator_set_vqmmc(mmc, ios);
01730558
DA		 1418
1419 if (ret) {
b19caf37 1420 dev_dbg(&mmc->class_dev,
e0848f5d
DA		 1421 "Regulator set error %d - %s V\n",
1422 ret, uhs & v18 ? "1.8" : "3.3");
01730558
DA		 1423 return ret;
1424 }
1425 }
1426 mci_writel(host, UHS_REG, uhs);
1427
1428 return 0;
1429}
1430
f95f3850
WN		 1431static int dw_mci_get_ro(struct mmc_host *mmc)
1432{
1433 int read_only;
1434 struct dw_mci_slot *slot = mmc_priv(mmc);
9795a846 1435 int gpio_ro = mmc_gpio_get_ro(mmc);
f95f3850
WN		 1436
1437 /* Use platform get_ro function, else try on board write protect */
eff8f2f5 1438 if (!IS_ERR_VALUE(gpio_ro))
9795a846 1439 read_only = gpio_ro;
f95f3850
WN		 1440 else
1441 read_only =
1442 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1443
1444 dev_dbg(&mmc->class_dev, "card is %s\n",
1445 read_only ? "read-only" : "read-write");
1446
1447 return read_only;
1448}
1449
1450static int dw_mci_get_cd(struct mmc_host *mmc)
1451{
1452 int present;
1453 struct dw_mci_slot *slot = mmc_priv(mmc);
1454 struct dw_mci_board *brd = slot->host->pdata;
7cf347bd
ZG		 1455 struct dw_mci *host = slot->host;
1456 int gpio_cd = mmc_gpio_get_cd(mmc);
f95f3850
WN		 1457
1458 /* Use platform get_cd function, else try onboard card detect */
4de3bf66
ZG		 1459 if ((brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION) ||
1460 (mmc->caps & MMC_CAP_NONREMOVABLE))
fc3d7720 1461 present = 1;
bf626e55 1462 else if (!IS_ERR_VALUE(gpio_cd))
7cf347bd 1463 present = gpio_cd;
f95f3850
WN		 1464 else
1465 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1466 == 0 ? 1 : 0;
1467
7cf347bd 1468 spin_lock_bh(&host->lock);
bf626e55
ZG		 1469 if (present) {
1470 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1471 dev_dbg(&mmc->class_dev, "card is present\n");
bf626e55
ZG		 1472 } else {
1473 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1474 dev_dbg(&mmc->class_dev, "card is not present\n");
bf626e55 1475 }
7cf347bd 1476 spin_unlock_bh(&host->lock);
f95f3850
WN		 1477
1478 return present;
1479}
1480
b24c8b26 1481static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
9623b5b9 1482{
b24c8b26 1483 struct dw_mci_slot *slot = mmc_priv(mmc);
9623b5b9 1484 struct dw_mci *host = slot->host;
9623b5b9 1485
b24c8b26
DA		 1486 /*
1487 * Low power mode will stop the card clock when idle. According to the
1488 * description of the CLKENA register we should disable low power mode
1489 * for SDIO cards if we need SDIO interrupts to work.
1490 */
1491 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1492 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1493 u32 clk_en_a_old;
1494 u32 clk_en_a;
9623b5b9 1495
b24c8b26
DA		 1496 clk_en_a_old = mci_readl(host, CLKENA);
1497
1498 if (card->type == MMC_TYPE_SDIO ||
1499 card->type == MMC_TYPE_SD_COMBO) {
1500 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1501 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1502 } else {
1503 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1504 clk_en_a = clk_en_a_old | clken_low_pwr;
1505 }
1506
1507 if (clk_en_a != clk_en_a_old) {
1508 mci_writel(host, CLKENA, clk_en_a);
1509 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1510 SDMMC_CMD_PRV_DAT_WAIT, 0);
1511 }
9623b5b9
DA		 1512 }
1513}
1514
1a5c8e1f
SH		 1515static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1516{
1517 struct dw_mci_slot *slot = mmc_priv(mmc);
1518 struct dw_mci *host = slot->host;
f8c58c11 1519 unsigned long irqflags;
1a5c8e1f
SH		 1520 u32 int_mask;
1521
f8c58c11
DA		 1522 spin_lock_irqsave(&host->irq_lock, irqflags);
1523
1a5c8e1f
SH		 1524 /* Enable/disable Slot Specific SDIO interrupt */
1525 int_mask = mci_readl(host, INTMASK);
b24c8b26
DA		 1526 if (enb)
1527 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1528 else
1529 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1530 mci_writel(host, INTMASK, int_mask);
f8c58c11
DA		 1531
1532 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1a5c8e1f
SH		 1533}
1534
0976f16d
SJ		 1535static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1536{
1537 struct dw_mci_slot *slot = mmc_priv(mmc);
1538 struct dw_mci *host = slot->host;
1539 const struct dw_mci_drv_data *drv_data = host->drv_data;
0e3a22c0 1540 int err = -EINVAL;
0976f16d 1541
0976f16d 1542 if (drv_data && drv_data->execute_tuning)
6c2c6506 1543 err = drv_data->execute_tuning(slot);
0976f16d
SJ		 1544 return err;
1545}
1546
0e3a22c0
SL		 1547static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1548 struct mmc_ios *ios)
80113132
SJ		 1549{
1550 struct dw_mci_slot *slot = mmc_priv(mmc);
1551 struct dw_mci *host = slot->host;
1552 const struct dw_mci_drv_data *drv_data = host->drv_data;
1553
1554 if (drv_data && drv_data->prepare_hs400_tuning)
1555 return drv_data->prepare_hs400_tuning(host, ios);
1556
1557 return 0;
1558}
1559
f95f3850 1560static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 1561 .request = dw_mci_request,
9aa51408
SJ		 1562 .pre_req = dw_mci_pre_req,
1563 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 1564 .set_ios = dw_mci_set_ios,
1565 .get_ro = dw_mci_get_ro,
1566 .get_cd = dw_mci_get_cd,
1567 .enable_sdio_irq = dw_mci_enable_sdio_irq,
0976f16d 1568 .execute_tuning = dw_mci_execute_tuning,
01730558
DA		 1569 .card_busy = dw_mci_card_busy,
1570 .start_signal_voltage_switch = dw_mci_switch_voltage,
b24c8b26 1571 .init_card = dw_mci_init_card,
80113132 1572 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
f95f3850
WN		 1573};
1574
1575static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1576 __releases(&host->lock)
1577 __acquires(&host->lock)
1578{
1579 struct dw_mci_slot *slot;
1580 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1581
1582 WARN_ON(host->cmd || host->data);
1583
1584 host->cur_slot->mrq = NULL;
1585 host->mrq = NULL;
1586 if (!list_empty(&host->queue)) {
1587 slot = list_entry(host->queue.next,
1588 struct dw_mci_slot, queue_node);
1589 list_del(&slot->queue_node);
4a90920c 1590 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 1591 mmc_hostname(slot->mmc));
1592 host->state = STATE_SENDING_CMD;
1593 dw_mci_start_request(host, slot);
1594 } else {
4a90920c 1595 dev_vdbg(host->dev, "list empty\n");
01730558
DA		 1596
1597 if (host->state == STATE_SENDING_CMD11)
1598 host->state = STATE_WAITING_CMD11_DONE;
1599 else
1600 host->state = STATE_IDLE;
f95f3850
WN		 1601 }
1602
1603 spin_unlock(&host->lock);
1604 mmc_request_done(prev_mmc, mrq);
1605 spin_lock(&host->lock);
1606}
1607
e352c813 1608static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
f95f3850
WN		 1609{
1610 u32 status = host->cmd_status;
1611
1612 host->cmd_status = 0;
1613
1614 /* Read the response from the card (up to 16 bytes) */
1615 if (cmd->flags & MMC_RSP_PRESENT) {
1616 if (cmd->flags & MMC_RSP_136) {
1617 cmd->resp[3] = mci_readl(host, RESP0);
1618 cmd->resp[2] = mci_readl(host, RESP1);
1619 cmd->resp[1] = mci_readl(host, RESP2);
1620 cmd->resp[0] = mci_readl(host, RESP3);
1621 } else {
1622 cmd->resp[0] = mci_readl(host, RESP0);
1623 cmd->resp[1] = 0;
1624 cmd->resp[2] = 0;
1625 cmd->resp[3] = 0;
1626 }
1627 }
1628
1629 if (status & SDMMC_INT_RTO)
1630 cmd->error = -ETIMEDOUT;
1631 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1632 cmd->error = -EILSEQ;
1633 else if (status & SDMMC_INT_RESP_ERR)
1634 cmd->error = -EIO;
1635 else
1636 cmd->error = 0;
1637
1638 if (cmd->error) {
1639 /* newer ip versions need a delay between retries */
1640 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
1641 mdelay(20);
f95f3850 1642 }
e352c813
SJ		 1643
1644 return cmd->error;
1645}
1646
1647static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1648{
31bff450 1649 u32 status = host->data_status;
e352c813
SJ		 1650
1651 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1652 if (status & SDMMC_INT_DRTO) {
1653 data->error = -ETIMEDOUT;
1654 } else if (status & SDMMC_INT_DCRC) {
1655 data->error = -EILSEQ;
1656 } else if (status & SDMMC_INT_EBE) {
1657 if (host->dir_status ==
1658 DW_MCI_SEND_STATUS) {
1659 /*
1660 * No data CRC status was returned.
1661 * The number of bytes transferred
1662 * will be exaggerated in PIO mode.
1663 */
1664 data->bytes_xfered = 0;
1665 data->error = -ETIMEDOUT;
1666 } else if (host->dir_status ==
1667 DW_MCI_RECV_STATUS) {
1668 data->error = -EIO;
1669 }
1670 } else {
1671 /* SDMMC_INT_SBE is included */
1672 data->error = -EIO;
1673 }
1674
e6cc0123 1675 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
e352c813
SJ		 1676
1677 /*
1678 * After an error, there may be data lingering
31bff450 1679 * in the FIFO
e352c813 1680 */
3a33a94c 1681 dw_mci_reset(host);
e352c813
SJ		 1682 } else {
1683 data->bytes_xfered = data->blocks * data->blksz;
1684 data->error = 0;
1685 }
1686
1687 return data->error;
f95f3850
WN		 1688}
1689
57e10486
AK		 1690static void dw_mci_set_drto(struct dw_mci *host)
1691{
1692 unsigned int drto_clks;
1693 unsigned int drto_ms;
1694
1695 drto_clks = mci_readl(host, TMOUT) >> 8;
1696 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1697
1698 /* add a bit spare time */
1699 drto_ms += 10;
1700
1701 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1702}
1703
f95f3850
WN		 1704static void dw_mci_tasklet_func(unsigned long priv)
1705{
1706 struct dw_mci *host = (struct dw_mci *)priv;
1707 struct mmc_data *data;
1708 struct mmc_command *cmd;
e352c813 1709 struct mmc_request *mrq;
f95f3850
WN		 1710 enum dw_mci_state state;
1711 enum dw_mci_state prev_state;
e352c813 1712 unsigned int err;
f95f3850
WN		 1713
1714 spin_lock(&host->lock);
1715
1716 state = host->state;
1717 data = host->data;
e352c813 1718 mrq = host->mrq;
f95f3850
WN		 1719
1720 do {
1721 prev_state = state;
1722
1723 switch (state) {
1724 case STATE_IDLE:
01730558 1725 case STATE_WAITING_CMD11_DONE:
f95f3850
WN		 1726 break;
1727
01730558 1728 case STATE_SENDING_CMD11:
f95f3850
WN		 1729 case STATE_SENDING_CMD:
1730 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1731 &host->pending_events))
1732 break;
1733
1734 cmd = host->cmd;
1735 host->cmd = NULL;
1736 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
e352c813
SJ		 1737 err = dw_mci_command_complete(host, cmd);
1738 if (cmd == mrq->sbc && !err) {
053b3ce6
SJ		 1739 prev_state = state = STATE_SENDING_CMD;
1740 __dw_mci_start_request(host, host->cur_slot,
e352c813 1741 mrq->cmd);
053b3ce6
SJ		 1742 goto unlock;
1743 }
1744
e352c813 1745 if (cmd->data && err) {
71abb133 1746 dw_mci_stop_dma(host);
90c2143a
SJ		 1747 send_stop_abort(host, data);
1748 state = STATE_SENDING_STOP;
1749 break;
71abb133
SJ		 1750 }
1751
e352c813
SJ		 1752 if (!cmd->data || err) {
1753 dw_mci_request_end(host, mrq);
f95f3850
WN		 1754 goto unlock;
1755 }
1756
1757 prev_state = state = STATE_SENDING_DATA;
1758 /* fall through */
1759
1760 case STATE_SENDING_DATA:
2aa35465
DA		 1761 /*
1762 * We could get a data error and never a transfer
1763 * complete so we'd better check for it here.
1764 *
1765 * Note that we don't really care if we also got a
1766 * transfer complete; stopping the DMA and sending an
1767 * abort won't hurt.
1768 */
f95f3850
WN		 1769 if (test_and_clear_bit(EVENT_DATA_ERROR,
1770 &host->pending_events)) {
1771 dw_mci_stop_dma(host);
bdb9a90b 1772 if (data->stop ||
1773 !(host->data_status & (SDMMC_INT_DRTO |
1774 SDMMC_INT_EBE)))
1775 send_stop_abort(host, data);
f95f3850
WN		 1776 state = STATE_DATA_ERROR;
1777 break;
1778 }
1779
1780 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
57e10486
AK		 1781 &host->pending_events)) {
1782 /*
1783 * If all data-related interrupts don't come
1784 * within the given time in reading data state.
1785 */
1786 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1787 (host->dir_status == DW_MCI_RECV_STATUS))
1788 dw_mci_set_drto(host);
f95f3850 1789 break;
57e10486 1790 }
f95f3850
WN		 1791
1792 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2aa35465
DA		 1793
1794 /*
1795 * Handle an EVENT_DATA_ERROR that might have shown up
1796 * before the transfer completed. This might not have
1797 * been caught by the check above because the interrupt
1798 * could have gone off between the previous check and
1799 * the check for transfer complete.
1800 *
1801 * Technically this ought not be needed assuming we
1802 * get a DATA_COMPLETE eventually (we'll notice the
1803 * error and end the request), but it shouldn't hurt.
1804 *
1805 * This has the advantage of sending the stop command.
1806 */
1807 if (test_and_clear_bit(EVENT_DATA_ERROR,
1808 &host->pending_events)) {
1809 dw_mci_stop_dma(host);
bdb9a90b 1810 if (data->stop ||
1811 !(host->data_status & (SDMMC_INT_DRTO |
1812 SDMMC_INT_EBE)))
1813 send_stop_abort(host, data);
2aa35465
DA		 1814 state = STATE_DATA_ERROR;
1815 break;
1816 }
f95f3850 1817 prev_state = state = STATE_DATA_BUSY;
2aa35465 1818
f95f3850
WN		 1819 /* fall through */
1820
1821 case STATE_DATA_BUSY:
1822 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
57e10486
AK		 1823 &host->pending_events)) {
1824 /*
1825 * If data error interrupt comes but data over
1826 * interrupt doesn't come within the given time.
1827 * in reading data state.
1828 */
1829 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1830 (host->dir_status == DW_MCI_RECV_STATUS))
1831 dw_mci_set_drto(host);
f95f3850 1832 break;
57e10486 1833 }
f95f3850
WN		 1834
1835 host->data = NULL;
1836 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
e352c813
SJ		 1837 err = dw_mci_data_complete(host, data);
1838
1839 if (!err) {
1840 if (!data->stop || mrq->sbc) {
17c8bc85 1841 if (mrq->sbc && data->stop)
e352c813
SJ		 1842 data->stop->error = 0;
1843 dw_mci_request_end(host, mrq);
1844 goto unlock;
f95f3850 1845 }
f95f3850 1846
e352c813
SJ		 1847 /* stop command for open-ended transfer*/
1848 if (data->stop)
1849 send_stop_abort(host, data);
2aa35465
DA		 1850 } else {
1851 /*
1852 * If we don't have a command complete now we'll
1853 * never get one since we just reset everything;
1854 * better end the request.
1855 *
1856 * If we do have a command complete we'll fall
1857 * through to the SENDING_STOP command and
1858 * everything will be peachy keen.
1859 */
1860 if (!test_bit(EVENT_CMD_COMPLETE,
1861 &host->pending_events)) {
1862 host->cmd = NULL;
1863 dw_mci_request_end(host, mrq);
1864 goto unlock;
1865 }
053b3ce6
SJ		 1866 }
1867
e352c813
SJ		 1868 /*
1869 * If err has non-zero,
1870 * stop-abort command has been already issued.
1871 */
f95f3850 1872 prev_state = state = STATE_SENDING_STOP;
e352c813 1873
f95f3850
WN		 1874 /* fall through */
1875
1876 case STATE_SENDING_STOP:
1877 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1878 &host->pending_events))
1879 break;
1880
71abb133 1881 /* CMD error in data command */
31bff450 1882 if (mrq->cmd->error && mrq->data)
3a33a94c 1883 dw_mci_reset(host);
71abb133 1884
f95f3850 1885 host->cmd = NULL;
71abb133 1886 host->data = NULL;
90c2143a 1887
e352c813
SJ		 1888 if (mrq->stop)
1889 dw_mci_command_complete(host, mrq->stop);
90c2143a
SJ		 1890 else
1891 host->cmd_status = 0;
1892
e352c813 1893 dw_mci_request_end(host, mrq);
f95f3850
WN		 1894 goto unlock;
1895
1896 case STATE_DATA_ERROR:
1897 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1898 &host->pending_events))
1899 break;
1900
1901 state = STATE_DATA_BUSY;
1902 break;
1903 }
1904 } while (state != prev_state);
1905
1906 host->state = state;
1907unlock:
1908 spin_unlock(&host->lock);
1909
1910}
1911
34b664a2
JH		 1912/* push final bytes to part_buf, only use during push */
1913static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1914{
34b664a2
JH		 1915 memcpy((void *)&host->part_buf, buf, cnt);
1916 host->part_buf_count = cnt;
1917}
f95f3850 1918
34b664a2
JH		 1919/* append bytes to part_buf, only use during push */
1920static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1921{
1922 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1923 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1924 host->part_buf_count += cnt;
1925 return cnt;
1926}
f95f3850 1927
34b664a2
JH		 1928/* pull first bytes from part_buf, only use during pull */
1929static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1930{
0e3a22c0 1931 cnt = min_t(int, cnt, host->part_buf_count);
34b664a2
JH		 1932 if (cnt) {
1933 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1934 cnt);
1935 host->part_buf_count -= cnt;
1936 host->part_buf_start += cnt;
f95f3850 1937 }
34b664a2 1938 return cnt;
f95f3850
WN		 1939}
1940
34b664a2
JH		 1941/* pull final bytes from the part_buf, assuming it's just been filled */
1942static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1943{
34b664a2
JH		 1944 memcpy(buf, &host->part_buf, cnt);
1945 host->part_buf_start = cnt;
1946 host->part_buf_count = (1 << host->data_shift) - cnt;
1947}
f95f3850 1948
34b664a2
JH		 1949static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1950{
cfbeb59c
MC		 1951 struct mmc_data *data = host->data;
1952 int init_cnt = cnt;
1953
34b664a2
JH		 1954 /* try and push anything in the part_buf */
1955 if (unlikely(host->part_buf_count)) {
1956 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 1957
34b664a2
JH		 1958 buf += len;
1959 cnt -= len;
cfbeb59c 1960 if (host->part_buf_count == 2) {
76184ac1 1961 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 1962 host->part_buf_count = 0;
1963 }
1964 }
1965#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1966 if (unlikely((unsigned long)buf & 0x1)) {
1967 while (cnt >= 2) {
1968 u16 aligned_buf[64];
1969 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1970 int items = len >> 1;
1971 int i;
1972 /* memcpy from input buffer into aligned buffer */
1973 memcpy(aligned_buf, buf, len);
1974 buf += len;
1975 cnt -= len;
1976 /* push data from aligned buffer into fifo */
1977 for (i = 0; i < items; ++i)
76184ac1 1978 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 1979 }
1980 } else
1981#endif
1982 {
1983 u16 *pdata = buf;
0e3a22c0 1984
34b664a2 1985 for (; cnt >= 2; cnt -= 2)
76184ac1 1986 mci_fifo_writew(host->fifo_reg, *pdata++);
34b664a2
JH		 1987 buf = pdata;
1988 }
1989 /* put anything remaining in the part_buf */
1990 if (cnt) {
1991 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 1992 /* Push data if we have reached the expected data length */
1993 if ((data->bytes_xfered + init_cnt) ==
1994 (data->blksz * data->blocks))
76184ac1 1995 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 1996 }
1997}
f95f3850 1998
34b664a2
JH		 1999static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2000{
2001#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2002 if (unlikely((unsigned long)buf & 0x1)) {
2003 while (cnt >= 2) {
2004 /* pull data from fifo into aligned buffer */
2005 u16 aligned_buf[64];
2006 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2007 int items = len >> 1;
2008 int i;
0e3a22c0 2009
34b664a2 2010 for (i = 0; i < items; ++i)
76184ac1 2011 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2012 /* memcpy from aligned buffer into output buffer */
2013 memcpy(buf, aligned_buf, len);
2014 buf += len;
2015 cnt -= len;
2016 }
2017 } else
2018#endif
2019 {
2020 u16 *pdata = buf;
0e3a22c0 2021
34b664a2 2022 for (; cnt >= 2; cnt -= 2)
76184ac1 2023 *pdata++ = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2024 buf = pdata;
2025 }
2026 if (cnt) {
76184ac1 2027 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
34b664a2 2028 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2029 }
2030}
2031
2032static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2033{
cfbeb59c
MC		 2034 struct mmc_data *data = host->data;
2035 int init_cnt = cnt;
2036
34b664a2
JH		 2037 /* try and push anything in the part_buf */
2038 if (unlikely(host->part_buf_count)) {
2039 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2040
34b664a2
JH		 2041 buf += len;
2042 cnt -= len;
cfbeb59c 2043 if (host->part_buf_count == 4) {
76184ac1 2044 mci_fifo_writel(host->fifo_reg, host->part_buf32);
34b664a2
JH		 2045 host->part_buf_count = 0;
2046 }
2047 }
2048#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2049 if (unlikely((unsigned long)buf & 0x3)) {
2050 while (cnt >= 4) {
2051 u32 aligned_buf[32];
2052 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2053 int items = len >> 2;
2054 int i;
2055 /* memcpy from input buffer into aligned buffer */
2056 memcpy(aligned_buf, buf, len);
2057 buf += len;
2058 cnt -= len;
2059 /* push data from aligned buffer into fifo */
2060 for (i = 0; i < items; ++i)
76184ac1 2061 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2062 }
2063 } else
2064#endif
2065 {
2066 u32 *pdata = buf;
0e3a22c0 2067
34b664a2 2068 for (; cnt >= 4; cnt -= 4)
76184ac1 2069 mci_fifo_writel(host->fifo_reg, *pdata++);
34b664a2
JH		 2070 buf = pdata;
2071 }
2072 /* put anything remaining in the part_buf */
2073 if (cnt) {
2074 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2075 /* Push data if we have reached the expected data length */
2076 if ((data->bytes_xfered + init_cnt) ==
2077 (data->blksz * data->blocks))
76184ac1 2078 mci_fifo_writel(host->fifo_reg, host->part_buf32);
f95f3850
WN		 2079 }
2080}
2081
2082static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2083{
34b664a2
JH		 2084#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2085 if (unlikely((unsigned long)buf & 0x3)) {
2086 while (cnt >= 4) {
2087 /* pull data from fifo into aligned buffer */
2088 u32 aligned_buf[32];
2089 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2090 int items = len >> 2;
2091 int i;
0e3a22c0 2092
34b664a2 2093 for (i = 0; i < items; ++i)
76184ac1 2094 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2095 /* memcpy from aligned buffer into output buffer */
2096 memcpy(buf, aligned_buf, len);
2097 buf += len;
2098 cnt -= len;
2099 }
2100 } else
2101#endif
2102 {
2103 u32 *pdata = buf;
0e3a22c0 2104
34b664a2 2105 for (; cnt >= 4; cnt -= 4)
76184ac1 2106 *pdata++ = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2107 buf = pdata;
2108 }
2109 if (cnt) {
76184ac1 2110 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
34b664a2 2111 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2112 }
2113}
2114
2115static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2116{
cfbeb59c
MC		 2117 struct mmc_data *data = host->data;
2118 int init_cnt = cnt;
2119
34b664a2
JH		 2120 /* try and push anything in the part_buf */
2121 if (unlikely(host->part_buf_count)) {
2122 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2123
34b664a2
JH		 2124 buf += len;
2125 cnt -= len;
c09fbd74 2126
cfbeb59c 2127 if (host->part_buf_count == 8) {
76184ac1 2128 mci_fifo_writeq(host->fifo_reg, host->part_buf);
34b664a2
JH		 2129 host->part_buf_count = 0;
2130 }
2131 }
2132#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2133 if (unlikely((unsigned long)buf & 0x7)) {
2134 while (cnt >= 8) {
2135 u64 aligned_buf[16];
2136 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2137 int items = len >> 3;
2138 int i;
2139 /* memcpy from input buffer into aligned buffer */
2140 memcpy(aligned_buf, buf, len);
2141 buf += len;
2142 cnt -= len;
2143 /* push data from aligned buffer into fifo */
2144 for (i = 0; i < items; ++i)
76184ac1 2145 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2146 }
2147 } else
2148#endif
2149 {
2150 u64 *pdata = buf;
0e3a22c0 2151
34b664a2 2152 for (; cnt >= 8; cnt -= 8)
76184ac1 2153 mci_fifo_writeq(host->fifo_reg, *pdata++);
34b664a2
JH		 2154 buf = pdata;
2155 }
2156 /* put anything remaining in the part_buf */
2157 if (cnt) {
2158 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2159 /* Push data if we have reached the expected data length */
2160 if ((data->bytes_xfered + init_cnt) ==
2161 (data->blksz * data->blocks))
76184ac1 2162 mci_fifo_writeq(host->fifo_reg, host->part_buf);
f95f3850
WN		 2163 }
2164}
2165
2166static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2167{
34b664a2
JH		 2168#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2169 if (unlikely((unsigned long)buf & 0x7)) {
2170 while (cnt >= 8) {
2171 /* pull data from fifo into aligned buffer */
2172 u64 aligned_buf[16];
2173 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2174 int items = len >> 3;
2175 int i;
0e3a22c0 2176
34b664a2 2177 for (i = 0; i < items; ++i)
76184ac1
BD		 2178 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2179
34b664a2
JH		 2180 /* memcpy from aligned buffer into output buffer */
2181 memcpy(buf, aligned_buf, len);
2182 buf += len;
2183 cnt -= len;
2184 }
2185 } else
2186#endif
2187 {
2188 u64 *pdata = buf;
0e3a22c0 2189
34b664a2 2190 for (; cnt >= 8; cnt -= 8)
76184ac1 2191 *pdata++ = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2192 buf = pdata;
2193 }
2194 if (cnt) {
76184ac1 2195 host->part_buf = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2196 dw_mci_pull_final_bytes(host, buf, cnt);
2197 }
2198}
f95f3850 2199
34b664a2
JH		 2200static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2201{
2202 int len;
f95f3850 2203
34b664a2
JH		 2204 /* get remaining partial bytes */
2205 len = dw_mci_pull_part_bytes(host, buf, cnt);
2206 if (unlikely(len == cnt))
2207 return;
2208 buf += len;
2209 cnt -= len;
2210
2211 /* get the rest of the data */
2212 host->pull_data(host, buf, cnt);
f95f3850
WN		 2213}
2214
87a74d39 2215static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
f95f3850 2216{
f9c2a0dc
SJ		 2217 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2218 void *buf;
2219 unsigned int offset;
f95f3850
WN		 2220 struct mmc_data *data = host->data;
2221 int shift = host->data_shift;
2222 u32 status;
3e4b0d8b 2223 unsigned int len;
f9c2a0dc 2224 unsigned int remain, fcnt;
f95f3850
WN		 2225
2226 do {
f9c2a0dc
SJ		 2227 if (!sg_miter_next(sg_miter))
2228 goto done;
2229
4225fc85 2230 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2231 buf = sg_miter->addr;
2232 remain = sg_miter->length;
2233 offset = 0;
2234
2235 do {
2236 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2237 << shift) + host->part_buf_count;
2238 len = min(remain, fcnt);
2239 if (!len)
2240 break;
34b664a2 2241 dw_mci_pull_data(host, (void *)(buf + offset), len);
3e4b0d8b 2242 data->bytes_xfered += len;
f95f3850 2243 offset += len;
f9c2a0dc
SJ		 2244 remain -= len;
2245 } while (remain);
f95f3850 2246
e74f3a9c 2247 sg_miter->consumed = offset;
f95f3850
WN		 2248 status = mci_readl(host, MINTSTS);
2249 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
87a74d39
KK		 2250 /* if the RXDR is ready read again */
2251 } while ((status & SDMMC_INT_RXDR) ||
2252 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
f9c2a0dc
SJ		 2253
2254 if (!remain) {
2255 if (!sg_miter_next(sg_miter))
2256 goto done;
2257 sg_miter->consumed = 0;
2258 }
2259 sg_miter_stop(sg_miter);
f95f3850
WN		 2260 return;
2261
2262done:
f9c2a0dc
SJ		 2263 sg_miter_stop(sg_miter);
2264 host->sg = NULL;
0e3a22c0 2265 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2266 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2267}
2268
2269static void dw_mci_write_data_pio(struct dw_mci *host)
2270{
f9c2a0dc
SJ		 2271 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2272 void *buf;
2273 unsigned int offset;
f95f3850
WN		 2274 struct mmc_data *data = host->data;
2275 int shift = host->data_shift;
2276 u32 status;
3e4b0d8b 2277 unsigned int len;
f9c2a0dc
SJ		 2278 unsigned int fifo_depth = host->fifo_depth;
2279 unsigned int remain, fcnt;
f95f3850
WN		 2280
2281 do {
f9c2a0dc
SJ		 2282 if (!sg_miter_next(sg_miter))
2283 goto done;
2284
4225fc85 2285 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2286 buf = sg_miter->addr;
2287 remain = sg_miter->length;
2288 offset = 0;
2289
2290 do {
2291 fcnt = ((fifo_depth -
2292 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2293 << shift) - host->part_buf_count;
2294 len = min(remain, fcnt);
2295 if (!len)
2296 break;
f95f3850 2297 host->push_data(host, (void *)(buf + offset), len);
3e4b0d8b 2298 data->bytes_xfered += len;
f95f3850 2299 offset += len;
f9c2a0dc
SJ		 2300 remain -= len;
2301 } while (remain);
f95f3850 2302
e74f3a9c 2303 sg_miter->consumed = offset;
f95f3850
WN		 2304 status = mci_readl(host, MINTSTS);
2305 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 2306 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f9c2a0dc
SJ		 2307
2308 if (!remain) {
2309 if (!sg_miter_next(sg_miter))
2310 goto done;
2311 sg_miter->consumed = 0;
2312 }
2313 sg_miter_stop(sg_miter);
f95f3850
WN		 2314 return;
2315
2316done:
f9c2a0dc
SJ		 2317 sg_miter_stop(sg_miter);
2318 host->sg = NULL;
0e3a22c0 2319 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2320 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2321}
2322
2323static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2324{
2325 if (!host->cmd_status)
2326 host->cmd_status = status;
2327
0e3a22c0 2328 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2329
2330 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2331 tasklet_schedule(&host->tasklet);
2332}
2333
6130e7a9
DA		 2334static void dw_mci_handle_cd(struct dw_mci *host)
2335{
2336 int i;
2337
2338 for (i = 0; i < host->num_slots; i++) {
2339 struct dw_mci_slot *slot = host->slot[i];
2340
2341 if (!slot)
2342 continue;
2343
2344 if (slot->mmc->ops->card_event)
2345 slot->mmc->ops->card_event(slot->mmc);
2346 mmc_detect_change(slot->mmc,
2347 msecs_to_jiffies(host->pdata->detect_delay_ms));
2348 }
2349}
2350
f95f3850
WN		 2351static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2352{
2353 struct dw_mci *host = dev_id;
182c9081 2354 u32 pending;
1a5c8e1f 2355 int i;
f95f3850 2356
1fb5f68a
MC		 2357 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2358
476d79f1
DA		 2359 /*
2360 * DTO fix - version 2.10a and below, and only if internal DMA
2361 * is configured.
2362 */
2363 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
2364 if (!pending &&
2365 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
2366 pending |= SDMMC_INT_DATA_OVER;
2367 }
f95f3850 2368
476d79f1 2369 if (pending) {
01730558
DA		 2370 /* Check volt switch first, since it can look like an error */
2371 if ((host->state == STATE_SENDING_CMD11) &&
2372 (pending & SDMMC_INT_VOLT_SWITCH)) {
49ba0302 2373 unsigned long irqflags;
5c935165 2374
01730558
DA		 2375 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2376 pending &= ~SDMMC_INT_VOLT_SWITCH;
49ba0302
DA		 2377
2378 /*
2379 * Hold the lock; we know cmd11_timer can't be kicked
2380 * off after the lock is released, so safe to delete.
2381 */
2382 spin_lock_irqsave(&host->irq_lock, irqflags);
01730558 2383 dw_mci_cmd_interrupt(host, pending);
49ba0302
DA		 2384 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2385
2386 del_timer(&host->cmd11_timer);
01730558
DA		 2387 }
2388
f95f3850
WN		 2389 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2390 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 2391 host->cmd_status = pending;
0e3a22c0 2392 smp_wmb(); /* drain writebuffer */
f95f3850 2393 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 2394 }
2395
2396 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2397 /* if there is an error report DATA_ERROR */
2398 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 2399 host->data_status = pending;
0e3a22c0 2400 smp_wmb(); /* drain writebuffer */
f95f3850 2401 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 2402 tasklet_schedule(&host->tasklet);
f95f3850
WN		 2403 }
2404
2405 if (pending & SDMMC_INT_DATA_OVER) {
57e10486
AK		 2406 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
2407 del_timer(&host->dto_timer);
2408
f95f3850
WN		 2409 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2410 if (!host->data_status)
182c9081 2411 host->data_status = pending;
0e3a22c0 2412 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2413 if (host->dir_status == DW_MCI_RECV_STATUS) {
2414 if (host->sg != NULL)
87a74d39 2415 dw_mci_read_data_pio(host, true);
f95f3850
WN		 2416 }
2417 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2418 tasklet_schedule(&host->tasklet);
2419 }
2420
2421 if (pending & SDMMC_INT_RXDR) {
2422 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 2423 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
87a74d39 2424 dw_mci_read_data_pio(host, false);
f95f3850
WN		 2425 }
2426
2427 if (pending & SDMMC_INT_TXDR) {
2428 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 2429 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 2430 dw_mci_write_data_pio(host);
2431 }
2432
2433 if (pending & SDMMC_INT_CMD_DONE) {
2434 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 2435 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 2436 }
2437
2438 if (pending & SDMMC_INT_CD) {
2439 mci_writel(host, RINTSTS, SDMMC_INT_CD);
6130e7a9 2440 dw_mci_handle_cd(host);
f95f3850
WN		 2441 }
2442
1a5c8e1f
SH		 2443 /* Handle SDIO Interrupts */
2444 for (i = 0; i < host->num_slots; i++) {
2445 struct dw_mci_slot *slot = host->slot[i];
ed2540ef
DA		 2446
2447 if (!slot)
2448 continue;
2449
76756234
AK		 2450 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2451 mci_writel(host, RINTSTS,
2452 SDMMC_INT_SDIO(slot->sdio_id));
1a5c8e1f
SH		 2453 mmc_signal_sdio_irq(slot->mmc);
2454 }
2455 }
2456
1fb5f68a 2457 }
f95f3850 2458
3fc7eaef
SL		 2459 if (host->use_dma != TRANS_MODE_IDMAC)
2460 return IRQ_HANDLED;
2461
2462 /* Handle IDMA interrupts */
69d99fdc
PT		 2463 if (host->dma_64bit_address == 1) {
2464 pending = mci_readl(host, IDSTS64);
2465 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2466 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2467 SDMMC_IDMAC_INT_RI);
2468 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
3fc7eaef 2469 host->dma_ops->complete((void *)host);
69d99fdc
PT		 2470 }
2471 } else {
2472 pending = mci_readl(host, IDSTS);
2473 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2474 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2475 SDMMC_IDMAC_INT_RI);
2476 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3fc7eaef 2477 host->dma_ops->complete((void *)host);
69d99fdc 2478 }
f95f3850 2479 }
f95f3850
WN		 2480
2481 return IRQ_HANDLED;
2482}
2483
c91eab4b 2484#ifdef CONFIG_OF
eff8f2f5
LPC		 2485/* given a slot, find out the device node representing that slot */
2486static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
c91eab4b 2487{
eff8f2f5 2488 struct device *dev = slot->mmc->parent;
c91eab4b
TA		 2489 struct device_node *np;
2490 const __be32 *addr;
2491 int len;
2492
2493 if (!dev || !dev->of_node)
2494 return NULL;
2495
2496 for_each_child_of_node(dev->of_node, np) {
2497 addr = of_get_property(np, "reg", &len);
2498 if (!addr || (len < sizeof(int)))
2499 continue;
eff8f2f5 2500 if (be32_to_cpup(addr) == slot->id)
c91eab4b
TA		 2501 return np;
2502 }
2503 return NULL;
2504}
2505
eff8f2f5 2506static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
a70aaa64 2507{
eff8f2f5 2508 struct device_node *np = dw_mci_of_find_slot_node(slot);
a70aaa64 2509
eff8f2f5
LPC		 2510 if (!np)
2511 return;
a70aaa64 2512
eff8f2f5
LPC		 2513 if (of_property_read_bool(np, "disable-wp")) {
2514 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2515 dev_warn(slot->mmc->parent,
2516 "Slot quirk 'disable-wp' is deprecated\n");
2517 }
a70aaa64 2518}
c91eab4b 2519#else /* CONFIG_OF */
eff8f2f5 2520static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
a70aaa64 2521{
a70aaa64 2522}
c91eab4b
TA		 2523#endif /* CONFIG_OF */
2524
36c179a9 2525static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 2526{
2527 struct mmc_host *mmc;
2528 struct dw_mci_slot *slot;
e95baf13 2529 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2530 int ctrl_id, ret;
1f44a2a5 2531 u32 freq[2];
f95f3850 2532
4a90920c 2533 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 2534 if (!mmc)
2535 return -ENOMEM;
2536
2537 slot = mmc_priv(mmc);
2538 slot->id = id;
76756234 2539 slot->sdio_id = host->sdio_id0 + id;
f95f3850
WN		 2540 slot->mmc = mmc;
2541 slot->host = host;
c91eab4b 2542 host->slot[id] = slot;
f95f3850
WN		 2543
2544 mmc->ops = &dw_mci_ops;
1f44a2a5
SJ		 2545 if (of_property_read_u32_array(host->dev->of_node,
2546 "clock-freq-min-max", freq, 2)) {
2547 mmc->f_min = DW_MCI_FREQ_MIN;
2548 mmc->f_max = DW_MCI_FREQ_MAX;
2549 } else {
2550 mmc->f_min = freq[0];
2551 mmc->f_max = freq[1];
2552 }
f95f3850 2553
51da2240
YC		 2554 /*if there are external regulators, get them*/
2555 ret = mmc_regulator_get_supply(mmc);
2556 if (ret == -EPROBE_DEFER)
3cf890fc 2557 goto err_host_allocated;
51da2240
YC		 2558
2559 if (!mmc->ocr_avail)
2560 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
f95f3850 2561
fc3d7720
JC		 2562 if (host->pdata->caps)
2563 mmc->caps = host->pdata->caps;
fc3d7720 2564
ab269128
AK		 2565 if (host->pdata->pm_caps)
2566 mmc->pm_caps = host->pdata->pm_caps;
2567
800d78bf
TA		 2568 if (host->dev->of_node) {
2569 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2570 if (ctrl_id < 0)
2571 ctrl_id = 0;
2572 } else {
2573 ctrl_id = to_platform_device(host->dev)->id;
2574 }
cb27a843
JH		 2575 if (drv_data && drv_data->caps)
2576 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 2577
4f408cc6
SJ		 2578 if (host->pdata->caps2)
2579 mmc->caps2 = host->pdata->caps2;
4f408cc6 2580
eff8f2f5
LPC		 2581 dw_mci_slot_of_parse(slot);
2582
3cf890fc
DA		 2583 ret = mmc_of_parse(mmc);
2584 if (ret)
2585 goto err_host_allocated;
f95f3850 2586
2b708df2 2587 /* Useful defaults if platform data is unset. */
3fc7eaef 2588 if (host->use_dma == TRANS_MODE_IDMAC) {
2b708df2
JC		 2589 mmc->max_segs = host->ring_size;
2590 mmc->max_blk_size = 65536;
2591 mmc->max_seg_size = 0x1000;
2592 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2593 mmc->max_blk_count = mmc->max_req_size / 512;
3fc7eaef
SL		 2594 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2595 mmc->max_segs = 64;
2596 mmc->max_blk_size = 65536;
2597 mmc->max_blk_count = 65535;
2598 mmc->max_req_size =
2599 mmc->max_blk_size * mmc->max_blk_count;
2600 mmc->max_seg_size = mmc->max_req_size;
f95f3850 2601 } else {
3fc7eaef 2602 /* TRANS_MODE_PIO */
2b708df2
JC		 2603 mmc->max_segs = 64;
2604 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2605 mmc->max_blk_count = 512;
2606 mmc->max_req_size = mmc->max_blk_size *
2607 mmc->max_blk_count;
2608 mmc->max_seg_size = mmc->max_req_size;
a39e5746 2609 }
f95f3850 2610
ae0eb348
JC		 2611 if (dw_mci_get_cd(mmc))
2612 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2613 else
2614 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2615
0cea529d
JC		 2616 ret = mmc_add_host(mmc);
2617 if (ret)
3cf890fc 2618 goto err_host_allocated;
f95f3850
WN		 2619
2620#if defined(CONFIG_DEBUG_FS)
2621 dw_mci_init_debugfs(slot);
2622#endif
2623
f95f3850 2624 return 0;
800d78bf 2625
3cf890fc 2626err_host_allocated:
800d78bf 2627 mmc_free_host(mmc);
51da2240 2628 return ret;
f95f3850
WN		 2629}
2630
2631static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2632{
f95f3850
WN		 2633 /* Debugfs stuff is cleaned up by mmc core */
2634 mmc_remove_host(slot->mmc);
2635 slot->host->slot[id] = NULL;
2636 mmc_free_host(slot->mmc);
2637}
2638
2639static void dw_mci_init_dma(struct dw_mci *host)
2640{
69d99fdc 2641 int addr_config;
3fc7eaef
SL		 2642 struct device *dev = host->dev;
2643 struct device_node *np = dev->of_node;
69d99fdc 2644
3fc7eaef
SL		 2645 /*
2646 * Check tansfer mode from HCON[17:16]
2647 * Clear the ambiguous description of dw_mmc databook:
2648 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2649 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2650 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2651 * 2b'11: Non DW DMA Interface -> pio only
2652 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2653 * simpler request/acknowledge handshake mechanism and both of them
2654 * are regarded as external dma master for dw_mmc.
2655 */
2656 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2657 if (host->use_dma == DMA_INTERFACE_IDMA) {
2658 host->use_dma = TRANS_MODE_IDMAC;
2659 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2660 host->use_dma == DMA_INTERFACE_GDMA) {
2661 host->use_dma = TRANS_MODE_EDMAC;
2662 } else {
f95f3850
WN		 2663 goto no_dma;
2664 }
2665
2666 /* Determine which DMA interface to use */
3fc7eaef
SL		 2667 if (host->use_dma == TRANS_MODE_IDMAC) {
2668 /*
2669 * Check ADDR_CONFIG bit in HCON to find
2670 * IDMAC address bus width
2671 */
70692752 2672 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
3fc7eaef
SL		 2673
2674 if (addr_config == 1) {
2675 /* host supports IDMAC in 64-bit address mode */
2676 host->dma_64bit_address = 1;
2677 dev_info(host->dev,
2678 "IDMAC supports 64-bit address mode.\n");
2679 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2680 dma_set_coherent_mask(host->dev,
2681 DMA_BIT_MASK(64));
2682 } else {
2683 /* host supports IDMAC in 32-bit address mode */
2684 host->dma_64bit_address = 0;
2685 dev_info(host->dev,
2686 "IDMAC supports 32-bit address mode.\n");
2687 }
f95f3850 2688
3fc7eaef
SL		 2689 /* Alloc memory for sg translation */
2690 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2691 &host->sg_dma, GFP_KERNEL);
2692 if (!host->sg_cpu) {
2693 dev_err(host->dev,
2694 "%s: could not alloc DMA memory\n",
2695 __func__);
2696 goto no_dma;
2697 }
2698
2699 host->dma_ops = &dw_mci_idmac_ops;
2700 dev_info(host->dev, "Using internal DMA controller.\n");
2701 } else {
2702 /* TRANS_MODE_EDMAC: check dma bindings again */
2703 if ((of_property_count_strings(np, "dma-names") < 0) ||
2704 (!of_find_property(np, "dmas", NULL))) {
2705 goto no_dma;
2706 }
2707 host->dma_ops = &dw_mci_edmac_ops;
2708 dev_info(host->dev, "Using external DMA controller.\n");
2709 }
f95f3850 2710
e1631f98
JC		 2711 if (host->dma_ops->init && host->dma_ops->start &&
2712 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 2713 if (host->dma_ops->init(host)) {
0e3a22c0
SL		 2714 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2715 __func__);
f95f3850
WN		 2716 goto no_dma;
2717 }
2718 } else {
4a90920c 2719 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 2720 goto no_dma;
2721 }
2722
f95f3850
WN		 2723 return;
2724
2725no_dma:
4a90920c 2726 dev_info(host->dev, "Using PIO mode.\n");
3fc7eaef 2727 host->use_dma = TRANS_MODE_PIO;
f95f3850
WN		 2728}
2729
31bff450 2730static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
f95f3850
WN		 2731{
2732 unsigned long timeout = jiffies + msecs_to_jiffies(500);
31bff450 2733 u32 ctrl;
f95f3850 2734
31bff450
SJ		 2735 ctrl = mci_readl(host, CTRL);
2736 ctrl |= reset;
2737 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 2738
2739 /* wait till resets clear */
2740 do {
2741 ctrl = mci_readl(host, CTRL);
31bff450 2742 if (!(ctrl & reset))
f95f3850
WN		 2743 return true;
2744 } while (time_before(jiffies, timeout));
2745
31bff450
SJ		 2746 dev_err(host->dev,
2747 "Timeout resetting block (ctrl reset %#x)\n",
2748 ctrl & reset);
f95f3850
WN		 2749
2750 return false;
2751}
2752
3a33a94c 2753static bool dw_mci_reset(struct dw_mci *host)
31bff450 2754{
3a33a94c
SR		 2755 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2756 bool ret = false;
2757
31bff450
SJ		 2758 /*
2759 * Reseting generates a block interrupt, hence setting
2760 * the scatter-gather pointer to NULL.
2761 */
2762 if (host->sg) {
2763 sg_miter_stop(&host->sg_miter);
2764 host->sg = NULL;
2765 }
2766
3a33a94c
SR		 2767 if (host->use_dma)
2768 flags |= SDMMC_CTRL_DMA_RESET;
31bff450 2769
3a33a94c
SR		 2770 if (dw_mci_ctrl_reset(host, flags)) {
2771 /*
2772 * In all cases we clear the RAWINTS register to clear any
2773 * interrupts.
2774 */
2775 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2776
2777 /* if using dma we wait for dma_req to clear */
2778 if (host->use_dma) {
2779 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2780 u32 status;
0e3a22c0 2781
3a33a94c
SR		 2782 do {
2783 status = mci_readl(host, STATUS);
2784 if (!(status & SDMMC_STATUS_DMA_REQ))
2785 break;
2786 cpu_relax();
2787 } while (time_before(jiffies, timeout));
2788
2789 if (status & SDMMC_STATUS_DMA_REQ) {
2790 dev_err(host->dev,
0e3a22c0
SL		 2791 "%s: Timeout waiting for dma_req to clear during reset\n",
2792 __func__);
3a33a94c
SR		 2793 goto ciu_out;
2794 }
2795
2796 /* when using DMA next we reset the fifo again */
2797 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2798 goto ciu_out;
2799 }
2800 } else {
2801 /* if the controller reset bit did clear, then set clock regs */
2802 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
0e3a22c0
SL		 2803 dev_err(host->dev,
2804 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
3a33a94c
SR		 2805 __func__);
2806 goto ciu_out;
2807 }
2808 }
2809
3fc7eaef
SL		 2810 if (host->use_dma == TRANS_MODE_IDMAC)
2811 /* It is also recommended that we reset and reprogram idmac */
2812 dw_mci_idmac_reset(host);
3a33a94c
SR		 2813
2814 ret = true;
2815
2816ciu_out:
2817 /* After a CTRL reset we need to have CIU set clock registers */
2818 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2819
2820 return ret;
31bff450
SJ		 2821}
2822
5c935165
DA		 2823static void dw_mci_cmd11_timer(unsigned long arg)
2824{
2825 struct dw_mci *host = (struct dw_mci *)arg;
2826
fd674198
DA		 2827 if (host->state != STATE_SENDING_CMD11) {
2828 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2829 return;
2830 }
5c935165
DA		 2831
2832 host->cmd_status = SDMMC_INT_RTO;
2833 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2834 tasklet_schedule(&host->tasklet);
2835}
2836
57e10486
AK		 2837static void dw_mci_dto_timer(unsigned long arg)
2838{
2839 struct dw_mci *host = (struct dw_mci *)arg;
2840
2841 switch (host->state) {
2842 case STATE_SENDING_DATA:
2843 case STATE_DATA_BUSY:
2844 /*
2845 * If DTO interrupt does NOT come in sending data state,
2846 * we should notify the driver to terminate current transfer
2847 * and report a data timeout to the core.
2848 */
2849 host->data_status = SDMMC_INT_DRTO;
2850 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2851 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2852 tasklet_schedule(&host->tasklet);
2853 break;
2854 default:
2855 break;
2856 }
2857}
2858
c91eab4b
TA		 2859#ifdef CONFIG_OF
2860static struct dw_mci_of_quirks {
2861 char *quirk;
2862 int id;
2863} of_quirks[] = {
2864 {
c91eab4b
TA		 2865 .quirk = "broken-cd",
2866 .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
2867 },
2868};
2869
2870static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2871{
2872 struct dw_mci_board *pdata;
2873 struct device *dev = host->dev;
2874 struct device_node *np = dev->of_node;
e95baf13 2875 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2876 int idx, ret;
3c6d89ea 2877 u32 clock_frequency;
c91eab4b
TA		 2878
2879 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
bf3707ea 2880 if (!pdata)
c91eab4b 2881 return ERR_PTR(-ENOMEM);
c91eab4b
TA		 2882
2883 /* find out number of slots supported */
2884 if (of_property_read_u32(dev->of_node, "num-slots",
2885 &pdata->num_slots)) {
0e3a22c0
SL		 2886 dev_info(dev,
2887 "num-slots property not found, assuming 1 slot is available\n");
c91eab4b
TA		 2888 pdata->num_slots = 1;
2889 }
2890
2891 /* get quirks */
2892 for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
2893 if (of_get_property(np, of_quirks[idx].quirk, NULL))
2894 pdata->quirks |= of_quirks[idx].id;
2895
2896 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
0e3a22c0
SL		 2897 dev_info(dev,
2898 "fifo-depth property not found, using value of FIFOTH register as default\n");
c91eab4b
TA		 2899
2900 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2901
3c6d89ea
DA		 2902 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2903 pdata->bus_hz = clock_frequency;
2904
cb27a843
JH		 2905 if (drv_data && drv_data->parse_dt) {
2906 ret = drv_data->parse_dt(host);
800d78bf
TA		 2907 if (ret)
2908 return ERR_PTR(ret);
2909 }
2910
40a7a463
JC		 2911 if (of_find_property(np, "supports-highspeed", NULL)) {
2912 dev_info(dev, "supports-highspeed property is deprecated.\n");
10b49841 2913 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
40a7a463 2914 }
10b49841 2915
c91eab4b
TA		 2916 return pdata;
2917}
2918
2919#else /* CONFIG_OF */
2920static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2921{
2922 return ERR_PTR(-EINVAL);
2923}
2924#endif /* CONFIG_OF */
2925
fa0c3283
DA		 2926static void dw_mci_enable_cd(struct dw_mci *host)
2927{
2928 struct dw_mci_board *brd = host->pdata;
2929 unsigned long irqflags;
2930 u32 temp;
2931 int i;
2932
2933 /* No need for CD if broken card detection */
2934 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
2935 return;
2936
2937 /* No need for CD if all slots have a non-error GPIO */
2938 for (i = 0; i < host->num_slots; i++) {
2939 struct dw_mci_slot *slot = host->slot[i];
2940
2941 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2942 break;
2943 }
2944 if (i == host->num_slots)
2945 return;
2946
2947 spin_lock_irqsave(&host->irq_lock, irqflags);
2948 temp = mci_readl(host, INTMASK);
2949 temp |= SDMMC_INT_CD;
2950 mci_writel(host, INTMASK, temp);
2951 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2952}
2953
62ca8034 2954int dw_mci_probe(struct dw_mci *host)
f95f3850 2955{
e95baf13 2956 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 2957 int width, i, ret = 0;
f95f3850 2958 u32 fifo_size;
1c2215b7 2959 int init_slots = 0;
f95f3850 2960
c91eab4b
TA		 2961 if (!host->pdata) {
2962 host->pdata = dw_mci_parse_dt(host);
2963 if (IS_ERR(host->pdata)) {
2964 dev_err(host->dev, "platform data not available\n");
2965 return -EINVAL;
2966 }
f95f3850
WN		 2967 }
2968
9e747b7e 2969 if (host->pdata->num_slots < 1) {
4a90920c 2970 dev_err(host->dev,
907abd51 2971 "Platform data must supply num_slots.\n");
62ca8034 2972 return -ENODEV;
f95f3850
WN		 2973 }
2974
780f22af 2975 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 2976 if (IS_ERR(host->biu_clk)) {
2977 dev_dbg(host->dev, "biu clock not available\n");
2978 } else {
2979 ret = clk_prepare_enable(host->biu_clk);
2980 if (ret) {
2981 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 2982 return ret;
2983 }
2984 }
2985
780f22af 2986 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 2987 if (IS_ERR(host->ciu_clk)) {
2988 dev_dbg(host->dev, "ciu clock not available\n");
3c6d89ea 2989 host->bus_hz = host->pdata->bus_hz;
f90a0612
TA		 2990 } else {
2991 ret = clk_prepare_enable(host->ciu_clk);
2992 if (ret) {
2993 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 2994 goto err_clk_biu;
2995 }
f90a0612 2996
3c6d89ea
DA		 2997 if (host->pdata->bus_hz) {
2998 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2999 if (ret)
3000 dev_warn(host->dev,
612de4c1 3001 "Unable to set bus rate to %uHz\n",
3c6d89ea
DA		 3002 host->pdata->bus_hz);
3003 }
f90a0612 3004 host->bus_hz = clk_get_rate(host->ciu_clk);
3c6d89ea 3005 }
f90a0612 3006
612de4c1
JC		 3007 if (!host->bus_hz) {
3008 dev_err(host->dev,
3009 "Platform data must supply bus speed\n");
3010 ret = -ENODEV;
3011 goto err_clk_ciu;
3012 }
3013
002f0d5c
YK		 3014 if (drv_data && drv_data->init) {
3015 ret = drv_data->init(host);
3016 if (ret) {
3017 dev_err(host->dev,
3018 "implementation specific init failed\n");
3019 goto err_clk_ciu;
3020 }
3021 }
3022
cb27a843
JH		 3023 if (drv_data && drv_data->setup_clock) {
3024 ret = drv_data->setup_clock(host);
800d78bf
TA		 3025 if (ret) {
3026 dev_err(host->dev,
3027 "implementation specific clock setup failed\n");
3028 goto err_clk_ciu;
3029 }
3030 }
3031
5c935165
DA		 3032 setup_timer(&host->cmd11_timer,
3033 dw_mci_cmd11_timer, (unsigned long)host);
3034
62ca8034 3035 host->quirks = host->pdata->quirks;
f95f3850 3036
57e10486
AK		 3037 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3038 setup_timer(&host->dto_timer,
3039 dw_mci_dto_timer, (unsigned long)host);
3040
f95f3850 3041 spin_lock_init(&host->lock);
f8c58c11 3042 spin_lock_init(&host->irq_lock);
f95f3850
WN		 3043 INIT_LIST_HEAD(&host->queue);
3044
f95f3850
WN		 3045 /*
3046 * Get the host data width - this assumes that HCON has been set with
3047 * the correct values.
3048 */
70692752 3049 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
f95f3850
WN		 3050 if (!i) {
3051 host->push_data = dw_mci_push_data16;
3052 host->pull_data = dw_mci_pull_data16;
3053 width = 16;
3054 host->data_shift = 1;
3055 } else if (i == 2) {
3056 host->push_data = dw_mci_push_data64;
3057 host->pull_data = dw_mci_pull_data64;
3058 width = 64;
3059 host->data_shift = 3;
3060 } else {
3061 /* Check for a reserved value, and warn if it is */
3062 WARN((i != 1),
3063 "HCON reports a reserved host data width!\n"
3064 "Defaulting to 32-bit access.\n");
3065 host->push_data = dw_mci_push_data32;
3066 host->pull_data = dw_mci_pull_data32;
3067 width = 32;
3068 host->data_shift = 2;
3069 }
3070
3071 /* Reset all blocks */
3a33a94c 3072 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS))
141a712a
SJ		 3073 return -ENODEV;
3074
3075 host->dma_ops = host->pdata->dma_ops;
3076 dw_mci_init_dma(host);
f95f3850
WN		 3077
3078 /* Clear the interrupts for the host controller */
3079 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3080 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3081
3082 /* Put in max timeout */
3083 mci_writel(host, TMOUT, 0xFFFFFFFF);
3084
3085 /*
3086 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3087 * Tx Mark = fifo_size / 2 DMA Size = 8
3088 */
b86d8253
JH		 3089 if (!host->pdata->fifo_depth) {
3090 /*
3091 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3092 * have been overwritten by the bootloader, just like we're
3093 * about to do, so if you know the value for your hardware, you
3094 * should put it in the platform data.
3095 */
3096 fifo_size = mci_readl(host, FIFOTH);
8234e869 3097 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 3098 } else {
3099 fifo_size = host->pdata->fifo_depth;
3100 }
3101 host->fifo_depth = fifo_size;
52426899
SJ		 3102 host->fifoth_val =
3103 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
e61cf118 3104 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 3105
3106 /* disable clock to CIU */
3107 mci_writel(host, CLKENA, 0);
3108 mci_writel(host, CLKSRC, 0);
3109
63008768
JH		 3110 /*
3111 * In 2.40a spec, Data offset is changed.
3112 * Need to check the version-id and set data-offset for DATA register.
3113 */
3114 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3115 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3116
3117 if (host->verid < DW_MMC_240A)
76184ac1 3118 host->fifo_reg = host->regs + DATA_OFFSET;
63008768 3119 else
76184ac1 3120 host->fifo_reg = host->regs + DATA_240A_OFFSET;
63008768 3121
f95f3850 3122 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
780f22af
SJ		 3123 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3124 host->irq_flags, "dw-mci", host);
f95f3850 3125 if (ret)
6130e7a9 3126 goto err_dmaunmap;
f95f3850 3127
f95f3850
WN		 3128 if (host->pdata->num_slots)
3129 host->num_slots = host->pdata->num_slots;
3130 else
70692752 3131 host->num_slots = SDMMC_GET_SLOT_NUM(mci_readl(host, HCON));
f95f3850 3132
2da1d7f2 3133 /*
fa0c3283 3134 * Enable interrupts for command done, data over, data empty,
2da1d7f2
YC		 3135 * receive ready and error such as transmit, receive timeout, crc error
3136 */
3137 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3138 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3139 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3140 DW_MCI_ERROR_FLAGS);
0e3a22c0
SL		 3141 /* Enable mci interrupt */
3142 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2da1d7f2 3143
0e3a22c0
SL		 3144 dev_info(host->dev,
3145 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
2da1d7f2
YC		 3146 host->irq, width, fifo_size);
3147
f95f3850
WN		 3148 /* We need at least one slot to succeed */
3149 for (i = 0; i < host->num_slots; i++) {
3150 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 3151 if (ret)
3152 dev_dbg(host->dev, "slot %d init failed\n", i);
3153 else
3154 init_slots++;
3155 }
3156
3157 if (init_slots) {
3158 dev_info(host->dev, "%d slots initialized\n", init_slots);
3159 } else {
0e3a22c0
SL		 3160 dev_dbg(host->dev,
3161 "attempted to initialize %d slots, but failed on all\n",
3162 host->num_slots);
6130e7a9 3163 goto err_dmaunmap;
f95f3850
WN		 3164 }
3165
b793f658
DA		 3166 /* Now that slots are all setup, we can enable card detect */
3167 dw_mci_enable_cd(host);
3168
f95f3850 3169 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4a90920c 3170 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
f95f3850
WN		 3171
3172 return 0;
3173
f95f3850
WN		 3174err_dmaunmap:
3175 if (host->use_dma && host->dma_ops->exit)
3176 host->dma_ops->exit(host);
f90a0612
TA		 3177
3178err_clk_ciu:
780f22af 3179 if (!IS_ERR(host->ciu_clk))
f90a0612 3180 clk_disable_unprepare(host->ciu_clk);
780f22af 3181
f90a0612 3182err_clk_biu:
780f22af 3183 if (!IS_ERR(host->biu_clk))
f90a0612 3184 clk_disable_unprepare(host->biu_clk);
780f22af 3185
f95f3850
WN		 3186 return ret;
3187}
62ca8034 3188EXPORT_SYMBOL(dw_mci_probe);
f95f3850 3189
62ca8034 3190void dw_mci_remove(struct dw_mci *host)
f95f3850 3191{
f95f3850
WN		 3192 int i;
3193
f95f3850 3194 for (i = 0; i < host->num_slots; i++) {
4a90920c 3195 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 3196 if (host->slot[i])
3197 dw_mci_cleanup_slot(host->slot[i], i);
3198 }
3199
048fd7e6
PT		 3200 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3201 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3202
f95f3850
WN		 3203 /* disable clock to CIU */
3204 mci_writel(host, CLKENA, 0);
3205 mci_writel(host, CLKSRC, 0);
3206
f95f3850
WN		 3207 if (host->use_dma && host->dma_ops->exit)
3208 host->dma_ops->exit(host);
3209
f90a0612
TA		 3210 if (!IS_ERR(host->ciu_clk))
3211 clk_disable_unprepare(host->ciu_clk);
780f22af 3212
f90a0612
TA		 3213 if (!IS_ERR(host->biu_clk))
3214 clk_disable_unprepare(host->biu_clk);
f95f3850 3215}
62ca8034
SH		 3216EXPORT_SYMBOL(dw_mci_remove);
3217
3218
f95f3850 3219
6fe8890d 3220#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 3221/*
3222 * TODO: we should probably disable the clock to the card in the suspend path.
3223 */
62ca8034 3224int dw_mci_suspend(struct dw_mci *host)
f95f3850 3225{
3fc7eaef
SL		 3226 if (host->use_dma && host->dma_ops->exit)
3227 host->dma_ops->exit(host);
3228
f95f3850
WN		 3229 return 0;
3230}
62ca8034 3231EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 3232
62ca8034 3233int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 3234{
3235 int i, ret;
f95f3850 3236
3a33a94c 3237 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
e61cf118
JC		 3238 ret = -ENODEV;
3239 return ret;
3240 }
3241
3bfe619d 3242 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 3243 host->dma_ops->init(host);
3244
52426899
SJ		 3245 /*
3246 * Restore the initial value at FIFOTH register
3247 * And Invalidate the prev_blksz with zero
3248 */
e61cf118 3249 mci_writel(host, FIFOTH, host->fifoth_val);
52426899 3250 host->prev_blksz = 0;
e61cf118 3251
2eb2944f
DA		 3252 /* Put in max timeout */
3253 mci_writel(host, TMOUT, 0xFFFFFFFF);
3254
e61cf118
JC		 3255 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3256 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3257 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3258 DW_MCI_ERROR_FLAGS);
e61cf118
JC		 3259 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3260
f95f3850
WN		 3261 for (i = 0; i < host->num_slots; i++) {
3262 struct dw_mci_slot *slot = host->slot[i];
0e3a22c0 3263
f95f3850
WN		 3264 if (!slot)
3265 continue;
ab269128
AK		 3266 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3267 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3268 dw_mci_setup_bus(slot, true);
3269 }
f95f3850 3270 }
fa0c3283
DA		 3271
3272 /* Now that slots are all setup, we can enable card detect */
3273 dw_mci_enable_cd(host);
3274
f95f3850
WN		 3275 return 0;
3276}
62ca8034 3277EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 3278#endif /* CONFIG_PM_SLEEP */
3279
f95f3850
WN		 3280static int __init dw_mci_init(void)
3281{
8e1c4e4d 3282 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
62ca8034 3283 return 0;
f95f3850
WN		 3284}
3285
3286static void __exit dw_mci_exit(void)
3287{
f95f3850
WN		 3288}
3289
3290module_init(dw_mci_init);
3291module_exit(dw_mci_exit);
3292
3293MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3294MODULE_AUTHOR("NXP Semiconductor VietNam");
3295MODULE_AUTHOR("Imagination Technologies Ltd");
3296MODULE_LICENSE("GPL v2");
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