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mmc: dw_mmc-rockchip: add MMC_CAP_CMD23 capabilities
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
b24c8b26 30#include <linux/mmc/card.h>
f95f3850
WN		 31#include <linux/mmc/host.h>
32#include <linux/mmc/mmc.h>
01730558 33#include <linux/mmc/sd.h>
90c2143a 34#include <linux/mmc/sdio.h>
f95f3850
WN		 35#include <linux/mmc/dw_mmc.h>
36#include <linux/bitops.h>
c07946a3 37#include <linux/regulator/consumer.h>
c91eab4b 38#include <linux/of.h>
55a6ceb2 39#include <linux/of_gpio.h>
bf626e55 40#include <linux/mmc/slot-gpio.h>
f95f3850
WN		 41
42#include "dw_mmc.h"
43
44/* Common flag combinations */
3f7eec62 45#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
f95f3850
WN		 46 SDMMC_INT_HTO | SDMMC_INT_SBE | \
47 SDMMC_INT_EBE)
48#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
49 SDMMC_INT_RESP_ERR)
50#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
51 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
52#define DW_MCI_SEND_STATUS 1
53#define DW_MCI_RECV_STATUS 2
54#define DW_MCI_DMA_THRESHOLD 16
55
1f44a2a5
SJ		 56#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
57#define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
58
fc79a4d6
JS		 59#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
60 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
61 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
62 SDMMC_IDMAC_INT_TI)
63
69d99fdc
PT		 64struct idmac_desc_64addr {
65 u32 des0; /* Control Descriptor */
66
67 u32 des1; /* Reserved */
68
69 u32 des2; /*Buffer sizes */
70#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
6687c42f
BD		 71 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
72 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
69d99fdc
PT		 73
74 u32 des3; /* Reserved */
75
76 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
77 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
78
79 u32 des6; /* Lower 32-bits of Next Descriptor Address */
80 u32 des7; /* Upper 32-bits of Next Descriptor Address */
81};
82
f95f3850 83struct idmac_desc {
6687c42f 84 __le32 des0; /* Control Descriptor */
f95f3850
WN		 85#define IDMAC_DES0_DIC BIT(1)
86#define IDMAC_DES0_LD BIT(2)
87#define IDMAC_DES0_FD BIT(3)
88#define IDMAC_DES0_CH BIT(4)
89#define IDMAC_DES0_ER BIT(5)
90#define IDMAC_DES0_CES BIT(30)
91#define IDMAC_DES0_OWN BIT(31)
92
6687c42f 93 __le32 des1; /* Buffer sizes */
f95f3850 94#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 95 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850 96
6687c42f 97 __le32 des2; /* buffer 1 physical address */
f95f3850 98
6687c42f 99 __le32 des3; /* buffer 2 physical address */
f95f3850 100};
5959b32e
AB		 101
102/* Each descriptor can transfer up to 4KB of data in chained mode */
103#define DW_MCI_DESC_DATA_LENGTH 0x1000
f95f3850 104
3a33a94c 105static bool dw_mci_reset(struct dw_mci *host);
536f6b91 106static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset);
0bdbd0e8 107static int dw_mci_card_busy(struct mmc_host *mmc);
31bff450 108
f95f3850
WN		 109#if defined(CONFIG_DEBUG_FS)
110static int dw_mci_req_show(struct seq_file *s, void *v)
111{
112 struct dw_mci_slot *slot = s->private;
113 struct mmc_request *mrq;
114 struct mmc_command *cmd;
115 struct mmc_command *stop;
116 struct mmc_data *data;
117
118 /* Make sure we get a consistent snapshot */
119 spin_lock_bh(&slot->host->lock);
120 mrq = slot->mrq;
121
122 if (mrq) {
123 cmd = mrq->cmd;
124 data = mrq->data;
125 stop = mrq->stop;
126
127 if (cmd)
128 seq_printf(s,
129 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
130 cmd->opcode, cmd->arg, cmd->flags,
131 cmd->resp[0], cmd->resp[1], cmd->resp[2],
132 cmd->resp[2], cmd->error);
133 if (data)
134 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
135 data->bytes_xfered, data->blocks,
136 data->blksz, data->flags, data->error);
137 if (stop)
138 seq_printf(s,
139 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
140 stop->opcode, stop->arg, stop->flags,
141 stop->resp[0], stop->resp[1], stop->resp[2],
142 stop->resp[2], stop->error);
143 }
144
145 spin_unlock_bh(&slot->host->lock);
146
147 return 0;
148}
149
150static int dw_mci_req_open(struct inode *inode, struct file *file)
151{
152 return single_open(file, dw_mci_req_show, inode->i_private);
153}
154
155static const struct file_operations dw_mci_req_fops = {
156 .owner = THIS_MODULE,
157 .open = dw_mci_req_open,
158 .read = seq_read,
159 .llseek = seq_lseek,
160 .release = single_release,
161};
162
163static int dw_mci_regs_show(struct seq_file *s, void *v)
164{
165 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
166 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
167 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
168 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
169 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
170 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
171
172 return 0;
173}
174
175static int dw_mci_regs_open(struct inode *inode, struct file *file)
176{
177 return single_open(file, dw_mci_regs_show, inode->i_private);
178}
179
180static const struct file_operations dw_mci_regs_fops = {
181 .owner = THIS_MODULE,
182 .open = dw_mci_regs_open,
183 .read = seq_read,
184 .llseek = seq_lseek,
185 .release = single_release,
186};
187
188static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
189{
190 struct mmc_host *mmc = slot->mmc;
191 struct dw_mci *host = slot->host;
192 struct dentry *root;
193 struct dentry *node;
194
195 root = mmc->debugfs_root;
196 if (!root)
197 return;
198
199 node = debugfs_create_file("regs", S_IRUSR, root, host,
200 &dw_mci_regs_fops);
201 if (!node)
202 goto err;
203
204 node = debugfs_create_file("req", S_IRUSR, root, slot,
205 &dw_mci_req_fops);
206 if (!node)
207 goto err;
208
209 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
210 if (!node)
211 goto err;
212
213 node = debugfs_create_x32("pending_events", S_IRUSR, root,
214 (u32 *)&host->pending_events);
215 if (!node)
216 goto err;
217
218 node = debugfs_create_x32("completed_events", S_IRUSR, root,
219 (u32 *)&host->completed_events);
220 if (!node)
221 goto err;
222
223 return;
224
225err:
226 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
227}
228#endif /* defined(CONFIG_DEBUG_FS) */
229
01730558
DA		 230static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg);
231
f95f3850
WN		 232static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
233{
234 struct mmc_data *data;
800d78bf 235 struct dw_mci_slot *slot = mmc_priv(mmc);
01730558 236 struct dw_mci *host = slot->host;
f95f3850 237 u32 cmdr;
f95f3850 238
0e3a22c0 239 cmd->error = -EINPROGRESS;
f95f3850
WN		 240 cmdr = cmd->opcode;
241
90c2143a
SJ		 242 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
243 cmd->opcode == MMC_GO_IDLE_STATE ||
244 cmd->opcode == MMC_GO_INACTIVE_STATE ||
245 (cmd->opcode == SD_IO_RW_DIRECT &&
246 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
f95f3850 247 cmdr |= SDMMC_CMD_STOP;
4a1b27ad
JC		 248 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
249 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
f95f3850 250
01730558
DA		 251 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
252 u32 clk_en_a;
253
254 /* Special bit makes CMD11 not die */
255 cmdr |= SDMMC_CMD_VOLT_SWITCH;
256
257 /* Change state to continue to handle CMD11 weirdness */
258 WARN_ON(slot->host->state != STATE_SENDING_CMD);
259 slot->host->state = STATE_SENDING_CMD11;
260
261 /*
262 * We need to disable low power mode (automatic clock stop)
263 * while doing voltage switch so we don't confuse the card,
264 * since stopping the clock is a specific part of the UHS
265 * voltage change dance.
266 *
267 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
268 * unconditionally turned back on in dw_mci_setup_bus() if it's
269 * ever called with a non-zero clock. That shouldn't happen
270 * until the voltage change is all done.
271 */
272 clk_en_a = mci_readl(host, CLKENA);
273 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
274 mci_writel(host, CLKENA, clk_en_a);
275 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
276 SDMMC_CMD_PRV_DAT_WAIT, 0);
277 }
278
f95f3850
WN		 279 if (cmd->flags & MMC_RSP_PRESENT) {
280 /* We expect a response, so set this bit */
281 cmdr |= SDMMC_CMD_RESP_EXP;
282 if (cmd->flags & MMC_RSP_136)
283 cmdr |= SDMMC_CMD_RESP_LONG;
284 }
285
286 if (cmd->flags & MMC_RSP_CRC)
287 cmdr |= SDMMC_CMD_RESP_CRC;
288
289 data = cmd->data;
290 if (data) {
291 cmdr |= SDMMC_CMD_DAT_EXP;
f95f3850
WN		 292 if (data->flags & MMC_DATA_WRITE)
293 cmdr |= SDMMC_CMD_DAT_WR;
294 }
295
aaaaeb7a
JC		 296 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
297 cmdr |= SDMMC_CMD_USE_HOLD_REG;
800d78bf 298
f95f3850
WN		 299 return cmdr;
300}
301
90c2143a
SJ		 302static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
303{
304 struct mmc_command *stop;
305 u32 cmdr;
306
307 if (!cmd->data)
308 return 0;
309
310 stop = &host->stop_abort;
311 cmdr = cmd->opcode;
312 memset(stop, 0, sizeof(struct mmc_command));
313
314 if (cmdr == MMC_READ_SINGLE_BLOCK ||
315 cmdr == MMC_READ_MULTIPLE_BLOCK ||
316 cmdr == MMC_WRITE_BLOCK ||
6c2c6506
UH		 317 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
318 cmdr == MMC_SEND_TUNING_BLOCK ||
319 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
90c2143a
SJ		 320 stop->opcode = MMC_STOP_TRANSMISSION;
321 stop->arg = 0;
322 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
323 } else if (cmdr == SD_IO_RW_EXTENDED) {
324 stop->opcode = SD_IO_RW_DIRECT;
325 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
326 ((cmd->arg >> 28) & 0x7);
327 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
328 } else {
329 return 0;
330 }
331
332 cmdr = stop->opcode | SDMMC_CMD_STOP |
333 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
334
335 return cmdr;
336}
337
0bdbd0e8
DA		 338static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
339{
340 unsigned long timeout = jiffies + msecs_to_jiffies(500);
341
342 /*
343 * Databook says that before issuing a new data transfer command
344 * we need to check to see if the card is busy. Data transfer commands
345 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
346 *
347 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
348 * expected.
349 */
350 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
351 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
352 while (mci_readl(host, STATUS) & SDMMC_STATUS_BUSY) {
353 if (time_after(jiffies, timeout)) {
354 /* Command will fail; we'll pass error then */
355 dev_err(host->dev, "Busy; trying anyway\n");
356 break;
357 }
358 udelay(10);
359 }
360 }
361}
362
f95f3850
WN		 363static void dw_mci_start_command(struct dw_mci *host,
364 struct mmc_command *cmd, u32 cmd_flags)
365{
366 host->cmd = cmd;
4a90920c 367 dev_vdbg(host->dev,
f95f3850
WN		 368 "start command: ARGR=0x%08x CMDR=0x%08x\n",
369 cmd->arg, cmd_flags);
370
371 mci_writel(host, CMDARG, cmd->arg);
0e3a22c0 372 wmb(); /* drain writebuffer */
0bdbd0e8 373 dw_mci_wait_while_busy(host, cmd_flags);
f95f3850
WN		 374
375 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
376}
377
90c2143a 378static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
f95f3850 379{
90c2143a 380 struct mmc_command *stop = data->stop ? data->stop : &host->stop_abort;
0e3a22c0 381
90c2143a 382 dw_mci_start_command(host, stop, host->stop_cmdr);
f95f3850
WN		 383}
384
385/* DMA interface functions */
386static void dw_mci_stop_dma(struct dw_mci *host)
387{
03e8cb53 388 if (host->using_dma) {
f95f3850
WN		 389 host->dma_ops->stop(host);
390 host->dma_ops->cleanup(host);
f95f3850 391 }
aa50f259
SJ		 392
393 /* Data transfer was stopped by the interrupt handler */
394 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
f95f3850
WN		 395}
396
9aa51408
SJ		 397static int dw_mci_get_dma_dir(struct mmc_data *data)
398{
399 if (data->flags & MMC_DATA_WRITE)
400 return DMA_TO_DEVICE;
401 else
402 return DMA_FROM_DEVICE;
403}
404
f95f3850
WN		 405static void dw_mci_dma_cleanup(struct dw_mci *host)
406{
407 struct mmc_data *data = host->data;
408
409 if (data)
9aa51408 410 if (!data->host_cookie)
4a90920c 411 dma_unmap_sg(host->dev,
9aa51408
SJ		 412 data->sg,
413 data->sg_len,
414 dw_mci_get_dma_dir(data));
f95f3850
WN		 415}
416
5ce9d961
SJ		 417static void dw_mci_idmac_reset(struct dw_mci *host)
418{
419 u32 bmod = mci_readl(host, BMOD);
420 /* Software reset of DMA */
421 bmod |= SDMMC_IDMAC_SWRESET;
422 mci_writel(host, BMOD, bmod);
423}
424
f95f3850
WN		 425static void dw_mci_idmac_stop_dma(struct dw_mci *host)
426{
427 u32 temp;
428
429 /* Disable and reset the IDMAC interface */
430 temp = mci_readl(host, CTRL);
431 temp &= ~SDMMC_CTRL_USE_IDMAC;
432 temp |= SDMMC_CTRL_DMA_RESET;
433 mci_writel(host, CTRL, temp);
434
435 /* Stop the IDMAC running */
436 temp = mci_readl(host, BMOD);
a5289a43 437 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
5ce9d961 438 temp |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 439 mci_writel(host, BMOD, temp);
440}
441
3fc7eaef 442static void dw_mci_dmac_complete_dma(void *arg)
f95f3850 443{
3fc7eaef 444 struct dw_mci *host = arg;
f95f3850
WN		 445 struct mmc_data *data = host->data;
446
4a90920c 447 dev_vdbg(host->dev, "DMA complete\n");
f95f3850 448
3fc7eaef
SL		 449 if ((host->use_dma == TRANS_MODE_EDMAC) &&
450 data && (data->flags & MMC_DATA_READ))
451 /* Invalidate cache after read */
452 dma_sync_sg_for_cpu(mmc_dev(host->cur_slot->mmc),
453 data->sg,
454 data->sg_len,
455 DMA_FROM_DEVICE);
456
f95f3850
WN		 457 host->dma_ops->cleanup(host);
458
459 /*
460 * If the card was removed, data will be NULL. No point in trying to
461 * send the stop command or waiting for NBUSY in this case.
462 */
463 if (data) {
464 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
465 tasklet_schedule(&host->tasklet);
466 }
467}
468
469static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
470 unsigned int sg_len)
471{
5959b32e 472 unsigned int desc_len;
f95f3850 473 int i;
0e3a22c0 474
69d99fdc 475 if (host->dma_64bit_address == 1) {
5959b32e
AB		 476 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
477
478 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 479
5959b32e 480 for (i = 0; i < sg_len; i++) {
69d99fdc 481 unsigned int length = sg_dma_len(&data->sg[i]);
0e3a22c0 482
69d99fdc 483 u64 mem_addr = sg_dma_address(&data->sg[i]);
f95f3850 484
5959b32e
AB		 485 for ( ; length ; desc++) {
486 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
487 length : DW_MCI_DESC_DATA_LENGTH;
488
489 length -= desc_len;
490
491 /*
492 * Set the OWN bit and disable interrupts
493 * for this descriptor
494 */
495 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
496 IDMAC_DES0_CH;
497
498 /* Buffer length */
499 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
500
501 /* Physical address to DMA to/from */
502 desc->des4 = mem_addr & 0xffffffff;
503 desc->des5 = mem_addr >> 32;
504
505 /* Update physical address for the next desc */
506 mem_addr += desc_len;
507
508 /* Save pointer to the last descriptor */
509 desc_last = desc;
510 }
69d99fdc 511 }
f95f3850 512
69d99fdc 513 /* Set first descriptor */
5959b32e 514 desc_first->des0 |= IDMAC_DES0_FD;
f95f3850 515
69d99fdc 516 /* Set last descriptor */
5959b32e
AB		 517 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
518 desc_last->des0 |= IDMAC_DES0_LD;
f95f3850 519
69d99fdc 520 } else {
5959b32e
AB		 521 struct idmac_desc *desc_first, *desc_last, *desc;
522
523 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 524
5959b32e 525 for (i = 0; i < sg_len; i++) {
69d99fdc 526 unsigned int length = sg_dma_len(&data->sg[i]);
0e3a22c0 527
69d99fdc
PT		 528 u32 mem_addr = sg_dma_address(&data->sg[i]);
529
5959b32e
AB		 530 for ( ; length ; desc++) {
531 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
532 length : DW_MCI_DESC_DATA_LENGTH;
533
534 length -= desc_len;
535
536 /*
537 * Set the OWN bit and disable interrupts
538 * for this descriptor
539 */
540 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
541 IDMAC_DES0_DIC |
542 IDMAC_DES0_CH);
543
544 /* Buffer length */
545 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
f95f3850 546
5959b32e
AB		 547 /* Physical address to DMA to/from */
548 desc->des2 = cpu_to_le32(mem_addr);
549
550 /* Update physical address for the next desc */
551 mem_addr += desc_len;
552
553 /* Save pointer to the last descriptor */
554 desc_last = desc;
555 }
69d99fdc
PT		 556 }
557
558 /* Set first descriptor */
5959b32e 559 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
f95f3850 560
69d99fdc 561 /* Set last descriptor */
5959b32e
AB		 562 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
563 IDMAC_DES0_DIC));
564 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
69d99fdc 565 }
f95f3850 566
0e3a22c0 567 wmb(); /* drain writebuffer */
f95f3850
WN		 568}
569
3fc7eaef 570static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
f95f3850
WN		 571{
572 u32 temp;
573
574 dw_mci_translate_sglist(host, host->data, sg_len);
575
536f6b91
SR		 576 /* Make sure to reset DMA in case we did PIO before this */
577 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
578 dw_mci_idmac_reset(host);
579
f95f3850
WN		 580 /* Select IDMAC interface */
581 temp = mci_readl(host, CTRL);
582 temp |= SDMMC_CTRL_USE_IDMAC;
583 mci_writel(host, CTRL, temp);
584
0e3a22c0 585 /* drain writebuffer */
f95f3850
WN		 586 wmb();
587
588 /* Enable the IDMAC */
589 temp = mci_readl(host, BMOD);
a5289a43 590 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 591 mci_writel(host, BMOD, temp);
592
593 /* Start it running */
594 mci_writel(host, PLDMND, 1);
3fc7eaef
SL		 595
596 return 0;
f95f3850
WN		 597}
598
599static int dw_mci_idmac_init(struct dw_mci *host)
600{
897b69e7 601 int i;
f95f3850 602
69d99fdc
PT		 603 if (host->dma_64bit_address == 1) {
604 struct idmac_desc_64addr *p;
605 /* Number of descriptors in the ring buffer */
606 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc_64addr);
607
608 /* Forward link the descriptor list */
609 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
610 i++, p++) {
611 p->des6 = (host->sg_dma +
612 (sizeof(struct idmac_desc_64addr) *
613 (i + 1))) & 0xffffffff;
614
615 p->des7 = (u64)(host->sg_dma +
616 (sizeof(struct idmac_desc_64addr) *
617 (i + 1))) >> 32;
618 /* Initialize reserved and buffer size fields to "0" */
619 p->des1 = 0;
620 p->des2 = 0;
621 p->des3 = 0;
622 }
f95f3850 623
69d99fdc
PT		 624 /* Set the last descriptor as the end-of-ring descriptor */
625 p->des6 = host->sg_dma & 0xffffffff;
626 p->des7 = (u64)host->sg_dma >> 32;
627 p->des0 = IDMAC_DES0_ER;
f95f3850 628
69d99fdc
PT		 629 } else {
630 struct idmac_desc *p;
631 /* Number of descriptors in the ring buffer */
632 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
633
634 /* Forward link the descriptor list */
0e3a22c0
SL		 635 for (i = 0, p = host->sg_cpu;
636 i < host->ring_size - 1;
637 i++, p++) {
6687c42f
BD		 638 p->des3 = cpu_to_le32(host->sg_dma +
639 (sizeof(struct idmac_desc) * (i + 1)));
4b244724
ZG		 640 p->des1 = 0;
641 }
69d99fdc
PT		 642
643 /* Set the last descriptor as the end-of-ring descriptor */
6687c42f
BD		 644 p->des3 = cpu_to_le32(host->sg_dma);
645 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
69d99fdc 646 }
f95f3850 647
5ce9d961 648 dw_mci_idmac_reset(host);
141a712a 649
69d99fdc
PT		 650 if (host->dma_64bit_address == 1) {
651 /* Mask out interrupts - get Tx & Rx complete only */
652 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
653 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
654 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
655
656 /* Set the descriptor base address */
657 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
658 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
659
660 } else {
661 /* Mask out interrupts - get Tx & Rx complete only */
662 mci_writel(host, IDSTS, IDMAC_INT_CLR);
663 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
664 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
665
666 /* Set the descriptor base address */
667 mci_writel(host, DBADDR, host->sg_dma);
668 }
f95f3850 669
f95f3850
WN		 670 return 0;
671}
672
8e2b36ea 673static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 674 .init = dw_mci_idmac_init,
675 .start = dw_mci_idmac_start_dma,
676 .stop = dw_mci_idmac_stop_dma,
3fc7eaef
SL		 677 .complete = dw_mci_dmac_complete_dma,
678 .cleanup = dw_mci_dma_cleanup,
679};
680
681static void dw_mci_edmac_stop_dma(struct dw_mci *host)
682{
ab925a31 683 dmaengine_terminate_async(host->dms->ch);
3fc7eaef
SL		 684}
685
686static int dw_mci_edmac_start_dma(struct dw_mci *host,
687 unsigned int sg_len)
688{
689 struct dma_slave_config cfg;
690 struct dma_async_tx_descriptor *desc = NULL;
691 struct scatterlist *sgl = host->data->sg;
692 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
693 u32 sg_elems = host->data->sg_len;
694 u32 fifoth_val;
695 u32 fifo_offset = host->fifo_reg - host->regs;
696 int ret = 0;
697
698 /* Set external dma config: burst size, burst width */
260b3164 699 cfg.dst_addr = host->phy_regs + fifo_offset;
3fc7eaef
SL		 700 cfg.src_addr = cfg.dst_addr;
701 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
702 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
703
704 /* Match burst msize with external dma config */
705 fifoth_val = mci_readl(host, FIFOTH);
706 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
707 cfg.src_maxburst = cfg.dst_maxburst;
708
709 if (host->data->flags & MMC_DATA_WRITE)
710 cfg.direction = DMA_MEM_TO_DEV;
711 else
712 cfg.direction = DMA_DEV_TO_MEM;
713
714 ret = dmaengine_slave_config(host->dms->ch, &cfg);
715 if (ret) {
716 dev_err(host->dev, "Failed to config edmac.\n");
717 return -EBUSY;
718 }
719
720 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
721 sg_len, cfg.direction,
722 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
723 if (!desc) {
724 dev_err(host->dev, "Can't prepare slave sg.\n");
725 return -EBUSY;
726 }
727
728 /* Set dw_mci_dmac_complete_dma as callback */
729 desc->callback = dw_mci_dmac_complete_dma;
730 desc->callback_param = (void *)host;
731 dmaengine_submit(desc);
732
733 /* Flush cache before write */
734 if (host->data->flags & MMC_DATA_WRITE)
735 dma_sync_sg_for_device(mmc_dev(host->cur_slot->mmc), sgl,
736 sg_elems, DMA_TO_DEVICE);
737
738 dma_async_issue_pending(host->dms->ch);
739
740 return 0;
741}
742
743static int dw_mci_edmac_init(struct dw_mci *host)
744{
745 /* Request external dma channel */
746 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
747 if (!host->dms)
748 return -ENOMEM;
749
750 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
751 if (!host->dms->ch) {
4539d36e 752 dev_err(host->dev, "Failed to get external DMA channel.\n");
3fc7eaef
SL		 753 kfree(host->dms);
754 host->dms = NULL;
755 return -ENXIO;
756 }
757
758 return 0;
759}
760
761static void dw_mci_edmac_exit(struct dw_mci *host)
762{
763 if (host->dms) {
764 if (host->dms->ch) {
765 dma_release_channel(host->dms->ch);
766 host->dms->ch = NULL;
767 }
768 kfree(host->dms);
769 host->dms = NULL;
770 }
771}
772
773static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
774 .init = dw_mci_edmac_init,
775 .exit = dw_mci_edmac_exit,
776 .start = dw_mci_edmac_start_dma,
777 .stop = dw_mci_edmac_stop_dma,
778 .complete = dw_mci_dmac_complete_dma,
885c3e80
SJ		 779 .cleanup = dw_mci_dma_cleanup,
780};
885c3e80 781
9aa51408
SJ		 782static int dw_mci_pre_dma_transfer(struct dw_mci *host,
783 struct mmc_data *data,
784 bool next)
f95f3850
WN		 785{
786 struct scatterlist *sg;
9aa51408 787 unsigned int i, sg_len;
03e8cb53 788
9aa51408
SJ		 789 if (!next && data->host_cookie)
790 return data->host_cookie;
f95f3850
WN		 791
792 /*
793 * We don't do DMA on "complex" transfers, i.e. with
794 * non-word-aligned buffers or lengths. Also, we don't bother
795 * with all the DMA setup overhead for short transfers.
796 */
797 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
798 return -EINVAL;
9aa51408 799
f95f3850
WN		 800 if (data->blksz & 3)
801 return -EINVAL;
802
803 for_each_sg(data->sg, sg, data->sg_len, i) {
804 if (sg->offset & 3 || sg->length & 3)
805 return -EINVAL;
806 }
807
4a90920c 808 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 809 data->sg,
810 data->sg_len,
811 dw_mci_get_dma_dir(data));
812 if (sg_len == 0)
813 return -EINVAL;
03e8cb53 814
9aa51408
SJ		 815 if (next)
816 data->host_cookie = sg_len;
f95f3850 817
9aa51408
SJ		 818 return sg_len;
819}
820
9aa51408
SJ		 821static void dw_mci_pre_req(struct mmc_host *mmc,
822 struct mmc_request *mrq,
823 bool is_first_req)
824{
825 struct dw_mci_slot *slot = mmc_priv(mmc);
826 struct mmc_data *data = mrq->data;
827
828 if (!slot->host->use_dma || !data)
829 return;
830
831 if (data->host_cookie) {
832 data->host_cookie = 0;
833 return;
834 }
835
836 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
837 data->host_cookie = 0;
838}
839
840static void dw_mci_post_req(struct mmc_host *mmc,
841 struct mmc_request *mrq,
842 int err)
843{
844 struct dw_mci_slot *slot = mmc_priv(mmc);
845 struct mmc_data *data = mrq->data;
846
847 if (!slot->host->use_dma || !data)
848 return;
849
850 if (data->host_cookie)
4a90920c 851 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 852 data->sg,
853 data->sg_len,
854 dw_mci_get_dma_dir(data));
855 data->host_cookie = 0;
856}
857
52426899
SJ		 858static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
859{
52426899
SJ		 860 unsigned int blksz = data->blksz;
861 const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
862 u32 fifo_width = 1 << host->data_shift;
863 u32 blksz_depth = blksz / fifo_width, fifoth_val;
864 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
0e3a22c0 865 int idx = ARRAY_SIZE(mszs) - 1;
52426899 866
3fc7eaef
SL		 867 /* pio should ship this scenario */
868 if (!host->use_dma)
869 return;
870
52426899
SJ		 871 tx_wmark = (host->fifo_depth) / 2;
872 tx_wmark_invers = host->fifo_depth - tx_wmark;
873
874 /*
875 * MSIZE is '1',
876 * if blksz is not a multiple of the FIFO width
877 */
878 if (blksz % fifo_width) {
879 msize = 0;
880 rx_wmark = 1;
881 goto done;
882 }
883
884 do {
885 if (!((blksz_depth % mszs[idx]) ||
886 (tx_wmark_invers % mszs[idx]))) {
887 msize = idx;
888 rx_wmark = mszs[idx] - 1;
889 break;
890 }
891 } while (--idx > 0);
892 /*
893 * If idx is '0', it won't be tried
894 * Thus, initial values are uesed
895 */
896done:
897 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
898 mci_writel(host, FIFOTH, fifoth_val);
52426899
SJ		 899}
900
f1d2736c
SJ		 901static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
902{
903 unsigned int blksz = data->blksz;
904 u32 blksz_depth, fifo_depth;
905 u16 thld_size;
906
907 WARN_ON(!(data->flags & MMC_DATA_READ));
908
66dfd101
JH		 909 /*
910 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
911 * in the FIFO region, so we really shouldn't access it).
912 */
913 if (host->verid < DW_MMC_240A)
914 return;
915
f1d2736c 916 if (host->timing != MMC_TIMING_MMC_HS200 &&
488b8d63 917 host->timing != MMC_TIMING_MMC_HS400 &&
f1d2736c
SJ		 918 host->timing != MMC_TIMING_UHS_SDR104)
919 goto disable;
920
921 blksz_depth = blksz / (1 << host->data_shift);
922 fifo_depth = host->fifo_depth;
923
924 if (blksz_depth > fifo_depth)
925 goto disable;
926
927 /*
928 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
929 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
930 * Currently just choose blksz.
931 */
932 thld_size = blksz;
933 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
934 return;
935
936disable:
937 mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
938}
939
9aa51408
SJ		 940static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
941{
f8c58c11 942 unsigned long irqflags;
9aa51408
SJ		 943 int sg_len;
944 u32 temp;
945
946 host->using_dma = 0;
947
948 /* If we don't have a channel, we can't do DMA */
949 if (!host->use_dma)
950 return -ENODEV;
951
952 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 953 if (sg_len < 0) {
954 host->dma_ops->stop(host);
9aa51408 955 return sg_len;
a99aa9b9 956 }
9aa51408
SJ		 957
958 host->using_dma = 1;
f95f3850 959
3fc7eaef
SL		 960 if (host->use_dma == TRANS_MODE_IDMAC)
961 dev_vdbg(host->dev,
962 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
963 (unsigned long)host->sg_cpu,
964 (unsigned long)host->sg_dma,
965 sg_len);
f95f3850 966
52426899
SJ		 967 /*
968 * Decide the MSIZE and RX/TX Watermark.
969 * If current block size is same with previous size,
970 * no need to update fifoth.
971 */
972 if (host->prev_blksz != data->blksz)
973 dw_mci_adjust_fifoth(host, data);
974
f95f3850
WN		 975 /* Enable the DMA interface */
976 temp = mci_readl(host, CTRL);
977 temp |= SDMMC_CTRL_DMA_ENABLE;
978 mci_writel(host, CTRL, temp);
979
980 /* Disable RX/TX IRQs, let DMA handle it */
f8c58c11 981 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 982 temp = mci_readl(host, INTMASK);
983 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
984 mci_writel(host, INTMASK, temp);
f8c58c11 985 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850 986
3fc7eaef
SL		 987 if (host->dma_ops->start(host, sg_len)) {
988 /* We can't do DMA */
989 dev_err(host->dev, "%s: failed to start DMA.\n", __func__);
990 return -ENODEV;
991 }
f95f3850
WN		 992
993 return 0;
994}
995
996static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
997{
f8c58c11 998 unsigned long irqflags;
0e3a22c0 999 int flags = SG_MITER_ATOMIC;
f95f3850
WN		 1000 u32 temp;
1001
1002 data->error = -EINPROGRESS;
1003
1004 WARN_ON(host->data);
1005 host->sg = NULL;
1006 host->data = data;
1007
f1d2736c 1008 if (data->flags & MMC_DATA_READ) {
55c5efbc 1009 host->dir_status = DW_MCI_RECV_STATUS;
f1d2736c
SJ		 1010 dw_mci_ctrl_rd_thld(host, data);
1011 } else {
55c5efbc 1012 host->dir_status = DW_MCI_SEND_STATUS;
f1d2736c 1013 }
55c5efbc 1014
f95f3850 1015 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 1016 if (host->data->flags & MMC_DATA_READ)
1017 flags |= SG_MITER_TO_SG;
1018 else
1019 flags |= SG_MITER_FROM_SG;
1020
1021 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 1022 host->sg = data->sg;
34b664a2
JH		 1023 host->part_buf_start = 0;
1024 host->part_buf_count = 0;
f95f3850 1025
b40af3aa 1026 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f8c58c11
DA		 1027
1028 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1029 temp = mci_readl(host, INTMASK);
1030 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1031 mci_writel(host, INTMASK, temp);
f8c58c11 1032 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 1033
1034 temp = mci_readl(host, CTRL);
1035 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1036 mci_writel(host, CTRL, temp);
52426899
SJ		 1037
1038 /*
1039 * Use the initial fifoth_val for PIO mode.
1040 * If next issued data may be transfered by DMA mode,
1041 * prev_blksz should be invalidated.
1042 */
1043 mci_writel(host, FIFOTH, host->fifoth_val);
1044 host->prev_blksz = 0;
1045 } else {
1046 /*
1047 * Keep the current block size.
1048 * It will be used to decide whether to update
1049 * fifoth register next time.
1050 */
1051 host->prev_blksz = data->blksz;
f95f3850
WN		 1052 }
1053}
1054
1055static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
1056{
1057 struct dw_mci *host = slot->host;
1058 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1059 unsigned int cmd_status = 0;
1060
1061 mci_writel(host, CMDARG, arg);
0e3a22c0 1062 wmb(); /* drain writebuffer */
0bdbd0e8 1063 dw_mci_wait_while_busy(host, cmd);
f95f3850
WN		 1064 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
1065
1066 while (time_before(jiffies, timeout)) {
1067 cmd_status = mci_readl(host, CMD);
1068 if (!(cmd_status & SDMMC_CMD_START))
1069 return;
1070 }
1071 dev_err(&slot->mmc->class_dev,
1072 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
1073 cmd, arg, cmd_status);
1074}
1075
ab269128 1076static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 1077{
1078 struct dw_mci *host = slot->host;
fdf492a1 1079 unsigned int clock = slot->clock;
f95f3850 1080 u32 div;
9623b5b9 1081 u32 clk_en_a;
01730558
DA		 1082 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1083
1084 /* We must continue to set bit 28 in CMD until the change is complete */
1085 if (host->state == STATE_WAITING_CMD11_DONE)
1086 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
f95f3850 1087
fdf492a1
DA		 1088 if (!clock) {
1089 mci_writel(host, CLKENA, 0);
01730558 1090 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
fdf492a1
DA		 1091 } else if (clock != host->current_speed || force_clkinit) {
1092 div = host->bus_hz / clock;
1093 if (host->bus_hz % clock && host->bus_hz > clock)
f95f3850
WN		 1094 /*
1095 * move the + 1 after the divide to prevent
1096 * over-clocking the card.
1097 */
e419990b
SJ		 1098 div += 1;
1099
fdf492a1 1100 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850 1101
fdf492a1
DA		 1102 if ((clock << div) != slot->__clk_old || force_clkinit)
1103 dev_info(&slot->mmc->class_dev,
1104 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1105 slot->id, host->bus_hz, clock,
1106 div ? ((host->bus_hz / div) >> 1) :
1107 host->bus_hz, div);
f95f3850
WN		 1108
1109 /* disable clock */
1110 mci_writel(host, CLKENA, 0);
1111 mci_writel(host, CLKSRC, 0);
1112
1113 /* inform CIU */
01730558 1114 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850
WN		 1115
1116 /* set clock to desired speed */
1117 mci_writel(host, CLKDIV, div);
1118
1119 /* inform CIU */
01730558 1120 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1121
9623b5b9
DA		 1122 /* enable clock; only low power if no SDIO */
1123 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
b24c8b26 1124 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
9623b5b9
DA		 1125 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1126 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 1127
1128 /* inform CIU */
01730558 1129 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1130
fdf492a1
DA		 1131 /* keep the clock with reflecting clock dividor */
1132 slot->__clk_old = clock << div;
f95f3850
WN		 1133 }
1134
fdf492a1
DA		 1135 host->current_speed = clock;
1136
f95f3850 1137 /* Set the current slot bus width */
1d56c453 1138 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 1139}
1140
053b3ce6
SJ		 1141static void __dw_mci_start_request(struct dw_mci *host,
1142 struct dw_mci_slot *slot,
1143 struct mmc_command *cmd)
f95f3850
WN		 1144{
1145 struct mmc_request *mrq;
f95f3850
WN		 1146 struct mmc_data *data;
1147 u32 cmdflags;
1148
1149 mrq = slot->mrq;
f95f3850 1150
f95f3850
WN		 1151 host->cur_slot = slot;
1152 host->mrq = mrq;
1153
1154 host->pending_events = 0;
1155 host->completed_events = 0;
e352c813 1156 host->cmd_status = 0;
f95f3850 1157 host->data_status = 0;
e352c813 1158 host->dir_status = 0;
f95f3850 1159
053b3ce6 1160 data = cmd->data;
f95f3850 1161 if (data) {
f16afa88 1162 mci_writel(host, TMOUT, 0xFFFFFFFF);
f95f3850
WN		 1163 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1164 mci_writel(host, BLKSIZ, data->blksz);
1165 }
1166
f95f3850
WN		 1167 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1168
1169 /* this is the first command, send the initialization clock */
1170 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1171 cmdflags |= SDMMC_CMD_INIT;
1172
1173 if (data) {
1174 dw_mci_submit_data(host, data);
0e3a22c0 1175 wmb(); /* drain writebuffer */
f95f3850
WN		 1176 }
1177
1178 dw_mci_start_command(host, cmd, cmdflags);
1179
5c935165 1180 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
49ba0302
DA		 1181 unsigned long irqflags;
1182
5c935165 1183 /*
8886a6fd
DA		 1184 * Databook says to fail after 2ms w/ no response, but evidence
1185 * shows that sometimes the cmd11 interrupt takes over 130ms.
1186 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1187 * is just about to roll over.
49ba0302
DA		 1188 *
1189 * We do this whole thing under spinlock and only if the
1190 * command hasn't already completed (indicating the the irq
1191 * already ran so we don't want the timeout).
5c935165 1192 */
49ba0302
DA		 1193 spin_lock_irqsave(&host->irq_lock, irqflags);
1194 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1195 mod_timer(&host->cmd11_timer,
1196 jiffies + msecs_to_jiffies(500) + 1);
1197 spin_unlock_irqrestore(&host->irq_lock, irqflags);
5c935165
DA		 1198 }
1199
f95f3850
WN		 1200 if (mrq->stop)
1201 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
90c2143a
SJ		 1202 else
1203 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
f95f3850
WN		 1204}
1205
053b3ce6
SJ		 1206static void dw_mci_start_request(struct dw_mci *host,
1207 struct dw_mci_slot *slot)
1208{
1209 struct mmc_request *mrq = slot->mrq;
1210 struct mmc_command *cmd;
1211
1212 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1213 __dw_mci_start_request(host, slot, cmd);
1214}
1215
7456caae 1216/* must be called with host->lock held */
f95f3850
WN		 1217static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1218 struct mmc_request *mrq)
1219{
1220 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1221 host->state);
1222
f95f3850
WN		 1223 slot->mrq = mrq;
1224
01730558
DA		 1225 if (host->state == STATE_WAITING_CMD11_DONE) {
1226 dev_warn(&slot->mmc->class_dev,
1227 "Voltage change didn't complete\n");
1228 /*
1229 * this case isn't expected to happen, so we can
1230 * either crash here or just try to continue on
1231 * in the closest possible state
1232 */
1233 host->state = STATE_IDLE;
1234 }
1235
f95f3850
WN		 1236 if (host->state == STATE_IDLE) {
1237 host->state = STATE_SENDING_CMD;
1238 dw_mci_start_request(host, slot);
1239 } else {
1240 list_add_tail(&slot->queue_node, &host->queue);
1241 }
f95f3850
WN		 1242}
1243
1244static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1245{
1246 struct dw_mci_slot *slot = mmc_priv(mmc);
1247 struct dw_mci *host = slot->host;
1248
1249 WARN_ON(slot->mrq);
1250
7456caae
JH		 1251 /*
1252 * The check for card presence and queueing of the request must be
1253 * atomic, otherwise the card could be removed in between and the
1254 * request wouldn't fail until another card was inserted.
1255 */
1256 spin_lock_bh(&host->lock);
1257
f95f3850 1258 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 1259 spin_unlock_bh(&host->lock);
f95f3850
WN		 1260 mrq->cmd->error = -ENOMEDIUM;
1261 mmc_request_done(mmc, mrq);
1262 return;
1263 }
1264
f95f3850 1265 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 1266
1267 spin_unlock_bh(&host->lock);
f95f3850
WN		 1268}
1269
1270static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1271{
1272 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 1273 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 1274 u32 regs;
51da2240 1275 int ret;
f95f3850 1276
f95f3850 1277 switch (ios->bus_width) {
f95f3850
WN		 1278 case MMC_BUS_WIDTH_4:
1279 slot->ctype = SDMMC_CTYPE_4BIT;
1280 break;
c9b2a06f
JC		 1281 case MMC_BUS_WIDTH_8:
1282 slot->ctype = SDMMC_CTYPE_8BIT;
1283 break;
b2f7cb45
JC		 1284 default:
1285 /* set default 1 bit mode */
1286 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 1287 }
1288
3f514291
SJ		 1289 regs = mci_readl(slot->host, UHS_REG);
1290
41babf75 1291 /* DDR mode set */
80113132 1292 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
7cc8d580 1293 ios->timing == MMC_TIMING_UHS_DDR50 ||
80113132 1294 ios->timing == MMC_TIMING_MMC_HS400)
c69042a5 1295 regs |= ((0x1 << slot->id) << 16);
3f514291 1296 else
c69042a5 1297 regs &= ~((0x1 << slot->id) << 16);
3f514291
SJ		 1298
1299 mci_writel(slot->host, UHS_REG, regs);
f1d2736c 1300 slot->host->timing = ios->timing;
41babf75 1301
fdf492a1
DA		 1302 /*
1303 * Use mirror of ios->clock to prevent race with mmc
1304 * core ios update when finding the minimum.
1305 */
1306 slot->clock = ios->clock;
f95f3850 1307
cb27a843
JH		 1308 if (drv_data && drv_data->set_ios)
1309 drv_data->set_ios(slot->host, ios);
800d78bf 1310
f95f3850
WN		 1311 switch (ios->power_mode) {
1312 case MMC_POWER_UP:
51da2240
YC		 1313 if (!IS_ERR(mmc->supply.vmmc)) {
1314 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1315 ios->vdd);
1316 if (ret) {
1317 dev_err(slot->host->dev,
1318 "failed to enable vmmc regulator\n");
1319 /*return, if failed turn on vmmc*/
1320 return;
1321 }
1322 }
29d0d161
DA		 1323 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1324 regs = mci_readl(slot->host, PWREN);
1325 regs |= (1 << slot->id);
1326 mci_writel(slot->host, PWREN, regs);
1327 break;
1328 case MMC_POWER_ON:
d1f1dd86
DA		 1329 if (!slot->host->vqmmc_enabled) {
1330 if (!IS_ERR(mmc->supply.vqmmc)) {
1331 ret = regulator_enable(mmc->supply.vqmmc);
1332 if (ret < 0)
1333 dev_err(slot->host->dev,
1334 "failed to enable vqmmc\n");
1335 else
1336 slot->host->vqmmc_enabled = true;
1337
1338 } else {
1339 /* Keep track so we don't reset again */
51da2240 1340 slot->host->vqmmc_enabled = true;
d1f1dd86
DA		 1341 }
1342
1343 /* Reset our state machine after powering on */
1344 dw_mci_ctrl_reset(slot->host,
1345 SDMMC_CTRL_ALL_RESET_FLAGS);
51da2240 1346 }
655babbd
DA		 1347
1348 /* Adjust clock / bus width after power is up */
1349 dw_mci_setup_bus(slot, false);
1350
e6f34e2f
JH		 1351 break;
1352 case MMC_POWER_OFF:
655babbd
DA		 1353 /* Turn clock off before power goes down */
1354 dw_mci_setup_bus(slot, false);
1355
51da2240
YC		 1356 if (!IS_ERR(mmc->supply.vmmc))
1357 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1358
d1f1dd86 1359 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
51da2240 1360 regulator_disable(mmc->supply.vqmmc);
d1f1dd86 1361 slot->host->vqmmc_enabled = false;
51da2240 1362
4366dcc5
JC		 1363 regs = mci_readl(slot->host, PWREN);
1364 regs &= ~(1 << slot->id);
1365 mci_writel(slot->host, PWREN, regs);
f95f3850
WN		 1366 break;
1367 default:
1368 break;
1369 }
655babbd
DA		 1370
1371 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1372 slot->host->state = STATE_IDLE;
f95f3850
WN		 1373}
1374
01730558
DA		 1375static int dw_mci_card_busy(struct mmc_host *mmc)
1376{
1377 struct dw_mci_slot *slot = mmc_priv(mmc);
1378 u32 status;
1379
1380 /*
1381 * Check the busy bit which is low when DAT[3:0]
1382 * (the data lines) are 0000
1383 */
1384 status = mci_readl(slot->host, STATUS);
1385
1386 return !!(status & SDMMC_STATUS_BUSY);
1387}
1388
1389static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1390{
1391 struct dw_mci_slot *slot = mmc_priv(mmc);
1392 struct dw_mci *host = slot->host;
8f7849c4 1393 const struct dw_mci_drv_data *drv_data = host->drv_data;
01730558
DA		 1394 u32 uhs;
1395 u32 v18 = SDMMC_UHS_18V << slot->id;
01730558
DA		 1396 int ret;
1397
8f7849c4
ZG		 1398 if (drv_data && drv_data->switch_voltage)
1399 return drv_data->switch_voltage(mmc, ios);
1400
01730558
DA		 1401 /*
1402 * Program the voltage. Note that some instances of dw_mmc may use
1403 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1404 * does no harm but you need to set the regulator directly. Try both.
1405 */
1406 uhs = mci_readl(host, UHS_REG);
e0848f5d 1407 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
01730558 1408 uhs &= ~v18;
e0848f5d 1409 else
01730558 1410 uhs |= v18;
e0848f5d 1411
01730558 1412 if (!IS_ERR(mmc->supply.vqmmc)) {
e0848f5d 1413 ret = mmc_regulator_set_vqmmc(mmc, ios);
01730558
DA		 1414
1415 if (ret) {
b19caf37 1416 dev_dbg(&mmc->class_dev,
e0848f5d
DA		 1417 "Regulator set error %d - %s V\n",
1418 ret, uhs & v18 ? "1.8" : "3.3");
01730558
DA		 1419 return ret;
1420 }
1421 }
1422 mci_writel(host, UHS_REG, uhs);
1423
1424 return 0;
1425}
1426
f95f3850
WN		 1427static int dw_mci_get_ro(struct mmc_host *mmc)
1428{
1429 int read_only;
1430 struct dw_mci_slot *slot = mmc_priv(mmc);
9795a846 1431 int gpio_ro = mmc_gpio_get_ro(mmc);
f95f3850
WN		 1432
1433 /* Use platform get_ro function, else try on board write protect */
eff8f2f5 1434 if (!IS_ERR_VALUE(gpio_ro))
9795a846 1435 read_only = gpio_ro;
f95f3850
WN		 1436 else
1437 read_only =
1438 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1439
1440 dev_dbg(&mmc->class_dev, "card is %s\n",
1441 read_only ? "read-only" : "read-write");
1442
1443 return read_only;
1444}
1445
1446static int dw_mci_get_cd(struct mmc_host *mmc)
1447{
1448 int present;
1449 struct dw_mci_slot *slot = mmc_priv(mmc);
7cf347bd
ZG		 1450 struct dw_mci *host = slot->host;
1451 int gpio_cd = mmc_gpio_get_cd(mmc);
f95f3850
WN		 1452
1453 /* Use platform get_cd function, else try onboard card detect */
e8cc37b8 1454 if ((mmc->caps & MMC_CAP_NEEDS_POLL) ||
4de3bf66 1455 (mmc->caps & MMC_CAP_NONREMOVABLE))
fc3d7720 1456 present = 1;
bf626e55 1457 else if (!IS_ERR_VALUE(gpio_cd))
7cf347bd 1458 present = gpio_cd;
f95f3850
WN		 1459 else
1460 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1461 == 0 ? 1 : 0;
1462
7cf347bd 1463 spin_lock_bh(&host->lock);
bf626e55
ZG		 1464 if (present) {
1465 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1466 dev_dbg(&mmc->class_dev, "card is present\n");
bf626e55
ZG		 1467 } else {
1468 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850 1469 dev_dbg(&mmc->class_dev, "card is not present\n");
bf626e55 1470 }
7cf347bd 1471 spin_unlock_bh(&host->lock);
f95f3850
WN		 1472
1473 return present;
1474}
1475
935a665e
SL		 1476static void dw_mci_hw_reset(struct mmc_host *mmc)
1477{
1478 struct dw_mci_slot *slot = mmc_priv(mmc);
1479 struct dw_mci *host = slot->host;
1480 int reset;
1481
1482 if (host->use_dma == TRANS_MODE_IDMAC)
1483 dw_mci_idmac_reset(host);
1484
1485 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1486 SDMMC_CTRL_FIFO_RESET))
1487 return;
1488
1489 /*
1490 * According to eMMC spec, card reset procedure:
1491 * tRstW >= 1us: RST_n pulse width
1492 * tRSCA >= 200us: RST_n to Command time
1493 * tRSTH >= 1us: RST_n high period
1494 */
1495 reset = mci_readl(host, RST_N);
1496 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1497 mci_writel(host, RST_N, reset);
1498 usleep_range(1, 2);
1499 reset |= SDMMC_RST_HWACTIVE << slot->id;
1500 mci_writel(host, RST_N, reset);
1501 usleep_range(200, 300);
1502}
1503
b24c8b26 1504static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
9623b5b9 1505{
b24c8b26 1506 struct dw_mci_slot *slot = mmc_priv(mmc);
9623b5b9 1507 struct dw_mci *host = slot->host;
9623b5b9 1508
b24c8b26
DA		 1509 /*
1510 * Low power mode will stop the card clock when idle. According to the
1511 * description of the CLKENA register we should disable low power mode
1512 * for SDIO cards if we need SDIO interrupts to work.
1513 */
1514 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1515 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1516 u32 clk_en_a_old;
1517 u32 clk_en_a;
9623b5b9 1518
b24c8b26
DA		 1519 clk_en_a_old = mci_readl(host, CLKENA);
1520
1521 if (card->type == MMC_TYPE_SDIO ||
1522 card->type == MMC_TYPE_SD_COMBO) {
1523 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1524 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1525 } else {
1526 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1527 clk_en_a = clk_en_a_old | clken_low_pwr;
1528 }
1529
1530 if (clk_en_a != clk_en_a_old) {
1531 mci_writel(host, CLKENA, clk_en_a);
1532 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1533 SDMMC_CMD_PRV_DAT_WAIT, 0);
1534 }
9623b5b9
DA		 1535 }
1536}
1537
1a5c8e1f
SH		 1538static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1539{
1540 struct dw_mci_slot *slot = mmc_priv(mmc);
1541 struct dw_mci *host = slot->host;
f8c58c11 1542 unsigned long irqflags;
1a5c8e1f
SH		 1543 u32 int_mask;
1544
f8c58c11
DA		 1545 spin_lock_irqsave(&host->irq_lock, irqflags);
1546
1a5c8e1f
SH		 1547 /* Enable/disable Slot Specific SDIO interrupt */
1548 int_mask = mci_readl(host, INTMASK);
b24c8b26
DA		 1549 if (enb)
1550 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1551 else
1552 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1553 mci_writel(host, INTMASK, int_mask);
f8c58c11
DA		 1554
1555 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1a5c8e1f
SH		 1556}
1557
0976f16d
SJ		 1558static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1559{
1560 struct dw_mci_slot *slot = mmc_priv(mmc);
1561 struct dw_mci *host = slot->host;
1562 const struct dw_mci_drv_data *drv_data = host->drv_data;
0e3a22c0 1563 int err = -EINVAL;
0976f16d 1564
0976f16d 1565 if (drv_data && drv_data->execute_tuning)
9979dbe5 1566 err = drv_data->execute_tuning(slot, opcode);
0976f16d
SJ		 1567 return err;
1568}
1569
0e3a22c0
SL		 1570static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1571 struct mmc_ios *ios)
80113132
SJ		 1572{
1573 struct dw_mci_slot *slot = mmc_priv(mmc);
1574 struct dw_mci *host = slot->host;
1575 const struct dw_mci_drv_data *drv_data = host->drv_data;
1576
1577 if (drv_data && drv_data->prepare_hs400_tuning)
1578 return drv_data->prepare_hs400_tuning(host, ios);
1579
1580 return 0;
1581}
1582
f95f3850 1583static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 1584 .request = dw_mci_request,
9aa51408
SJ		 1585 .pre_req = dw_mci_pre_req,
1586 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 1587 .set_ios = dw_mci_set_ios,
1588 .get_ro = dw_mci_get_ro,
1589 .get_cd = dw_mci_get_cd,
935a665e 1590 .hw_reset = dw_mci_hw_reset,
1a5c8e1f 1591 .enable_sdio_irq = dw_mci_enable_sdio_irq,
0976f16d 1592 .execute_tuning = dw_mci_execute_tuning,
01730558
DA		 1593 .card_busy = dw_mci_card_busy,
1594 .start_signal_voltage_switch = dw_mci_switch_voltage,
b24c8b26 1595 .init_card = dw_mci_init_card,
80113132 1596 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
f95f3850
WN		 1597};
1598
1599static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1600 __releases(&host->lock)
1601 __acquires(&host->lock)
1602{
1603 struct dw_mci_slot *slot;
1604 struct mmc_host *prev_mmc = host->cur_slot->mmc;
1605
1606 WARN_ON(host->cmd || host->data);
1607
1608 host->cur_slot->mrq = NULL;
1609 host->mrq = NULL;
1610 if (!list_empty(&host->queue)) {
1611 slot = list_entry(host->queue.next,
1612 struct dw_mci_slot, queue_node);
1613 list_del(&slot->queue_node);
4a90920c 1614 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 1615 mmc_hostname(slot->mmc));
1616 host->state = STATE_SENDING_CMD;
1617 dw_mci_start_request(host, slot);
1618 } else {
4a90920c 1619 dev_vdbg(host->dev, "list empty\n");
01730558
DA		 1620
1621 if (host->state == STATE_SENDING_CMD11)
1622 host->state = STATE_WAITING_CMD11_DONE;
1623 else
1624 host->state = STATE_IDLE;
f95f3850
WN		 1625 }
1626
1627 spin_unlock(&host->lock);
1628 mmc_request_done(prev_mmc, mrq);
1629 spin_lock(&host->lock);
1630}
1631
e352c813 1632static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
f95f3850
WN		 1633{
1634 u32 status = host->cmd_status;
1635
1636 host->cmd_status = 0;
1637
1638 /* Read the response from the card (up to 16 bytes) */
1639 if (cmd->flags & MMC_RSP_PRESENT) {
1640 if (cmd->flags & MMC_RSP_136) {
1641 cmd->resp[3] = mci_readl(host, RESP0);
1642 cmd->resp[2] = mci_readl(host, RESP1);
1643 cmd->resp[1] = mci_readl(host, RESP2);
1644 cmd->resp[0] = mci_readl(host, RESP3);
1645 } else {
1646 cmd->resp[0] = mci_readl(host, RESP0);
1647 cmd->resp[1] = 0;
1648 cmd->resp[2] = 0;
1649 cmd->resp[3] = 0;
1650 }
1651 }
1652
1653 if (status & SDMMC_INT_RTO)
1654 cmd->error = -ETIMEDOUT;
1655 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1656 cmd->error = -EILSEQ;
1657 else if (status & SDMMC_INT_RESP_ERR)
1658 cmd->error = -EIO;
1659 else
1660 cmd->error = 0;
1661
e352c813
SJ		 1662 return cmd->error;
1663}
1664
1665static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1666{
31bff450 1667 u32 status = host->data_status;
e352c813
SJ		 1668
1669 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1670 if (status & SDMMC_INT_DRTO) {
1671 data->error = -ETIMEDOUT;
1672 } else if (status & SDMMC_INT_DCRC) {
1673 data->error = -EILSEQ;
1674 } else if (status & SDMMC_INT_EBE) {
1675 if (host->dir_status ==
1676 DW_MCI_SEND_STATUS) {
1677 /*
1678 * No data CRC status was returned.
1679 * The number of bytes transferred
1680 * will be exaggerated in PIO mode.
1681 */
1682 data->bytes_xfered = 0;
1683 data->error = -ETIMEDOUT;
1684 } else if (host->dir_status ==
1685 DW_MCI_RECV_STATUS) {
1686 data->error = -EIO;
1687 }
1688 } else {
1689 /* SDMMC_INT_SBE is included */
1690 data->error = -EIO;
1691 }
1692
e6cc0123 1693 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
e352c813
SJ		 1694
1695 /*
1696 * After an error, there may be data lingering
31bff450 1697 * in the FIFO
e352c813 1698 */
3a33a94c 1699 dw_mci_reset(host);
e352c813
SJ		 1700 } else {
1701 data->bytes_xfered = data->blocks * data->blksz;
1702 data->error = 0;
1703 }
1704
1705 return data->error;
f95f3850
WN		 1706}
1707
57e10486
AK		 1708static void dw_mci_set_drto(struct dw_mci *host)
1709{
1710 unsigned int drto_clks;
1711 unsigned int drto_ms;
1712
1713 drto_clks = mci_readl(host, TMOUT) >> 8;
1714 drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1715
1716 /* add a bit spare time */
1717 drto_ms += 10;
1718
1719 mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1720}
1721
f95f3850
WN		 1722static void dw_mci_tasklet_func(unsigned long priv)
1723{
1724 struct dw_mci *host = (struct dw_mci *)priv;
1725 struct mmc_data *data;
1726 struct mmc_command *cmd;
e352c813 1727 struct mmc_request *mrq;
f95f3850
WN		 1728 enum dw_mci_state state;
1729 enum dw_mci_state prev_state;
e352c813 1730 unsigned int err;
f95f3850
WN		 1731
1732 spin_lock(&host->lock);
1733
1734 state = host->state;
1735 data = host->data;
e352c813 1736 mrq = host->mrq;
f95f3850
WN		 1737
1738 do {
1739 prev_state = state;
1740
1741 switch (state) {
1742 case STATE_IDLE:
01730558 1743 case STATE_WAITING_CMD11_DONE:
f95f3850
WN		 1744 break;
1745
01730558 1746 case STATE_SENDING_CMD11:
f95f3850
WN		 1747 case STATE_SENDING_CMD:
1748 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1749 &host->pending_events))
1750 break;
1751
1752 cmd = host->cmd;
1753 host->cmd = NULL;
1754 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
e352c813
SJ		 1755 err = dw_mci_command_complete(host, cmd);
1756 if (cmd == mrq->sbc && !err) {
053b3ce6
SJ		 1757 prev_state = state = STATE_SENDING_CMD;
1758 __dw_mci_start_request(host, host->cur_slot,
e352c813 1759 mrq->cmd);
053b3ce6
SJ		 1760 goto unlock;
1761 }
1762
e352c813 1763 if (cmd->data && err) {
71abb133 1764 dw_mci_stop_dma(host);
90c2143a
SJ		 1765 send_stop_abort(host, data);
1766 state = STATE_SENDING_STOP;
1767 break;
71abb133
SJ		 1768 }
1769
e352c813
SJ		 1770 if (!cmd->data || err) {
1771 dw_mci_request_end(host, mrq);
f95f3850
WN		 1772 goto unlock;
1773 }
1774
1775 prev_state = state = STATE_SENDING_DATA;
1776 /* fall through */
1777
1778 case STATE_SENDING_DATA:
2aa35465
DA		 1779 /*
1780 * We could get a data error and never a transfer
1781 * complete so we'd better check for it here.
1782 *
1783 * Note that we don't really care if we also got a
1784 * transfer complete; stopping the DMA and sending an
1785 * abort won't hurt.
1786 */
f95f3850
WN		 1787 if (test_and_clear_bit(EVENT_DATA_ERROR,
1788 &host->pending_events)) {
1789 dw_mci_stop_dma(host);
bdb9a90b 1790 if (data->stop ||
1791 !(host->data_status & (SDMMC_INT_DRTO |
1792 SDMMC_INT_EBE)))
1793 send_stop_abort(host, data);
f95f3850
WN		 1794 state = STATE_DATA_ERROR;
1795 break;
1796 }
1797
1798 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
57e10486
AK		 1799 &host->pending_events)) {
1800 /*
1801 * If all data-related interrupts don't come
1802 * within the given time in reading data state.
1803 */
1804 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1805 (host->dir_status == DW_MCI_RECV_STATUS))
1806 dw_mci_set_drto(host);
f95f3850 1807 break;
57e10486 1808 }
f95f3850
WN		 1809
1810 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2aa35465
DA		 1811
1812 /*
1813 * Handle an EVENT_DATA_ERROR that might have shown up
1814 * before the transfer completed. This might not have
1815 * been caught by the check above because the interrupt
1816 * could have gone off between the previous check and
1817 * the check for transfer complete.
1818 *
1819 * Technically this ought not be needed assuming we
1820 * get a DATA_COMPLETE eventually (we'll notice the
1821 * error and end the request), but it shouldn't hurt.
1822 *
1823 * This has the advantage of sending the stop command.
1824 */
1825 if (test_and_clear_bit(EVENT_DATA_ERROR,
1826 &host->pending_events)) {
1827 dw_mci_stop_dma(host);
bdb9a90b 1828 if (data->stop ||
1829 !(host->data_status & (SDMMC_INT_DRTO |
1830 SDMMC_INT_EBE)))
1831 send_stop_abort(host, data);
2aa35465
DA		 1832 state = STATE_DATA_ERROR;
1833 break;
1834 }
f95f3850 1835 prev_state = state = STATE_DATA_BUSY;
2aa35465 1836
f95f3850
WN		 1837 /* fall through */
1838
1839 case STATE_DATA_BUSY:
1840 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
57e10486
AK		 1841 &host->pending_events)) {
1842 /*
1843 * If data error interrupt comes but data over
1844 * interrupt doesn't come within the given time.
1845 * in reading data state.
1846 */
1847 if ((host->quirks & DW_MCI_QUIRK_BROKEN_DTO) &&
1848 (host->dir_status == DW_MCI_RECV_STATUS))
1849 dw_mci_set_drto(host);
f95f3850 1850 break;
57e10486 1851 }
f95f3850
WN		 1852
1853 host->data = NULL;
1854 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
e352c813
SJ		 1855 err = dw_mci_data_complete(host, data);
1856
1857 if (!err) {
1858 if (!data->stop || mrq->sbc) {
17c8bc85 1859 if (mrq->sbc && data->stop)
e352c813
SJ		 1860 data->stop->error = 0;
1861 dw_mci_request_end(host, mrq);
1862 goto unlock;
f95f3850 1863 }
f95f3850 1864
e352c813
SJ		 1865 /* stop command for open-ended transfer*/
1866 if (data->stop)
1867 send_stop_abort(host, data);
2aa35465
DA		 1868 } else {
1869 /*
1870 * If we don't have a command complete now we'll
1871 * never get one since we just reset everything;
1872 * better end the request.
1873 *
1874 * If we do have a command complete we'll fall
1875 * through to the SENDING_STOP command and
1876 * everything will be peachy keen.
1877 */
1878 if (!test_bit(EVENT_CMD_COMPLETE,
1879 &host->pending_events)) {
1880 host->cmd = NULL;
1881 dw_mci_request_end(host, mrq);
1882 goto unlock;
1883 }
053b3ce6
SJ		 1884 }
1885
e352c813
SJ		 1886 /*
1887 * If err has non-zero,
1888 * stop-abort command has been already issued.
1889 */
f95f3850 1890 prev_state = state = STATE_SENDING_STOP;
e352c813 1891
f95f3850
WN		 1892 /* fall through */
1893
1894 case STATE_SENDING_STOP:
1895 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1896 &host->pending_events))
1897 break;
1898
71abb133 1899 /* CMD error in data command */
31bff450 1900 if (mrq->cmd->error && mrq->data)
3a33a94c 1901 dw_mci_reset(host);
71abb133 1902
f95f3850 1903 host->cmd = NULL;
71abb133 1904 host->data = NULL;
90c2143a 1905
e352c813
SJ		 1906 if (mrq->stop)
1907 dw_mci_command_complete(host, mrq->stop);
90c2143a
SJ		 1908 else
1909 host->cmd_status = 0;
1910
e352c813 1911 dw_mci_request_end(host, mrq);
f95f3850
WN		 1912 goto unlock;
1913
1914 case STATE_DATA_ERROR:
1915 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1916 &host->pending_events))
1917 break;
1918
1919 state = STATE_DATA_BUSY;
1920 break;
1921 }
1922 } while (state != prev_state);
1923
1924 host->state = state;
1925unlock:
1926 spin_unlock(&host->lock);
1927
1928}
1929
34b664a2
JH		 1930/* push final bytes to part_buf, only use during push */
1931static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1932{
34b664a2
JH		 1933 memcpy((void *)&host->part_buf, buf, cnt);
1934 host->part_buf_count = cnt;
1935}
f95f3850 1936
34b664a2
JH		 1937/* append bytes to part_buf, only use during push */
1938static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1939{
1940 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1941 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1942 host->part_buf_count += cnt;
1943 return cnt;
1944}
f95f3850 1945
34b664a2
JH		 1946/* pull first bytes from part_buf, only use during pull */
1947static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1948{
0e3a22c0 1949 cnt = min_t(int, cnt, host->part_buf_count);
34b664a2
JH		 1950 if (cnt) {
1951 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1952 cnt);
1953 host->part_buf_count -= cnt;
1954 host->part_buf_start += cnt;
f95f3850 1955 }
34b664a2 1956 return cnt;
f95f3850
WN		 1957}
1958
34b664a2
JH		 1959/* pull final bytes from the part_buf, assuming it's just been filled */
1960static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1961{
34b664a2
JH		 1962 memcpy(buf, &host->part_buf, cnt);
1963 host->part_buf_start = cnt;
1964 host->part_buf_count = (1 << host->data_shift) - cnt;
1965}
f95f3850 1966
34b664a2
JH		 1967static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1968{
cfbeb59c
MC		 1969 struct mmc_data *data = host->data;
1970 int init_cnt = cnt;
1971
34b664a2
JH		 1972 /* try and push anything in the part_buf */
1973 if (unlikely(host->part_buf_count)) {
1974 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 1975
34b664a2
JH		 1976 buf += len;
1977 cnt -= len;
cfbeb59c 1978 if (host->part_buf_count == 2) {
76184ac1 1979 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 1980 host->part_buf_count = 0;
1981 }
1982 }
1983#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1984 if (unlikely((unsigned long)buf & 0x1)) {
1985 while (cnt >= 2) {
1986 u16 aligned_buf[64];
1987 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1988 int items = len >> 1;
1989 int i;
1990 /* memcpy from input buffer into aligned buffer */
1991 memcpy(aligned_buf, buf, len);
1992 buf += len;
1993 cnt -= len;
1994 /* push data from aligned buffer into fifo */
1995 for (i = 0; i < items; ++i)
76184ac1 1996 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 1997 }
1998 } else
1999#endif
2000 {
2001 u16 *pdata = buf;
0e3a22c0 2002
34b664a2 2003 for (; cnt >= 2; cnt -= 2)
76184ac1 2004 mci_fifo_writew(host->fifo_reg, *pdata++);
34b664a2
JH		 2005 buf = pdata;
2006 }
2007 /* put anything remaining in the part_buf */
2008 if (cnt) {
2009 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2010 /* Push data if we have reached the expected data length */
2011 if ((data->bytes_xfered + init_cnt) ==
2012 (data->blksz * data->blocks))
76184ac1 2013 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 2014 }
2015}
f95f3850 2016
34b664a2
JH		 2017static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2018{
2019#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2020 if (unlikely((unsigned long)buf & 0x1)) {
2021 while (cnt >= 2) {
2022 /* pull data from fifo into aligned buffer */
2023 u16 aligned_buf[64];
2024 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2025 int items = len >> 1;
2026 int i;
0e3a22c0 2027
34b664a2 2028 for (i = 0; i < items; ++i)
76184ac1 2029 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2030 /* memcpy from aligned buffer into output buffer */
2031 memcpy(buf, aligned_buf, len);
2032 buf += len;
2033 cnt -= len;
2034 }
2035 } else
2036#endif
2037 {
2038 u16 *pdata = buf;
0e3a22c0 2039
34b664a2 2040 for (; cnt >= 2; cnt -= 2)
76184ac1 2041 *pdata++ = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2042 buf = pdata;
2043 }
2044 if (cnt) {
76184ac1 2045 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
34b664a2 2046 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2047 }
2048}
2049
2050static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2051{
cfbeb59c
MC		 2052 struct mmc_data *data = host->data;
2053 int init_cnt = cnt;
2054
34b664a2
JH		 2055 /* try and push anything in the part_buf */
2056 if (unlikely(host->part_buf_count)) {
2057 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2058
34b664a2
JH		 2059 buf += len;
2060 cnt -= len;
cfbeb59c 2061 if (host->part_buf_count == 4) {
76184ac1 2062 mci_fifo_writel(host->fifo_reg, host->part_buf32);
34b664a2
JH		 2063 host->part_buf_count = 0;
2064 }
2065 }
2066#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2067 if (unlikely((unsigned long)buf & 0x3)) {
2068 while (cnt >= 4) {
2069 u32 aligned_buf[32];
2070 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2071 int items = len >> 2;
2072 int i;
2073 /* memcpy from input buffer into aligned buffer */
2074 memcpy(aligned_buf, buf, len);
2075 buf += len;
2076 cnt -= len;
2077 /* push data from aligned buffer into fifo */
2078 for (i = 0; i < items; ++i)
76184ac1 2079 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2080 }
2081 } else
2082#endif
2083 {
2084 u32 *pdata = buf;
0e3a22c0 2085
34b664a2 2086 for (; cnt >= 4; cnt -= 4)
76184ac1 2087 mci_fifo_writel(host->fifo_reg, *pdata++);
34b664a2
JH		 2088 buf = pdata;
2089 }
2090 /* put anything remaining in the part_buf */
2091 if (cnt) {
2092 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2093 /* Push data if we have reached the expected data length */
2094 if ((data->bytes_xfered + init_cnt) ==
2095 (data->blksz * data->blocks))
76184ac1 2096 mci_fifo_writel(host->fifo_reg, host->part_buf32);
f95f3850
WN		 2097 }
2098}
2099
2100static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2101{
34b664a2
JH		 2102#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2103 if (unlikely((unsigned long)buf & 0x3)) {
2104 while (cnt >= 4) {
2105 /* pull data from fifo into aligned buffer */
2106 u32 aligned_buf[32];
2107 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2108 int items = len >> 2;
2109 int i;
0e3a22c0 2110
34b664a2 2111 for (i = 0; i < items; ++i)
76184ac1 2112 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2113 /* memcpy from aligned buffer into output buffer */
2114 memcpy(buf, aligned_buf, len);
2115 buf += len;
2116 cnt -= len;
2117 }
2118 } else
2119#endif
2120 {
2121 u32 *pdata = buf;
0e3a22c0 2122
34b664a2 2123 for (; cnt >= 4; cnt -= 4)
76184ac1 2124 *pdata++ = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2125 buf = pdata;
2126 }
2127 if (cnt) {
76184ac1 2128 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
34b664a2 2129 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2130 }
2131}
2132
2133static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2134{
cfbeb59c
MC		 2135 struct mmc_data *data = host->data;
2136 int init_cnt = cnt;
2137
34b664a2
JH		 2138 /* try and push anything in the part_buf */
2139 if (unlikely(host->part_buf_count)) {
2140 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2141
34b664a2
JH		 2142 buf += len;
2143 cnt -= len;
c09fbd74 2144
cfbeb59c 2145 if (host->part_buf_count == 8) {
76184ac1 2146 mci_fifo_writeq(host->fifo_reg, host->part_buf);
34b664a2
JH		 2147 host->part_buf_count = 0;
2148 }
2149 }
2150#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2151 if (unlikely((unsigned long)buf & 0x7)) {
2152 while (cnt >= 8) {
2153 u64 aligned_buf[16];
2154 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2155 int items = len >> 3;
2156 int i;
2157 /* memcpy from input buffer into aligned buffer */
2158 memcpy(aligned_buf, buf, len);
2159 buf += len;
2160 cnt -= len;
2161 /* push data from aligned buffer into fifo */
2162 for (i = 0; i < items; ++i)
76184ac1 2163 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2164 }
2165 } else
2166#endif
2167 {
2168 u64 *pdata = buf;
0e3a22c0 2169
34b664a2 2170 for (; cnt >= 8; cnt -= 8)
76184ac1 2171 mci_fifo_writeq(host->fifo_reg, *pdata++);
34b664a2
JH		 2172 buf = pdata;
2173 }
2174 /* put anything remaining in the part_buf */
2175 if (cnt) {
2176 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2177 /* Push data if we have reached the expected data length */
2178 if ((data->bytes_xfered + init_cnt) ==
2179 (data->blksz * data->blocks))
76184ac1 2180 mci_fifo_writeq(host->fifo_reg, host->part_buf);
f95f3850
WN		 2181 }
2182}
2183
2184static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2185{
34b664a2
JH		 2186#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2187 if (unlikely((unsigned long)buf & 0x7)) {
2188 while (cnt >= 8) {
2189 /* pull data from fifo into aligned buffer */
2190 u64 aligned_buf[16];
2191 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2192 int items = len >> 3;
2193 int i;
0e3a22c0 2194
34b664a2 2195 for (i = 0; i < items; ++i)
76184ac1
BD		 2196 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2197
34b664a2
JH		 2198 /* memcpy from aligned buffer into output buffer */
2199 memcpy(buf, aligned_buf, len);
2200 buf += len;
2201 cnt -= len;
2202 }
2203 } else
2204#endif
2205 {
2206 u64 *pdata = buf;
0e3a22c0 2207
34b664a2 2208 for (; cnt >= 8; cnt -= 8)
76184ac1 2209 *pdata++ = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2210 buf = pdata;
2211 }
2212 if (cnt) {
76184ac1 2213 host->part_buf = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2214 dw_mci_pull_final_bytes(host, buf, cnt);
2215 }
2216}
f95f3850 2217
34b664a2
JH		 2218static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2219{
2220 int len;
f95f3850 2221
34b664a2
JH		 2222 /* get remaining partial bytes */
2223 len = dw_mci_pull_part_bytes(host, buf, cnt);
2224 if (unlikely(len == cnt))
2225 return;
2226 buf += len;
2227 cnt -= len;
2228
2229 /* get the rest of the data */
2230 host->pull_data(host, buf, cnt);
f95f3850
WN		 2231}
2232
87a74d39 2233static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
f95f3850 2234{
f9c2a0dc
SJ		 2235 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2236 void *buf;
2237 unsigned int offset;
f95f3850
WN		 2238 struct mmc_data *data = host->data;
2239 int shift = host->data_shift;
2240 u32 status;
3e4b0d8b 2241 unsigned int len;
f9c2a0dc 2242 unsigned int remain, fcnt;
f95f3850
WN		 2243
2244 do {
f9c2a0dc
SJ		 2245 if (!sg_miter_next(sg_miter))
2246 goto done;
2247
4225fc85 2248 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2249 buf = sg_miter->addr;
2250 remain = sg_miter->length;
2251 offset = 0;
2252
2253 do {
2254 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2255 << shift) + host->part_buf_count;
2256 len = min(remain, fcnt);
2257 if (!len)
2258 break;
34b664a2 2259 dw_mci_pull_data(host, (void *)(buf + offset), len);
3e4b0d8b 2260 data->bytes_xfered += len;
f95f3850 2261 offset += len;
f9c2a0dc
SJ		 2262 remain -= len;
2263 } while (remain);
f95f3850 2264
e74f3a9c 2265 sg_miter->consumed = offset;
f95f3850
WN		 2266 status = mci_readl(host, MINTSTS);
2267 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
87a74d39
KK		 2268 /* if the RXDR is ready read again */
2269 } while ((status & SDMMC_INT_RXDR) ||
2270 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
f9c2a0dc
SJ		 2271
2272 if (!remain) {
2273 if (!sg_miter_next(sg_miter))
2274 goto done;
2275 sg_miter->consumed = 0;
2276 }
2277 sg_miter_stop(sg_miter);
f95f3850
WN		 2278 return;
2279
2280done:
f9c2a0dc
SJ		 2281 sg_miter_stop(sg_miter);
2282 host->sg = NULL;
0e3a22c0 2283 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2284 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2285}
2286
2287static void dw_mci_write_data_pio(struct dw_mci *host)
2288{
f9c2a0dc
SJ		 2289 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2290 void *buf;
2291 unsigned int offset;
f95f3850
WN		 2292 struct mmc_data *data = host->data;
2293 int shift = host->data_shift;
2294 u32 status;
3e4b0d8b 2295 unsigned int len;
f9c2a0dc
SJ		 2296 unsigned int fifo_depth = host->fifo_depth;
2297 unsigned int remain, fcnt;
f95f3850
WN		 2298
2299 do {
f9c2a0dc
SJ		 2300 if (!sg_miter_next(sg_miter))
2301 goto done;
2302
4225fc85 2303 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2304 buf = sg_miter->addr;
2305 remain = sg_miter->length;
2306 offset = 0;
2307
2308 do {
2309 fcnt = ((fifo_depth -
2310 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2311 << shift) - host->part_buf_count;
2312 len = min(remain, fcnt);
2313 if (!len)
2314 break;
f95f3850 2315 host->push_data(host, (void *)(buf + offset), len);
3e4b0d8b 2316 data->bytes_xfered += len;
f95f3850 2317 offset += len;
f9c2a0dc
SJ		 2318 remain -= len;
2319 } while (remain);
f95f3850 2320
e74f3a9c 2321 sg_miter->consumed = offset;
f95f3850
WN		 2322 status = mci_readl(host, MINTSTS);
2323 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 2324 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f9c2a0dc
SJ		 2325
2326 if (!remain) {
2327 if (!sg_miter_next(sg_miter))
2328 goto done;
2329 sg_miter->consumed = 0;
2330 }
2331 sg_miter_stop(sg_miter);
f95f3850
WN		 2332 return;
2333
2334done:
f9c2a0dc
SJ		 2335 sg_miter_stop(sg_miter);
2336 host->sg = NULL;
0e3a22c0 2337 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2338 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2339}
2340
2341static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2342{
2343 if (!host->cmd_status)
2344 host->cmd_status = status;
2345
0e3a22c0 2346 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2347
2348 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2349 tasklet_schedule(&host->tasklet);
2350}
2351
6130e7a9
DA		 2352static void dw_mci_handle_cd(struct dw_mci *host)
2353{
2354 int i;
2355
2356 for (i = 0; i < host->num_slots; i++) {
2357 struct dw_mci_slot *slot = host->slot[i];
2358
2359 if (!slot)
2360 continue;
2361
2362 if (slot->mmc->ops->card_event)
2363 slot->mmc->ops->card_event(slot->mmc);
2364 mmc_detect_change(slot->mmc,
2365 msecs_to_jiffies(host->pdata->detect_delay_ms));
2366 }
2367}
2368
f95f3850
WN		 2369static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2370{
2371 struct dw_mci *host = dev_id;
182c9081 2372 u32 pending;
1a5c8e1f 2373 int i;
f95f3850 2374
1fb5f68a
MC		 2375 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2376
476d79f1 2377 if (pending) {
01730558
DA		 2378 /* Check volt switch first, since it can look like an error */
2379 if ((host->state == STATE_SENDING_CMD11) &&
2380 (pending & SDMMC_INT_VOLT_SWITCH)) {
49ba0302 2381 unsigned long irqflags;
5c935165 2382
01730558
DA		 2383 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2384 pending &= ~SDMMC_INT_VOLT_SWITCH;
49ba0302
DA		 2385
2386 /*
2387 * Hold the lock; we know cmd11_timer can't be kicked
2388 * off after the lock is released, so safe to delete.
2389 */
2390 spin_lock_irqsave(&host->irq_lock, irqflags);
01730558 2391 dw_mci_cmd_interrupt(host, pending);
49ba0302
DA		 2392 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2393
2394 del_timer(&host->cmd11_timer);
01730558
DA		 2395 }
2396
f95f3850
WN		 2397 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2398 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 2399 host->cmd_status = pending;
0e3a22c0 2400 smp_wmb(); /* drain writebuffer */
f95f3850 2401 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 2402 }
2403
2404 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2405 /* if there is an error report DATA_ERROR */
2406 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 2407 host->data_status = pending;
0e3a22c0 2408 smp_wmb(); /* drain writebuffer */
f95f3850 2409 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 2410 tasklet_schedule(&host->tasklet);
f95f3850
WN		 2411 }
2412
2413 if (pending & SDMMC_INT_DATA_OVER) {
57e10486
AK		 2414 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
2415 del_timer(&host->dto_timer);
2416
f95f3850
WN		 2417 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2418 if (!host->data_status)
182c9081 2419 host->data_status = pending;
0e3a22c0 2420 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2421 if (host->dir_status == DW_MCI_RECV_STATUS) {
2422 if (host->sg != NULL)
87a74d39 2423 dw_mci_read_data_pio(host, true);
f95f3850
WN		 2424 }
2425 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2426 tasklet_schedule(&host->tasklet);
2427 }
2428
2429 if (pending & SDMMC_INT_RXDR) {
2430 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 2431 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
87a74d39 2432 dw_mci_read_data_pio(host, false);
f95f3850
WN		 2433 }
2434
2435 if (pending & SDMMC_INT_TXDR) {
2436 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 2437 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 2438 dw_mci_write_data_pio(host);
2439 }
2440
2441 if (pending & SDMMC_INT_CMD_DONE) {
2442 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 2443 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 2444 }
2445
2446 if (pending & SDMMC_INT_CD) {
2447 mci_writel(host, RINTSTS, SDMMC_INT_CD);
6130e7a9 2448 dw_mci_handle_cd(host);
f95f3850
WN		 2449 }
2450
1a5c8e1f
SH		 2451 /* Handle SDIO Interrupts */
2452 for (i = 0; i < host->num_slots; i++) {
2453 struct dw_mci_slot *slot = host->slot[i];
ed2540ef
DA		 2454
2455 if (!slot)
2456 continue;
2457
76756234
AK		 2458 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2459 mci_writel(host, RINTSTS,
2460 SDMMC_INT_SDIO(slot->sdio_id));
1a5c8e1f
SH		 2461 mmc_signal_sdio_irq(slot->mmc);
2462 }
2463 }
2464
1fb5f68a 2465 }
f95f3850 2466
3fc7eaef
SL		 2467 if (host->use_dma != TRANS_MODE_IDMAC)
2468 return IRQ_HANDLED;
2469
2470 /* Handle IDMA interrupts */
69d99fdc
PT		 2471 if (host->dma_64bit_address == 1) {
2472 pending = mci_readl(host, IDSTS64);
2473 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2474 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2475 SDMMC_IDMAC_INT_RI);
2476 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
3fc7eaef 2477 host->dma_ops->complete((void *)host);
69d99fdc
PT		 2478 }
2479 } else {
2480 pending = mci_readl(host, IDSTS);
2481 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2482 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2483 SDMMC_IDMAC_INT_RI);
2484 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
3fc7eaef 2485 host->dma_ops->complete((void *)host);
69d99fdc 2486 }
f95f3850 2487 }
f95f3850
WN		 2488
2489 return IRQ_HANDLED;
2490}
2491
c91eab4b 2492#ifdef CONFIG_OF
eff8f2f5
LPC		 2493/* given a slot, find out the device node representing that slot */
2494static struct device_node *dw_mci_of_find_slot_node(struct dw_mci_slot *slot)
c91eab4b 2495{
eff8f2f5 2496 struct device *dev = slot->mmc->parent;
c91eab4b
TA		 2497 struct device_node *np;
2498 const __be32 *addr;
2499 int len;
2500
2501 if (!dev || !dev->of_node)
2502 return NULL;
2503
2504 for_each_child_of_node(dev->of_node, np) {
2505 addr = of_get_property(np, "reg", &len);
2506 if (!addr || (len < sizeof(int)))
2507 continue;
eff8f2f5 2508 if (be32_to_cpup(addr) == slot->id)
c91eab4b
TA		 2509 return np;
2510 }
2511 return NULL;
2512}
2513
eff8f2f5 2514static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
a70aaa64 2515{
eff8f2f5 2516 struct device_node *np = dw_mci_of_find_slot_node(slot);
a70aaa64 2517
eff8f2f5
LPC		 2518 if (!np)
2519 return;
a70aaa64 2520
eff8f2f5
LPC		 2521 if (of_property_read_bool(np, "disable-wp")) {
2522 slot->mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
2523 dev_warn(slot->mmc->parent,
2524 "Slot quirk 'disable-wp' is deprecated\n");
2525 }
a70aaa64 2526}
c91eab4b 2527#else /* CONFIG_OF */
eff8f2f5 2528static void dw_mci_slot_of_parse(struct dw_mci_slot *slot)
a70aaa64 2529{
a70aaa64 2530}
c91eab4b
TA		 2531#endif /* CONFIG_OF */
2532
36c179a9 2533static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 2534{
2535 struct mmc_host *mmc;
2536 struct dw_mci_slot *slot;
e95baf13 2537 const struct dw_mci_drv_data *drv_data = host->drv_data;
800d78bf 2538 int ctrl_id, ret;
1f44a2a5 2539 u32 freq[2];
f95f3850 2540
4a90920c 2541 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 2542 if (!mmc)
2543 return -ENOMEM;
2544
2545 slot = mmc_priv(mmc);
2546 slot->id = id;
76756234 2547 slot->sdio_id = host->sdio_id0 + id;
f95f3850
WN		 2548 slot->mmc = mmc;
2549 slot->host = host;
c91eab4b 2550 host->slot[id] = slot;
f95f3850
WN		 2551
2552 mmc->ops = &dw_mci_ops;
1f44a2a5
SJ		 2553 if (of_property_read_u32_array(host->dev->of_node,
2554 "clock-freq-min-max", freq, 2)) {
2555 mmc->f_min = DW_MCI_FREQ_MIN;
2556 mmc->f_max = DW_MCI_FREQ_MAX;
2557 } else {
2558 mmc->f_min = freq[0];
2559 mmc->f_max = freq[1];
2560 }
f95f3850 2561
51da2240
YC		 2562 /*if there are external regulators, get them*/
2563 ret = mmc_regulator_get_supply(mmc);
2564 if (ret == -EPROBE_DEFER)
3cf890fc 2565 goto err_host_allocated;
51da2240
YC		 2566
2567 if (!mmc->ocr_avail)
2568 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
f95f3850 2569
fc3d7720
JC		 2570 if (host->pdata->caps)
2571 mmc->caps = host->pdata->caps;
fc3d7720 2572
ab269128
AK		 2573 if (host->pdata->pm_caps)
2574 mmc->pm_caps = host->pdata->pm_caps;
2575
800d78bf
TA		 2576 if (host->dev->of_node) {
2577 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2578 if (ctrl_id < 0)
2579 ctrl_id = 0;
2580 } else {
2581 ctrl_id = to_platform_device(host->dev)->id;
2582 }
cb27a843
JH		 2583 if (drv_data && drv_data->caps)
2584 mmc->caps |= drv_data->caps[ctrl_id];
800d78bf 2585
4f408cc6
SJ		 2586 if (host->pdata->caps2)
2587 mmc->caps2 = host->pdata->caps2;
4f408cc6 2588
eff8f2f5
LPC		 2589 dw_mci_slot_of_parse(slot);
2590
3cf890fc
DA		 2591 ret = mmc_of_parse(mmc);
2592 if (ret)
2593 goto err_host_allocated;
f95f3850 2594
2b708df2 2595 /* Useful defaults if platform data is unset. */
3fc7eaef 2596 if (host->use_dma == TRANS_MODE_IDMAC) {
2b708df2
JC		 2597 mmc->max_segs = host->ring_size;
2598 mmc->max_blk_size = 65536;
2599 mmc->max_seg_size = 0x1000;
2600 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2601 mmc->max_blk_count = mmc->max_req_size / 512;
3fc7eaef
SL		 2602 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2603 mmc->max_segs = 64;
2604 mmc->max_blk_size = 65536;
2605 mmc->max_blk_count = 65535;
2606 mmc->max_req_size =
2607 mmc->max_blk_size * mmc->max_blk_count;
2608 mmc->max_seg_size = mmc->max_req_size;
f95f3850 2609 } else {
3fc7eaef 2610 /* TRANS_MODE_PIO */
2b708df2
JC		 2611 mmc->max_segs = 64;
2612 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
2613 mmc->max_blk_count = 512;
2614 mmc->max_req_size = mmc->max_blk_size *
2615 mmc->max_blk_count;
2616 mmc->max_seg_size = mmc->max_req_size;
a39e5746 2617 }
f95f3850 2618
ae0eb348
JC		 2619 if (dw_mci_get_cd(mmc))
2620 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2621 else
2622 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
2623
0cea529d
JC		 2624 ret = mmc_add_host(mmc);
2625 if (ret)
3cf890fc 2626 goto err_host_allocated;
f95f3850
WN		 2627
2628#if defined(CONFIG_DEBUG_FS)
2629 dw_mci_init_debugfs(slot);
2630#endif
2631
f95f3850 2632 return 0;
800d78bf 2633
3cf890fc 2634err_host_allocated:
800d78bf 2635 mmc_free_host(mmc);
51da2240 2636 return ret;
f95f3850
WN		 2637}
2638
2639static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
2640{
f95f3850
WN		 2641 /* Debugfs stuff is cleaned up by mmc core */
2642 mmc_remove_host(slot->mmc);
2643 slot->host->slot[id] = NULL;
2644 mmc_free_host(slot->mmc);
2645}
2646
2647static void dw_mci_init_dma(struct dw_mci *host)
2648{
69d99fdc 2649 int addr_config;
3fc7eaef
SL		 2650 struct device *dev = host->dev;
2651 struct device_node *np = dev->of_node;
69d99fdc 2652
3fc7eaef
SL		 2653 /*
2654 * Check tansfer mode from HCON[17:16]
2655 * Clear the ambiguous description of dw_mmc databook:
2656 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2657 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2658 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2659 * 2b'11: Non DW DMA Interface -> pio only
2660 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2661 * simpler request/acknowledge handshake mechanism and both of them
2662 * are regarded as external dma master for dw_mmc.
2663 */
2664 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2665 if (host->use_dma == DMA_INTERFACE_IDMA) {
2666 host->use_dma = TRANS_MODE_IDMAC;
2667 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2668 host->use_dma == DMA_INTERFACE_GDMA) {
2669 host->use_dma = TRANS_MODE_EDMAC;
2670 } else {
f95f3850
WN		 2671 goto no_dma;
2672 }
2673
2674 /* Determine which DMA interface to use */
3fc7eaef
SL		 2675 if (host->use_dma == TRANS_MODE_IDMAC) {
2676 /*
2677 * Check ADDR_CONFIG bit in HCON to find
2678 * IDMAC address bus width
2679 */
70692752 2680 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
3fc7eaef
SL		 2681
2682 if (addr_config == 1) {
2683 /* host supports IDMAC in 64-bit address mode */
2684 host->dma_64bit_address = 1;
2685 dev_info(host->dev,
2686 "IDMAC supports 64-bit address mode.\n");
2687 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2688 dma_set_coherent_mask(host->dev,
2689 DMA_BIT_MASK(64));
2690 } else {
2691 /* host supports IDMAC in 32-bit address mode */
2692 host->dma_64bit_address = 0;
2693 dev_info(host->dev,
2694 "IDMAC supports 32-bit address mode.\n");
2695 }
f95f3850 2696
3fc7eaef
SL		 2697 /* Alloc memory for sg translation */
2698 host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
2699 &host->sg_dma, GFP_KERNEL);
2700 if (!host->sg_cpu) {
2701 dev_err(host->dev,
2702 "%s: could not alloc DMA memory\n",
2703 __func__);
2704 goto no_dma;
2705 }
2706
2707 host->dma_ops = &dw_mci_idmac_ops;
2708 dev_info(host->dev, "Using internal DMA controller.\n");
2709 } else {
2710 /* TRANS_MODE_EDMAC: check dma bindings again */
2711 if ((of_property_count_strings(np, "dma-names") < 0) ||
2712 (!of_find_property(np, "dmas", NULL))) {
2713 goto no_dma;
2714 }
2715 host->dma_ops = &dw_mci_edmac_ops;
2716 dev_info(host->dev, "Using external DMA controller.\n");
2717 }
f95f3850 2718
e1631f98
JC		 2719 if (host->dma_ops->init && host->dma_ops->start &&
2720 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 2721 if (host->dma_ops->init(host)) {
0e3a22c0
SL		 2722 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2723 __func__);
f95f3850
WN		 2724 goto no_dma;
2725 }
2726 } else {
4a90920c 2727 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 2728 goto no_dma;
2729 }
2730
f95f3850
WN		 2731 return;
2732
2733no_dma:
4a90920c 2734 dev_info(host->dev, "Using PIO mode.\n");
3fc7eaef 2735 host->use_dma = TRANS_MODE_PIO;
f95f3850
WN		 2736}
2737
31bff450 2738static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
f95f3850
WN		 2739{
2740 unsigned long timeout = jiffies + msecs_to_jiffies(500);
31bff450 2741 u32 ctrl;
f95f3850 2742
31bff450
SJ		 2743 ctrl = mci_readl(host, CTRL);
2744 ctrl |= reset;
2745 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 2746
2747 /* wait till resets clear */
2748 do {
2749 ctrl = mci_readl(host, CTRL);
31bff450 2750 if (!(ctrl & reset))
f95f3850
WN		 2751 return true;
2752 } while (time_before(jiffies, timeout));
2753
31bff450
SJ		 2754 dev_err(host->dev,
2755 "Timeout resetting block (ctrl reset %#x)\n",
2756 ctrl & reset);
f95f3850
WN		 2757
2758 return false;
2759}
2760
3a33a94c 2761static bool dw_mci_reset(struct dw_mci *host)
31bff450 2762{
3a33a94c
SR		 2763 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
2764 bool ret = false;
2765
31bff450
SJ		 2766 /*
2767 * Reseting generates a block interrupt, hence setting
2768 * the scatter-gather pointer to NULL.
2769 */
2770 if (host->sg) {
2771 sg_miter_stop(&host->sg_miter);
2772 host->sg = NULL;
2773 }
2774
3a33a94c
SR		 2775 if (host->use_dma)
2776 flags |= SDMMC_CTRL_DMA_RESET;
31bff450 2777
3a33a94c
SR		 2778 if (dw_mci_ctrl_reset(host, flags)) {
2779 /*
2780 * In all cases we clear the RAWINTS register to clear any
2781 * interrupts.
2782 */
2783 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2784
2785 /* if using dma we wait for dma_req to clear */
2786 if (host->use_dma) {
2787 unsigned long timeout = jiffies + msecs_to_jiffies(500);
2788 u32 status;
0e3a22c0 2789
3a33a94c
SR		 2790 do {
2791 status = mci_readl(host, STATUS);
2792 if (!(status & SDMMC_STATUS_DMA_REQ))
2793 break;
2794 cpu_relax();
2795 } while (time_before(jiffies, timeout));
2796
2797 if (status & SDMMC_STATUS_DMA_REQ) {
2798 dev_err(host->dev,
0e3a22c0
SL		 2799 "%s: Timeout waiting for dma_req to clear during reset\n",
2800 __func__);
3a33a94c
SR		 2801 goto ciu_out;
2802 }
2803
2804 /* when using DMA next we reset the fifo again */
2805 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
2806 goto ciu_out;
2807 }
2808 } else {
2809 /* if the controller reset bit did clear, then set clock regs */
2810 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
0e3a22c0
SL		 2811 dev_err(host->dev,
2812 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
3a33a94c
SR		 2813 __func__);
2814 goto ciu_out;
2815 }
2816 }
2817
3fc7eaef
SL		 2818 if (host->use_dma == TRANS_MODE_IDMAC)
2819 /* It is also recommended that we reset and reprogram idmac */
2820 dw_mci_idmac_reset(host);
3a33a94c
SR		 2821
2822 ret = true;
2823
2824ciu_out:
2825 /* After a CTRL reset we need to have CIU set clock registers */
2826 mci_send_cmd(host->cur_slot, SDMMC_CMD_UPD_CLK, 0);
2827
2828 return ret;
31bff450
SJ		 2829}
2830
5c935165
DA		 2831static void dw_mci_cmd11_timer(unsigned long arg)
2832{
2833 struct dw_mci *host = (struct dw_mci *)arg;
2834
fd674198
DA		 2835 if (host->state != STATE_SENDING_CMD11) {
2836 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2837 return;
2838 }
5c935165
DA		 2839
2840 host->cmd_status = SDMMC_INT_RTO;
2841 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2842 tasklet_schedule(&host->tasklet);
2843}
2844
57e10486
AK		 2845static void dw_mci_dto_timer(unsigned long arg)
2846{
2847 struct dw_mci *host = (struct dw_mci *)arg;
2848
2849 switch (host->state) {
2850 case STATE_SENDING_DATA:
2851 case STATE_DATA_BUSY:
2852 /*
2853 * If DTO interrupt does NOT come in sending data state,
2854 * we should notify the driver to terminate current transfer
2855 * and report a data timeout to the core.
2856 */
2857 host->data_status = SDMMC_INT_DRTO;
2858 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2859 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2860 tasklet_schedule(&host->tasklet);
2861 break;
2862 default:
2863 break;
2864 }
2865}
2866
c91eab4b 2867#ifdef CONFIG_OF
c91eab4b
TA		 2868static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2869{
2870 struct dw_mci_board *pdata;
2871 struct device *dev = host->dev;
2872 struct device_node *np = dev->of_node;
e95baf13 2873 const struct dw_mci_drv_data *drv_data = host->drv_data;
e8cc37b8 2874 int ret;
3c6d89ea 2875 u32 clock_frequency;
c91eab4b
TA		 2876
2877 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
bf3707ea 2878 if (!pdata)
c91eab4b 2879 return ERR_PTR(-ENOMEM);
c91eab4b
TA		 2880
2881 /* find out number of slots supported */
8a629d26 2882 of_property_read_u32(np, "num-slots", &pdata->num_slots);
c91eab4b 2883
c91eab4b 2884 if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
0e3a22c0
SL		 2885 dev_info(dev,
2886 "fifo-depth property not found, using value of FIFOTH register as default\n");
c91eab4b
TA		 2887
2888 of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
2889
3c6d89ea
DA		 2890 if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
2891 pdata->bus_hz = clock_frequency;
2892
cb27a843
JH		 2893 if (drv_data && drv_data->parse_dt) {
2894 ret = drv_data->parse_dt(host);
800d78bf
TA		 2895 if (ret)
2896 return ERR_PTR(ret);
2897 }
2898
40a7a463
JC		 2899 if (of_find_property(np, "supports-highspeed", NULL)) {
2900 dev_info(dev, "supports-highspeed property is deprecated.\n");
10b49841 2901 pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
40a7a463 2902 }
10b49841 2903
c91eab4b
TA		 2904 return pdata;
2905}
2906
2907#else /* CONFIG_OF */
2908static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2909{
2910 return ERR_PTR(-EINVAL);
2911}
2912#endif /* CONFIG_OF */
2913
fa0c3283
DA		 2914static void dw_mci_enable_cd(struct dw_mci *host)
2915{
fa0c3283
DA		 2916 unsigned long irqflags;
2917 u32 temp;
2918 int i;
e8cc37b8 2919 struct dw_mci_slot *slot;
fa0c3283 2920
e8cc37b8
SL		 2921 /*
2922 * No need for CD if all slots have a non-error GPIO
2923 * as well as broken card detection is found.
2924 */
fa0c3283 2925 for (i = 0; i < host->num_slots; i++) {
e8cc37b8
SL		 2926 slot = host->slot[i];
2927 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL)
2928 return;
fa0c3283
DA		 2929
2930 if (IS_ERR_VALUE(mmc_gpio_get_cd(slot->mmc)))
2931 break;
2932 }
2933 if (i == host->num_slots)
2934 return;
2935
2936 spin_lock_irqsave(&host->irq_lock, irqflags);
2937 temp = mci_readl(host, INTMASK);
2938 temp |= SDMMC_INT_CD;
2939 mci_writel(host, INTMASK, temp);
2940 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2941}
2942
62ca8034 2943int dw_mci_probe(struct dw_mci *host)
f95f3850 2944{
e95baf13 2945 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 2946 int width, i, ret = 0;
f95f3850 2947 u32 fifo_size;
1c2215b7 2948 int init_slots = 0;
f95f3850 2949
c91eab4b
TA		 2950 if (!host->pdata) {
2951 host->pdata = dw_mci_parse_dt(host);
2952 if (IS_ERR(host->pdata)) {
2953 dev_err(host->dev, "platform data not available\n");
2954 return -EINVAL;
2955 }
f95f3850
WN		 2956 }
2957
780f22af 2958 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 2959 if (IS_ERR(host->biu_clk)) {
2960 dev_dbg(host->dev, "biu clock not available\n");
2961 } else {
2962 ret = clk_prepare_enable(host->biu_clk);
2963 if (ret) {
2964 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 2965 return ret;
2966 }
2967 }
2968
780f22af 2969 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 2970 if (IS_ERR(host->ciu_clk)) {
2971 dev_dbg(host->dev, "ciu clock not available\n");
3c6d89ea 2972 host->bus_hz = host->pdata->bus_hz;
f90a0612
TA		 2973 } else {
2974 ret = clk_prepare_enable(host->ciu_clk);
2975 if (ret) {
2976 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 2977 goto err_clk_biu;
2978 }
f90a0612 2979
3c6d89ea
DA		 2980 if (host->pdata->bus_hz) {
2981 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
2982 if (ret)
2983 dev_warn(host->dev,
612de4c1 2984 "Unable to set bus rate to %uHz\n",
3c6d89ea
DA		 2985 host->pdata->bus_hz);
2986 }
f90a0612 2987 host->bus_hz = clk_get_rate(host->ciu_clk);
3c6d89ea 2988 }
f90a0612 2989
612de4c1
JC		 2990 if (!host->bus_hz) {
2991 dev_err(host->dev,
2992 "Platform data must supply bus speed\n");
2993 ret = -ENODEV;
2994 goto err_clk_ciu;
2995 }
2996
002f0d5c
YK		 2997 if (drv_data && drv_data->init) {
2998 ret = drv_data->init(host);
2999 if (ret) {
3000 dev_err(host->dev,
3001 "implementation specific init failed\n");
3002 goto err_clk_ciu;
3003 }
3004 }
3005
5c935165
DA		 3006 setup_timer(&host->cmd11_timer,
3007 dw_mci_cmd11_timer, (unsigned long)host);
3008
62ca8034 3009 host->quirks = host->pdata->quirks;
f95f3850 3010
57e10486
AK		 3011 if (host->quirks & DW_MCI_QUIRK_BROKEN_DTO)
3012 setup_timer(&host->dto_timer,
3013 dw_mci_dto_timer, (unsigned long)host);
3014
f95f3850 3015 spin_lock_init(&host->lock);
f8c58c11 3016 spin_lock_init(&host->irq_lock);
f95f3850
WN		 3017 INIT_LIST_HEAD(&host->queue);
3018
f95f3850
WN		 3019 /*
3020 * Get the host data width - this assumes that HCON has been set with
3021 * the correct values.
3022 */
70692752 3023 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
f95f3850
WN		 3024 if (!i) {
3025 host->push_data = dw_mci_push_data16;
3026 host->pull_data = dw_mci_pull_data16;
3027 width = 16;
3028 host->data_shift = 1;
3029 } else if (i == 2) {
3030 host->push_data = dw_mci_push_data64;
3031 host->pull_data = dw_mci_pull_data64;
3032 width = 64;
3033 host->data_shift = 3;
3034 } else {
3035 /* Check for a reserved value, and warn if it is */
3036 WARN((i != 1),
3037 "HCON reports a reserved host data width!\n"
3038 "Defaulting to 32-bit access.\n");
3039 host->push_data = dw_mci_push_data32;
3040 host->pull_data = dw_mci_pull_data32;
3041 width = 32;
3042 host->data_shift = 2;
3043 }
3044
3045 /* Reset all blocks */
3744415c
SL		 3046 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3047 ret = -ENODEV;
3048 goto err_clk_ciu;
3049 }
141a712a
SJ		 3050
3051 host->dma_ops = host->pdata->dma_ops;
3052 dw_mci_init_dma(host);
f95f3850
WN		 3053
3054 /* Clear the interrupts for the host controller */
3055 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3056 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3057
3058 /* Put in max timeout */
3059 mci_writel(host, TMOUT, 0xFFFFFFFF);
3060
3061 /*
3062 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3063 * Tx Mark = fifo_size / 2 DMA Size = 8
3064 */
b86d8253
JH		 3065 if (!host->pdata->fifo_depth) {
3066 /*
3067 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3068 * have been overwritten by the bootloader, just like we're
3069 * about to do, so if you know the value for your hardware, you
3070 * should put it in the platform data.
3071 */
3072 fifo_size = mci_readl(host, FIFOTH);
8234e869 3073 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 3074 } else {
3075 fifo_size = host->pdata->fifo_depth;
3076 }
3077 host->fifo_depth = fifo_size;
52426899
SJ		 3078 host->fifoth_val =
3079 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
e61cf118 3080 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 3081
3082 /* disable clock to CIU */
3083 mci_writel(host, CLKENA, 0);
3084 mci_writel(host, CLKSRC, 0);
3085
63008768
JH		 3086 /*
3087 * In 2.40a spec, Data offset is changed.
3088 * Need to check the version-id and set data-offset for DATA register.
3089 */
3090 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3091 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3092
3093 if (host->verid < DW_MMC_240A)
76184ac1 3094 host->fifo_reg = host->regs + DATA_OFFSET;
63008768 3095 else
76184ac1 3096 host->fifo_reg = host->regs + DATA_240A_OFFSET;
63008768 3097
f95f3850 3098 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
780f22af
SJ		 3099 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3100 host->irq_flags, "dw-mci", host);
f95f3850 3101 if (ret)
6130e7a9 3102 goto err_dmaunmap;
f95f3850 3103
f95f3850
WN		 3104 if (host->pdata->num_slots)
3105 host->num_slots = host->pdata->num_slots;
3106 else
8a629d26
SL		 3107 host->num_slots = 1;
3108
3109 if (host->num_slots < 1 ||
3110 host->num_slots > SDMMC_GET_SLOT_NUM(mci_readl(host, HCON))) {
3111 dev_err(host->dev,
3112 "Platform data must supply correct num_slots.\n");
3113 ret = -ENODEV;
3114 goto err_clk_ciu;
3115 }
f95f3850 3116
2da1d7f2 3117 /*
fa0c3283 3118 * Enable interrupts for command done, data over, data empty,
2da1d7f2
YC		 3119 * receive ready and error such as transmit, receive timeout, crc error
3120 */
2da1d7f2
YC		 3121 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3122 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3123 DW_MCI_ERROR_FLAGS);
0e3a22c0
SL		 3124 /* Enable mci interrupt */
3125 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2da1d7f2 3126
0e3a22c0
SL		 3127 dev_info(host->dev,
3128 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
2da1d7f2
YC		 3129 host->irq, width, fifo_size);
3130
f95f3850
WN		 3131 /* We need at least one slot to succeed */
3132 for (i = 0; i < host->num_slots; i++) {
3133 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 3134 if (ret)
3135 dev_dbg(host->dev, "slot %d init failed\n", i);
3136 else
3137 init_slots++;
3138 }
3139
3140 if (init_slots) {
3141 dev_info(host->dev, "%d slots initialized\n", init_slots);
3142 } else {
0e3a22c0
SL		 3143 dev_dbg(host->dev,
3144 "attempted to initialize %d slots, but failed on all\n",
3145 host->num_slots);
6130e7a9 3146 goto err_dmaunmap;
f95f3850
WN		 3147 }
3148
b793f658
DA		 3149 /* Now that slots are all setup, we can enable card detect */
3150 dw_mci_enable_cd(host);
3151
f95f3850
WN		 3152 return 0;
3153
f95f3850
WN		 3154err_dmaunmap:
3155 if (host->use_dma && host->dma_ops->exit)
3156 host->dma_ops->exit(host);
f90a0612
TA		 3157
3158err_clk_ciu:
780f22af 3159 if (!IS_ERR(host->ciu_clk))
f90a0612 3160 clk_disable_unprepare(host->ciu_clk);
780f22af 3161
f90a0612 3162err_clk_biu:
780f22af 3163 if (!IS_ERR(host->biu_clk))
f90a0612 3164 clk_disable_unprepare(host->biu_clk);
780f22af 3165
f95f3850
WN		 3166 return ret;
3167}
62ca8034 3168EXPORT_SYMBOL(dw_mci_probe);
f95f3850 3169
62ca8034 3170void dw_mci_remove(struct dw_mci *host)
f95f3850 3171{
f95f3850
WN		 3172 int i;
3173
f95f3850 3174 for (i = 0; i < host->num_slots; i++) {
4a90920c 3175 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 3176 if (host->slot[i])
3177 dw_mci_cleanup_slot(host->slot[i], i);
3178 }
3179
048fd7e6
PT		 3180 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3181 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3182
f95f3850
WN		 3183 /* disable clock to CIU */
3184 mci_writel(host, CLKENA, 0);
3185 mci_writel(host, CLKSRC, 0);
3186
f95f3850
WN		 3187 if (host->use_dma && host->dma_ops->exit)
3188 host->dma_ops->exit(host);
3189
f90a0612
TA		 3190 if (!IS_ERR(host->ciu_clk))
3191 clk_disable_unprepare(host->ciu_clk);
780f22af 3192
f90a0612
TA		 3193 if (!IS_ERR(host->biu_clk))
3194 clk_disable_unprepare(host->biu_clk);
f95f3850 3195}
62ca8034
SH		 3196EXPORT_SYMBOL(dw_mci_remove);
3197
3198
f95f3850 3199
6fe8890d 3200#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 3201/*
3202 * TODO: we should probably disable the clock to the card in the suspend path.
3203 */
62ca8034 3204int dw_mci_suspend(struct dw_mci *host)
f95f3850 3205{
3fc7eaef
SL		 3206 if (host->use_dma && host->dma_ops->exit)
3207 host->dma_ops->exit(host);
3208
f95f3850
WN		 3209 return 0;
3210}
62ca8034 3211EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 3212
62ca8034 3213int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 3214{
3215 int i, ret;
f95f3850 3216
3a33a94c 3217 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
e61cf118
JC		 3218 ret = -ENODEV;
3219 return ret;
3220 }
3221
3bfe619d 3222 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 3223 host->dma_ops->init(host);
3224
52426899
SJ		 3225 /*
3226 * Restore the initial value at FIFOTH register
3227 * And Invalidate the prev_blksz with zero
3228 */
e61cf118 3229 mci_writel(host, FIFOTH, host->fifoth_val);
52426899 3230 host->prev_blksz = 0;
e61cf118 3231
2eb2944f
DA		 3232 /* Put in max timeout */
3233 mci_writel(host, TMOUT, 0xFFFFFFFF);
3234
e61cf118
JC		 3235 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3236 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3237 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3238 DW_MCI_ERROR_FLAGS);
e61cf118
JC		 3239 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3240
f95f3850
WN		 3241 for (i = 0; i < host->num_slots; i++) {
3242 struct dw_mci_slot *slot = host->slot[i];
0e3a22c0 3243
f95f3850
WN		 3244 if (!slot)
3245 continue;
ab269128
AK		 3246 if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
3247 dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
3248 dw_mci_setup_bus(slot, true);
3249 }
f95f3850 3250 }
fa0c3283
DA		 3251
3252 /* Now that slots are all setup, we can enable card detect */
3253 dw_mci_enable_cd(host);
3254
f95f3850
WN		 3255 return 0;
3256}
62ca8034 3257EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 3258#endif /* CONFIG_PM_SLEEP */
3259
f95f3850
WN		 3260static int __init dw_mci_init(void)
3261{
8e1c4e4d 3262 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
62ca8034 3263 return 0;
f95f3850
WN		 3264}
3265
3266static void __exit dw_mci_exit(void)
3267{
f95f3850
WN		 3268}
3269
3270module_init(dw_mci_init);
3271module_exit(dw_mci_exit);
3272
3273MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3274MODULE_AUTHOR("NXP Semiconductor VietNam");
3275MODULE_AUTHOR("Imagination Technologies Ltd");
3276MODULE_LICENSE("GPL v2");
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