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mmc: esdhc: Workaround for data crc error on p1010rdb
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
32#include <linux/mmc/dw_mmc.h>
33#include <linux/bitops.h>
c07946a3 34#include <linux/regulator/consumer.h>
1791b13e 35#include <linux/workqueue.h>
f95f3850
WN		 36
37#include "dw_mmc.h"
38
39/* Common flag combinations */
40#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
41 SDMMC_INT_HTO | SDMMC_INT_SBE | \
42 SDMMC_INT_EBE)
43#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
44 SDMMC_INT_RESP_ERR)
45#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
46 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
47#define DW_MCI_SEND_STATUS 1
48#define DW_MCI_RECV_STATUS 2
49#define DW_MCI_DMA_THRESHOLD 16
50
51#ifdef CONFIG_MMC_DW_IDMAC
52struct idmac_desc {
53 u32 des0; /* Control Descriptor */
54#define IDMAC_DES0_DIC BIT(1)
55#define IDMAC_DES0_LD BIT(2)
56#define IDMAC_DES0_FD BIT(3)
57#define IDMAC_DES0_CH BIT(4)
58#define IDMAC_DES0_ER BIT(5)
59#define IDMAC_DES0_CES BIT(30)
60#define IDMAC_DES0_OWN BIT(31)
61
62 u32 des1; /* Buffer sizes */
63#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 64 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850
WN		 65
66 u32 des2; /* buffer 1 physical address */
67
68 u32 des3; /* buffer 2 physical address */
69};
70#endif /* CONFIG_MMC_DW_IDMAC */
71
72/**
73 * struct dw_mci_slot - MMC slot state
74 * @mmc: The mmc_host representing this slot.
75 * @host: The MMC controller this slot is using.
76 * @ctype: Card type for this slot.
77 * @mrq: mmc_request currently being processed or waiting to be
78 * processed, or NULL when the slot is idle.
79 * @queue_node: List node for placing this node in the @queue list of
80 * &struct dw_mci.
81 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
82 * @flags: Random state bits associated with the slot.
83 * @id: Number of this slot.
84 * @last_detect_state: Most recently observed card detect state.
85 */
86struct dw_mci_slot {
87 struct mmc_host *mmc;
88 struct dw_mci *host;
89
90 u32 ctype;
91
92 struct mmc_request *mrq;
93 struct list_head queue_node;
94
95 unsigned int clock;
96 unsigned long flags;
97#define DW_MMC_CARD_PRESENT 0
98#define DW_MMC_CARD_NEED_INIT 1
99 int id;
100 int last_detect_state;
101};
102
1791b13e
JH		 103static struct workqueue_struct *dw_mci_card_workqueue;
104
f95f3850
WN		 105#if defined(CONFIG_DEBUG_FS)
106static int dw_mci_req_show(struct seq_file *s, void *v)
107{
108 struct dw_mci_slot *slot = s->private;
109 struct mmc_request *mrq;
110 struct mmc_command *cmd;
111 struct mmc_command *stop;
112 struct mmc_data *data;
113
114 /* Make sure we get a consistent snapshot */
115 spin_lock_bh(&slot->host->lock);
116 mrq = slot->mrq;
117
118 if (mrq) {
119 cmd = mrq->cmd;
120 data = mrq->data;
121 stop = mrq->stop;
122
123 if (cmd)
124 seq_printf(s,
125 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
126 cmd->opcode, cmd->arg, cmd->flags,
127 cmd->resp[0], cmd->resp[1], cmd->resp[2],
128 cmd->resp[2], cmd->error);
129 if (data)
130 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
131 data->bytes_xfered, data->blocks,
132 data->blksz, data->flags, data->error);
133 if (stop)
134 seq_printf(s,
135 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
136 stop->opcode, stop->arg, stop->flags,
137 stop->resp[0], stop->resp[1], stop->resp[2],
138 stop->resp[2], stop->error);
139 }
140
141 spin_unlock_bh(&slot->host->lock);
142
143 return 0;
144}
145
146static int dw_mci_req_open(struct inode *inode, struct file *file)
147{
148 return single_open(file, dw_mci_req_show, inode->i_private);
149}
150
151static const struct file_operations dw_mci_req_fops = {
152 .owner = THIS_MODULE,
153 .open = dw_mci_req_open,
154 .read = seq_read,
155 .llseek = seq_lseek,
156 .release = single_release,
157};
158
159static int dw_mci_regs_show(struct seq_file *s, void *v)
160{
161 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
162 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
163 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
164 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
165 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
166 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
167
168 return 0;
169}
170
171static int dw_mci_regs_open(struct inode *inode, struct file *file)
172{
173 return single_open(file, dw_mci_regs_show, inode->i_private);
174}
175
176static const struct file_operations dw_mci_regs_fops = {
177 .owner = THIS_MODULE,
178 .open = dw_mci_regs_open,
179 .read = seq_read,
180 .llseek = seq_lseek,
181 .release = single_release,
182};
183
184static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
185{
186 struct mmc_host *mmc = slot->mmc;
187 struct dw_mci *host = slot->host;
188 struct dentry *root;
189 struct dentry *node;
190
191 root = mmc->debugfs_root;
192 if (!root)
193 return;
194
195 node = debugfs_create_file("regs", S_IRUSR, root, host,
196 &dw_mci_regs_fops);
197 if (!node)
198 goto err;
199
200 node = debugfs_create_file("req", S_IRUSR, root, slot,
201 &dw_mci_req_fops);
202 if (!node)
203 goto err;
204
205 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
206 if (!node)
207 goto err;
208
209 node = debugfs_create_x32("pending_events", S_IRUSR, root,
210 (u32 *)&host->pending_events);
211 if (!node)
212 goto err;
213
214 node = debugfs_create_x32("completed_events", S_IRUSR, root,
215 (u32 *)&host->completed_events);
216 if (!node)
217 goto err;
218
219 return;
220
221err:
222 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
223}
224#endif /* defined(CONFIG_DEBUG_FS) */
225
226static void dw_mci_set_timeout(struct dw_mci *host)
227{
228 /* timeout (maximum) */
229 mci_writel(host, TMOUT, 0xffffffff);
230}
231
232static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
233{
234 struct mmc_data *data;
235 u32 cmdr;
236 cmd->error = -EINPROGRESS;
237
238 cmdr = cmd->opcode;
239
240 if (cmdr == MMC_STOP_TRANSMISSION)
241 cmdr |= SDMMC_CMD_STOP;
242 else
243 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
244
245 if (cmd->flags & MMC_RSP_PRESENT) {
246 /* We expect a response, so set this bit */
247 cmdr |= SDMMC_CMD_RESP_EXP;
248 if (cmd->flags & MMC_RSP_136)
249 cmdr |= SDMMC_CMD_RESP_LONG;
250 }
251
252 if (cmd->flags & MMC_RSP_CRC)
253 cmdr |= SDMMC_CMD_RESP_CRC;
254
255 data = cmd->data;
256 if (data) {
257 cmdr |= SDMMC_CMD_DAT_EXP;
258 if (data->flags & MMC_DATA_STREAM)
259 cmdr |= SDMMC_CMD_STRM_MODE;
260 if (data->flags & MMC_DATA_WRITE)
261 cmdr |= SDMMC_CMD_DAT_WR;
262 }
263
264 return cmdr;
265}
266
267static void dw_mci_start_command(struct dw_mci *host,
268 struct mmc_command *cmd, u32 cmd_flags)
269{
270 host->cmd = cmd;
62ca8034 271 dev_vdbg(&host->dev,
f95f3850
WN		 272 "start command: ARGR=0x%08x CMDR=0x%08x\n",
273 cmd->arg, cmd_flags);
274
275 mci_writel(host, CMDARG, cmd->arg);
276 wmb();
277
278 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
279}
280
281static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
282{
283 dw_mci_start_command(host, data->stop, host->stop_cmdr);
284}
285
286/* DMA interface functions */
287static void dw_mci_stop_dma(struct dw_mci *host)
288{
03e8cb53 289 if (host->using_dma) {
f95f3850
WN		 290 host->dma_ops->stop(host);
291 host->dma_ops->cleanup(host);
292 } else {
293 /* Data transfer was stopped by the interrupt handler */
294 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
295 }
296}
297
298#ifdef CONFIG_MMC_DW_IDMAC
9aa51408
SJ		 299static int dw_mci_get_dma_dir(struct mmc_data *data)
300{
301 if (data->flags & MMC_DATA_WRITE)
302 return DMA_TO_DEVICE;
303 else
304 return DMA_FROM_DEVICE;
305}
306
f95f3850
WN		 307static void dw_mci_dma_cleanup(struct dw_mci *host)
308{
309 struct mmc_data *data = host->data;
310
311 if (data)
9aa51408
SJ		 312 if (!data->host_cookie)
313 dma_unmap_sg(&host->dev,
314 data->sg,
315 data->sg_len,
316 dw_mci_get_dma_dir(data));
f95f3850
WN		 317}
318
319static void dw_mci_idmac_stop_dma(struct dw_mci *host)
320{
321 u32 temp;
322
323 /* Disable and reset the IDMAC interface */
324 temp = mci_readl(host, CTRL);
325 temp &= ~SDMMC_CTRL_USE_IDMAC;
326 temp |= SDMMC_CTRL_DMA_RESET;
327 mci_writel(host, CTRL, temp);
328
329 /* Stop the IDMAC running */
330 temp = mci_readl(host, BMOD);
a5289a43 331 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
f95f3850
WN		 332 mci_writel(host, BMOD, temp);
333}
334
335static void dw_mci_idmac_complete_dma(struct dw_mci *host)
336{
337 struct mmc_data *data = host->data;
338
62ca8034 339 dev_vdbg(&host->dev, "DMA complete\n");
f95f3850
WN		 340
341 host->dma_ops->cleanup(host);
342
343 /*
344 * If the card was removed, data will be NULL. No point in trying to
345 * send the stop command or waiting for NBUSY in this case.
346 */
347 if (data) {
348 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
349 tasklet_schedule(&host->tasklet);
350 }
351}
352
353static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
354 unsigned int sg_len)
355{
356 int i;
357 struct idmac_desc *desc = host->sg_cpu;
358
359 for (i = 0; i < sg_len; i++, desc++) {
360 unsigned int length = sg_dma_len(&data->sg[i]);
361 u32 mem_addr = sg_dma_address(&data->sg[i]);
362
363 /* Set the OWN bit and disable interrupts for this descriptor */
364 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
365
366 /* Buffer length */
367 IDMAC_SET_BUFFER1_SIZE(desc, length);
368
369 /* Physical address to DMA to/from */
370 desc->des2 = mem_addr;
371 }
372
373 /* Set first descriptor */
374 desc = host->sg_cpu;
375 desc->des0 |= IDMAC_DES0_FD;
376
377 /* Set last descriptor */
378 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
379 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
380 desc->des0 |= IDMAC_DES0_LD;
381
382 wmb();
383}
384
385static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
386{
387 u32 temp;
388
389 dw_mci_translate_sglist(host, host->data, sg_len);
390
391 /* Select IDMAC interface */
392 temp = mci_readl(host, CTRL);
393 temp |= SDMMC_CTRL_USE_IDMAC;
394 mci_writel(host, CTRL, temp);
395
396 wmb();
397
398 /* Enable the IDMAC */
399 temp = mci_readl(host, BMOD);
a5289a43 400 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 401 mci_writel(host, BMOD, temp);
402
403 /* Start it running */
404 mci_writel(host, PLDMND, 1);
405}
406
407static int dw_mci_idmac_init(struct dw_mci *host)
408{
409 struct idmac_desc *p;
410 int i;
411
412 /* Number of descriptors in the ring buffer */
413 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
414
415 /* Forward link the descriptor list */
416 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
417 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
418
419 /* Set the last descriptor as the end-of-ring descriptor */
420 p->des3 = host->sg_dma;
421 p->des0 = IDMAC_DES0_ER;
422
423 /* Mask out interrupts - get Tx & Rx complete only */
424 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
425 SDMMC_IDMAC_INT_TI);
426
427 /* Set the descriptor base address */
428 mci_writel(host, DBADDR, host->sg_dma);
429 return 0;
430}
431
9aa51408
SJ		 432static int dw_mci_pre_dma_transfer(struct dw_mci *host,
433 struct mmc_data *data,
434 bool next)
f95f3850
WN		 435{
436 struct scatterlist *sg;
9aa51408 437 unsigned int i, sg_len;
03e8cb53 438
9aa51408
SJ		 439 if (!next && data->host_cookie)
440 return data->host_cookie;
f95f3850
WN		 441
442 /*
443 * We don't do DMA on "complex" transfers, i.e. with
444 * non-word-aligned buffers or lengths. Also, we don't bother
445 * with all the DMA setup overhead for short transfers.
446 */
447 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
448 return -EINVAL;
9aa51408 449
f95f3850
WN		 450 if (data->blksz & 3)
451 return -EINVAL;
452
453 for_each_sg(data->sg, sg, data->sg_len, i) {
454 if (sg->offset & 3 || sg->length & 3)
455 return -EINVAL;
456 }
457
9aa51408
SJ		 458 sg_len = dma_map_sg(&host->dev,
459 data->sg,
460 data->sg_len,
461 dw_mci_get_dma_dir(data));
462 if (sg_len == 0)
463 return -EINVAL;
03e8cb53 464
9aa51408
SJ		 465 if (next)
466 data->host_cookie = sg_len;
f95f3850 467
9aa51408
SJ		 468 return sg_len;
469}
470
471static struct dw_mci_dma_ops dw_mci_idmac_ops = {
472 .init = dw_mci_idmac_init,
473 .start = dw_mci_idmac_start_dma,
474 .stop = dw_mci_idmac_stop_dma,
475 .complete = dw_mci_idmac_complete_dma,
476 .cleanup = dw_mci_dma_cleanup,
477};
478#else
479static int dw_mci_pre_dma_transfer(struct dw_mci *host,
480 struct mmc_data *data,
481 bool next)
482{
483 return -ENOSYS;
484}
485#endif /* CONFIG_MMC_DW_IDMAC */
486
487static void dw_mci_pre_req(struct mmc_host *mmc,
488 struct mmc_request *mrq,
489 bool is_first_req)
490{
491 struct dw_mci_slot *slot = mmc_priv(mmc);
492 struct mmc_data *data = mrq->data;
493
494 if (!slot->host->use_dma || !data)
495 return;
496
497 if (data->host_cookie) {
498 data->host_cookie = 0;
499 return;
500 }
501
502 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
503 data->host_cookie = 0;
504}
505
506static void dw_mci_post_req(struct mmc_host *mmc,
507 struct mmc_request *mrq,
508 int err)
509{
510 struct dw_mci_slot *slot = mmc_priv(mmc);
511 struct mmc_data *data = mrq->data;
512
513 if (!slot->host->use_dma || !data)
514 return;
515
516 if (data->host_cookie)
517 dma_unmap_sg(&slot->host->dev,
518 data->sg,
519 data->sg_len,
520 dw_mci_get_dma_dir(data));
521 data->host_cookie = 0;
522}
523
524static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
525{
526 int sg_len;
527 u32 temp;
528
529 host->using_dma = 0;
530
531 /* If we don't have a channel, we can't do DMA */
532 if (!host->use_dma)
533 return -ENODEV;
534
535 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
536 if (sg_len < 0)
537 return sg_len;
538
539 host->using_dma = 1;
f95f3850 540
62ca8034 541 dev_vdbg(&host->dev,
f95f3850
WN		 542 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
543 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
544 sg_len);
545
546 /* Enable the DMA interface */
547 temp = mci_readl(host, CTRL);
548 temp |= SDMMC_CTRL_DMA_ENABLE;
549 mci_writel(host, CTRL, temp);
550
551 /* Disable RX/TX IRQs, let DMA handle it */
552 temp = mci_readl(host, INTMASK);
553 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
554 mci_writel(host, INTMASK, temp);
555
556 host->dma_ops->start(host, sg_len);
557
558 return 0;
559}
560
561static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
562{
563 u32 temp;
564
565 data->error = -EINPROGRESS;
566
567 WARN_ON(host->data);
568 host->sg = NULL;
569 host->data = data;
570
55c5efbc
JH		 571 if (data->flags & MMC_DATA_READ)
572 host->dir_status = DW_MCI_RECV_STATUS;
573 else
574 host->dir_status = DW_MCI_SEND_STATUS;
575
f95f3850 576 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 577 int flags = SG_MITER_ATOMIC;
578 if (host->data->flags & MMC_DATA_READ)
579 flags |= SG_MITER_TO_SG;
580 else
581 flags |= SG_MITER_FROM_SG;
582
583 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 584 host->sg = data->sg;
34b664a2
JH		 585 host->part_buf_start = 0;
586 host->part_buf_count = 0;
f95f3850 587
b40af3aa 588 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 589 temp = mci_readl(host, INTMASK);
590 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
591 mci_writel(host, INTMASK, temp);
592
593 temp = mci_readl(host, CTRL);
594 temp &= ~SDMMC_CTRL_DMA_ENABLE;
595 mci_writel(host, CTRL, temp);
596 }
597}
598
599static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
600{
601 struct dw_mci *host = slot->host;
602 unsigned long timeout = jiffies + msecs_to_jiffies(500);
603 unsigned int cmd_status = 0;
604
605 mci_writel(host, CMDARG, arg);
606 wmb();
607 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
608
609 while (time_before(jiffies, timeout)) {
610 cmd_status = mci_readl(host, CMD);
611 if (!(cmd_status & SDMMC_CMD_START))
612 return;
613 }
614 dev_err(&slot->mmc->class_dev,
615 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
616 cmd, arg, cmd_status);
617}
618
619static void dw_mci_setup_bus(struct dw_mci_slot *slot)
620{
621 struct dw_mci *host = slot->host;
622 u32 div;
623
624 if (slot->clock != host->current_speed) {
625 if (host->bus_hz % slot->clock)
626 /*
627 * move the + 1 after the divide to prevent
628 * over-clocking the card.
629 */
630 div = ((host->bus_hz / slot->clock) >> 1) + 1;
631 else
632 div = (host->bus_hz / slot->clock) >> 1;
633
634 dev_info(&slot->mmc->class_dev,
635 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
636 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
637 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
638
639 /* disable clock */
640 mci_writel(host, CLKENA, 0);
641 mci_writel(host, CLKSRC, 0);
642
643 /* inform CIU */
644 mci_send_cmd(slot,
645 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
646
647 /* set clock to desired speed */
648 mci_writel(host, CLKDIV, div);
649
650 /* inform CIU */
651 mci_send_cmd(slot,
652 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
653
654 /* enable clock */
aadb9f41
WN		 655 mci_writel(host, CLKENA, SDMMC_CLKEN_ENABLE |
656 SDMMC_CLKEN_LOW_PWR);
f95f3850
WN		 657
658 /* inform CIU */
659 mci_send_cmd(slot,
660 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
661
662 host->current_speed = slot->clock;
663 }
664
665 /* Set the current slot bus width */
1d56c453 666 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 667}
668
053b3ce6
SJ		 669static void __dw_mci_start_request(struct dw_mci *host,
670 struct dw_mci_slot *slot,
671 struct mmc_command *cmd)
f95f3850
WN		 672{
673 struct mmc_request *mrq;
f95f3850
WN		 674 struct mmc_data *data;
675 u32 cmdflags;
676
677 mrq = slot->mrq;
678 if (host->pdata->select_slot)
679 host->pdata->select_slot(slot->id);
680
681 /* Slot specific timing and width adjustment */
682 dw_mci_setup_bus(slot);
683
684 host->cur_slot = slot;
685 host->mrq = mrq;
686
687 host->pending_events = 0;
688 host->completed_events = 0;
689 host->data_status = 0;
690
053b3ce6 691 data = cmd->data;
f95f3850
WN		 692 if (data) {
693 dw_mci_set_timeout(host);
694 mci_writel(host, BYTCNT, data->blksz*data->blocks);
695 mci_writel(host, BLKSIZ, data->blksz);
696 }
697
f95f3850
WN		 698 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
699
700 /* this is the first command, send the initialization clock */
701 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
702 cmdflags |= SDMMC_CMD_INIT;
703
704 if (data) {
705 dw_mci_submit_data(host, data);
706 wmb();
707 }
708
709 dw_mci_start_command(host, cmd, cmdflags);
710
711 if (mrq->stop)
712 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
713}
714
053b3ce6
SJ		 715static void dw_mci_start_request(struct dw_mci *host,
716 struct dw_mci_slot *slot)
717{
718 struct mmc_request *mrq = slot->mrq;
719 struct mmc_command *cmd;
720
721 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
722 __dw_mci_start_request(host, slot, cmd);
723}
724
7456caae 725/* must be called with host->lock held */
f95f3850
WN		 726static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
727 struct mmc_request *mrq)
728{
729 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
730 host->state);
731
f95f3850
WN		 732 slot->mrq = mrq;
733
734 if (host->state == STATE_IDLE) {
735 host->state = STATE_SENDING_CMD;
736 dw_mci_start_request(host, slot);
737 } else {
738 list_add_tail(&slot->queue_node, &host->queue);
739 }
f95f3850
WN		 740}
741
742static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
743{
744 struct dw_mci_slot *slot = mmc_priv(mmc);
745 struct dw_mci *host = slot->host;
746
747 WARN_ON(slot->mrq);
748
7456caae
JH		 749 /*
750 * The check for card presence and queueing of the request must be
751 * atomic, otherwise the card could be removed in between and the
752 * request wouldn't fail until another card was inserted.
753 */
754 spin_lock_bh(&host->lock);
755
f95f3850 756 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 757 spin_unlock_bh(&host->lock);
f95f3850
WN		 758 mrq->cmd->error = -ENOMEDIUM;
759 mmc_request_done(mmc, mrq);
760 return;
761 }
762
f95f3850 763 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 764
765 spin_unlock_bh(&host->lock);
f95f3850
WN		 766}
767
768static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
769{
770 struct dw_mci_slot *slot = mmc_priv(mmc);
41babf75 771 u32 regs;
f95f3850
WN		 772
773 /* set default 1 bit mode */
774 slot->ctype = SDMMC_CTYPE_1BIT;
775
776 switch (ios->bus_width) {
777 case MMC_BUS_WIDTH_1:
778 slot->ctype = SDMMC_CTYPE_1BIT;
779 break;
780 case MMC_BUS_WIDTH_4:
781 slot->ctype = SDMMC_CTYPE_4BIT;
782 break;
c9b2a06f
JC		 783 case MMC_BUS_WIDTH_8:
784 slot->ctype = SDMMC_CTYPE_8BIT;
785 break;
f95f3850
WN		 786 }
787
3f514291
SJ		 788 regs = mci_readl(slot->host, UHS_REG);
789
41babf75 790 /* DDR mode set */
3f514291 791 if (ios->timing == MMC_TIMING_UHS_DDR50)
41babf75 792 regs |= (0x1 << slot->id) << 16;
3f514291
SJ		 793 else
794 regs &= ~(0x1 << slot->id) << 16;
795
796 mci_writel(slot->host, UHS_REG, regs);
41babf75 797
f95f3850
WN		 798 if (ios->clock) {
799 /*
800 * Use mirror of ios->clock to prevent race with mmc
801 * core ios update when finding the minimum.
802 */
803 slot->clock = ios->clock;
804 }
805
806 switch (ios->power_mode) {
807 case MMC_POWER_UP:
808 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
809 break;
810 default:
811 break;
812 }
813}
814
815static int dw_mci_get_ro(struct mmc_host *mmc)
816{
817 int read_only;
818 struct dw_mci_slot *slot = mmc_priv(mmc);
819 struct dw_mci_board *brd = slot->host->pdata;
820
821 /* Use platform get_ro function, else try on board write protect */
822 if (brd->get_ro)
823 read_only = brd->get_ro(slot->id);
824 else
825 read_only =
826 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
827
828 dev_dbg(&mmc->class_dev, "card is %s\n",
829 read_only ? "read-only" : "read-write");
830
831 return read_only;
832}
833
834static int dw_mci_get_cd(struct mmc_host *mmc)
835{
836 int present;
837 struct dw_mci_slot *slot = mmc_priv(mmc);
838 struct dw_mci_board *brd = slot->host->pdata;
839
840 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 841 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
842 present = 1;
843 else if (brd->get_cd)
f95f3850
WN		 844 present = !brd->get_cd(slot->id);
845 else
846 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
847 == 0 ? 1 : 0;
848
849 if (present)
850 dev_dbg(&mmc->class_dev, "card is present\n");
851 else
852 dev_dbg(&mmc->class_dev, "card is not present\n");
853
854 return present;
855}
856
1a5c8e1f
SH		 857static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
858{
859 struct dw_mci_slot *slot = mmc_priv(mmc);
860 struct dw_mci *host = slot->host;
861 u32 int_mask;
862
863 /* Enable/disable Slot Specific SDIO interrupt */
864 int_mask = mci_readl(host, INTMASK);
865 if (enb) {
866 mci_writel(host, INTMASK,
867 (int_mask | (1 << SDMMC_INT_SDIO(slot->id))));
868 } else {
869 mci_writel(host, INTMASK,
870 (int_mask & ~(1 << SDMMC_INT_SDIO(slot->id))));
871 }
872}
873
f95f3850 874static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 875 .request = dw_mci_request,
9aa51408
SJ		 876 .pre_req = dw_mci_pre_req,
877 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 878 .set_ios = dw_mci_set_ios,
879 .get_ro = dw_mci_get_ro,
880 .get_cd = dw_mci_get_cd,
881 .enable_sdio_irq = dw_mci_enable_sdio_irq,
f95f3850
WN		 882};
883
884static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
885 __releases(&host->lock)
886 __acquires(&host->lock)
887{
888 struct dw_mci_slot *slot;
889 struct mmc_host *prev_mmc = host->cur_slot->mmc;
890
891 WARN_ON(host->cmd || host->data);
892
893 host->cur_slot->mrq = NULL;
894 host->mrq = NULL;
895 if (!list_empty(&host->queue)) {
896 slot = list_entry(host->queue.next,
897 struct dw_mci_slot, queue_node);
898 list_del(&slot->queue_node);
62ca8034 899 dev_vdbg(&host->dev, "list not empty: %s is next\n",
f95f3850
WN		 900 mmc_hostname(slot->mmc));
901 host->state = STATE_SENDING_CMD;
902 dw_mci_start_request(host, slot);
903 } else {
62ca8034 904 dev_vdbg(&host->dev, "list empty\n");
f95f3850
WN		 905 host->state = STATE_IDLE;
906 }
907
908 spin_unlock(&host->lock);
909 mmc_request_done(prev_mmc, mrq);
910 spin_lock(&host->lock);
911}
912
913static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
914{
915 u32 status = host->cmd_status;
916
917 host->cmd_status = 0;
918
919 /* Read the response from the card (up to 16 bytes) */
920 if (cmd->flags & MMC_RSP_PRESENT) {
921 if (cmd->flags & MMC_RSP_136) {
922 cmd->resp[3] = mci_readl(host, RESP0);
923 cmd->resp[2] = mci_readl(host, RESP1);
924 cmd->resp[1] = mci_readl(host, RESP2);
925 cmd->resp[0] = mci_readl(host, RESP3);
926 } else {
927 cmd->resp[0] = mci_readl(host, RESP0);
928 cmd->resp[1] = 0;
929 cmd->resp[2] = 0;
930 cmd->resp[3] = 0;
931 }
932 }
933
934 if (status & SDMMC_INT_RTO)
935 cmd->error = -ETIMEDOUT;
936 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
937 cmd->error = -EILSEQ;
938 else if (status & SDMMC_INT_RESP_ERR)
939 cmd->error = -EIO;
940 else
941 cmd->error = 0;
942
943 if (cmd->error) {
944 /* newer ip versions need a delay between retries */
945 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
946 mdelay(20);
947
948 if (cmd->data) {
949 host->data = NULL;
950 dw_mci_stop_dma(host);
951 }
952 }
953}
954
955static void dw_mci_tasklet_func(unsigned long priv)
956{
957 struct dw_mci *host = (struct dw_mci *)priv;
958 struct mmc_data *data;
959 struct mmc_command *cmd;
960 enum dw_mci_state state;
961 enum dw_mci_state prev_state;
94dd5b33 962 u32 status, ctrl;
f95f3850
WN		 963
964 spin_lock(&host->lock);
965
966 state = host->state;
967 data = host->data;
968
969 do {
970 prev_state = state;
971
972 switch (state) {
973 case STATE_IDLE:
974 break;
975
976 case STATE_SENDING_CMD:
977 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
978 &host->pending_events))
979 break;
980
981 cmd = host->cmd;
982 host->cmd = NULL;
983 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
053b3ce6
SJ		 984 dw_mci_command_complete(host, cmd);
985 if (cmd == host->mrq->sbc && !cmd->error) {
986 prev_state = state = STATE_SENDING_CMD;
987 __dw_mci_start_request(host, host->cur_slot,
988 host->mrq->cmd);
989 goto unlock;
990 }
991
f95f3850
WN		 992 if (!host->mrq->data || cmd->error) {
993 dw_mci_request_end(host, host->mrq);
994 goto unlock;
995 }
996
997 prev_state = state = STATE_SENDING_DATA;
998 /* fall through */
999
1000 case STATE_SENDING_DATA:
1001 if (test_and_clear_bit(EVENT_DATA_ERROR,
1002 &host->pending_events)) {
1003 dw_mci_stop_dma(host);
1004 if (data->stop)
1005 send_stop_cmd(host, data);
1006 state = STATE_DATA_ERROR;
1007 break;
1008 }
1009
1010 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1011 &host->pending_events))
1012 break;
1013
1014 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1015 prev_state = state = STATE_DATA_BUSY;
1016 /* fall through */
1017
1018 case STATE_DATA_BUSY:
1019 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1020 &host->pending_events))
1021 break;
1022
1023 host->data = NULL;
1024 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1025 status = host->data_status;
1026
1027 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1028 if (status & SDMMC_INT_DTO) {
f95f3850
WN		 1029 data->error = -ETIMEDOUT;
1030 } else if (status & SDMMC_INT_DCRC) {
f95f3850 1031 data->error = -EILSEQ;
55c5efbc
JH		 1032 } else if (status & SDMMC_INT_EBE &&
1033 host->dir_status ==
1034 DW_MCI_SEND_STATUS) {
1035 /*
1036 * No data CRC status was returned.
1037 * The number of bytes transferred will
1038 * be exaggerated in PIO mode.
1039 */
1040 data->bytes_xfered = 0;
1041 data->error = -ETIMEDOUT;
f95f3850 1042 } else {
62ca8034 1043 dev_err(&host->dev,
f95f3850
WN		 1044 "data FIFO error "
1045 "(status=%08x)\n",
1046 status);
1047 data->error = -EIO;
1048 }
94dd5b33
JH		 1049 /*
1050 * After an error, there may be data lingering
1051 * in the FIFO, so reset it - doing so
1052 * generates a block interrupt, hence setting
1053 * the scatter-gather pointer to NULL.
1054 */
f9c2a0dc 1055 sg_miter_stop(&host->sg_miter);
94dd5b33
JH		 1056 host->sg = NULL;
1057 ctrl = mci_readl(host, CTRL);
1058 ctrl |= SDMMC_CTRL_FIFO_RESET;
1059 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 1060 } else {
1061 data->bytes_xfered = data->blocks * data->blksz;
1062 data->error = 0;
1063 }
1064
1065 if (!data->stop) {
1066 dw_mci_request_end(host, host->mrq);
1067 goto unlock;
1068 }
1069
053b3ce6
SJ		 1070 if (host->mrq->sbc && !data->error) {
1071 data->stop->error = 0;
1072 dw_mci_request_end(host, host->mrq);
1073 goto unlock;
1074 }
1075
f95f3850
WN		 1076 prev_state = state = STATE_SENDING_STOP;
1077 if (!data->error)
1078 send_stop_cmd(host, data);
1079 /* fall through */
1080
1081 case STATE_SENDING_STOP:
1082 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1083 &host->pending_events))
1084 break;
1085
1086 host->cmd = NULL;
1087 dw_mci_command_complete(host, host->mrq->stop);
1088 dw_mci_request_end(host, host->mrq);
1089 goto unlock;
1090
1091 case STATE_DATA_ERROR:
1092 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1093 &host->pending_events))
1094 break;
1095
1096 state = STATE_DATA_BUSY;
1097 break;
1098 }
1099 } while (state != prev_state);
1100
1101 host->state = state;
1102unlock:
1103 spin_unlock(&host->lock);
1104
1105}
1106
34b664a2
JH		 1107/* push final bytes to part_buf, only use during push */
1108static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1109{
34b664a2
JH		 1110 memcpy((void *)&host->part_buf, buf, cnt);
1111 host->part_buf_count = cnt;
1112}
f95f3850 1113
34b664a2
JH		 1114/* append bytes to part_buf, only use during push */
1115static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1116{
1117 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1118 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1119 host->part_buf_count += cnt;
1120 return cnt;
1121}
f95f3850 1122
34b664a2
JH		 1123/* pull first bytes from part_buf, only use during pull */
1124static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1125{
1126 cnt = min(cnt, (int)host->part_buf_count);
1127 if (cnt) {
1128 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1129 cnt);
1130 host->part_buf_count -= cnt;
1131 host->part_buf_start += cnt;
f95f3850 1132 }
34b664a2 1133 return cnt;
f95f3850
WN		 1134}
1135
34b664a2
JH		 1136/* pull final bytes from the part_buf, assuming it's just been filled */
1137static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1138{
34b664a2
JH		 1139 memcpy(buf, &host->part_buf, cnt);
1140 host->part_buf_start = cnt;
1141 host->part_buf_count = (1 << host->data_shift) - cnt;
1142}
f95f3850 1143
34b664a2
JH		 1144static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1145{
1146 /* try and push anything in the part_buf */
1147 if (unlikely(host->part_buf_count)) {
1148 int len = dw_mci_push_part_bytes(host, buf, cnt);
1149 buf += len;
1150 cnt -= len;
1151 if (!sg_next(host->sg) || host->part_buf_count == 2) {
4e0a5adf
JC		 1152 mci_writew(host, DATA(host->data_offset),
1153 host->part_buf16);
34b664a2
JH		 1154 host->part_buf_count = 0;
1155 }
1156 }
1157#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1158 if (unlikely((unsigned long)buf & 0x1)) {
1159 while (cnt >= 2) {
1160 u16 aligned_buf[64];
1161 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1162 int items = len >> 1;
1163 int i;
1164 /* memcpy from input buffer into aligned buffer */
1165 memcpy(aligned_buf, buf, len);
1166 buf += len;
1167 cnt -= len;
1168 /* push data from aligned buffer into fifo */
1169 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1170 mci_writew(host, DATA(host->data_offset),
1171 aligned_buf[i]);
34b664a2
JH		 1172 }
1173 } else
1174#endif
1175 {
1176 u16 *pdata = buf;
1177 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1178 mci_writew(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1179 buf = pdata;
1180 }
1181 /* put anything remaining in the part_buf */
1182 if (cnt) {
1183 dw_mci_set_part_bytes(host, buf, cnt);
1184 if (!sg_next(host->sg))
4e0a5adf
JC		 1185 mci_writew(host, DATA(host->data_offset),
1186 host->part_buf16);
34b664a2
JH		 1187 }
1188}
f95f3850 1189
34b664a2
JH		 1190static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1191{
1192#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1193 if (unlikely((unsigned long)buf & 0x1)) {
1194 while (cnt >= 2) {
1195 /* pull data from fifo into aligned buffer */
1196 u16 aligned_buf[64];
1197 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1198 int items = len >> 1;
1199 int i;
1200 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1201 aligned_buf[i] = mci_readw(host,
1202 DATA(host->data_offset));
34b664a2
JH		 1203 /* memcpy from aligned buffer into output buffer */
1204 memcpy(buf, aligned_buf, len);
1205 buf += len;
1206 cnt -= len;
1207 }
1208 } else
1209#endif
1210 {
1211 u16 *pdata = buf;
1212 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1213 *pdata++ = mci_readw(host, DATA(host->data_offset));
34b664a2
JH		 1214 buf = pdata;
1215 }
1216 if (cnt) {
4e0a5adf 1217 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
34b664a2 1218 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1219 }
1220}
1221
1222static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1223{
34b664a2
JH		 1224 /* try and push anything in the part_buf */
1225 if (unlikely(host->part_buf_count)) {
1226 int len = dw_mci_push_part_bytes(host, buf, cnt);
1227 buf += len;
1228 cnt -= len;
1229 if (!sg_next(host->sg) || host->part_buf_count == 4) {
4e0a5adf
JC		 1230 mci_writel(host, DATA(host->data_offset),
1231 host->part_buf32);
34b664a2
JH		 1232 host->part_buf_count = 0;
1233 }
1234 }
1235#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1236 if (unlikely((unsigned long)buf & 0x3)) {
1237 while (cnt >= 4) {
1238 u32 aligned_buf[32];
1239 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1240 int items = len >> 2;
1241 int i;
1242 /* memcpy from input buffer into aligned buffer */
1243 memcpy(aligned_buf, buf, len);
1244 buf += len;
1245 cnt -= len;
1246 /* push data from aligned buffer into fifo */
1247 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1248 mci_writel(host, DATA(host->data_offset),
1249 aligned_buf[i]);
34b664a2
JH		 1250 }
1251 } else
1252#endif
1253 {
1254 u32 *pdata = buf;
1255 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1256 mci_writel(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1257 buf = pdata;
1258 }
1259 /* put anything remaining in the part_buf */
1260 if (cnt) {
1261 dw_mci_set_part_bytes(host, buf, cnt);
1262 if (!sg_next(host->sg))
4e0a5adf
JC		 1263 mci_writel(host, DATA(host->data_offset),
1264 host->part_buf32);
f95f3850
WN		 1265 }
1266}
1267
1268static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1269{
34b664a2
JH		 1270#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1271 if (unlikely((unsigned long)buf & 0x3)) {
1272 while (cnt >= 4) {
1273 /* pull data from fifo into aligned buffer */
1274 u32 aligned_buf[32];
1275 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1276 int items = len >> 2;
1277 int i;
1278 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1279 aligned_buf[i] = mci_readl(host,
1280 DATA(host->data_offset));
34b664a2
JH		 1281 /* memcpy from aligned buffer into output buffer */
1282 memcpy(buf, aligned_buf, len);
1283 buf += len;
1284 cnt -= len;
1285 }
1286 } else
1287#endif
1288 {
1289 u32 *pdata = buf;
1290 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1291 *pdata++ = mci_readl(host, DATA(host->data_offset));
34b664a2
JH		 1292 buf = pdata;
1293 }
1294 if (cnt) {
4e0a5adf 1295 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
34b664a2 1296 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1297 }
1298}
1299
1300static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1301{
34b664a2
JH		 1302 /* try and push anything in the part_buf */
1303 if (unlikely(host->part_buf_count)) {
1304 int len = dw_mci_push_part_bytes(host, buf, cnt);
1305 buf += len;
1306 cnt -= len;
1307 if (!sg_next(host->sg) || host->part_buf_count == 8) {
4e0a5adf
JC		 1308 mci_writew(host, DATA(host->data_offset),
1309 host->part_buf);
34b664a2
JH		 1310 host->part_buf_count = 0;
1311 }
1312 }
1313#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1314 if (unlikely((unsigned long)buf & 0x7)) {
1315 while (cnt >= 8) {
1316 u64 aligned_buf[16];
1317 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1318 int items = len >> 3;
1319 int i;
1320 /* memcpy from input buffer into aligned buffer */
1321 memcpy(aligned_buf, buf, len);
1322 buf += len;
1323 cnt -= len;
1324 /* push data from aligned buffer into fifo */
1325 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1326 mci_writeq(host, DATA(host->data_offset),
1327 aligned_buf[i]);
34b664a2
JH		 1328 }
1329 } else
1330#endif
1331 {
1332 u64 *pdata = buf;
1333 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1334 mci_writeq(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1335 buf = pdata;
1336 }
1337 /* put anything remaining in the part_buf */
1338 if (cnt) {
1339 dw_mci_set_part_bytes(host, buf, cnt);
1340 if (!sg_next(host->sg))
4e0a5adf
JC		 1341 mci_writeq(host, DATA(host->data_offset),
1342 host->part_buf);
f95f3850
WN		 1343 }
1344}
1345
1346static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1347{
34b664a2
JH		 1348#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1349 if (unlikely((unsigned long)buf & 0x7)) {
1350 while (cnt >= 8) {
1351 /* pull data from fifo into aligned buffer */
1352 u64 aligned_buf[16];
1353 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1354 int items = len >> 3;
1355 int i;
1356 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1357 aligned_buf[i] = mci_readq(host,
1358 DATA(host->data_offset));
34b664a2
JH		 1359 /* memcpy from aligned buffer into output buffer */
1360 memcpy(buf, aligned_buf, len);
1361 buf += len;
1362 cnt -= len;
1363 }
1364 } else
1365#endif
1366 {
1367 u64 *pdata = buf;
1368 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1369 *pdata++ = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1370 buf = pdata;
1371 }
1372 if (cnt) {
4e0a5adf 1373 host->part_buf = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1374 dw_mci_pull_final_bytes(host, buf, cnt);
1375 }
1376}
f95f3850 1377
34b664a2
JH		 1378static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1379{
1380 int len;
f95f3850 1381
34b664a2
JH		 1382 /* get remaining partial bytes */
1383 len = dw_mci_pull_part_bytes(host, buf, cnt);
1384 if (unlikely(len == cnt))
1385 return;
1386 buf += len;
1387 cnt -= len;
1388
1389 /* get the rest of the data */
1390 host->pull_data(host, buf, cnt);
f95f3850
WN		 1391}
1392
1393static void dw_mci_read_data_pio(struct dw_mci *host)
1394{
f9c2a0dc
SJ		 1395 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1396 void *buf;
1397 unsigned int offset;
f95f3850
WN		 1398 struct mmc_data *data = host->data;
1399 int shift = host->data_shift;
1400 u32 status;
ba6a902d 1401 unsigned int nbytes = 0, len;
f9c2a0dc 1402 unsigned int remain, fcnt;
f95f3850
WN		 1403
1404 do {
f9c2a0dc
SJ		 1405 if (!sg_miter_next(sg_miter))
1406 goto done;
1407
1408 host->sg = sg_miter->__sg;
1409 buf = sg_miter->addr;
1410 remain = sg_miter->length;
1411 offset = 0;
1412
1413 do {
1414 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1415 << shift) + host->part_buf_count;
1416 len = min(remain, fcnt);
1417 if (!len)
1418 break;
34b664a2 1419 dw_mci_pull_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1420 offset += len;
1421 nbytes += len;
f9c2a0dc
SJ		 1422 remain -= len;
1423 } while (remain);
1424 sg_miter->consumed = offset;
f95f3850
WN		 1425
1426 status = mci_readl(host, MINTSTS);
1427 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
1428 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1429 host->data_status = status;
1430 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1431 sg_miter_stop(sg_miter);
1432 host->sg = NULL;
f95f3850
WN		 1433 smp_wmb();
1434
1435 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1436
1437 tasklet_schedule(&host->tasklet);
1438 return;
1439 }
f95f3850 1440 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
f95f3850 1441 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1442
1443 if (!remain) {
1444 if (!sg_miter_next(sg_miter))
1445 goto done;
1446 sg_miter->consumed = 0;
1447 }
1448 sg_miter_stop(sg_miter);
f95f3850
WN		 1449 return;
1450
1451done:
1452 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1453 sg_miter_stop(sg_miter);
1454 host->sg = NULL;
f95f3850
WN		 1455 smp_wmb();
1456 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1457}
1458
1459static void dw_mci_write_data_pio(struct dw_mci *host)
1460{
f9c2a0dc
SJ		 1461 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1462 void *buf;
1463 unsigned int offset;
f95f3850
WN		 1464 struct mmc_data *data = host->data;
1465 int shift = host->data_shift;
1466 u32 status;
1467 unsigned int nbytes = 0, len;
f9c2a0dc
SJ		 1468 unsigned int fifo_depth = host->fifo_depth;
1469 unsigned int remain, fcnt;
f95f3850
WN		 1470
1471 do {
f9c2a0dc
SJ		 1472 if (!sg_miter_next(sg_miter))
1473 goto done;
1474
1475 host->sg = sg_miter->__sg;
1476 buf = sg_miter->addr;
1477 remain = sg_miter->length;
1478 offset = 0;
1479
1480 do {
1481 fcnt = ((fifo_depth -
1482 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1483 << shift) - host->part_buf_count;
1484 len = min(remain, fcnt);
1485 if (!len)
1486 break;
f95f3850 1487 host->push_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1488 offset += len;
1489 nbytes += len;
f9c2a0dc
SJ		 1490 remain -= len;
1491 } while (remain);
1492 sg_miter->consumed = offset;
f95f3850
WN		 1493
1494 status = mci_readl(host, MINTSTS);
1495 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
1496 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1497 host->data_status = status;
1498 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1499 sg_miter_stop(sg_miter);
1500 host->sg = NULL;
f95f3850
WN		 1501
1502 smp_wmb();
1503
1504 set_bit(EVENT_DATA_ERROR, &host->pending_events);
1505
1506 tasklet_schedule(&host->tasklet);
1507 return;
1508 }
1509 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f95f3850 1510 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1511
1512 if (!remain) {
1513 if (!sg_miter_next(sg_miter))
1514 goto done;
1515 sg_miter->consumed = 0;
1516 }
1517 sg_miter_stop(sg_miter);
f95f3850
WN		 1518 return;
1519
1520done:
1521 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1522 sg_miter_stop(sg_miter);
1523 host->sg = NULL;
f95f3850
WN		 1524 smp_wmb();
1525 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1526}
1527
1528static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1529{
1530 if (!host->cmd_status)
1531 host->cmd_status = status;
1532
1533 smp_wmb();
1534
1535 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1536 tasklet_schedule(&host->tasklet);
1537}
1538
1539static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1540{
1541 struct dw_mci *host = dev_id;
1542 u32 status, pending;
1543 unsigned int pass_count = 0;
1a5c8e1f 1544 int i;
f95f3850
WN		 1545
1546 do {
1547 status = mci_readl(host, RINTSTS);
1548 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1549
1550 /*
1551 * DTO fix - version 2.10a and below, and only if internal DMA
1552 * is configured.
1553 */
1554 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1555 if (!pending &&
1556 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1557 pending |= SDMMC_INT_DATA_OVER;
1558 }
1559
1560 if (!pending)
1561 break;
1562
1563 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1564 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
1565 host->cmd_status = status;
1566 smp_wmb();
1567 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1568 }
1569
1570 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1571 /* if there is an error report DATA_ERROR */
1572 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
1573 host->data_status = status;
1574 smp_wmb();
1575 set_bit(EVENT_DATA_ERROR, &host->pending_events);
6e83e10d
SJ		 1576 if (!(pending & (SDMMC_INT_DTO | SDMMC_INT_DCRC |
1577 SDMMC_INT_SBE | SDMMC_INT_EBE)))
1578 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1579 }
1580
1581 if (pending & SDMMC_INT_DATA_OVER) {
1582 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1583 if (!host->data_status)
1584 host->data_status = status;
1585 smp_wmb();
1586 if (host->dir_status == DW_MCI_RECV_STATUS) {
1587 if (host->sg != NULL)
1588 dw_mci_read_data_pio(host);
1589 }
1590 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1591 tasklet_schedule(&host->tasklet);
1592 }
1593
1594 if (pending & SDMMC_INT_RXDR) {
1595 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 1596 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
f95f3850
WN		 1597 dw_mci_read_data_pio(host);
1598 }
1599
1600 if (pending & SDMMC_INT_TXDR) {
1601 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 1602 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 1603 dw_mci_write_data_pio(host);
1604 }
1605
1606 if (pending & SDMMC_INT_CMD_DONE) {
1607 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
1608 dw_mci_cmd_interrupt(host, status);
1609 }
1610
1611 if (pending & SDMMC_INT_CD) {
1612 mci_writel(host, RINTSTS, SDMMC_INT_CD);
1791b13e 1613 queue_work(dw_mci_card_workqueue, &host->card_work);
f95f3850
WN		 1614 }
1615
1a5c8e1f
SH		 1616 /* Handle SDIO Interrupts */
1617 for (i = 0; i < host->num_slots; i++) {
1618 struct dw_mci_slot *slot = host->slot[i];
1619 if (pending & SDMMC_INT_SDIO(i)) {
1620 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1621 mmc_signal_sdio_irq(slot->mmc);
1622 }
1623 }
1624
f95f3850
WN		 1625 } while (pass_count++ < 5);
1626
1627#ifdef CONFIG_MMC_DW_IDMAC
1628 /* Handle DMA interrupts */
1629 pending = mci_readl(host, IDSTS);
1630 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1631 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1632 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
1633 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1634 host->dma_ops->complete(host);
1635 }
1636#endif
1637
1638 return IRQ_HANDLED;
1639}
1640
1791b13e 1641static void dw_mci_work_routine_card(struct work_struct *work)
f95f3850 1642{
1791b13e 1643 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
f95f3850
WN		 1644 int i;
1645
1646 for (i = 0; i < host->num_slots; i++) {
1647 struct dw_mci_slot *slot = host->slot[i];
1648 struct mmc_host *mmc = slot->mmc;
1649 struct mmc_request *mrq;
1650 int present;
1651 u32 ctrl;
1652
1653 present = dw_mci_get_cd(mmc);
1654 while (present != slot->last_detect_state) {
f95f3850
WN		 1655 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1656 present ? "inserted" : "removed");
1657
1791b13e
JH		 1658 /* Power up slot (before spin_lock, may sleep) */
1659 if (present != 0 && host->pdata->setpower)
1660 host->pdata->setpower(slot->id, mmc->ocr_avail);
1661
1662 spin_lock_bh(&host->lock);
1663
f95f3850
WN		 1664 /* Card change detected */
1665 slot->last_detect_state = present;
1666
1791b13e
JH		 1667 /* Mark card as present if applicable */
1668 if (present != 0)
f95f3850 1669 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850
WN		 1670
1671 /* Clean up queue if present */
1672 mrq = slot->mrq;
1673 if (mrq) {
1674 if (mrq == host->mrq) {
1675 host->data = NULL;
1676 host->cmd = NULL;
1677
1678 switch (host->state) {
1679 case STATE_IDLE:
1680 break;
1681 case STATE_SENDING_CMD:
1682 mrq->cmd->error = -ENOMEDIUM;
1683 if (!mrq->data)
1684 break;
1685 /* fall through */
1686 case STATE_SENDING_DATA:
1687 mrq->data->error = -ENOMEDIUM;
1688 dw_mci_stop_dma(host);
1689 break;
1690 case STATE_DATA_BUSY:
1691 case STATE_DATA_ERROR:
1692 if (mrq->data->error == -EINPROGRESS)
1693 mrq->data->error = -ENOMEDIUM;
1694 if (!mrq->stop)
1695 break;
1696 /* fall through */
1697 case STATE_SENDING_STOP:
1698 mrq->stop->error = -ENOMEDIUM;
1699 break;
1700 }
1701
1702 dw_mci_request_end(host, mrq);
1703 } else {
1704 list_del(&slot->queue_node);
1705 mrq->cmd->error = -ENOMEDIUM;
1706 if (mrq->data)
1707 mrq->data->error = -ENOMEDIUM;
1708 if (mrq->stop)
1709 mrq->stop->error = -ENOMEDIUM;
1710
1711 spin_unlock(&host->lock);
1712 mmc_request_done(slot->mmc, mrq);
1713 spin_lock(&host->lock);
1714 }
1715 }
1716
1717 /* Power down slot */
1718 if (present == 0) {
f95f3850
WN		 1719 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1720
1721 /*
1722 * Clear down the FIFO - doing so generates a
1723 * block interrupt, hence setting the
1724 * scatter-gather pointer to NULL.
1725 */
f9c2a0dc 1726 sg_miter_stop(&host->sg_miter);
f95f3850
WN		 1727 host->sg = NULL;
1728
1729 ctrl = mci_readl(host, CTRL);
1730 ctrl |= SDMMC_CTRL_FIFO_RESET;
1731 mci_writel(host, CTRL, ctrl);
1732
1733#ifdef CONFIG_MMC_DW_IDMAC
1734 ctrl = mci_readl(host, BMOD);
1735 ctrl |= 0x01; /* Software reset of DMA */
1736 mci_writel(host, BMOD, ctrl);
1737#endif
1738
1739 }
1740
1791b13e
JH		 1741 spin_unlock_bh(&host->lock);
1742
1743 /* Power down slot (after spin_unlock, may sleep) */
1744 if (present == 0 && host->pdata->setpower)
1745 host->pdata->setpower(slot->id, 0);
1746
f95f3850
WN		 1747 present = dw_mci_get_cd(mmc);
1748 }
1749
1750 mmc_detect_change(slot->mmc,
1751 msecs_to_jiffies(host->pdata->detect_delay_ms));
1752 }
1753}
1754
1755static int __init dw_mci_init_slot(struct dw_mci *host, unsigned int id)
1756{
1757 struct mmc_host *mmc;
1758 struct dw_mci_slot *slot;
1759
62ca8034 1760 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), &host->dev);
f95f3850
WN		 1761 if (!mmc)
1762 return -ENOMEM;
1763
1764 slot = mmc_priv(mmc);
1765 slot->id = id;
1766 slot->mmc = mmc;
1767 slot->host = host;
1768
1769 mmc->ops = &dw_mci_ops;
1770 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1771 mmc->f_max = host->bus_hz;
1772
1773 if (host->pdata->get_ocr)
1774 mmc->ocr_avail = host->pdata->get_ocr(id);
1775 else
1776 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1777
1778 /*
1779 * Start with slot power disabled, it will be enabled when a card
1780 * is detected.
1781 */
1782 if (host->pdata->setpower)
1783 host->pdata->setpower(id, 0);
1784
fc3d7720
JC		 1785 if (host->pdata->caps)
1786 mmc->caps = host->pdata->caps;
fc3d7720 1787
4f408cc6
SJ		 1788 if (host->pdata->caps2)
1789 mmc->caps2 = host->pdata->caps2;
4f408cc6 1790
f95f3850
WN		 1791 if (host->pdata->get_bus_wd)
1792 if (host->pdata->get_bus_wd(slot->id) >= 4)
1793 mmc->caps |= MMC_CAP_4_BIT_DATA;
1794
1795 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
6daa7778 1796 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
f95f3850 1797
356ac2cf
JC		 1798 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
1799 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
1800 else
1801 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
1802
f95f3850
WN		 1803 if (host->pdata->blk_settings) {
1804 mmc->max_segs = host->pdata->blk_settings->max_segs;
1805 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1806 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1807 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1808 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1809 } else {
1810 /* Useful defaults if platform data is unset. */
a39e5746
JC		 1811#ifdef CONFIG_MMC_DW_IDMAC
1812 mmc->max_segs = host->ring_size;
1813 mmc->max_blk_size = 65536;
1814 mmc->max_blk_count = host->ring_size;
1815 mmc->max_seg_size = 0x1000;
1816 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1817#else
f95f3850
WN		 1818 mmc->max_segs = 64;
1819 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1820 mmc->max_blk_count = 512;
1821 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1822 mmc->max_seg_size = mmc->max_req_size;
f95f3850 1823#endif /* CONFIG_MMC_DW_IDMAC */
a39e5746 1824 }
f95f3850 1825
c07946a3
JC		 1826 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1827 if (IS_ERR(host->vmmc)) {
a3c76eb9 1828 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
c07946a3
JC		 1829 host->vmmc = NULL;
1830 } else
1831 regulator_enable(host->vmmc);
1832
f95f3850
WN		 1833 if (dw_mci_get_cd(mmc))
1834 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1835 else
1836 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1837
1838 host->slot[id] = slot;
1839 mmc_add_host(mmc);
1840
1841#if defined(CONFIG_DEBUG_FS)
1842 dw_mci_init_debugfs(slot);
1843#endif
1844
1845 /* Card initially undetected */
1846 slot->last_detect_state = 0;
1847
dd6c4b98
WN		 1848 /*
1849 * Card may have been plugged in prior to boot so we
1850 * need to run the detect tasklet
1851 */
1791b13e 1852 queue_work(dw_mci_card_workqueue, &host->card_work);
dd6c4b98 1853
f95f3850
WN		 1854 return 0;
1855}
1856
1857static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1858{
1859 /* Shutdown detect IRQ */
1860 if (slot->host->pdata->exit)
1861 slot->host->pdata->exit(id);
1862
1863 /* Debugfs stuff is cleaned up by mmc core */
1864 mmc_remove_host(slot->mmc);
1865 slot->host->slot[id] = NULL;
1866 mmc_free_host(slot->mmc);
1867}
1868
1869static void dw_mci_init_dma(struct dw_mci *host)
1870{
1871 /* Alloc memory for sg translation */
62ca8034 1872 host->sg_cpu = dma_alloc_coherent(&host->dev, PAGE_SIZE,
f95f3850
WN		 1873 &host->sg_dma, GFP_KERNEL);
1874 if (!host->sg_cpu) {
62ca8034 1875 dev_err(&host->dev, "%s: could not alloc DMA memory\n",
f95f3850
WN		 1876 __func__);
1877 goto no_dma;
1878 }
1879
1880 /* Determine which DMA interface to use */
1881#ifdef CONFIG_MMC_DW_IDMAC
1882 host->dma_ops = &dw_mci_idmac_ops;
62ca8034 1883 dev_info(&host->dev, "Using internal DMA controller.\n");
f95f3850
WN		 1884#endif
1885
1886 if (!host->dma_ops)
1887 goto no_dma;
1888
1889 if (host->dma_ops->init) {
1890 if (host->dma_ops->init(host)) {
62ca8034 1891 dev_err(&host->dev, "%s: Unable to initialize "
f95f3850
WN		 1892 "DMA Controller.\n", __func__);
1893 goto no_dma;
1894 }
1895 } else {
62ca8034 1896 dev_err(&host->dev, "DMA initialization not found.\n");
f95f3850
WN		 1897 goto no_dma;
1898 }
1899
1900 host->use_dma = 1;
1901 return;
1902
1903no_dma:
62ca8034 1904 dev_info(&host->dev, "Using PIO mode.\n");
f95f3850
WN		 1905 host->use_dma = 0;
1906 return;
1907}
1908
1909static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1910{
1911 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1912 unsigned int ctrl;
1913
1914 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1915 SDMMC_CTRL_DMA_RESET));
1916
1917 /* wait till resets clear */
1918 do {
1919 ctrl = mci_readl(host, CTRL);
1920 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1921 SDMMC_CTRL_DMA_RESET)))
1922 return true;
1923 } while (time_before(jiffies, timeout));
1924
1925 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1926
1927 return false;
1928}
1929
62ca8034 1930int dw_mci_probe(struct dw_mci *host)
f95f3850 1931{
62ca8034 1932 int width, i, ret = 0;
f95f3850
WN		 1933 u32 fifo_size;
1934
62ca8034
SH		 1935 if (!host->pdata || !host->pdata->init) {
1936 dev_err(&host->dev,
f95f3850 1937 "Platform data must supply init function\n");
62ca8034 1938 return -ENODEV;
f95f3850
WN		 1939 }
1940
62ca8034
SH		 1941 if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
1942 dev_err(&host->dev,
f95f3850 1943 "Platform data must supply select_slot function\n");
62ca8034 1944 return -ENODEV;
f95f3850
WN		 1945 }
1946
62ca8034
SH		 1947 if (!host->pdata->bus_hz) {
1948 dev_err(&host->dev,
f95f3850 1949 "Platform data must supply bus speed\n");
62ca8034 1950 return -ENODEV;
f95f3850
WN		 1951 }
1952
62ca8034
SH		 1953 host->bus_hz = host->pdata->bus_hz;
1954 host->quirks = host->pdata->quirks;
f95f3850
WN		 1955
1956 spin_lock_init(&host->lock);
1957 INIT_LIST_HEAD(&host->queue);
1958
f95f3850 1959
62ca8034 1960 host->dma_ops = host->pdata->dma_ops;
f95f3850
WN		 1961 dw_mci_init_dma(host);
1962
1963 /*
1964 * Get the host data width - this assumes that HCON has been set with
1965 * the correct values.
1966 */
1967 i = (mci_readl(host, HCON) >> 7) & 0x7;
1968 if (!i) {
1969 host->push_data = dw_mci_push_data16;
1970 host->pull_data = dw_mci_pull_data16;
1971 width = 16;
1972 host->data_shift = 1;
1973 } else if (i == 2) {
1974 host->push_data = dw_mci_push_data64;
1975 host->pull_data = dw_mci_pull_data64;
1976 width = 64;
1977 host->data_shift = 3;
1978 } else {
1979 /* Check for a reserved value, and warn if it is */
1980 WARN((i != 1),
1981 "HCON reports a reserved host data width!\n"
1982 "Defaulting to 32-bit access.\n");
1983 host->push_data = dw_mci_push_data32;
1984 host->pull_data = dw_mci_pull_data32;
1985 width = 32;
1986 host->data_shift = 2;
1987 }
1988
1989 /* Reset all blocks */
62ca8034 1990 if (!mci_wait_reset(&host->dev, host)) {
f95f3850
WN		 1991 ret = -ENODEV;
1992 goto err_dmaunmap;
1993 }
1994
1995 /* Clear the interrupts for the host controller */
1996 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1997 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
1998
1999 /* Put in max timeout */
2000 mci_writel(host, TMOUT, 0xFFFFFFFF);
2001
2002 /*
2003 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2004 * Tx Mark = fifo_size / 2 DMA Size = 8
2005 */
b86d8253
JH		 2006 if (!host->pdata->fifo_depth) {
2007 /*
2008 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2009 * have been overwritten by the bootloader, just like we're
2010 * about to do, so if you know the value for your hardware, you
2011 * should put it in the platform data.
2012 */
2013 fifo_size = mci_readl(host, FIFOTH);
8234e869 2014 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 2015 } else {
2016 fifo_size = host->pdata->fifo_depth;
2017 }
2018 host->fifo_depth = fifo_size;
e61cf118
JC		 2019 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2020 ((fifo_size/2) << 0));
2021 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 2022
2023 /* disable clock to CIU */
2024 mci_writel(host, CLKENA, 0);
2025 mci_writel(host, CLKSRC, 0);
2026
2027 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
1791b13e
JH		 2028 dw_mci_card_workqueue = alloc_workqueue("dw-mci-card",
2029 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
2030 if (!dw_mci_card_workqueue)
2031 goto err_dmaunmap;
2032 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
62ca8034 2033 ret = request_irq(host->irq, dw_mci_interrupt, host->irq_flags, "dw-mci", host);
f95f3850 2034 if (ret)
1791b13e 2035 goto err_workqueue;
f95f3850 2036
f95f3850
WN		 2037 if (host->pdata->num_slots)
2038 host->num_slots = host->pdata->num_slots;
2039 else
2040 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2041
2042 /* We need at least one slot to succeed */
2043 for (i = 0; i < host->num_slots; i++) {
2044 ret = dw_mci_init_slot(host, i);
2045 if (ret) {
2046 ret = -ENODEV;
2047 goto err_init_slot;
2048 }
2049 }
2050
4e0a5adf
JC		 2051 /*
2052 * In 2.40a spec, Data offset is changed.
2053 * Need to check the version-id and set data-offset for DATA register.
2054 */
2055 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
62ca8034 2056 dev_info(&host->dev, "Version ID is %04x\n", host->verid);
4e0a5adf
JC		 2057
2058 if (host->verid < DW_MMC_240A)
2059 host->data_offset = DATA_OFFSET;
2060 else
2061 host->data_offset = DATA_240A_OFFSET;
2062
f95f3850
WN		 2063 /*
2064 * Enable interrupts for command done, data over, data empty, card det,
2065 * receive ready and error such as transmit, receive timeout, crc error
2066 */
2067 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2068 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2069 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2070 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2071 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2072
62ca8034 2073 dev_info(&host->dev, "DW MMC controller at irq %d, "
b86d8253
JH		 2074 "%d bit host data width, "
2075 "%u deep fifo\n",
62ca8034 2076 host->irq, width, fifo_size);
f95f3850 2077 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
62ca8034 2078 dev_info(&host->dev, "Internal DMAC interrupt fix enabled.\n");
f95f3850
WN		 2079
2080 return 0;
2081
2082err_init_slot:
2083 /* De-init any initialized slots */
2084 while (i > 0) {
2085 if (host->slot[i])
2086 dw_mci_cleanup_slot(host->slot[i], i);
2087 i--;
2088 }
62ca8034 2089 free_irq(host->irq, host);
f95f3850 2090
1791b13e
JH		 2091err_workqueue:
2092 destroy_workqueue(dw_mci_card_workqueue);
2093
f95f3850
WN		 2094err_dmaunmap:
2095 if (host->use_dma && host->dma_ops->exit)
2096 host->dma_ops->exit(host);
62ca8034 2097 dma_free_coherent(&host->dev, PAGE_SIZE,
f95f3850 2098 host->sg_cpu, host->sg_dma);
f95f3850 2099
c07946a3
JC		 2100 if (host->vmmc) {
2101 regulator_disable(host->vmmc);
2102 regulator_put(host->vmmc);
2103 }
f95f3850
WN		 2104 return ret;
2105}
62ca8034 2106EXPORT_SYMBOL(dw_mci_probe);
f95f3850 2107
62ca8034 2108void dw_mci_remove(struct dw_mci *host)
f95f3850 2109{
f95f3850
WN		 2110 int i;
2111
2112 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2113 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2114
f95f3850 2115 for (i = 0; i < host->num_slots; i++) {
62ca8034 2116 dev_dbg(&host->dev, "remove slot %d\n", i);
f95f3850
WN		 2117 if (host->slot[i])
2118 dw_mci_cleanup_slot(host->slot[i], i);
2119 }
2120
2121 /* disable clock to CIU */
2122 mci_writel(host, CLKENA, 0);
2123 mci_writel(host, CLKSRC, 0);
2124
62ca8034 2125 free_irq(host->irq, host);
1791b13e 2126 destroy_workqueue(dw_mci_card_workqueue);
62ca8034 2127 dma_free_coherent(&host->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
f95f3850
WN		 2128
2129 if (host->use_dma && host->dma_ops->exit)
2130 host->dma_ops->exit(host);
2131
c07946a3
JC		 2132 if (host->vmmc) {
2133 regulator_disable(host->vmmc);
2134 regulator_put(host->vmmc);
2135 }
2136
f95f3850 2137}
62ca8034
SH		 2138EXPORT_SYMBOL(dw_mci_remove);
2139
2140
f95f3850 2141
6fe8890d 2142#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 2143/*
2144 * TODO: we should probably disable the clock to the card in the suspend path.
2145 */
62ca8034 2146int dw_mci_suspend(struct dw_mci *host)
f95f3850 2147{
62ca8034 2148 int i, ret = 0;
f95f3850
WN		 2149
2150 for (i = 0; i < host->num_slots; i++) {
2151 struct dw_mci_slot *slot = host->slot[i];
2152 if (!slot)
2153 continue;
2154 ret = mmc_suspend_host(slot->mmc);
2155 if (ret < 0) {
2156 while (--i >= 0) {
2157 slot = host->slot[i];
2158 if (slot)
2159 mmc_resume_host(host->slot[i]->mmc);
2160 }
2161 return ret;
2162 }
2163 }
2164
c07946a3
JC		 2165 if (host->vmmc)
2166 regulator_disable(host->vmmc);
2167
f95f3850
WN		 2168 return 0;
2169}
62ca8034 2170EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 2171
62ca8034 2172int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 2173{
2174 int i, ret;
f95f3850 2175
1d6c4e0a
JC		 2176 if (host->vmmc)
2177 regulator_enable(host->vmmc);
2178
e61cf118
JC		 2179 if (host->dma_ops->init)
2180 host->dma_ops->init(host);
2181
62ca8034 2182 if (!mci_wait_reset(&host->dev, host)) {
e61cf118
JC		 2183 ret = -ENODEV;
2184 return ret;
2185 }
2186
2187 /* Restore the old value at FIFOTH register */
2188 mci_writel(host, FIFOTH, host->fifoth_val);
2189
2190 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2191 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2192 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2193 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2194 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2195
f95f3850
WN		 2196 for (i = 0; i < host->num_slots; i++) {
2197 struct dw_mci_slot *slot = host->slot[i];
2198 if (!slot)
2199 continue;
2200 ret = mmc_resume_host(host->slot[i]->mmc);
2201 if (ret < 0)
2202 return ret;
2203 }
f95f3850
WN		 2204 return 0;
2205}
62ca8034 2206EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 2207#endif /* CONFIG_PM_SLEEP */
2208
f95f3850
WN		 2209static int __init dw_mci_init(void)
2210{
62ca8034
SH		 2211 printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2212 return 0;
f95f3850
WN		 2213}
2214
2215static void __exit dw_mci_exit(void)
2216{
f95f3850
WN		 2217}
2218
2219module_init(dw_mci_init);
2220module_exit(dw_mci_exit);
2221
2222MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2223MODULE_AUTHOR("NXP Semiconductor VietNam");
2224MODULE_AUTHOR("Imagination Technologies Ltd");
2225MODULE_LICENSE("GPL v2");
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