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mmc: dw_mmc: Fix occasional hang after tuning on eMMC
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
b6d2d81c 22#include <linux/iopoll.h>
f95f3850
WN		 23#include <linux/ioport.h>
24#include <linux/module.h>
25#include <linux/platform_device.h>
a6db2c86 26#include <linux/pm_runtime.h>
f95f3850
WN		 27#include <linux/seq_file.h>
28#include <linux/slab.h>
29#include <linux/stat.h>
30#include <linux/delay.h>
31#include <linux/irq.h>
b24c8b26 32#include <linux/mmc/card.h>
f95f3850
WN		 33#include <linux/mmc/host.h>
34#include <linux/mmc/mmc.h>
01730558 35#include <linux/mmc/sd.h>
90c2143a 36#include <linux/mmc/sdio.h>
f95f3850 37#include <linux/bitops.h>
c07946a3 38#include <linux/regulator/consumer.h>
c91eab4b 39#include <linux/of.h>
55a6ceb2 40#include <linux/of_gpio.h>
bf626e55 41#include <linux/mmc/slot-gpio.h>
f95f3850
WN		 42
43#include "dw_mmc.h"
44
45/* Common flag combinations */
3f7eec62 46#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
f95f3850 47 SDMMC_INT_HTO | SDMMC_INT_SBE | \
7a3c5677 48 SDMMC_INT_EBE | SDMMC_INT_HLE)
f95f3850 49#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
7a3c5677 50 SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
f95f3850 51#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
7a3c5677 52 DW_MCI_CMD_ERROR_FLAGS)
f95f3850
WN		 53#define DW_MCI_SEND_STATUS 1
54#define DW_MCI_RECV_STATUS 2
55#define DW_MCI_DMA_THRESHOLD 16
56
1f44a2a5 57#define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
72e83577 58#define DW_MCI_FREQ_MIN 100000 /* unit: HZ */
1f44a2a5 59
fc79a4d6
JS		 60#define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
61 SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
62 SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
63 SDMMC_IDMAC_INT_TI)
64
cc190d4c
SL		 65#define DESC_RING_BUF_SZ PAGE_SIZE
66
69d99fdc
PT		 67struct idmac_desc_64addr {
68 u32 des0; /* Control Descriptor */
b6d2d81c
SL		 69#define IDMAC_OWN_CLR64(x) \
70 !((x) & cpu_to_le32(IDMAC_DES0_OWN))
69d99fdc
PT		 71
72 u32 des1; /* Reserved */
73
74 u32 des2; /*Buffer sizes */
75#define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
6687c42f
BD		 76 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
77 ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
69d99fdc
PT		 78
79 u32 des3; /* Reserved */
80
81 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
82 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
83
84 u32 des6; /* Lower 32-bits of Next Descriptor Address */
85 u32 des7; /* Upper 32-bits of Next Descriptor Address */
86};
87
f95f3850 88struct idmac_desc {
6687c42f 89 __le32 des0; /* Control Descriptor */
f95f3850
WN		 90#define IDMAC_DES0_DIC BIT(1)
91#define IDMAC_DES0_LD BIT(2)
92#define IDMAC_DES0_FD BIT(3)
93#define IDMAC_DES0_CH BIT(4)
94#define IDMAC_DES0_ER BIT(5)
95#define IDMAC_DES0_CES BIT(30)
96#define IDMAC_DES0_OWN BIT(31)
97
6687c42f 98 __le32 des1; /* Buffer sizes */
f95f3850 99#define IDMAC_SET_BUFFER1_SIZE(d, s) \
e5306c3a 100 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
f95f3850 101
6687c42f 102 __le32 des2; /* buffer 1 physical address */
f95f3850 103
6687c42f 104 __le32 des3; /* buffer 2 physical address */
f95f3850 105};
5959b32e
AB		 106
107/* Each descriptor can transfer up to 4KB of data in chained mode */
108#define DW_MCI_DESC_DATA_LENGTH 0x1000
f95f3850 109
f95f3850
WN		 110#if defined(CONFIG_DEBUG_FS)
111static int dw_mci_req_show(struct seq_file *s, void *v)
112{
113 struct dw_mci_slot *slot = s->private;
114 struct mmc_request *mrq;
115 struct mmc_command *cmd;
116 struct mmc_command *stop;
117 struct mmc_data *data;
118
119 /* Make sure we get a consistent snapshot */
120 spin_lock_bh(&slot->host->lock);
121 mrq = slot->mrq;
122
123 if (mrq) {
124 cmd = mrq->cmd;
125 data = mrq->data;
126 stop = mrq->stop;
127
128 if (cmd)
129 seq_printf(s,
130 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
131 cmd->opcode, cmd->arg, cmd->flags,
132 cmd->resp[0], cmd->resp[1], cmd->resp[2],
133 cmd->resp[2], cmd->error);
134 if (data)
135 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
136 data->bytes_xfered, data->blocks,
137 data->blksz, data->flags, data->error);
138 if (stop)
139 seq_printf(s,
140 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
141 stop->opcode, stop->arg, stop->flags,
142 stop->resp[0], stop->resp[1], stop->resp[2],
143 stop->resp[2], stop->error);
144 }
145
146 spin_unlock_bh(&slot->host->lock);
147
148 return 0;
149}
150
151static int dw_mci_req_open(struct inode *inode, struct file *file)
152{
153 return single_open(file, dw_mci_req_show, inode->i_private);
154}
155
156static const struct file_operations dw_mci_req_fops = {
157 .owner = THIS_MODULE,
158 .open = dw_mci_req_open,
159 .read = seq_read,
160 .llseek = seq_lseek,
161 .release = single_release,
162};
163
164static int dw_mci_regs_show(struct seq_file *s, void *v)
165{
21657ebd
JC		 166 struct dw_mci *host = s->private;
167
e56b4c64
SL		 168 pm_runtime_get_sync(host->dev);
169
21657ebd
JC		 170 seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
171 seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
172 seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
173 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
174 seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
175 seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
f95f3850 176
e56b4c64
SL		 177 pm_runtime_put_autosuspend(host->dev);
178
f95f3850
WN		 179 return 0;
180}
181
182static int dw_mci_regs_open(struct inode *inode, struct file *file)
183{
184 return single_open(file, dw_mci_regs_show, inode->i_private);
185}
186
187static const struct file_operations dw_mci_regs_fops = {
188 .owner = THIS_MODULE,
189 .open = dw_mci_regs_open,
190 .read = seq_read,
191 .llseek = seq_lseek,
192 .release = single_release,
193};
194
195static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
196{
197 struct mmc_host *mmc = slot->mmc;
198 struct dw_mci *host = slot->host;
199 struct dentry *root;
200 struct dentry *node;
201
202 root = mmc->debugfs_root;
203 if (!root)
204 return;
205
206 node = debugfs_create_file("regs", S_IRUSR, root, host,
207 &dw_mci_regs_fops);
208 if (!node)
209 goto err;
210
211 node = debugfs_create_file("req", S_IRUSR, root, slot,
212 &dw_mci_req_fops);
213 if (!node)
214 goto err;
215
216 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
217 if (!node)
218 goto err;
219
220 node = debugfs_create_x32("pending_events", S_IRUSR, root,
221 (u32 *)&host->pending_events);
222 if (!node)
223 goto err;
224
225 node = debugfs_create_x32("completed_events", S_IRUSR, root,
226 (u32 *)&host->completed_events);
227 if (!node)
228 goto err;
229
230 return;
231
232err:
233 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
234}
235#endif /* defined(CONFIG_DEBUG_FS) */
236
8e6db1f6
SL		 237static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
238{
239 u32 ctrl;
240
241 ctrl = mci_readl(host, CTRL);
242 ctrl |= reset;
243 mci_writel(host, CTRL, ctrl);
244
245 /* wait till resets clear */
246 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
247 !(ctrl & reset),
248 1, 500 * USEC_PER_MSEC)) {
249 dev_err(host->dev,
250 "Timeout resetting block (ctrl reset %#x)\n",
251 ctrl & reset);
252 return false;
253 }
254
255 return true;
256}
01730558 257
4dba18de
SL		 258static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
259{
260 u32 status;
261
262 /*
263 * Databook says that before issuing a new data transfer command
264 * we need to check to see if the card is busy. Data transfer commands
265 * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
266 *
267 * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
268 * expected.
269 */
270 if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
271 !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
272 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
273 status,
274 !(status & SDMMC_STATUS_BUSY),
275 10, 500 * USEC_PER_MSEC))
276 dev_err(host->dev, "Busy; trying anyway\n");
277 }
278}
279
280static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
281{
282 struct dw_mci *host = slot->host;
283 unsigned int cmd_status = 0;
284
285 mci_writel(host, CMDARG, arg);
286 wmb(); /* drain writebuffer */
287 dw_mci_wait_while_busy(host, cmd);
288 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
289
290 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
291 !(cmd_status & SDMMC_CMD_START),
292 1, 500 * USEC_PER_MSEC))
293 dev_err(&slot->mmc->class_dev,
294 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
295 cmd, arg, cmd_status);
296}
297
f95f3850
WN		 298static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
299{
800d78bf 300 struct dw_mci_slot *slot = mmc_priv(mmc);
01730558 301 struct dw_mci *host = slot->host;
f95f3850 302 u32 cmdr;
f95f3850 303
0e3a22c0 304 cmd->error = -EINPROGRESS;
f95f3850
WN		 305 cmdr = cmd->opcode;
306
90c2143a
SJ		 307 if (cmd->opcode == MMC_STOP_TRANSMISSION ||
308 cmd->opcode == MMC_GO_IDLE_STATE ||
309 cmd->opcode == MMC_GO_INACTIVE_STATE ||
310 (cmd->opcode == SD_IO_RW_DIRECT &&
311 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
f95f3850 312 cmdr |= SDMMC_CMD_STOP;
4a1b27ad
JC		 313 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
314 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
f95f3850 315
01730558
DA		 316 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
317 u32 clk_en_a;
318
319 /* Special bit makes CMD11 not die */
320 cmdr |= SDMMC_CMD_VOLT_SWITCH;
321
322 /* Change state to continue to handle CMD11 weirdness */
323 WARN_ON(slot->host->state != STATE_SENDING_CMD);
324 slot->host->state = STATE_SENDING_CMD11;
325
326 /*
327 * We need to disable low power mode (automatic clock stop)
328 * while doing voltage switch so we don't confuse the card,
329 * since stopping the clock is a specific part of the UHS
330 * voltage change dance.
331 *
332 * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
333 * unconditionally turned back on in dw_mci_setup_bus() if it's
334 * ever called with a non-zero clock. That shouldn't happen
335 * until the voltage change is all done.
336 */
337 clk_en_a = mci_readl(host, CLKENA);
338 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
339 mci_writel(host, CLKENA, clk_en_a);
340 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
341 SDMMC_CMD_PRV_DAT_WAIT, 0);
342 }
343
f95f3850
WN		 344 if (cmd->flags & MMC_RSP_PRESENT) {
345 /* We expect a response, so set this bit */
346 cmdr |= SDMMC_CMD_RESP_EXP;
347 if (cmd->flags & MMC_RSP_136)
348 cmdr |= SDMMC_CMD_RESP_LONG;
349 }
350
351 if (cmd->flags & MMC_RSP_CRC)
352 cmdr |= SDMMC_CMD_RESP_CRC;
353
0349c085 354 if (cmd->data) {
f95f3850 355 cmdr |= SDMMC_CMD_DAT_EXP;
0349c085 356 if (cmd->data->flags & MMC_DATA_WRITE)
f95f3850
WN		 357 cmdr |= SDMMC_CMD_DAT_WR;
358 }
359
aaaaeb7a
JC		 360 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
361 cmdr |= SDMMC_CMD_USE_HOLD_REG;
800d78bf 362
f95f3850
WN		 363 return cmdr;
364}
365
90c2143a
SJ		 366static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
367{
368 struct mmc_command *stop;
369 u32 cmdr;
370
371 if (!cmd->data)
372 return 0;
373
374 stop = &host->stop_abort;
375 cmdr = cmd->opcode;
376 memset(stop, 0, sizeof(struct mmc_command));
377
378 if (cmdr == MMC_READ_SINGLE_BLOCK ||
379 cmdr == MMC_READ_MULTIPLE_BLOCK ||
380 cmdr == MMC_WRITE_BLOCK ||
6c2c6506
UH		 381 cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
382 cmdr == MMC_SEND_TUNING_BLOCK ||
383 cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
90c2143a
SJ		 384 stop->opcode = MMC_STOP_TRANSMISSION;
385 stop->arg = 0;
386 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
387 } else if (cmdr == SD_IO_RW_EXTENDED) {
388 stop->opcode = SD_IO_RW_DIRECT;
389 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
390 ((cmd->arg >> 28) & 0x7);
391 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
392 } else {
393 return 0;
394 }
395
396 cmdr = stop->opcode | SDMMC_CMD_STOP |
397 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
398
42f989c0 399 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
8c005b40
JC		 400 cmdr |= SDMMC_CMD_USE_HOLD_REG;
401
90c2143a
SJ		 402 return cmdr;
403}
404
03de1921
AK		 405static inline void dw_mci_set_cto(struct dw_mci *host)
406{
407 unsigned int cto_clks;
4c2357f5 408 unsigned int cto_div;
03de1921 409 unsigned int cto_ms;
8892b705 410 unsigned long irqflags;
03de1921
AK		 411
412 cto_clks = mci_readl(host, TMOUT) & 0xff;
4c2357f5
DA		 413 cto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
414 if (cto_div == 0)
415 cto_div = 1;
7ff1c704
ED		 416
417 cto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * cto_clks * cto_div,
418 host->bus_hz);
03de1921
AK		 419
420 /* add a bit spare time */
421 cto_ms += 10;
422
8892b705
DA		 423 /*
424 * The durations we're working with are fairly short so we have to be
425 * extra careful about synchronization here. Specifically in hardware a
426 * command timeout is _at most_ 5.1 ms, so that means we expect an
427 * interrupt (either command done or timeout) to come rather quickly
428 * after the mci_writel. ...but just in case we have a long interrupt
429 * latency let's add a bit of paranoia.
430 *
431 * In general we'll assume that at least an interrupt will be asserted
432 * in hardware by the time the cto_timer runs. ...and if it hasn't
433 * been asserted in hardware by that time then we'll assume it'll never
434 * come.
435 */
436 spin_lock_irqsave(&host->irq_lock, irqflags);
437 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
438 mod_timer(&host->cto_timer,
439 jiffies + msecs_to_jiffies(cto_ms) + 1);
440 spin_unlock_irqrestore(&host->irq_lock, irqflags);
03de1921
AK		 441}
442
f95f3850
WN		 443static void dw_mci_start_command(struct dw_mci *host,
444 struct mmc_command *cmd, u32 cmd_flags)
445{
446 host->cmd = cmd;
4a90920c 447 dev_vdbg(host->dev,
f95f3850
WN		 448 "start command: ARGR=0x%08x CMDR=0x%08x\n",
449 cmd->arg, cmd_flags);
450
451 mci_writel(host, CMDARG, cmd->arg);
0e3a22c0 452 wmb(); /* drain writebuffer */
0bdbd0e8 453 dw_mci_wait_while_busy(host, cmd_flags);
f95f3850 454
8892b705
DA		 455 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
456
03de1921
AK		 457 /* response expected command only */
458 if (cmd_flags & SDMMC_CMD_RESP_EXP)
459 dw_mci_set_cto(host);
f95f3850
WN		 460}
461
90c2143a 462static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
f95f3850 463{
e13c3c08 464 struct mmc_command *stop = &host->stop_abort;
0e3a22c0 465
90c2143a 466 dw_mci_start_command(host, stop, host->stop_cmdr);
f95f3850
WN		 467}
468
469/* DMA interface functions */
470static void dw_mci_stop_dma(struct dw_mci *host)
471{
03e8cb53 472 if (host->using_dma) {
f95f3850
WN		 473 host->dma_ops->stop(host);
474 host->dma_ops->cleanup(host);
f95f3850 475 }
aa50f259
SJ		 476
477 /* Data transfer was stopped by the interrupt handler */
478 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
f95f3850
WN		 479}
480
f95f3850
WN		 481static void dw_mci_dma_cleanup(struct dw_mci *host)
482{
483 struct mmc_data *data = host->data;
484
a4cc7eb4
JC		 485 if (data && data->host_cookie == COOKIE_MAPPED) {
486 dma_unmap_sg(host->dev,
487 data->sg,
488 data->sg_len,
feeef096 489 mmc_get_dma_dir(data));
a4cc7eb4
JC		 490 data->host_cookie = COOKIE_UNMAPPED;
491 }
f95f3850
WN		 492}
493
5ce9d961
SJ		 494static void dw_mci_idmac_reset(struct dw_mci *host)
495{
496 u32 bmod = mci_readl(host, BMOD);
497 /* Software reset of DMA */
498 bmod |= SDMMC_IDMAC_SWRESET;
499 mci_writel(host, BMOD, bmod);
500}
501
f95f3850
WN		 502static void dw_mci_idmac_stop_dma(struct dw_mci *host)
503{
504 u32 temp;
505
506 /* Disable and reset the IDMAC interface */
507 temp = mci_readl(host, CTRL);
508 temp &= ~SDMMC_CTRL_USE_IDMAC;
509 temp |= SDMMC_CTRL_DMA_RESET;
510 mci_writel(host, CTRL, temp);
511
512 /* Stop the IDMAC running */
513 temp = mci_readl(host, BMOD);
a5289a43 514 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
5ce9d961 515 temp |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 516 mci_writel(host, BMOD, temp);
517}
518
3fc7eaef 519static void dw_mci_dmac_complete_dma(void *arg)
f95f3850 520{
3fc7eaef 521 struct dw_mci *host = arg;
f95f3850
WN		 522 struct mmc_data *data = host->data;
523
4a90920c 524 dev_vdbg(host->dev, "DMA complete\n");
f95f3850 525
3fc7eaef
SL		 526 if ((host->use_dma == TRANS_MODE_EDMAC) &&
527 data && (data->flags & MMC_DATA_READ))
528 /* Invalidate cache after read */
42f989c0 529 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
3fc7eaef
SL		 530 data->sg,
531 data->sg_len,
532 DMA_FROM_DEVICE);
533
f95f3850
WN		 534 host->dma_ops->cleanup(host);
535
536 /*
537 * If the card was removed, data will be NULL. No point in trying to
538 * send the stop command or waiting for NBUSY in this case.
539 */
540 if (data) {
541 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
542 tasklet_schedule(&host->tasklet);
543 }
544}
545
3b2a067b
SL		 546static int dw_mci_idmac_init(struct dw_mci *host)
547{
548 int i;
549
550 if (host->dma_64bit_address == 1) {
551 struct idmac_desc_64addr *p;
552 /* Number of descriptors in the ring buffer */
cc190d4c
SL		 553 host->ring_size =
554 DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
3b2a067b
SL		 555
556 /* Forward link the descriptor list */
557 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
558 i++, p++) {
559 p->des6 = (host->sg_dma +
560 (sizeof(struct idmac_desc_64addr) *
561 (i + 1))) & 0xffffffff;
562
563 p->des7 = (u64)(host->sg_dma +
564 (sizeof(struct idmac_desc_64addr) *
565 (i + 1))) >> 32;
566 /* Initialize reserved and buffer size fields to "0" */
7e1f7619 567 p->des0 = 0;
3b2a067b
SL		 568 p->des1 = 0;
569 p->des2 = 0;
570 p->des3 = 0;
571 }
572
573 /* Set the last descriptor as the end-of-ring descriptor */
574 p->des6 = host->sg_dma & 0xffffffff;
575 p->des7 = (u64)host->sg_dma >> 32;
576 p->des0 = IDMAC_DES0_ER;
577
578 } else {
579 struct idmac_desc *p;
580 /* Number of descriptors in the ring buffer */
cc190d4c
SL		 581 host->ring_size =
582 DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
3b2a067b
SL		 583
584 /* Forward link the descriptor list */
585 for (i = 0, p = host->sg_cpu;
586 i < host->ring_size - 1;
587 i++, p++) {
588 p->des3 = cpu_to_le32(host->sg_dma +
589 (sizeof(struct idmac_desc) * (i + 1)));
7e1f7619 590 p->des0 = 0;
3b2a067b
SL		 591 p->des1 = 0;
592 }
593
594 /* Set the last descriptor as the end-of-ring descriptor */
595 p->des3 = cpu_to_le32(host->sg_dma);
596 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
597 }
598
599 dw_mci_idmac_reset(host);
600
601 if (host->dma_64bit_address == 1) {
602 /* Mask out interrupts - get Tx & Rx complete only */
603 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
604 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
605 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
606
607 /* Set the descriptor base address */
608 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
609 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
610
611 } else {
612 /* Mask out interrupts - get Tx & Rx complete only */
613 mci_writel(host, IDSTS, IDMAC_INT_CLR);
614 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
615 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
616
617 /* Set the descriptor base address */
618 mci_writel(host, DBADDR, host->sg_dma);
619 }
620
621 return 0;
622}
623
624static inline int dw_mci_prepare_desc64(struct dw_mci *host,
ec0baaa6
SL		 625 struct mmc_data *data,
626 unsigned int sg_len)
f95f3850 627{
5959b32e 628 unsigned int desc_len;
ec0baaa6 629 struct idmac_desc_64addr *desc_first, *desc_last, *desc;
b6d2d81c 630 u32 val;
f95f3850 631 int i;
0e3a22c0 632
ec0baaa6 633 desc_first = desc_last = desc = host->sg_cpu;
5959b32e 634
ec0baaa6
SL		 635 for (i = 0; i < sg_len; i++) {
636 unsigned int length = sg_dma_len(&data->sg[i]);
69d99fdc 637
ec0baaa6 638 u64 mem_addr = sg_dma_address(&data->sg[i]);
0e3a22c0 639
ec0baaa6
SL		 640 for ( ; length ; desc++) {
641 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
642 length : DW_MCI_DESC_DATA_LENGTH;
f95f3850 643
ec0baaa6 644 length -= desc_len;
5959b32e 645
3b2a067b
SL		 646 /*
647 * Wait for the former clear OWN bit operation
648 * of IDMAC to make sure that this descriptor
649 * isn't still owned by IDMAC as IDMAC's write
650 * ops and CPU's read ops are asynchronous.
651 */
b6d2d81c
SL		 652 if (readl_poll_timeout_atomic(&desc->des0, val,
653 !(val & IDMAC_DES0_OWN),
654 10, 100 * USEC_PER_MSEC))
655 goto err_own_bit;
3b2a067b 656
ec0baaa6
SL		 657 /*
658 * Set the OWN bit and disable interrupts
659 * for this descriptor
660 */
661 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
662 IDMAC_DES0_CH;
5959b32e 663
ec0baaa6
SL		 664 /* Buffer length */
665 IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
5959b32e 666
ec0baaa6
SL		 667 /* Physical address to DMA to/from */
668 desc->des4 = mem_addr & 0xffffffff;
669 desc->des5 = mem_addr >> 32;
5959b32e 670
ec0baaa6
SL		 671 /* Update physical address for the next desc */
672 mem_addr += desc_len;
5959b32e 673
ec0baaa6
SL		 674 /* Save pointer to the last descriptor */
675 desc_last = desc;
69d99fdc 676 }
ec0baaa6 677 }
f95f3850 678
ec0baaa6
SL		 679 /* Set first descriptor */
680 desc_first->des0 |= IDMAC_DES0_FD;
f95f3850 681
ec0baaa6
SL		 682 /* Set last descriptor */
683 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
684 desc_last->des0 |= IDMAC_DES0_LD;
3b2a067b
SL		 685
686 return 0;
687err_own_bit:
688 /* restore the descriptor chain as it's polluted */
26be9d70 689 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
cc190d4c 690 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
3b2a067b
SL		 691 dw_mci_idmac_init(host);
692 return -EINVAL;
ec0baaa6 693}
5959b32e 694
69d99fdc 695
3b2a067b 696static inline int dw_mci_prepare_desc32(struct dw_mci *host,
ec0baaa6
SL		 697 struct mmc_data *data,
698 unsigned int sg_len)
699{
700 unsigned int desc_len;
701 struct idmac_desc *desc_first, *desc_last, *desc;
b6d2d81c 702 u32 val;
ec0baaa6 703 int i;
0e3a22c0 704
ec0baaa6 705 desc_first = desc_last = desc = host->sg_cpu;
69d99fdc 706
ec0baaa6
SL		 707 for (i = 0; i < sg_len; i++) {
708 unsigned int length = sg_dma_len(&data->sg[i]);
5959b32e 709
ec0baaa6 710 u32 mem_addr = sg_dma_address(&data->sg[i]);
5959b32e 711
ec0baaa6
SL		 712 for ( ; length ; desc++) {
713 desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
714 length : DW_MCI_DESC_DATA_LENGTH;
5959b32e 715
ec0baaa6 716 length -= desc_len;
f95f3850 717
3b2a067b
SL		 718 /*
719 * Wait for the former clear OWN bit operation
720 * of IDMAC to make sure that this descriptor
721 * isn't still owned by IDMAC as IDMAC's write
722 * ops and CPU's read ops are asynchronous.
723 */
b6d2d81c
SL		 724 if (readl_poll_timeout_atomic(&desc->des0, val,
725 IDMAC_OWN_CLR64(val),
726 10,
727 100 * USEC_PER_MSEC))
728 goto err_own_bit;
3b2a067b 729
ec0baaa6
SL		 730 /*
731 * Set the OWN bit and disable interrupts
732 * for this descriptor
733 */
734 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
735 IDMAC_DES0_DIC |
736 IDMAC_DES0_CH);
5959b32e 737
ec0baaa6
SL		 738 /* Buffer length */
739 IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
5959b32e 740
ec0baaa6
SL		 741 /* Physical address to DMA to/from */
742 desc->des2 = cpu_to_le32(mem_addr);
69d99fdc 743
ec0baaa6
SL		 744 /* Update physical address for the next desc */
745 mem_addr += desc_len;
f95f3850 746
ec0baaa6
SL		 747 /* Save pointer to the last descriptor */
748 desc_last = desc;
749 }
69d99fdc 750 }
f95f3850 751
ec0baaa6
SL		 752 /* Set first descriptor */
753 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
754
755 /* Set last descriptor */
756 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
757 IDMAC_DES0_DIC));
758 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
3b2a067b
SL		 759
760 return 0;
761err_own_bit:
762 /* restore the descriptor chain as it's polluted */
26be9d70 763 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
cc190d4c 764 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
3b2a067b
SL		 765 dw_mci_idmac_init(host);
766 return -EINVAL;
f95f3850
WN		 767}
768
3fc7eaef 769static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
f95f3850
WN		 770{
771 u32 temp;
3b2a067b 772 int ret;
f95f3850 773
ec0baaa6 774 if (host->dma_64bit_address == 1)
3b2a067b 775 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
ec0baaa6 776 else
3b2a067b
SL		 777 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
778
779 if (ret)
780 goto out;
ec0baaa6
SL		 781
782 /* drain writebuffer */
783 wmb();
f95f3850 784
536f6b91
SR		 785 /* Make sure to reset DMA in case we did PIO before this */
786 dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
787 dw_mci_idmac_reset(host);
788
f95f3850
WN		 789 /* Select IDMAC interface */
790 temp = mci_readl(host, CTRL);
791 temp |= SDMMC_CTRL_USE_IDMAC;
792 mci_writel(host, CTRL, temp);
793
0e3a22c0 794 /* drain writebuffer */
f95f3850
WN		 795 wmb();
796
797 /* Enable the IDMAC */
798 temp = mci_readl(host, BMOD);
a5289a43 799 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 800 mci_writel(host, BMOD, temp);
801
802 /* Start it running */
803 mci_writel(host, PLDMND, 1);
3fc7eaef 804
3b2a067b
SL		 805out:
806 return ret;
f95f3850
WN		 807}
808
8e2b36ea 809static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
885c3e80
SJ		 810 .init = dw_mci_idmac_init,
811 .start = dw_mci_idmac_start_dma,
812 .stop = dw_mci_idmac_stop_dma,
3fc7eaef
SL		 813 .complete = dw_mci_dmac_complete_dma,
814 .cleanup = dw_mci_dma_cleanup,
815};
816
817static void dw_mci_edmac_stop_dma(struct dw_mci *host)
818{
ab925a31 819 dmaengine_terminate_async(host->dms->ch);
3fc7eaef
SL		 820}
821
822static int dw_mci_edmac_start_dma(struct dw_mci *host,
823 unsigned int sg_len)
824{
825 struct dma_slave_config cfg;
826 struct dma_async_tx_descriptor *desc = NULL;
827 struct scatterlist *sgl = host->data->sg;
27d70d36 828 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
3fc7eaef
SL		 829 u32 sg_elems = host->data->sg_len;
830 u32 fifoth_val;
831 u32 fifo_offset = host->fifo_reg - host->regs;
832 int ret = 0;
833
834 /* Set external dma config: burst size, burst width */
260b3164 835 cfg.dst_addr = host->phy_regs + fifo_offset;
3fc7eaef
SL		 836 cfg.src_addr = cfg.dst_addr;
837 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
838 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
839
840 /* Match burst msize with external dma config */
841 fifoth_val = mci_readl(host, FIFOTH);
842 cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
843 cfg.src_maxburst = cfg.dst_maxburst;
844
845 if (host->data->flags & MMC_DATA_WRITE)
846 cfg.direction = DMA_MEM_TO_DEV;
847 else
848 cfg.direction = DMA_DEV_TO_MEM;
849
850 ret = dmaengine_slave_config(host->dms->ch, &cfg);
851 if (ret) {
852 dev_err(host->dev, "Failed to config edmac.\n");
853 return -EBUSY;
854 }
855
856 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
857 sg_len, cfg.direction,
858 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
859 if (!desc) {
860 dev_err(host->dev, "Can't prepare slave sg.\n");
861 return -EBUSY;
862 }
863
864 /* Set dw_mci_dmac_complete_dma as callback */
865 desc->callback = dw_mci_dmac_complete_dma;
866 desc->callback_param = (void *)host;
867 dmaengine_submit(desc);
868
869 /* Flush cache before write */
870 if (host->data->flags & MMC_DATA_WRITE)
42f989c0 871 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
3fc7eaef
SL		 872 sg_elems, DMA_TO_DEVICE);
873
874 dma_async_issue_pending(host->dms->ch);
875
876 return 0;
877}
878
879static int dw_mci_edmac_init(struct dw_mci *host)
880{
881 /* Request external dma channel */
882 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
883 if (!host->dms)
884 return -ENOMEM;
885
886 host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
887 if (!host->dms->ch) {
4539d36e 888 dev_err(host->dev, "Failed to get external DMA channel.\n");
3fc7eaef
SL		 889 kfree(host->dms);
890 host->dms = NULL;
891 return -ENXIO;
892 }
893
894 return 0;
895}
896
897static void dw_mci_edmac_exit(struct dw_mci *host)
898{
899 if (host->dms) {
900 if (host->dms->ch) {
901 dma_release_channel(host->dms->ch);
902 host->dms->ch = NULL;
903 }
904 kfree(host->dms);
905 host->dms = NULL;
906 }
907}
908
909static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
910 .init = dw_mci_edmac_init,
911 .exit = dw_mci_edmac_exit,
912 .start = dw_mci_edmac_start_dma,
913 .stop = dw_mci_edmac_stop_dma,
914 .complete = dw_mci_dmac_complete_dma,
885c3e80
SJ		 915 .cleanup = dw_mci_dma_cleanup,
916};
885c3e80 917
9aa51408
SJ		 918static int dw_mci_pre_dma_transfer(struct dw_mci *host,
919 struct mmc_data *data,
a4cc7eb4 920 int cookie)
f95f3850
WN		 921{
922 struct scatterlist *sg;
9aa51408 923 unsigned int i, sg_len;
03e8cb53 924
a4cc7eb4
JC		 925 if (data->host_cookie == COOKIE_PRE_MAPPED)
926 return data->sg_len;
f95f3850
WN		 927
928 /*
929 * We don't do DMA on "complex" transfers, i.e. with
930 * non-word-aligned buffers or lengths. Also, we don't bother
931 * with all the DMA setup overhead for short transfers.
932 */
933 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
934 return -EINVAL;
9aa51408 935
f95f3850
WN		 936 if (data->blksz & 3)
937 return -EINVAL;
938
939 for_each_sg(data->sg, sg, data->sg_len, i) {
940 if (sg->offset & 3 || sg->length & 3)
941 return -EINVAL;
942 }
943
4a90920c 944 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 945 data->sg,
946 data->sg_len,
feeef096 947 mmc_get_dma_dir(data));
9aa51408
SJ		 948 if (sg_len == 0)
949 return -EINVAL;
03e8cb53 950
a4cc7eb4 951 data->host_cookie = cookie;
f95f3850 952
9aa51408
SJ		 953 return sg_len;
954}
955
9aa51408 956static void dw_mci_pre_req(struct mmc_host *mmc,
d3c6aac3 957 struct mmc_request *mrq)
9aa51408
SJ		 958{
959 struct dw_mci_slot *slot = mmc_priv(mmc);
960 struct mmc_data *data = mrq->data;
961
962 if (!slot->host->use_dma || !data)
963 return;
964
a4cc7eb4
JC		 965 /* This data might be unmapped at this time */
966 data->host_cookie = COOKIE_UNMAPPED;
9aa51408 967
a4cc7eb4
JC		 968 if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
969 COOKIE_PRE_MAPPED) < 0)
970 data->host_cookie = COOKIE_UNMAPPED;
9aa51408
SJ		 971}
972
973static void dw_mci_post_req(struct mmc_host *mmc,
974 struct mmc_request *mrq,
975 int err)
976{
977 struct dw_mci_slot *slot = mmc_priv(mmc);
978 struct mmc_data *data = mrq->data;
979
980 if (!slot->host->use_dma || !data)
981 return;
982
a4cc7eb4 983 if (data->host_cookie != COOKIE_UNMAPPED)
4a90920c 984 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 985 data->sg,
986 data->sg_len,
feeef096 987 mmc_get_dma_dir(data));
a4cc7eb4 988 data->host_cookie = COOKIE_UNMAPPED;
9aa51408
SJ		 989}
990
671fa142
SL		 991static int dw_mci_get_cd(struct mmc_host *mmc)
992{
993 int present;
994 struct dw_mci_slot *slot = mmc_priv(mmc);
995 struct dw_mci *host = slot->host;
996 int gpio_cd = mmc_gpio_get_cd(mmc);
997
998 /* Use platform get_cd function, else try onboard card detect */
999 if (((mmc->caps & MMC_CAP_NEEDS_POLL)
1000 || !mmc_card_is_removable(mmc))) {
1001 present = 1;
1002
1003 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
1004 if (mmc->caps & MMC_CAP_NEEDS_POLL) {
1005 dev_info(&mmc->class_dev,
1006 "card is polling.\n");
1007 } else {
1008 dev_info(&mmc->class_dev,
1009 "card is non-removable.\n");
1010 }
1011 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1012 }
1013
1014 return present;
1015 } else if (gpio_cd >= 0)
1016 present = gpio_cd;
1017 else
1018 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
1019 == 0 ? 1 : 0;
1020
1021 spin_lock_bh(&host->lock);
1022 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1023 dev_dbg(&mmc->class_dev, "card is present\n");
1024 else if (!present &&
1025 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
1026 dev_dbg(&mmc->class_dev, "card is not present\n");
1027 spin_unlock_bh(&host->lock);
1028
1029 return present;
1030}
1031
52426899
SJ		 1032static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
1033{
52426899 1034 unsigned int blksz = data->blksz;
27d70d36 1035 static const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
52426899
SJ		 1036 u32 fifo_width = 1 << host->data_shift;
1037 u32 blksz_depth = blksz / fifo_width, fifoth_val;
1038 u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
0e3a22c0 1039 int idx = ARRAY_SIZE(mszs) - 1;
52426899 1040
3fc7eaef
SL		 1041 /* pio should ship this scenario */
1042 if (!host->use_dma)
1043 return;
1044
52426899
SJ		 1045 tx_wmark = (host->fifo_depth) / 2;
1046 tx_wmark_invers = host->fifo_depth - tx_wmark;
1047
1048 /*
1049 * MSIZE is '1',
1050 * if blksz is not a multiple of the FIFO width
1051 */
20753569 1052 if (blksz % fifo_width)
52426899 1053 goto done;
52426899
SJ		 1054
1055 do {
1056 if (!((blksz_depth % mszs[idx]) ||
1057 (tx_wmark_invers % mszs[idx]))) {
1058 msize = idx;
1059 rx_wmark = mszs[idx] - 1;
1060 break;
1061 }
1062 } while (--idx > 0);
1063 /*
1064 * If idx is '0', it won't be tried
1065 * Thus, initial values are uesed
1066 */
1067done:
1068 fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1069 mci_writel(host, FIFOTH, fifoth_val);
52426899
SJ		 1070}
1071
7e4bf1bc 1072static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
f1d2736c
SJ		 1073{
1074 unsigned int blksz = data->blksz;
1075 u32 blksz_depth, fifo_depth;
1076 u16 thld_size;
7e4bf1bc 1077 u8 enable;
f1d2736c 1078
66dfd101
JH		 1079 /*
1080 * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1081 * in the FIFO region, so we really shouldn't access it).
1082 */
7e4bf1bc
JC		 1083 if (host->verid < DW_MMC_240A ||
1084 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1085 return;
1086
1087 /*
1088 * Card write Threshold is introduced since 2.80a
1089 * It's used when HS400 mode is enabled.
1090 */
1091 if (data->flags & MMC_DATA_WRITE &&
caa7f812 1092 host->timing != MMC_TIMING_MMC_HS400)
1093 goto disable;
66dfd101 1094
7e4bf1bc
JC		 1095 if (data->flags & MMC_DATA_WRITE)
1096 enable = SDMMC_CARD_WR_THR_EN;
1097 else
1098 enable = SDMMC_CARD_RD_THR_EN;
1099
f1d2736c 1100 if (host->timing != MMC_TIMING_MMC_HS200 &&
caa7f812 1101 host->timing != MMC_TIMING_UHS_SDR104 &&
1102 host->timing != MMC_TIMING_MMC_HS400)
f1d2736c
SJ		 1103 goto disable;
1104
1105 blksz_depth = blksz / (1 << host->data_shift);
1106 fifo_depth = host->fifo_depth;
1107
1108 if (blksz_depth > fifo_depth)
1109 goto disable;
1110
1111 /*
1112 * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1113 * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
1114 * Currently just choose blksz.
1115 */
1116 thld_size = blksz;
7e4bf1bc 1117 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
f1d2736c
SJ		 1118 return;
1119
1120disable:
7e4bf1bc 1121 mci_writel(host, CDTHRCTL, 0);
f1d2736c
SJ		 1122}
1123
9aa51408
SJ		 1124static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1125{
f8c58c11 1126 unsigned long irqflags;
9aa51408
SJ		 1127 int sg_len;
1128 u32 temp;
1129
1130 host->using_dma = 0;
1131
1132 /* If we don't have a channel, we can't do DMA */
1133 if (!host->use_dma)
1134 return -ENODEV;
1135
a4cc7eb4 1136 sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
a99aa9b9
SJ		 1137 if (sg_len < 0) {
1138 host->dma_ops->stop(host);
9aa51408 1139 return sg_len;
a99aa9b9 1140 }
9aa51408
SJ		 1141
1142 host->using_dma = 1;
f95f3850 1143
3fc7eaef
SL		 1144 if (host->use_dma == TRANS_MODE_IDMAC)
1145 dev_vdbg(host->dev,
1146 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1147 (unsigned long)host->sg_cpu,
1148 (unsigned long)host->sg_dma,
1149 sg_len);
f95f3850 1150
52426899
SJ		 1151 /*
1152 * Decide the MSIZE and RX/TX Watermark.
1153 * If current block size is same with previous size,
1154 * no need to update fifoth.
1155 */
1156 if (host->prev_blksz != data->blksz)
1157 dw_mci_adjust_fifoth(host, data);
1158
f95f3850
WN		 1159 /* Enable the DMA interface */
1160 temp = mci_readl(host, CTRL);
1161 temp |= SDMMC_CTRL_DMA_ENABLE;
1162 mci_writel(host, CTRL, temp);
1163
1164 /* Disable RX/TX IRQs, let DMA handle it */
f8c58c11 1165 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1166 temp = mci_readl(host, INTMASK);
1167 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1168 mci_writel(host, INTMASK, temp);
f8c58c11 1169 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850 1170
3fc7eaef 1171 if (host->dma_ops->start(host, sg_len)) {
647f80a1 1172 host->dma_ops->stop(host);
d12d0cb1
SL		 1173 /* We can't do DMA, try PIO for this one */
1174 dev_dbg(host->dev,
1175 "%s: fall back to PIO mode for current transfer\n",
1176 __func__);
3fc7eaef
SL		 1177 return -ENODEV;
1178 }
f95f3850
WN		 1179
1180 return 0;
1181}
1182
1183static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1184{
f8c58c11 1185 unsigned long irqflags;
0e3a22c0 1186 int flags = SG_MITER_ATOMIC;
f95f3850
WN		 1187 u32 temp;
1188
1189 data->error = -EINPROGRESS;
1190
1191 WARN_ON(host->data);
1192 host->sg = NULL;
1193 host->data = data;
1194
7e4bf1bc 1195 if (data->flags & MMC_DATA_READ)
55c5efbc 1196 host->dir_status = DW_MCI_RECV_STATUS;
7e4bf1bc 1197 else
55c5efbc 1198 host->dir_status = DW_MCI_SEND_STATUS;
7e4bf1bc
JC		 1199
1200 dw_mci_ctrl_thld(host, data);
55c5efbc 1201
f95f3850 1202 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 1203 if (host->data->flags & MMC_DATA_READ)
1204 flags |= SG_MITER_TO_SG;
1205 else
1206 flags |= SG_MITER_FROM_SG;
1207
1208 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 1209 host->sg = data->sg;
34b664a2
JH		 1210 host->part_buf_start = 0;
1211 host->part_buf_count = 0;
f95f3850 1212
b40af3aa 1213 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f8c58c11
DA		 1214
1215 spin_lock_irqsave(&host->irq_lock, irqflags);
f95f3850
WN		 1216 temp = mci_readl(host, INTMASK);
1217 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1218 mci_writel(host, INTMASK, temp);
f8c58c11 1219 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 1220
1221 temp = mci_readl(host, CTRL);
1222 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1223 mci_writel(host, CTRL, temp);
52426899
SJ		 1224
1225 /*
d6fced83
JN		 1226 * Use the initial fifoth_val for PIO mode. If wm_algined
1227 * is set, we set watermark same as data size.
52426899
SJ		 1228 * If next issued data may be transfered by DMA mode,
1229 * prev_blksz should be invalidated.
1230 */
d6fced83
JN		 1231 if (host->wm_aligned)
1232 dw_mci_adjust_fifoth(host, data);
1233 else
1234 mci_writel(host, FIFOTH, host->fifoth_val);
52426899
SJ		 1235 host->prev_blksz = 0;
1236 } else {
1237 /*
1238 * Keep the current block size.
1239 * It will be used to decide whether to update
1240 * fifoth register next time.
1241 */
1242 host->prev_blksz = data->blksz;
f95f3850
WN		 1243 }
1244}
1245
ab269128 1246static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
f95f3850
WN		 1247{
1248 struct dw_mci *host = slot->host;
fdf492a1 1249 unsigned int clock = slot->clock;
f95f3850 1250 u32 div;
9623b5b9 1251 u32 clk_en_a;
01730558
DA		 1252 u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1253
1254 /* We must continue to set bit 28 in CMD until the change is complete */
1255 if (host->state == STATE_WAITING_CMD11_DONE)
1256 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
f95f3850 1257
cd1795ff
SL		 1258 slot->mmc->actual_clock = 0;
1259
fdf492a1
DA		 1260 if (!clock) {
1261 mci_writel(host, CLKENA, 0);
01730558 1262 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
fdf492a1
DA		 1263 } else if (clock != host->current_speed || force_clkinit) {
1264 div = host->bus_hz / clock;
1265 if (host->bus_hz % clock && host->bus_hz > clock)
f95f3850
WN		 1266 /*
1267 * move the + 1 after the divide to prevent
1268 * over-clocking the card.
1269 */
e419990b
SJ		 1270 div += 1;
1271
fdf492a1 1272 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850 1273
e6cd7a8e
JC		 1274 if ((clock != slot->__clk_old &&
1275 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1276 force_clkinit) {
ce69e2fe
SL		 1277 /* Silent the verbose log if calling from PM context */
1278 if (!force_clkinit)
1279 dev_info(&slot->mmc->class_dev,
1280 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1281 slot->id, host->bus_hz, clock,
1282 div ? ((host->bus_hz / div) >> 1) :
1283 host->bus_hz, div);
f95f3850 1284
e6cd7a8e
JC		 1285 /*
1286 * If card is polling, display the message only
1287 * one time at boot time.
1288 */
1289 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1290 slot->mmc->f_min == clock)
1291 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1292 }
1293
f95f3850
WN		 1294 /* disable clock */
1295 mci_writel(host, CLKENA, 0);
1296 mci_writel(host, CLKSRC, 0);
1297
1298 /* inform CIU */
01730558 1299 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850
WN		 1300
1301 /* set clock to desired speed */
1302 mci_writel(host, CLKDIV, div);
1303
1304 /* inform CIU */
01730558 1305 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
f95f3850 1306
9623b5b9
DA		 1307 /* enable clock; only low power if no SDIO */
1308 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
b24c8b26 1309 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
9623b5b9
DA		 1310 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1311 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 1312
1313 /* inform CIU */
01730558 1314 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
005d675a
JC		 1315
1316 /* keep the last clock value that was requested from core */
1317 slot->__clk_old = clock;
cd1795ff
SL		 1318 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) :
1319 host->bus_hz;
f95f3850
WN		 1320 }
1321
fdf492a1
DA		 1322 host->current_speed = clock;
1323
f95f3850 1324 /* Set the current slot bus width */
1d56c453 1325 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 1326}
1327
053b3ce6
SJ		 1328static void __dw_mci_start_request(struct dw_mci *host,
1329 struct dw_mci_slot *slot,
1330 struct mmc_command *cmd)
f95f3850
WN		 1331{
1332 struct mmc_request *mrq;
f95f3850
WN		 1333 struct mmc_data *data;
1334 u32 cmdflags;
1335
1336 mrq = slot->mrq;
f95f3850 1337
f95f3850
WN		 1338 host->mrq = mrq;
1339
1340 host->pending_events = 0;
1341 host->completed_events = 0;
e352c813 1342 host->cmd_status = 0;
f95f3850 1343 host->data_status = 0;
e352c813 1344 host->dir_status = 0;
f95f3850 1345
053b3ce6 1346 data = cmd->data;
f95f3850 1347 if (data) {
f16afa88 1348 mci_writel(host, TMOUT, 0xFFFFFFFF);
f95f3850
WN		 1349 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1350 mci_writel(host, BLKSIZ, data->blksz);
1351 }
1352
f95f3850
WN		 1353 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1354
1355 /* this is the first command, send the initialization clock */
1356 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1357 cmdflags |= SDMMC_CMD_INIT;
1358
1359 if (data) {
1360 dw_mci_submit_data(host, data);
0e3a22c0 1361 wmb(); /* drain writebuffer */
f95f3850
WN		 1362 }
1363
1364 dw_mci_start_command(host, cmd, cmdflags);
1365
5c935165 1366 if (cmd->opcode == SD_SWITCH_VOLTAGE) {
49ba0302
DA		 1367 unsigned long irqflags;
1368
5c935165 1369 /*
8886a6fd
DA		 1370 * Databook says to fail after 2ms w/ no response, but evidence
1371 * shows that sometimes the cmd11 interrupt takes over 130ms.
1372 * We'll set to 500ms, plus an extra jiffy just in case jiffies
1373 * is just about to roll over.
49ba0302
DA		 1374 *
1375 * We do this whole thing under spinlock and only if the
1376 * command hasn't already completed (indicating the the irq
1377 * already ran so we don't want the timeout).
5c935165 1378 */
49ba0302
DA		 1379 spin_lock_irqsave(&host->irq_lock, irqflags);
1380 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1381 mod_timer(&host->cmd11_timer,
1382 jiffies + msecs_to_jiffies(500) + 1);
1383 spin_unlock_irqrestore(&host->irq_lock, irqflags);
5c935165
DA		 1384 }
1385
e13c3c08 1386 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
f95f3850
WN		 1387}
1388
053b3ce6
SJ		 1389static void dw_mci_start_request(struct dw_mci *host,
1390 struct dw_mci_slot *slot)
1391{
1392 struct mmc_request *mrq = slot->mrq;
1393 struct mmc_command *cmd;
1394
1395 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1396 __dw_mci_start_request(host, slot, cmd);
1397}
1398
7456caae 1399/* must be called with host->lock held */
f95f3850
WN		 1400static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1401 struct mmc_request *mrq)
1402{
1403 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1404 host->state);
1405
f95f3850
WN		 1406 slot->mrq = mrq;
1407
01730558
DA		 1408 if (host->state == STATE_WAITING_CMD11_DONE) {
1409 dev_warn(&slot->mmc->class_dev,
1410 "Voltage change didn't complete\n");
1411 /*
1412 * this case isn't expected to happen, so we can
1413 * either crash here or just try to continue on
1414 * in the closest possible state
1415 */
1416 host->state = STATE_IDLE;
1417 }
1418
f95f3850
WN		 1419 if (host->state == STATE_IDLE) {
1420 host->state = STATE_SENDING_CMD;
1421 dw_mci_start_request(host, slot);
1422 } else {
1423 list_add_tail(&slot->queue_node, &host->queue);
1424 }
f95f3850
WN		 1425}
1426
1427static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1428{
1429 struct dw_mci_slot *slot = mmc_priv(mmc);
1430 struct dw_mci *host = slot->host;
1431
1432 WARN_ON(slot->mrq);
1433
7456caae
JH		 1434 /*
1435 * The check for card presence and queueing of the request must be
1436 * atomic, otherwise the card could be removed in between and the
1437 * request wouldn't fail until another card was inserted.
1438 */
7456caae 1439
56f6911c 1440 if (!dw_mci_get_cd(mmc)) {
f95f3850
WN		 1441 mrq->cmd->error = -ENOMEDIUM;
1442 mmc_request_done(mmc, mrq);
1443 return;
1444 }
1445
56f6911c
SL		 1446 spin_lock_bh(&host->lock);
1447
f95f3850 1448 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 1449
1450 spin_unlock_bh(&host->lock);
f95f3850
WN		 1451}
1452
1453static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1454{
1455 struct dw_mci_slot *slot = mmc_priv(mmc);
e95baf13 1456 const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
41babf75 1457 u32 regs;
51da2240 1458 int ret;
f95f3850 1459
f95f3850 1460 switch (ios->bus_width) {
f95f3850
WN		 1461 case MMC_BUS_WIDTH_4:
1462 slot->ctype = SDMMC_CTYPE_4BIT;
1463 break;
c9b2a06f
JC		 1464 case MMC_BUS_WIDTH_8:
1465 slot->ctype = SDMMC_CTYPE_8BIT;
1466 break;
b2f7cb45
JC		 1467 default:
1468 /* set default 1 bit mode */
1469 slot->ctype = SDMMC_CTYPE_1BIT;
f95f3850
WN		 1470 }
1471
3f514291
SJ		 1472 regs = mci_readl(slot->host, UHS_REG);
1473
41babf75 1474 /* DDR mode set */
80113132 1475 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
7cc8d580 1476 ios->timing == MMC_TIMING_UHS_DDR50 ||
80113132 1477 ios->timing == MMC_TIMING_MMC_HS400)
c69042a5 1478 regs |= ((0x1 << slot->id) << 16);
3f514291 1479 else
c69042a5 1480 regs &= ~((0x1 << slot->id) << 16);
3f514291
SJ		 1481
1482 mci_writel(slot->host, UHS_REG, regs);
f1d2736c 1483 slot->host->timing = ios->timing;
41babf75 1484
fdf492a1
DA		 1485 /*
1486 * Use mirror of ios->clock to prevent race with mmc
1487 * core ios update when finding the minimum.
1488 */
1489 slot->clock = ios->clock;
f95f3850 1490
cb27a843
JH		 1491 if (drv_data && drv_data->set_ios)
1492 drv_data->set_ios(slot->host, ios);
800d78bf 1493
f95f3850
WN		 1494 switch (ios->power_mode) {
1495 case MMC_POWER_UP:
51da2240
YC		 1496 if (!IS_ERR(mmc->supply.vmmc)) {
1497 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1498 ios->vdd);
1499 if (ret) {
1500 dev_err(slot->host->dev,
1501 "failed to enable vmmc regulator\n");
1502 /*return, if failed turn on vmmc*/
1503 return;
1504 }
1505 }
29d0d161
DA		 1506 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1507 regs = mci_readl(slot->host, PWREN);
1508 regs |= (1 << slot->id);
1509 mci_writel(slot->host, PWREN, regs);
1510 break;
1511 case MMC_POWER_ON:
d1f1dd86
DA		 1512 if (!slot->host->vqmmc_enabled) {
1513 if (!IS_ERR(mmc->supply.vqmmc)) {
1514 ret = regulator_enable(mmc->supply.vqmmc);
1515 if (ret < 0)
1516 dev_err(slot->host->dev,
1517 "failed to enable vqmmc\n");
1518 else
1519 slot->host->vqmmc_enabled = true;
1520
1521 } else {
1522 /* Keep track so we don't reset again */
51da2240 1523 slot->host->vqmmc_enabled = true;
d1f1dd86
DA		 1524 }
1525
1526 /* Reset our state machine after powering on */
1527 dw_mci_ctrl_reset(slot->host,
1528 SDMMC_CTRL_ALL_RESET_FLAGS);
51da2240 1529 }
655babbd
DA		 1530
1531 /* Adjust clock / bus width after power is up */
1532 dw_mci_setup_bus(slot, false);
1533
e6f34e2f
JH		 1534 break;
1535 case MMC_POWER_OFF:
655babbd
DA		 1536 /* Turn clock off before power goes down */
1537 dw_mci_setup_bus(slot, false);
1538
51da2240
YC		 1539 if (!IS_ERR(mmc->supply.vmmc))
1540 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1541
d1f1dd86 1542 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
51da2240 1543 regulator_disable(mmc->supply.vqmmc);
d1f1dd86 1544 slot->host->vqmmc_enabled = false;
51da2240 1545
4366dcc5
JC		 1546 regs = mci_readl(slot->host, PWREN);
1547 regs &= ~(1 << slot->id);
1548 mci_writel(slot->host, PWREN, regs);
f95f3850
WN		 1549 break;
1550 default:
1551 break;
1552 }
655babbd
DA		 1553
1554 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1555 slot->host->state = STATE_IDLE;
f95f3850
WN		 1556}
1557
01730558
DA		 1558static int dw_mci_card_busy(struct mmc_host *mmc)
1559{
1560 struct dw_mci_slot *slot = mmc_priv(mmc);
1561 u32 status;
1562
1563 /*
1564 * Check the busy bit which is low when DAT[3:0]
1565 * (the data lines) are 0000
1566 */
1567 status = mci_readl(slot->host, STATUS);
1568
1569 return !!(status & SDMMC_STATUS_BUSY);
1570}
1571
1572static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1573{
1574 struct dw_mci_slot *slot = mmc_priv(mmc);
1575 struct dw_mci *host = slot->host;
8f7849c4 1576 const struct dw_mci_drv_data *drv_data = host->drv_data;
01730558
DA		 1577 u32 uhs;
1578 u32 v18 = SDMMC_UHS_18V << slot->id;
01730558
DA		 1579 int ret;
1580
8f7849c4
ZG		 1581 if (drv_data && drv_data->switch_voltage)
1582 return drv_data->switch_voltage(mmc, ios);
1583
01730558
DA		 1584 /*
1585 * Program the voltage. Note that some instances of dw_mmc may use
1586 * the UHS_REG for this. For other instances (like exynos) the UHS_REG
1587 * does no harm but you need to set the regulator directly. Try both.
1588 */
1589 uhs = mci_readl(host, UHS_REG);
e0848f5d 1590 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
01730558 1591 uhs &= ~v18;
e0848f5d 1592 else
01730558 1593 uhs |= v18;
e0848f5d 1594
01730558 1595 if (!IS_ERR(mmc->supply.vqmmc)) {
e0848f5d 1596 ret = mmc_regulator_set_vqmmc(mmc, ios);
01730558
DA		 1597
1598 if (ret) {
b19caf37 1599 dev_dbg(&mmc->class_dev,
e0848f5d
DA		 1600 "Regulator set error %d - %s V\n",
1601 ret, uhs & v18 ? "1.8" : "3.3");
01730558
DA		 1602 return ret;
1603 }
1604 }
1605 mci_writel(host, UHS_REG, uhs);
1606
1607 return 0;
1608}
1609
f95f3850
WN		 1610static int dw_mci_get_ro(struct mmc_host *mmc)
1611{
1612 int read_only;
1613 struct dw_mci_slot *slot = mmc_priv(mmc);
9795a846 1614 int gpio_ro = mmc_gpio_get_ro(mmc);
f95f3850
WN		 1615
1616 /* Use platform get_ro function, else try on board write protect */
287980e4 1617 if (gpio_ro >= 0)
9795a846 1618 read_only = gpio_ro;
f95f3850
WN		 1619 else
1620 read_only =
1621 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1622
1623 dev_dbg(&mmc->class_dev, "card is %s\n",
1624 read_only ? "read-only" : "read-write");
1625
1626 return read_only;
1627}
1628
935a665e
SL		 1629static void dw_mci_hw_reset(struct mmc_host *mmc)
1630{
1631 struct dw_mci_slot *slot = mmc_priv(mmc);
1632 struct dw_mci *host = slot->host;
1633 int reset;
1634
1635 if (host->use_dma == TRANS_MODE_IDMAC)
1636 dw_mci_idmac_reset(host);
1637
1638 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1639 SDMMC_CTRL_FIFO_RESET))
1640 return;
1641
1642 /*
1643 * According to eMMC spec, card reset procedure:
1644 * tRstW >= 1us: RST_n pulse width
1645 * tRSCA >= 200us: RST_n to Command time
1646 * tRSTH >= 1us: RST_n high period
1647 */
1648 reset = mci_readl(host, RST_N);
1649 reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1650 mci_writel(host, RST_N, reset);
1651 usleep_range(1, 2);
1652 reset |= SDMMC_RST_HWACTIVE << slot->id;
1653 mci_writel(host, RST_N, reset);
1654 usleep_range(200, 300);
1655}
1656
b24c8b26 1657static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
9623b5b9 1658{
b24c8b26 1659 struct dw_mci_slot *slot = mmc_priv(mmc);
9623b5b9 1660 struct dw_mci *host = slot->host;
9623b5b9 1661
b24c8b26
DA		 1662 /*
1663 * Low power mode will stop the card clock when idle. According to the
1664 * description of the CLKENA register we should disable low power mode
1665 * for SDIO cards if we need SDIO interrupts to work.
1666 */
1667 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1668 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1669 u32 clk_en_a_old;
1670 u32 clk_en_a;
9623b5b9 1671
b24c8b26
DA		 1672 clk_en_a_old = mci_readl(host, CLKENA);
1673
1674 if (card->type == MMC_TYPE_SDIO ||
1675 card->type == MMC_TYPE_SD_COMBO) {
0eebf9b9 1676 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
b24c8b26
DA		 1677 clk_en_a = clk_en_a_old & ~clken_low_pwr;
1678 } else {
0eebf9b9 1679 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
b24c8b26
DA		 1680 clk_en_a = clk_en_a_old | clken_low_pwr;
1681 }
1682
1683 if (clk_en_a != clk_en_a_old) {
1684 mci_writel(host, CLKENA, clk_en_a);
1685 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1686 SDMMC_CMD_PRV_DAT_WAIT, 0);
1687 }
9623b5b9
DA		 1688 }
1689}
1690
32dba737 1691static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1a5c8e1f 1692{
1a5c8e1f 1693 struct dw_mci *host = slot->host;
f8c58c11 1694 unsigned long irqflags;
1a5c8e1f
SH		 1695 u32 int_mask;
1696
f8c58c11
DA		 1697 spin_lock_irqsave(&host->irq_lock, irqflags);
1698
1a5c8e1f
SH		 1699 /* Enable/disable Slot Specific SDIO interrupt */
1700 int_mask = mci_readl(host, INTMASK);
b24c8b26
DA		 1701 if (enb)
1702 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1703 else
1704 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1705 mci_writel(host, INTMASK, int_mask);
f8c58c11
DA		 1706
1707 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1a5c8e1f
SH		 1708}
1709
32dba737
UH		 1710static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1711{
1712 struct dw_mci_slot *slot = mmc_priv(mmc);
ca8971ca 1713 struct dw_mci *host = slot->host;
32dba737
UH		 1714
1715 __dw_mci_enable_sdio_irq(slot, enb);
ca8971ca
UH		 1716
1717 /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1718 if (enb)
1719 pm_runtime_get_noresume(host->dev);
1720 else
1721 pm_runtime_put_noidle(host->dev);
32dba737
UH		 1722}
1723
1724static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1725{
1726 struct dw_mci_slot *slot = mmc_priv(mmc);
1727
1728 __dw_mci_enable_sdio_irq(slot, 1);
1729}
1730
0976f16d
SJ		 1731static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1732{
1733 struct dw_mci_slot *slot = mmc_priv(mmc);
1734 struct dw_mci *host = slot->host;
1735 const struct dw_mci_drv_data *drv_data = host->drv_data;
0e3a22c0 1736 int err = -EINVAL;
0976f16d 1737
0976f16d 1738 if (drv_data && drv_data->execute_tuning)
9979dbe5 1739 err = drv_data->execute_tuning(slot, opcode);
0976f16d
SJ		 1740 return err;
1741}
1742
0e3a22c0
SL		 1743static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1744 struct mmc_ios *ios)
80113132
SJ		 1745{
1746 struct dw_mci_slot *slot = mmc_priv(mmc);
1747 struct dw_mci *host = slot->host;
1748 const struct dw_mci_drv_data *drv_data = host->drv_data;
1749
1750 if (drv_data && drv_data->prepare_hs400_tuning)
1751 return drv_data->prepare_hs400_tuning(host, ios);
1752
1753 return 0;
1754}
1755
4e7392b2
SL		 1756static bool dw_mci_reset(struct dw_mci *host)
1757{
1758 u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1759 bool ret = false;
bc2dcc1a 1760 u32 status = 0;
4e7392b2
SL		 1761
1762 /*
1763 * Resetting generates a block interrupt, hence setting
1764 * the scatter-gather pointer to NULL.
1765 */
1766 if (host->sg) {
1767 sg_miter_stop(&host->sg_miter);
1768 host->sg = NULL;
1769 }
1770
1771 if (host->use_dma)
1772 flags |= SDMMC_CTRL_DMA_RESET;
1773
1774 if (dw_mci_ctrl_reset(host, flags)) {
1775 /*
bc2dcc1a
SL		 1776 * In all cases we clear the RAWINTS
1777 * register to clear any interrupts.
4e7392b2
SL		 1778 */
1779 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1780
bc2dcc1a
SL		 1781 if (!host->use_dma) {
1782 ret = true;
1783 goto ciu_out;
1784 }
4e7392b2 1785
bc2dcc1a
SL		 1786 /* Wait for dma_req to be cleared */
1787 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1788 status,
1789 !(status & SDMMC_STATUS_DMA_REQ),
1790 1, 500 * USEC_PER_MSEC)) {
1791 dev_err(host->dev,
1792 "%s: Timeout waiting for dma_req to be cleared\n",
1793 __func__);
1794 goto ciu_out;
4e7392b2 1795 }
bc2dcc1a
SL		 1796
1797 /* when using DMA next we reset the fifo again */
1798 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1799 goto ciu_out;
4e7392b2
SL		 1800 } else {
1801 /* if the controller reset bit did clear, then set clock regs */
1802 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1803 dev_err(host->dev,
1804 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1805 __func__);
1806 goto ciu_out;
1807 }
1808 }
1809
1810 if (host->use_dma == TRANS_MODE_IDMAC)
7e1f7619
ED		 1811 /* It is also required that we reinit idmac */
1812 dw_mci_idmac_init(host);
4e7392b2
SL		 1813
1814 ret = true;
1815
1816ciu_out:
1817 /* After a CTRL reset we need to have CIU set clock registers */
42f989c0 1818 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
4e7392b2
SL		 1819
1820 return ret;
1821}
1822
f95f3850 1823static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 1824 .request = dw_mci_request,
9aa51408
SJ		 1825 .pre_req = dw_mci_pre_req,
1826 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 1827 .set_ios = dw_mci_set_ios,
1828 .get_ro = dw_mci_get_ro,
1829 .get_cd = dw_mci_get_cd,
935a665e 1830 .hw_reset = dw_mci_hw_reset,
1a5c8e1f 1831 .enable_sdio_irq = dw_mci_enable_sdio_irq,
32dba737 1832 .ack_sdio_irq = dw_mci_ack_sdio_irq,
0976f16d 1833 .execute_tuning = dw_mci_execute_tuning,
01730558
DA		 1834 .card_busy = dw_mci_card_busy,
1835 .start_signal_voltage_switch = dw_mci_switch_voltage,
b24c8b26 1836 .init_card = dw_mci_init_card,
80113132 1837 .prepare_hs400_tuning = dw_mci_prepare_hs400_tuning,
f95f3850
WN		 1838};
1839
1840static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1841 __releases(&host->lock)
1842 __acquires(&host->lock)
1843{
1844 struct dw_mci_slot *slot;
42f989c0 1845 struct mmc_host *prev_mmc = host->slot->mmc;
f95f3850
WN		 1846
1847 WARN_ON(host->cmd || host->data);
1848
42f989c0 1849 host->slot->mrq = NULL;
f95f3850
WN		 1850 host->mrq = NULL;
1851 if (!list_empty(&host->queue)) {
1852 slot = list_entry(host->queue.next,
1853 struct dw_mci_slot, queue_node);
1854 list_del(&slot->queue_node);
4a90920c 1855 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 1856 mmc_hostname(slot->mmc));
1857 host->state = STATE_SENDING_CMD;
1858 dw_mci_start_request(host, slot);
1859 } else {
4a90920c 1860 dev_vdbg(host->dev, "list empty\n");
01730558
DA		 1861
1862 if (host->state == STATE_SENDING_CMD11)
1863 host->state = STATE_WAITING_CMD11_DONE;
1864 else
1865 host->state = STATE_IDLE;
f95f3850
WN		 1866 }
1867
1868 spin_unlock(&host->lock);
1869 mmc_request_done(prev_mmc, mrq);
1870 spin_lock(&host->lock);
1871}
1872
e352c813 1873static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
f95f3850
WN		 1874{
1875 u32 status = host->cmd_status;
1876
1877 host->cmd_status = 0;
1878
1879 /* Read the response from the card (up to 16 bytes) */
1880 if (cmd->flags & MMC_RSP_PRESENT) {
1881 if (cmd->flags & MMC_RSP_136) {
1882 cmd->resp[3] = mci_readl(host, RESP0);
1883 cmd->resp[2] = mci_readl(host, RESP1);
1884 cmd->resp[1] = mci_readl(host, RESP2);
1885 cmd->resp[0] = mci_readl(host, RESP3);
1886 } else {
1887 cmd->resp[0] = mci_readl(host, RESP0);
1888 cmd->resp[1] = 0;
1889 cmd->resp[2] = 0;
1890 cmd->resp[3] = 0;
1891 }
1892 }
1893
1894 if (status & SDMMC_INT_RTO)
1895 cmd->error = -ETIMEDOUT;
1896 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1897 cmd->error = -EILSEQ;
1898 else if (status & SDMMC_INT_RESP_ERR)
1899 cmd->error = -EIO;
1900 else
1901 cmd->error = 0;
1902
e352c813
SJ		 1903 return cmd->error;
1904}
1905
1906static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1907{
31bff450 1908 u32 status = host->data_status;
e352c813
SJ		 1909
1910 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1911 if (status & SDMMC_INT_DRTO) {
1912 data->error = -ETIMEDOUT;
1913 } else if (status & SDMMC_INT_DCRC) {
1914 data->error = -EILSEQ;
1915 } else if (status & SDMMC_INT_EBE) {
1916 if (host->dir_status ==
1917 DW_MCI_SEND_STATUS) {
1918 /*
1919 * No data CRC status was returned.
1920 * The number of bytes transferred
1921 * will be exaggerated in PIO mode.
1922 */
1923 data->bytes_xfered = 0;
1924 data->error = -ETIMEDOUT;
1925 } else if (host->dir_status ==
1926 DW_MCI_RECV_STATUS) {
e7a1dec1 1927 data->error = -EILSEQ;
e352c813
SJ		 1928 }
1929 } else {
1930 /* SDMMC_INT_SBE is included */
e7a1dec1 1931 data->error = -EILSEQ;
e352c813
SJ		 1932 }
1933
e6cc0123 1934 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
e352c813
SJ		 1935
1936 /*
1937 * After an error, there may be data lingering
31bff450 1938 * in the FIFO
e352c813 1939 */
3a33a94c 1940 dw_mci_reset(host);
e352c813
SJ		 1941 } else {
1942 data->bytes_xfered = data->blocks * data->blksz;
1943 data->error = 0;
1944 }
1945
1946 return data->error;
f95f3850
WN		 1947}
1948
57e10486
AK		 1949static void dw_mci_set_drto(struct dw_mci *host)
1950{
1951 unsigned int drto_clks;
9d9491a7 1952 unsigned int drto_div;
57e10486 1953 unsigned int drto_ms;
93c23ae3 1954 unsigned long irqflags;
57e10486
AK		 1955
1956 drto_clks = mci_readl(host, TMOUT) >> 8;
9d9491a7
DA		 1957 drto_div = (mci_readl(host, CLKDIV) & 0xff) * 2;
1958 if (drto_div == 0)
1959 drto_div = 1;
7ff1c704
ED		 1960
1961 drto_ms = DIV_ROUND_UP_ULL((u64)MSEC_PER_SEC * drto_clks * drto_div,
1962 host->bus_hz);
57e10486
AK		 1963
1964 /* add a bit spare time */
1965 drto_ms += 10;
1966
93c23ae3
DA		 1967 spin_lock_irqsave(&host->irq_lock, irqflags);
1968 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1969 mod_timer(&host->dto_timer,
1970 jiffies + msecs_to_jiffies(drto_ms));
1971 spin_unlock_irqrestore(&host->irq_lock, irqflags);
57e10486
AK		 1972}
1973
8892b705
DA		 1974static bool dw_mci_clear_pending_cmd_complete(struct dw_mci *host)
1975{
1976 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1977 return false;
1978
1979 /*
1980 * Really be certain that the timer has stopped. This is a bit of
1981 * paranoia and could only really happen if we had really bad
1982 * interrupt latency and the interrupt routine and timeout were
1983 * running concurrently so that the del_timer() in the interrupt
1984 * handler couldn't run.
1985 */
1986 WARN_ON(del_timer_sync(&host->cto_timer));
1987 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1988
1989 return true;
1990}
1991
93c23ae3
DA		 1992static bool dw_mci_clear_pending_data_complete(struct dw_mci *host)
1993{
1994 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events))
1995 return false;
1996
1997 /* Extra paranoia just like dw_mci_clear_pending_cmd_complete() */
1998 WARN_ON(del_timer_sync(&host->dto_timer));
1999 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2000
2001 return true;
2002}
2003
f95f3850
WN		 2004static void dw_mci_tasklet_func(unsigned long priv)
2005{
2006 struct dw_mci *host = (struct dw_mci *)priv;
2007 struct mmc_data *data;
2008 struct mmc_command *cmd;
e352c813 2009 struct mmc_request *mrq;
f95f3850
WN		 2010 enum dw_mci_state state;
2011 enum dw_mci_state prev_state;
e352c813 2012 unsigned int err;
f95f3850
WN		 2013
2014 spin_lock(&host->lock);
2015
2016 state = host->state;
2017 data = host->data;
e352c813 2018 mrq = host->mrq;
f95f3850
WN		 2019
2020 do {
2021 prev_state = state;
2022
2023 switch (state) {
2024 case STATE_IDLE:
01730558 2025 case STATE_WAITING_CMD11_DONE:
f95f3850
WN		 2026 break;
2027
01730558 2028 case STATE_SENDING_CMD11:
f95f3850 2029 case STATE_SENDING_CMD:
8892b705 2030 if (!dw_mci_clear_pending_cmd_complete(host))
f95f3850
WN		 2031 break;
2032
2033 cmd = host->cmd;
2034 host->cmd = NULL;
2035 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
e352c813
SJ		 2036 err = dw_mci_command_complete(host, cmd);
2037 if (cmd == mrq->sbc && !err) {
053b3ce6 2038 prev_state = state = STATE_SENDING_CMD;
42f989c0 2039 __dw_mci_start_request(host, host->slot,
e352c813 2040 mrq->cmd);
053b3ce6
SJ		 2041 goto unlock;
2042 }
2043
e352c813 2044 if (cmd->data && err) {
46d17952
DA		 2045 /*
2046 * During UHS tuning sequence, sending the stop
2047 * command after the response CRC error would
2048 * throw the system into a confused state
2049 * causing all future tuning phases to report
2050 * failure.
2051 *
2052 * In such case controller will move into a data
2053 * transfer state after a response error or
2054 * response CRC error. Let's let that finish
2055 * before trying to send a stop, so we'll go to
2056 * STATE_SENDING_DATA.
2057 *
2058 * Although letting the data transfer take place
2059 * will waste a bit of time (we already know
2060 * the command was bad), it can't cause any
2061 * errors since it's possible it would have
2062 * taken place anyway if this tasklet got
2063 * delayed. Allowing the transfer to take place
2064 * avoids races and keeps things simple.
2065 */
f524983e 2066 if (err != -ETIMEDOUT) {
46d17952
DA		 2067 state = STATE_SENDING_DATA;
2068 continue;
2069 }
2070
71abb133 2071 dw_mci_stop_dma(host);
90c2143a
SJ		 2072 send_stop_abort(host, data);
2073 state = STATE_SENDING_STOP;
2074 break;
71abb133
SJ		 2075 }
2076
e352c813
SJ		 2077 if (!cmd->data || err) {
2078 dw_mci_request_end(host, mrq);
f95f3850
WN		 2079 goto unlock;
2080 }
2081
2082 prev_state = state = STATE_SENDING_DATA;
2083 /* fall through */
2084
2085 case STATE_SENDING_DATA:
2aa35465
DA		 2086 /*
2087 * We could get a data error and never a transfer
2088 * complete so we'd better check for it here.
2089 *
2090 * Note that we don't really care if we also got a
2091 * transfer complete; stopping the DMA and sending an
2092 * abort won't hurt.
2093 */
f95f3850
WN		 2094 if (test_and_clear_bit(EVENT_DATA_ERROR,
2095 &host->pending_events)) {
2096 dw_mci_stop_dma(host);
e13c3c08 2097 if (!(host->data_status & (SDMMC_INT_DRTO |
bdb9a90b 2098 SDMMC_INT_EBE)))
2099 send_stop_abort(host, data);
f95f3850
WN		 2100 state = STATE_DATA_ERROR;
2101 break;
2102 }
2103
2104 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
57e10486
AK		 2105 &host->pending_events)) {
2106 /*
2107 * If all data-related interrupts don't come
2108 * within the given time in reading data state.
2109 */
16a34574 2110 if (host->dir_status == DW_MCI_RECV_STATUS)
57e10486 2111 dw_mci_set_drto(host);
f95f3850 2112 break;
57e10486 2113 }
f95f3850
WN		 2114
2115 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2aa35465
DA		 2116
2117 /*
2118 * Handle an EVENT_DATA_ERROR that might have shown up
2119 * before the transfer completed. This might not have
2120 * been caught by the check above because the interrupt
2121 * could have gone off between the previous check and
2122 * the check for transfer complete.
2123 *
2124 * Technically this ought not be needed assuming we
2125 * get a DATA_COMPLETE eventually (we'll notice the
2126 * error and end the request), but it shouldn't hurt.
2127 *
2128 * This has the advantage of sending the stop command.
2129 */
2130 if (test_and_clear_bit(EVENT_DATA_ERROR,
2131 &host->pending_events)) {
2132 dw_mci_stop_dma(host);
e13c3c08 2133 if (!(host->data_status & (SDMMC_INT_DRTO |
bdb9a90b 2134 SDMMC_INT_EBE)))
2135 send_stop_abort(host, data);
2aa35465
DA		 2136 state = STATE_DATA_ERROR;
2137 break;
2138 }
f95f3850 2139 prev_state = state = STATE_DATA_BUSY;
2aa35465 2140
f95f3850
WN		 2141 /* fall through */
2142
2143 case STATE_DATA_BUSY:
93c23ae3 2144 if (!dw_mci_clear_pending_data_complete(host)) {
57e10486
AK		 2145 /*
2146 * If data error interrupt comes but data over
2147 * interrupt doesn't come within the given time.
2148 * in reading data state.
2149 */
16a34574 2150 if (host->dir_status == DW_MCI_RECV_STATUS)
57e10486 2151 dw_mci_set_drto(host);
f95f3850 2152 break;
57e10486 2153 }
f95f3850
WN		 2154
2155 host->data = NULL;
2156 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
e352c813
SJ		 2157 err = dw_mci_data_complete(host, data);
2158
2159 if (!err) {
2160 if (!data->stop || mrq->sbc) {
17c8bc85 2161 if (mrq->sbc && data->stop)
e352c813
SJ		 2162 data->stop->error = 0;
2163 dw_mci_request_end(host, mrq);
2164 goto unlock;
f95f3850 2165 }
f95f3850 2166
e352c813
SJ		 2167 /* stop command for open-ended transfer*/
2168 if (data->stop)
2169 send_stop_abort(host, data);
2aa35465
DA		 2170 } else {
2171 /*
2172 * If we don't have a command complete now we'll
2173 * never get one since we just reset everything;
2174 * better end the request.
2175 *
2176 * If we do have a command complete we'll fall
2177 * through to the SENDING_STOP command and
2178 * everything will be peachy keen.
2179 */
2180 if (!test_bit(EVENT_CMD_COMPLETE,
2181 &host->pending_events)) {
2182 host->cmd = NULL;
2183 dw_mci_request_end(host, mrq);
2184 goto unlock;
2185 }
053b3ce6
SJ		 2186 }
2187
e352c813
SJ		 2188 /*
2189 * If err has non-zero,
2190 * stop-abort command has been already issued.
2191 */
f95f3850 2192 prev_state = state = STATE_SENDING_STOP;
e352c813 2193
f95f3850
WN		 2194 /* fall through */
2195
2196 case STATE_SENDING_STOP:
8892b705 2197 if (!dw_mci_clear_pending_cmd_complete(host))
f95f3850
WN		 2198 break;
2199
71abb133 2200 /* CMD error in data command */
31bff450 2201 if (mrq->cmd->error && mrq->data)
3a33a94c 2202 dw_mci_reset(host);
71abb133 2203
f95f3850 2204 host->cmd = NULL;
71abb133 2205 host->data = NULL;
90c2143a 2206
e13c3c08 2207 if (!mrq->sbc && mrq->stop)
e352c813 2208 dw_mci_command_complete(host, mrq->stop);
90c2143a
SJ		 2209 else
2210 host->cmd_status = 0;
2211
e352c813 2212 dw_mci_request_end(host, mrq);
f95f3850
WN		 2213 goto unlock;
2214
2215 case STATE_DATA_ERROR:
2216 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2217 &host->pending_events))
2218 break;
2219
2220 state = STATE_DATA_BUSY;
2221 break;
2222 }
2223 } while (state != prev_state);
2224
2225 host->state = state;
2226unlock:
2227 spin_unlock(&host->lock);
2228
2229}
2230
34b664a2
JH		 2231/* push final bytes to part_buf, only use during push */
2232static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 2233{
34b664a2
JH		 2234 memcpy((void *)&host->part_buf, buf, cnt);
2235 host->part_buf_count = cnt;
2236}
f95f3850 2237
34b664a2
JH		 2238/* append bytes to part_buf, only use during push */
2239static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2240{
2241 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2242 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2243 host->part_buf_count += cnt;
2244 return cnt;
2245}
f95f3850 2246
34b664a2
JH		 2247/* pull first bytes from part_buf, only use during pull */
2248static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2249{
0e3a22c0 2250 cnt = min_t(int, cnt, host->part_buf_count);
34b664a2
JH		 2251 if (cnt) {
2252 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2253 cnt);
2254 host->part_buf_count -= cnt;
2255 host->part_buf_start += cnt;
f95f3850 2256 }
34b664a2 2257 return cnt;
f95f3850
WN		 2258}
2259
34b664a2
JH		 2260/* pull final bytes from the part_buf, assuming it's just been filled */
2261static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 2262{
34b664a2
JH		 2263 memcpy(buf, &host->part_buf, cnt);
2264 host->part_buf_start = cnt;
2265 host->part_buf_count = (1 << host->data_shift) - cnt;
2266}
f95f3850 2267
34b664a2
JH		 2268static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2269{
cfbeb59c
MC		 2270 struct mmc_data *data = host->data;
2271 int init_cnt = cnt;
2272
34b664a2
JH		 2273 /* try and push anything in the part_buf */
2274 if (unlikely(host->part_buf_count)) {
2275 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2276
34b664a2
JH		 2277 buf += len;
2278 cnt -= len;
cfbeb59c 2279 if (host->part_buf_count == 2) {
76184ac1 2280 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 2281 host->part_buf_count = 0;
2282 }
2283 }
2284#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2285 if (unlikely((unsigned long)buf & 0x1)) {
2286 while (cnt >= 2) {
2287 u16 aligned_buf[64];
2288 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2289 int items = len >> 1;
2290 int i;
2291 /* memcpy from input buffer into aligned buffer */
2292 memcpy(aligned_buf, buf, len);
2293 buf += len;
2294 cnt -= len;
2295 /* push data from aligned buffer into fifo */
2296 for (i = 0; i < items; ++i)
76184ac1 2297 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2298 }
2299 } else
2300#endif
2301 {
2302 u16 *pdata = buf;
0e3a22c0 2303
34b664a2 2304 for (; cnt >= 2; cnt -= 2)
76184ac1 2305 mci_fifo_writew(host->fifo_reg, *pdata++);
34b664a2
JH		 2306 buf = pdata;
2307 }
2308 /* put anything remaining in the part_buf */
2309 if (cnt) {
2310 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2311 /* Push data if we have reached the expected data length */
2312 if ((data->bytes_xfered + init_cnt) ==
2313 (data->blksz * data->blocks))
76184ac1 2314 mci_fifo_writew(host->fifo_reg, host->part_buf16);
34b664a2
JH		 2315 }
2316}
f95f3850 2317
34b664a2
JH		 2318static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2319{
2320#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2321 if (unlikely((unsigned long)buf & 0x1)) {
2322 while (cnt >= 2) {
2323 /* pull data from fifo into aligned buffer */
2324 u16 aligned_buf[64];
2325 int len = min(cnt & -2, (int)sizeof(aligned_buf));
2326 int items = len >> 1;
2327 int i;
0e3a22c0 2328
34b664a2 2329 for (i = 0; i < items; ++i)
76184ac1 2330 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2331 /* memcpy from aligned buffer into output buffer */
2332 memcpy(buf, aligned_buf, len);
2333 buf += len;
2334 cnt -= len;
2335 }
2336 } else
2337#endif
2338 {
2339 u16 *pdata = buf;
0e3a22c0 2340
34b664a2 2341 for (; cnt >= 2; cnt -= 2)
76184ac1 2342 *pdata++ = mci_fifo_readw(host->fifo_reg);
34b664a2
JH		 2343 buf = pdata;
2344 }
2345 if (cnt) {
76184ac1 2346 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
34b664a2 2347 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2348 }
2349}
2350
2351static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2352{
cfbeb59c
MC		 2353 struct mmc_data *data = host->data;
2354 int init_cnt = cnt;
2355
34b664a2
JH		 2356 /* try and push anything in the part_buf */
2357 if (unlikely(host->part_buf_count)) {
2358 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2359
34b664a2
JH		 2360 buf += len;
2361 cnt -= len;
cfbeb59c 2362 if (host->part_buf_count == 4) {
76184ac1 2363 mci_fifo_writel(host->fifo_reg, host->part_buf32);
34b664a2
JH		 2364 host->part_buf_count = 0;
2365 }
2366 }
2367#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2368 if (unlikely((unsigned long)buf & 0x3)) {
2369 while (cnt >= 4) {
2370 u32 aligned_buf[32];
2371 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2372 int items = len >> 2;
2373 int i;
2374 /* memcpy from input buffer into aligned buffer */
2375 memcpy(aligned_buf, buf, len);
2376 buf += len;
2377 cnt -= len;
2378 /* push data from aligned buffer into fifo */
2379 for (i = 0; i < items; ++i)
76184ac1 2380 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2381 }
2382 } else
2383#endif
2384 {
2385 u32 *pdata = buf;
0e3a22c0 2386
34b664a2 2387 for (; cnt >= 4; cnt -= 4)
76184ac1 2388 mci_fifo_writel(host->fifo_reg, *pdata++);
34b664a2
JH		 2389 buf = pdata;
2390 }
2391 /* put anything remaining in the part_buf */
2392 if (cnt) {
2393 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2394 /* Push data if we have reached the expected data length */
2395 if ((data->bytes_xfered + init_cnt) ==
2396 (data->blksz * data->blocks))
76184ac1 2397 mci_fifo_writel(host->fifo_reg, host->part_buf32);
f95f3850
WN		 2398 }
2399}
2400
2401static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2402{
34b664a2
JH		 2403#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2404 if (unlikely((unsigned long)buf & 0x3)) {
2405 while (cnt >= 4) {
2406 /* pull data from fifo into aligned buffer */
2407 u32 aligned_buf[32];
2408 int len = min(cnt & -4, (int)sizeof(aligned_buf));
2409 int items = len >> 2;
2410 int i;
0e3a22c0 2411
34b664a2 2412 for (i = 0; i < items; ++i)
76184ac1 2413 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2414 /* memcpy from aligned buffer into output buffer */
2415 memcpy(buf, aligned_buf, len);
2416 buf += len;
2417 cnt -= len;
2418 }
2419 } else
2420#endif
2421 {
2422 u32 *pdata = buf;
0e3a22c0 2423
34b664a2 2424 for (; cnt >= 4; cnt -= 4)
76184ac1 2425 *pdata++ = mci_fifo_readl(host->fifo_reg);
34b664a2
JH		 2426 buf = pdata;
2427 }
2428 if (cnt) {
76184ac1 2429 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
34b664a2 2430 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 2431 }
2432}
2433
2434static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2435{
cfbeb59c
MC		 2436 struct mmc_data *data = host->data;
2437 int init_cnt = cnt;
2438
34b664a2
JH		 2439 /* try and push anything in the part_buf */
2440 if (unlikely(host->part_buf_count)) {
2441 int len = dw_mci_push_part_bytes(host, buf, cnt);
0e3a22c0 2442
34b664a2
JH		 2443 buf += len;
2444 cnt -= len;
c09fbd74 2445
cfbeb59c 2446 if (host->part_buf_count == 8) {
76184ac1 2447 mci_fifo_writeq(host->fifo_reg, host->part_buf);
34b664a2
JH		 2448 host->part_buf_count = 0;
2449 }
2450 }
2451#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2452 if (unlikely((unsigned long)buf & 0x7)) {
2453 while (cnt >= 8) {
2454 u64 aligned_buf[16];
2455 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2456 int items = len >> 3;
2457 int i;
2458 /* memcpy from input buffer into aligned buffer */
2459 memcpy(aligned_buf, buf, len);
2460 buf += len;
2461 cnt -= len;
2462 /* push data from aligned buffer into fifo */
2463 for (i = 0; i < items; ++i)
76184ac1 2464 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
34b664a2
JH		 2465 }
2466 } else
2467#endif
2468 {
2469 u64 *pdata = buf;
0e3a22c0 2470
34b664a2 2471 for (; cnt >= 8; cnt -= 8)
76184ac1 2472 mci_fifo_writeq(host->fifo_reg, *pdata++);
34b664a2
JH		 2473 buf = pdata;
2474 }
2475 /* put anything remaining in the part_buf */
2476 if (cnt) {
2477 dw_mci_set_part_bytes(host, buf, cnt);
cfbeb59c
MC		 2478 /* Push data if we have reached the expected data length */
2479 if ((data->bytes_xfered + init_cnt) ==
2480 (data->blksz * data->blocks))
76184ac1 2481 mci_fifo_writeq(host->fifo_reg, host->part_buf);
f95f3850
WN		 2482 }
2483}
2484
2485static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2486{
34b664a2
JH		 2487#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2488 if (unlikely((unsigned long)buf & 0x7)) {
2489 while (cnt >= 8) {
2490 /* pull data from fifo into aligned buffer */
2491 u64 aligned_buf[16];
2492 int len = min(cnt & -8, (int)sizeof(aligned_buf));
2493 int items = len >> 3;
2494 int i;
0e3a22c0 2495
34b664a2 2496 for (i = 0; i < items; ++i)
76184ac1
BD		 2497 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2498
34b664a2
JH		 2499 /* memcpy from aligned buffer into output buffer */
2500 memcpy(buf, aligned_buf, len);
2501 buf += len;
2502 cnt -= len;
2503 }
2504 } else
2505#endif
2506 {
2507 u64 *pdata = buf;
0e3a22c0 2508
34b664a2 2509 for (; cnt >= 8; cnt -= 8)
76184ac1 2510 *pdata++ = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2511 buf = pdata;
2512 }
2513 if (cnt) {
76184ac1 2514 host->part_buf = mci_fifo_readq(host->fifo_reg);
34b664a2
JH		 2515 dw_mci_pull_final_bytes(host, buf, cnt);
2516 }
2517}
f95f3850 2518
34b664a2
JH		 2519static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2520{
2521 int len;
f95f3850 2522
34b664a2
JH		 2523 /* get remaining partial bytes */
2524 len = dw_mci_pull_part_bytes(host, buf, cnt);
2525 if (unlikely(len == cnt))
2526 return;
2527 buf += len;
2528 cnt -= len;
2529
2530 /* get the rest of the data */
2531 host->pull_data(host, buf, cnt);
f95f3850
WN		 2532}
2533
87a74d39 2534static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
f95f3850 2535{
f9c2a0dc
SJ		 2536 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2537 void *buf;
2538 unsigned int offset;
f95f3850
WN		 2539 struct mmc_data *data = host->data;
2540 int shift = host->data_shift;
2541 u32 status;
3e4b0d8b 2542 unsigned int len;
f9c2a0dc 2543 unsigned int remain, fcnt;
f95f3850
WN		 2544
2545 do {
f9c2a0dc
SJ		 2546 if (!sg_miter_next(sg_miter))
2547 goto done;
2548
4225fc85 2549 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2550 buf = sg_miter->addr;
2551 remain = sg_miter->length;
2552 offset = 0;
2553
2554 do {
2555 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2556 << shift) + host->part_buf_count;
2557 len = min(remain, fcnt);
2558 if (!len)
2559 break;
34b664a2 2560 dw_mci_pull_data(host, (void *)(buf + offset), len);
3e4b0d8b 2561 data->bytes_xfered += len;
f95f3850 2562 offset += len;
f9c2a0dc
SJ		 2563 remain -= len;
2564 } while (remain);
f95f3850 2565
e74f3a9c 2566 sg_miter->consumed = offset;
f95f3850
WN		 2567 status = mci_readl(host, MINTSTS);
2568 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
87a74d39
KK		 2569 /* if the RXDR is ready read again */
2570 } while ((status & SDMMC_INT_RXDR) ||
2571 (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
f9c2a0dc
SJ		 2572
2573 if (!remain) {
2574 if (!sg_miter_next(sg_miter))
2575 goto done;
2576 sg_miter->consumed = 0;
2577 }
2578 sg_miter_stop(sg_miter);
f95f3850
WN		 2579 return;
2580
2581done:
f9c2a0dc
SJ		 2582 sg_miter_stop(sg_miter);
2583 host->sg = NULL;
0e3a22c0 2584 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2585 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2586}
2587
2588static void dw_mci_write_data_pio(struct dw_mci *host)
2589{
f9c2a0dc
SJ		 2590 struct sg_mapping_iter *sg_miter = &host->sg_miter;
2591 void *buf;
2592 unsigned int offset;
f95f3850
WN		 2593 struct mmc_data *data = host->data;
2594 int shift = host->data_shift;
2595 u32 status;
3e4b0d8b 2596 unsigned int len;
f9c2a0dc
SJ		 2597 unsigned int fifo_depth = host->fifo_depth;
2598 unsigned int remain, fcnt;
f95f3850
WN		 2599
2600 do {
f9c2a0dc
SJ		 2601 if (!sg_miter_next(sg_miter))
2602 goto done;
2603
4225fc85 2604 host->sg = sg_miter->piter.sg;
f9c2a0dc
SJ		 2605 buf = sg_miter->addr;
2606 remain = sg_miter->length;
2607 offset = 0;
2608
2609 do {
2610 fcnt = ((fifo_depth -
2611 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2612 << shift) - host->part_buf_count;
2613 len = min(remain, fcnt);
2614 if (!len)
2615 break;
f95f3850 2616 host->push_data(host, (void *)(buf + offset), len);
3e4b0d8b 2617 data->bytes_xfered += len;
f95f3850 2618 offset += len;
f9c2a0dc
SJ		 2619 remain -= len;
2620 } while (remain);
f95f3850 2621
e74f3a9c 2622 sg_miter->consumed = offset;
f95f3850
WN		 2623 status = mci_readl(host, MINTSTS);
2624 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 2625 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f9c2a0dc
SJ		 2626
2627 if (!remain) {
2628 if (!sg_miter_next(sg_miter))
2629 goto done;
2630 sg_miter->consumed = 0;
2631 }
2632 sg_miter_stop(sg_miter);
f95f3850
WN		 2633 return;
2634
2635done:
f9c2a0dc
SJ		 2636 sg_miter_stop(sg_miter);
2637 host->sg = NULL;
0e3a22c0 2638 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2639 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2640}
2641
2642static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2643{
0363b12d
DA		 2644 del_timer(&host->cto_timer);
2645
f95f3850
WN		 2646 if (!host->cmd_status)
2647 host->cmd_status = status;
2648
0e3a22c0 2649 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2650
2651 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2652 tasklet_schedule(&host->tasklet);
2653}
2654
6130e7a9
DA		 2655static void dw_mci_handle_cd(struct dw_mci *host)
2656{
b23475fa 2657 struct dw_mci_slot *slot = host->slot;
6130e7a9 2658
58870241
JC		 2659 if (slot->mmc->ops->card_event)
2660 slot->mmc->ops->card_event(slot->mmc);
2661 mmc_detect_change(slot->mmc,
2662 msecs_to_jiffies(host->pdata->detect_delay_ms));
6130e7a9
DA		 2663}
2664
f95f3850
WN		 2665static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2666{
2667 struct dw_mci *host = dev_id;
182c9081 2668 u32 pending;
b23475fa 2669 struct dw_mci_slot *slot = host->slot;
8892b705 2670 unsigned long irqflags;
f95f3850 2671
1fb5f68a
MC		 2672 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2673
476d79f1 2674 if (pending) {
01730558
DA		 2675 /* Check volt switch first, since it can look like an error */
2676 if ((host->state == STATE_SENDING_CMD11) &&
2677 (pending & SDMMC_INT_VOLT_SWITCH)) {
2678 mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2679 pending &= ~SDMMC_INT_VOLT_SWITCH;
49ba0302
DA		 2680
2681 /*
2682 * Hold the lock; we know cmd11_timer can't be kicked
2683 * off after the lock is released, so safe to delete.
2684 */
2685 spin_lock_irqsave(&host->irq_lock, irqflags);
01730558 2686 dw_mci_cmd_interrupt(host, pending);
49ba0302
DA		 2687 spin_unlock_irqrestore(&host->irq_lock, irqflags);
2688
2689 del_timer(&host->cmd11_timer);
01730558
DA		 2690 }
2691
f95f3850 2692 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
8892b705
DA		 2693 spin_lock_irqsave(&host->irq_lock, irqflags);
2694
03de1921 2695 del_timer(&host->cto_timer);
f95f3850 2696 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 2697 host->cmd_status = pending;
0e3a22c0 2698 smp_wmb(); /* drain writebuffer */
f95f3850 2699 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
8892b705
DA		 2700
2701 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 2702 }
2703
2704 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2705 /* if there is an error report DATA_ERROR */
2706 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 2707 host->data_status = pending;
0e3a22c0 2708 smp_wmb(); /* drain writebuffer */
f95f3850 2709 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 2710 tasklet_schedule(&host->tasklet);
f95f3850
WN		 2711 }
2712
2713 if (pending & SDMMC_INT_DATA_OVER) {
93c23ae3
DA		 2714 spin_lock_irqsave(&host->irq_lock, irqflags);
2715
16a34574 2716 del_timer(&host->dto_timer);
57e10486 2717
f95f3850
WN		 2718 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2719 if (!host->data_status)
182c9081 2720 host->data_status = pending;
0e3a22c0 2721 smp_wmb(); /* drain writebuffer */
f95f3850
WN		 2722 if (host->dir_status == DW_MCI_RECV_STATUS) {
2723 if (host->sg != NULL)
87a74d39 2724 dw_mci_read_data_pio(host, true);
f95f3850
WN		 2725 }
2726 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2727 tasklet_schedule(&host->tasklet);
93c23ae3
DA		 2728
2729 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 2730 }
2731
2732 if (pending & SDMMC_INT_RXDR) {
2733 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 2734 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
87a74d39 2735 dw_mci_read_data_pio(host, false);
f95f3850
WN		 2736 }
2737
2738 if (pending & SDMMC_INT_TXDR) {
2739 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 2740 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 2741 dw_mci_write_data_pio(host);
2742 }
2743
2744 if (pending & SDMMC_INT_CMD_DONE) {
8892b705
DA		 2745 spin_lock_irqsave(&host->irq_lock, irqflags);
2746
f95f3850 2747 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 2748 dw_mci_cmd_interrupt(host, pending);
8892b705
DA		 2749
2750 spin_unlock_irqrestore(&host->irq_lock, irqflags);
f95f3850
WN		 2751 }
2752
2753 if (pending & SDMMC_INT_CD) {
2754 mci_writel(host, RINTSTS, SDMMC_INT_CD);
6130e7a9 2755 dw_mci_handle_cd(host);
f95f3850
WN		 2756 }
2757
58870241
JC		 2758 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2759 mci_writel(host, RINTSTS,
2760 SDMMC_INT_SDIO(slot->sdio_id));
2761 __dw_mci_enable_sdio_irq(slot, 0);
2762 sdio_signal_irq(slot->mmc);
1a5c8e1f
SH		 2763 }
2764
1fb5f68a 2765 }
f95f3850 2766
3fc7eaef
SL		 2767 if (host->use_dma != TRANS_MODE_IDMAC)
2768 return IRQ_HANDLED;
2769
2770 /* Handle IDMA interrupts */
69d99fdc
PT		 2771 if (host->dma_64bit_address == 1) {
2772 pending = mci_readl(host, IDSTS64);
2773 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2774 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2775 SDMMC_IDMAC_INT_RI);
2776 mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
faecf411
SL		 2777 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2778 host->dma_ops->complete((void *)host);
69d99fdc
PT		 2779 }
2780 } else {
2781 pending = mci_readl(host, IDSTS);
2782 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2783 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2784 SDMMC_IDMAC_INT_RI);
2785 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
faecf411
SL		 2786 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2787 host->dma_ops->complete((void *)host);
69d99fdc 2788 }
f95f3850 2789 }
f95f3850
WN		 2790
2791 return IRQ_HANDLED;
2792}
2793
3a43bbee
SL		 2794static int dw_mci_init_slot_caps(struct dw_mci_slot *slot)
2795{
2796 struct dw_mci *host = slot->host;
2797 const struct dw_mci_drv_data *drv_data = host->drv_data;
2798 struct mmc_host *mmc = slot->mmc;
2799 int ctrl_id;
2800
2801 if (host->pdata->caps)
2802 mmc->caps = host->pdata->caps;
2803
2804 /*
2805 * Support MMC_CAP_ERASE by default.
2806 * It needs to use trim/discard/erase commands.
2807 */
2808 mmc->caps |= MMC_CAP_ERASE;
2809
2810 if (host->pdata->pm_caps)
2811 mmc->pm_caps = host->pdata->pm_caps;
2812
2813 if (host->dev->of_node) {
2814 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2815 if (ctrl_id < 0)
2816 ctrl_id = 0;
2817 } else {
2818 ctrl_id = to_platform_device(host->dev)->id;
2819 }
358234b6
SL		 2820
2821 if (drv_data && drv_data->caps) {
2822 if (ctrl_id >= drv_data->num_caps) {
2823 dev_err(host->dev, "invalid controller id %d\n",
2824 ctrl_id);
2825 return -EINVAL;
2826 }
3a43bbee 2827 mmc->caps |= drv_data->caps[ctrl_id];
358234b6 2828 }
3a43bbee
SL		 2829
2830 if (host->pdata->caps2)
2831 mmc->caps2 = host->pdata->caps2;
2832
2833 /* Process SDIO IRQs through the sdio_irq_work. */
2834 if (mmc->caps & MMC_CAP_SDIO_IRQ)
2835 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2836
2837 return 0;
2838}
2839
e4a65ef7 2840static int dw_mci_init_slot(struct dw_mci *host)
f95f3850
WN		 2841{
2842 struct mmc_host *mmc;
2843 struct dw_mci_slot *slot;
3a43bbee 2844 int ret;
1f44a2a5 2845 u32 freq[2];
f95f3850 2846
4a90920c 2847 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 2848 if (!mmc)
2849 return -ENOMEM;
2850
2851 slot = mmc_priv(mmc);
e4a65ef7
JC		 2852 slot->id = 0;
2853 slot->sdio_id = host->sdio_id0 + slot->id;
f95f3850
WN		 2854 slot->mmc = mmc;
2855 slot->host = host;
b23475fa 2856 host->slot = slot;
f95f3850
WN		 2857
2858 mmc->ops = &dw_mci_ops;
852ff5fe
DW		 2859 if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2860 freq, 2)) {
1f44a2a5
SJ		 2861 mmc->f_min = DW_MCI_FREQ_MIN;
2862 mmc->f_max = DW_MCI_FREQ_MAX;
2863 } else {
b023030f
JC		 2864 dev_info(host->dev,
2865 "'clock-freq-min-max' property was deprecated.\n");
1f44a2a5
SJ		 2866 mmc->f_min = freq[0];
2867 mmc->f_max = freq[1];
2868 }
f95f3850 2869
51da2240
YC		 2870 /*if there are external regulators, get them*/
2871 ret = mmc_regulator_get_supply(mmc);
0f3a47b8 2872 if (ret)
3cf890fc 2873 goto err_host_allocated;
51da2240
YC		 2874
2875 if (!mmc->ocr_avail)
2876 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
f95f3850 2877
3cf890fc
DA		 2878 ret = mmc_of_parse(mmc);
2879 if (ret)
2880 goto err_host_allocated;
f95f3850 2881
3a43bbee
SL		 2882 ret = dw_mci_init_slot_caps(slot);
2883 if (ret)
2884 goto err_host_allocated;
32dba737 2885
2b708df2 2886 /* Useful defaults if platform data is unset. */
3fc7eaef 2887 if (host->use_dma == TRANS_MODE_IDMAC) {
2b708df2 2888 mmc->max_segs = host->ring_size;
225faf87 2889 mmc->max_blk_size = 65535;
2b708df2
JC		 2890 mmc->max_seg_size = 0x1000;
2891 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2892 mmc->max_blk_count = mmc->max_req_size / 512;
3fc7eaef
SL		 2893 } else if (host->use_dma == TRANS_MODE_EDMAC) {
2894 mmc->max_segs = 64;
225faf87 2895 mmc->max_blk_size = 65535;
3fc7eaef
SL		 2896 mmc->max_blk_count = 65535;
2897 mmc->max_req_size =
2898 mmc->max_blk_size * mmc->max_blk_count;
2899 mmc->max_seg_size = mmc->max_req_size;
f95f3850 2900 } else {
3fc7eaef 2901 /* TRANS_MODE_PIO */
2b708df2 2902 mmc->max_segs = 64;
225faf87 2903 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2b708df2
JC		 2904 mmc->max_blk_count = 512;
2905 mmc->max_req_size = mmc->max_blk_size *
2906 mmc->max_blk_count;
2907 mmc->max_seg_size = mmc->max_req_size;
a39e5746 2908 }
f95f3850 2909
c0834a58 2910 dw_mci_get_cd(mmc);
ae0eb348 2911
0cea529d
JC		 2912 ret = mmc_add_host(mmc);
2913 if (ret)
3cf890fc 2914 goto err_host_allocated;
f95f3850
WN		 2915
2916#if defined(CONFIG_DEBUG_FS)
2917 dw_mci_init_debugfs(slot);
2918#endif
2919
f95f3850 2920 return 0;
800d78bf 2921
3cf890fc 2922err_host_allocated:
800d78bf 2923 mmc_free_host(mmc);
51da2240 2924 return ret;
f95f3850
WN		 2925}
2926
e4a65ef7 2927static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
f95f3850 2928{
f95f3850
WN		 2929 /* Debugfs stuff is cleaned up by mmc core */
2930 mmc_remove_host(slot->mmc);
b23475fa 2931 slot->host->slot = NULL;
f95f3850
WN		 2932 mmc_free_host(slot->mmc);
2933}
2934
2935static void dw_mci_init_dma(struct dw_mci *host)
2936{
69d99fdc 2937 int addr_config;
3fc7eaef 2938 struct device *dev = host->dev;
69d99fdc 2939
3fc7eaef
SL		 2940 /*
2941 * Check tansfer mode from HCON[17:16]
2942 * Clear the ambiguous description of dw_mmc databook:
2943 * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2944 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2945 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2946 * 2b'11: Non DW DMA Interface -> pio only
2947 * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2948 * simpler request/acknowledge handshake mechanism and both of them
2949 * are regarded as external dma master for dw_mmc.
2950 */
2951 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2952 if (host->use_dma == DMA_INTERFACE_IDMA) {
2953 host->use_dma = TRANS_MODE_IDMAC;
2954 } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2955 host->use_dma == DMA_INTERFACE_GDMA) {
2956 host->use_dma = TRANS_MODE_EDMAC;
2957 } else {
f95f3850
WN		 2958 goto no_dma;
2959 }
2960
2961 /* Determine which DMA interface to use */
3fc7eaef
SL		 2962 if (host->use_dma == TRANS_MODE_IDMAC) {
2963 /*
2964 * Check ADDR_CONFIG bit in HCON to find
2965 * IDMAC address bus width
2966 */
70692752 2967 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
3fc7eaef
SL		 2968
2969 if (addr_config == 1) {
2970 /* host supports IDMAC in 64-bit address mode */
2971 host->dma_64bit_address = 1;
2972 dev_info(host->dev,
2973 "IDMAC supports 64-bit address mode.\n");
2974 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2975 dma_set_coherent_mask(host->dev,
2976 DMA_BIT_MASK(64));
2977 } else {
2978 /* host supports IDMAC in 32-bit address mode */
2979 host->dma_64bit_address = 0;
2980 dev_info(host->dev,
2981 "IDMAC supports 32-bit address mode.\n");
2982 }
f95f3850 2983
3fc7eaef 2984 /* Alloc memory for sg translation */
cc190d4c
SL		 2985 host->sg_cpu = dmam_alloc_coherent(host->dev,
2986 DESC_RING_BUF_SZ,
3fc7eaef
SL		 2987 &host->sg_dma, GFP_KERNEL);
2988 if (!host->sg_cpu) {
2989 dev_err(host->dev,
2990 "%s: could not alloc DMA memory\n",
2991 __func__);
2992 goto no_dma;
2993 }
2994
2995 host->dma_ops = &dw_mci_idmac_ops;
2996 dev_info(host->dev, "Using internal DMA controller.\n");
2997 } else {
2998 /* TRANS_MODE_EDMAC: check dma bindings again */
852ff5fe
DW		 2999 if ((device_property_read_string_array(dev, "dma-names",
3000 NULL, 0) < 0) ||
3001 !device_property_present(dev, "dmas")) {
3fc7eaef
SL		 3002 goto no_dma;
3003 }
3004 host->dma_ops = &dw_mci_edmac_ops;
3005 dev_info(host->dev, "Using external DMA controller.\n");
3006 }
f95f3850 3007
e1631f98
JC		 3008 if (host->dma_ops->init && host->dma_ops->start &&
3009 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 3010 if (host->dma_ops->init(host)) {
0e3a22c0
SL		 3011 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
3012 __func__);
f95f3850
WN		 3013 goto no_dma;
3014 }
3015 } else {
4a90920c 3016 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 3017 goto no_dma;
3018 }
3019
f95f3850
WN		 3020 return;
3021
3022no_dma:
4a90920c 3023 dev_info(host->dev, "Using PIO mode.\n");
3fc7eaef 3024 host->use_dma = TRANS_MODE_PIO;
f95f3850
WN		 3025}
3026
37977729 3027static void dw_mci_cmd11_timer(struct timer_list *t)
5c935165 3028{
37977729 3029 struct dw_mci *host = from_timer(host, t, cmd11_timer);
5c935165 3030
fd674198
DA		 3031 if (host->state != STATE_SENDING_CMD11) {
3032 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
3033 return;
3034 }
5c935165
DA		 3035
3036 host->cmd_status = SDMMC_INT_RTO;
3037 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3038 tasklet_schedule(&host->tasklet);
3039}
3040
37977729 3041static void dw_mci_cto_timer(struct timer_list *t)
03de1921 3042{
37977729 3043 struct dw_mci *host = from_timer(host, t, cto_timer);
8892b705
DA		 3044 unsigned long irqflags;
3045 u32 pending;
03de1921 3046
8892b705 3047 spin_lock_irqsave(&host->irq_lock, irqflags);
03de1921 3048
8892b705
DA		 3049 /*
3050 * If somehow we have very bad interrupt latency it's remotely possible
3051 * that the timer could fire while the interrupt is still pending or
3052 * while the interrupt is midway through running. Let's be paranoid
3053 * and detect those two cases. Note that this is paranoia is somewhat
3054 * justified because in this function we don't actually cancel the
3055 * pending command in the controller--we just assume it will never come.
3056 */
3057 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3058 if (pending & (DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_CMD_DONE)) {
3059 /* The interrupt should fire; no need to act but we can warn */
3060 dev_warn(host->dev, "Unexpected interrupt latency\n");
3061 goto exit;
3062 }
3063 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) {
3064 /* Presumably interrupt handler couldn't delete the timer */
3065 dev_warn(host->dev, "CTO timeout when already completed\n");
3066 goto exit;
3067 }
3068
3069 /*
3070 * Continued paranoia to make sure we're in the state we expect.
3071 * This paranoia isn't really justified but it seems good to be safe.
3072 */
03de1921
AK		 3073 switch (host->state) {
3074 case STATE_SENDING_CMD11:
3075 case STATE_SENDING_CMD:
3076 case STATE_SENDING_STOP:
3077 /*
3078 * If CMD_DONE interrupt does NOT come in sending command
3079 * state, we should notify the driver to terminate current
3080 * transfer and report a command timeout to the core.
3081 */
3082 host->cmd_status = SDMMC_INT_RTO;
3083 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
3084 tasklet_schedule(&host->tasklet);
3085 break;
3086 default:
3087 dev_warn(host->dev, "Unexpected command timeout, state %d\n",
3088 host->state);
3089 break;
3090 }
8892b705
DA		 3091
3092exit:
3093 spin_unlock_irqrestore(&host->irq_lock, irqflags);
03de1921
AK		 3094}
3095
37977729 3096static void dw_mci_dto_timer(struct timer_list *t)
57e10486 3097{
37977729 3098 struct dw_mci *host = from_timer(host, t, dto_timer);
93c23ae3
DA		 3099 unsigned long irqflags;
3100 u32 pending;
3101
3102 spin_lock_irqsave(&host->irq_lock, irqflags);
57e10486 3103
93c23ae3
DA		 3104 /*
3105 * The DTO timer is much longer than the CTO timer, so it's even less
3106 * likely that we'll these cases, but it pays to be paranoid.
3107 */
3108 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
3109 if (pending & SDMMC_INT_DATA_OVER) {
3110 /* The interrupt should fire; no need to act but we can warn */
3111 dev_warn(host->dev, "Unexpected data interrupt latency\n");
3112 goto exit;
3113 }
3114 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) {
3115 /* Presumably interrupt handler couldn't delete the timer */
3116 dev_warn(host->dev, "DTO timeout when already completed\n");
3117 goto exit;
3118 }
3119
3120 /*
3121 * Continued paranoia to make sure we're in the state we expect.
3122 * This paranoia isn't really justified but it seems good to be safe.
3123 */
57e10486
AK		 3124 switch (host->state) {
3125 case STATE_SENDING_DATA:
3126 case STATE_DATA_BUSY:
3127 /*
3128 * If DTO interrupt does NOT come in sending data state,
3129 * we should notify the driver to terminate current transfer
3130 * and report a data timeout to the core.
3131 */
3132 host->data_status = SDMMC_INT_DRTO;
3133 set_bit(EVENT_DATA_ERROR, &host->pending_events);
3134 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
3135 tasklet_schedule(&host->tasklet);
3136 break;
3137 default:
93c23ae3
DA		 3138 dev_warn(host->dev, "Unexpected data timeout, state %d\n",
3139 host->state);
57e10486
AK		 3140 break;
3141 }
93c23ae3
DA		 3142
3143exit:
3144 spin_unlock_irqrestore(&host->irq_lock, irqflags);
57e10486
AK		 3145}
3146
c91eab4b 3147#ifdef CONFIG_OF
c91eab4b
TA		 3148static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3149{
3150 struct dw_mci_board *pdata;
3151 struct device *dev = host->dev;
e95baf13 3152 const struct dw_mci_drv_data *drv_data = host->drv_data;
e8cc37b8 3153 int ret;
3c6d89ea 3154 u32 clock_frequency;
c91eab4b
TA		 3155
3156 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
bf3707ea 3157 if (!pdata)
c91eab4b 3158 return ERR_PTR(-ENOMEM);
c91eab4b 3159
d6786fef 3160 /* find reset controller when exist */
a93d6f31 3161 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset");
d6786fef
GX		 3162 if (IS_ERR(pdata->rstc)) {
3163 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
3164 return ERR_PTR(-EPROBE_DEFER);
3165 }
3166
c91eab4b 3167 /* find out number of slots supported */
16f5df8b 3168 if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots))
d30a8f7b 3169 dev_info(dev, "'num-slots' was deprecated.\n");
c91eab4b 3170
852ff5fe 3171 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
0e3a22c0
SL		 3172 dev_info(dev,
3173 "fifo-depth property not found, using value of FIFOTH register as default\n");
c91eab4b 3174
852ff5fe
DW		 3175 device_property_read_u32(dev, "card-detect-delay",
3176 &pdata->detect_delay_ms);
c91eab4b 3177
852ff5fe 3178 device_property_read_u32(dev, "data-addr", &host->data_addr_override);
a0361c1a 3179
852ff5fe 3180 if (device_property_present(dev, "fifo-watermark-aligned"))
d6fced83
JN		 3181 host->wm_aligned = true;
3182
852ff5fe 3183 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
3c6d89ea
DA		 3184 pdata->bus_hz = clock_frequency;
3185
cb27a843
JH		 3186 if (drv_data && drv_data->parse_dt) {
3187 ret = drv_data->parse_dt(host);
800d78bf
TA		 3188 if (ret)
3189 return ERR_PTR(ret);
3190 }
3191
c91eab4b
TA		 3192 return pdata;
3193}
3194
3195#else /* CONFIG_OF */
3196static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
3197{
3198 return ERR_PTR(-EINVAL);
3199}
3200#endif /* CONFIG_OF */
3201
fa0c3283
DA		 3202static void dw_mci_enable_cd(struct dw_mci *host)
3203{
fa0c3283
DA		 3204 unsigned long irqflags;
3205 u32 temp;
fa0c3283 3206
e8cc37b8
SL		 3207 /*
3208 * No need for CD if all slots have a non-error GPIO
3209 * as well as broken card detection is found.
3210 */
e47c0b96 3211 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
fa0c3283
DA		 3212 return;
3213
e47c0b96 3214 if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
58870241
JC		 3215 spin_lock_irqsave(&host->irq_lock, irqflags);
3216 temp = mci_readl(host, INTMASK);
3217 temp |= SDMMC_INT_CD;
3218 mci_writel(host, INTMASK, temp);
3219 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3220 }
fa0c3283
DA		 3221}
3222
62ca8034 3223int dw_mci_probe(struct dw_mci *host)
f95f3850 3224{
e95baf13 3225 const struct dw_mci_drv_data *drv_data = host->drv_data;
62ca8034 3226 int width, i, ret = 0;
f95f3850
WN		 3227 u32 fifo_size;
3228
c91eab4b
TA		 3229 if (!host->pdata) {
3230 host->pdata = dw_mci_parse_dt(host);
d6786fef
GX		 3231 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3232 return -EPROBE_DEFER;
3233 } else if (IS_ERR(host->pdata)) {
c91eab4b
TA		 3234 dev_err(host->dev, "platform data not available\n");
3235 return -EINVAL;
3236 }
f95f3850
WN		 3237 }
3238
780f22af 3239 host->biu_clk = devm_clk_get(host->dev, "biu");
f90a0612
TA		 3240 if (IS_ERR(host->biu_clk)) {
3241 dev_dbg(host->dev, "biu clock not available\n");
3242 } else {
3243 ret = clk_prepare_enable(host->biu_clk);
3244 if (ret) {
3245 dev_err(host->dev, "failed to enable biu clock\n");
f90a0612
TA		 3246 return ret;
3247 }
3248 }
3249
780f22af 3250 host->ciu_clk = devm_clk_get(host->dev, "ciu");
f90a0612
TA		 3251 if (IS_ERR(host->ciu_clk)) {
3252 dev_dbg(host->dev, "ciu clock not available\n");
3c6d89ea 3253 host->bus_hz = host->pdata->bus_hz;
f90a0612
TA		 3254 } else {
3255 ret = clk_prepare_enable(host->ciu_clk);
3256 if (ret) {
3257 dev_err(host->dev, "failed to enable ciu clock\n");
f90a0612
TA		 3258 goto err_clk_biu;
3259 }
f90a0612 3260
3c6d89ea
DA		 3261 if (host->pdata->bus_hz) {
3262 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3263 if (ret)
3264 dev_warn(host->dev,
612de4c1 3265 "Unable to set bus rate to %uHz\n",
3c6d89ea
DA		 3266 host->pdata->bus_hz);
3267 }
f90a0612 3268 host->bus_hz = clk_get_rate(host->ciu_clk);
3c6d89ea 3269 }
f90a0612 3270
612de4c1
JC		 3271 if (!host->bus_hz) {
3272 dev_err(host->dev,
3273 "Platform data must supply bus speed\n");
3274 ret = -ENODEV;
3275 goto err_clk_ciu;
3276 }
3277
941e372d 3278 if (!IS_ERR(host->pdata->rstc)) {
3279 reset_control_assert(host->pdata->rstc);
3280 usleep_range(10, 50);
3281 reset_control_deassert(host->pdata->rstc);
3282 }
3283
002f0d5c
YK		 3284 if (drv_data && drv_data->init) {
3285 ret = drv_data->init(host);
3286 if (ret) {
3287 dev_err(host->dev,
3288 "implementation specific init failed\n");
3289 goto err_clk_ciu;
3290 }
3291 }
3292
37977729
KC		 3293 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0);
3294 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0);
3295 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0);
57e10486 3296
f95f3850 3297 spin_lock_init(&host->lock);
f8c58c11 3298 spin_lock_init(&host->irq_lock);
f95f3850
WN		 3299 INIT_LIST_HEAD(&host->queue);
3300
f95f3850
WN		 3301 /*
3302 * Get the host data width - this assumes that HCON has been set with
3303 * the correct values.
3304 */
70692752 3305 i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
f95f3850
WN		 3306 if (!i) {
3307 host->push_data = dw_mci_push_data16;
3308 host->pull_data = dw_mci_pull_data16;
3309 width = 16;
3310 host->data_shift = 1;
3311 } else if (i == 2) {
3312 host->push_data = dw_mci_push_data64;
3313 host->pull_data = dw_mci_pull_data64;
3314 width = 64;
3315 host->data_shift = 3;
3316 } else {
3317 /* Check for a reserved value, and warn if it is */
3318 WARN((i != 1),
3319 "HCON reports a reserved host data width!\n"
3320 "Defaulting to 32-bit access.\n");
3321 host->push_data = dw_mci_push_data32;
3322 host->pull_data = dw_mci_pull_data32;
3323 width = 32;
3324 host->data_shift = 2;
3325 }
3326
3327 /* Reset all blocks */
3744415c
SL		 3328 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3329 ret = -ENODEV;
3330 goto err_clk_ciu;
3331 }
141a712a
SJ		 3332
3333 host->dma_ops = host->pdata->dma_ops;
3334 dw_mci_init_dma(host);
f95f3850
WN		 3335
3336 /* Clear the interrupts for the host controller */
3337 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3338 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3339
3340 /* Put in max timeout */
3341 mci_writel(host, TMOUT, 0xFFFFFFFF);
3342
3343 /*
3344 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
3345 * Tx Mark = fifo_size / 2 DMA Size = 8
3346 */
b86d8253
JH		 3347 if (!host->pdata->fifo_depth) {
3348 /*
3349 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3350 * have been overwritten by the bootloader, just like we're
3351 * about to do, so if you know the value for your hardware, you
3352 * should put it in the platform data.
3353 */
3354 fifo_size = mci_readl(host, FIFOTH);
8234e869 3355 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 3356 } else {
3357 fifo_size = host->pdata->fifo_depth;
3358 }
3359 host->fifo_depth = fifo_size;
52426899
SJ		 3360 host->fifoth_val =
3361 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
e61cf118 3362 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 3363
3364 /* disable clock to CIU */
3365 mci_writel(host, CLKENA, 0);
3366 mci_writel(host, CLKSRC, 0);
3367
63008768
JH		 3368 /*
3369 * In 2.40a spec, Data offset is changed.
3370 * Need to check the version-id and set data-offset for DATA register.
3371 */
3372 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3373 dev_info(host->dev, "Version ID is %04x\n", host->verid);
3374
a0361c1a
JN		 3375 if (host->data_addr_override)
3376 host->fifo_reg = host->regs + host->data_addr_override;
3377 else if (host->verid < DW_MMC_240A)
76184ac1 3378 host->fifo_reg = host->regs + DATA_OFFSET;
63008768 3379 else
76184ac1 3380 host->fifo_reg = host->regs + DATA_240A_OFFSET;
63008768 3381
f95f3850 3382 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
780f22af
SJ		 3383 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3384 host->irq_flags, "dw-mci", host);
f95f3850 3385 if (ret)
6130e7a9 3386 goto err_dmaunmap;
f95f3850 3387
2da1d7f2 3388 /*
fa0c3283 3389 * Enable interrupts for command done, data over, data empty,
2da1d7f2
YC		 3390 * receive ready and error such as transmit, receive timeout, crc error
3391 */
2da1d7f2
YC		 3392 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3393 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3394 DW_MCI_ERROR_FLAGS);
0e3a22c0
SL		 3395 /* Enable mci interrupt */
3396 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2da1d7f2 3397
0e3a22c0
SL		 3398 dev_info(host->dev,
3399 "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
2da1d7f2
YC		 3400 host->irq, width, fifo_size);
3401
f95f3850 3402 /* We need at least one slot to succeed */
e4a65ef7 3403 ret = dw_mci_init_slot(host);
58870241
JC		 3404 if (ret) {
3405 dev_dbg(host->dev, "slot %d init failed\n", i);
6130e7a9 3406 goto err_dmaunmap;
f95f3850
WN		 3407 }
3408
b793f658
DA		 3409 /* Now that slots are all setup, we can enable card detect */
3410 dw_mci_enable_cd(host);
3411
f95f3850
WN		 3412 return 0;
3413
f95f3850
WN		 3414err_dmaunmap:
3415 if (host->use_dma && host->dma_ops->exit)
3416 host->dma_ops->exit(host);
f90a0612 3417
d6786fef
GX		 3418 if (!IS_ERR(host->pdata->rstc))
3419 reset_control_assert(host->pdata->rstc);
3420
f90a0612 3421err_clk_ciu:
7037f3be 3422 clk_disable_unprepare(host->ciu_clk);
780f22af 3423
f90a0612 3424err_clk_biu:
7037f3be 3425 clk_disable_unprepare(host->biu_clk);
780f22af 3426
f95f3850
WN		 3427 return ret;
3428}
62ca8034 3429EXPORT_SYMBOL(dw_mci_probe);
f95f3850 3430
62ca8034 3431void dw_mci_remove(struct dw_mci *host)
f95f3850 3432{
e4a65ef7 3433 dev_dbg(host->dev, "remove slot\n");
b23475fa 3434 if (host->slot)
e4a65ef7 3435 dw_mci_cleanup_slot(host->slot);
f95f3850 3436
048fd7e6
PT		 3437 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3438 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3439
f95f3850
WN		 3440 /* disable clock to CIU */
3441 mci_writel(host, CLKENA, 0);
3442 mci_writel(host, CLKSRC, 0);
3443
f95f3850
WN		 3444 if (host->use_dma && host->dma_ops->exit)
3445 host->dma_ops->exit(host);
3446
d6786fef
GX		 3447 if (!IS_ERR(host->pdata->rstc))
3448 reset_control_assert(host->pdata->rstc);
3449
7037f3be
JC		 3450 clk_disable_unprepare(host->ciu_clk);
3451 clk_disable_unprepare(host->biu_clk);
f95f3850 3452}
62ca8034
SH		 3453EXPORT_SYMBOL(dw_mci_remove);
3454
3455
f95f3850 3456
e9ed8835 3457#ifdef CONFIG_PM
ed24e1ff 3458int dw_mci_runtime_suspend(struct device *dev)
f95f3850 3459{
ed24e1ff
SL		 3460 struct dw_mci *host = dev_get_drvdata(dev);
3461
3fc7eaef
SL		 3462 if (host->use_dma && host->dma_ops->exit)
3463 host->dma_ops->exit(host);
3464
ed24e1ff
SL		 3465 clk_disable_unprepare(host->ciu_clk);
3466
42f989c0
JC		 3467 if (host->slot &&
3468 (mmc_can_gpio_cd(host->slot->mmc) ||
3469 !mmc_card_is_removable(host->slot->mmc)))
ed24e1ff
SL		 3470 clk_disable_unprepare(host->biu_clk);
3471
f95f3850
WN		 3472 return 0;
3473}
ed24e1ff 3474EXPORT_SYMBOL(dw_mci_runtime_suspend);
f95f3850 3475
ed24e1ff 3476int dw_mci_runtime_resume(struct device *dev)
f95f3850 3477{
b23475fa 3478 int ret = 0;
ed24e1ff 3479 struct dw_mci *host = dev_get_drvdata(dev);
f95f3850 3480
42f989c0
JC		 3481 if (host->slot &&
3482 (mmc_can_gpio_cd(host->slot->mmc) ||
3483 !mmc_card_is_removable(host->slot->mmc))) {
ed24e1ff
SL		 3484 ret = clk_prepare_enable(host->biu_clk);
3485 if (ret)
3486 return ret;
e61cf118
JC		 3487 }
3488
ed24e1ff
SL		 3489 ret = clk_prepare_enable(host->ciu_clk);
3490 if (ret)
df9bcc2b
JS		 3491 goto err;
3492
3493 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3494 clk_disable_unprepare(host->ciu_clk);
3495 ret = -ENODEV;
3496 goto err;
3497 }
ed24e1ff 3498
3bfe619d 3499 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 3500 host->dma_ops->init(host);
3501
52426899
SJ		 3502 /*
3503 * Restore the initial value at FIFOTH register
3504 * And Invalidate the prev_blksz with zero
3505 */
ed24e1ff
SL		 3506 mci_writel(host, FIFOTH, host->fifoth_val);
3507 host->prev_blksz = 0;
e61cf118 3508
2eb2944f
DA		 3509 /* Put in max timeout */
3510 mci_writel(host, TMOUT, 0xFFFFFFFF);
3511
e61cf118
JC		 3512 mci_writel(host, RINTSTS, 0xFFFFFFFF);
3513 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3514 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
fa0c3283 3515 DW_MCI_ERROR_FLAGS);
e61cf118
JC		 3516 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3517
0e3a22c0 3518
e47c0b96
JC		 3519 if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3520 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
e9748e03 3521
58870241 3522 /* Force setup bus to guarantee available clock output */
e47c0b96 3523 dw_mci_setup_bus(host->slot, true);
fa0c3283
DA		 3524
3525 /* Now that slots are all setup, we can enable card detect */
3526 dw_mci_enable_cd(host);
3527
df9bcc2b
JS		 3528 return 0;
3529
3530err:
42f989c0
JC		 3531 if (host->slot &&
3532 (mmc_can_gpio_cd(host->slot->mmc) ||
3533 !mmc_card_is_removable(host->slot->mmc)))
df9bcc2b
JS		 3534 clk_disable_unprepare(host->biu_clk);
3535
ed24e1ff 3536 return ret;
e9ed8835
SL		 3537}
3538EXPORT_SYMBOL(dw_mci_runtime_resume);
3539#endif /* CONFIG_PM */
6fe8890d 3540
f95f3850
WN		 3541static int __init dw_mci_init(void)
3542{
8e1c4e4d 3543 pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
62ca8034 3544 return 0;
f95f3850
WN		 3545}
3546
3547static void __exit dw_mci_exit(void)
3548{
f95f3850
WN		 3549}
3550
3551module_init(dw_mci_init);
3552module_exit(dw_mci_exit);
3553
3554MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3555MODULE_AUTHOR("NXP Semiconductor VietNam");
3556MODULE_AUTHOR("Imagination Technologies Ltd");
3557MODULE_LICENSE("GPL v2");
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