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mmc: dw_mmc: lookup for optional biu and ciu clocks
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / dw_mmc.c
CommitLineData
f95f3850
WN		 1/*
2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
4 *
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/blkdev.h>
15#include <linux/clk.h>
16#include <linux/debugfs.h>
17#include <linux/device.h>
18#include <linux/dma-mapping.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/ioport.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
f95f3850
WN		 25#include <linux/seq_file.h>
26#include <linux/slab.h>
27#include <linux/stat.h>
28#include <linux/delay.h>
29#include <linux/irq.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
32#include <linux/mmc/dw_mmc.h>
33#include <linux/bitops.h>
c07946a3 34#include <linux/regulator/consumer.h>
1791b13e 35#include <linux/workqueue.h>
f95f3850
WN		 36
37#include "dw_mmc.h"
38
39/* Common flag combinations */
40#define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DTO | SDMMC_INT_DCRC | \
41 SDMMC_INT_HTO | SDMMC_INT_SBE | \
42 SDMMC_INT_EBE)
43#define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
44 SDMMC_INT_RESP_ERR)
45#define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
46 DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
47#define DW_MCI_SEND_STATUS 1
48#define DW_MCI_RECV_STATUS 2
49#define DW_MCI_DMA_THRESHOLD 16
50
51#ifdef CONFIG_MMC_DW_IDMAC
52struct idmac_desc {
53 u32 des0; /* Control Descriptor */
54#define IDMAC_DES0_DIC BIT(1)
55#define IDMAC_DES0_LD BIT(2)
56#define IDMAC_DES0_FD BIT(3)
57#define IDMAC_DES0_CH BIT(4)
58#define IDMAC_DES0_ER BIT(5)
59#define IDMAC_DES0_CES BIT(30)
60#define IDMAC_DES0_OWN BIT(31)
61
62 u32 des1; /* Buffer sizes */
63#define IDMAC_SET_BUFFER1_SIZE(d, s) \
9b7bbe10 64 ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
f95f3850
WN		 65
66 u32 des2; /* buffer 1 physical address */
67
68 u32 des3; /* buffer 2 physical address */
69};
70#endif /* CONFIG_MMC_DW_IDMAC */
71
72/**
73 * struct dw_mci_slot - MMC slot state
74 * @mmc: The mmc_host representing this slot.
75 * @host: The MMC controller this slot is using.
76 * @ctype: Card type for this slot.
77 * @mrq: mmc_request currently being processed or waiting to be
78 * processed, or NULL when the slot is idle.
79 * @queue_node: List node for placing this node in the @queue list of
80 * &struct dw_mci.
81 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
82 * @flags: Random state bits associated with the slot.
83 * @id: Number of this slot.
84 * @last_detect_state: Most recently observed card detect state.
85 */
86struct dw_mci_slot {
87 struct mmc_host *mmc;
88 struct dw_mci *host;
89
90 u32 ctype;
91
92 struct mmc_request *mrq;
93 struct list_head queue_node;
94
95 unsigned int clock;
96 unsigned long flags;
97#define DW_MMC_CARD_PRESENT 0
98#define DW_MMC_CARD_NEED_INIT 1
99 int id;
100 int last_detect_state;
101};
102
103#if defined(CONFIG_DEBUG_FS)
104static int dw_mci_req_show(struct seq_file *s, void *v)
105{
106 struct dw_mci_slot *slot = s->private;
107 struct mmc_request *mrq;
108 struct mmc_command *cmd;
109 struct mmc_command *stop;
110 struct mmc_data *data;
111
112 /* Make sure we get a consistent snapshot */
113 spin_lock_bh(&slot->host->lock);
114 mrq = slot->mrq;
115
116 if (mrq) {
117 cmd = mrq->cmd;
118 data = mrq->data;
119 stop = mrq->stop;
120
121 if (cmd)
122 seq_printf(s,
123 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
124 cmd->opcode, cmd->arg, cmd->flags,
125 cmd->resp[0], cmd->resp[1], cmd->resp[2],
126 cmd->resp[2], cmd->error);
127 if (data)
128 seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
129 data->bytes_xfered, data->blocks,
130 data->blksz, data->flags, data->error);
131 if (stop)
132 seq_printf(s,
133 "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
134 stop->opcode, stop->arg, stop->flags,
135 stop->resp[0], stop->resp[1], stop->resp[2],
136 stop->resp[2], stop->error);
137 }
138
139 spin_unlock_bh(&slot->host->lock);
140
141 return 0;
142}
143
144static int dw_mci_req_open(struct inode *inode, struct file *file)
145{
146 return single_open(file, dw_mci_req_show, inode->i_private);
147}
148
149static const struct file_operations dw_mci_req_fops = {
150 .owner = THIS_MODULE,
151 .open = dw_mci_req_open,
152 .read = seq_read,
153 .llseek = seq_lseek,
154 .release = single_release,
155};
156
157static int dw_mci_regs_show(struct seq_file *s, void *v)
158{
159 seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
160 seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
161 seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
162 seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
163 seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
164 seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
165
166 return 0;
167}
168
169static int dw_mci_regs_open(struct inode *inode, struct file *file)
170{
171 return single_open(file, dw_mci_regs_show, inode->i_private);
172}
173
174static const struct file_operations dw_mci_regs_fops = {
175 .owner = THIS_MODULE,
176 .open = dw_mci_regs_open,
177 .read = seq_read,
178 .llseek = seq_lseek,
179 .release = single_release,
180};
181
182static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
183{
184 struct mmc_host *mmc = slot->mmc;
185 struct dw_mci *host = slot->host;
186 struct dentry *root;
187 struct dentry *node;
188
189 root = mmc->debugfs_root;
190 if (!root)
191 return;
192
193 node = debugfs_create_file("regs", S_IRUSR, root, host,
194 &dw_mci_regs_fops);
195 if (!node)
196 goto err;
197
198 node = debugfs_create_file("req", S_IRUSR, root, slot,
199 &dw_mci_req_fops);
200 if (!node)
201 goto err;
202
203 node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
204 if (!node)
205 goto err;
206
207 node = debugfs_create_x32("pending_events", S_IRUSR, root,
208 (u32 *)&host->pending_events);
209 if (!node)
210 goto err;
211
212 node = debugfs_create_x32("completed_events", S_IRUSR, root,
213 (u32 *)&host->completed_events);
214 if (!node)
215 goto err;
216
217 return;
218
219err:
220 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
221}
222#endif /* defined(CONFIG_DEBUG_FS) */
223
224static void dw_mci_set_timeout(struct dw_mci *host)
225{
226 /* timeout (maximum) */
227 mci_writel(host, TMOUT, 0xffffffff);
228}
229
230static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
231{
232 struct mmc_data *data;
233 u32 cmdr;
234 cmd->error = -EINPROGRESS;
235
236 cmdr = cmd->opcode;
237
238 if (cmdr == MMC_STOP_TRANSMISSION)
239 cmdr |= SDMMC_CMD_STOP;
240 else
241 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
242
243 if (cmd->flags & MMC_RSP_PRESENT) {
244 /* We expect a response, so set this bit */
245 cmdr |= SDMMC_CMD_RESP_EXP;
246 if (cmd->flags & MMC_RSP_136)
247 cmdr |= SDMMC_CMD_RESP_LONG;
248 }
249
250 if (cmd->flags & MMC_RSP_CRC)
251 cmdr |= SDMMC_CMD_RESP_CRC;
252
253 data = cmd->data;
254 if (data) {
255 cmdr |= SDMMC_CMD_DAT_EXP;
256 if (data->flags & MMC_DATA_STREAM)
257 cmdr |= SDMMC_CMD_STRM_MODE;
258 if (data->flags & MMC_DATA_WRITE)
259 cmdr |= SDMMC_CMD_DAT_WR;
260 }
261
262 return cmdr;
263}
264
265static void dw_mci_start_command(struct dw_mci *host,
266 struct mmc_command *cmd, u32 cmd_flags)
267{
268 host->cmd = cmd;
4a90920c 269 dev_vdbg(host->dev,
f95f3850
WN		 270 "start command: ARGR=0x%08x CMDR=0x%08x\n",
271 cmd->arg, cmd_flags);
272
273 mci_writel(host, CMDARG, cmd->arg);
274 wmb();
275
276 mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
277}
278
279static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
280{
281 dw_mci_start_command(host, data->stop, host->stop_cmdr);
282}
283
284/* DMA interface functions */
285static void dw_mci_stop_dma(struct dw_mci *host)
286{
03e8cb53 287 if (host->using_dma) {
f95f3850
WN		 288 host->dma_ops->stop(host);
289 host->dma_ops->cleanup(host);
290 } else {
291 /* Data transfer was stopped by the interrupt handler */
292 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
293 }
294}
295
9aa51408
SJ		 296static int dw_mci_get_dma_dir(struct mmc_data *data)
297{
298 if (data->flags & MMC_DATA_WRITE)
299 return DMA_TO_DEVICE;
300 else
301 return DMA_FROM_DEVICE;
302}
303
9beee912 304#ifdef CONFIG_MMC_DW_IDMAC
f95f3850
WN		 305static void dw_mci_dma_cleanup(struct dw_mci *host)
306{
307 struct mmc_data *data = host->data;
308
309 if (data)
9aa51408 310 if (!data->host_cookie)
4a90920c 311 dma_unmap_sg(host->dev,
9aa51408
SJ		 312 data->sg,
313 data->sg_len,
314 dw_mci_get_dma_dir(data));
f95f3850
WN		 315}
316
317static void dw_mci_idmac_stop_dma(struct dw_mci *host)
318{
319 u32 temp;
320
321 /* Disable and reset the IDMAC interface */
322 temp = mci_readl(host, CTRL);
323 temp &= ~SDMMC_CTRL_USE_IDMAC;
324 temp |= SDMMC_CTRL_DMA_RESET;
325 mci_writel(host, CTRL, temp);
326
327 /* Stop the IDMAC running */
328 temp = mci_readl(host, BMOD);
a5289a43 329 temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
f95f3850
WN		 330 mci_writel(host, BMOD, temp);
331}
332
333static void dw_mci_idmac_complete_dma(struct dw_mci *host)
334{
335 struct mmc_data *data = host->data;
336
4a90920c 337 dev_vdbg(host->dev, "DMA complete\n");
f95f3850
WN		 338
339 host->dma_ops->cleanup(host);
340
341 /*
342 * If the card was removed, data will be NULL. No point in trying to
343 * send the stop command or waiting for NBUSY in this case.
344 */
345 if (data) {
346 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
347 tasklet_schedule(&host->tasklet);
348 }
349}
350
351static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
352 unsigned int sg_len)
353{
354 int i;
355 struct idmac_desc *desc = host->sg_cpu;
356
357 for (i = 0; i < sg_len; i++, desc++) {
358 unsigned int length = sg_dma_len(&data->sg[i]);
359 u32 mem_addr = sg_dma_address(&data->sg[i]);
360
361 /* Set the OWN bit and disable interrupts for this descriptor */
362 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
363
364 /* Buffer length */
365 IDMAC_SET_BUFFER1_SIZE(desc, length);
366
367 /* Physical address to DMA to/from */
368 desc->des2 = mem_addr;
369 }
370
371 /* Set first descriptor */
372 desc = host->sg_cpu;
373 desc->des0 |= IDMAC_DES0_FD;
374
375 /* Set last descriptor */
376 desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
377 desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
378 desc->des0 |= IDMAC_DES0_LD;
379
380 wmb();
381}
382
383static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
384{
385 u32 temp;
386
387 dw_mci_translate_sglist(host, host->data, sg_len);
388
389 /* Select IDMAC interface */
390 temp = mci_readl(host, CTRL);
391 temp |= SDMMC_CTRL_USE_IDMAC;
392 mci_writel(host, CTRL, temp);
393
394 wmb();
395
396 /* Enable the IDMAC */
397 temp = mci_readl(host, BMOD);
a5289a43 398 temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
f95f3850
WN		 399 mci_writel(host, BMOD, temp);
400
401 /* Start it running */
402 mci_writel(host, PLDMND, 1);
403}
404
405static int dw_mci_idmac_init(struct dw_mci *host)
406{
407 struct idmac_desc *p;
94c6cee9 408 int i, dma_support;
f95f3850
WN		 409
410 /* Number of descriptors in the ring buffer */
411 host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
412
94c6cee9
G		 413 /* Check if Hardware Configuration Register has support for DMA */
414 dma_support = (mci_readl(host, HCON) >> 16) & 0x3;
415
416 if (!dma_support || dma_support > 2) {
4a90920c 417 dev_err(host->dev,
94c6cee9
G		 418 "Host Controller does not support IDMA Tx.\n");
419 host->dma_ops = NULL;
420 return -ENODEV;
421 }
422
4a90920c 423 dev_info(host->dev, "Using internal DMA controller.\n");
94c6cee9 424
f95f3850
WN		 425 /* Forward link the descriptor list */
426 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
427 p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
428
429 /* Set the last descriptor as the end-of-ring descriptor */
430 p->des3 = host->sg_dma;
431 p->des0 = IDMAC_DES0_ER;
432
141a712a
SJ		 433 mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
434
f95f3850
WN		 435 /* Mask out interrupts - get Tx & Rx complete only */
436 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
437 SDMMC_IDMAC_INT_TI);
438
439 /* Set the descriptor base address */
440 mci_writel(host, DBADDR, host->sg_dma);
441 return 0;
442}
443
885c3e80
SJ		 444static struct dw_mci_dma_ops dw_mci_idmac_ops = {
445 .init = dw_mci_idmac_init,
446 .start = dw_mci_idmac_start_dma,
447 .stop = dw_mci_idmac_stop_dma,
448 .complete = dw_mci_idmac_complete_dma,
449 .cleanup = dw_mci_dma_cleanup,
450};
451#endif /* CONFIG_MMC_DW_IDMAC */
452
9aa51408
SJ		 453static int dw_mci_pre_dma_transfer(struct dw_mci *host,
454 struct mmc_data *data,
455 bool next)
f95f3850
WN		 456{
457 struct scatterlist *sg;
9aa51408 458 unsigned int i, sg_len;
03e8cb53 459
9aa51408
SJ		 460 if (!next && data->host_cookie)
461 return data->host_cookie;
f95f3850
WN		 462
463 /*
464 * We don't do DMA on "complex" transfers, i.e. with
465 * non-word-aligned buffers or lengths. Also, we don't bother
466 * with all the DMA setup overhead for short transfers.
467 */
468 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
469 return -EINVAL;
9aa51408 470
f95f3850
WN		 471 if (data->blksz & 3)
472 return -EINVAL;
473
474 for_each_sg(data->sg, sg, data->sg_len, i) {
475 if (sg->offset & 3 || sg->length & 3)
476 return -EINVAL;
477 }
478
4a90920c 479 sg_len = dma_map_sg(host->dev,
9aa51408
SJ		 480 data->sg,
481 data->sg_len,
482 dw_mci_get_dma_dir(data));
483 if (sg_len == 0)
484 return -EINVAL;
03e8cb53 485
9aa51408
SJ		 486 if (next)
487 data->host_cookie = sg_len;
f95f3850 488
9aa51408
SJ		 489 return sg_len;
490}
491
9aa51408
SJ		 492static void dw_mci_pre_req(struct mmc_host *mmc,
493 struct mmc_request *mrq,
494 bool is_first_req)
495{
496 struct dw_mci_slot *slot = mmc_priv(mmc);
497 struct mmc_data *data = mrq->data;
498
499 if (!slot->host->use_dma || !data)
500 return;
501
502 if (data->host_cookie) {
503 data->host_cookie = 0;
504 return;
505 }
506
507 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
508 data->host_cookie = 0;
509}
510
511static void dw_mci_post_req(struct mmc_host *mmc,
512 struct mmc_request *mrq,
513 int err)
514{
515 struct dw_mci_slot *slot = mmc_priv(mmc);
516 struct mmc_data *data = mrq->data;
517
518 if (!slot->host->use_dma || !data)
519 return;
520
521 if (data->host_cookie)
4a90920c 522 dma_unmap_sg(slot->host->dev,
9aa51408
SJ		 523 data->sg,
524 data->sg_len,
525 dw_mci_get_dma_dir(data));
526 data->host_cookie = 0;
527}
528
529static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
530{
531 int sg_len;
532 u32 temp;
533
534 host->using_dma = 0;
535
536 /* If we don't have a channel, we can't do DMA */
537 if (!host->use_dma)
538 return -ENODEV;
539
540 sg_len = dw_mci_pre_dma_transfer(host, data, 0);
a99aa9b9
SJ		 541 if (sg_len < 0) {
542 host->dma_ops->stop(host);
9aa51408 543 return sg_len;
a99aa9b9 544 }
9aa51408
SJ		 545
546 host->using_dma = 1;
f95f3850 547
4a90920c 548 dev_vdbg(host->dev,
f95f3850
WN		 549 "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
550 (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
551 sg_len);
552
553 /* Enable the DMA interface */
554 temp = mci_readl(host, CTRL);
555 temp |= SDMMC_CTRL_DMA_ENABLE;
556 mci_writel(host, CTRL, temp);
557
558 /* Disable RX/TX IRQs, let DMA handle it */
559 temp = mci_readl(host, INTMASK);
560 temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
561 mci_writel(host, INTMASK, temp);
562
563 host->dma_ops->start(host, sg_len);
564
565 return 0;
566}
567
568static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
569{
570 u32 temp;
571
572 data->error = -EINPROGRESS;
573
574 WARN_ON(host->data);
575 host->sg = NULL;
576 host->data = data;
577
55c5efbc
JH		 578 if (data->flags & MMC_DATA_READ)
579 host->dir_status = DW_MCI_RECV_STATUS;
580 else
581 host->dir_status = DW_MCI_SEND_STATUS;
582
f95f3850 583 if (dw_mci_submit_data_dma(host, data)) {
f9c2a0dc
SJ		 584 int flags = SG_MITER_ATOMIC;
585 if (host->data->flags & MMC_DATA_READ)
586 flags |= SG_MITER_TO_SG;
587 else
588 flags |= SG_MITER_FROM_SG;
589
590 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
f95f3850 591 host->sg = data->sg;
34b664a2
JH		 592 host->part_buf_start = 0;
593 host->part_buf_count = 0;
f95f3850 594
b40af3aa 595 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
f95f3850
WN		 596 temp = mci_readl(host, INTMASK);
597 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
598 mci_writel(host, INTMASK, temp);
599
600 temp = mci_readl(host, CTRL);
601 temp &= ~SDMMC_CTRL_DMA_ENABLE;
602 mci_writel(host, CTRL, temp);
603 }
604}
605
606static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
607{
608 struct dw_mci *host = slot->host;
609 unsigned long timeout = jiffies + msecs_to_jiffies(500);
610 unsigned int cmd_status = 0;
611
612 mci_writel(host, CMDARG, arg);
613 wmb();
614 mci_writel(host, CMD, SDMMC_CMD_START | cmd);
615
616 while (time_before(jiffies, timeout)) {
617 cmd_status = mci_readl(host, CMD);
618 if (!(cmd_status & SDMMC_CMD_START))
619 return;
620 }
621 dev_err(&slot->mmc->class_dev,
622 "Timeout sending command (cmd %#x arg %#x status %#x)\n",
623 cmd, arg, cmd_status);
624}
625
626static void dw_mci_setup_bus(struct dw_mci_slot *slot)
627{
628 struct dw_mci *host = slot->host;
629 u32 div;
9623b5b9 630 u32 clk_en_a;
f95f3850
WN		 631
632 if (slot->clock != host->current_speed) {
e419990b
SJ		 633 div = host->bus_hz / slot->clock;
634 if (host->bus_hz % slot->clock && host->bus_hz > slot->clock)
f95f3850
WN		 635 /*
636 * move the + 1 after the divide to prevent
637 * over-clocking the card.
638 */
e419990b
SJ		 639 div += 1;
640
641 div = (host->bus_hz != slot->clock) ? DIV_ROUND_UP(div, 2) : 0;
f95f3850
WN		 642
643 dev_info(&slot->mmc->class_dev,
644 "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ"
645 " div = %d)\n", slot->id, host->bus_hz, slot->clock,
646 div ? ((host->bus_hz / div) >> 1) : host->bus_hz, div);
647
648 /* disable clock */
649 mci_writel(host, CLKENA, 0);
650 mci_writel(host, CLKSRC, 0);
651
652 /* inform CIU */
653 mci_send_cmd(slot,
654 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
655
656 /* set clock to desired speed */
657 mci_writel(host, CLKDIV, div);
658
659 /* inform CIU */
660 mci_send_cmd(slot,
661 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
662
9623b5b9
DA		 663 /* enable clock; only low power if no SDIO */
664 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
665 if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
666 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
667 mci_writel(host, CLKENA, clk_en_a);
f95f3850
WN		 668
669 /* inform CIU */
670 mci_send_cmd(slot,
671 SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
672
673 host->current_speed = slot->clock;
674 }
675
676 /* Set the current slot bus width */
1d56c453 677 mci_writel(host, CTYPE, (slot->ctype << slot->id));
f95f3850
WN		 678}
679
053b3ce6
SJ		 680static void __dw_mci_start_request(struct dw_mci *host,
681 struct dw_mci_slot *slot,
682 struct mmc_command *cmd)
f95f3850
WN		 683{
684 struct mmc_request *mrq;
f95f3850
WN		 685 struct mmc_data *data;
686 u32 cmdflags;
687
688 mrq = slot->mrq;
689 if (host->pdata->select_slot)
690 host->pdata->select_slot(slot->id);
691
692 /* Slot specific timing and width adjustment */
693 dw_mci_setup_bus(slot);
694
695 host->cur_slot = slot;
696 host->mrq = mrq;
697
698 host->pending_events = 0;
699 host->completed_events = 0;
700 host->data_status = 0;
701
053b3ce6 702 data = cmd->data;
f95f3850
WN		 703 if (data) {
704 dw_mci_set_timeout(host);
705 mci_writel(host, BYTCNT, data->blksz*data->blocks);
706 mci_writel(host, BLKSIZ, data->blksz);
707 }
708
f95f3850
WN		 709 cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
710
711 /* this is the first command, send the initialization clock */
712 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
713 cmdflags |= SDMMC_CMD_INIT;
714
715 if (data) {
716 dw_mci_submit_data(host, data);
717 wmb();
718 }
719
720 dw_mci_start_command(host, cmd, cmdflags);
721
722 if (mrq->stop)
723 host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
724}
725
053b3ce6
SJ		 726static void dw_mci_start_request(struct dw_mci *host,
727 struct dw_mci_slot *slot)
728{
729 struct mmc_request *mrq = slot->mrq;
730 struct mmc_command *cmd;
731
732 cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
733 __dw_mci_start_request(host, slot, cmd);
734}
735
7456caae 736/* must be called with host->lock held */
f95f3850
WN		 737static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
738 struct mmc_request *mrq)
739{
740 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
741 host->state);
742
f95f3850
WN		 743 slot->mrq = mrq;
744
745 if (host->state == STATE_IDLE) {
746 host->state = STATE_SENDING_CMD;
747 dw_mci_start_request(host, slot);
748 } else {
749 list_add_tail(&slot->queue_node, &host->queue);
750 }
f95f3850
WN		 751}
752
753static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
754{
755 struct dw_mci_slot *slot = mmc_priv(mmc);
756 struct dw_mci *host = slot->host;
757
758 WARN_ON(slot->mrq);
759
7456caae
JH		 760 /*
761 * The check for card presence and queueing of the request must be
762 * atomic, otherwise the card could be removed in between and the
763 * request wouldn't fail until another card was inserted.
764 */
765 spin_lock_bh(&host->lock);
766
f95f3850 767 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
7456caae 768 spin_unlock_bh(&host->lock);
f95f3850
WN		 769 mrq->cmd->error = -ENOMEDIUM;
770 mmc_request_done(mmc, mrq);
771 return;
772 }
773
f95f3850 774 dw_mci_queue_request(host, slot, mrq);
7456caae
JH		 775
776 spin_unlock_bh(&host->lock);
f95f3850
WN		 777}
778
779static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
780{
781 struct dw_mci_slot *slot = mmc_priv(mmc);
41babf75 782 u32 regs;
f95f3850
WN		 783
784 /* set default 1 bit mode */
785 slot->ctype = SDMMC_CTYPE_1BIT;
786
787 switch (ios->bus_width) {
788 case MMC_BUS_WIDTH_1:
789 slot->ctype = SDMMC_CTYPE_1BIT;
790 break;
791 case MMC_BUS_WIDTH_4:
792 slot->ctype = SDMMC_CTYPE_4BIT;
793 break;
c9b2a06f
JC		 794 case MMC_BUS_WIDTH_8:
795 slot->ctype = SDMMC_CTYPE_8BIT;
796 break;
f95f3850
WN		 797 }
798
3f514291
SJ		 799 regs = mci_readl(slot->host, UHS_REG);
800
41babf75 801 /* DDR mode set */
3f514291 802 if (ios->timing == MMC_TIMING_UHS_DDR50)
41babf75 803 regs |= (0x1 << slot->id) << 16;
3f514291
SJ		 804 else
805 regs &= ~(0x1 << slot->id) << 16;
806
807 mci_writel(slot->host, UHS_REG, regs);
41babf75 808
f95f3850
WN		 809 if (ios->clock) {
810 /*
811 * Use mirror of ios->clock to prevent race with mmc
812 * core ios update when finding the minimum.
813 */
814 slot->clock = ios->clock;
815 }
816
817 switch (ios->power_mode) {
818 case MMC_POWER_UP:
819 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
820 break;
821 default:
822 break;
823 }
824}
825
826static int dw_mci_get_ro(struct mmc_host *mmc)
827{
828 int read_only;
829 struct dw_mci_slot *slot = mmc_priv(mmc);
830 struct dw_mci_board *brd = slot->host->pdata;
831
832 /* Use platform get_ro function, else try on board write protect */
833 if (brd->get_ro)
834 read_only = brd->get_ro(slot->id);
835 else
836 read_only =
837 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
838
839 dev_dbg(&mmc->class_dev, "card is %s\n",
840 read_only ? "read-only" : "read-write");
841
842 return read_only;
843}
844
845static int dw_mci_get_cd(struct mmc_host *mmc)
846{
847 int present;
848 struct dw_mci_slot *slot = mmc_priv(mmc);
849 struct dw_mci_board *brd = slot->host->pdata;
850
851 /* Use platform get_cd function, else try onboard card detect */
fc3d7720
JC		 852 if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
853 present = 1;
854 else if (brd->get_cd)
f95f3850
WN		 855 present = !brd->get_cd(slot->id);
856 else
857 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
858 == 0 ? 1 : 0;
859
860 if (present)
861 dev_dbg(&mmc->class_dev, "card is present\n");
862 else
863 dev_dbg(&mmc->class_dev, "card is not present\n");
864
865 return present;
866}
867
9623b5b9
DA		 868/*
869 * Disable lower power mode.
870 *
871 * Low power mode will stop the card clock when idle. According to the
872 * description of the CLKENA register we should disable low power mode
873 * for SDIO cards if we need SDIO interrupts to work.
874 *
875 * This function is fast if low power mode is already disabled.
876 */
877static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
878{
879 struct dw_mci *host = slot->host;
880 u32 clk_en_a;
881 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
882
883 clk_en_a = mci_readl(host, CLKENA);
884
885 if (clk_en_a & clken_low_pwr) {
886 mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
887 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
888 SDMMC_CMD_PRV_DAT_WAIT, 0);
889 }
890}
891
1a5c8e1f
SH		 892static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
893{
894 struct dw_mci_slot *slot = mmc_priv(mmc);
895 struct dw_mci *host = slot->host;
896 u32 int_mask;
897
898 /* Enable/disable Slot Specific SDIO interrupt */
899 int_mask = mci_readl(host, INTMASK);
900 if (enb) {
9623b5b9
DA		 901 /*
902 * Turn off low power mode if it was enabled. This is a bit of
903 * a heavy operation and we disable / enable IRQs a lot, so
904 * we'll leave low power mode disabled and it will get
905 * re-enabled again in dw_mci_setup_bus().
906 */
907 dw_mci_disable_low_power(slot);
908
1a5c8e1f 909 mci_writel(host, INTMASK,
705ad047 910 (int_mask | SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 911 } else {
912 mci_writel(host, INTMASK,
705ad047 913 (int_mask & ~SDMMC_INT_SDIO(slot->id)));
1a5c8e1f
SH		 914 }
915}
916
f95f3850 917static const struct mmc_host_ops dw_mci_ops = {
1a5c8e1f 918 .request = dw_mci_request,
9aa51408
SJ		 919 .pre_req = dw_mci_pre_req,
920 .post_req = dw_mci_post_req,
1a5c8e1f
SH		 921 .set_ios = dw_mci_set_ios,
922 .get_ro = dw_mci_get_ro,
923 .get_cd = dw_mci_get_cd,
924 .enable_sdio_irq = dw_mci_enable_sdio_irq,
f95f3850
WN		 925};
926
927static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
928 __releases(&host->lock)
929 __acquires(&host->lock)
930{
931 struct dw_mci_slot *slot;
932 struct mmc_host *prev_mmc = host->cur_slot->mmc;
933
934 WARN_ON(host->cmd || host->data);
935
936 host->cur_slot->mrq = NULL;
937 host->mrq = NULL;
938 if (!list_empty(&host->queue)) {
939 slot = list_entry(host->queue.next,
940 struct dw_mci_slot, queue_node);
941 list_del(&slot->queue_node);
4a90920c 942 dev_vdbg(host->dev, "list not empty: %s is next\n",
f95f3850
WN		 943 mmc_hostname(slot->mmc));
944 host->state = STATE_SENDING_CMD;
945 dw_mci_start_request(host, slot);
946 } else {
4a90920c 947 dev_vdbg(host->dev, "list empty\n");
f95f3850
WN		 948 host->state = STATE_IDLE;
949 }
950
951 spin_unlock(&host->lock);
952 mmc_request_done(prev_mmc, mrq);
953 spin_lock(&host->lock);
954}
955
956static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
957{
958 u32 status = host->cmd_status;
959
960 host->cmd_status = 0;
961
962 /* Read the response from the card (up to 16 bytes) */
963 if (cmd->flags & MMC_RSP_PRESENT) {
964 if (cmd->flags & MMC_RSP_136) {
965 cmd->resp[3] = mci_readl(host, RESP0);
966 cmd->resp[2] = mci_readl(host, RESP1);
967 cmd->resp[1] = mci_readl(host, RESP2);
968 cmd->resp[0] = mci_readl(host, RESP3);
969 } else {
970 cmd->resp[0] = mci_readl(host, RESP0);
971 cmd->resp[1] = 0;
972 cmd->resp[2] = 0;
973 cmd->resp[3] = 0;
974 }
975 }
976
977 if (status & SDMMC_INT_RTO)
978 cmd->error = -ETIMEDOUT;
979 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
980 cmd->error = -EILSEQ;
981 else if (status & SDMMC_INT_RESP_ERR)
982 cmd->error = -EIO;
983 else
984 cmd->error = 0;
985
986 if (cmd->error) {
987 /* newer ip versions need a delay between retries */
988 if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
989 mdelay(20);
990
991 if (cmd->data) {
f95f3850 992 dw_mci_stop_dma(host);
fda5f736 993 host->data = NULL;
f95f3850
WN		 994 }
995 }
996}
997
998static void dw_mci_tasklet_func(unsigned long priv)
999{
1000 struct dw_mci *host = (struct dw_mci *)priv;
1001 struct mmc_data *data;
1002 struct mmc_command *cmd;
1003 enum dw_mci_state state;
1004 enum dw_mci_state prev_state;
94dd5b33 1005 u32 status, ctrl;
f95f3850
WN		 1006
1007 spin_lock(&host->lock);
1008
1009 state = host->state;
1010 data = host->data;
1011
1012 do {
1013 prev_state = state;
1014
1015 switch (state) {
1016 case STATE_IDLE:
1017 break;
1018
1019 case STATE_SENDING_CMD:
1020 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1021 &host->pending_events))
1022 break;
1023
1024 cmd = host->cmd;
1025 host->cmd = NULL;
1026 set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
053b3ce6
SJ		 1027 dw_mci_command_complete(host, cmd);
1028 if (cmd == host->mrq->sbc && !cmd->error) {
1029 prev_state = state = STATE_SENDING_CMD;
1030 __dw_mci_start_request(host, host->cur_slot,
1031 host->mrq->cmd);
1032 goto unlock;
1033 }
1034
f95f3850
WN		 1035 if (!host->mrq->data || cmd->error) {
1036 dw_mci_request_end(host, host->mrq);
1037 goto unlock;
1038 }
1039
1040 prev_state = state = STATE_SENDING_DATA;
1041 /* fall through */
1042
1043 case STATE_SENDING_DATA:
1044 if (test_and_clear_bit(EVENT_DATA_ERROR,
1045 &host->pending_events)) {
1046 dw_mci_stop_dma(host);
1047 if (data->stop)
1048 send_stop_cmd(host, data);
1049 state = STATE_DATA_ERROR;
1050 break;
1051 }
1052
1053 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1054 &host->pending_events))
1055 break;
1056
1057 set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
1058 prev_state = state = STATE_DATA_BUSY;
1059 /* fall through */
1060
1061 case STATE_DATA_BUSY:
1062 if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
1063 &host->pending_events))
1064 break;
1065
1066 host->data = NULL;
1067 set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
1068 status = host->data_status;
1069
1070 if (status & DW_MCI_DATA_ERROR_FLAGS) {
1071 if (status & SDMMC_INT_DTO) {
f95f3850
WN		 1072 data->error = -ETIMEDOUT;
1073 } else if (status & SDMMC_INT_DCRC) {
f95f3850 1074 data->error = -EILSEQ;
55c5efbc
JH		 1075 } else if (status & SDMMC_INT_EBE &&
1076 host->dir_status ==
1077 DW_MCI_SEND_STATUS) {
1078 /*
1079 * No data CRC status was returned.
1080 * The number of bytes transferred will
1081 * be exaggerated in PIO mode.
1082 */
1083 data->bytes_xfered = 0;
1084 data->error = -ETIMEDOUT;
f95f3850 1085 } else {
4a90920c 1086 dev_err(host->dev,
f95f3850
WN		 1087 "data FIFO error "
1088 "(status=%08x)\n",
1089 status);
1090 data->error = -EIO;
1091 }
94dd5b33
JH		 1092 /*
1093 * After an error, there may be data lingering
1094 * in the FIFO, so reset it - doing so
1095 * generates a block interrupt, hence setting
1096 * the scatter-gather pointer to NULL.
1097 */
f9c2a0dc 1098 sg_miter_stop(&host->sg_miter);
94dd5b33
JH		 1099 host->sg = NULL;
1100 ctrl = mci_readl(host, CTRL);
1101 ctrl |= SDMMC_CTRL_FIFO_RESET;
1102 mci_writel(host, CTRL, ctrl);
f95f3850
WN		 1103 } else {
1104 data->bytes_xfered = data->blocks * data->blksz;
1105 data->error = 0;
1106 }
1107
1108 if (!data->stop) {
1109 dw_mci_request_end(host, host->mrq);
1110 goto unlock;
1111 }
1112
053b3ce6
SJ		 1113 if (host->mrq->sbc && !data->error) {
1114 data->stop->error = 0;
1115 dw_mci_request_end(host, host->mrq);
1116 goto unlock;
1117 }
1118
f95f3850
WN		 1119 prev_state = state = STATE_SENDING_STOP;
1120 if (!data->error)
1121 send_stop_cmd(host, data);
1122 /* fall through */
1123
1124 case STATE_SENDING_STOP:
1125 if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1126 &host->pending_events))
1127 break;
1128
1129 host->cmd = NULL;
1130 dw_mci_command_complete(host, host->mrq->stop);
1131 dw_mci_request_end(host, host->mrq);
1132 goto unlock;
1133
1134 case STATE_DATA_ERROR:
1135 if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
1136 &host->pending_events))
1137 break;
1138
1139 state = STATE_DATA_BUSY;
1140 break;
1141 }
1142 } while (state != prev_state);
1143
1144 host->state = state;
1145unlock:
1146 spin_unlock(&host->lock);
1147
1148}
1149
34b664a2
JH		 1150/* push final bytes to part_buf, only use during push */
1151static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1152{
34b664a2
JH		 1153 memcpy((void *)&host->part_buf, buf, cnt);
1154 host->part_buf_count = cnt;
1155}
f95f3850 1156
34b664a2
JH		 1157/* append bytes to part_buf, only use during push */
1158static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
1159{
1160 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
1161 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
1162 host->part_buf_count += cnt;
1163 return cnt;
1164}
f95f3850 1165
34b664a2
JH		 1166/* pull first bytes from part_buf, only use during pull */
1167static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
1168{
1169 cnt = min(cnt, (int)host->part_buf_count);
1170 if (cnt) {
1171 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
1172 cnt);
1173 host->part_buf_count -= cnt;
1174 host->part_buf_start += cnt;
f95f3850 1175 }
34b664a2 1176 return cnt;
f95f3850
WN		 1177}
1178
34b664a2
JH		 1179/* pull final bytes from the part_buf, assuming it's just been filled */
1180static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
f95f3850 1181{
34b664a2
JH		 1182 memcpy(buf, &host->part_buf, cnt);
1183 host->part_buf_start = cnt;
1184 host->part_buf_count = (1 << host->data_shift) - cnt;
1185}
f95f3850 1186
34b664a2
JH		 1187static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
1188{
1189 /* try and push anything in the part_buf */
1190 if (unlikely(host->part_buf_count)) {
1191 int len = dw_mci_push_part_bytes(host, buf, cnt);
1192 buf += len;
1193 cnt -= len;
1194 if (!sg_next(host->sg) || host->part_buf_count == 2) {
4e0a5adf
JC		 1195 mci_writew(host, DATA(host->data_offset),
1196 host->part_buf16);
34b664a2
JH		 1197 host->part_buf_count = 0;
1198 }
1199 }
1200#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1201 if (unlikely((unsigned long)buf & 0x1)) {
1202 while (cnt >= 2) {
1203 u16 aligned_buf[64];
1204 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1205 int items = len >> 1;
1206 int i;
1207 /* memcpy from input buffer into aligned buffer */
1208 memcpy(aligned_buf, buf, len);
1209 buf += len;
1210 cnt -= len;
1211 /* push data from aligned buffer into fifo */
1212 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1213 mci_writew(host, DATA(host->data_offset),
1214 aligned_buf[i]);
34b664a2
JH		 1215 }
1216 } else
1217#endif
1218 {
1219 u16 *pdata = buf;
1220 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1221 mci_writew(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1222 buf = pdata;
1223 }
1224 /* put anything remaining in the part_buf */
1225 if (cnt) {
1226 dw_mci_set_part_bytes(host, buf, cnt);
1227 if (!sg_next(host->sg))
4e0a5adf
JC		 1228 mci_writew(host, DATA(host->data_offset),
1229 host->part_buf16);
34b664a2
JH		 1230 }
1231}
f95f3850 1232
34b664a2
JH		 1233static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
1234{
1235#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1236 if (unlikely((unsigned long)buf & 0x1)) {
1237 while (cnt >= 2) {
1238 /* pull data from fifo into aligned buffer */
1239 u16 aligned_buf[64];
1240 int len = min(cnt & -2, (int)sizeof(aligned_buf));
1241 int items = len >> 1;
1242 int i;
1243 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1244 aligned_buf[i] = mci_readw(host,
1245 DATA(host->data_offset));
34b664a2
JH		 1246 /* memcpy from aligned buffer into output buffer */
1247 memcpy(buf, aligned_buf, len);
1248 buf += len;
1249 cnt -= len;
1250 }
1251 } else
1252#endif
1253 {
1254 u16 *pdata = buf;
1255 for (; cnt >= 2; cnt -= 2)
4e0a5adf 1256 *pdata++ = mci_readw(host, DATA(host->data_offset));
34b664a2
JH		 1257 buf = pdata;
1258 }
1259 if (cnt) {
4e0a5adf 1260 host->part_buf16 = mci_readw(host, DATA(host->data_offset));
34b664a2 1261 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1262 }
1263}
1264
1265static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
1266{
34b664a2
JH		 1267 /* try and push anything in the part_buf */
1268 if (unlikely(host->part_buf_count)) {
1269 int len = dw_mci_push_part_bytes(host, buf, cnt);
1270 buf += len;
1271 cnt -= len;
1272 if (!sg_next(host->sg) || host->part_buf_count == 4) {
4e0a5adf
JC		 1273 mci_writel(host, DATA(host->data_offset),
1274 host->part_buf32);
34b664a2
JH		 1275 host->part_buf_count = 0;
1276 }
1277 }
1278#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1279 if (unlikely((unsigned long)buf & 0x3)) {
1280 while (cnt >= 4) {
1281 u32 aligned_buf[32];
1282 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1283 int items = len >> 2;
1284 int i;
1285 /* memcpy from input buffer into aligned buffer */
1286 memcpy(aligned_buf, buf, len);
1287 buf += len;
1288 cnt -= len;
1289 /* push data from aligned buffer into fifo */
1290 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1291 mci_writel(host, DATA(host->data_offset),
1292 aligned_buf[i]);
34b664a2
JH		 1293 }
1294 } else
1295#endif
1296 {
1297 u32 *pdata = buf;
1298 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1299 mci_writel(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1300 buf = pdata;
1301 }
1302 /* put anything remaining in the part_buf */
1303 if (cnt) {
1304 dw_mci_set_part_bytes(host, buf, cnt);
1305 if (!sg_next(host->sg))
4e0a5adf
JC		 1306 mci_writel(host, DATA(host->data_offset),
1307 host->part_buf32);
f95f3850
WN		 1308 }
1309}
1310
1311static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
1312{
34b664a2
JH		 1313#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1314 if (unlikely((unsigned long)buf & 0x3)) {
1315 while (cnt >= 4) {
1316 /* pull data from fifo into aligned buffer */
1317 u32 aligned_buf[32];
1318 int len = min(cnt & -4, (int)sizeof(aligned_buf));
1319 int items = len >> 2;
1320 int i;
1321 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1322 aligned_buf[i] = mci_readl(host,
1323 DATA(host->data_offset));
34b664a2
JH		 1324 /* memcpy from aligned buffer into output buffer */
1325 memcpy(buf, aligned_buf, len);
1326 buf += len;
1327 cnt -= len;
1328 }
1329 } else
1330#endif
1331 {
1332 u32 *pdata = buf;
1333 for (; cnt >= 4; cnt -= 4)
4e0a5adf 1334 *pdata++ = mci_readl(host, DATA(host->data_offset));
34b664a2
JH		 1335 buf = pdata;
1336 }
1337 if (cnt) {
4e0a5adf 1338 host->part_buf32 = mci_readl(host, DATA(host->data_offset));
34b664a2 1339 dw_mci_pull_final_bytes(host, buf, cnt);
f95f3850
WN		 1340 }
1341}
1342
1343static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
1344{
34b664a2
JH		 1345 /* try and push anything in the part_buf */
1346 if (unlikely(host->part_buf_count)) {
1347 int len = dw_mci_push_part_bytes(host, buf, cnt);
1348 buf += len;
1349 cnt -= len;
1350 if (!sg_next(host->sg) || host->part_buf_count == 8) {
4e0a5adf
JC		 1351 mci_writew(host, DATA(host->data_offset),
1352 host->part_buf);
34b664a2
JH		 1353 host->part_buf_count = 0;
1354 }
1355 }
1356#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1357 if (unlikely((unsigned long)buf & 0x7)) {
1358 while (cnt >= 8) {
1359 u64 aligned_buf[16];
1360 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1361 int items = len >> 3;
1362 int i;
1363 /* memcpy from input buffer into aligned buffer */
1364 memcpy(aligned_buf, buf, len);
1365 buf += len;
1366 cnt -= len;
1367 /* push data from aligned buffer into fifo */
1368 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1369 mci_writeq(host, DATA(host->data_offset),
1370 aligned_buf[i]);
34b664a2
JH		 1371 }
1372 } else
1373#endif
1374 {
1375 u64 *pdata = buf;
1376 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1377 mci_writeq(host, DATA(host->data_offset), *pdata++);
34b664a2
JH		 1378 buf = pdata;
1379 }
1380 /* put anything remaining in the part_buf */
1381 if (cnt) {
1382 dw_mci_set_part_bytes(host, buf, cnt);
1383 if (!sg_next(host->sg))
4e0a5adf
JC		 1384 mci_writeq(host, DATA(host->data_offset),
1385 host->part_buf);
f95f3850
WN		 1386 }
1387}
1388
1389static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
1390{
34b664a2
JH		 1391#ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
1392 if (unlikely((unsigned long)buf & 0x7)) {
1393 while (cnt >= 8) {
1394 /* pull data from fifo into aligned buffer */
1395 u64 aligned_buf[16];
1396 int len = min(cnt & -8, (int)sizeof(aligned_buf));
1397 int items = len >> 3;
1398 int i;
1399 for (i = 0; i < items; ++i)
4e0a5adf
JC		 1400 aligned_buf[i] = mci_readq(host,
1401 DATA(host->data_offset));
34b664a2
JH		 1402 /* memcpy from aligned buffer into output buffer */
1403 memcpy(buf, aligned_buf, len);
1404 buf += len;
1405 cnt -= len;
1406 }
1407 } else
1408#endif
1409 {
1410 u64 *pdata = buf;
1411 for (; cnt >= 8; cnt -= 8)
4e0a5adf 1412 *pdata++ = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1413 buf = pdata;
1414 }
1415 if (cnt) {
4e0a5adf 1416 host->part_buf = mci_readq(host, DATA(host->data_offset));
34b664a2
JH		 1417 dw_mci_pull_final_bytes(host, buf, cnt);
1418 }
1419}
f95f3850 1420
34b664a2
JH		 1421static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
1422{
1423 int len;
f95f3850 1424
34b664a2
JH		 1425 /* get remaining partial bytes */
1426 len = dw_mci_pull_part_bytes(host, buf, cnt);
1427 if (unlikely(len == cnt))
1428 return;
1429 buf += len;
1430 cnt -= len;
1431
1432 /* get the rest of the data */
1433 host->pull_data(host, buf, cnt);
f95f3850
WN		 1434}
1435
1436static void dw_mci_read_data_pio(struct dw_mci *host)
1437{
f9c2a0dc
SJ		 1438 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1439 void *buf;
1440 unsigned int offset;
f95f3850
WN		 1441 struct mmc_data *data = host->data;
1442 int shift = host->data_shift;
1443 u32 status;
ba6a902d 1444 unsigned int nbytes = 0, len;
f9c2a0dc 1445 unsigned int remain, fcnt;
f95f3850
WN		 1446
1447 do {
f9c2a0dc
SJ		 1448 if (!sg_miter_next(sg_miter))
1449 goto done;
1450
1451 host->sg = sg_miter->__sg;
1452 buf = sg_miter->addr;
1453 remain = sg_miter->length;
1454 offset = 0;
1455
1456 do {
1457 fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
1458 << shift) + host->part_buf_count;
1459 len = min(remain, fcnt);
1460 if (!len)
1461 break;
34b664a2 1462 dw_mci_pull_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1463 offset += len;
1464 nbytes += len;
f9c2a0dc
SJ		 1465 remain -= len;
1466 } while (remain);
f95f3850 1467
e74f3a9c 1468 sg_miter->consumed = offset;
f95f3850
WN		 1469 status = mci_readl(host, MINTSTS);
1470 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
f95f3850 1471 } while (status & SDMMC_INT_RXDR); /*if the RXDR is ready read again*/
f95f3850 1472 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1473
1474 if (!remain) {
1475 if (!sg_miter_next(sg_miter))
1476 goto done;
1477 sg_miter->consumed = 0;
1478 }
1479 sg_miter_stop(sg_miter);
f95f3850
WN		 1480 return;
1481
1482done:
1483 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1484 sg_miter_stop(sg_miter);
1485 host->sg = NULL;
f95f3850
WN		 1486 smp_wmb();
1487 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1488}
1489
1490static void dw_mci_write_data_pio(struct dw_mci *host)
1491{
f9c2a0dc
SJ		 1492 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1493 void *buf;
1494 unsigned int offset;
f95f3850
WN		 1495 struct mmc_data *data = host->data;
1496 int shift = host->data_shift;
1497 u32 status;
1498 unsigned int nbytes = 0, len;
f9c2a0dc
SJ		 1499 unsigned int fifo_depth = host->fifo_depth;
1500 unsigned int remain, fcnt;
f95f3850
WN		 1501
1502 do {
f9c2a0dc
SJ		 1503 if (!sg_miter_next(sg_miter))
1504 goto done;
1505
1506 host->sg = sg_miter->__sg;
1507 buf = sg_miter->addr;
1508 remain = sg_miter->length;
1509 offset = 0;
1510
1511 do {
1512 fcnt = ((fifo_depth -
1513 SDMMC_GET_FCNT(mci_readl(host, STATUS)))
1514 << shift) - host->part_buf_count;
1515 len = min(remain, fcnt);
1516 if (!len)
1517 break;
f95f3850 1518 host->push_data(host, (void *)(buf + offset), len);
f95f3850
WN		 1519 offset += len;
1520 nbytes += len;
f9c2a0dc
SJ		 1521 remain -= len;
1522 } while (remain);
f95f3850 1523
e74f3a9c 1524 sg_miter->consumed = offset;
f95f3850
WN		 1525 status = mci_readl(host, MINTSTS);
1526 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
f95f3850 1527 } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
f95f3850 1528 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1529
1530 if (!remain) {
1531 if (!sg_miter_next(sg_miter))
1532 goto done;
1533 sg_miter->consumed = 0;
1534 }
1535 sg_miter_stop(sg_miter);
f95f3850
WN		 1536 return;
1537
1538done:
1539 data->bytes_xfered += nbytes;
f9c2a0dc
SJ		 1540 sg_miter_stop(sg_miter);
1541 host->sg = NULL;
f95f3850
WN		 1542 smp_wmb();
1543 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
1544}
1545
1546static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
1547{
1548 if (!host->cmd_status)
1549 host->cmd_status = status;
1550
1551 smp_wmb();
1552
1553 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
1554 tasklet_schedule(&host->tasklet);
1555}
1556
1557static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
1558{
1559 struct dw_mci *host = dev_id;
182c9081 1560 u32 pending;
f95f3850 1561 unsigned int pass_count = 0;
1a5c8e1f 1562 int i;
f95f3850
WN		 1563
1564 do {
f95f3850
WN		 1565 pending = mci_readl(host, MINTSTS); /* read-only mask reg */
1566
1567 /*
1568 * DTO fix - version 2.10a and below, and only if internal DMA
1569 * is configured.
1570 */
1571 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
1572 if (!pending &&
1573 ((mci_readl(host, STATUS) >> 17) & 0x1fff))
1574 pending |= SDMMC_INT_DATA_OVER;
1575 }
1576
1577 if (!pending)
1578 break;
1579
1580 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
1581 mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
182c9081 1582 host->cmd_status = pending;
f95f3850
WN		 1583 smp_wmb();
1584 set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
f95f3850
WN		 1585 }
1586
1587 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
1588 /* if there is an error report DATA_ERROR */
1589 mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
182c9081 1590 host->data_status = pending;
f95f3850
WN		 1591 smp_wmb();
1592 set_bit(EVENT_DATA_ERROR, &host->pending_events);
9b2026a1 1593 tasklet_schedule(&host->tasklet);
f95f3850
WN		 1594 }
1595
1596 if (pending & SDMMC_INT_DATA_OVER) {
1597 mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
1598 if (!host->data_status)
182c9081 1599 host->data_status = pending;
f95f3850
WN		 1600 smp_wmb();
1601 if (host->dir_status == DW_MCI_RECV_STATUS) {
1602 if (host->sg != NULL)
1603 dw_mci_read_data_pio(host);
1604 }
1605 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
1606 tasklet_schedule(&host->tasklet);
1607 }
1608
1609 if (pending & SDMMC_INT_RXDR) {
1610 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
b40af3aa 1611 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
f95f3850
WN		 1612 dw_mci_read_data_pio(host);
1613 }
1614
1615 if (pending & SDMMC_INT_TXDR) {
1616 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
b40af3aa 1617 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
f95f3850
WN		 1618 dw_mci_write_data_pio(host);
1619 }
1620
1621 if (pending & SDMMC_INT_CMD_DONE) {
1622 mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
182c9081 1623 dw_mci_cmd_interrupt(host, pending);
f95f3850
WN		 1624 }
1625
1626 if (pending & SDMMC_INT_CD) {
1627 mci_writel(host, RINTSTS, SDMMC_INT_CD);
95dcc2cb 1628 queue_work(host->card_workqueue, &host->card_work);
f95f3850
WN		 1629 }
1630
1a5c8e1f
SH		 1631 /* Handle SDIO Interrupts */
1632 for (i = 0; i < host->num_slots; i++) {
1633 struct dw_mci_slot *slot = host->slot[i];
1634 if (pending & SDMMC_INT_SDIO(i)) {
1635 mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
1636 mmc_signal_sdio_irq(slot->mmc);
1637 }
1638 }
1639
f95f3850
WN		 1640 } while (pass_count++ < 5);
1641
1642#ifdef CONFIG_MMC_DW_IDMAC
1643 /* Handle DMA interrupts */
1644 pending = mci_readl(host, IDSTS);
1645 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
1646 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
1647 mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
f95f3850
WN		 1648 host->dma_ops->complete(host);
1649 }
1650#endif
1651
1652 return IRQ_HANDLED;
1653}
1654
1791b13e 1655static void dw_mci_work_routine_card(struct work_struct *work)
f95f3850 1656{
1791b13e 1657 struct dw_mci *host = container_of(work, struct dw_mci, card_work);
f95f3850
WN		 1658 int i;
1659
1660 for (i = 0; i < host->num_slots; i++) {
1661 struct dw_mci_slot *slot = host->slot[i];
1662 struct mmc_host *mmc = slot->mmc;
1663 struct mmc_request *mrq;
1664 int present;
1665 u32 ctrl;
1666
1667 present = dw_mci_get_cd(mmc);
1668 while (present != slot->last_detect_state) {
f95f3850
WN		 1669 dev_dbg(&slot->mmc->class_dev, "card %s\n",
1670 present ? "inserted" : "removed");
1671
1791b13e
JH		 1672 /* Power up slot (before spin_lock, may sleep) */
1673 if (present != 0 && host->pdata->setpower)
1674 host->pdata->setpower(slot->id, mmc->ocr_avail);
1675
1676 spin_lock_bh(&host->lock);
1677
f95f3850
WN		 1678 /* Card change detected */
1679 slot->last_detect_state = present;
1680
1791b13e
JH		 1681 /* Mark card as present if applicable */
1682 if (present != 0)
f95f3850 1683 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
f95f3850
WN		 1684
1685 /* Clean up queue if present */
1686 mrq = slot->mrq;
1687 if (mrq) {
1688 if (mrq == host->mrq) {
1689 host->data = NULL;
1690 host->cmd = NULL;
1691
1692 switch (host->state) {
1693 case STATE_IDLE:
1694 break;
1695 case STATE_SENDING_CMD:
1696 mrq->cmd->error = -ENOMEDIUM;
1697 if (!mrq->data)
1698 break;
1699 /* fall through */
1700 case STATE_SENDING_DATA:
1701 mrq->data->error = -ENOMEDIUM;
1702 dw_mci_stop_dma(host);
1703 break;
1704 case STATE_DATA_BUSY:
1705 case STATE_DATA_ERROR:
1706 if (mrq->data->error == -EINPROGRESS)
1707 mrq->data->error = -ENOMEDIUM;
1708 if (!mrq->stop)
1709 break;
1710 /* fall through */
1711 case STATE_SENDING_STOP:
1712 mrq->stop->error = -ENOMEDIUM;
1713 break;
1714 }
1715
1716 dw_mci_request_end(host, mrq);
1717 } else {
1718 list_del(&slot->queue_node);
1719 mrq->cmd->error = -ENOMEDIUM;
1720 if (mrq->data)
1721 mrq->data->error = -ENOMEDIUM;
1722 if (mrq->stop)
1723 mrq->stop->error = -ENOMEDIUM;
1724
1725 spin_unlock(&host->lock);
1726 mmc_request_done(slot->mmc, mrq);
1727 spin_lock(&host->lock);
1728 }
1729 }
1730
1731 /* Power down slot */
1732 if (present == 0) {
f95f3850
WN		 1733 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1734
1735 /*
1736 * Clear down the FIFO - doing so generates a
1737 * block interrupt, hence setting the
1738 * scatter-gather pointer to NULL.
1739 */
f9c2a0dc 1740 sg_miter_stop(&host->sg_miter);
f95f3850
WN		 1741 host->sg = NULL;
1742
1743 ctrl = mci_readl(host, CTRL);
1744 ctrl |= SDMMC_CTRL_FIFO_RESET;
1745 mci_writel(host, CTRL, ctrl);
1746
1747#ifdef CONFIG_MMC_DW_IDMAC
1748 ctrl = mci_readl(host, BMOD);
141a712a
SJ		 1749 /* Software reset of DMA */
1750 ctrl |= SDMMC_IDMAC_SWRESET;
f95f3850
WN		 1751 mci_writel(host, BMOD, ctrl);
1752#endif
1753
1754 }
1755
1791b13e
JH		 1756 spin_unlock_bh(&host->lock);
1757
1758 /* Power down slot (after spin_unlock, may sleep) */
1759 if (present == 0 && host->pdata->setpower)
1760 host->pdata->setpower(slot->id, 0);
1761
f95f3850
WN		 1762 present = dw_mci_get_cd(mmc);
1763 }
1764
1765 mmc_detect_change(slot->mmc,
1766 msecs_to_jiffies(host->pdata->detect_delay_ms));
1767 }
1768}
1769
36c179a9 1770static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
f95f3850
WN		 1771{
1772 struct mmc_host *mmc;
1773 struct dw_mci_slot *slot;
1774
4a90920c 1775 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
f95f3850
WN		 1776 if (!mmc)
1777 return -ENOMEM;
1778
1779 slot = mmc_priv(mmc);
1780 slot->id = id;
1781 slot->mmc = mmc;
1782 slot->host = host;
1783
1784 mmc->ops = &dw_mci_ops;
1785 mmc->f_min = DIV_ROUND_UP(host->bus_hz, 510);
1786 mmc->f_max = host->bus_hz;
1787
1788 if (host->pdata->get_ocr)
1789 mmc->ocr_avail = host->pdata->get_ocr(id);
1790 else
1791 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
1792
1793 /*
1794 * Start with slot power disabled, it will be enabled when a card
1795 * is detected.
1796 */
1797 if (host->pdata->setpower)
1798 host->pdata->setpower(id, 0);
1799
fc3d7720
JC		 1800 if (host->pdata->caps)
1801 mmc->caps = host->pdata->caps;
fc3d7720 1802
4f408cc6
SJ		 1803 if (host->pdata->caps2)
1804 mmc->caps2 = host->pdata->caps2;
4f408cc6 1805
f95f3850
WN		 1806 if (host->pdata->get_bus_wd)
1807 if (host->pdata->get_bus_wd(slot->id) >= 4)
1808 mmc->caps |= MMC_CAP_4_BIT_DATA;
1809
1810 if (host->pdata->quirks & DW_MCI_QUIRK_HIGHSPEED)
6daa7778 1811 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
f95f3850 1812
356ac2cf
JC		 1813 if (mmc->caps2 & MMC_CAP2_POWEROFF_NOTIFY)
1814 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_SHORT;
1815 else
1816 mmc->power_notify_type = MMC_HOST_PW_NOTIFY_NONE;
1817
f95f3850
WN		 1818 if (host->pdata->blk_settings) {
1819 mmc->max_segs = host->pdata->blk_settings->max_segs;
1820 mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
1821 mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
1822 mmc->max_req_size = host->pdata->blk_settings->max_req_size;
1823 mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
1824 } else {
1825 /* Useful defaults if platform data is unset. */
a39e5746
JC		 1826#ifdef CONFIG_MMC_DW_IDMAC
1827 mmc->max_segs = host->ring_size;
1828 mmc->max_blk_size = 65536;
1829 mmc->max_blk_count = host->ring_size;
1830 mmc->max_seg_size = 0x1000;
1831 mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
1832#else
f95f3850
WN		 1833 mmc->max_segs = 64;
1834 mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
1835 mmc->max_blk_count = 512;
1836 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1837 mmc->max_seg_size = mmc->max_req_size;
f95f3850 1838#endif /* CONFIG_MMC_DW_IDMAC */
a39e5746 1839 }
f95f3850 1840
c07946a3
JC		 1841 host->vmmc = regulator_get(mmc_dev(mmc), "vmmc");
1842 if (IS_ERR(host->vmmc)) {
a3c76eb9 1843 pr_info("%s: no vmmc regulator found\n", mmc_hostname(mmc));
c07946a3
JC		 1844 host->vmmc = NULL;
1845 } else
1846 regulator_enable(host->vmmc);
1847
f95f3850
WN		 1848 if (dw_mci_get_cd(mmc))
1849 set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1850 else
1851 clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
1852
1853 host->slot[id] = slot;
1854 mmc_add_host(mmc);
1855
1856#if defined(CONFIG_DEBUG_FS)
1857 dw_mci_init_debugfs(slot);
1858#endif
1859
1860 /* Card initially undetected */
1861 slot->last_detect_state = 0;
1862
dd6c4b98
WN		 1863 /*
1864 * Card may have been plugged in prior to boot so we
1865 * need to run the detect tasklet
1866 */
95dcc2cb 1867 queue_work(host->card_workqueue, &host->card_work);
dd6c4b98 1868
f95f3850
WN		 1869 return 0;
1870}
1871
1872static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
1873{
1874 /* Shutdown detect IRQ */
1875 if (slot->host->pdata->exit)
1876 slot->host->pdata->exit(id);
1877
1878 /* Debugfs stuff is cleaned up by mmc core */
1879 mmc_remove_host(slot->mmc);
1880 slot->host->slot[id] = NULL;
1881 mmc_free_host(slot->mmc);
1882}
1883
1884static void dw_mci_init_dma(struct dw_mci *host)
1885{
1886 /* Alloc memory for sg translation */
4a90920c 1887 host->sg_cpu = dma_alloc_coherent(host->dev, PAGE_SIZE,
f95f3850
WN		 1888 &host->sg_dma, GFP_KERNEL);
1889 if (!host->sg_cpu) {
4a90920c 1890 dev_err(host->dev, "%s: could not alloc DMA memory\n",
f95f3850
WN		 1891 __func__);
1892 goto no_dma;
1893 }
1894
1895 /* Determine which DMA interface to use */
1896#ifdef CONFIG_MMC_DW_IDMAC
1897 host->dma_ops = &dw_mci_idmac_ops;
f95f3850
WN		 1898#endif
1899
1900 if (!host->dma_ops)
1901 goto no_dma;
1902
e1631f98
JC		 1903 if (host->dma_ops->init && host->dma_ops->start &&
1904 host->dma_ops->stop && host->dma_ops->cleanup) {
f95f3850 1905 if (host->dma_ops->init(host)) {
4a90920c 1906 dev_err(host->dev, "%s: Unable to initialize "
f95f3850
WN		 1907 "DMA Controller.\n", __func__);
1908 goto no_dma;
1909 }
1910 } else {
4a90920c 1911 dev_err(host->dev, "DMA initialization not found.\n");
f95f3850
WN		 1912 goto no_dma;
1913 }
1914
1915 host->use_dma = 1;
1916 return;
1917
1918no_dma:
4a90920c 1919 dev_info(host->dev, "Using PIO mode.\n");
f95f3850
WN		 1920 host->use_dma = 0;
1921 return;
1922}
1923
1924static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
1925{
1926 unsigned long timeout = jiffies + msecs_to_jiffies(500);
1927 unsigned int ctrl;
1928
1929 mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1930 SDMMC_CTRL_DMA_RESET));
1931
1932 /* wait till resets clear */
1933 do {
1934 ctrl = mci_readl(host, CTRL);
1935 if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
1936 SDMMC_CTRL_DMA_RESET)))
1937 return true;
1938 } while (time_before(jiffies, timeout));
1939
1940 dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
1941
1942 return false;
1943}
1944
62ca8034 1945int dw_mci_probe(struct dw_mci *host)
f95f3850 1946{
62ca8034 1947 int width, i, ret = 0;
f95f3850 1948 u32 fifo_size;
1c2215b7 1949 int init_slots = 0;
f95f3850 1950
62ca8034 1951 if (!host->pdata || !host->pdata->init) {
4a90920c 1952 dev_err(host->dev,
f95f3850 1953 "Platform data must supply init function\n");
62ca8034 1954 return -ENODEV;
f95f3850
WN		 1955 }
1956
62ca8034 1957 if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
4a90920c 1958 dev_err(host->dev,
f95f3850 1959 "Platform data must supply select_slot function\n");
62ca8034 1960 return -ENODEV;
f95f3850
WN		 1961 }
1962
f90a0612
TA		 1963 host->biu_clk = clk_get(host->dev, "biu");
1964 if (IS_ERR(host->biu_clk)) {
1965 dev_dbg(host->dev, "biu clock not available\n");
1966 } else {
1967 ret = clk_prepare_enable(host->biu_clk);
1968 if (ret) {
1969 dev_err(host->dev, "failed to enable biu clock\n");
1970 clk_put(host->biu_clk);
1971 return ret;
1972 }
1973 }
1974
1975 host->ciu_clk = clk_get(host->dev, "ciu");
1976 if (IS_ERR(host->ciu_clk)) {
1977 dev_dbg(host->dev, "ciu clock not available\n");
1978 } else {
1979 ret = clk_prepare_enable(host->ciu_clk);
1980 if (ret) {
1981 dev_err(host->dev, "failed to enable ciu clock\n");
1982 clk_put(host->ciu_clk);
1983 goto err_clk_biu;
1984 }
1985 }
1986
1987 if (IS_ERR(host->ciu_clk))
1988 host->bus_hz = host->pdata->bus_hz;
1989 else
1990 host->bus_hz = clk_get_rate(host->ciu_clk);
1991
1992 if (!host->bus_hz) {
4a90920c 1993 dev_err(host->dev,
f95f3850 1994 "Platform data must supply bus speed\n");
f90a0612
TA		 1995 ret = -ENODEV;
1996 goto err_clk_ciu;
f95f3850
WN		 1997 }
1998
62ca8034 1999 host->quirks = host->pdata->quirks;
f95f3850
WN		 2000
2001 spin_lock_init(&host->lock);
2002 INIT_LIST_HEAD(&host->queue);
2003
f95f3850
WN		 2004 /*
2005 * Get the host data width - this assumes that HCON has been set with
2006 * the correct values.
2007 */
2008 i = (mci_readl(host, HCON) >> 7) & 0x7;
2009 if (!i) {
2010 host->push_data = dw_mci_push_data16;
2011 host->pull_data = dw_mci_pull_data16;
2012 width = 16;
2013 host->data_shift = 1;
2014 } else if (i == 2) {
2015 host->push_data = dw_mci_push_data64;
2016 host->pull_data = dw_mci_pull_data64;
2017 width = 64;
2018 host->data_shift = 3;
2019 } else {
2020 /* Check for a reserved value, and warn if it is */
2021 WARN((i != 1),
2022 "HCON reports a reserved host data width!\n"
2023 "Defaulting to 32-bit access.\n");
2024 host->push_data = dw_mci_push_data32;
2025 host->pull_data = dw_mci_pull_data32;
2026 width = 32;
2027 host->data_shift = 2;
2028 }
2029
2030 /* Reset all blocks */
4a90920c 2031 if (!mci_wait_reset(host->dev, host))
141a712a
SJ		 2032 return -ENODEV;
2033
2034 host->dma_ops = host->pdata->dma_ops;
2035 dw_mci_init_dma(host);
f95f3850
WN		 2036
2037 /* Clear the interrupts for the host controller */
2038 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2039 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2040
2041 /* Put in max timeout */
2042 mci_writel(host, TMOUT, 0xFFFFFFFF);
2043
2044 /*
2045 * FIFO threshold settings RxMark = fifo_size / 2 - 1,
2046 * Tx Mark = fifo_size / 2 DMA Size = 8
2047 */
b86d8253
JH		 2048 if (!host->pdata->fifo_depth) {
2049 /*
2050 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
2051 * have been overwritten by the bootloader, just like we're
2052 * about to do, so if you know the value for your hardware, you
2053 * should put it in the platform data.
2054 */
2055 fifo_size = mci_readl(host, FIFOTH);
8234e869 2056 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
b86d8253
JH		 2057 } else {
2058 fifo_size = host->pdata->fifo_depth;
2059 }
2060 host->fifo_depth = fifo_size;
e61cf118
JC		 2061 host->fifoth_val = ((0x2 << 28) | ((fifo_size/2 - 1) << 16) |
2062 ((fifo_size/2) << 0));
2063 mci_writel(host, FIFOTH, host->fifoth_val);
f95f3850
WN		 2064
2065 /* disable clock to CIU */
2066 mci_writel(host, CLKENA, 0);
2067 mci_writel(host, CLKSRC, 0);
2068
2069 tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
95dcc2cb 2070 host->card_workqueue = alloc_workqueue("dw-mci-card",
1791b13e 2071 WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
95dcc2cb 2072 if (!host->card_workqueue)
1791b13e
JH		 2073 goto err_dmaunmap;
2074 INIT_WORK(&host->card_work, dw_mci_work_routine_card);
62ca8034 2075 ret = request_irq(host->irq, dw_mci_interrupt, host->irq_flags, "dw-mci", host);
f95f3850 2076 if (ret)
1791b13e 2077 goto err_workqueue;
f95f3850 2078
f95f3850
WN		 2079 if (host->pdata->num_slots)
2080 host->num_slots = host->pdata->num_slots;
2081 else
2082 host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
2083
2084 /* We need at least one slot to succeed */
2085 for (i = 0; i < host->num_slots; i++) {
2086 ret = dw_mci_init_slot(host, i);
1c2215b7
TA		 2087 if (ret)
2088 dev_dbg(host->dev, "slot %d init failed\n", i);
2089 else
2090 init_slots++;
2091 }
2092
2093 if (init_slots) {
2094 dev_info(host->dev, "%d slots initialized\n", init_slots);
2095 } else {
2096 dev_dbg(host->dev, "attempted to initialize %d slots, "
2097 "but failed on all\n", host->num_slots);
2098 goto err_init_slot;
f95f3850
WN		 2099 }
2100
4e0a5adf
JC		 2101 /*
2102 * In 2.40a spec, Data offset is changed.
2103 * Need to check the version-id and set data-offset for DATA register.
2104 */
2105 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
4a90920c 2106 dev_info(host->dev, "Version ID is %04x\n", host->verid);
4e0a5adf
JC		 2107
2108 if (host->verid < DW_MMC_240A)
2109 host->data_offset = DATA_OFFSET;
2110 else
2111 host->data_offset = DATA_240A_OFFSET;
2112
f95f3850
WN		 2113 /*
2114 * Enable interrupts for command done, data over, data empty, card det,
2115 * receive ready and error such as transmit, receive timeout, crc error
2116 */
2117 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2118 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2119 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2120 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2121 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
2122
4a90920c 2123 dev_info(host->dev, "DW MMC controller at irq %d, "
b86d8253
JH		 2124 "%d bit host data width, "
2125 "%u deep fifo\n",
62ca8034 2126 host->irq, width, fifo_size);
f95f3850 2127 if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
4a90920c 2128 dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
f95f3850
WN		 2129
2130 return 0;
2131
2132err_init_slot:
62ca8034 2133 free_irq(host->irq, host);
f95f3850 2134
1791b13e 2135err_workqueue:
95dcc2cb 2136 destroy_workqueue(host->card_workqueue);
1791b13e 2137
f95f3850
WN		 2138err_dmaunmap:
2139 if (host->use_dma && host->dma_ops->exit)
2140 host->dma_ops->exit(host);
4a90920c 2141 dma_free_coherent(host->dev, PAGE_SIZE,
f95f3850 2142 host->sg_cpu, host->sg_dma);
f95f3850 2143
c07946a3
JC		 2144 if (host->vmmc) {
2145 regulator_disable(host->vmmc);
2146 regulator_put(host->vmmc);
2147 }
f90a0612
TA		 2148
2149err_clk_ciu:
2150 if (!IS_ERR(host->ciu_clk)) {
2151 clk_disable_unprepare(host->ciu_clk);
2152 clk_put(host->ciu_clk);
2153 }
2154err_clk_biu:
2155 if (!IS_ERR(host->biu_clk)) {
2156 clk_disable_unprepare(host->biu_clk);
2157 clk_put(host->biu_clk);
2158 }
f95f3850
WN		 2159 return ret;
2160}
62ca8034 2161EXPORT_SYMBOL(dw_mci_probe);
f95f3850 2162
62ca8034 2163void dw_mci_remove(struct dw_mci *host)
f95f3850 2164{
f95f3850
WN		 2165 int i;
2166
2167 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2168 mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
2169
f95f3850 2170 for (i = 0; i < host->num_slots; i++) {
4a90920c 2171 dev_dbg(host->dev, "remove slot %d\n", i);
f95f3850
WN		 2172 if (host->slot[i])
2173 dw_mci_cleanup_slot(host->slot[i], i);
2174 }
2175
2176 /* disable clock to CIU */
2177 mci_writel(host, CLKENA, 0);
2178 mci_writel(host, CLKSRC, 0);
2179
62ca8034 2180 free_irq(host->irq, host);
95dcc2cb 2181 destroy_workqueue(host->card_workqueue);
4a90920c 2182 dma_free_coherent(host->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
f95f3850
WN		 2183
2184 if (host->use_dma && host->dma_ops->exit)
2185 host->dma_ops->exit(host);
2186
c07946a3
JC		 2187 if (host->vmmc) {
2188 regulator_disable(host->vmmc);
2189 regulator_put(host->vmmc);
2190 }
2191
f90a0612
TA		 2192 if (!IS_ERR(host->ciu_clk))
2193 clk_disable_unprepare(host->ciu_clk);
2194 if (!IS_ERR(host->biu_clk))
2195 clk_disable_unprepare(host->biu_clk);
2196 clk_put(host->ciu_clk);
2197 clk_put(host->biu_clk);
f95f3850 2198}
62ca8034
SH		 2199EXPORT_SYMBOL(dw_mci_remove);
2200
2201
f95f3850 2202
6fe8890d 2203#ifdef CONFIG_PM_SLEEP
f95f3850
WN		 2204/*
2205 * TODO: we should probably disable the clock to the card in the suspend path.
2206 */
62ca8034 2207int dw_mci_suspend(struct dw_mci *host)
f95f3850 2208{
62ca8034 2209 int i, ret = 0;
f95f3850
WN		 2210
2211 for (i = 0; i < host->num_slots; i++) {
2212 struct dw_mci_slot *slot = host->slot[i];
2213 if (!slot)
2214 continue;
2215 ret = mmc_suspend_host(slot->mmc);
2216 if (ret < 0) {
2217 while (--i >= 0) {
2218 slot = host->slot[i];
2219 if (slot)
2220 mmc_resume_host(host->slot[i]->mmc);
2221 }
2222 return ret;
2223 }
2224 }
2225
c07946a3
JC		 2226 if (host->vmmc)
2227 regulator_disable(host->vmmc);
2228
f95f3850
WN		 2229 return 0;
2230}
62ca8034 2231EXPORT_SYMBOL(dw_mci_suspend);
f95f3850 2232
62ca8034 2233int dw_mci_resume(struct dw_mci *host)
f95f3850
WN		 2234{
2235 int i, ret;
f95f3850 2236
1d6c4e0a
JC		 2237 if (host->vmmc)
2238 regulator_enable(host->vmmc);
2239
4a90920c 2240 if (!mci_wait_reset(host->dev, host)) {
e61cf118
JC		 2241 ret = -ENODEV;
2242 return ret;
2243 }
2244
3bfe619d 2245 if (host->use_dma && host->dma_ops->init)
141a712a
SJ		 2246 host->dma_ops->init(host);
2247
e61cf118
JC		 2248 /* Restore the old value at FIFOTH register */
2249 mci_writel(host, FIFOTH, host->fifoth_val);
2250
2251 mci_writel(host, RINTSTS, 0xFFFFFFFF);
2252 mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
2253 SDMMC_INT_TXDR | SDMMC_INT_RXDR |
2254 DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
2255 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
2256
f95f3850
WN		 2257 for (i = 0; i < host->num_slots; i++) {
2258 struct dw_mci_slot *slot = host->slot[i];
2259 if (!slot)
2260 continue;
2261 ret = mmc_resume_host(host->slot[i]->mmc);
2262 if (ret < 0)
2263 return ret;
2264 }
f95f3850
WN		 2265 return 0;
2266}
62ca8034 2267EXPORT_SYMBOL(dw_mci_resume);
6fe8890d
JC		 2268#endif /* CONFIG_PM_SLEEP */
2269
f95f3850
WN		 2270static int __init dw_mci_init(void)
2271{
62ca8034
SH		 2272 printk(KERN_INFO "Synopsys Designware Multimedia Card Interface Driver");
2273 return 0;
f95f3850
WN		 2274}
2275
2276static void __exit dw_mci_exit(void)
2277{
f95f3850
WN		 2278}
2279
2280module_init(dw_mci_init);
2281module_exit(dw_mci_exit);
2282
2283MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
2284MODULE_AUTHOR("NXP Semiconductor VietNam");
2285MODULE_AUTHOR("Imagination Technologies Ltd");
2286MODULE_LICENSE("GPL v2");
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