[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / dw_mmc.h

/*
 * Synopsys DesignWare Multimedia Card Interface driver
 *  (Based on NXP driver for lpc 31xx)
 *
 * Copyright (C) 2009 NXP Semiconductors
 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef _DW_MMC_H_
#define _DW_MMC_H_

#include <linux/scatterlist.h>
#include <linux/mmc/core.h>
#include <linux/dmaengine.h>
#include <linux/reset.h>
#include <linux/interrupt.h>

#define MAX_MCI_SLOTS	2

enum dw_mci_state {
	STATE_IDLE = 0,
	STATE_SENDING_CMD,
	STATE_SENDING_DATA,
	STATE_DATA_BUSY,
	STATE_SENDING_STOP,
	STATE_DATA_ERROR,
	STATE_SENDING_CMD11,
	STATE_WAITING_CMD11_DONE,
};

enum {
	EVENT_CMD_COMPLETE = 0,
	EVENT_XFER_COMPLETE,
	EVENT_DATA_COMPLETE,
	EVENT_DATA_ERROR,
};

enum dw_mci_cookie {
	COOKIE_UNMAPPED,
	COOKIE_PRE_MAPPED,	/* mapped by pre_req() of dwmmc */
	COOKIE_MAPPED,		/* mapped by prepare_data() of dwmmc */
};

struct mmc_data;

enum {
	TRANS_MODE_PIO = 0,
	TRANS_MODE_IDMAC,
	TRANS_MODE_EDMAC
};

struct dw_mci_dma_slave {
	struct dma_chan *ch;
	enum dma_transfer_direction direction;
};

/**
 * struct dw_mci - MMC controller state shared between all slots
 * @lock: Spinlock protecting the queue and associated data.
 * @irq_lock: Spinlock protecting the INTMASK setting.
 * @regs: Pointer to MMIO registers.
 * @fifo_reg: Pointer to MMIO registers for data FIFO
 * @sg: Scatterlist entry currently being processed by PIO code, if any.
 * @sg_miter: PIO mapping scatterlist iterator.
 * @cur_slot: The slot which is currently using the controller.
 * @mrq: The request currently being processed on @cur_slot,
 *	or NULL if the controller is idle.
 * @cmd: The command currently being sent to the card, or NULL.
 * @data: The data currently being transferred, or NULL if no data
 *	transfer is in progress.
 * @stop_abort: The command currently prepared for stoping transfer.
 * @prev_blksz: The former transfer blksz record.
 * @timing: Record of current ios timing.
 * @use_dma: Whether DMA channel is initialized or not.
 * @using_dma: Whether DMA is in use for the current transfer.
 * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
 * @sg_dma: Bus address of DMA buffer.
 * @sg_cpu: Virtual address of DMA buffer.
 * @dma_ops: Pointer to platform-specific DMA callbacks.
 * @cmd_status: Snapshot of SR taken upon completion of the current
 * @ring_size: Buffer size for idma descriptors.
 *	command. Only valid when EVENT_CMD_COMPLETE is pending.
 * @dms: structure of slave-dma private data.
 * @phy_regs: physical address of controller's register map
 * @data_status: Snapshot of SR taken upon completion of the current
 *	data transfer. Only valid when EVENT_DATA_COMPLETE or
 *	EVENT_DATA_ERROR is pending.
 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
 *	to be sent.
 * @dir_status: Direction of current transfer.
 * @tasklet: Tasklet running the request state machine.
 * @pending_events: Bitmask of events flagged by the interrupt handler
 *	to be processed by the tasklet.
 * @completed_events: Bitmask of events which the state machine has
 *	processed.
 * @state: Tasklet state.
 * @queue: List of slots waiting for access to the controller.
 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
 *	rate and timeout calculations.
 * @current_speed: Configured rate of the controller.
 * @num_slots: Number of slots available.
 * @fifoth_val: The value of FIFOTH register.
 * @verid: Denote Version ID.
 * @dev: Device associated with the MMC controller.
 * @pdata: Platform data associated with the MMC controller.
 * @drv_data: Driver specific data for identified variant of the controller
 * @priv: Implementation defined private data.
 * @biu_clk: Pointer to bus interface unit clock instance.
 * @ciu_clk: Pointer to card interface unit clock instance.
 * @slot: Slots sharing this MMC controller.
 * @fifo_depth: depth of FIFO.
 * @data_addr_override: override fifo reg offset with this value.
 * @wm_aligned: force fifo watermark equal with data length in PIO mode.
 *	Set as true if alignment is needed.
 * @data_shift: log2 of FIFO item size.
 * @part_buf_start: Start index in part_buf.
 * @part_buf_count: Bytes of partial data in part_buf.
 * @part_buf: Simple buffer for partial fifo reads/writes.
 * @push_data: Pointer to FIFO push function.
 * @pull_data: Pointer to FIFO pull function.
 * @vqmmc_enabled: Status of vqmmc, should be true or false.
 * @irq_flags: The flags to be passed to request_irq.
 * @irq: The irq value to be passed to request_irq.
 * @sdio_id0: Number of slot0 in the SDIO interrupt registers.
 * @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
 * @dto_timer: Timer for broken data transfer over scheme.
 *
 * Locking
 * =======
 *
 * @lock is a softirq-safe spinlock protecting @queue as well as
 * @cur_slot, @mrq and @state. These must always be updated
 * at the same time while holding @lock.
 *
 * @irq_lock is an irq-safe spinlock protecting the INTMASK register
 * to allow the interrupt handler to modify it directly.  Held for only long
 * enough to read-modify-write INTMASK and no other locks are grabbed when
 * holding this one.
 *
 * The @mrq field of struct dw_mci_slot is also protected by @lock,
 * and must always be written at the same time as the slot is added to
 * @queue.
 *
 * @pending_events and @completed_events are accessed using atomic bit
 * operations, so they don't need any locking.
 *
 * None of the fields touched by the interrupt handler need any
 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
 * interrupts must be disabled and @data_status updated with a
 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
 * CMDRDY interrupt must be disabled and @cmd_status updated with a
 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
 * bytes_xfered field of @data must be written. This is ensured by
 * using barriers.
 */
struct dw_mci {
	spinlock_t		lock;
	spinlock_t		irq_lock;
	void __iomem		*regs;
	void __iomem		*fifo_reg;
	u32			data_addr_override;
	bool			wm_aligned;

	struct scatterlist	*sg;
	struct sg_mapping_iter	sg_miter;

	struct dw_mci_slot	*cur_slot;
	struct mmc_request	*mrq;
	struct mmc_command	*cmd;
	struct mmc_data		*data;
	struct mmc_command	stop_abort;
	unsigned int		prev_blksz;
	unsigned char		timing;

	/* DMA interface members*/
	int			use_dma;
	int			using_dma;
	int			dma_64bit_address;

	dma_addr_t		sg_dma;
	void			*sg_cpu;
	const struct dw_mci_dma_ops	*dma_ops;
	/* For idmac */
	unsigned int		ring_size;

	/* For edmac */
	struct dw_mci_dma_slave *dms;
	/* Registers's physical base address */
	resource_size_t		phy_regs;

	u32			cmd_status;
	u32			data_status;
	u32			stop_cmdr;
	u32			dir_status;
	struct tasklet_struct	tasklet;
	unsigned long		pending_events;
	unsigned long		completed_events;
	enum dw_mci_state	state;
	struct list_head	queue;

	u32			bus_hz;
	u32			current_speed;
	u32			num_slots;
	u32			fifoth_val;
	u16			verid;
	struct device		*dev;
	struct dw_mci_board	*pdata;
	const struct dw_mci_drv_data	*drv_data;
	void			*priv;
	struct clk		*biu_clk;
	struct clk		*ciu_clk;
	struct dw_mci_slot	*slot[MAX_MCI_SLOTS];

	/* FIFO push and pull */
	int			fifo_depth;
	int			data_shift;
	u8			part_buf_start;
	u8			part_buf_count;
	union {
		u16		part_buf16;
		u32		part_buf32;
		u64		part_buf;
	};
	void (*push_data)(struct dw_mci *host, void *buf, int cnt);
	void (*pull_data)(struct dw_mci *host, void *buf, int cnt);

	bool			vqmmc_enabled;
	unsigned long		irq_flags; /* IRQ flags */
	int			irq;

	int			sdio_id0;

	struct timer_list       cmd11_timer;
	struct timer_list       dto_timer;
};

/* DMA ops for Internal/External DMAC interface */
struct dw_mci_dma_ops {
	/* DMA Ops */
	int (*init)(struct dw_mci *host);
	int (*start)(struct dw_mci *host, unsigned int sg_len);
	void (*complete)(void *host);
	void (*stop)(struct dw_mci *host);
	void (*cleanup)(struct dw_mci *host);
	void (*exit)(struct dw_mci *host);
};

struct dma_pdata;

/* Board platform data */
struct dw_mci_board {
	u32 num_slots;

	unsigned int bus_hz; /* Clock speed at the cclk_in pad */

	u32 caps;	/* Capabilities */
	u32 caps2;	/* More capabilities */
	u32 pm_caps;	/* PM capabilities */
	/*
	 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
	 * but note that this may not be reliable after a bootloader has used
	 * it.
	 */
	unsigned int fifo_depth;

	/* delay in mS before detecting cards after interrupt */
	u32 detect_delay_ms;

	struct reset_control *rstc;
	struct dw_mci_dma_ops *dma_ops;
	struct dma_pdata *data;
};

#define DW_MMC_240A		0x240a
#define DW_MMC_280A		0x280a

#define SDMMC_CTRL		0x000
#define SDMMC_PWREN		0x004
#define SDMMC_CLKDIV		0x008
#define SDMMC_CLKSRC		0x00c
#define SDMMC_CLKENA		0x010
#define SDMMC_TMOUT		0x014
#define SDMMC_CTYPE		0x018
#define SDMMC_BLKSIZ		0x01c
#define SDMMC_BYTCNT		0x020
#define SDMMC_INTMASK		0x024
#define SDMMC_CMDARG		0x028
#define SDMMC_CMD		0x02c
#define SDMMC_RESP0		0x030
#define SDMMC_RESP1		0x034
#define SDMMC_RESP2		0x038
#define SDMMC_RESP3		0x03c
#define SDMMC_MINTSTS		0x040
#define SDMMC_RINTSTS		0x044
#define SDMMC_STATUS		0x048
#define SDMMC_FIFOTH		0x04c
#define SDMMC_CDETECT		0x050
#define SDMMC_WRTPRT		0x054
#define SDMMC_GPIO		0x058
#define SDMMC_TCBCNT		0x05c
#define SDMMC_TBBCNT		0x060
#define SDMMC_DEBNCE		0x064
#define SDMMC_USRID		0x068
#define SDMMC_VERID		0x06c
#define SDMMC_HCON		0x070
#define SDMMC_UHS_REG		0x074
#define SDMMC_RST_N		0x078
#define SDMMC_BMOD		0x080
#define SDMMC_PLDMND		0x084
#define SDMMC_DBADDR		0x088
#define SDMMC_IDSTS		0x08c
#define SDMMC_IDINTEN		0x090
#define SDMMC_DSCADDR		0x094
#define SDMMC_BUFADDR		0x098
#define SDMMC_CDTHRCTL		0x100
#define SDMMC_DATA(x)		(x)
/*
* Registers to support idmac 64-bit address mode
*/
#define SDMMC_DBADDRL		0x088
#define SDMMC_DBADDRU		0x08c
#define SDMMC_IDSTS64		0x090
#define SDMMC_IDINTEN64		0x094
#define SDMMC_DSCADDRL		0x098
#define SDMMC_DSCADDRU		0x09c
#define SDMMC_BUFADDRL		0x0A0
#define SDMMC_BUFADDRU		0x0A4

/*
 * Data offset is difference according to Version
 * Lower than 2.40a : data register offest is 0x100
 */
#define DATA_OFFSET		0x100
#define DATA_240A_OFFSET	0x200

/* shift bit field */
#define _SBF(f, v)		((v) << (f))

/* Control register defines */
#define SDMMC_CTRL_USE_IDMAC		BIT(25)
#define SDMMC_CTRL_CEATA_INT_EN		BIT(11)
#define SDMMC_CTRL_SEND_AS_CCSD		BIT(10)
#define SDMMC_CTRL_SEND_CCSD		BIT(9)
#define SDMMC_CTRL_ABRT_READ_DATA	BIT(8)
#define SDMMC_CTRL_SEND_IRQ_RESP	BIT(7)
#define SDMMC_CTRL_READ_WAIT		BIT(6)
#define SDMMC_CTRL_DMA_ENABLE		BIT(5)
#define SDMMC_CTRL_INT_ENABLE		BIT(4)
#define SDMMC_CTRL_DMA_RESET		BIT(2)
#define SDMMC_CTRL_FIFO_RESET		BIT(1)
#define SDMMC_CTRL_RESET		BIT(0)
/* Clock Enable register defines */
#define SDMMC_CLKEN_LOW_PWR		BIT(16)
#define SDMMC_CLKEN_ENABLE		BIT(0)
/* time-out register defines */
#define SDMMC_TMOUT_DATA(n)		_SBF(8, (n))
#define SDMMC_TMOUT_DATA_MSK		0xFFFFFF00
#define SDMMC_TMOUT_RESP(n)		((n) & 0xFF)
#define SDMMC_TMOUT_RESP_MSK		0xFF
/* card-type register defines */
#define SDMMC_CTYPE_8BIT		BIT(16)
#define SDMMC_CTYPE_4BIT		BIT(0)
#define SDMMC_CTYPE_1BIT		0
/* Interrupt status & mask register defines */
#define SDMMC_INT_SDIO(n)		BIT(16 + (n))
#define SDMMC_INT_EBE			BIT(15)
#define SDMMC_INT_ACD			BIT(14)
#define SDMMC_INT_SBE			BIT(13)
#define SDMMC_INT_HLE			BIT(12)
#define SDMMC_INT_FRUN			BIT(11)
#define SDMMC_INT_HTO			BIT(10)
#define SDMMC_INT_VOLT_SWITCH		BIT(10) /* overloads bit 10! */
#define SDMMC_INT_DRTO			BIT(9)
#define SDMMC_INT_RTO			BIT(8)
#define SDMMC_INT_DCRC			BIT(7)
#define SDMMC_INT_RCRC			BIT(6)
#define SDMMC_INT_RXDR			BIT(5)
#define SDMMC_INT_TXDR			BIT(4)
#define SDMMC_INT_DATA_OVER		BIT(3)
#define SDMMC_INT_CMD_DONE		BIT(2)
#define SDMMC_INT_RESP_ERR		BIT(1)
#define SDMMC_INT_CD			BIT(0)
#define SDMMC_INT_ERROR			0xbfc2
/* Command register defines */
#define SDMMC_CMD_START			BIT(31)
#define SDMMC_CMD_USE_HOLD_REG	BIT(29)
#define SDMMC_CMD_VOLT_SWITCH		BIT(28)
#define SDMMC_CMD_CCS_EXP		BIT(23)
#define SDMMC_CMD_CEATA_RD		BIT(22)
#define SDMMC_CMD_UPD_CLK		BIT(21)
#define SDMMC_CMD_INIT			BIT(15)
#define SDMMC_CMD_STOP			BIT(14)
#define SDMMC_CMD_PRV_DAT_WAIT		BIT(13)
#define SDMMC_CMD_SEND_STOP		BIT(12)
#define SDMMC_CMD_STRM_MODE		BIT(11)
#define SDMMC_CMD_DAT_WR		BIT(10)
#define SDMMC_CMD_DAT_EXP		BIT(9)
#define SDMMC_CMD_RESP_CRC		BIT(8)
#define SDMMC_CMD_RESP_LONG		BIT(7)
#define SDMMC_CMD_RESP_EXP		BIT(6)
#define SDMMC_CMD_INDX(n)		((n) & 0x1F)
/* Status register defines */
#define SDMMC_GET_FCNT(x)		(((x)>>17) & 0x1FFF)
#define SDMMC_STATUS_DMA_REQ		BIT(31)
#define SDMMC_STATUS_BUSY		BIT(9)
/* FIFOTH register defines */
#define SDMMC_SET_FIFOTH(m, r, t)	(((m) & 0x7) << 28 | \
					 ((r) & 0xFFF) << 16 | \
					 ((t) & 0xFFF))
/* HCON register defines */
#define DMA_INTERFACE_IDMA		(0x0)
#define DMA_INTERFACE_DWDMA		(0x1)
#define DMA_INTERFACE_GDMA		(0x2)
#define DMA_INTERFACE_NODMA		(0x3)
#define SDMMC_GET_TRANS_MODE(x)		(((x)>>16) & 0x3)
#define SDMMC_GET_SLOT_NUM(x)		((((x)>>1) & 0x1F) + 1)
#define SDMMC_GET_HDATA_WIDTH(x)	(((x)>>7) & 0x7)
#define SDMMC_GET_ADDR_CONFIG(x)	(((x)>>27) & 0x1)
/* Internal DMAC interrupt defines */
#define SDMMC_IDMAC_INT_AI		BIT(9)
#define SDMMC_IDMAC_INT_NI		BIT(8)
#define SDMMC_IDMAC_INT_CES		BIT(5)
#define SDMMC_IDMAC_INT_DU		BIT(4)
#define SDMMC_IDMAC_INT_FBE		BIT(2)
#define SDMMC_IDMAC_INT_RI		BIT(1)
#define SDMMC_IDMAC_INT_TI		BIT(0)
/* Internal DMAC bus mode bits */
#define SDMMC_IDMAC_ENABLE		BIT(7)
#define SDMMC_IDMAC_FB			BIT(1)
#define SDMMC_IDMAC_SWRESET		BIT(0)
/* H/W reset */
#define SDMMC_RST_HWACTIVE		0x1
/* Version ID register define */
#define SDMMC_GET_VERID(x)		((x) & 0xFFFF)
/* Card read threshold */
#define SDMMC_SET_THLD(v, x)		(((v) & 0xFFF) << 16 | (x))
#define SDMMC_CARD_WR_THR_EN		BIT(2)
#define SDMMC_CARD_RD_THR_EN		BIT(0)
/* UHS-1 register defines */
#define SDMMC_UHS_18V			BIT(0)
/* All ctrl reset bits */
#define SDMMC_CTRL_ALL_RESET_FLAGS \
	(SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET | SDMMC_CTRL_DMA_RESET)

/* FIFO register access macros. These should not change the data endian-ness
 * as they are written to memory to be dealt with by the upper layers */
#define mci_fifo_readw(__reg)	__raw_readw(__reg)
#define mci_fifo_readl(__reg)	__raw_readl(__reg)
#define mci_fifo_readq(__reg)	__raw_readq(__reg)

#define mci_fifo_writew(__value, __reg)	__raw_writew(__reg, __value)
#define mci_fifo_writel(__value, __reg)	__raw_writel(__reg, __value)
#define mci_fifo_writeq(__value, __reg)	__raw_writeq(__reg, __value)

/* Register access macros */
#define mci_readl(dev, reg)			\
	readl_relaxed((dev)->regs + SDMMC_##reg)
#define mci_writel(dev, reg, value)			\
	writel_relaxed((value), (dev)->regs + SDMMC_##reg)

/* 16-bit FIFO access macros */
#define mci_readw(dev, reg)			\
	readw_relaxed((dev)->regs + SDMMC_##reg)
#define mci_writew(dev, reg, value)			\
	writew_relaxed((value), (dev)->regs + SDMMC_##reg)

/* 64-bit FIFO access macros */
#ifdef readq
#define mci_readq(dev, reg)			\
	readq_relaxed((dev)->regs + SDMMC_##reg)
#define mci_writeq(dev, reg, value)			\
	writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
#else
/*
 * Dummy readq implementation for architectures that don't define it.
 *
 * We would assume that none of these architectures would configure
 * the IP block with a 64bit FIFO width, so this code will never be
 * executed on those machines. Defining these macros here keeps the
 * rest of the code free from ifdefs.
 */
#define mci_readq(dev, reg)			\
	(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
#define mci_writeq(dev, reg, value)			\
	(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))

#define __raw_writeq(__value, __reg) \
	(*(volatile u64 __force *)(__reg) = (__value))
#define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
#endif

extern int dw_mci_probe(struct dw_mci *host);
extern void dw_mci_remove(struct dw_mci *host);
#ifdef CONFIG_PM
extern int dw_mci_runtime_suspend(struct device *device);
extern int dw_mci_runtime_resume(struct device *device);
#endif

/**
 * struct dw_mci_slot - MMC slot state
 * @mmc: The mmc_host representing this slot.
 * @host: The MMC controller this slot is using.
 * @ctype: Card type for this slot.
 * @mrq: mmc_request currently being processed or waiting to be
 *	processed, or NULL when the slot is idle.
 * @queue_node: List node for placing this node in the @queue list of
 *	&struct dw_mci.
 * @clock: Clock rate configured by set_ios(). Protected by host->lock.
 * @__clk_old: The last clock value that was requested from core.
 *	Keeping track of this helps us to avoid spamming the console.
 * @flags: Random state bits associated with the slot.
 * @id: Number of this slot.
 * @sdio_id: Number of this slot in the SDIO interrupt registers.
 */
struct dw_mci_slot {
	struct mmc_host		*mmc;
	struct dw_mci		*host;

	u32			ctype;

	struct mmc_request	*mrq;
	struct list_head	queue_node;

	unsigned int		clock;
	unsigned int		__clk_old;

	unsigned long		flags;
#define DW_MMC_CARD_PRESENT	0
#define DW_MMC_CARD_NEED_INIT	1
#define DW_MMC_CARD_NO_LOW_PWR	2
#define DW_MMC_CARD_NO_USE_HOLD 3
#define DW_MMC_CARD_NEEDS_POLL	4
	int			id;
	int			sdio_id;
};

/**
 * dw_mci driver data - dw-mshc implementation specific driver data.
 * @caps: mmc subsystem specified capabilities of the controller(s).
 * @init: early implementation specific initialization.
 * @set_ios: handle bus specific extensions.
 * @parse_dt: parse implementation specific device tree properties.
 * @execute_tuning: implementation specific tuning procedure.
 *
 * Provide controller implementation specific extensions. The usage of this
 * data structure is fully optional and usage of each member in this structure
 * is optional as well.
 */
struct dw_mci_drv_data {
	unsigned long	*caps;
	int		(*init)(struct dw_mci *host);
	void		(*set_ios)(struct dw_mci *host, struct mmc_ios *ios);
	int		(*parse_dt)(struct dw_mci *host);
	int		(*execute_tuning)(struct dw_mci_slot *slot, u32 opcode);
	int		(*prepare_hs400_tuning)(struct dw_mci *host,
						struct mmc_ios *ios);
	int		(*switch_voltage)(struct mmc_host *mmc,
					  struct mmc_ios *ios);
};
#endif /* _DW_MMC_H_ */
Commit	Line	Data
f95f3850 WN	1	/*
	2	* Synopsys DesignWare Multimedia Card Interface driver
	3	* (Based on NXP driver for lpc 31xx)
	4	*
	5	* Copyright (C) 2009 NXP Semiconductors
	6	* Copyright (C) 2009, 2010 Imagination Technologies Ltd.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*/
	13
	14	#ifndef _DW_MMC_H_
	15	#define _DW_MMC_H_
	16
0f21c58c UH	17	#include <linux/scatterlist.h>
	18	#include <linux/mmc/core.h>
	19	#include <linux/dmaengine.h>
	20	#include <linux/reset.h>
b8789ec4	21	#include <linux/interrupt.h>
0f21c58c UH	22
	23	#define MAX_MCI_SLOTS 2
	24
	25	enum dw_mci_state {
	26	STATE_IDLE = 0,
	27	STATE_SENDING_CMD,
	28	STATE_SENDING_DATA,
	29	STATE_DATA_BUSY,
	30	STATE_SENDING_STOP,
	31	STATE_DATA_ERROR,
	32	STATE_SENDING_CMD11,
	33	STATE_WAITING_CMD11_DONE,
	34	};
	35
	36	enum {
	37	EVENT_CMD_COMPLETE = 0,
	38	EVENT_XFER_COMPLETE,
	39	EVENT_DATA_COMPLETE,
	40	EVENT_DATA_ERROR,
	41	};
	42
	43	enum dw_mci_cookie {
	44	COOKIE_UNMAPPED,
	45	COOKIE_PRE_MAPPED, /* mapped by pre_req() of dwmmc */
	46	COOKIE_MAPPED, /* mapped by prepare_data() of dwmmc */
	47	};
	48
	49	struct mmc_data;
	50
	51	enum {
	52	TRANS_MODE_PIO = 0,
	53	TRANS_MODE_IDMAC,
	54	TRANS_MODE_EDMAC
	55	};
	56
	57	struct dw_mci_dma_slave {
	58	struct dma_chan *ch;
	59	enum dma_transfer_direction direction;
	60	};
	61
	62	/**
	63	* struct dw_mci - MMC controller state shared between all slots
	64	* @lock: Spinlock protecting the queue and associated data.
	65	* @irq_lock: Spinlock protecting the INTMASK setting.
	66	* @regs: Pointer to MMIO registers.
	67	* @fifo_reg: Pointer to MMIO registers for data FIFO
	68	* @sg: Scatterlist entry currently being processed by PIO code, if any.
	69	* @sg_miter: PIO mapping scatterlist iterator.
	70	* @cur_slot: The slot which is currently using the controller.
	71	* @mrq: The request currently being processed on @cur_slot,
	72	* or NULL if the controller is idle.
	73	* @cmd: The command currently being sent to the card, or NULL.
	74	* @data: The data currently being transferred, or NULL if no data
	75	* transfer is in progress.
	76	* @stop_abort: The command currently prepared for stoping transfer.
	77	* @prev_blksz: The former transfer blksz record.
	78	* @timing: Record of current ios timing.
	79	* @use_dma: Whether DMA channel is initialized or not.
	80	* @using_dma: Whether DMA is in use for the current transfer.
	81	* @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
	82	* @sg_dma: Bus address of DMA buffer.
	83	* @sg_cpu: Virtual address of DMA buffer.
	84	* @dma_ops: Pointer to platform-specific DMA callbacks.
	85	* @cmd_status: Snapshot of SR taken upon completion of the current
86	* @ring_size: Buffer size for idma descriptors.
87	* command. Only valid when EVENT_CMD_COMPLETE is pending.
88	* @dms: structure of slave-dma private data.
89	* @phy_regs: physical address of controller's register map
90	* @data_status: Snapshot of SR taken upon completion of the current
91	* data transfer. Only valid when EVENT_DATA_COMPLETE or
92	* EVENT_DATA_ERROR is pending.
93	* @stop_cmdr: Value to be loaded into CMDR when the stop command is
94	* to be sent.
95	* @dir_status: Direction of current transfer.
96	* @tasklet: Tasklet running the request state machine.
97	* @pending_events: Bitmask of events flagged by the interrupt handler
98	* to be processed by the tasklet.
99	* @completed_events: Bitmask of events which the state machine has
100	* processed.
101	* @state: Tasklet state.
102	* @queue: List of slots waiting for access to the controller.
103	* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
104	* rate and timeout calculations.
105	* @current_speed: Configured rate of the controller.
106	* @num_slots: Number of slots available.
107	* @fifoth_val: The value of FIFOTH register.
108	* @verid: Denote Version ID.
109	* @dev: Device associated with the MMC controller.
110	* @pdata: Platform data associated with the MMC controller.
111	* @drv_data: Driver specific data for identified variant of the controller
112	* @priv: Implementation defined private data.
113	* @biu_clk: Pointer to bus interface unit clock instance.
114	* @ciu_clk: Pointer to card interface unit clock instance.
115	* @slot: Slots sharing this MMC controller.
116	* @fifo_depth: depth of FIFO.
a0361c1a	117	* @data_addr_override: override fifo reg offset with this value.
d6fced83 JN	118	* @wm_aligned: force fifo watermark equal with data length in PIO mode.
d6fced83 JN	119	* Set as true if alignment is needed.
0f21c58c UH	120	* @data_shift: log2 of FIFO item size.
	121	* @part_buf_start: Start index in part_buf.
	122	* @part_buf_count: Bytes of partial data in part_buf.
	123	* @part_buf: Simple buffer for partial fifo reads/writes.
	124	* @push_data: Pointer to FIFO push function.
	125	* @pull_data: Pointer to FIFO pull function.
	126	* @vqmmc_enabled: Status of vqmmc, should be true or false.
	127	* @irq_flags: The flags to be passed to request_irq.
	128	* @irq: The irq value to be passed to request_irq.
	129	* @sdio_id0: Number of slot0 in the SDIO interrupt registers.
	130	* @cmd11_timer: Timer for SD3.0 voltage switch over scheme.
	131	* @dto_timer: Timer for broken data transfer over scheme.
	132	*
	133	* Locking
	134	* =======
	135	*
	136	* @lock is a softirq-safe spinlock protecting @queue as well as
	137	* @cur_slot, @mrq and @state. These must always be updated
	138	* at the same time while holding @lock.
	139	*
	140	* @irq_lock is an irq-safe spinlock protecting the INTMASK register
	141	* to allow the interrupt handler to modify it directly. Held for only long
	142	* enough to read-modify-write INTMASK and no other locks are grabbed when
	143	* holding this one.
	144	*
	145	* The @mrq field of struct dw_mci_slot is also protected by @lock,
	146	* and must always be written at the same time as the slot is added to
	147	* @queue.
	148	*
	149	* @pending_events and @completed_events are accessed using atomic bit
	150	* operations, so they don't need any locking.
	151	*
	152	* None of the fields touched by the interrupt handler need any
	153	* locking. However, ordering is important: Before EVENT_DATA_ERROR or
	154	* EVENT_DATA_COMPLETE is set in @pending_events, all data-related
	155	* interrupts must be disabled and @data_status updated with a
	156	* snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
	157	* CMDRDY interrupt must be disabled and @cmd_status updated with a
	158	* snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
	159	* bytes_xfered field of @data must be written. This is ensured by
	160	* using barriers.
	161	*/
	162	struct dw_mci {
	163	spinlock_t lock;
	164	spinlock_t irq_lock;
	165	void __iomem *regs;
	166	void __iomem *fifo_reg;
a0361c1a	167	u32 data_addr_override;
d6fced83	168	bool wm_aligned;
0f21c58c UH	169
	170	struct scatterlist *sg;
	171	struct sg_mapping_iter sg_miter;
	172
	173	struct dw_mci_slot *cur_slot;
	174	struct mmc_request *mrq;
	175	struct mmc_command *cmd;
	176	struct mmc_data *data;
	177	struct mmc_command stop_abort;
	178	unsigned int prev_blksz;
	179	unsigned char timing;
	180
	181	/* DMA interface members*/
	182	int use_dma;
	183	int using_dma;
	184	int dma_64bit_address;
	185
	186	dma_addr_t sg_dma;
	187	void *sg_cpu;
	188	const struct dw_mci_dma_ops *dma_ops;
	189	/* For idmac */
	190	unsigned int ring_size;
	191
	192	/* For edmac */
	193	struct dw_mci_dma_slave *dms;
	194	/* Registers's physical base address */
	195	resource_size_t phy_regs;
	196
	197	u32 cmd_status;
	198	u32 data_status;
	199	u32 stop_cmdr;
	200	u32 dir_status;
	201	struct tasklet_struct tasklet;
	202	unsigned long pending_events;
	203	unsigned long completed_events;
	204	enum dw_mci_state state;
	205	struct list_head queue;
	206
	207	u32 bus_hz;
	208	u32 current_speed;
	209	u32 num_slots;
	210	u32 fifoth_val;
	211	u16 verid;
	212	struct device *dev;
	213	struct dw_mci_board *pdata;
	214	const struct dw_mci_drv_data *drv_data;
	215	void *priv;
	216	struct clk *biu_clk;
	217	struct clk *ciu_clk;
	218	struct dw_mci_slot *slot[MAX_MCI_SLOTS];
	219
	220	/* FIFO push and pull */
	221	int fifo_depth;
	222	int data_shift;
	223	u8 part_buf_start;
	224	u8 part_buf_count;
	225	union {
	226	u16 part_buf16;
	227	u32 part_buf32;
	228	u64 part_buf;
	229	};
	230	void (push_data)(struct dw_mci host, void *buf, int cnt);
	231	void (pull_data)(struct dw_mci host, void *buf, int cnt);
	232
233	bool vqmmc_enabled;
234	unsigned long irq_flags; /* IRQ flags */
235	int irq;
236
237	int sdio_id0;
238
239	struct timer_list cmd11_timer;
240	struct timer_list dto_timer;
241	};
242
243	/* DMA ops for Internal/External DMAC interface */
244	struct dw_mci_dma_ops {
245	/* DMA Ops */
246	int (init)(struct dw_mci host);
247	int (start)(struct dw_mci host, unsigned int sg_len);
248	void (complete)(void host);
249	void (stop)(struct dw_mci host);
250	void (cleanup)(struct dw_mci host);
251	void (exit)(struct dw_mci host);
252	};
253
254	struct dma_pdata;
255
256	/* Board platform data */
257	struct dw_mci_board {
258	u32 num_slots;
259
260	unsigned int bus_hz; /* Clock speed at the cclk_in pad */
261
262	u32 caps; /* Capabilities */
263	u32 caps2; /* More capabilities */
264	u32 pm_caps; /* PM capabilities */
265	/*
266	* Override fifo depth. If 0, autodetect it from the FIFOTH register,
267	* but note that this may not be reliable after a bootloader has used
268	* it.
269	*/
270	unsigned int fifo_depth;
271
272	/* delay in mS before detecting cards after interrupt */
273	u32 detect_delay_ms;
274
275	struct reset_control *rstc;
276	struct dw_mci_dma_ops *dma_ops;
277	struct dma_pdata *data;
278	};
279
4e0a5adf	280	#define DW_MMC_240A 0x240a
7e4bf1bc	281	#define DW_MMC_280A 0x280a
4e0a5adf	282
f95f3850 WN	283	#define SDMMC_CTRL 0x000
	284	#define SDMMC_PWREN 0x004
	285	#define SDMMC_CLKDIV 0x008
	286	#define SDMMC_CLKSRC 0x00c
	287	#define SDMMC_CLKENA 0x010
	288	#define SDMMC_TMOUT 0x014
	289	#define SDMMC_CTYPE 0x018
	290	#define SDMMC_BLKSIZ 0x01c
	291	#define SDMMC_BYTCNT 0x020
	292	#define SDMMC_INTMASK 0x024
	293	#define SDMMC_CMDARG 0x028
	294	#define SDMMC_CMD 0x02c
	295	#define SDMMC_RESP0 0x030
	296	#define SDMMC_RESP1 0x034
	297	#define SDMMC_RESP2 0x038
	298	#define SDMMC_RESP3 0x03c
	299	#define SDMMC_MINTSTS 0x040
	300	#define SDMMC_RINTSTS 0x044
	301	#define SDMMC_STATUS 0x048
	302	#define SDMMC_FIFOTH 0x04c
	303	#define SDMMC_CDETECT 0x050
	304	#define SDMMC_WRTPRT 0x054
	305	#define SDMMC_GPIO 0x058
	306	#define SDMMC_TCBCNT 0x05c
	307	#define SDMMC_TBBCNT 0x060
	308	#define SDMMC_DEBNCE 0x064
	309	#define SDMMC_USRID 0x068
	310	#define SDMMC_VERID 0x06c
	311	#define SDMMC_HCON 0x070
41babf75	312	#define SDMMC_UHS_REG 0x074
935a665e	313	#define SDMMC_RST_N 0x078
f95f3850 WN	314	#define SDMMC_BMOD 0x080
	315	#define SDMMC_PLDMND 0x084
	316	#define SDMMC_DBADDR 0x088
	317	#define SDMMC_IDSTS 0x08c
	318	#define SDMMC_IDINTEN 0x090
	319	#define SDMMC_DSCADDR 0x094
	320	#define SDMMC_BUFADDR 0x098
f1d2736c	321	#define SDMMC_CDTHRCTL 0x100
4e0a5adf	322	#define SDMMC_DATA(x) (x)
69d99fdc PT	323	/*
	324	* Registers to support idmac 64-bit address mode
	325	*/
	326	#define SDMMC_DBADDRL 0x088
	327	#define SDMMC_DBADDRU 0x08c
	328	#define SDMMC_IDSTS64 0x090
	329	#define SDMMC_IDINTEN64 0x094
	330	#define SDMMC_DSCADDRL 0x098
	331	#define SDMMC_DSCADDRU 0x09c
	332	#define SDMMC_BUFADDRL 0x0A0
	333	#define SDMMC_BUFADDRU 0x0A4
4e0a5adf JC	334
	335	/*
	336	* Data offset is difference according to Version
	337	* Lower than 2.40a : data register offest is 0x100
	338	*/
	339	#define DATA_OFFSET 0x100
	340	#define DATA_240A_OFFSET 0x200
f95f3850 WN	341
	342	/* shift bit field */
	343	#define _SBF(f, v) ((v) << (f))
	344
	345	/* Control register defines */
	346	#define SDMMC_CTRL_USE_IDMAC BIT(25)
	347	#define SDMMC_CTRL_CEATA_INT_EN BIT(11)
	348	#define SDMMC_CTRL_SEND_AS_CCSD BIT(10)
	349	#define SDMMC_CTRL_SEND_CCSD BIT(9)
	350	#define SDMMC_CTRL_ABRT_READ_DATA BIT(8)
	351	#define SDMMC_CTRL_SEND_IRQ_RESP BIT(7)
	352	#define SDMMC_CTRL_READ_WAIT BIT(6)
	353	#define SDMMC_CTRL_DMA_ENABLE BIT(5)
	354	#define SDMMC_CTRL_INT_ENABLE BIT(4)
	355	#define SDMMC_CTRL_DMA_RESET BIT(2)
	356	#define SDMMC_CTRL_FIFO_RESET BIT(1)
	357	#define SDMMC_CTRL_RESET BIT(0)
	358	/* Clock Enable register defines */
	359	#define SDMMC_CLKEN_LOW_PWR BIT(16)
	360	#define SDMMC_CLKEN_ENABLE BIT(0)
	361	/* time-out register defines */
	362	#define SDMMC_TMOUT_DATA(n) _SBF(8, (n))
	363	#define SDMMC_TMOUT_DATA_MSK 0xFFFFFF00
	364	#define SDMMC_TMOUT_RESP(n) ((n) & 0xFF)
	365	#define SDMMC_TMOUT_RESP_MSK 0xFF
	366	/* card-type register defines */
	367	#define SDMMC_CTYPE_8BIT BIT(16)
	368	#define SDMMC_CTYPE_4BIT BIT(0)
	369	#define SDMMC_CTYPE_1BIT 0
	370	/* Interrupt status & mask register defines */
1a5c8e1f	371	#define SDMMC_INT_SDIO(n) BIT(16 + (n))
f95f3850 WN	372	#define SDMMC_INT_EBE BIT(15)
	373	#define SDMMC_INT_ACD BIT(14)
	374	#define SDMMC_INT_SBE BIT(13)
	375	#define SDMMC_INT_HLE BIT(12)
	376	#define SDMMC_INT_FRUN BIT(11)
	377	#define SDMMC_INT_HTO BIT(10)
01730558	378	#define SDMMC_INT_VOLT_SWITCH BIT(10) /* overloads bit 10! */
3f7eec62	379	#define SDMMC_INT_DRTO BIT(9)
f95f3850 WN	380	#define SDMMC_INT_RTO BIT(8)
	381	#define SDMMC_INT_DCRC BIT(7)
	382	#define SDMMC_INT_RCRC BIT(6)
	383	#define SDMMC_INT_RXDR BIT(5)
	384	#define SDMMC_INT_TXDR BIT(4)
	385	#define SDMMC_INT_DATA_OVER BIT(3)
	386	#define SDMMC_INT_CMD_DONE BIT(2)
	387	#define SDMMC_INT_RESP_ERR BIT(1)
	388	#define SDMMC_INT_CD BIT(0)
	389	#define SDMMC_INT_ERROR 0xbfc2
	390	/* Command register defines */
	391	#define SDMMC_CMD_START BIT(31)
eede2111	392	#define SDMMC_CMD_USE_HOLD_REG BIT(29)
01730558	393	#define SDMMC_CMD_VOLT_SWITCH BIT(28)
f95f3850 WN	394	#define SDMMC_CMD_CCS_EXP BIT(23)
	395	#define SDMMC_CMD_CEATA_RD BIT(22)
	396	#define SDMMC_CMD_UPD_CLK BIT(21)
	397	#define SDMMC_CMD_INIT BIT(15)
	398	#define SDMMC_CMD_STOP BIT(14)
	399	#define SDMMC_CMD_PRV_DAT_WAIT BIT(13)
	400	#define SDMMC_CMD_SEND_STOP BIT(12)
	401	#define SDMMC_CMD_STRM_MODE BIT(11)
	402	#define SDMMC_CMD_DAT_WR BIT(10)
	403	#define SDMMC_CMD_DAT_EXP BIT(9)
	404	#define SDMMC_CMD_RESP_CRC BIT(8)
	405	#define SDMMC_CMD_RESP_LONG BIT(7)
	406	#define SDMMC_CMD_RESP_EXP BIT(6)
	407	#define SDMMC_CMD_INDX(n) ((n) & 0x1F)
	408	/* Status register defines */
ee5d19b2	409	#define SDMMC_GET_FCNT(x) (((x)>>17) & 0x1FFF)
3a33a94c	410	#define SDMMC_STATUS_DMA_REQ BIT(31)
01730558	411	#define SDMMC_STATUS_BUSY BIT(9)
52426899 SJ	412	/* FIFOTH register defines */
	413	#define SDMMC_SET_FIFOTH(m, r, t) (((m) & 0x7) << 28 \| \
	414	((r) & 0xFFF) << 16 \| \
	415	((t) & 0xFFF))
3fc7eaef SL	416	/* HCON register defines */
	417	#define DMA_INTERFACE_IDMA (0x0)
	418	#define DMA_INTERFACE_DWDMA (0x1)
	419	#define DMA_INTERFACE_GDMA (0x2)
	420	#define DMA_INTERFACE_NODMA (0x3)
	421	#define SDMMC_GET_TRANS_MODE(x) (((x)>>16) & 0x3)
70692752 SL	422	#define SDMMC_GET_SLOT_NUM(x) ((((x)>>1) & 0x1F) + 1)
	423	#define SDMMC_GET_HDATA_WIDTH(x) (((x)>>7) & 0x7)
	424	#define SDMMC_GET_ADDR_CONFIG(x) (((x)>>27) & 0x1)
f95f3850 WN	425	/* Internal DMAC interrupt defines */
	426	#define SDMMC_IDMAC_INT_AI BIT(9)
	427	#define SDMMC_IDMAC_INT_NI BIT(8)
	428	#define SDMMC_IDMAC_INT_CES BIT(5)
	429	#define SDMMC_IDMAC_INT_DU BIT(4)
	430	#define SDMMC_IDMAC_INT_FBE BIT(2)
	431	#define SDMMC_IDMAC_INT_RI BIT(1)
	432	#define SDMMC_IDMAC_INT_TI BIT(0)
	433	/* Internal DMAC bus mode bits */
	434	#define SDMMC_IDMAC_ENABLE BIT(7)
	435	#define SDMMC_IDMAC_FB BIT(1)
	436	#define SDMMC_IDMAC_SWRESET BIT(0)
935a665e SL	437	/* H/W reset */
935a665e SL	438	#define SDMMC_RST_HWACTIVE 0x1
4e0a5adf JC	439	/* Version ID register define */
4e0a5adf JC	440	#define SDMMC_GET_VERID(x) ((x) & 0xFFFF)
f1d2736c	441	/* Card read threshold */
7e4bf1bc JC	442	#define SDMMC_SET_THLD(v, x) (((v) & 0xFFF) << 16 \| (x))
	443	#define SDMMC_CARD_WR_THR_EN BIT(2)
	444	#define SDMMC_CARD_RD_THR_EN BIT(0)
	445	/* UHS-1 register defines */
01730558	446	#define SDMMC_UHS_18V BIT(0)
3a33a94c SR	447	/* All ctrl reset bits */
	448	#define SDMMC_CTRL_ALL_RESET_FLAGS \
	449	(SDMMC_CTRL_RESET \| SDMMC_CTRL_FIFO_RESET \| SDMMC_CTRL_DMA_RESET)
	450
76184ac1 BD	451	/* FIFO register access macros. These should not change the data endian-ness
	452	* as they are written to memory to be dealt with by the upper layers */
	453	#define mci_fifo_readw(__reg) __raw_readw(__reg)
	454	#define mci_fifo_readl(__reg) __raw_readl(__reg)
	455	#define mci_fifo_readq(__reg) __raw_readq(__reg)
	456
	457	#define mci_fifo_writew(__value, __reg) __raw_writew(__reg, __value)
	458	#define mci_fifo_writel(__value, __reg) __raw_writel(__reg, __value)
	459	#define mci_fifo_writeq(__value, __reg) __raw_writeq(__reg, __value)
	460
f95f3850 WN	461	/* Register access macros */
f95f3850 WN	462	#define mci_readl(dev, reg) \
a2f17680	463	readl_relaxed((dev)->regs + SDMMC_##reg)
f95f3850	464	#define mci_writel(dev, reg, value) \
a2f17680	465	writel_relaxed((value), (dev)->regs + SDMMC_##reg)
f95f3850 WN	466
	467	/* 16-bit FIFO access macros */
	468	#define mci_readw(dev, reg) \
a2f17680	469	readw_relaxed((dev)->regs + SDMMC_##reg)
f95f3850	470	#define mci_writew(dev, reg, value) \
a2f17680	471	writew_relaxed((value), (dev)->regs + SDMMC_##reg)
f95f3850 WN	472
	473	/* 64-bit FIFO access macros */
	474	#ifdef readq
	475	#define mci_readq(dev, reg) \
a2f17680	476	readq_relaxed((dev)->regs + SDMMC_##reg)
f95f3850	477	#define mci_writeq(dev, reg, value) \
a2f17680	478	writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
f95f3850 WN	479	#else
	480	/*
	481	* Dummy readq implementation for architectures that don't define it.
	482	*
	483	* We would assume that none of these architectures would configure
	484	* the IP block with a 64bit FIFO width, so this code will never be
	485	* executed on those machines. Defining these macros here keeps the
	486	* rest of the code free from ifdefs.
	487	*/
	488	#define mci_readq(dev, reg) \
892b1e31	489	((volatile u64 __force )((dev)->regs + SDMMC_##reg))
f95f3850	490	#define mci_writeq(dev, reg, value) \
892b1e31	491	((volatile u64 __force )((dev)->regs + SDMMC_##reg) = (value))
76184ac1 BD	492
	493	#define __raw_writeq(__value, __reg) \
	494	((volatile u64 __force )(__reg) = (__value))
	495	#define __raw_readq(__reg) ((volatile u64 __force )(__reg))
f95f3850 WN	496	#endif
f95f3850 WN	497
62ca8034 SH	498	extern int dw_mci_probe(struct dw_mci *host);
62ca8034 SH	499	extern void dw_mci_remove(struct dw_mci *host);
e9ed8835	500	#ifdef CONFIG_PM
e9ed8835 SL	501	extern int dw_mci_runtime_suspend(struct device *device);
e9ed8835 SL	502	extern int dw_mci_runtime_resume(struct device *device);
62ca8034 SH	503	#endif
62ca8034 SH	504
0976f16d SJ	505	/**
	506	* struct dw_mci_slot - MMC slot state
	507	* @mmc: The mmc_host representing this slot.
	508	* @host: The MMC controller this slot is using.
0976f16d SJ	509	* @ctype: Card type for this slot.
	510	* @mrq: mmc_request currently being processed or waiting to be
	511	* processed, or NULL when the slot is idle.
	512	* @queue_node: List node for placing this node in the @queue list of
	513	* &struct dw_mci.
	514	* @clock: Clock rate configured by set_ios(). Protected by host->lock.
005d675a JC	515	* @__clk_old: The last clock value that was requested from core.
005d675a JC	516	* Keeping track of this helps us to avoid spamming the console.
0976f16d SJ	517	* @flags: Random state bits associated with the slot.
0976f16d SJ	518	* @id: Number of this slot.
76756234	519	* @sdio_id: Number of this slot in the SDIO interrupt registers.
0976f16d SJ	520	*/
	521	struct dw_mci_slot {
	522	struct mmc_host *mmc;
	523	struct dw_mci *host;
	524
0976f16d SJ	525	u32 ctype;
	526
	527	struct mmc_request *mrq;
	528	struct list_head queue_node;
	529
	530	unsigned int clock;
005d675a	531	unsigned int __clk_old;
0976f16d SJ	532
	533	unsigned long flags;
	534	#define DW_MMC_CARD_PRESENT 0
	535	#define DW_MMC_CARD_NEED_INIT 1
b24c8b26	536	#define DW_MMC_CARD_NO_LOW_PWR 2
aaaaeb7a	537	#define DW_MMC_CARD_NO_USE_HOLD 3
e6cd7a8e	538	#define DW_MMC_CARD_NEEDS_POLL 4
0976f16d	539	int id;
76756234	540	int sdio_id;
0976f16d SJ	541	};
0976f16d SJ	542
800d78bf TA	543	/**
	544	* dw_mci driver data - dw-mshc implementation specific driver data.
	545	* @caps: mmc subsystem specified capabilities of the controller(s).
	546	* @init: early implementation specific initialization.
800d78bf TA	547	* @set_ios: handle bus specific extensions.
800d78bf TA	548	* @parse_dt: parse implementation specific device tree properties.
5532ec51	549	* @execute_tuning: implementation specific tuning procedure.
800d78bf TA	550	*
	551	* Provide controller implementation specific extensions. The usage of this
	552	* data structure is fully optional and usage of each member in this structure
	553	* is optional as well.
	554	*/
	555	struct dw_mci_drv_data {
	556	unsigned long *caps;
	557	int (init)(struct dw_mci host);
800d78bf TA	558	void (set_ios)(struct dw_mci host, struct mmc_ios *ios);
800d78bf TA	559	int (parse_dt)(struct dw_mci host);
9979dbe5	560	int (execute_tuning)(struct dw_mci_slot slot, u32 opcode);
80113132 SJ	561	int (prepare_hs400_tuning)(struct dw_mci host,
80113132 SJ	562	struct mmc_ios *ios);
8f7849c4 ZG	563	int (switch_voltage)(struct mmc_host mmc,
8f7849c4 ZG	564	struct mmc_ios *ios);
800d78bf	565	};
f95f3850	566	#endif /* _DW_MMC_H_ */