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ed80a13b CC |
1 | /* |
2 | * meson-mx-sdio.c - Meson6, Meson8 and Meson8b SDIO/MMC Host Controller | |
3 | * | |
4 | * Copyright (C) 2015 Endless Mobile, Inc. | |
5 | * Author: Carlo Caione <carlo@endlessm.com> | |
6 | * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or (at | |
11 | * your option) any later version. | |
12 | */ | |
13 | ||
14 | #include <linux/bitfield.h> | |
15 | #include <linux/clk.h> | |
16 | #include <linux/clk-provider.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/module.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/ioport.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/of_platform.h> | |
25 | #include <linux/timer.h> | |
26 | #include <linux/types.h> | |
27 | ||
28 | #include <linux/mmc/host.h> | |
29 | #include <linux/mmc/mmc.h> | |
30 | #include <linux/mmc/sdio.h> | |
31 | #include <linux/mmc/slot-gpio.h> | |
32 | ||
33 | #define MESON_MX_SDIO_ARGU 0x00 | |
34 | ||
35 | #define MESON_MX_SDIO_SEND 0x04 | |
36 | #define MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK GENMASK(7, 0) | |
37 | #define MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK GENMASK(15, 8) | |
38 | #define MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7 BIT(16) | |
39 | #define MESON_MX_SDIO_SEND_RESP_HAS_DATA BIT(17) | |
40 | #define MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8 BIT(18) | |
41 | #define MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY BIT(19) | |
42 | #define MESON_MX_SDIO_SEND_DATA BIT(20) | |
43 | #define MESON_MX_SDIO_SEND_USE_INT_WINDOW BIT(21) | |
44 | #define MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK GENMASK(31, 24) | |
45 | ||
46 | #define MESON_MX_SDIO_CONF 0x08 | |
47 | #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT 0 | |
48 | #define MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH 10 | |
49 | #define MESON_MX_SDIO_CONF_CMD_DISABLE_CRC BIT(10) | |
50 | #define MESON_MX_SDIO_CONF_CMD_OUT_AT_POSITIVE_EDGE BIT(11) | |
51 | #define MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK GENMASK(17, 12) | |
52 | #define MESON_MX_SDIO_CONF_RESP_LATCH_AT_NEGATIVE_EDGE BIT(18) | |
53 | #define MESON_MX_SDIO_CONF_DATA_LATCH_AT_NEGATIVE_EDGE BIT(19) | |
54 | #define MESON_MX_SDIO_CONF_BUS_WIDTH BIT(20) | |
55 | #define MESON_MX_SDIO_CONF_M_ENDIAN_MASK GENMASK(22, 21) | |
56 | #define MESON_MX_SDIO_CONF_WRITE_NWR_MASK GENMASK(28, 23) | |
57 | #define MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK GENMASK(31, 29) | |
58 | ||
59 | #define MESON_MX_SDIO_IRQS 0x0c | |
60 | #define MESON_MX_SDIO_IRQS_STATUS_STATE_MACHINE_MASK GENMASK(3, 0) | |
61 | #define MESON_MX_SDIO_IRQS_CMD_BUSY BIT(4) | |
62 | #define MESON_MX_SDIO_IRQS_RESP_CRC7_OK BIT(5) | |
63 | #define MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK BIT(6) | |
64 | #define MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK BIT(7) | |
65 | #define MESON_MX_SDIO_IRQS_IF_INT BIT(8) | |
66 | #define MESON_MX_SDIO_IRQS_CMD_INT BIT(9) | |
67 | #define MESON_MX_SDIO_IRQS_STATUS_INFO_MASK GENMASK(15, 12) | |
68 | #define MESON_MX_SDIO_IRQS_TIMING_OUT_INT BIT(16) | |
69 | #define MESON_MX_SDIO_IRQS_AMRISC_TIMING_OUT_INT_EN BIT(17) | |
70 | #define MESON_MX_SDIO_IRQS_ARC_TIMING_OUT_INT_EN BIT(18) | |
71 | #define MESON_MX_SDIO_IRQS_TIMING_OUT_COUNT_MASK GENMASK(31, 19) | |
72 | ||
73 | #define MESON_MX_SDIO_IRQC 0x10 | |
74 | #define MESON_MX_SDIO_IRQC_ARC_IF_INT_EN BIT(3) | |
75 | #define MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN BIT(4) | |
76 | #define MESON_MX_SDIO_IRQC_IF_CONFIG_MASK GENMASK(7, 6) | |
77 | #define MESON_MX_SDIO_IRQC_FORCE_DATA_CLK BIT(8) | |
78 | #define MESON_MX_SDIO_IRQC_FORCE_DATA_CMD BIT(9) | |
79 | #define MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK GENMASK(10, 13) | |
80 | #define MESON_MX_SDIO_IRQC_SOFT_RESET BIT(15) | |
81 | #define MESON_MX_SDIO_IRQC_FORCE_HALT BIT(30) | |
82 | #define MESON_MX_SDIO_IRQC_HALT_HOLE BIT(31) | |
83 | ||
84 | #define MESON_MX_SDIO_MULT 0x14 | |
85 | #define MESON_MX_SDIO_MULT_PORT_SEL_MASK GENMASK(1, 0) | |
86 | #define MESON_MX_SDIO_MULT_MEMORY_STICK_ENABLE BIT(2) | |
87 | #define MESON_MX_SDIO_MULT_MEMORY_STICK_SCLK_ALWAYS BIT(3) | |
88 | #define MESON_MX_SDIO_MULT_STREAM_ENABLE BIT(4) | |
89 | #define MESON_MX_SDIO_MULT_STREAM_8BITS_MODE BIT(5) | |
90 | #define MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX BIT(8) | |
91 | #define MESON_MX_SDIO_MULT_DAT0_DAT1_SWAPPED BIT(10) | |
92 | #define MESON_MX_SDIO_MULT_DAT1_DAT0_SWAPPED BIT(11) | |
93 | #define MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK GENMASK(15, 12) | |
94 | ||
95 | #define MESON_MX_SDIO_ADDR 0x18 | |
96 | ||
97 | #define MESON_MX_SDIO_EXT 0x1c | |
98 | #define MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK GENMASK(29, 16) | |
99 | ||
100 | #define MESON_MX_SDIO_BOUNCE_REQ_SIZE (128 * 1024) | |
101 | #define MESON_MX_SDIO_RESPONSE_CRC16_BITS (16 - 1) | |
102 | #define MESON_MX_SDIO_MAX_SLOTS 3 | |
103 | ||
104 | struct meson_mx_mmc_host { | |
105 | struct device *controller_dev; | |
106 | ||
107 | struct clk *parent_clk; | |
108 | struct clk *core_clk; | |
109 | struct clk_divider cfg_div; | |
110 | struct clk *cfg_div_clk; | |
111 | struct clk_fixed_factor fixed_factor; | |
112 | struct clk *fixed_factor_clk; | |
113 | ||
114 | void __iomem *base; | |
115 | int irq; | |
116 | spinlock_t irq_lock; | |
117 | ||
118 | struct timer_list cmd_timeout; | |
119 | ||
120 | unsigned int slot_id; | |
121 | struct mmc_host *mmc; | |
122 | ||
123 | struct mmc_request *mrq; | |
124 | struct mmc_command *cmd; | |
125 | int error; | |
126 | }; | |
127 | ||
128 | static void meson_mx_mmc_mask_bits(struct mmc_host *mmc, char reg, u32 mask, | |
129 | u32 val) | |
130 | { | |
131 | struct meson_mx_mmc_host *host = mmc_priv(mmc); | |
132 | u32 regval; | |
133 | ||
134 | regval = readl(host->base + reg); | |
135 | regval &= ~mask; | |
136 | regval |= (val & mask); | |
137 | ||
138 | writel(regval, host->base + reg); | |
139 | } | |
140 | ||
141 | static void meson_mx_mmc_soft_reset(struct meson_mx_mmc_host *host) | |
142 | { | |
143 | writel(MESON_MX_SDIO_IRQC_SOFT_RESET, host->base + MESON_MX_SDIO_IRQC); | |
144 | udelay(2); | |
145 | } | |
146 | ||
147 | static struct mmc_command *meson_mx_mmc_get_next_cmd(struct mmc_command *cmd) | |
148 | { | |
149 | if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error) | |
150 | return cmd->mrq->cmd; | |
151 | else if (mmc_op_multi(cmd->opcode) && | |
152 | (!cmd->mrq->sbc || cmd->error || cmd->data->error)) | |
153 | return cmd->mrq->stop; | |
154 | else | |
155 | return NULL; | |
156 | } | |
157 | ||
158 | static void meson_mx_mmc_start_cmd(struct mmc_host *mmc, | |
159 | struct mmc_command *cmd) | |
160 | { | |
161 | struct meson_mx_mmc_host *host = mmc_priv(mmc); | |
162 | unsigned int pack_size; | |
163 | unsigned long irqflags, timeout; | |
164 | u32 mult, send = 0, ext = 0; | |
165 | ||
166 | host->cmd = cmd; | |
167 | ||
168 | if (cmd->busy_timeout) | |
169 | timeout = msecs_to_jiffies(cmd->busy_timeout); | |
170 | else | |
171 | timeout = msecs_to_jiffies(1000); | |
172 | ||
173 | switch (mmc_resp_type(cmd)) { | |
174 | case MMC_RSP_R1: | |
175 | case MMC_RSP_R1B: | |
176 | case MMC_RSP_R3: | |
177 | /* 7 (CMD) + 32 (response) + 7 (CRC) -1 */ | |
178 | send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 45); | |
179 | break; | |
180 | case MMC_RSP_R2: | |
181 | /* 7 (CMD) + 120 (response) + 7 (CRC) -1 */ | |
182 | send |= FIELD_PREP(MESON_MX_SDIO_SEND_CMD_RESP_BITS_MASK, 133); | |
183 | send |= MESON_MX_SDIO_SEND_RESP_CRC7_FROM_8; | |
184 | break; | |
185 | default: | |
186 | break; | |
187 | } | |
188 | ||
189 | if (!(cmd->flags & MMC_RSP_CRC)) | |
190 | send |= MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7; | |
191 | ||
192 | if (cmd->flags & MMC_RSP_BUSY) | |
193 | send |= MESON_MX_SDIO_SEND_CHECK_DAT0_BUSY; | |
194 | ||
195 | if (cmd->data) { | |
196 | send |= FIELD_PREP(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK, | |
197 | (cmd->data->blocks - 1)); | |
198 | ||
199 | pack_size = cmd->data->blksz * BITS_PER_BYTE; | |
200 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) | |
201 | pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 4; | |
202 | else | |
203 | pack_size += MESON_MX_SDIO_RESPONSE_CRC16_BITS * 1; | |
204 | ||
205 | ext |= FIELD_PREP(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK, | |
206 | pack_size); | |
207 | ||
208 | if (cmd->data->flags & MMC_DATA_WRITE) | |
209 | send |= MESON_MX_SDIO_SEND_DATA; | |
210 | else | |
211 | send |= MESON_MX_SDIO_SEND_RESP_HAS_DATA; | |
212 | ||
213 | cmd->data->bytes_xfered = 0; | |
214 | } | |
215 | ||
216 | send |= FIELD_PREP(MESON_MX_SDIO_SEND_COMMAND_INDEX_MASK, | |
217 | (0x40 | cmd->opcode)); | |
218 | ||
219 | spin_lock_irqsave(&host->irq_lock, irqflags); | |
220 | ||
221 | mult = readl(host->base + MESON_MX_SDIO_MULT); | |
222 | mult &= ~MESON_MX_SDIO_MULT_PORT_SEL_MASK; | |
223 | mult |= FIELD_PREP(MESON_MX_SDIO_MULT_PORT_SEL_MASK, host->slot_id); | |
224 | mult |= BIT(31); | |
225 | writel(mult, host->base + MESON_MX_SDIO_MULT); | |
226 | ||
227 | /* enable the CMD done interrupt */ | |
228 | meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQC, | |
229 | MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN, | |
230 | MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN); | |
231 | ||
232 | /* clear pending interrupts */ | |
233 | meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_IRQS, | |
234 | MESON_MX_SDIO_IRQS_CMD_INT, | |
235 | MESON_MX_SDIO_IRQS_CMD_INT); | |
236 | ||
237 | writel(cmd->arg, host->base + MESON_MX_SDIO_ARGU); | |
238 | writel(ext, host->base + MESON_MX_SDIO_EXT); | |
239 | writel(send, host->base + MESON_MX_SDIO_SEND); | |
240 | ||
241 | spin_unlock_irqrestore(&host->irq_lock, irqflags); | |
242 | ||
243 | mod_timer(&host->cmd_timeout, jiffies + timeout); | |
244 | } | |
245 | ||
246 | static void meson_mx_mmc_request_done(struct meson_mx_mmc_host *host) | |
247 | { | |
248 | struct mmc_request *mrq; | |
249 | ||
250 | mrq = host->mrq; | |
251 | ||
252 | host->mrq = NULL; | |
253 | host->cmd = NULL; | |
254 | ||
255 | mmc_request_done(host->mmc, mrq); | |
256 | } | |
257 | ||
258 | static void meson_mx_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
259 | { | |
260 | struct meson_mx_mmc_host *host = mmc_priv(mmc); | |
261 | unsigned short vdd = ios->vdd; | |
262 | unsigned long clk_rate = ios->clock; | |
263 | ||
264 | switch (ios->bus_width) { | |
265 | case MMC_BUS_WIDTH_1: | |
266 | meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF, | |
267 | MESON_MX_SDIO_CONF_BUS_WIDTH, 0); | |
268 | break; | |
269 | ||
270 | case MMC_BUS_WIDTH_4: | |
271 | meson_mx_mmc_mask_bits(mmc, MESON_MX_SDIO_CONF, | |
272 | MESON_MX_SDIO_CONF_BUS_WIDTH, | |
273 | MESON_MX_SDIO_CONF_BUS_WIDTH); | |
274 | break; | |
275 | ||
276 | case MMC_BUS_WIDTH_8: | |
277 | default: | |
278 | dev_err(mmc_dev(mmc), "unsupported bus width: %d\n", | |
279 | ios->bus_width); | |
280 | host->error = -EINVAL; | |
281 | return; | |
282 | } | |
283 | ||
284 | host->error = clk_set_rate(host->cfg_div_clk, ios->clock); | |
285 | if (host->error) { | |
286 | dev_warn(mmc_dev(mmc), | |
287 | "failed to set MMC clock to %lu: %d\n", | |
288 | clk_rate, host->error); | |
289 | return; | |
290 | } | |
291 | ||
292 | mmc->actual_clock = clk_get_rate(host->cfg_div_clk); | |
293 | ||
294 | switch (ios->power_mode) { | |
295 | case MMC_POWER_OFF: | |
296 | vdd = 0; | |
297 | /* fall-through: */ | |
298 | case MMC_POWER_UP: | |
299 | if (!IS_ERR(mmc->supply.vmmc)) { | |
300 | host->error = mmc_regulator_set_ocr(mmc, | |
301 | mmc->supply.vmmc, | |
302 | vdd); | |
303 | if (host->error) | |
304 | return; | |
305 | } | |
306 | break; | |
307 | } | |
308 | } | |
309 | ||
310 | static int meson_mx_mmc_map_dma(struct mmc_host *mmc, struct mmc_request *mrq) | |
311 | { | |
312 | struct mmc_data *data = mrq->data; | |
313 | int dma_len; | |
314 | struct scatterlist *sg; | |
315 | ||
316 | if (!data) | |
317 | return 0; | |
318 | ||
319 | sg = data->sg; | |
320 | if (sg->offset & 3 || sg->length & 3) { | |
321 | dev_err(mmc_dev(mmc), | |
322 | "unaligned scatterlist: offset %x length %d\n", | |
323 | sg->offset, sg->length); | |
324 | return -EINVAL; | |
325 | } | |
326 | ||
327 | dma_len = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len, | |
328 | mmc_get_dma_dir(data)); | |
329 | if (dma_len <= 0) { | |
330 | dev_err(mmc_dev(mmc), "dma_map_sg failed\n"); | |
331 | return -ENOMEM; | |
332 | } | |
333 | ||
334 | return 0; | |
335 | } | |
336 | ||
337 | static void meson_mx_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
338 | { | |
339 | struct meson_mx_mmc_host *host = mmc_priv(mmc); | |
340 | struct mmc_command *cmd = mrq->cmd; | |
341 | ||
342 | if (!host->error) | |
343 | host->error = meson_mx_mmc_map_dma(mmc, mrq); | |
344 | ||
345 | if (host->error) { | |
346 | cmd->error = host->error; | |
347 | mmc_request_done(mmc, mrq); | |
348 | return; | |
349 | } | |
350 | ||
351 | host->mrq = mrq; | |
352 | ||
353 | if (mrq->data) | |
354 | writel(sg_dma_address(mrq->data->sg), | |
355 | host->base + MESON_MX_SDIO_ADDR); | |
356 | ||
357 | if (mrq->sbc) | |
358 | meson_mx_mmc_start_cmd(mmc, mrq->sbc); | |
359 | else | |
360 | meson_mx_mmc_start_cmd(mmc, mrq->cmd); | |
361 | } | |
362 | ||
363 | static int meson_mx_mmc_card_busy(struct mmc_host *mmc) | |
364 | { | |
365 | struct meson_mx_mmc_host *host = mmc_priv(mmc); | |
366 | u32 irqc = readl(host->base + MESON_MX_SDIO_IRQC); | |
367 | ||
368 | return !!(irqc & MESON_MX_SDIO_IRQC_FORCE_DATA_DAT_MASK); | |
369 | } | |
370 | ||
371 | static void meson_mx_mmc_read_response(struct mmc_host *mmc, | |
372 | struct mmc_command *cmd) | |
373 | { | |
374 | struct meson_mx_mmc_host *host = mmc_priv(mmc); | |
375 | u32 mult; | |
376 | int i, resp[4]; | |
377 | ||
378 | mult = readl(host->base + MESON_MX_SDIO_MULT); | |
379 | mult |= MESON_MX_SDIO_MULT_WR_RD_OUT_INDEX; | |
380 | mult &= ~MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK; | |
381 | mult |= FIELD_PREP(MESON_MX_SDIO_MULT_RESP_READ_INDEX_MASK, 0); | |
382 | writel(mult, host->base + MESON_MX_SDIO_MULT); | |
383 | ||
384 | if (cmd->flags & MMC_RSP_136) { | |
385 | for (i = 0; i <= 3; i++) | |
386 | resp[3 - i] = readl(host->base + MESON_MX_SDIO_ARGU); | |
387 | cmd->resp[0] = (resp[0] << 8) | ((resp[1] >> 24) & 0xff); | |
388 | cmd->resp[1] = (resp[1] << 8) | ((resp[2] >> 24) & 0xff); | |
389 | cmd->resp[2] = (resp[2] << 8) | ((resp[3] >> 24) & 0xff); | |
390 | cmd->resp[3] = (resp[3] << 8); | |
391 | } else if (cmd->flags & MMC_RSP_PRESENT) { | |
392 | cmd->resp[0] = readl(host->base + MESON_MX_SDIO_ARGU); | |
393 | } | |
394 | } | |
395 | ||
396 | static irqreturn_t meson_mx_mmc_process_cmd_irq(struct meson_mx_mmc_host *host, | |
397 | u32 irqs, u32 send) | |
398 | { | |
399 | struct mmc_command *cmd = host->cmd; | |
400 | ||
401 | /* | |
402 | * NOTE: even though it shouldn't happen we sometimes get command | |
403 | * interrupts twice (at least this is what it looks like). Ideally | |
404 | * we find out why this happens and warn here as soon as it occurs. | |
405 | */ | |
406 | if (!cmd) | |
407 | return IRQ_HANDLED; | |
408 | ||
409 | cmd->error = 0; | |
410 | meson_mx_mmc_read_response(host->mmc, cmd); | |
411 | ||
412 | if (cmd->data) { | |
413 | if (!((irqs & MESON_MX_SDIO_IRQS_DATA_READ_CRC16_OK) || | |
414 | (irqs & MESON_MX_SDIO_IRQS_DATA_WRITE_CRC16_OK))) | |
415 | cmd->error = -EILSEQ; | |
416 | } else { | |
417 | if (!((irqs & MESON_MX_SDIO_IRQS_RESP_CRC7_OK) || | |
418 | (send & MESON_MX_SDIO_SEND_RESP_WITHOUT_CRC7))) | |
419 | cmd->error = -EILSEQ; | |
420 | } | |
421 | ||
422 | return IRQ_WAKE_THREAD; | |
423 | } | |
424 | ||
425 | static irqreturn_t meson_mx_mmc_irq(int irq, void *data) | |
426 | { | |
427 | struct meson_mx_mmc_host *host = (void *) data; | |
428 | u32 irqs, send; | |
429 | unsigned long irqflags; | |
430 | irqreturn_t ret; | |
431 | ||
432 | spin_lock_irqsave(&host->irq_lock, irqflags); | |
433 | ||
434 | irqs = readl(host->base + MESON_MX_SDIO_IRQS); | |
435 | send = readl(host->base + MESON_MX_SDIO_SEND); | |
436 | ||
437 | if (irqs & MESON_MX_SDIO_IRQS_CMD_INT) | |
438 | ret = meson_mx_mmc_process_cmd_irq(host, irqs, send); | |
439 | else | |
440 | ret = IRQ_HANDLED; | |
441 | ||
442 | /* finally ACK all pending interrupts */ | |
443 | writel(irqs, host->base + MESON_MX_SDIO_IRQS); | |
444 | ||
445 | spin_unlock_irqrestore(&host->irq_lock, irqflags); | |
446 | ||
447 | return ret; | |
448 | } | |
449 | ||
450 | static irqreturn_t meson_mx_mmc_irq_thread(int irq, void *irq_data) | |
451 | { | |
452 | struct meson_mx_mmc_host *host = (void *) irq_data; | |
453 | struct mmc_command *cmd = host->cmd, *next_cmd; | |
454 | ||
455 | if (WARN_ON(!cmd)) | |
456 | return IRQ_HANDLED; | |
457 | ||
458 | del_timer_sync(&host->cmd_timeout); | |
459 | ||
460 | if (cmd->data) { | |
461 | dma_unmap_sg(mmc_dev(host->mmc), cmd->data->sg, | |
462 | cmd->data->sg_len, | |
463 | mmc_get_dma_dir(cmd->data)); | |
464 | ||
465 | cmd->data->bytes_xfered = cmd->data->blksz * cmd->data->blocks; | |
466 | } | |
467 | ||
468 | next_cmd = meson_mx_mmc_get_next_cmd(cmd); | |
469 | if (next_cmd) | |
470 | meson_mx_mmc_start_cmd(host->mmc, next_cmd); | |
471 | else | |
472 | meson_mx_mmc_request_done(host); | |
473 | ||
474 | return IRQ_HANDLED; | |
475 | } | |
476 | ||
2ee4f620 | 477 | static void meson_mx_mmc_timeout(struct timer_list *t) |
ed80a13b | 478 | { |
2ee4f620 | 479 | struct meson_mx_mmc_host *host = from_timer(host, t, cmd_timeout); |
ed80a13b CC |
480 | unsigned long irqflags; |
481 | u32 irqc; | |
482 | ||
483 | spin_lock_irqsave(&host->irq_lock, irqflags); | |
484 | ||
485 | /* disable the CMD interrupt */ | |
486 | irqc = readl(host->base + MESON_MX_SDIO_IRQC); | |
487 | irqc &= ~MESON_MX_SDIO_IRQC_ARC_CMD_INT_EN; | |
488 | writel(irqc, host->base + MESON_MX_SDIO_IRQC); | |
489 | ||
490 | spin_unlock_irqrestore(&host->irq_lock, irqflags); | |
491 | ||
492 | /* | |
493 | * skip the timeout handling if the interrupt handler already processed | |
494 | * the command. | |
495 | */ | |
496 | if (!host->cmd) | |
497 | return; | |
498 | ||
499 | dev_dbg(mmc_dev(host->mmc), | |
500 | "Timeout on CMD%u (IRQS = 0x%08x, ARGU = 0x%08x)\n", | |
501 | host->cmd->opcode, readl(host->base + MESON_MX_SDIO_IRQS), | |
502 | readl(host->base + MESON_MX_SDIO_ARGU)); | |
503 | ||
504 | host->cmd->error = -ETIMEDOUT; | |
505 | ||
506 | meson_mx_mmc_request_done(host); | |
507 | } | |
508 | ||
509 | static struct mmc_host_ops meson_mx_mmc_ops = { | |
510 | .request = meson_mx_mmc_request, | |
511 | .set_ios = meson_mx_mmc_set_ios, | |
512 | .card_busy = meson_mx_mmc_card_busy, | |
513 | .get_cd = mmc_gpio_get_cd, | |
514 | .get_ro = mmc_gpio_get_ro, | |
515 | }; | |
516 | ||
517 | static struct platform_device *meson_mx_mmc_slot_pdev(struct device *parent) | |
518 | { | |
519 | struct device_node *slot_node; | |
d72f5ff7 | 520 | struct platform_device *pdev; |
ed80a13b CC |
521 | |
522 | /* | |
523 | * TODO: the MMC core framework currently does not support | |
524 | * controllers with multiple slots properly. So we only register | |
525 | * the first slot for now | |
526 | */ | |
d72f5ff7 | 527 | slot_node = of_get_compatible_child(parent->of_node, "mmc-slot"); |
ed80a13b CC |
528 | if (!slot_node) { |
529 | dev_warn(parent, "no 'mmc-slot' sub-node found\n"); | |
530 | return ERR_PTR(-ENOENT); | |
531 | } | |
532 | ||
d72f5ff7 JH |
533 | pdev = of_platform_device_create(slot_node, NULL, parent); |
534 | of_node_put(slot_node); | |
535 | ||
536 | return pdev; | |
ed80a13b CC |
537 | } |
538 | ||
539 | static int meson_mx_mmc_add_host(struct meson_mx_mmc_host *host) | |
540 | { | |
541 | struct mmc_host *mmc = host->mmc; | |
542 | struct device *slot_dev = mmc_dev(mmc); | |
543 | int ret; | |
544 | ||
545 | if (of_property_read_u32(slot_dev->of_node, "reg", &host->slot_id)) { | |
546 | dev_err(slot_dev, "missing 'reg' property\n"); | |
547 | return -EINVAL; | |
548 | } | |
549 | ||
550 | if (host->slot_id >= MESON_MX_SDIO_MAX_SLOTS) { | |
551 | dev_err(slot_dev, "invalid 'reg' property value %d\n", | |
552 | host->slot_id); | |
553 | return -EINVAL; | |
554 | } | |
555 | ||
556 | /* Get regulators and the supported OCR mask */ | |
557 | ret = mmc_regulator_get_supply(mmc); | |
aa5754c7 | 558 | if (ret) |
ed80a13b CC |
559 | return ret; |
560 | ||
561 | mmc->max_req_size = MESON_MX_SDIO_BOUNCE_REQ_SIZE; | |
562 | mmc->max_seg_size = mmc->max_req_size; | |
563 | mmc->max_blk_count = | |
564 | FIELD_GET(MESON_MX_SDIO_SEND_REPEAT_PACKAGE_TIMES_MASK, | |
565 | 0xffffffff); | |
566 | mmc->max_blk_size = FIELD_GET(MESON_MX_SDIO_EXT_DATA_RW_NUMBER_MASK, | |
567 | 0xffffffff); | |
568 | mmc->max_blk_size -= (4 * MESON_MX_SDIO_RESPONSE_CRC16_BITS); | |
569 | mmc->max_blk_size /= BITS_PER_BYTE; | |
570 | ||
571 | /* Get the min and max supported clock rates */ | |
572 | mmc->f_min = clk_round_rate(host->cfg_div_clk, 1); | |
573 | mmc->f_max = clk_round_rate(host->cfg_div_clk, | |
574 | clk_get_rate(host->parent_clk)); | |
575 | ||
576 | mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; | |
577 | mmc->ops = &meson_mx_mmc_ops; | |
578 | ||
579 | ret = mmc_of_parse(mmc); | |
580 | if (ret) | |
581 | return ret; | |
582 | ||
583 | ret = mmc_add_host(mmc); | |
584 | if (ret) | |
585 | return ret; | |
586 | ||
587 | return 0; | |
588 | } | |
589 | ||
590 | static int meson_mx_mmc_register_clks(struct meson_mx_mmc_host *host) | |
591 | { | |
592 | struct clk_init_data init; | |
593 | const char *clk_div_parent, *clk_fixed_factor_parent; | |
594 | ||
595 | clk_fixed_factor_parent = __clk_get_name(host->parent_clk); | |
596 | init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL, | |
597 | "%s#fixed_factor", | |
598 | dev_name(host->controller_dev)); | |
599 | init.ops = &clk_fixed_factor_ops; | |
600 | init.flags = 0; | |
601 | init.parent_names = &clk_fixed_factor_parent; | |
602 | init.num_parents = 1; | |
603 | host->fixed_factor.div = 2; | |
604 | host->fixed_factor.mult = 1; | |
605 | host->fixed_factor.hw.init = &init; | |
606 | ||
607 | host->fixed_factor_clk = devm_clk_register(host->controller_dev, | |
608 | &host->fixed_factor.hw); | |
2f129d39 | 609 | if (WARN_ON(IS_ERR(host->fixed_factor_clk))) |
ed80a13b CC |
610 | return PTR_ERR(host->fixed_factor_clk); |
611 | ||
612 | clk_div_parent = __clk_get_name(host->fixed_factor_clk); | |
613 | init.name = devm_kasprintf(host->controller_dev, GFP_KERNEL, | |
614 | "%s#div", dev_name(host->controller_dev)); | |
615 | init.ops = &clk_divider_ops; | |
616 | init.flags = CLK_SET_RATE_PARENT; | |
617 | init.parent_names = &clk_div_parent; | |
618 | init.num_parents = 1; | |
619 | host->cfg_div.reg = host->base + MESON_MX_SDIO_CONF; | |
620 | host->cfg_div.shift = MESON_MX_SDIO_CONF_CMD_CLK_DIV_SHIFT; | |
621 | host->cfg_div.width = MESON_MX_SDIO_CONF_CMD_CLK_DIV_WIDTH; | |
622 | host->cfg_div.hw.init = &init; | |
623 | host->cfg_div.flags = CLK_DIVIDER_ALLOW_ZERO; | |
624 | ||
625 | host->cfg_div_clk = devm_clk_register(host->controller_dev, | |
626 | &host->cfg_div.hw); | |
2f129d39 | 627 | if (WARN_ON(IS_ERR(host->cfg_div_clk))) |
7599b849 | 628 | return PTR_ERR(host->cfg_div_clk); |
ed80a13b CC |
629 | |
630 | return 0; | |
631 | } | |
632 | ||
633 | static int meson_mx_mmc_probe(struct platform_device *pdev) | |
634 | { | |
635 | struct platform_device *slot_pdev; | |
636 | struct mmc_host *mmc; | |
637 | struct meson_mx_mmc_host *host; | |
638 | struct resource *res; | |
639 | int ret, irq; | |
640 | u32 conf; | |
641 | ||
642 | slot_pdev = meson_mx_mmc_slot_pdev(&pdev->dev); | |
643 | if (!slot_pdev) | |
644 | return -ENODEV; | |
645 | else if (IS_ERR(slot_pdev)) | |
646 | return PTR_ERR(slot_pdev); | |
647 | ||
648 | mmc = mmc_alloc_host(sizeof(*host), &slot_pdev->dev); | |
649 | if (!mmc) { | |
650 | ret = -ENOMEM; | |
651 | goto error_unregister_slot_pdev; | |
652 | } | |
653 | ||
654 | host = mmc_priv(mmc); | |
655 | host->mmc = mmc; | |
656 | host->controller_dev = &pdev->dev; | |
657 | ||
658 | spin_lock_init(&host->irq_lock); | |
2ee4f620 | 659 | timer_setup(&host->cmd_timeout, meson_mx_mmc_timeout, 0); |
ed80a13b CC |
660 | |
661 | platform_set_drvdata(pdev, host); | |
662 | ||
663 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
664 | host->base = devm_ioremap_resource(host->controller_dev, res); | |
665 | if (IS_ERR(host->base)) { | |
666 | ret = PTR_ERR(host->base); | |
667 | goto error_free_mmc; | |
668 | } | |
669 | ||
670 | irq = platform_get_irq(pdev, 0); | |
671 | ret = devm_request_threaded_irq(host->controller_dev, irq, | |
672 | meson_mx_mmc_irq, | |
673 | meson_mx_mmc_irq_thread, IRQF_ONESHOT, | |
674 | NULL, host); | |
675 | if (ret) | |
676 | goto error_free_mmc; | |
677 | ||
678 | host->core_clk = devm_clk_get(host->controller_dev, "core"); | |
679 | if (IS_ERR(host->core_clk)) { | |
680 | ret = PTR_ERR(host->core_clk); | |
681 | goto error_free_mmc; | |
682 | } | |
683 | ||
684 | host->parent_clk = devm_clk_get(host->controller_dev, "clkin"); | |
685 | if (IS_ERR(host->parent_clk)) { | |
686 | ret = PTR_ERR(host->parent_clk); | |
687 | goto error_free_mmc; | |
688 | } | |
689 | ||
690 | ret = meson_mx_mmc_register_clks(host); | |
691 | if (ret) | |
692 | goto error_free_mmc; | |
693 | ||
694 | ret = clk_prepare_enable(host->core_clk); | |
695 | if (ret) { | |
696 | dev_err(host->controller_dev, "Failed to enable core clock\n"); | |
697 | goto error_free_mmc; | |
698 | } | |
699 | ||
700 | ret = clk_prepare_enable(host->cfg_div_clk); | |
701 | if (ret) { | |
702 | dev_err(host->controller_dev, "Failed to enable MMC clock\n"); | |
703 | goto error_disable_core_clk; | |
704 | } | |
705 | ||
706 | conf = 0; | |
707 | conf |= FIELD_PREP(MESON_MX_SDIO_CONF_CMD_ARGUMENT_BITS_MASK, 39); | |
708 | conf |= FIELD_PREP(MESON_MX_SDIO_CONF_M_ENDIAN_MASK, 0x3); | |
709 | conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_NWR_MASK, 0x2); | |
710 | conf |= FIELD_PREP(MESON_MX_SDIO_CONF_WRITE_CRC_OK_STATUS_MASK, 0x2); | |
711 | writel(conf, host->base + MESON_MX_SDIO_CONF); | |
712 | ||
713 | meson_mx_mmc_soft_reset(host); | |
714 | ||
715 | ret = meson_mx_mmc_add_host(host); | |
716 | if (ret) | |
717 | goto error_disable_clks; | |
718 | ||
719 | return 0; | |
720 | ||
721 | error_disable_clks: | |
722 | clk_disable_unprepare(host->cfg_div_clk); | |
723 | error_disable_core_clk: | |
724 | clk_disable_unprepare(host->core_clk); | |
725 | error_free_mmc: | |
726 | mmc_free_host(mmc); | |
727 | error_unregister_slot_pdev: | |
728 | of_platform_device_destroy(&slot_pdev->dev, NULL); | |
729 | return ret; | |
730 | } | |
731 | ||
732 | static int meson_mx_mmc_remove(struct platform_device *pdev) | |
733 | { | |
734 | struct meson_mx_mmc_host *host = platform_get_drvdata(pdev); | |
735 | struct device *slot_dev = mmc_dev(host->mmc); | |
736 | ||
737 | del_timer_sync(&host->cmd_timeout); | |
738 | ||
739 | mmc_remove_host(host->mmc); | |
740 | ||
741 | of_platform_device_destroy(slot_dev, NULL); | |
742 | ||
743 | clk_disable_unprepare(host->cfg_div_clk); | |
744 | clk_disable_unprepare(host->core_clk); | |
745 | ||
746 | mmc_free_host(host->mmc); | |
747 | ||
748 | return 0; | |
749 | } | |
750 | ||
751 | static const struct of_device_id meson_mx_mmc_of_match[] = { | |
752 | { .compatible = "amlogic,meson8-sdio", }, | |
753 | { .compatible = "amlogic,meson8b-sdio", }, | |
754 | { /* sentinel */ } | |
755 | }; | |
756 | MODULE_DEVICE_TABLE(of, meson_mx_mmc_of_match); | |
757 | ||
758 | static struct platform_driver meson_mx_mmc_driver = { | |
759 | .probe = meson_mx_mmc_probe, | |
760 | .remove = meson_mx_mmc_remove, | |
761 | .driver = { | |
762 | .name = "meson-mx-sdio", | |
763 | .of_match_table = of_match_ptr(meson_mx_mmc_of_match), | |
764 | }, | |
765 | }; | |
766 | ||
767 | module_platform_driver(meson_mx_mmc_driver); | |
768 | ||
769 | MODULE_DESCRIPTION("Meson6, Meson8 and Meson8b SDIO/MMC Host Driver"); | |
770 | MODULE_AUTHOR("Carlo Caione <carlo@endlessm.com>"); | |
771 | MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>"); | |
772 | MODULE_LICENSE("GPL v2"); |