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15a0580c DB |
1 | /* |
2 | * mmc_spi.c - Access SD/MMC cards through SPI master controllers | |
3 | * | |
4 | * (C) Copyright 2005, Intec Automation, | |
5 | * Mike Lavender (mike@steroidmicros) | |
6 | * (C) Copyright 2006-2007, David Brownell | |
7 | * (C) Copyright 2007, Axis Communications, | |
8 | * Hans-Peter Nilsson (hp@axis.com) | |
9 | * (C) Copyright 2007, ATRON electronic GmbH, | |
10 | * Jan Nikitenko <jan.nikitenko@gmail.com> | |
11 | * | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or modify | |
14 | * it under the terms of the GNU General Public License as published by | |
15 | * the Free Software Foundation; either version 2 of the License, or | |
16 | * (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | */ | |
27 | #include <linux/hrtimer.h> | |
28 | #include <linux/delay.h> | |
23fd5045 | 29 | #include <linux/bio.h> |
15a0580c DB |
30 | #include <linux/dma-mapping.h> |
31 | #include <linux/crc7.h> | |
32 | #include <linux/crc-itu-t.h> | |
e5712a6a | 33 | #include <linux/scatterlist.h> |
15a0580c DB |
34 | |
35 | #include <linux/mmc/host.h> | |
36 | #include <linux/mmc/mmc.h> /* for R1_SPI_* bit values */ | |
37 | ||
38 | #include <linux/spi/spi.h> | |
39 | #include <linux/spi/mmc_spi.h> | |
40 | ||
41 | #include <asm/unaligned.h> | |
42 | ||
43 | ||
44 | /* NOTES: | |
45 | * | |
46 | * - For now, we won't try to interoperate with a real mmc/sd/sdio | |
47 | * controller, although some of them do have hardware support for | |
48 | * SPI protocol. The main reason for such configs would be mmc-ish | |
49 | * cards like DataFlash, which don't support that "native" protocol. | |
50 | * | |
51 | * We don't have a "DataFlash/MMC/SD/SDIO card slot" abstraction to | |
52 | * switch between driver stacks, and in any case if "native" mode | |
53 | * is available, it will be faster and hence preferable. | |
54 | * | |
55 | * - MMC depends on a different chipselect management policy than the | |
56 | * SPI interface currently supports for shared bus segments: it needs | |
57 | * to issue multiple spi_message requests with the chipselect active, | |
58 | * using the results of one message to decide the next one to issue. | |
59 | * | |
60 | * Pending updates to the programming interface, this driver expects | |
61 | * that it not share the bus with other drivers (precluding conflicts). | |
62 | * | |
63 | * - We tell the controller to keep the chipselect active from the | |
64 | * beginning of an mmc_host_ops.request until the end. So beware | |
65 | * of SPI controller drivers that mis-handle the cs_change flag! | |
66 | * | |
67 | * However, many cards seem OK with chipselect flapping up/down | |
68 | * during that time ... at least on unshared bus segments. | |
69 | */ | |
70 | ||
71 | ||
72 | /* | |
73 | * Local protocol constants, internal to data block protocols. | |
74 | */ | |
75 | ||
76 | /* Response tokens used to ack each block written: */ | |
77 | #define SPI_MMC_RESPONSE_CODE(x) ((x) & 0x1f) | |
78 | #define SPI_RESPONSE_ACCEPTED ((2 << 1)|1) | |
79 | #define SPI_RESPONSE_CRC_ERR ((5 << 1)|1) | |
80 | #define SPI_RESPONSE_WRITE_ERR ((6 << 1)|1) | |
81 | ||
82 | /* Read and write blocks start with these tokens and end with crc; | |
83 | * on error, read tokens act like a subset of R2_SPI_* values. | |
84 | */ | |
85 | #define SPI_TOKEN_SINGLE 0xfe /* single block r/w, multiblock read */ | |
86 | #define SPI_TOKEN_MULTI_WRITE 0xfc /* multiblock write */ | |
87 | #define SPI_TOKEN_STOP_TRAN 0xfd /* terminate multiblock write */ | |
88 | ||
89 | #define MMC_SPI_BLOCKSIZE 512 | |
90 | ||
91 | ||
92 | /* These fixed timeouts come from the latest SD specs, which say to ignore | |
93 | * the CSD values. The R1B value is for card erase (e.g. the "I forgot the | |
94 | * card's password" scenario); it's mostly applied to STOP_TRANSMISSION after | |
95 | * reads which takes nowhere near that long. Older cards may be able to use | |
96 | * shorter timeouts ... but why bother? | |
97 | */ | |
15a0580c DB |
98 | #define r1b_timeout ktime_set(3, 0) |
99 | ||
100 | ||
101 | /****************************************************************************/ | |
102 | ||
103 | /* | |
104 | * Local Data Structures | |
105 | */ | |
106 | ||
107 | /* "scratch" is per-{command,block} data exchanged with the card */ | |
108 | struct scratch { | |
109 | u8 status[29]; | |
110 | u8 data_token; | |
111 | __be16 crc_val; | |
112 | }; | |
113 | ||
114 | struct mmc_spi_host { | |
115 | struct mmc_host *mmc; | |
116 | struct spi_device *spi; | |
117 | ||
118 | unsigned char power_mode; | |
119 | u16 powerup_msecs; | |
120 | ||
121 | struct mmc_spi_platform_data *pdata; | |
122 | ||
123 | /* for bulk data transfers */ | |
124 | struct spi_transfer token, t, crc, early_status; | |
125 | struct spi_message m; | |
126 | ||
127 | /* for status readback */ | |
128 | struct spi_transfer status; | |
129 | struct spi_message readback; | |
130 | ||
131 | /* underlying DMA-aware controller, or null */ | |
132 | struct device *dma_dev; | |
133 | ||
134 | /* buffer used for commands and for message "overhead" */ | |
135 | struct scratch *data; | |
136 | dma_addr_t data_dma; | |
137 | ||
138 | /* Specs say to write ones most of the time, even when the card | |
139 | * has no need to read its input data; and many cards won't care. | |
140 | * This is our source of those ones. | |
141 | */ | |
142 | void *ones; | |
143 | dma_addr_t ones_dma; | |
144 | }; | |
145 | ||
146 | ||
147 | /****************************************************************************/ | |
148 | ||
149 | /* | |
150 | * MMC-over-SPI protocol glue, used by the MMC stack interface | |
151 | */ | |
152 | ||
153 | static inline int mmc_cs_off(struct mmc_spi_host *host) | |
154 | { | |
155 | /* chipselect will always be inactive after setup() */ | |
156 | return spi_setup(host->spi); | |
157 | } | |
158 | ||
159 | static int | |
160 | mmc_spi_readbytes(struct mmc_spi_host *host, unsigned len) | |
161 | { | |
162 | int status; | |
163 | ||
164 | if (len > sizeof(*host->data)) { | |
165 | WARN_ON(1); | |
166 | return -EIO; | |
167 | } | |
168 | ||
169 | host->status.len = len; | |
170 | ||
171 | if (host->dma_dev) | |
172 | dma_sync_single_for_device(host->dma_dev, | |
173 | host->data_dma, sizeof(*host->data), | |
174 | DMA_FROM_DEVICE); | |
175 | ||
176 | status = spi_sync(host->spi, &host->readback); | |
15a0580c DB |
177 | |
178 | if (host->dma_dev) | |
179 | dma_sync_single_for_cpu(host->dma_dev, | |
180 | host->data_dma, sizeof(*host->data), | |
181 | DMA_FROM_DEVICE); | |
182 | ||
183 | return status; | |
184 | } | |
185 | ||
186 | static int | |
187 | mmc_spi_skip(struct mmc_spi_host *host, ktime_t timeout, unsigned n, u8 byte) | |
188 | { | |
189 | u8 *cp = host->data->status; | |
190 | ||
191 | timeout = ktime_add(timeout, ktime_get()); | |
192 | ||
193 | while (1) { | |
194 | int status; | |
195 | unsigned i; | |
196 | ||
197 | status = mmc_spi_readbytes(host, n); | |
198 | if (status < 0) | |
199 | return status; | |
200 | ||
201 | for (i = 0; i < n; i++) { | |
202 | if (cp[i] != byte) | |
203 | return cp[i]; | |
204 | } | |
205 | ||
206 | /* REVISIT investigate msleep() to avoid busy-wait I/O | |
207 | * in at least some cases. | |
208 | */ | |
209 | if (ktime_to_ns(ktime_sub(ktime_get(), timeout)) > 0) | |
210 | break; | |
211 | } | |
212 | return -ETIMEDOUT; | |
213 | } | |
214 | ||
215 | static inline int | |
216 | mmc_spi_wait_unbusy(struct mmc_spi_host *host, ktime_t timeout) | |
217 | { | |
218 | return mmc_spi_skip(host, timeout, sizeof(host->data->status), 0); | |
219 | } | |
220 | ||
162350eb | 221 | static int mmc_spi_readtoken(struct mmc_spi_host *host, ktime_t timeout) |
15a0580c | 222 | { |
162350eb | 223 | return mmc_spi_skip(host, timeout, 1, 0xff); |
15a0580c DB |
224 | } |
225 | ||
226 | ||
227 | /* | |
228 | * Note that for SPI, cmd->resp[0] is not the same data as "native" protocol | |
229 | * hosts return! The low byte holds R1_SPI bits. The next byte may hold | |
230 | * R2_SPI bits ... for SEND_STATUS, or after data read errors. | |
231 | * | |
232 | * cmd->resp[1] holds any four-byte response, for R3 (READ_OCR) and on | |
233 | * newer cards R7 (IF_COND). | |
234 | */ | |
235 | ||
236 | static char *maptype(struct mmc_command *cmd) | |
237 | { | |
238 | switch (mmc_spi_resp_type(cmd)) { | |
239 | case MMC_RSP_SPI_R1: return "R1"; | |
240 | case MMC_RSP_SPI_R1B: return "R1B"; | |
241 | case MMC_RSP_SPI_R2: return "R2/R5"; | |
242 | case MMC_RSP_SPI_R3: return "R3/R4/R7"; | |
243 | default: return "?"; | |
244 | } | |
245 | } | |
246 | ||
247 | /* return zero, else negative errno after setting cmd->error */ | |
248 | static int mmc_spi_response_get(struct mmc_spi_host *host, | |
249 | struct mmc_command *cmd, int cs_on) | |
250 | { | |
251 | u8 *cp = host->data->status; | |
252 | u8 *end = cp + host->t.len; | |
253 | int value = 0; | |
254 | char tag[32]; | |
255 | ||
256 | snprintf(tag, sizeof(tag), " ... CMD%d response SPI_%s", | |
257 | cmd->opcode, maptype(cmd)); | |
258 | ||
259 | /* Except for data block reads, the whole response will already | |
260 | * be stored in the scratch buffer. It's somewhere after the | |
261 | * command and the first byte we read after it. We ignore that | |
262 | * first byte. After STOP_TRANSMISSION command it may include | |
263 | * two data bits, but otherwise it's all ones. | |
264 | */ | |
265 | cp += 8; | |
266 | while (cp < end && *cp == 0xff) | |
267 | cp++; | |
268 | ||
269 | /* Data block reads (R1 response types) may need more data... */ | |
270 | if (cp == end) { | |
271 | unsigned i; | |
272 | ||
273 | cp = host->data->status; | |
274 | ||
275 | /* Card sends N(CR) (== 1..8) bytes of all-ones then one | |
276 | * status byte ... and we already scanned 2 bytes. | |
277 | * | |
278 | * REVISIT block read paths use nasty byte-at-a-time I/O | |
279 | * so it can always DMA directly into the target buffer. | |
280 | * It'd probably be better to memcpy() the first chunk and | |
281 | * avoid extra i/o calls... | |
282 | */ | |
283 | for (i = 2; i < 9; i++) { | |
284 | value = mmc_spi_readbytes(host, 1); | |
285 | if (value < 0) | |
286 | goto done; | |
287 | if (*cp != 0xff) | |
288 | goto checkstatus; | |
289 | } | |
290 | value = -ETIMEDOUT; | |
291 | goto done; | |
292 | } | |
293 | ||
294 | checkstatus: | |
295 | if (*cp & 0x80) { | |
296 | dev_dbg(&host->spi->dev, "%s: INVALID RESPONSE, %02x\n", | |
297 | tag, *cp); | |
298 | value = -EBADR; | |
299 | goto done; | |
300 | } | |
301 | ||
302 | cmd->resp[0] = *cp++; | |
303 | cmd->error = 0; | |
304 | ||
305 | /* Status byte: the entire seven-bit R1 response. */ | |
306 | if (cmd->resp[0] != 0) { | |
307 | if ((R1_SPI_PARAMETER | R1_SPI_ADDRESS | |
308 | | R1_SPI_ILLEGAL_COMMAND) | |
309 | & cmd->resp[0]) | |
310 | value = -EINVAL; | |
311 | else if (R1_SPI_COM_CRC & cmd->resp[0]) | |
312 | value = -EILSEQ; | |
313 | else if ((R1_SPI_ERASE_SEQ | R1_SPI_ERASE_RESET) | |
314 | & cmd->resp[0]) | |
315 | value = -EIO; | |
316 | /* else R1_SPI_IDLE, "it's resetting" */ | |
317 | } | |
318 | ||
319 | switch (mmc_spi_resp_type(cmd)) { | |
320 | ||
321 | /* SPI R1B == R1 + busy; STOP_TRANSMISSION (for multiblock reads) | |
322 | * and less-common stuff like various erase operations. | |
323 | */ | |
324 | case MMC_RSP_SPI_R1B: | |
325 | /* maybe we read all the busy tokens already */ | |
326 | while (cp < end && *cp == 0) | |
327 | cp++; | |
328 | if (cp == end) | |
329 | mmc_spi_wait_unbusy(host, r1b_timeout); | |
330 | break; | |
331 | ||
332 | /* SPI R2 == R1 + second status byte; SEND_STATUS | |
333 | * SPI R5 == R1 + data byte; IO_RW_DIRECT | |
334 | */ | |
335 | case MMC_RSP_SPI_R2: | |
336 | cmd->resp[0] |= *cp << 8; | |
337 | break; | |
338 | ||
339 | /* SPI R3, R4, or R7 == R1 + 4 bytes */ | |
340 | case MMC_RSP_SPI_R3: | |
48b2cf9e | 341 | cmd->resp[1] = get_unaligned_be32(cp); |
15a0580c DB |
342 | break; |
343 | ||
344 | /* SPI R1 == just one status byte */ | |
345 | case MMC_RSP_SPI_R1: | |
346 | break; | |
347 | ||
348 | default: | |
349 | dev_dbg(&host->spi->dev, "bad response type %04x\n", | |
350 | mmc_spi_resp_type(cmd)); | |
351 | if (value >= 0) | |
352 | value = -EINVAL; | |
353 | goto done; | |
354 | } | |
355 | ||
356 | if (value < 0) | |
357 | dev_dbg(&host->spi->dev, "%s: resp %04x %08x\n", | |
358 | tag, cmd->resp[0], cmd->resp[1]); | |
359 | ||
360 | /* disable chipselect on errors and some success cases */ | |
361 | if (value >= 0 && cs_on) | |
362 | return value; | |
363 | done: | |
364 | if (value < 0) | |
365 | cmd->error = value; | |
366 | mmc_cs_off(host); | |
367 | return value; | |
368 | } | |
369 | ||
370 | /* Issue command and read its response. | |
371 | * Returns zero on success, negative for error. | |
372 | * | |
373 | * On error, caller must cope with mmc core retry mechanism. That | |
374 | * means immediate low-level resubmit, which affects the bus lock... | |
375 | */ | |
376 | static int | |
377 | mmc_spi_command_send(struct mmc_spi_host *host, | |
378 | struct mmc_request *mrq, | |
379 | struct mmc_command *cmd, int cs_on) | |
380 | { | |
381 | struct scratch *data = host->data; | |
382 | u8 *cp = data->status; | |
383 | u32 arg = cmd->arg; | |
384 | int status; | |
385 | struct spi_transfer *t; | |
386 | ||
387 | /* We can handle most commands (except block reads) in one full | |
388 | * duplex I/O operation before either starting the next transfer | |
389 | * (data block or command) or else deselecting the card. | |
390 | * | |
391 | * First, write 7 bytes: | |
392 | * - an all-ones byte to ensure the card is ready | |
393 | * - opcode byte (plus start and transmission bits) | |
394 | * - four bytes of big-endian argument | |
395 | * - crc7 (plus end bit) ... always computed, it's cheap | |
396 | * | |
397 | * We init the whole buffer to all-ones, which is what we need | |
398 | * to write while we're reading (later) response data. | |
399 | */ | |
400 | memset(cp++, 0xff, sizeof(data->status)); | |
401 | ||
402 | *cp++ = 0x40 | cmd->opcode; | |
403 | *cp++ = (u8)(arg >> 24); | |
404 | *cp++ = (u8)(arg >> 16); | |
405 | *cp++ = (u8)(arg >> 8); | |
406 | *cp++ = (u8)arg; | |
407 | *cp++ = (crc7(0, &data->status[1], 5) << 1) | 0x01; | |
408 | ||
409 | /* Then, read up to 13 bytes (while writing all-ones): | |
410 | * - N(CR) (== 1..8) bytes of all-ones | |
411 | * - status byte (for all response types) | |
412 | * - the rest of the response, either: | |
413 | * + nothing, for R1 or R1B responses | |
414 | * + second status byte, for R2 responses | |
415 | * + four data bytes, for R3 and R7 responses | |
416 | * | |
417 | * Finally, read some more bytes ... in the nice cases we know in | |
418 | * advance how many, and reading 1 more is always OK: | |
419 | * - N(EC) (== 0..N) bytes of all-ones, before deselect/finish | |
420 | * - N(RC) (== 1..N) bytes of all-ones, before next command | |
421 | * - N(WR) (== 1..N) bytes of all-ones, before data write | |
422 | * | |
423 | * So in those cases one full duplex I/O of at most 21 bytes will | |
424 | * handle the whole command, leaving the card ready to receive a | |
425 | * data block or new command. We do that whenever we can, shaving | |
426 | * CPU and IRQ costs (especially when using DMA or FIFOs). | |
427 | * | |
428 | * There are two other cases, where it's not generally practical | |
429 | * to rely on a single I/O: | |
430 | * | |
431 | * - R1B responses need at least N(EC) bytes of all-zeroes. | |
432 | * | |
433 | * In this case we can *try* to fit it into one I/O, then | |
434 | * maybe read more data later. | |
435 | * | |
436 | * - Data block reads are more troublesome, since a variable | |
437 | * number of padding bytes precede the token and data. | |
438 | * + N(CX) (== 0..8) bytes of all-ones, before CSD or CID | |
439 | * + N(AC) (== 1..many) bytes of all-ones | |
440 | * | |
441 | * In this case we currently only have minimal speedups here: | |
442 | * when N(CR) == 1 we can avoid I/O in response_get(). | |
443 | */ | |
444 | if (cs_on && (mrq->data->flags & MMC_DATA_READ)) { | |
445 | cp += 2; /* min(N(CR)) + status */ | |
446 | /* R1 */ | |
447 | } else { | |
448 | cp += 10; /* max(N(CR)) + status + min(N(RC),N(WR)) */ | |
449 | if (cmd->flags & MMC_RSP_SPI_S2) /* R2/R5 */ | |
450 | cp++; | |
451 | else if (cmd->flags & MMC_RSP_SPI_B4) /* R3/R4/R7 */ | |
452 | cp += 4; | |
453 | else if (cmd->flags & MMC_RSP_BUSY) /* R1B */ | |
454 | cp = data->status + sizeof(data->status); | |
455 | /* else: R1 (most commands) */ | |
456 | } | |
457 | ||
458 | dev_dbg(&host->spi->dev, " mmc_spi: CMD%d, resp %s\n", | |
459 | cmd->opcode, maptype(cmd)); | |
460 | ||
461 | /* send command, leaving chipselect active */ | |
462 | spi_message_init(&host->m); | |
463 | ||
464 | t = &host->t; | |
465 | memset(t, 0, sizeof(*t)); | |
466 | t->tx_buf = t->rx_buf = data->status; | |
467 | t->tx_dma = t->rx_dma = host->data_dma; | |
468 | t->len = cp - data->status; | |
469 | t->cs_change = 1; | |
470 | spi_message_add_tail(t, &host->m); | |
471 | ||
472 | if (host->dma_dev) { | |
473 | host->m.is_dma_mapped = 1; | |
474 | dma_sync_single_for_device(host->dma_dev, | |
475 | host->data_dma, sizeof(*host->data), | |
476 | DMA_BIDIRECTIONAL); | |
477 | } | |
478 | status = spi_sync(host->spi, &host->m); | |
15a0580c DB |
479 | |
480 | if (host->dma_dev) | |
481 | dma_sync_single_for_cpu(host->dma_dev, | |
482 | host->data_dma, sizeof(*host->data), | |
483 | DMA_BIDIRECTIONAL); | |
484 | if (status < 0) { | |
485 | dev_dbg(&host->spi->dev, " ... write returned %d\n", status); | |
486 | cmd->error = status; | |
487 | return status; | |
488 | } | |
489 | ||
490 | /* after no-data commands and STOP_TRANSMISSION, chipselect off */ | |
491 | return mmc_spi_response_get(host, cmd, cs_on); | |
492 | } | |
493 | ||
494 | /* Build data message with up to four separate transfers. For TX, we | |
495 | * start by writing the data token. And in most cases, we finish with | |
496 | * a status transfer. | |
497 | * | |
498 | * We always provide TX data for data and CRC. The MMC/SD protocol | |
499 | * requires us to write ones; but Linux defaults to writing zeroes; | |
500 | * so we explicitly initialize it to all ones on RX paths. | |
501 | * | |
502 | * We also handle DMA mapping, so the underlying SPI controller does | |
503 | * not need to (re)do it for each message. | |
504 | */ | |
505 | static void | |
506 | mmc_spi_setup_data_message( | |
507 | struct mmc_spi_host *host, | |
508 | int multiple, | |
509 | enum dma_data_direction direction) | |
510 | { | |
511 | struct spi_transfer *t; | |
512 | struct scratch *scratch = host->data; | |
513 | dma_addr_t dma = host->data_dma; | |
514 | ||
515 | spi_message_init(&host->m); | |
516 | if (dma) | |
517 | host->m.is_dma_mapped = 1; | |
518 | ||
519 | /* for reads, readblock() skips 0xff bytes before finding | |
520 | * the token; for writes, this transfer issues that token. | |
521 | */ | |
522 | if (direction == DMA_TO_DEVICE) { | |
523 | t = &host->token; | |
524 | memset(t, 0, sizeof(*t)); | |
525 | t->len = 1; | |
526 | if (multiple) | |
527 | scratch->data_token = SPI_TOKEN_MULTI_WRITE; | |
528 | else | |
529 | scratch->data_token = SPI_TOKEN_SINGLE; | |
530 | t->tx_buf = &scratch->data_token; | |
531 | if (dma) | |
532 | t->tx_dma = dma + offsetof(struct scratch, data_token); | |
533 | spi_message_add_tail(t, &host->m); | |
534 | } | |
535 | ||
536 | /* Body of transfer is buffer, then CRC ... | |
537 | * either TX-only, or RX with TX-ones. | |
538 | */ | |
539 | t = &host->t; | |
540 | memset(t, 0, sizeof(*t)); | |
541 | t->tx_buf = host->ones; | |
542 | t->tx_dma = host->ones_dma; | |
543 | /* length and actual buffer info are written later */ | |
544 | spi_message_add_tail(t, &host->m); | |
545 | ||
546 | t = &host->crc; | |
547 | memset(t, 0, sizeof(*t)); | |
548 | t->len = 2; | |
549 | if (direction == DMA_TO_DEVICE) { | |
550 | /* the actual CRC may get written later */ | |
551 | t->tx_buf = &scratch->crc_val; | |
552 | if (dma) | |
553 | t->tx_dma = dma + offsetof(struct scratch, crc_val); | |
554 | } else { | |
555 | t->tx_buf = host->ones; | |
556 | t->tx_dma = host->ones_dma; | |
557 | t->rx_buf = &scratch->crc_val; | |
558 | if (dma) | |
559 | t->rx_dma = dma + offsetof(struct scratch, crc_val); | |
560 | } | |
561 | spi_message_add_tail(t, &host->m); | |
562 | ||
563 | /* | |
564 | * A single block read is followed by N(EC) [0+] all-ones bytes | |
565 | * before deselect ... don't bother. | |
566 | * | |
567 | * Multiblock reads are followed by N(AC) [1+] all-ones bytes before | |
568 | * the next block is read, or a STOP_TRANSMISSION is issued. We'll | |
569 | * collect that single byte, so readblock() doesn't need to. | |
570 | * | |
571 | * For a write, the one-byte data response follows immediately, then | |
572 | * come zero or more busy bytes, then N(WR) [1+] all-ones bytes. | |
573 | * Then single block reads may deselect, and multiblock ones issue | |
574 | * the next token (next data block, or STOP_TRAN). We can try to | |
575 | * minimize I/O ops by using a single read to collect end-of-busy. | |
576 | */ | |
577 | if (multiple || direction == DMA_TO_DEVICE) { | |
578 | t = &host->early_status; | |
579 | memset(t, 0, sizeof(*t)); | |
580 | t->len = (direction == DMA_TO_DEVICE) | |
581 | ? sizeof(scratch->status) | |
582 | : 1; | |
583 | t->tx_buf = host->ones; | |
584 | t->tx_dma = host->ones_dma; | |
585 | t->rx_buf = scratch->status; | |
586 | if (dma) | |
587 | t->rx_dma = dma + offsetof(struct scratch, status); | |
588 | t->cs_change = 1; | |
589 | spi_message_add_tail(t, &host->m); | |
590 | } | |
591 | } | |
592 | ||
593 | /* | |
594 | * Write one block: | |
595 | * - caller handled preceding N(WR) [1+] all-ones bytes | |
596 | * - data block | |
597 | * + token | |
598 | * + data bytes | |
599 | * + crc16 | |
600 | * - an all-ones byte ... card writes a data-response byte | |
601 | * - followed by N(EC) [0+] all-ones bytes, card writes zero/'busy' | |
602 | * | |
603 | * Return negative errno, else success. | |
604 | */ | |
605 | static int | |
162350eb MF |
606 | mmc_spi_writeblock(struct mmc_spi_host *host, struct spi_transfer *t, |
607 | ktime_t timeout) | |
15a0580c DB |
608 | { |
609 | struct spi_device *spi = host->spi; | |
610 | int status, i; | |
611 | struct scratch *scratch = host->data; | |
612 | ||
613 | if (host->mmc->use_spi_crc) | |
614 | scratch->crc_val = cpu_to_be16( | |
615 | crc_itu_t(0, t->tx_buf, t->len)); | |
616 | if (host->dma_dev) | |
617 | dma_sync_single_for_device(host->dma_dev, | |
618 | host->data_dma, sizeof(*scratch), | |
619 | DMA_BIDIRECTIONAL); | |
620 | ||
621 | status = spi_sync(spi, &host->m); | |
15a0580c DB |
622 | |
623 | if (status != 0) { | |
624 | dev_dbg(&spi->dev, "write error (%d)\n", status); | |
625 | return status; | |
626 | } | |
627 | ||
628 | if (host->dma_dev) | |
629 | dma_sync_single_for_cpu(host->dma_dev, | |
630 | host->data_dma, sizeof(*scratch), | |
631 | DMA_BIDIRECTIONAL); | |
632 | ||
633 | /* | |
634 | * Get the transmission data-response reply. It must follow | |
635 | * immediately after the data block we transferred. This reply | |
636 | * doesn't necessarily tell whether the write operation succeeded; | |
637 | * it just says if the transmission was ok and whether *earlier* | |
638 | * writes succeeded; see the standard. | |
639 | */ | |
640 | switch (SPI_MMC_RESPONSE_CODE(scratch->status[0])) { | |
641 | case SPI_RESPONSE_ACCEPTED: | |
642 | status = 0; | |
643 | break; | |
644 | case SPI_RESPONSE_CRC_ERR: | |
645 | /* host shall then issue MMC_STOP_TRANSMISSION */ | |
646 | status = -EILSEQ; | |
647 | break; | |
648 | case SPI_RESPONSE_WRITE_ERR: | |
649 | /* host shall then issue MMC_STOP_TRANSMISSION, | |
650 | * and should MMC_SEND_STATUS to sort it out | |
651 | */ | |
652 | status = -EIO; | |
653 | break; | |
654 | default: | |
655 | status = -EPROTO; | |
656 | break; | |
657 | } | |
658 | if (status != 0) { | |
659 | dev_dbg(&spi->dev, "write error %02x (%d)\n", | |
660 | scratch->status[0], status); | |
661 | return status; | |
662 | } | |
663 | ||
664 | t->tx_buf += t->len; | |
665 | if (host->dma_dev) | |
666 | t->tx_dma += t->len; | |
667 | ||
668 | /* Return when not busy. If we didn't collect that status yet, | |
669 | * we'll need some more I/O. | |
670 | */ | |
671 | for (i = 1; i < sizeof(scratch->status); i++) { | |
672 | if (scratch->status[i] != 0) | |
673 | return 0; | |
674 | } | |
162350eb | 675 | return mmc_spi_wait_unbusy(host, timeout); |
15a0580c DB |
676 | } |
677 | ||
678 | /* | |
679 | * Read one block: | |
680 | * - skip leading all-ones bytes ... either | |
681 | * + N(AC) [1..f(clock,CSD)] usually, else | |
682 | * + N(CX) [0..8] when reading CSD or CID | |
683 | * - data block | |
684 | * + token ... if error token, no data or crc | |
685 | * + data bytes | |
686 | * + crc16 | |
687 | * | |
688 | * After single block reads, we're done; N(EC) [0+] all-ones bytes follow | |
689 | * before dropping chipselect. | |
690 | * | |
691 | * For multiblock reads, caller either reads the next block or issues a | |
692 | * STOP_TRANSMISSION command. | |
693 | */ | |
694 | static int | |
162350eb MF |
695 | mmc_spi_readblock(struct mmc_spi_host *host, struct spi_transfer *t, |
696 | ktime_t timeout) | |
15a0580c DB |
697 | { |
698 | struct spi_device *spi = host->spi; | |
699 | int status; | |
700 | struct scratch *scratch = host->data; | |
701 | ||
702 | /* At least one SD card sends an all-zeroes byte when N(CX) | |
703 | * applies, before the all-ones bytes ... just cope with that. | |
704 | */ | |
705 | status = mmc_spi_readbytes(host, 1); | |
706 | if (status < 0) | |
707 | return status; | |
708 | status = scratch->status[0]; | |
709 | if (status == 0xff || status == 0) | |
162350eb | 710 | status = mmc_spi_readtoken(host, timeout); |
15a0580c DB |
711 | |
712 | if (status == SPI_TOKEN_SINGLE) { | |
713 | if (host->dma_dev) { | |
714 | dma_sync_single_for_device(host->dma_dev, | |
715 | host->data_dma, sizeof(*scratch), | |
716 | DMA_BIDIRECTIONAL); | |
717 | dma_sync_single_for_device(host->dma_dev, | |
718 | t->rx_dma, t->len, | |
719 | DMA_FROM_DEVICE); | |
720 | } | |
721 | ||
722 | status = spi_sync(spi, &host->m); | |
15a0580c DB |
723 | |
724 | if (host->dma_dev) { | |
725 | dma_sync_single_for_cpu(host->dma_dev, | |
726 | host->data_dma, sizeof(*scratch), | |
727 | DMA_BIDIRECTIONAL); | |
728 | dma_sync_single_for_cpu(host->dma_dev, | |
729 | t->rx_dma, t->len, | |
730 | DMA_FROM_DEVICE); | |
731 | } | |
732 | ||
733 | } else { | |
734 | dev_dbg(&spi->dev, "read error %02x (%d)\n", status, status); | |
735 | ||
736 | /* we've read extra garbage, timed out, etc */ | |
737 | if (status < 0) | |
738 | return status; | |
739 | ||
740 | /* low four bits are an R2 subset, fifth seems to be | |
741 | * vendor specific ... map them all to generic error.. | |
742 | */ | |
743 | return -EIO; | |
744 | } | |
745 | ||
746 | if (host->mmc->use_spi_crc) { | |
747 | u16 crc = crc_itu_t(0, t->rx_buf, t->len); | |
748 | ||
749 | be16_to_cpus(&scratch->crc_val); | |
750 | if (scratch->crc_val != crc) { | |
751 | dev_dbg(&spi->dev, "read - crc error: crc_val=0x%04x, " | |
752 | "computed=0x%04x len=%d\n", | |
753 | scratch->crc_val, crc, t->len); | |
754 | return -EILSEQ; | |
755 | } | |
756 | } | |
757 | ||
758 | t->rx_buf += t->len; | |
759 | if (host->dma_dev) | |
760 | t->rx_dma += t->len; | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | /* | |
766 | * An MMC/SD data stage includes one or more blocks, optional CRCs, | |
767 | * and inline handshaking. That handhaking makes it unlike most | |
768 | * other SPI protocol stacks. | |
769 | */ | |
770 | static void | |
771 | mmc_spi_data_do(struct mmc_spi_host *host, struct mmc_command *cmd, | |
772 | struct mmc_data *data, u32 blk_size) | |
773 | { | |
774 | struct spi_device *spi = host->spi; | |
775 | struct device *dma_dev = host->dma_dev; | |
776 | struct spi_transfer *t; | |
777 | enum dma_data_direction direction; | |
778 | struct scatterlist *sg; | |
779 | unsigned n_sg; | |
780 | int multiple = (data->blocks > 1); | |
162350eb MF |
781 | u32 clock_rate; |
782 | ktime_t timeout; | |
15a0580c DB |
783 | |
784 | if (data->flags & MMC_DATA_READ) | |
785 | direction = DMA_FROM_DEVICE; | |
786 | else | |
787 | direction = DMA_TO_DEVICE; | |
788 | mmc_spi_setup_data_message(host, multiple, direction); | |
789 | t = &host->t; | |
790 | ||
162350eb MF |
791 | if (t->speed_hz) |
792 | clock_rate = t->speed_hz; | |
793 | else | |
794 | clock_rate = spi->max_speed_hz; | |
795 | ||
796 | timeout = ktime_add_ns(ktime_set(0, 0), data->timeout_ns + | |
797 | data->timeout_clks * 1000000 / clock_rate); | |
798 | ||
15a0580c DB |
799 | /* Handle scatterlist segments one at a time, with synch for |
800 | * each 512-byte block | |
801 | */ | |
802 | for (sg = data->sg, n_sg = data->sg_len; n_sg; n_sg--, sg++) { | |
803 | int status = 0; | |
804 | dma_addr_t dma_addr = 0; | |
805 | void *kmap_addr; | |
806 | unsigned length = sg->length; | |
807 | enum dma_data_direction dir = direction; | |
808 | ||
809 | /* set up dma mapping for controller drivers that might | |
810 | * use DMA ... though they may fall back to PIO | |
811 | */ | |
812 | if (dma_dev) { | |
813 | /* never invalidate whole *shared* pages ... */ | |
814 | if ((sg->offset != 0 || length != PAGE_SIZE) | |
815 | && dir == DMA_FROM_DEVICE) | |
816 | dir = DMA_BIDIRECTIONAL; | |
817 | ||
45711f1a | 818 | dma_addr = dma_map_page(dma_dev, sg_page(sg), 0, |
15a0580c DB |
819 | PAGE_SIZE, dir); |
820 | if (direction == DMA_TO_DEVICE) | |
821 | t->tx_dma = dma_addr + sg->offset; | |
822 | else | |
823 | t->rx_dma = dma_addr + sg->offset; | |
824 | } | |
825 | ||
826 | /* allow pio too; we don't allow highmem */ | |
45711f1a | 827 | kmap_addr = kmap(sg_page(sg)); |
15a0580c DB |
828 | if (direction == DMA_TO_DEVICE) |
829 | t->tx_buf = kmap_addr + sg->offset; | |
830 | else | |
831 | t->rx_buf = kmap_addr + sg->offset; | |
832 | ||
833 | /* transfer each block, and update request status */ | |
834 | while (length) { | |
835 | t->len = min(length, blk_size); | |
836 | ||
837 | dev_dbg(&host->spi->dev, | |
838 | " mmc_spi: %s block, %d bytes\n", | |
839 | (direction == DMA_TO_DEVICE) | |
840 | ? "write" | |
841 | : "read", | |
842 | t->len); | |
843 | ||
844 | if (direction == DMA_TO_DEVICE) | |
162350eb | 845 | status = mmc_spi_writeblock(host, t, timeout); |
15a0580c | 846 | else |
162350eb | 847 | status = mmc_spi_readblock(host, t, timeout); |
15a0580c DB |
848 | if (status < 0) |
849 | break; | |
850 | ||
851 | data->bytes_xfered += t->len; | |
852 | length -= t->len; | |
853 | ||
854 | if (!multiple) | |
855 | break; | |
856 | } | |
857 | ||
858 | /* discard mappings */ | |
859 | if (direction == DMA_FROM_DEVICE) | |
45711f1a JA |
860 | flush_kernel_dcache_page(sg_page(sg)); |
861 | kunmap(sg_page(sg)); | |
15a0580c DB |
862 | if (dma_dev) |
863 | dma_unmap_page(dma_dev, dma_addr, PAGE_SIZE, dir); | |
864 | ||
865 | if (status < 0) { | |
866 | data->error = status; | |
867 | dev_dbg(&spi->dev, "%s status %d\n", | |
868 | (direction == DMA_TO_DEVICE) | |
869 | ? "write" : "read", | |
870 | status); | |
871 | break; | |
872 | } | |
873 | } | |
874 | ||
875 | /* NOTE some docs describe an MMC-only SET_BLOCK_COUNT (CMD23) that | |
876 | * can be issued before multiblock writes. Unlike its more widely | |
877 | * documented analogue for SD cards (SET_WR_BLK_ERASE_COUNT, ACMD23), | |
878 | * that can affect the STOP_TRAN logic. Complete (and current) | |
879 | * MMC specs should sort that out before Linux starts using CMD23. | |
880 | */ | |
881 | if (direction == DMA_TO_DEVICE && multiple) { | |
882 | struct scratch *scratch = host->data; | |
883 | int tmp; | |
884 | const unsigned statlen = sizeof(scratch->status); | |
885 | ||
886 | dev_dbg(&spi->dev, " mmc_spi: STOP_TRAN\n"); | |
887 | ||
888 | /* Tweak the per-block message we set up earlier by morphing | |
889 | * it to hold single buffer with the token followed by some | |
890 | * all-ones bytes ... skip N(BR) (0..1), scan the rest for | |
891 | * "not busy any longer" status, and leave chip selected. | |
892 | */ | |
893 | INIT_LIST_HEAD(&host->m.transfers); | |
894 | list_add(&host->early_status.transfer_list, | |
895 | &host->m.transfers); | |
896 | ||
897 | memset(scratch->status, 0xff, statlen); | |
898 | scratch->status[0] = SPI_TOKEN_STOP_TRAN; | |
899 | ||
900 | host->early_status.tx_buf = host->early_status.rx_buf; | |
901 | host->early_status.tx_dma = host->early_status.rx_dma; | |
902 | host->early_status.len = statlen; | |
903 | ||
904 | if (host->dma_dev) | |
905 | dma_sync_single_for_device(host->dma_dev, | |
906 | host->data_dma, sizeof(*scratch), | |
907 | DMA_BIDIRECTIONAL); | |
908 | ||
909 | tmp = spi_sync(spi, &host->m); | |
15a0580c DB |
910 | |
911 | if (host->dma_dev) | |
912 | dma_sync_single_for_cpu(host->dma_dev, | |
913 | host->data_dma, sizeof(*scratch), | |
914 | DMA_BIDIRECTIONAL); | |
915 | ||
916 | if (tmp < 0) { | |
917 | if (!data->error) | |
918 | data->error = tmp; | |
919 | return; | |
920 | } | |
921 | ||
922 | /* Ideally we collected "not busy" status with one I/O, | |
923 | * avoiding wasteful byte-at-a-time scanning... but more | |
924 | * I/O is often needed. | |
925 | */ | |
926 | for (tmp = 2; tmp < statlen; tmp++) { | |
927 | if (scratch->status[tmp] != 0) | |
928 | return; | |
929 | } | |
162350eb | 930 | tmp = mmc_spi_wait_unbusy(host, timeout); |
15a0580c DB |
931 | if (tmp < 0 && !data->error) |
932 | data->error = tmp; | |
933 | } | |
934 | } | |
935 | ||
936 | /****************************************************************************/ | |
937 | ||
938 | /* | |
939 | * MMC driver implementation -- the interface to the MMC stack | |
940 | */ | |
941 | ||
942 | static void mmc_spi_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
943 | { | |
944 | struct mmc_spi_host *host = mmc_priv(mmc); | |
945 | int status = -EINVAL; | |
946 | ||
947 | #ifdef DEBUG | |
948 | /* MMC core and layered drivers *MUST* issue SPI-aware commands */ | |
949 | { | |
950 | struct mmc_command *cmd; | |
951 | int invalid = 0; | |
952 | ||
953 | cmd = mrq->cmd; | |
954 | if (!mmc_spi_resp_type(cmd)) { | |
955 | dev_dbg(&host->spi->dev, "bogus command\n"); | |
956 | cmd->error = -EINVAL; | |
957 | invalid = 1; | |
958 | } | |
959 | ||
960 | cmd = mrq->stop; | |
961 | if (cmd && !mmc_spi_resp_type(cmd)) { | |
962 | dev_dbg(&host->spi->dev, "bogus STOP command\n"); | |
963 | cmd->error = -EINVAL; | |
964 | invalid = 1; | |
965 | } | |
966 | ||
967 | if (invalid) { | |
968 | dump_stack(); | |
969 | mmc_request_done(host->mmc, mrq); | |
970 | return; | |
971 | } | |
972 | } | |
973 | #endif | |
974 | ||
975 | /* issue command; then optionally data and stop */ | |
976 | status = mmc_spi_command_send(host, mrq, mrq->cmd, mrq->data != NULL); | |
977 | if (status == 0 && mrq->data) { | |
978 | mmc_spi_data_do(host, mrq->cmd, mrq->data, mrq->data->blksz); | |
979 | if (mrq->stop) | |
980 | status = mmc_spi_command_send(host, mrq, mrq->stop, 0); | |
981 | else | |
982 | mmc_cs_off(host); | |
983 | } | |
984 | ||
985 | mmc_request_done(host->mmc, mrq); | |
986 | } | |
987 | ||
988 | /* See Section 6.4.1, in SD "Simplified Physical Layer Specification 2.0" | |
989 | * | |
990 | * NOTE that here we can't know that the card has just been powered up; | |
991 | * not all MMC/SD sockets support power switching. | |
992 | * | |
993 | * FIXME when the card is still in SPI mode, e.g. from a previous kernel, | |
994 | * this doesn't seem to do the right thing at all... | |
995 | */ | |
996 | static void mmc_spi_initsequence(struct mmc_spi_host *host) | |
997 | { | |
998 | /* Try to be very sure any previous command has completed; | |
999 | * wait till not-busy, skip debris from any old commands. | |
1000 | */ | |
1001 | mmc_spi_wait_unbusy(host, r1b_timeout); | |
1002 | mmc_spi_readbytes(host, 10); | |
1003 | ||
1004 | /* | |
1005 | * Do a burst with chipselect active-high. We need to do this to | |
1006 | * meet the requirement of 74 clock cycles with both chipselect | |
1007 | * and CMD (MOSI) high before CMD0 ... after the card has been | |
1008 | * powered up to Vdd(min), and so is ready to take commands. | |
1009 | * | |
1010 | * Some cards are particularly needy of this (e.g. Viking "SD256") | |
1011 | * while most others don't seem to care. | |
1012 | * | |
1013 | * Note that this is one of the places MMC/SD plays games with the | |
1014 | * SPI protocol. Another is that when chipselect is released while | |
1015 | * the card returns BUSY status, the clock must issue several cycles | |
1016 | * with chipselect high before the card will stop driving its output. | |
1017 | */ | |
1018 | host->spi->mode |= SPI_CS_HIGH; | |
1019 | if (spi_setup(host->spi) != 0) { | |
1020 | /* Just warn; most cards work without it. */ | |
1021 | dev_warn(&host->spi->dev, | |
1022 | "can't change chip-select polarity\n"); | |
1023 | host->spi->mode &= ~SPI_CS_HIGH; | |
1024 | } else { | |
1025 | mmc_spi_readbytes(host, 18); | |
1026 | ||
1027 | host->spi->mode &= ~SPI_CS_HIGH; | |
1028 | if (spi_setup(host->spi) != 0) { | |
1029 | /* Wot, we can't get the same setup we had before? */ | |
1030 | dev_err(&host->spi->dev, | |
1031 | "can't restore chip-select polarity\n"); | |
1032 | } | |
1033 | } | |
1034 | } | |
1035 | ||
1036 | static char *mmc_powerstring(u8 power_mode) | |
1037 | { | |
1038 | switch (power_mode) { | |
1039 | case MMC_POWER_OFF: return "off"; | |
1040 | case MMC_POWER_UP: return "up"; | |
1041 | case MMC_POWER_ON: return "on"; | |
1042 | } | |
1043 | return "?"; | |
1044 | } | |
1045 | ||
1046 | static void mmc_spi_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1047 | { | |
1048 | struct mmc_spi_host *host = mmc_priv(mmc); | |
1049 | ||
1050 | if (host->power_mode != ios->power_mode) { | |
1051 | int canpower; | |
1052 | ||
1053 | canpower = host->pdata && host->pdata->setpower; | |
1054 | ||
1055 | dev_dbg(&host->spi->dev, "mmc_spi: power %s (%d)%s\n", | |
1056 | mmc_powerstring(ios->power_mode), | |
1057 | ios->vdd, | |
1058 | canpower ? ", can switch" : ""); | |
1059 | ||
1060 | /* switch power on/off if possible, accounting for | |
1061 | * max 250msec powerup time if needed. | |
1062 | */ | |
1063 | if (canpower) { | |
1064 | switch (ios->power_mode) { | |
1065 | case MMC_POWER_OFF: | |
1066 | case MMC_POWER_UP: | |
1067 | host->pdata->setpower(&host->spi->dev, | |
1068 | ios->vdd); | |
1069 | if (ios->power_mode == MMC_POWER_UP) | |
1070 | msleep(host->powerup_msecs); | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | /* See 6.4.1 in the simplified SD card physical spec 2.0 */ | |
1075 | if (ios->power_mode == MMC_POWER_ON) | |
1076 | mmc_spi_initsequence(host); | |
1077 | ||
1078 | /* If powering down, ground all card inputs to avoid power | |
1079 | * delivery from data lines! On a shared SPI bus, this | |
1080 | * will probably be temporary; 6.4.2 of the simplified SD | |
1081 | * spec says this must last at least 1msec. | |
1082 | * | |
1083 | * - Clock low means CPOL 0, e.g. mode 0 | |
1084 | * - MOSI low comes from writing zero | |
1085 | * - Chipselect is usually active low... | |
1086 | */ | |
1087 | if (canpower && ios->power_mode == MMC_POWER_OFF) { | |
1088 | int mres; | |
1685a03e | 1089 | u8 nullbyte = 0; |
15a0580c DB |
1090 | |
1091 | host->spi->mode &= ~(SPI_CPOL|SPI_CPHA); | |
1092 | mres = spi_setup(host->spi); | |
1093 | if (mres < 0) | |
1094 | dev_dbg(&host->spi->dev, | |
1095 | "switch to SPI mode 0 failed\n"); | |
1096 | ||
1685a03e | 1097 | if (spi_write(host->spi, &nullbyte, 1) < 0) |
15a0580c DB |
1098 | dev_dbg(&host->spi->dev, |
1099 | "put spi signals to low failed\n"); | |
1100 | ||
1101 | /* | |
1102 | * Now clock should be low due to spi mode 0; | |
1103 | * MOSI should be low because of written 0x00; | |
1104 | * chipselect should be low (it is active low) | |
1105 | * power supply is off, so now MMC is off too! | |
1106 | * | |
1107 | * FIXME no, chipselect can be high since the | |
1108 | * device is inactive and SPI_CS_HIGH is clear... | |
1109 | */ | |
1110 | msleep(10); | |
1111 | if (mres == 0) { | |
1112 | host->spi->mode |= (SPI_CPOL|SPI_CPHA); | |
1113 | mres = spi_setup(host->spi); | |
1114 | if (mres < 0) | |
1115 | dev_dbg(&host->spi->dev, | |
1116 | "switch back to SPI mode 3" | |
1117 | " failed\n"); | |
1118 | } | |
1119 | } | |
1120 | ||
1121 | host->power_mode = ios->power_mode; | |
1122 | } | |
1123 | ||
1124 | if (host->spi->max_speed_hz != ios->clock && ios->clock != 0) { | |
1125 | int status; | |
1126 | ||
1127 | host->spi->max_speed_hz = ios->clock; | |
1128 | status = spi_setup(host->spi); | |
1129 | dev_dbg(&host->spi->dev, | |
1130 | "mmc_spi: clock to %d Hz, %d\n", | |
1131 | host->spi->max_speed_hz, status); | |
1132 | } | |
1133 | } | |
1134 | ||
1135 | static int mmc_spi_get_ro(struct mmc_host *mmc) | |
1136 | { | |
1137 | struct mmc_spi_host *host = mmc_priv(mmc); | |
1138 | ||
1139 | if (host->pdata && host->pdata->get_ro) | |
08f80bb5 AV |
1140 | return !!host->pdata->get_ro(mmc->parent); |
1141 | /* | |
1142 | * Board doesn't support read only detection; let the mmc core | |
1143 | * decide what to do. | |
1144 | */ | |
1145 | return -ENOSYS; | |
15a0580c DB |
1146 | } |
1147 | ||
619ef4b4 AV |
1148 | static int mmc_spi_get_cd(struct mmc_host *mmc) |
1149 | { | |
1150 | struct mmc_spi_host *host = mmc_priv(mmc); | |
1151 | ||
1152 | if (host->pdata && host->pdata->get_cd) | |
1153 | return !!host->pdata->get_cd(mmc->parent); | |
1154 | return -ENOSYS; | |
1155 | } | |
15a0580c DB |
1156 | |
1157 | static const struct mmc_host_ops mmc_spi_ops = { | |
1158 | .request = mmc_spi_request, | |
1159 | .set_ios = mmc_spi_set_ios, | |
1160 | .get_ro = mmc_spi_get_ro, | |
619ef4b4 | 1161 | .get_cd = mmc_spi_get_cd, |
15a0580c DB |
1162 | }; |
1163 | ||
1164 | ||
1165 | /****************************************************************************/ | |
1166 | ||
1167 | /* | |
1168 | * SPI driver implementation | |
1169 | */ | |
1170 | ||
1171 | static irqreturn_t | |
1172 | mmc_spi_detect_irq(int irq, void *mmc) | |
1173 | { | |
1174 | struct mmc_spi_host *host = mmc_priv(mmc); | |
1175 | u16 delay_msec = max(host->pdata->detect_delay, (u16)100); | |
1176 | ||
1177 | mmc_detect_change(mmc, msecs_to_jiffies(delay_msec)); | |
1178 | return IRQ_HANDLED; | |
1179 | } | |
1180 | ||
460cd058 DB |
1181 | struct count_children { |
1182 | unsigned n; | |
1183 | struct bus_type *bus; | |
1184 | }; | |
1185 | ||
1186 | static int maybe_count_child(struct device *dev, void *c) | |
1187 | { | |
1188 | struct count_children *ccp = c; | |
1189 | ||
1190 | if (dev->bus == ccp->bus) { | |
1191 | if (ccp->n) | |
1192 | return -EBUSY; | |
1193 | ccp->n++; | |
1194 | } | |
1195 | return 0; | |
1196 | } | |
1197 | ||
15a0580c DB |
1198 | static int mmc_spi_probe(struct spi_device *spi) |
1199 | { | |
1200 | void *ones; | |
1201 | struct mmc_host *mmc; | |
1202 | struct mmc_spi_host *host; | |
1203 | int status; | |
1204 | ||
1205 | /* MMC and SD specs only seem to care that sampling is on the | |
1206 | * rising edge ... meaning SPI modes 0 or 3. So either SPI mode | |
1207 | * should be legit. We'll use mode 0 since it seems to be a | |
1208 | * bit less troublesome on some hardware ... unclear why. | |
1209 | */ | |
1210 | spi->mode = SPI_MODE_0; | |
1211 | spi->bits_per_word = 8; | |
1212 | ||
1213 | status = spi_setup(spi); | |
1214 | if (status < 0) { | |
1215 | dev_dbg(&spi->dev, "needs SPI mode %02x, %d KHz; %d\n", | |
1216 | spi->mode, spi->max_speed_hz / 1000, | |
1217 | status); | |
1218 | return status; | |
1219 | } | |
1220 | ||
460cd058 DB |
1221 | /* We can use the bus safely iff nobody else will interfere with us. |
1222 | * Most commands consist of one SPI message to issue a command, then | |
1223 | * several more to collect its response, then possibly more for data | |
1224 | * transfer. Clocking access to other devices during that period will | |
1225 | * corrupt the command execution. | |
1226 | * | |
1227 | * Until we have software primitives which guarantee non-interference, | |
1228 | * we'll aim for a hardware-level guarantee. | |
1229 | * | |
1230 | * REVISIT we can't guarantee another device won't be added later... | |
15a0580c DB |
1231 | */ |
1232 | if (spi->master->num_chipselect > 1) { | |
460cd058 | 1233 | struct count_children cc; |
15a0580c | 1234 | |
460cd058 DB |
1235 | cc.n = 0; |
1236 | cc.bus = spi->dev.bus; | |
1237 | status = device_for_each_child(spi->dev.parent, &cc, | |
1238 | maybe_count_child); | |
15a0580c DB |
1239 | if (status < 0) { |
1240 | dev_err(&spi->dev, "can't share SPI bus\n"); | |
1241 | return status; | |
1242 | } | |
1243 | ||
460cd058 | 1244 | dev_warn(&spi->dev, "ASSUMING SPI bus stays unshared!\n"); |
15a0580c DB |
1245 | } |
1246 | ||
1247 | /* We need a supply of ones to transmit. This is the only time | |
1248 | * the CPU touches these, so cache coherency isn't a concern. | |
1249 | * | |
1250 | * NOTE if many systems use more than one MMC-over-SPI connector | |
1251 | * it'd save some memory to share this. That's evidently rare. | |
1252 | */ | |
1253 | status = -ENOMEM; | |
1254 | ones = kmalloc(MMC_SPI_BLOCKSIZE, GFP_KERNEL); | |
1255 | if (!ones) | |
1256 | goto nomem; | |
1257 | memset(ones, 0xff, MMC_SPI_BLOCKSIZE); | |
1258 | ||
1259 | mmc = mmc_alloc_host(sizeof(*host), &spi->dev); | |
1260 | if (!mmc) | |
1261 | goto nomem; | |
1262 | ||
1263 | mmc->ops = &mmc_spi_ops; | |
1264 | mmc->max_blk_size = MMC_SPI_BLOCKSIZE; | |
1265 | ||
23af6039 | 1266 | mmc->caps = MMC_CAP_SPI; |
15a0580c DB |
1267 | |
1268 | /* SPI doesn't need the lowspeed device identification thing for | |
1269 | * MMC or SD cards, since it never comes up in open drain mode. | |
1270 | * That's good; some SPI masters can't handle very low speeds! | |
1271 | * | |
1272 | * However, low speed SDIO cards need not handle over 400 KHz; | |
1273 | * that's the only reason not to use a few MHz for f_min (until | |
1274 | * the upper layer reads the target frequency from the CSD). | |
1275 | */ | |
1276 | mmc->f_min = 400000; | |
1277 | mmc->f_max = spi->max_speed_hz; | |
1278 | ||
1279 | host = mmc_priv(mmc); | |
1280 | host->mmc = mmc; | |
1281 | host->spi = spi; | |
1282 | ||
1283 | host->ones = ones; | |
1284 | ||
1285 | /* Platform data is used to hook up things like card sensing | |
1286 | * and power switching gpios. | |
1287 | */ | |
9c43df57 | 1288 | host->pdata = mmc_spi_get_pdata(spi); |
15a0580c DB |
1289 | if (host->pdata) |
1290 | mmc->ocr_avail = host->pdata->ocr_mask; | |
1291 | if (!mmc->ocr_avail) { | |
1292 | dev_warn(&spi->dev, "ASSUMING 3.2-3.4 V slot power\n"); | |
1293 | mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34; | |
1294 | } | |
1295 | if (host->pdata && host->pdata->setpower) { | |
1296 | host->powerup_msecs = host->pdata->powerup_msecs; | |
1297 | if (!host->powerup_msecs || host->powerup_msecs > 250) | |
1298 | host->powerup_msecs = 250; | |
1299 | } | |
1300 | ||
1301 | dev_set_drvdata(&spi->dev, mmc); | |
1302 | ||
1303 | /* preallocate dma buffers */ | |
1304 | host->data = kmalloc(sizeof(*host->data), GFP_KERNEL); | |
1305 | if (!host->data) | |
1306 | goto fail_nobuf1; | |
1307 | ||
49dce689 TJ |
1308 | if (spi->master->dev.parent->dma_mask) { |
1309 | struct device *dev = spi->master->dev.parent; | |
15a0580c DB |
1310 | |
1311 | host->dma_dev = dev; | |
1312 | host->ones_dma = dma_map_single(dev, ones, | |
1313 | MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE); | |
1314 | host->data_dma = dma_map_single(dev, host->data, | |
1315 | sizeof(*host->data), DMA_BIDIRECTIONAL); | |
1316 | ||
1317 | /* REVISIT in theory those map operations can fail... */ | |
1318 | ||
1319 | dma_sync_single_for_cpu(host->dma_dev, | |
1320 | host->data_dma, sizeof(*host->data), | |
1321 | DMA_BIDIRECTIONAL); | |
1322 | } | |
1323 | ||
1324 | /* setup message for status/busy readback */ | |
1325 | spi_message_init(&host->readback); | |
1326 | host->readback.is_dma_mapped = (host->dma_dev != NULL); | |
1327 | ||
1328 | spi_message_add_tail(&host->status, &host->readback); | |
1329 | host->status.tx_buf = host->ones; | |
1330 | host->status.tx_dma = host->ones_dma; | |
1331 | host->status.rx_buf = &host->data->status; | |
1332 | host->status.rx_dma = host->data_dma + offsetof(struct scratch, status); | |
1333 | host->status.cs_change = 1; | |
1334 | ||
1335 | /* register card detect irq */ | |
1336 | if (host->pdata && host->pdata->init) { | |
1337 | status = host->pdata->init(&spi->dev, mmc_spi_detect_irq, mmc); | |
1338 | if (status != 0) | |
1339 | goto fail_glue_init; | |
1340 | } | |
1341 | ||
619ef4b4 AV |
1342 | /* pass platform capabilities, if any */ |
1343 | if (host->pdata) | |
1344 | mmc->caps |= host->pdata->caps; | |
1345 | ||
15a0580c DB |
1346 | status = mmc_add_host(mmc); |
1347 | if (status != 0) | |
1348 | goto fail_add_host; | |
1349 | ||
619ef4b4 | 1350 | dev_info(&spi->dev, "SD/MMC host %s%s%s%s%s\n", |
d1b26863 | 1351 | dev_name(&mmc->class_dev), |
15a0580c DB |
1352 | host->dma_dev ? "" : ", no DMA", |
1353 | (host->pdata && host->pdata->get_ro) | |
1354 | ? "" : ", no WP", | |
1355 | (host->pdata && host->pdata->setpower) | |
619ef4b4 AV |
1356 | ? "" : ", no poweroff", |
1357 | (mmc->caps & MMC_CAP_NEEDS_POLL) | |
1358 | ? ", cd polling" : ""); | |
15a0580c DB |
1359 | return 0; |
1360 | ||
1361 | fail_add_host: | |
1362 | mmc_remove_host (mmc); | |
1363 | fail_glue_init: | |
1364 | if (host->dma_dev) | |
1365 | dma_unmap_single(host->dma_dev, host->data_dma, | |
1366 | sizeof(*host->data), DMA_BIDIRECTIONAL); | |
1367 | kfree(host->data); | |
1368 | ||
1369 | fail_nobuf1: | |
1370 | mmc_free_host(mmc); | |
9c43df57 | 1371 | mmc_spi_put_pdata(spi); |
15a0580c DB |
1372 | dev_set_drvdata(&spi->dev, NULL); |
1373 | ||
1374 | nomem: | |
1375 | kfree(ones); | |
1376 | return status; | |
1377 | } | |
1378 | ||
1379 | ||
1380 | static int __devexit mmc_spi_remove(struct spi_device *spi) | |
1381 | { | |
1382 | struct mmc_host *mmc = dev_get_drvdata(&spi->dev); | |
1383 | struct mmc_spi_host *host; | |
1384 | ||
1385 | if (mmc) { | |
1386 | host = mmc_priv(mmc); | |
1387 | ||
1388 | /* prevent new mmc_detect_change() calls */ | |
1389 | if (host->pdata && host->pdata->exit) | |
1390 | host->pdata->exit(&spi->dev, mmc); | |
1391 | ||
1392 | mmc_remove_host(mmc); | |
1393 | ||
1394 | if (host->dma_dev) { | |
1395 | dma_unmap_single(host->dma_dev, host->ones_dma, | |
1396 | MMC_SPI_BLOCKSIZE, DMA_TO_DEVICE); | |
1397 | dma_unmap_single(host->dma_dev, host->data_dma, | |
1398 | sizeof(*host->data), DMA_BIDIRECTIONAL); | |
1399 | } | |
1400 | ||
1401 | kfree(host->data); | |
1402 | kfree(host->ones); | |
1403 | ||
1404 | spi->max_speed_hz = mmc->f_max; | |
1405 | mmc_free_host(mmc); | |
9c43df57 | 1406 | mmc_spi_put_pdata(spi); |
15a0580c DB |
1407 | dev_set_drvdata(&spi->dev, NULL); |
1408 | } | |
1409 | return 0; | |
1410 | } | |
1411 | ||
1412 | ||
1413 | static struct spi_driver mmc_spi_driver = { | |
1414 | .driver = { | |
1415 | .name = "mmc_spi", | |
1416 | .bus = &spi_bus_type, | |
1417 | .owner = THIS_MODULE, | |
1418 | }, | |
1419 | .probe = mmc_spi_probe, | |
1420 | .remove = __devexit_p(mmc_spi_remove), | |
1421 | }; | |
1422 | ||
1423 | ||
1424 | static int __init mmc_spi_init(void) | |
1425 | { | |
1426 | return spi_register_driver(&mmc_spi_driver); | |
1427 | } | |
1428 | module_init(mmc_spi_init); | |
1429 | ||
1430 | ||
1431 | static void __exit mmc_spi_exit(void) | |
1432 | { | |
1433 | spi_unregister_driver(&mmc_spi_driver); | |
1434 | } | |
1435 | module_exit(mmc_spi_exit); | |
1436 | ||
1437 | ||
1438 | MODULE_AUTHOR("Mike Lavender, David Brownell, " | |
1439 | "Hans-Peter Nilsson, Jan Nikitenko"); | |
1440 | MODULE_DESCRIPTION("SPI SD/MMC host driver"); | |
1441 | MODULE_LICENSE("GPL"); |