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Commit | Line | Data |
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1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
64de0289 | 5 | * Copyright (C) 2010 ST-Ericsson AB. |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/highmem.h> | |
019a5f56 | 20 | #include <linux/log2.h> |
1da177e4 | 21 | #include <linux/mmc/host.h> |
a62c80e5 | 22 | #include <linux/amba/bus.h> |
f8ce2547 | 23 | #include <linux/clk.h> |
bd6dee6f | 24 | #include <linux/scatterlist.h> |
89001446 | 25 | #include <linux/gpio.h> |
6ef297f8 | 26 | #include <linux/amba/mmci.h> |
34e84f39 | 27 | #include <linux/regulator/consumer.h> |
1da177e4 | 28 | |
7b09cdac | 29 | #include <asm/div64.h> |
1da177e4 | 30 | #include <asm/io.h> |
c6b8fdad | 31 | #include <asm/sizes.h> |
1da177e4 LT |
32 | |
33 | #include "mmci.h" | |
34 | ||
35 | #define DRIVER_NAME "mmci-pl18x" | |
36 | ||
1da177e4 LT |
37 | static unsigned int fmax = 515633; |
38 | ||
4956e109 RV |
39 | /** |
40 | * struct variant_data - MMCI variant-specific quirks | |
41 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 42 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 43 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
44 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
45 | * is asserted (likewise for RX) | |
46 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
47 | * is asserted (likewise for RX) | |
4956e109 RV |
48 | */ |
49 | struct variant_data { | |
50 | unsigned int clkreg; | |
4380c14f | 51 | unsigned int clkreg_enable; |
08458ef6 | 52 | unsigned int datalength_bits; |
8301bb68 RV |
53 | unsigned int fifosize; |
54 | unsigned int fifohalfsize; | |
4956e109 RV |
55 | }; |
56 | ||
57 | static struct variant_data variant_arm = { | |
8301bb68 RV |
58 | .fifosize = 16 * 4, |
59 | .fifohalfsize = 8 * 4, | |
08458ef6 | 60 | .datalength_bits = 16, |
4956e109 RV |
61 | }; |
62 | ||
63 | static struct variant_data variant_u300 = { | |
8301bb68 RV |
64 | .fifosize = 16 * 4, |
65 | .fifohalfsize = 8 * 4, | |
4380c14f | 66 | .clkreg_enable = 1 << 13, /* HWFCEN */ |
08458ef6 | 67 | .datalength_bits = 16, |
4956e109 RV |
68 | }; |
69 | ||
70 | static struct variant_data variant_ux500 = { | |
8301bb68 RV |
71 | .fifosize = 30 * 4, |
72 | .fifohalfsize = 8 * 4, | |
4956e109 | 73 | .clkreg = MCI_CLK_ENABLE, |
4380c14f | 74 | .clkreg_enable = 1 << 14, /* HWFCEN */ |
08458ef6 | 75 | .datalength_bits = 24, |
4956e109 | 76 | }; |
a6a6464a LW |
77 | /* |
78 | * This must be called with host->lock held | |
79 | */ | |
80 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
81 | { | |
4956e109 RV |
82 | struct variant_data *variant = host->variant; |
83 | u32 clk = variant->clkreg; | |
a6a6464a LW |
84 | |
85 | if (desired) { | |
86 | if (desired >= host->mclk) { | |
87 | clk = MCI_CLK_BYPASS; | |
88 | host->cclk = host->mclk; | |
89 | } else { | |
90 | clk = host->mclk / (2 * desired) - 1; | |
91 | if (clk >= 256) | |
92 | clk = 255; | |
93 | host->cclk = host->mclk / (2 * (clk + 1)); | |
94 | } | |
4380c14f RV |
95 | |
96 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
97 | clk |= MCI_CLK_ENABLE; |
98 | /* This hasn't proven to be worthwhile */ | |
99 | /* clk |= MCI_CLK_PWRSAVE; */ | |
100 | } | |
101 | ||
9e6c82cd | 102 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
103 | clk |= MCI_4BIT_BUS; |
104 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
105 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 106 | |
a6a6464a LW |
107 | writel(clk, host->base + MMCICLOCK); |
108 | } | |
109 | ||
1da177e4 LT |
110 | static void |
111 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
112 | { | |
113 | writel(0, host->base + MMCICOMMAND); | |
114 | ||
e47c222b RK |
115 | BUG_ON(host->data); |
116 | ||
1da177e4 LT |
117 | host->mrq = NULL; |
118 | host->cmd = NULL; | |
119 | ||
120 | if (mrq->data) | |
121 | mrq->data->bytes_xfered = host->data_xfered; | |
122 | ||
123 | /* | |
124 | * Need to drop the host lock here; mmc_request_done may call | |
125 | * back into the driver... | |
126 | */ | |
127 | spin_unlock(&host->lock); | |
128 | mmc_request_done(host->mmc, mrq); | |
129 | spin_lock(&host->lock); | |
130 | } | |
131 | ||
132 | static void mmci_stop_data(struct mmci_host *host) | |
133 | { | |
134 | writel(0, host->base + MMCIDATACTRL); | |
135 | writel(0, host->base + MMCIMASK1); | |
136 | host->data = NULL; | |
137 | } | |
138 | ||
4ce1d6cb RV |
139 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
140 | { | |
141 | unsigned int flags = SG_MITER_ATOMIC; | |
142 | ||
143 | if (data->flags & MMC_DATA_READ) | |
144 | flags |= SG_MITER_TO_SG; | |
145 | else | |
146 | flags |= SG_MITER_FROM_SG; | |
147 | ||
148 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
149 | } | |
150 | ||
1da177e4 LT |
151 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
152 | { | |
8301bb68 | 153 | struct variant_data *variant = host->variant; |
1da177e4 | 154 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 155 | unsigned long long clks; |
1da177e4 | 156 | void __iomem *base; |
3bc87f24 | 157 | int blksz_bits; |
1da177e4 | 158 | |
64de0289 LW |
159 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
160 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
161 | |
162 | host->data = data; | |
528320db | 163 | host->size = data->blksz * data->blocks; |
1da177e4 LT |
164 | host->data_xfered = 0; |
165 | ||
166 | mmci_init_sg(host, data); | |
167 | ||
7b09cdac RK |
168 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
169 | do_div(clks, 1000000000UL); | |
170 | ||
171 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
172 | |
173 | base = host->base; | |
174 | writel(timeout, base + MMCIDATATIMER); | |
175 | writel(host->size, base + MMCIDATALENGTH); | |
176 | ||
3bc87f24 RK |
177 | blksz_bits = ffs(data->blksz) - 1; |
178 | BUG_ON(1 << blksz_bits != data->blksz); | |
179 | ||
180 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
1da177e4 LT |
181 | if (data->flags & MMC_DATA_READ) { |
182 | datactrl |= MCI_DPSM_DIRECTION; | |
183 | irqmask = MCI_RXFIFOHALFFULLMASK; | |
0425a142 RK |
184 | |
185 | /* | |
186 | * If we have less than a FIFOSIZE of bytes to transfer, | |
187 | * trigger a PIO interrupt as soon as any data is available. | |
188 | */ | |
8301bb68 | 189 | if (host->size < variant->fifosize) |
0425a142 | 190 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
191 | } else { |
192 | /* | |
193 | * We don't actually need to include "FIFO empty" here | |
194 | * since its implicit in "FIFO half empty". | |
195 | */ | |
196 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
197 | } | |
198 | ||
199 | writel(datactrl, base + MMCIDATACTRL); | |
200 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
201 | writel(irqmask, base + MMCIMASK1); | |
202 | } | |
203 | ||
204 | static void | |
205 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
206 | { | |
207 | void __iomem *base = host->base; | |
208 | ||
64de0289 | 209 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
210 | cmd->opcode, cmd->arg, cmd->flags); |
211 | ||
212 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
213 | writel(0, base + MMCICOMMAND); | |
214 | udelay(1); | |
215 | } | |
216 | ||
217 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
218 | if (cmd->flags & MMC_RSP_PRESENT) { |
219 | if (cmd->flags & MMC_RSP_136) | |
220 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 221 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
222 | } |
223 | if (/*interrupt*/0) | |
224 | c |= MCI_CPSM_INTERRUPT; | |
225 | ||
226 | host->cmd = cmd; | |
227 | ||
228 | writel(cmd->arg, base + MMCIARGUMENT); | |
229 | writel(c, base + MMCICOMMAND); | |
230 | } | |
231 | ||
232 | static void | |
233 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
234 | unsigned int status) | |
235 | { | |
236 | if (status & MCI_DATABLOCKEND) { | |
3bc87f24 | 237 | host->data_xfered += data->blksz; |
f28e8a4d LW |
238 | #ifdef CONFIG_ARCH_U300 |
239 | /* | |
240 | * On the U300 some signal or other is | |
241 | * badly routed so that a data write does | |
242 | * not properly terminate with a MCI_DATAEND | |
243 | * status flag. This quirk will make writes | |
244 | * work again. | |
245 | */ | |
246 | if (data->flags & MMC_DATA_WRITE) | |
247 | status |= MCI_DATAEND; | |
248 | #endif | |
1da177e4 LT |
249 | } |
250 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
64de0289 | 251 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); |
1da177e4 | 252 | if (status & MCI_DATACRCFAIL) |
17b0429d | 253 | data->error = -EILSEQ; |
1da177e4 | 254 | else if (status & MCI_DATATIMEOUT) |
17b0429d | 255 | data->error = -ETIMEDOUT; |
1da177e4 | 256 | else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) |
17b0429d | 257 | data->error = -EIO; |
1da177e4 | 258 | status |= MCI_DATAEND; |
e9c091b4 RK |
259 | |
260 | /* | |
261 | * We hit an error condition. Ensure that any data | |
262 | * partially written to a page is properly coherent. | |
263 | */ | |
4ce1d6cb RV |
264 | if (data->flags & MMC_DATA_READ) { |
265 | struct sg_mapping_iter *sg_miter = &host->sg_miter; | |
266 | unsigned long flags; | |
267 | ||
268 | local_irq_save(flags); | |
269 | if (sg_miter_next(sg_miter)) { | |
270 | flush_dcache_page(sg_miter->page); | |
271 | sg_miter_stop(sg_miter); | |
272 | } | |
273 | local_irq_restore(flags); | |
274 | } | |
1da177e4 LT |
275 | } |
276 | if (status & MCI_DATAEND) { | |
277 | mmci_stop_data(host); | |
278 | ||
279 | if (!data->stop) { | |
280 | mmci_request_end(host, data->mrq); | |
281 | } else { | |
282 | mmci_start_command(host, data->stop, 0); | |
283 | } | |
284 | } | |
285 | } | |
286 | ||
287 | static void | |
288 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
289 | unsigned int status) | |
290 | { | |
291 | void __iomem *base = host->base; | |
292 | ||
293 | host->cmd = NULL; | |
294 | ||
295 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
296 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
297 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
298 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
299 | ||
300 | if (status & MCI_CMDTIMEOUT) { | |
17b0429d | 301 | cmd->error = -ETIMEDOUT; |
1da177e4 | 302 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 303 | cmd->error = -EILSEQ; |
1da177e4 LT |
304 | } |
305 | ||
17b0429d | 306 | if (!cmd->data || cmd->error) { |
e47c222b RK |
307 | if (host->data) |
308 | mmci_stop_data(host); | |
1da177e4 LT |
309 | mmci_request_end(host, cmd->mrq); |
310 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
311 | mmci_start_data(host, cmd->data); | |
312 | } | |
313 | } | |
314 | ||
315 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
316 | { | |
317 | void __iomem *base = host->base; | |
318 | char *ptr = buffer; | |
319 | u32 status; | |
26eed9a5 | 320 | int host_remain = host->size; |
1da177e4 LT |
321 | |
322 | do { | |
26eed9a5 | 323 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
324 | |
325 | if (count > remain) | |
326 | count = remain; | |
327 | ||
328 | if (count <= 0) | |
329 | break; | |
330 | ||
331 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
332 | ||
333 | ptr += count; | |
334 | remain -= count; | |
26eed9a5 | 335 | host_remain -= count; |
1da177e4 LT |
336 | |
337 | if (remain == 0) | |
338 | break; | |
339 | ||
340 | status = readl(base + MMCISTATUS); | |
341 | } while (status & MCI_RXDATAAVLBL); | |
342 | ||
343 | return ptr - buffer; | |
344 | } | |
345 | ||
346 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
347 | { | |
8301bb68 | 348 | struct variant_data *variant = host->variant; |
1da177e4 LT |
349 | void __iomem *base = host->base; |
350 | char *ptr = buffer; | |
351 | ||
352 | do { | |
353 | unsigned int count, maxcnt; | |
354 | ||
8301bb68 RV |
355 | maxcnt = status & MCI_TXFIFOEMPTY ? |
356 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
357 | count = min(remain, maxcnt); |
358 | ||
359 | writesl(base + MMCIFIFO, ptr, count >> 2); | |
360 | ||
361 | ptr += count; | |
362 | remain -= count; | |
363 | ||
364 | if (remain == 0) | |
365 | break; | |
366 | ||
367 | status = readl(base + MMCISTATUS); | |
368 | } while (status & MCI_TXFIFOHALFEMPTY); | |
369 | ||
370 | return ptr - buffer; | |
371 | } | |
372 | ||
373 | /* | |
374 | * PIO data transfer IRQ handler. | |
375 | */ | |
7d12e780 | 376 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
377 | { |
378 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 379 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 380 | struct variant_data *variant = host->variant; |
1da177e4 | 381 | void __iomem *base = host->base; |
4ce1d6cb | 382 | unsigned long flags; |
1da177e4 LT |
383 | u32 status; |
384 | ||
385 | status = readl(base + MMCISTATUS); | |
386 | ||
64de0289 | 387 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 388 | |
4ce1d6cb RV |
389 | local_irq_save(flags); |
390 | ||
1da177e4 | 391 | do { |
1da177e4 LT |
392 | unsigned int remain, len; |
393 | char *buffer; | |
394 | ||
395 | /* | |
396 | * For write, we only need to test the half-empty flag | |
397 | * here - if the FIFO is completely empty, then by | |
398 | * definition it is more than half empty. | |
399 | * | |
400 | * For read, check for data available. | |
401 | */ | |
402 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
403 | break; | |
404 | ||
4ce1d6cb RV |
405 | if (!sg_miter_next(sg_miter)) |
406 | break; | |
407 | ||
408 | buffer = sg_miter->addr; | |
409 | remain = sg_miter->length; | |
1da177e4 LT |
410 | |
411 | len = 0; | |
412 | if (status & MCI_RXACTIVE) | |
413 | len = mmci_pio_read(host, buffer, remain); | |
414 | if (status & MCI_TXACTIVE) | |
415 | len = mmci_pio_write(host, buffer, remain, status); | |
416 | ||
4ce1d6cb | 417 | sg_miter->consumed = len; |
1da177e4 | 418 | |
1da177e4 LT |
419 | host->size -= len; |
420 | remain -= len; | |
421 | ||
422 | if (remain) | |
423 | break; | |
424 | ||
e9c091b4 | 425 | if (status & MCI_RXACTIVE) |
4ce1d6cb | 426 | flush_dcache_page(sg_miter->page); |
1da177e4 LT |
427 | |
428 | status = readl(base + MMCISTATUS); | |
429 | } while (1); | |
430 | ||
4ce1d6cb RV |
431 | sg_miter_stop(sg_miter); |
432 | ||
433 | local_irq_restore(flags); | |
434 | ||
1da177e4 LT |
435 | /* |
436 | * If we're nearing the end of the read, switch to | |
437 | * "any data available" mode. | |
438 | */ | |
8301bb68 | 439 | if (status & MCI_RXACTIVE && host->size < variant->fifosize) |
1da177e4 LT |
440 | writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); |
441 | ||
442 | /* | |
443 | * If we run out of data, disable the data IRQs; this | |
444 | * prevents a race where the FIFO becomes empty before | |
445 | * the chip itself has disabled the data path, and | |
446 | * stops us racing with our data end IRQ. | |
447 | */ | |
448 | if (host->size == 0) { | |
449 | writel(0, base + MMCIMASK1); | |
450 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); | |
451 | } | |
452 | ||
453 | return IRQ_HANDLED; | |
454 | } | |
455 | ||
456 | /* | |
457 | * Handle completion of command and data transfers. | |
458 | */ | |
7d12e780 | 459 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
460 | { |
461 | struct mmci_host *host = dev_id; | |
462 | u32 status; | |
463 | int ret = 0; | |
464 | ||
465 | spin_lock(&host->lock); | |
466 | ||
467 | do { | |
468 | struct mmc_command *cmd; | |
469 | struct mmc_data *data; | |
470 | ||
471 | status = readl(host->base + MMCISTATUS); | |
472 | status &= readl(host->base + MMCIMASK0); | |
473 | writel(status, host->base + MMCICLEAR); | |
474 | ||
64de0289 | 475 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
476 | |
477 | data = host->data; | |
478 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | |
479 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) | |
480 | mmci_data_irq(host, data, status); | |
481 | ||
482 | cmd = host->cmd; | |
483 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
484 | mmci_cmd_irq(host, cmd, status); | |
485 | ||
486 | ret = 1; | |
487 | } while (status); | |
488 | ||
489 | spin_unlock(&host->lock); | |
490 | ||
491 | return IRQ_RETVAL(ret); | |
492 | } | |
493 | ||
494 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
495 | { | |
496 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 497 | unsigned long flags; |
1da177e4 LT |
498 | |
499 | WARN_ON(host->mrq != NULL); | |
500 | ||
019a5f56 | 501 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
502 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
503 | mrq->data->blksz); | |
255d01af PO |
504 | mrq->cmd->error = -EINVAL; |
505 | mmc_request_done(mmc, mrq); | |
506 | return; | |
507 | } | |
508 | ||
9e943021 | 509 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
510 | |
511 | host->mrq = mrq; | |
512 | ||
513 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) | |
514 | mmci_start_data(host, mrq->data); | |
515 | ||
516 | mmci_start_command(host, mrq->cmd, 0); | |
517 | ||
9e943021 | 518 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
519 | } |
520 | ||
521 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
522 | { | |
523 | struct mmci_host *host = mmc_priv(mmc); | |
a6a6464a LW |
524 | u32 pwr = 0; |
525 | unsigned long flags; | |
1da177e4 | 526 | |
1da177e4 LT |
527 | switch (ios->power_mode) { |
528 | case MMC_POWER_OFF: | |
34e84f39 LW |
529 | if(host->vcc && |
530 | regulator_is_enabled(host->vcc)) | |
531 | regulator_disable(host->vcc); | |
1da177e4 LT |
532 | break; |
533 | case MMC_POWER_UP: | |
34e84f39 LW |
534 | #ifdef CONFIG_REGULATOR |
535 | if (host->vcc) | |
536 | /* This implicitly enables the regulator */ | |
537 | mmc_regulator_set_ocr(host->vcc, ios->vdd); | |
538 | #endif | |
bb8f563c RV |
539 | if (host->plat->vdd_handler) |
540 | pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, | |
541 | ios->power_mode); | |
cc30d60e | 542 | /* The ST version does not have this, fall through to POWER_ON */ |
f17a1f06 | 543 | if (host->hw_designer != AMBA_VENDOR_ST) { |
cc30d60e LW |
544 | pwr |= MCI_PWR_UP; |
545 | break; | |
546 | } | |
1da177e4 LT |
547 | case MMC_POWER_ON: |
548 | pwr |= MCI_PWR_ON; | |
549 | break; | |
550 | } | |
551 | ||
cc30d60e | 552 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 553 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
554 | pwr |= MCI_ROD; |
555 | else { | |
556 | /* | |
557 | * The ST Micro variant use the ROD bit for something | |
558 | * else and only has OD (Open Drain). | |
559 | */ | |
560 | pwr |= MCI_OD; | |
561 | } | |
562 | } | |
1da177e4 | 563 | |
a6a6464a LW |
564 | spin_lock_irqsave(&host->lock, flags); |
565 | ||
566 | mmci_set_clkreg(host, ios->clock); | |
1da177e4 LT |
567 | |
568 | if (host->pwr != pwr) { | |
569 | host->pwr = pwr; | |
570 | writel(pwr, host->base + MMCIPOWER); | |
571 | } | |
a6a6464a LW |
572 | |
573 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
574 | } |
575 | ||
89001446 RK |
576 | static int mmci_get_ro(struct mmc_host *mmc) |
577 | { | |
578 | struct mmci_host *host = mmc_priv(mmc); | |
579 | ||
580 | if (host->gpio_wp == -ENOSYS) | |
581 | return -ENOSYS; | |
582 | ||
583 | return gpio_get_value(host->gpio_wp); | |
584 | } | |
585 | ||
586 | static int mmci_get_cd(struct mmc_host *mmc) | |
587 | { | |
588 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 589 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
590 | unsigned int status; |
591 | ||
592 | if (host->gpio_cd == -ENOSYS) | |
29719445 | 593 | status = plat->status(mmc_dev(host->mmc)); |
89001446 | 594 | else |
29719445 | 595 | status = !!gpio_get_value(host->gpio_cd) ^ plat->cd_invert; |
89001446 | 596 | |
74bc8093 RK |
597 | /* |
598 | * Use positive logic throughout - status is zero for no card, | |
599 | * non-zero for card inserted. | |
600 | */ | |
601 | return status; | |
89001446 RK |
602 | } |
603 | ||
148b8b39 RV |
604 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
605 | { | |
606 | struct mmci_host *host = dev_id; | |
607 | ||
608 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
609 | ||
610 | return IRQ_HANDLED; | |
611 | } | |
612 | ||
ab7aefd0 | 613 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 LT |
614 | .request = mmci_request, |
615 | .set_ios = mmci_set_ios, | |
89001446 RK |
616 | .get_ro = mmci_get_ro, |
617 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
618 | }; |
619 | ||
03fbdb15 | 620 | static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) |
1da177e4 | 621 | { |
6ef297f8 | 622 | struct mmci_platform_data *plat = dev->dev.platform_data; |
4956e109 | 623 | struct variant_data *variant = id->data; |
1da177e4 LT |
624 | struct mmci_host *host; |
625 | struct mmc_host *mmc; | |
626 | int ret; | |
627 | ||
628 | /* must have platform data */ | |
629 | if (!plat) { | |
630 | ret = -EINVAL; | |
631 | goto out; | |
632 | } | |
633 | ||
634 | ret = amba_request_regions(dev, DRIVER_NAME); | |
635 | if (ret) | |
636 | goto out; | |
637 | ||
638 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
639 | if (!mmc) { | |
640 | ret = -ENOMEM; | |
641 | goto rel_regions; | |
642 | } | |
643 | ||
644 | host = mmc_priv(mmc); | |
4ea580f1 | 645 | host->mmc = mmc; |
012b7d33 | 646 | |
89001446 RK |
647 | host->gpio_wp = -ENOSYS; |
648 | host->gpio_cd = -ENOSYS; | |
148b8b39 | 649 | host->gpio_cd_irq = -1; |
89001446 | 650 | |
012b7d33 RK |
651 | host->hw_designer = amba_manf(dev); |
652 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
653 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
654 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 655 | |
ee569c43 | 656 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
657 | if (IS_ERR(host->clk)) { |
658 | ret = PTR_ERR(host->clk); | |
659 | host->clk = NULL; | |
660 | goto host_free; | |
661 | } | |
662 | ||
1da177e4 LT |
663 | ret = clk_enable(host->clk); |
664 | if (ret) | |
a8d3584a | 665 | goto clk_free; |
1da177e4 LT |
666 | |
667 | host->plat = plat; | |
4956e109 | 668 | host->variant = variant; |
1da177e4 | 669 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
670 | /* |
671 | * According to the spec, mclk is max 100 MHz, | |
672 | * so we try to adjust the clock down to this, | |
673 | * (if possible). | |
674 | */ | |
675 | if (host->mclk > 100000000) { | |
676 | ret = clk_set_rate(host->clk, 100000000); | |
677 | if (ret < 0) | |
678 | goto clk_disable; | |
679 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
680 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
681 | host->mclk); | |
c8df9a53 | 682 | } |
dc890c2d | 683 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
684 | if (!host->base) { |
685 | ret = -ENOMEM; | |
686 | goto clk_disable; | |
687 | } | |
688 | ||
689 | mmc->ops = &mmci_ops; | |
690 | mmc->f_min = (host->mclk + 511) / 512; | |
808d97cc LW |
691 | /* |
692 | * If the platform data supplies a maximum operating | |
693 | * frequency, this takes precedence. Else, we fall back | |
694 | * to using the module parameter, which has a (low) | |
695 | * default value in case it is not specified. Either | |
696 | * value must not exceed the clock rate into the block, | |
697 | * of course. | |
698 | */ | |
699 | if (plat->f_max) | |
700 | mmc->f_max = min(host->mclk, plat->f_max); | |
701 | else | |
702 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
703 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
704 | ||
34e84f39 LW |
705 | #ifdef CONFIG_REGULATOR |
706 | /* If we're using the regulator framework, try to fetch a regulator */ | |
707 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
708 | if (IS_ERR(host->vcc)) | |
709 | host->vcc = NULL; | |
710 | else { | |
711 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
712 | ||
713 | if (mask < 0) | |
714 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
715 | mask); | |
716 | else { | |
717 | host->mmc->ocr_avail = (u32) mask; | |
718 | if (plat->ocr_mask) | |
719 | dev_warn(&dev->dev, | |
720 | "Provided ocr_mask/setpower will not be used " | |
721 | "(using regulator instead)\n"); | |
722 | } | |
723 | } | |
724 | #endif | |
725 | /* Fall back to platform data if no regulator is found */ | |
726 | if (host->vcc == NULL) | |
727 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 728 | mmc->caps = plat->capabilities; |
1da177e4 LT |
729 | |
730 | /* | |
731 | * We can do SGIO | |
732 | */ | |
733 | mmc->max_hw_segs = 16; | |
734 | mmc->max_phys_segs = NR_SG; | |
735 | ||
736 | /* | |
08458ef6 RV |
737 | * Since only a certain number of bits are valid in the data length |
738 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
739 | * single request. | |
1da177e4 | 740 | */ |
08458ef6 | 741 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
742 | |
743 | /* | |
744 | * Set the maximum segment size. Since we aren't doing DMA | |
745 | * (yet) we are only limited by the data length register. | |
746 | */ | |
55db890a | 747 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 748 | |
fe4a3c7a PO |
749 | /* |
750 | * Block size can be up to 2048 bytes, but must be a power of two. | |
751 | */ | |
752 | mmc->max_blk_size = 2048; | |
753 | ||
55db890a PO |
754 | /* |
755 | * No limit on the number of blocks transferred. | |
756 | */ | |
757 | mmc->max_blk_count = mmc->max_req_size; | |
758 | ||
1da177e4 LT |
759 | spin_lock_init(&host->lock); |
760 | ||
761 | writel(0, host->base + MMCIMASK0); | |
762 | writel(0, host->base + MMCIMASK1); | |
763 | writel(0xfff, host->base + MMCICLEAR); | |
764 | ||
89001446 RK |
765 | if (gpio_is_valid(plat->gpio_cd)) { |
766 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
767 | if (ret == 0) | |
768 | ret = gpio_direction_input(plat->gpio_cd); | |
769 | if (ret == 0) | |
770 | host->gpio_cd = plat->gpio_cd; | |
771 | else if (ret != -ENOSYS) | |
772 | goto err_gpio_cd; | |
148b8b39 RV |
773 | |
774 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), | |
775 | mmci_cd_irq, 0, | |
776 | DRIVER_NAME " (cd)", host); | |
777 | if (ret >= 0) | |
778 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); | |
89001446 RK |
779 | } |
780 | if (gpio_is_valid(plat->gpio_wp)) { | |
781 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
782 | if (ret == 0) | |
783 | ret = gpio_direction_input(plat->gpio_wp); | |
784 | if (ret == 0) | |
785 | host->gpio_wp = plat->gpio_wp; | |
786 | else if (ret != -ENOSYS) | |
787 | goto err_gpio_wp; | |
788 | } | |
789 | ||
148b8b39 RV |
790 | if (host->gpio_cd_irq < 0) |
791 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
792 | ||
dace1453 | 793 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
794 | if (ret) |
795 | goto unmap; | |
796 | ||
dace1453 | 797 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host); |
1da177e4 LT |
798 | if (ret) |
799 | goto irq0_free; | |
800 | ||
801 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
802 | ||
803 | amba_set_drvdata(dev, mmc); | |
804 | ||
805 | mmc_add_host(mmc); | |
806 | ||
64de0289 | 807 | dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", |
d366b643 | 808 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), |
e29419ff | 809 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); |
1da177e4 | 810 | |
1da177e4 LT |
811 | return 0; |
812 | ||
813 | irq0_free: | |
814 | free_irq(dev->irq[0], host); | |
815 | unmap: | |
89001446 RK |
816 | if (host->gpio_wp != -ENOSYS) |
817 | gpio_free(host->gpio_wp); | |
818 | err_gpio_wp: | |
148b8b39 RV |
819 | if (host->gpio_cd_irq >= 0) |
820 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
821 | if (host->gpio_cd != -ENOSYS) |
822 | gpio_free(host->gpio_cd); | |
823 | err_gpio_cd: | |
1da177e4 LT |
824 | iounmap(host->base); |
825 | clk_disable: | |
826 | clk_disable(host->clk); | |
1da177e4 LT |
827 | clk_free: |
828 | clk_put(host->clk); | |
829 | host_free: | |
830 | mmc_free_host(mmc); | |
831 | rel_regions: | |
832 | amba_release_regions(dev); | |
833 | out: | |
834 | return ret; | |
835 | } | |
836 | ||
6dc4a47a | 837 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
838 | { |
839 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
840 | ||
841 | amba_set_drvdata(dev, NULL); | |
842 | ||
843 | if (mmc) { | |
844 | struct mmci_host *host = mmc_priv(mmc); | |
845 | ||
1da177e4 LT |
846 | mmc_remove_host(mmc); |
847 | ||
848 | writel(0, host->base + MMCIMASK0); | |
849 | writel(0, host->base + MMCIMASK1); | |
850 | ||
851 | writel(0, host->base + MMCICOMMAND); | |
852 | writel(0, host->base + MMCIDATACTRL); | |
853 | ||
854 | free_irq(dev->irq[0], host); | |
855 | free_irq(dev->irq[1], host); | |
856 | ||
89001446 RK |
857 | if (host->gpio_wp != -ENOSYS) |
858 | gpio_free(host->gpio_wp); | |
148b8b39 RV |
859 | if (host->gpio_cd_irq >= 0) |
860 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
861 | if (host->gpio_cd != -ENOSYS) |
862 | gpio_free(host->gpio_cd); | |
863 | ||
1da177e4 LT |
864 | iounmap(host->base); |
865 | clk_disable(host->clk); | |
1da177e4 LT |
866 | clk_put(host->clk); |
867 | ||
34e84f39 LW |
868 | if (regulator_is_enabled(host->vcc)) |
869 | regulator_disable(host->vcc); | |
870 | regulator_put(host->vcc); | |
871 | ||
1da177e4 LT |
872 | mmc_free_host(mmc); |
873 | ||
874 | amba_release_regions(dev); | |
875 | } | |
876 | ||
877 | return 0; | |
878 | } | |
879 | ||
880 | #ifdef CONFIG_PM | |
e5378ca8 | 881 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
1da177e4 LT |
882 | { |
883 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
884 | int ret = 0; | |
885 | ||
886 | if (mmc) { | |
887 | struct mmci_host *host = mmc_priv(mmc); | |
888 | ||
1a13f8fa | 889 | ret = mmc_suspend_host(mmc); |
1da177e4 LT |
890 | if (ret == 0) |
891 | writel(0, host->base + MMCIMASK0); | |
892 | } | |
893 | ||
894 | return ret; | |
895 | } | |
896 | ||
897 | static int mmci_resume(struct amba_device *dev) | |
898 | { | |
899 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
900 | int ret = 0; | |
901 | ||
902 | if (mmc) { | |
903 | struct mmci_host *host = mmc_priv(mmc); | |
904 | ||
905 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
906 | ||
907 | ret = mmc_resume_host(mmc); | |
908 | } | |
909 | ||
910 | return ret; | |
911 | } | |
912 | #else | |
913 | #define mmci_suspend NULL | |
914 | #define mmci_resume NULL | |
915 | #endif | |
916 | ||
917 | static struct amba_id mmci_ids[] = { | |
918 | { | |
919 | .id = 0x00041180, | |
920 | .mask = 0x000fffff, | |
4956e109 | 921 | .data = &variant_arm, |
1da177e4 LT |
922 | }, |
923 | { | |
924 | .id = 0x00041181, | |
925 | .mask = 0x000fffff, | |
4956e109 | 926 | .data = &variant_arm, |
1da177e4 | 927 | }, |
cc30d60e LW |
928 | /* ST Micro variants */ |
929 | { | |
930 | .id = 0x00180180, | |
931 | .mask = 0x00ffffff, | |
4956e109 | 932 | .data = &variant_u300, |
cc30d60e LW |
933 | }, |
934 | { | |
935 | .id = 0x00280180, | |
936 | .mask = 0x00ffffff, | |
4956e109 RV |
937 | .data = &variant_u300, |
938 | }, | |
939 | { | |
940 | .id = 0x00480180, | |
941 | .mask = 0x00ffffff, | |
942 | .data = &variant_ux500, | |
cc30d60e | 943 | }, |
1da177e4 LT |
944 | { 0, 0 }, |
945 | }; | |
946 | ||
947 | static struct amba_driver mmci_driver = { | |
948 | .drv = { | |
949 | .name = DRIVER_NAME, | |
950 | }, | |
951 | .probe = mmci_probe, | |
6dc4a47a | 952 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
953 | .suspend = mmci_suspend, |
954 | .resume = mmci_resume, | |
955 | .id_table = mmci_ids, | |
956 | }; | |
957 | ||
958 | static int __init mmci_init(void) | |
959 | { | |
960 | return amba_driver_register(&mmci_driver); | |
961 | } | |
962 | ||
963 | static void __exit mmci_exit(void) | |
964 | { | |
965 | amba_driver_unregister(&mmci_driver); | |
966 | } | |
967 | ||
968 | module_init(mmci_init); | |
969 | module_exit(mmci_exit); | |
970 | module_param(fmax, uint, 0444); | |
971 | ||
972 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
973 | MODULE_LICENSE("GPL"); |