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Commit | Line | Data |
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1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
64de0289 | 5 | * Copyright (C) 2010 ST-Ericsson AB. |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/highmem.h> | |
019a5f56 | 20 | #include <linux/log2.h> |
1da177e4 | 21 | #include <linux/mmc/host.h> |
a62c80e5 | 22 | #include <linux/amba/bus.h> |
f8ce2547 | 23 | #include <linux/clk.h> |
bd6dee6f | 24 | #include <linux/scatterlist.h> |
89001446 | 25 | #include <linux/gpio.h> |
6ef297f8 | 26 | #include <linux/amba/mmci.h> |
34e84f39 | 27 | #include <linux/regulator/consumer.h> |
1da177e4 | 28 | |
7b09cdac | 29 | #include <asm/div64.h> |
1da177e4 | 30 | #include <asm/io.h> |
c6b8fdad | 31 | #include <asm/sizes.h> |
1da177e4 LT |
32 | |
33 | #include "mmci.h" | |
34 | ||
35 | #define DRIVER_NAME "mmci-pl18x" | |
36 | ||
1da177e4 LT |
37 | static unsigned int fmax = 515633; |
38 | ||
4956e109 RV |
39 | /** |
40 | * struct variant_data - MMCI variant-specific quirks | |
41 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 42 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 43 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
44 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
45 | * is asserted (likewise for RX) | |
46 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
47 | * is asserted (likewise for RX) | |
4956e109 RV |
48 | */ |
49 | struct variant_data { | |
50 | unsigned int clkreg; | |
4380c14f | 51 | unsigned int clkreg_enable; |
08458ef6 | 52 | unsigned int datalength_bits; |
8301bb68 RV |
53 | unsigned int fifosize; |
54 | unsigned int fifohalfsize; | |
4956e109 RV |
55 | }; |
56 | ||
57 | static struct variant_data variant_arm = { | |
8301bb68 RV |
58 | .fifosize = 16 * 4, |
59 | .fifohalfsize = 8 * 4, | |
08458ef6 | 60 | .datalength_bits = 16, |
4956e109 RV |
61 | }; |
62 | ||
63 | static struct variant_data variant_u300 = { | |
8301bb68 RV |
64 | .fifosize = 16 * 4, |
65 | .fifohalfsize = 8 * 4, | |
4380c14f | 66 | .clkreg_enable = 1 << 13, /* HWFCEN */ |
08458ef6 | 67 | .datalength_bits = 16, |
4956e109 RV |
68 | }; |
69 | ||
70 | static struct variant_data variant_ux500 = { | |
8301bb68 RV |
71 | .fifosize = 30 * 4, |
72 | .fifohalfsize = 8 * 4, | |
4956e109 | 73 | .clkreg = MCI_CLK_ENABLE, |
4380c14f | 74 | .clkreg_enable = 1 << 14, /* HWFCEN */ |
08458ef6 | 75 | .datalength_bits = 24, |
4956e109 | 76 | }; |
a6a6464a LW |
77 | /* |
78 | * This must be called with host->lock held | |
79 | */ | |
80 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
81 | { | |
4956e109 RV |
82 | struct variant_data *variant = host->variant; |
83 | u32 clk = variant->clkreg; | |
a6a6464a LW |
84 | |
85 | if (desired) { | |
86 | if (desired >= host->mclk) { | |
87 | clk = MCI_CLK_BYPASS; | |
88 | host->cclk = host->mclk; | |
89 | } else { | |
90 | clk = host->mclk / (2 * desired) - 1; | |
91 | if (clk >= 256) | |
92 | clk = 255; | |
93 | host->cclk = host->mclk / (2 * (clk + 1)); | |
94 | } | |
4380c14f RV |
95 | |
96 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
97 | clk |= MCI_CLK_ENABLE; |
98 | /* This hasn't proven to be worthwhile */ | |
99 | /* clk |= MCI_CLK_PWRSAVE; */ | |
100 | } | |
101 | ||
9e6c82cd | 102 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
103 | clk |= MCI_4BIT_BUS; |
104 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
105 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 106 | |
a6a6464a LW |
107 | writel(clk, host->base + MMCICLOCK); |
108 | } | |
109 | ||
1da177e4 LT |
110 | static void |
111 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
112 | { | |
113 | writel(0, host->base + MMCICOMMAND); | |
114 | ||
e47c222b RK |
115 | BUG_ON(host->data); |
116 | ||
1da177e4 LT |
117 | host->mrq = NULL; |
118 | host->cmd = NULL; | |
119 | ||
120 | if (mrq->data) | |
121 | mrq->data->bytes_xfered = host->data_xfered; | |
122 | ||
123 | /* | |
124 | * Need to drop the host lock here; mmc_request_done may call | |
125 | * back into the driver... | |
126 | */ | |
127 | spin_unlock(&host->lock); | |
128 | mmc_request_done(host->mmc, mrq); | |
129 | spin_lock(&host->lock); | |
130 | } | |
131 | ||
2686b4b4 LW |
132 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
133 | { | |
134 | void __iomem *base = host->base; | |
135 | ||
136 | if (host->singleirq) { | |
137 | unsigned int mask0 = readl(base + MMCIMASK0); | |
138 | ||
139 | mask0 &= ~MCI_IRQ1MASK; | |
140 | mask0 |= mask; | |
141 | ||
142 | writel(mask0, base + MMCIMASK0); | |
143 | } | |
144 | ||
145 | writel(mask, base + MMCIMASK1); | |
146 | } | |
147 | ||
1da177e4 LT |
148 | static void mmci_stop_data(struct mmci_host *host) |
149 | { | |
150 | writel(0, host->base + MMCIDATACTRL); | |
2686b4b4 | 151 | mmci_set_mask1(host, 0); |
1da177e4 LT |
152 | host->data = NULL; |
153 | } | |
154 | ||
4ce1d6cb RV |
155 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
156 | { | |
157 | unsigned int flags = SG_MITER_ATOMIC; | |
158 | ||
159 | if (data->flags & MMC_DATA_READ) | |
160 | flags |= SG_MITER_TO_SG; | |
161 | else | |
162 | flags |= SG_MITER_FROM_SG; | |
163 | ||
164 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
165 | } | |
166 | ||
1da177e4 LT |
167 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
168 | { | |
8301bb68 | 169 | struct variant_data *variant = host->variant; |
1da177e4 | 170 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 171 | unsigned long long clks; |
1da177e4 | 172 | void __iomem *base; |
3bc87f24 | 173 | int blksz_bits; |
1da177e4 | 174 | |
64de0289 LW |
175 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
176 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
177 | |
178 | host->data = data; | |
528320db | 179 | host->size = data->blksz * data->blocks; |
1da177e4 LT |
180 | host->data_xfered = 0; |
181 | ||
182 | mmci_init_sg(host, data); | |
183 | ||
7b09cdac RK |
184 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
185 | do_div(clks, 1000000000UL); | |
186 | ||
187 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
188 | |
189 | base = host->base; | |
190 | writel(timeout, base + MMCIDATATIMER); | |
191 | writel(host->size, base + MMCIDATALENGTH); | |
192 | ||
3bc87f24 RK |
193 | blksz_bits = ffs(data->blksz) - 1; |
194 | BUG_ON(1 << blksz_bits != data->blksz); | |
195 | ||
196 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
1da177e4 LT |
197 | if (data->flags & MMC_DATA_READ) { |
198 | datactrl |= MCI_DPSM_DIRECTION; | |
199 | irqmask = MCI_RXFIFOHALFFULLMASK; | |
0425a142 RK |
200 | |
201 | /* | |
202 | * If we have less than a FIFOSIZE of bytes to transfer, | |
203 | * trigger a PIO interrupt as soon as any data is available. | |
204 | */ | |
8301bb68 | 205 | if (host->size < variant->fifosize) |
0425a142 | 206 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
207 | } else { |
208 | /* | |
209 | * We don't actually need to include "FIFO empty" here | |
210 | * since its implicit in "FIFO half empty". | |
211 | */ | |
212 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
213 | } | |
214 | ||
215 | writel(datactrl, base + MMCIDATACTRL); | |
216 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
2686b4b4 | 217 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
218 | } |
219 | ||
220 | static void | |
221 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
222 | { | |
223 | void __iomem *base = host->base; | |
224 | ||
64de0289 | 225 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
226 | cmd->opcode, cmd->arg, cmd->flags); |
227 | ||
228 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
229 | writel(0, base + MMCICOMMAND); | |
230 | udelay(1); | |
231 | } | |
232 | ||
233 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
234 | if (cmd->flags & MMC_RSP_PRESENT) { |
235 | if (cmd->flags & MMC_RSP_136) | |
236 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 237 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
238 | } |
239 | if (/*interrupt*/0) | |
240 | c |= MCI_CPSM_INTERRUPT; | |
241 | ||
242 | host->cmd = cmd; | |
243 | ||
244 | writel(cmd->arg, base + MMCIARGUMENT); | |
245 | writel(c, base + MMCICOMMAND); | |
246 | } | |
247 | ||
248 | static void | |
249 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
250 | unsigned int status) | |
251 | { | |
252 | if (status & MCI_DATABLOCKEND) { | |
3bc87f24 | 253 | host->data_xfered += data->blksz; |
f28e8a4d LW |
254 | #ifdef CONFIG_ARCH_U300 |
255 | /* | |
256 | * On the U300 some signal or other is | |
257 | * badly routed so that a data write does | |
258 | * not properly terminate with a MCI_DATAEND | |
259 | * status flag. This quirk will make writes | |
260 | * work again. | |
261 | */ | |
262 | if (data->flags & MMC_DATA_WRITE) | |
263 | status |= MCI_DATAEND; | |
264 | #endif | |
1da177e4 LT |
265 | } |
266 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
64de0289 | 267 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); |
1da177e4 | 268 | if (status & MCI_DATACRCFAIL) |
17b0429d | 269 | data->error = -EILSEQ; |
1da177e4 | 270 | else if (status & MCI_DATATIMEOUT) |
17b0429d | 271 | data->error = -ETIMEDOUT; |
1da177e4 | 272 | else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) |
17b0429d | 273 | data->error = -EIO; |
1da177e4 | 274 | status |= MCI_DATAEND; |
e9c091b4 RK |
275 | |
276 | /* | |
277 | * We hit an error condition. Ensure that any data | |
278 | * partially written to a page is properly coherent. | |
279 | */ | |
4ce1d6cb RV |
280 | if (data->flags & MMC_DATA_READ) { |
281 | struct sg_mapping_iter *sg_miter = &host->sg_miter; | |
282 | unsigned long flags; | |
283 | ||
284 | local_irq_save(flags); | |
285 | if (sg_miter_next(sg_miter)) { | |
286 | flush_dcache_page(sg_miter->page); | |
287 | sg_miter_stop(sg_miter); | |
288 | } | |
289 | local_irq_restore(flags); | |
290 | } | |
1da177e4 LT |
291 | } |
292 | if (status & MCI_DATAEND) { | |
293 | mmci_stop_data(host); | |
294 | ||
295 | if (!data->stop) { | |
296 | mmci_request_end(host, data->mrq); | |
297 | } else { | |
298 | mmci_start_command(host, data->stop, 0); | |
299 | } | |
300 | } | |
301 | } | |
302 | ||
303 | static void | |
304 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
305 | unsigned int status) | |
306 | { | |
307 | void __iomem *base = host->base; | |
308 | ||
309 | host->cmd = NULL; | |
310 | ||
311 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
312 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
313 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
314 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
315 | ||
316 | if (status & MCI_CMDTIMEOUT) { | |
17b0429d | 317 | cmd->error = -ETIMEDOUT; |
1da177e4 | 318 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 319 | cmd->error = -EILSEQ; |
1da177e4 LT |
320 | } |
321 | ||
17b0429d | 322 | if (!cmd->data || cmd->error) { |
e47c222b RK |
323 | if (host->data) |
324 | mmci_stop_data(host); | |
1da177e4 LT |
325 | mmci_request_end(host, cmd->mrq); |
326 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
327 | mmci_start_data(host, cmd->data); | |
328 | } | |
329 | } | |
330 | ||
331 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
332 | { | |
333 | void __iomem *base = host->base; | |
334 | char *ptr = buffer; | |
335 | u32 status; | |
26eed9a5 | 336 | int host_remain = host->size; |
1da177e4 LT |
337 | |
338 | do { | |
26eed9a5 | 339 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
340 | |
341 | if (count > remain) | |
342 | count = remain; | |
343 | ||
344 | if (count <= 0) | |
345 | break; | |
346 | ||
347 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
348 | ||
349 | ptr += count; | |
350 | remain -= count; | |
26eed9a5 | 351 | host_remain -= count; |
1da177e4 LT |
352 | |
353 | if (remain == 0) | |
354 | break; | |
355 | ||
356 | status = readl(base + MMCISTATUS); | |
357 | } while (status & MCI_RXDATAAVLBL); | |
358 | ||
359 | return ptr - buffer; | |
360 | } | |
361 | ||
362 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
363 | { | |
8301bb68 | 364 | struct variant_data *variant = host->variant; |
1da177e4 LT |
365 | void __iomem *base = host->base; |
366 | char *ptr = buffer; | |
367 | ||
368 | do { | |
369 | unsigned int count, maxcnt; | |
370 | ||
8301bb68 RV |
371 | maxcnt = status & MCI_TXFIFOEMPTY ? |
372 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
373 | count = min(remain, maxcnt); |
374 | ||
375 | writesl(base + MMCIFIFO, ptr, count >> 2); | |
376 | ||
377 | ptr += count; | |
378 | remain -= count; | |
379 | ||
380 | if (remain == 0) | |
381 | break; | |
382 | ||
383 | status = readl(base + MMCISTATUS); | |
384 | } while (status & MCI_TXFIFOHALFEMPTY); | |
385 | ||
386 | return ptr - buffer; | |
387 | } | |
388 | ||
389 | /* | |
390 | * PIO data transfer IRQ handler. | |
391 | */ | |
7d12e780 | 392 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
393 | { |
394 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 395 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 396 | struct variant_data *variant = host->variant; |
1da177e4 | 397 | void __iomem *base = host->base; |
4ce1d6cb | 398 | unsigned long flags; |
1da177e4 LT |
399 | u32 status; |
400 | ||
401 | status = readl(base + MMCISTATUS); | |
402 | ||
64de0289 | 403 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 404 | |
4ce1d6cb RV |
405 | local_irq_save(flags); |
406 | ||
1da177e4 | 407 | do { |
1da177e4 LT |
408 | unsigned int remain, len; |
409 | char *buffer; | |
410 | ||
411 | /* | |
412 | * For write, we only need to test the half-empty flag | |
413 | * here - if the FIFO is completely empty, then by | |
414 | * definition it is more than half empty. | |
415 | * | |
416 | * For read, check for data available. | |
417 | */ | |
418 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
419 | break; | |
420 | ||
4ce1d6cb RV |
421 | if (!sg_miter_next(sg_miter)) |
422 | break; | |
423 | ||
424 | buffer = sg_miter->addr; | |
425 | remain = sg_miter->length; | |
1da177e4 LT |
426 | |
427 | len = 0; | |
428 | if (status & MCI_RXACTIVE) | |
429 | len = mmci_pio_read(host, buffer, remain); | |
430 | if (status & MCI_TXACTIVE) | |
431 | len = mmci_pio_write(host, buffer, remain, status); | |
432 | ||
4ce1d6cb | 433 | sg_miter->consumed = len; |
1da177e4 | 434 | |
1da177e4 LT |
435 | host->size -= len; |
436 | remain -= len; | |
437 | ||
438 | if (remain) | |
439 | break; | |
440 | ||
e9c091b4 | 441 | if (status & MCI_RXACTIVE) |
4ce1d6cb | 442 | flush_dcache_page(sg_miter->page); |
1da177e4 LT |
443 | |
444 | status = readl(base + MMCISTATUS); | |
445 | } while (1); | |
446 | ||
4ce1d6cb RV |
447 | sg_miter_stop(sg_miter); |
448 | ||
449 | local_irq_restore(flags); | |
450 | ||
1da177e4 LT |
451 | /* |
452 | * If we're nearing the end of the read, switch to | |
453 | * "any data available" mode. | |
454 | */ | |
8301bb68 | 455 | if (status & MCI_RXACTIVE && host->size < variant->fifosize) |
2686b4b4 | 456 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
457 | |
458 | /* | |
459 | * If we run out of data, disable the data IRQs; this | |
460 | * prevents a race where the FIFO becomes empty before | |
461 | * the chip itself has disabled the data path, and | |
462 | * stops us racing with our data end IRQ. | |
463 | */ | |
464 | if (host->size == 0) { | |
2686b4b4 | 465 | mmci_set_mask1(host, 0); |
1da177e4 LT |
466 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
467 | } | |
468 | ||
469 | return IRQ_HANDLED; | |
470 | } | |
471 | ||
472 | /* | |
473 | * Handle completion of command and data transfers. | |
474 | */ | |
7d12e780 | 475 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
476 | { |
477 | struct mmci_host *host = dev_id; | |
478 | u32 status; | |
479 | int ret = 0; | |
480 | ||
481 | spin_lock(&host->lock); | |
482 | ||
483 | do { | |
484 | struct mmc_command *cmd; | |
485 | struct mmc_data *data; | |
486 | ||
487 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
488 | |
489 | if (host->singleirq) { | |
490 | if (status & readl(host->base + MMCIMASK1)) | |
491 | mmci_pio_irq(irq, dev_id); | |
492 | ||
493 | status &= ~MCI_IRQ1MASK; | |
494 | } | |
495 | ||
1da177e4 LT |
496 | status &= readl(host->base + MMCIMASK0); |
497 | writel(status, host->base + MMCICLEAR); | |
498 | ||
64de0289 | 499 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
500 | |
501 | data = host->data; | |
502 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | |
503 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) | |
504 | mmci_data_irq(host, data, status); | |
505 | ||
506 | cmd = host->cmd; | |
507 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
508 | mmci_cmd_irq(host, cmd, status); | |
509 | ||
510 | ret = 1; | |
511 | } while (status); | |
512 | ||
513 | spin_unlock(&host->lock); | |
514 | ||
515 | return IRQ_RETVAL(ret); | |
516 | } | |
517 | ||
518 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
519 | { | |
520 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 521 | unsigned long flags; |
1da177e4 LT |
522 | |
523 | WARN_ON(host->mrq != NULL); | |
524 | ||
019a5f56 | 525 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
526 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
527 | mrq->data->blksz); | |
255d01af PO |
528 | mrq->cmd->error = -EINVAL; |
529 | mmc_request_done(mmc, mrq); | |
530 | return; | |
531 | } | |
532 | ||
9e943021 | 533 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
534 | |
535 | host->mrq = mrq; | |
536 | ||
537 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) | |
538 | mmci_start_data(host, mrq->data); | |
539 | ||
540 | mmci_start_command(host, mrq->cmd, 0); | |
541 | ||
9e943021 | 542 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
543 | } |
544 | ||
545 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
546 | { | |
547 | struct mmci_host *host = mmc_priv(mmc); | |
a6a6464a LW |
548 | u32 pwr = 0; |
549 | unsigned long flags; | |
99fc5131 | 550 | int ret; |
1da177e4 | 551 | |
1da177e4 LT |
552 | switch (ios->power_mode) { |
553 | case MMC_POWER_OFF: | |
99fc5131 LW |
554 | if (host->vcc) |
555 | ret = mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
1da177e4 LT |
556 | break; |
557 | case MMC_POWER_UP: | |
99fc5131 LW |
558 | if (host->vcc) { |
559 | ret = mmc_regulator_set_ocr(mmc, host->vcc, ios->vdd); | |
560 | if (ret) { | |
561 | dev_err(mmc_dev(mmc), "unable to set OCR\n"); | |
562 | /* | |
563 | * The .set_ios() function in the mmc_host_ops | |
564 | * struct return void, and failing to set the | |
565 | * power should be rare so we print an error | |
566 | * and return here. | |
567 | */ | |
568 | return; | |
569 | } | |
570 | } | |
bb8f563c RV |
571 | if (host->plat->vdd_handler) |
572 | pwr |= host->plat->vdd_handler(mmc_dev(mmc), ios->vdd, | |
573 | ios->power_mode); | |
cc30d60e | 574 | /* The ST version does not have this, fall through to POWER_ON */ |
f17a1f06 | 575 | if (host->hw_designer != AMBA_VENDOR_ST) { |
cc30d60e LW |
576 | pwr |= MCI_PWR_UP; |
577 | break; | |
578 | } | |
1da177e4 LT |
579 | case MMC_POWER_ON: |
580 | pwr |= MCI_PWR_ON; | |
581 | break; | |
582 | } | |
583 | ||
cc30d60e | 584 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 585 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
586 | pwr |= MCI_ROD; |
587 | else { | |
588 | /* | |
589 | * The ST Micro variant use the ROD bit for something | |
590 | * else and only has OD (Open Drain). | |
591 | */ | |
592 | pwr |= MCI_OD; | |
593 | } | |
594 | } | |
1da177e4 | 595 | |
a6a6464a LW |
596 | spin_lock_irqsave(&host->lock, flags); |
597 | ||
598 | mmci_set_clkreg(host, ios->clock); | |
1da177e4 LT |
599 | |
600 | if (host->pwr != pwr) { | |
601 | host->pwr = pwr; | |
602 | writel(pwr, host->base + MMCIPOWER); | |
603 | } | |
a6a6464a LW |
604 | |
605 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
606 | } |
607 | ||
89001446 RK |
608 | static int mmci_get_ro(struct mmc_host *mmc) |
609 | { | |
610 | struct mmci_host *host = mmc_priv(mmc); | |
611 | ||
612 | if (host->gpio_wp == -ENOSYS) | |
613 | return -ENOSYS; | |
614 | ||
18a06301 | 615 | return gpio_get_value_cansleep(host->gpio_wp); |
89001446 RK |
616 | } |
617 | ||
618 | static int mmci_get_cd(struct mmc_host *mmc) | |
619 | { | |
620 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 621 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
622 | unsigned int status; |
623 | ||
4b8caec0 RV |
624 | if (host->gpio_cd == -ENOSYS) { |
625 | if (!plat->status) | |
626 | return 1; /* Assume always present */ | |
627 | ||
29719445 | 628 | status = plat->status(mmc_dev(host->mmc)); |
4b8caec0 | 629 | } else |
18a06301 LW |
630 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
631 | ^ plat->cd_invert; | |
89001446 | 632 | |
74bc8093 RK |
633 | /* |
634 | * Use positive logic throughout - status is zero for no card, | |
635 | * non-zero for card inserted. | |
636 | */ | |
637 | return status; | |
89001446 RK |
638 | } |
639 | ||
148b8b39 RV |
640 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
641 | { | |
642 | struct mmci_host *host = dev_id; | |
643 | ||
644 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
645 | ||
646 | return IRQ_HANDLED; | |
647 | } | |
648 | ||
ab7aefd0 | 649 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 LT |
650 | .request = mmci_request, |
651 | .set_ios = mmci_set_ios, | |
89001446 RK |
652 | .get_ro = mmci_get_ro, |
653 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
654 | }; |
655 | ||
03fbdb15 | 656 | static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) |
1da177e4 | 657 | { |
6ef297f8 | 658 | struct mmci_platform_data *plat = dev->dev.platform_data; |
4956e109 | 659 | struct variant_data *variant = id->data; |
1da177e4 LT |
660 | struct mmci_host *host; |
661 | struct mmc_host *mmc; | |
2686b4b4 | 662 | unsigned int mask; |
1da177e4 LT |
663 | int ret; |
664 | ||
665 | /* must have platform data */ | |
666 | if (!plat) { | |
667 | ret = -EINVAL; | |
668 | goto out; | |
669 | } | |
670 | ||
671 | ret = amba_request_regions(dev, DRIVER_NAME); | |
672 | if (ret) | |
673 | goto out; | |
674 | ||
675 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
676 | if (!mmc) { | |
677 | ret = -ENOMEM; | |
678 | goto rel_regions; | |
679 | } | |
680 | ||
681 | host = mmc_priv(mmc); | |
4ea580f1 | 682 | host->mmc = mmc; |
012b7d33 | 683 | |
89001446 RK |
684 | host->gpio_wp = -ENOSYS; |
685 | host->gpio_cd = -ENOSYS; | |
148b8b39 | 686 | host->gpio_cd_irq = -1; |
89001446 | 687 | |
012b7d33 RK |
688 | host->hw_designer = amba_manf(dev); |
689 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
690 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
691 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 692 | |
ee569c43 | 693 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
694 | if (IS_ERR(host->clk)) { |
695 | ret = PTR_ERR(host->clk); | |
696 | host->clk = NULL; | |
697 | goto host_free; | |
698 | } | |
699 | ||
1da177e4 LT |
700 | ret = clk_enable(host->clk); |
701 | if (ret) | |
a8d3584a | 702 | goto clk_free; |
1da177e4 LT |
703 | |
704 | host->plat = plat; | |
4956e109 | 705 | host->variant = variant; |
1da177e4 | 706 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
707 | /* |
708 | * According to the spec, mclk is max 100 MHz, | |
709 | * so we try to adjust the clock down to this, | |
710 | * (if possible). | |
711 | */ | |
712 | if (host->mclk > 100000000) { | |
713 | ret = clk_set_rate(host->clk, 100000000); | |
714 | if (ret < 0) | |
715 | goto clk_disable; | |
716 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
717 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
718 | host->mclk); | |
c8df9a53 | 719 | } |
dc890c2d | 720 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
721 | if (!host->base) { |
722 | ret = -ENOMEM; | |
723 | goto clk_disable; | |
724 | } | |
725 | ||
726 | mmc->ops = &mmci_ops; | |
727 | mmc->f_min = (host->mclk + 511) / 512; | |
808d97cc LW |
728 | /* |
729 | * If the platform data supplies a maximum operating | |
730 | * frequency, this takes precedence. Else, we fall back | |
731 | * to using the module parameter, which has a (low) | |
732 | * default value in case it is not specified. Either | |
733 | * value must not exceed the clock rate into the block, | |
734 | * of course. | |
735 | */ | |
736 | if (plat->f_max) | |
737 | mmc->f_max = min(host->mclk, plat->f_max); | |
738 | else | |
739 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
740 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
741 | ||
34e84f39 LW |
742 | #ifdef CONFIG_REGULATOR |
743 | /* If we're using the regulator framework, try to fetch a regulator */ | |
744 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
745 | if (IS_ERR(host->vcc)) | |
746 | host->vcc = NULL; | |
747 | else { | |
748 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
749 | ||
750 | if (mask < 0) | |
751 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
752 | mask); | |
753 | else { | |
754 | host->mmc->ocr_avail = (u32) mask; | |
755 | if (plat->ocr_mask) | |
756 | dev_warn(&dev->dev, | |
757 | "Provided ocr_mask/setpower will not be used " | |
758 | "(using regulator instead)\n"); | |
759 | } | |
760 | } | |
761 | #endif | |
762 | /* Fall back to platform data if no regulator is found */ | |
763 | if (host->vcc == NULL) | |
764 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 765 | mmc->caps = plat->capabilities; |
1da177e4 LT |
766 | |
767 | /* | |
768 | * We can do SGIO | |
769 | */ | |
a36274e0 | 770 | mmc->max_segs = NR_SG; |
1da177e4 LT |
771 | |
772 | /* | |
08458ef6 RV |
773 | * Since only a certain number of bits are valid in the data length |
774 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
775 | * single request. | |
1da177e4 | 776 | */ |
08458ef6 | 777 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
778 | |
779 | /* | |
780 | * Set the maximum segment size. Since we aren't doing DMA | |
781 | * (yet) we are only limited by the data length register. | |
782 | */ | |
55db890a | 783 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 784 | |
fe4a3c7a PO |
785 | /* |
786 | * Block size can be up to 2048 bytes, but must be a power of two. | |
787 | */ | |
788 | mmc->max_blk_size = 2048; | |
789 | ||
55db890a PO |
790 | /* |
791 | * No limit on the number of blocks transferred. | |
792 | */ | |
793 | mmc->max_blk_count = mmc->max_req_size; | |
794 | ||
1da177e4 LT |
795 | spin_lock_init(&host->lock); |
796 | ||
797 | writel(0, host->base + MMCIMASK0); | |
798 | writel(0, host->base + MMCIMASK1); | |
799 | writel(0xfff, host->base + MMCICLEAR); | |
800 | ||
89001446 RK |
801 | if (gpio_is_valid(plat->gpio_cd)) { |
802 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
803 | if (ret == 0) | |
804 | ret = gpio_direction_input(plat->gpio_cd); | |
805 | if (ret == 0) | |
806 | host->gpio_cd = plat->gpio_cd; | |
807 | else if (ret != -ENOSYS) | |
808 | goto err_gpio_cd; | |
148b8b39 RV |
809 | |
810 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), | |
811 | mmci_cd_irq, 0, | |
812 | DRIVER_NAME " (cd)", host); | |
813 | if (ret >= 0) | |
814 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); | |
89001446 RK |
815 | } |
816 | if (gpio_is_valid(plat->gpio_wp)) { | |
817 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
818 | if (ret == 0) | |
819 | ret = gpio_direction_input(plat->gpio_wp); | |
820 | if (ret == 0) | |
821 | host->gpio_wp = plat->gpio_wp; | |
822 | else if (ret != -ENOSYS) | |
823 | goto err_gpio_wp; | |
824 | } | |
825 | ||
4b8caec0 RV |
826 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
827 | && host->gpio_cd_irq < 0) | |
148b8b39 RV |
828 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
829 | ||
dace1453 | 830 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
831 | if (ret) |
832 | goto unmap; | |
833 | ||
2686b4b4 LW |
834 | if (dev->irq[1] == NO_IRQ) |
835 | host->singleirq = true; | |
836 | else { | |
837 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, | |
838 | DRIVER_NAME " (pio)", host); | |
839 | if (ret) | |
840 | goto irq0_free; | |
841 | } | |
1da177e4 | 842 | |
2686b4b4 LW |
843 | mask = MCI_IRQENABLE; |
844 | writel(mask, host->base + MMCIMASK0); | |
1da177e4 LT |
845 | |
846 | amba_set_drvdata(dev, mmc); | |
847 | ||
848 | mmc_add_host(mmc); | |
849 | ||
64de0289 | 850 | dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", |
d366b643 | 851 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), |
e29419ff | 852 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); |
1da177e4 | 853 | |
1da177e4 LT |
854 | return 0; |
855 | ||
856 | irq0_free: | |
857 | free_irq(dev->irq[0], host); | |
858 | unmap: | |
89001446 RK |
859 | if (host->gpio_wp != -ENOSYS) |
860 | gpio_free(host->gpio_wp); | |
861 | err_gpio_wp: | |
148b8b39 RV |
862 | if (host->gpio_cd_irq >= 0) |
863 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
864 | if (host->gpio_cd != -ENOSYS) |
865 | gpio_free(host->gpio_cd); | |
866 | err_gpio_cd: | |
1da177e4 LT |
867 | iounmap(host->base); |
868 | clk_disable: | |
869 | clk_disable(host->clk); | |
1da177e4 LT |
870 | clk_free: |
871 | clk_put(host->clk); | |
872 | host_free: | |
873 | mmc_free_host(mmc); | |
874 | rel_regions: | |
875 | amba_release_regions(dev); | |
876 | out: | |
877 | return ret; | |
878 | } | |
879 | ||
6dc4a47a | 880 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
881 | { |
882 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
883 | ||
884 | amba_set_drvdata(dev, NULL); | |
885 | ||
886 | if (mmc) { | |
887 | struct mmci_host *host = mmc_priv(mmc); | |
888 | ||
1da177e4 LT |
889 | mmc_remove_host(mmc); |
890 | ||
891 | writel(0, host->base + MMCIMASK0); | |
892 | writel(0, host->base + MMCIMASK1); | |
893 | ||
894 | writel(0, host->base + MMCICOMMAND); | |
895 | writel(0, host->base + MMCIDATACTRL); | |
896 | ||
897 | free_irq(dev->irq[0], host); | |
2686b4b4 LW |
898 | if (!host->singleirq) |
899 | free_irq(dev->irq[1], host); | |
1da177e4 | 900 | |
89001446 RK |
901 | if (host->gpio_wp != -ENOSYS) |
902 | gpio_free(host->gpio_wp); | |
148b8b39 RV |
903 | if (host->gpio_cd_irq >= 0) |
904 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
905 | if (host->gpio_cd != -ENOSYS) |
906 | gpio_free(host->gpio_cd); | |
907 | ||
1da177e4 LT |
908 | iounmap(host->base); |
909 | clk_disable(host->clk); | |
1da177e4 LT |
910 | clk_put(host->clk); |
911 | ||
99fc5131 LW |
912 | if (host->vcc) |
913 | mmc_regulator_set_ocr(mmc, host->vcc, 0); | |
34e84f39 LW |
914 | regulator_put(host->vcc); |
915 | ||
1da177e4 LT |
916 | mmc_free_host(mmc); |
917 | ||
918 | amba_release_regions(dev); | |
919 | } | |
920 | ||
921 | return 0; | |
922 | } | |
923 | ||
924 | #ifdef CONFIG_PM | |
e5378ca8 | 925 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
1da177e4 LT |
926 | { |
927 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
928 | int ret = 0; | |
929 | ||
930 | if (mmc) { | |
931 | struct mmci_host *host = mmc_priv(mmc); | |
932 | ||
1a13f8fa | 933 | ret = mmc_suspend_host(mmc); |
1da177e4 LT |
934 | if (ret == 0) |
935 | writel(0, host->base + MMCIMASK0); | |
936 | } | |
937 | ||
938 | return ret; | |
939 | } | |
940 | ||
941 | static int mmci_resume(struct amba_device *dev) | |
942 | { | |
943 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
944 | int ret = 0; | |
945 | ||
946 | if (mmc) { | |
947 | struct mmci_host *host = mmc_priv(mmc); | |
948 | ||
949 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
950 | ||
951 | ret = mmc_resume_host(mmc); | |
952 | } | |
953 | ||
954 | return ret; | |
955 | } | |
956 | #else | |
957 | #define mmci_suspend NULL | |
958 | #define mmci_resume NULL | |
959 | #endif | |
960 | ||
961 | static struct amba_id mmci_ids[] = { | |
962 | { | |
963 | .id = 0x00041180, | |
964 | .mask = 0x000fffff, | |
4956e109 | 965 | .data = &variant_arm, |
1da177e4 LT |
966 | }, |
967 | { | |
968 | .id = 0x00041181, | |
969 | .mask = 0x000fffff, | |
4956e109 | 970 | .data = &variant_arm, |
1da177e4 | 971 | }, |
cc30d60e LW |
972 | /* ST Micro variants */ |
973 | { | |
974 | .id = 0x00180180, | |
975 | .mask = 0x00ffffff, | |
4956e109 | 976 | .data = &variant_u300, |
cc30d60e LW |
977 | }, |
978 | { | |
979 | .id = 0x00280180, | |
980 | .mask = 0x00ffffff, | |
4956e109 RV |
981 | .data = &variant_u300, |
982 | }, | |
983 | { | |
984 | .id = 0x00480180, | |
985 | .mask = 0x00ffffff, | |
986 | .data = &variant_ux500, | |
cc30d60e | 987 | }, |
1da177e4 LT |
988 | { 0, 0 }, |
989 | }; | |
990 | ||
991 | static struct amba_driver mmci_driver = { | |
992 | .drv = { | |
993 | .name = DRIVER_NAME, | |
994 | }, | |
995 | .probe = mmci_probe, | |
6dc4a47a | 996 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
997 | .suspend = mmci_suspend, |
998 | .resume = mmci_resume, | |
999 | .id_table = mmci_ids, | |
1000 | }; | |
1001 | ||
1002 | static int __init mmci_init(void) | |
1003 | { | |
1004 | return amba_driver_register(&mmci_driver); | |
1005 | } | |
1006 | ||
1007 | static void __exit mmci_exit(void) | |
1008 | { | |
1009 | amba_driver_unregister(&mmci_driver); | |
1010 | } | |
1011 | ||
1012 | module_init(mmci_init); | |
1013 | module_exit(mmci_exit); | |
1014 | module_param(fmax, uint, 0444); | |
1015 | ||
1016 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1017 | MODULE_LICENSE("GPL"); |