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Commit | Line | Data |
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1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 5 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
613b152c | 17 | #include <linux/kernel.h> |
000bc9d5 | 18 | #include <linux/slab.h> |
1da177e4 LT |
19 | #include <linux/delay.h> |
20 | #include <linux/err.h> | |
21 | #include <linux/highmem.h> | |
019a5f56 | 22 | #include <linux/log2.h> |
70be208f | 23 | #include <linux/mmc/pm.h> |
1da177e4 | 24 | #include <linux/mmc/host.h> |
34177802 | 25 | #include <linux/mmc/card.h> |
a62c80e5 | 26 | #include <linux/amba/bus.h> |
f8ce2547 | 27 | #include <linux/clk.h> |
bd6dee6f | 28 | #include <linux/scatterlist.h> |
89001446 | 29 | #include <linux/gpio.h> |
9a597016 | 30 | #include <linux/of_gpio.h> |
34e84f39 | 31 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
32 | #include <linux/dmaengine.h> |
33 | #include <linux/dma-mapping.h> | |
34 | #include <linux/amba/mmci.h> | |
1c3be369 | 35 | #include <linux/pm_runtime.h> |
258aea76 | 36 | #include <linux/types.h> |
a9a83785 | 37 | #include <linux/pinctrl/consumer.h> |
1da177e4 | 38 | |
7b09cdac | 39 | #include <asm/div64.h> |
1da177e4 | 40 | #include <asm/io.h> |
c6b8fdad | 41 | #include <asm/sizes.h> |
1da177e4 LT |
42 | |
43 | #include "mmci.h" | |
44 | ||
45 | #define DRIVER_NAME "mmci-pl18x" | |
46 | ||
1da177e4 LT |
47 | static unsigned int fmax = 515633; |
48 | ||
4956e109 RV |
49 | /** |
50 | * struct variant_data - MMCI variant-specific quirks | |
51 | * @clkreg: default value for MCICLOCK register | |
4380c14f | 52 | * @clkreg_enable: enable value for MMCICLOCK register |
08458ef6 | 53 | * @datalength_bits: number of bits in the MMCIDATALENGTH register |
8301bb68 RV |
54 | * @fifosize: number of bytes that can be written when MMCI_TXFIFOEMPTY |
55 | * is asserted (likewise for RX) | |
56 | * @fifohalfsize: number of bytes that can be written when MCI_TXFIFOHALFEMPTY | |
57 | * is asserted (likewise for RX) | |
34177802 | 58 | * @sdio: variant supports SDIO |
b70a67f9 | 59 | * @st_clkdiv: true if using a ST-specific clock divider algorithm |
1784b157 | 60 | * @blksz_datactrl16: true if Block size is at b16..b30 position in datactrl register |
7d72a1d4 | 61 | * @pwrreg_powerup: power up value for MMCIPOWER register |
4d1a3a0d | 62 | * @signal_direction: input/out direction of bus signals can be indicated |
4956e109 RV |
63 | */ |
64 | struct variant_data { | |
65 | unsigned int clkreg; | |
4380c14f | 66 | unsigned int clkreg_enable; |
08458ef6 | 67 | unsigned int datalength_bits; |
8301bb68 RV |
68 | unsigned int fifosize; |
69 | unsigned int fifohalfsize; | |
34177802 | 70 | bool sdio; |
b70a67f9 | 71 | bool st_clkdiv; |
1784b157 | 72 | bool blksz_datactrl16; |
7d72a1d4 | 73 | u32 pwrreg_powerup; |
4d1a3a0d | 74 | bool signal_direction; |
4956e109 RV |
75 | }; |
76 | ||
77 | static struct variant_data variant_arm = { | |
8301bb68 RV |
78 | .fifosize = 16 * 4, |
79 | .fifohalfsize = 8 * 4, | |
08458ef6 | 80 | .datalength_bits = 16, |
7d72a1d4 | 81 | .pwrreg_powerup = MCI_PWR_UP, |
4956e109 RV |
82 | }; |
83 | ||
768fbc18 PM |
84 | static struct variant_data variant_arm_extended_fifo = { |
85 | .fifosize = 128 * 4, | |
86 | .fifohalfsize = 64 * 4, | |
87 | .datalength_bits = 16, | |
7d72a1d4 | 88 | .pwrreg_powerup = MCI_PWR_UP, |
768fbc18 PM |
89 | }; |
90 | ||
4956e109 | 91 | static struct variant_data variant_u300 = { |
8301bb68 RV |
92 | .fifosize = 16 * 4, |
93 | .fifohalfsize = 8 * 4, | |
49ac215e | 94 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
08458ef6 | 95 | .datalength_bits = 16, |
34177802 | 96 | .sdio = true, |
7d72a1d4 | 97 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 98 | .signal_direction = true, |
4956e109 RV |
99 | }; |
100 | ||
34fd4213 LW |
101 | static struct variant_data variant_nomadik = { |
102 | .fifosize = 16 * 4, | |
103 | .fifohalfsize = 8 * 4, | |
104 | .clkreg = MCI_CLK_ENABLE, | |
105 | .datalength_bits = 24, | |
106 | .sdio = true, | |
107 | .st_clkdiv = true, | |
108 | .pwrreg_powerup = MCI_PWR_ON, | |
109 | .signal_direction = true, | |
110 | }; | |
111 | ||
4956e109 | 112 | static struct variant_data variant_ux500 = { |
8301bb68 RV |
113 | .fifosize = 30 * 4, |
114 | .fifohalfsize = 8 * 4, | |
4956e109 | 115 | .clkreg = MCI_CLK_ENABLE, |
49ac215e | 116 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
08458ef6 | 117 | .datalength_bits = 24, |
34177802 | 118 | .sdio = true, |
b70a67f9 | 119 | .st_clkdiv = true, |
7d72a1d4 | 120 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 121 | .signal_direction = true, |
4956e109 | 122 | }; |
b70a67f9 | 123 | |
1784b157 PL |
124 | static struct variant_data variant_ux500v2 = { |
125 | .fifosize = 30 * 4, | |
126 | .fifohalfsize = 8 * 4, | |
127 | .clkreg = MCI_CLK_ENABLE, | |
128 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
129 | .datalength_bits = 24, | |
130 | .sdio = true, | |
131 | .st_clkdiv = true, | |
132 | .blksz_datactrl16 = true, | |
7d72a1d4 | 133 | .pwrreg_powerup = MCI_PWR_ON, |
4d1a3a0d | 134 | .signal_direction = true, |
1784b157 PL |
135 | }; |
136 | ||
7437cfa5 UH |
137 | /* |
138 | * This must be called with host->lock held | |
139 | */ | |
140 | static void mmci_write_clkreg(struct mmci_host *host, u32 clk) | |
141 | { | |
142 | if (host->clk_reg != clk) { | |
143 | host->clk_reg = clk; | |
144 | writel(clk, host->base + MMCICLOCK); | |
145 | } | |
146 | } | |
147 | ||
148 | /* | |
149 | * This must be called with host->lock held | |
150 | */ | |
151 | static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) | |
152 | { | |
153 | if (host->pwr_reg != pwr) { | |
154 | host->pwr_reg = pwr; | |
155 | writel(pwr, host->base + MMCIPOWER); | |
156 | } | |
157 | } | |
158 | ||
a6a6464a LW |
159 | /* |
160 | * This must be called with host->lock held | |
161 | */ | |
162 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
163 | { | |
4956e109 RV |
164 | struct variant_data *variant = host->variant; |
165 | u32 clk = variant->clkreg; | |
a6a6464a LW |
166 | |
167 | if (desired) { | |
168 | if (desired >= host->mclk) { | |
991a86e1 | 169 | clk = MCI_CLK_BYPASS; |
399bc486 LW |
170 | if (variant->st_clkdiv) |
171 | clk |= MCI_ST_UX500_NEG_EDGE; | |
a6a6464a | 172 | host->cclk = host->mclk; |
b70a67f9 LW |
173 | } else if (variant->st_clkdiv) { |
174 | /* | |
175 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
176 | * => clkdiv = (mclk / f) - 2 | |
177 | * Round the divider up so we don't exceed the max | |
178 | * frequency | |
179 | */ | |
180 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
181 | if (clk >= 256) | |
182 | clk = 255; | |
183 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 184 | } else { |
b70a67f9 LW |
185 | /* |
186 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
187 | * => clkdiv = mclk / (2 * f) - 1 | |
188 | */ | |
a6a6464a LW |
189 | clk = host->mclk / (2 * desired) - 1; |
190 | if (clk >= 256) | |
191 | clk = 255; | |
192 | host->cclk = host->mclk / (2 * (clk + 1)); | |
193 | } | |
4380c14f RV |
194 | |
195 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
196 | clk |= MCI_CLK_ENABLE; |
197 | /* This hasn't proven to be worthwhile */ | |
198 | /* clk |= MCI_CLK_PWRSAVE; */ | |
199 | } | |
200 | ||
9e6c82cd | 201 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
202 | clk |= MCI_4BIT_BUS; |
203 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
204 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 205 | |
6dbb6ee0 UH |
206 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) |
207 | clk |= MCI_ST_UX500_NEG_EDGE; | |
208 | ||
7437cfa5 | 209 | mmci_write_clkreg(host, clk); |
a6a6464a LW |
210 | } |
211 | ||
1da177e4 LT |
212 | static void |
213 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
214 | { | |
215 | writel(0, host->base + MMCICOMMAND); | |
216 | ||
e47c222b RK |
217 | BUG_ON(host->data); |
218 | ||
1da177e4 LT |
219 | host->mrq = NULL; |
220 | host->cmd = NULL; | |
221 | ||
1da177e4 | 222 | mmc_request_done(host->mmc, mrq); |
2cd976c4 UH |
223 | |
224 | pm_runtime_mark_last_busy(mmc_dev(host->mmc)); | |
225 | pm_runtime_put_autosuspend(mmc_dev(host->mmc)); | |
1da177e4 LT |
226 | } |
227 | ||
2686b4b4 LW |
228 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
229 | { | |
230 | void __iomem *base = host->base; | |
231 | ||
232 | if (host->singleirq) { | |
233 | unsigned int mask0 = readl(base + MMCIMASK0); | |
234 | ||
235 | mask0 &= ~MCI_IRQ1MASK; | |
236 | mask0 |= mask; | |
237 | ||
238 | writel(mask0, base + MMCIMASK0); | |
239 | } | |
240 | ||
241 | writel(mask, base + MMCIMASK1); | |
242 | } | |
243 | ||
1da177e4 LT |
244 | static void mmci_stop_data(struct mmci_host *host) |
245 | { | |
246 | writel(0, host->base + MMCIDATACTRL); | |
2686b4b4 | 247 | mmci_set_mask1(host, 0); |
1da177e4 LT |
248 | host->data = NULL; |
249 | } | |
250 | ||
4ce1d6cb RV |
251 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
252 | { | |
253 | unsigned int flags = SG_MITER_ATOMIC; | |
254 | ||
255 | if (data->flags & MMC_DATA_READ) | |
256 | flags |= SG_MITER_TO_SG; | |
257 | else | |
258 | flags |= SG_MITER_FROM_SG; | |
259 | ||
260 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
261 | } | |
262 | ||
c8ebae37 RK |
263 | /* |
264 | * All the DMA operation mode stuff goes inside this ifdef. | |
265 | * This assumes that you have a generic DMA device interface, | |
266 | * no custom DMA interfaces are supported. | |
267 | */ | |
268 | #ifdef CONFIG_DMA_ENGINE | |
c3be1efd | 269 | static void mmci_dma_setup(struct mmci_host *host) |
c8ebae37 RK |
270 | { |
271 | struct mmci_platform_data *plat = host->plat; | |
272 | const char *rxname, *txname; | |
273 | dma_cap_mask_t mask; | |
274 | ||
275 | if (!plat || !plat->dma_filter) { | |
276 | dev_info(mmc_dev(host->mmc), "no DMA platform data\n"); | |
277 | return; | |
278 | } | |
279 | ||
58c7ccbf PF |
280 | /* initialize pre request cookie */ |
281 | host->next_data.cookie = 1; | |
282 | ||
c8ebae37 RK |
283 | /* Try to acquire a generic DMA engine slave channel */ |
284 | dma_cap_zero(mask); | |
285 | dma_cap_set(DMA_SLAVE, mask); | |
286 | ||
287 | /* | |
288 | * If only an RX channel is specified, the driver will | |
289 | * attempt to use it bidirectionally, however if it is | |
290 | * is specified but cannot be located, DMA will be disabled. | |
291 | */ | |
292 | if (plat->dma_rx_param) { | |
293 | host->dma_rx_channel = dma_request_channel(mask, | |
294 | plat->dma_filter, | |
295 | plat->dma_rx_param); | |
296 | /* E.g if no DMA hardware is present */ | |
297 | if (!host->dma_rx_channel) | |
298 | dev_err(mmc_dev(host->mmc), "no RX DMA channel\n"); | |
299 | } | |
300 | ||
301 | if (plat->dma_tx_param) { | |
302 | host->dma_tx_channel = dma_request_channel(mask, | |
303 | plat->dma_filter, | |
304 | plat->dma_tx_param); | |
305 | if (!host->dma_tx_channel) | |
306 | dev_warn(mmc_dev(host->mmc), "no TX DMA channel\n"); | |
307 | } else { | |
308 | host->dma_tx_channel = host->dma_rx_channel; | |
309 | } | |
310 | ||
311 | if (host->dma_rx_channel) | |
312 | rxname = dma_chan_name(host->dma_rx_channel); | |
313 | else | |
314 | rxname = "none"; | |
315 | ||
316 | if (host->dma_tx_channel) | |
317 | txname = dma_chan_name(host->dma_tx_channel); | |
318 | else | |
319 | txname = "none"; | |
320 | ||
321 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
322 | rxname, txname); | |
323 | ||
324 | /* | |
325 | * Limit the maximum segment size in any SG entry according to | |
326 | * the parameters of the DMA engine device. | |
327 | */ | |
328 | if (host->dma_tx_channel) { | |
329 | struct device *dev = host->dma_tx_channel->device->dev; | |
330 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
331 | ||
332 | if (max_seg_size < host->mmc->max_seg_size) | |
333 | host->mmc->max_seg_size = max_seg_size; | |
334 | } | |
335 | if (host->dma_rx_channel) { | |
336 | struct device *dev = host->dma_rx_channel->device->dev; | |
337 | unsigned int max_seg_size = dma_get_max_seg_size(dev); | |
338 | ||
339 | if (max_seg_size < host->mmc->max_seg_size) | |
340 | host->mmc->max_seg_size = max_seg_size; | |
341 | } | |
342 | } | |
343 | ||
344 | /* | |
6e0ee714 | 345 | * This is used in or so inline it |
c8ebae37 RK |
346 | * so it can be discarded. |
347 | */ | |
348 | static inline void mmci_dma_release(struct mmci_host *host) | |
349 | { | |
350 | struct mmci_platform_data *plat = host->plat; | |
351 | ||
352 | if (host->dma_rx_channel) | |
353 | dma_release_channel(host->dma_rx_channel); | |
354 | if (host->dma_tx_channel && plat->dma_tx_param) | |
355 | dma_release_channel(host->dma_tx_channel); | |
356 | host->dma_rx_channel = host->dma_tx_channel = NULL; | |
357 | } | |
358 | ||
359 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
360 | { | |
361 | struct dma_chan *chan = host->dma_current; | |
362 | enum dma_data_direction dir; | |
363 | u32 status; | |
364 | int i; | |
365 | ||
366 | /* Wait up to 1ms for the DMA to complete */ | |
367 | for (i = 0; ; i++) { | |
368 | status = readl(host->base + MMCISTATUS); | |
369 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
370 | break; | |
371 | udelay(10); | |
372 | } | |
373 | ||
374 | /* | |
375 | * Check to see whether we still have some data left in the FIFO - | |
376 | * this catches DMA controllers which are unable to monitor the | |
377 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
378 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
379 | */ | |
380 | if (status & MCI_RXDATAAVLBLMASK) { | |
381 | dmaengine_terminate_all(chan); | |
382 | if (!data->error) | |
383 | data->error = -EIO; | |
384 | } | |
385 | ||
386 | if (data->flags & MMC_DATA_WRITE) { | |
387 | dir = DMA_TO_DEVICE; | |
388 | } else { | |
389 | dir = DMA_FROM_DEVICE; | |
390 | } | |
391 | ||
58c7ccbf PF |
392 | if (!data->host_cookie) |
393 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, dir); | |
c8ebae37 RK |
394 | |
395 | /* | |
396 | * Use of DMA with scatter-gather is impossible. | |
397 | * Give up with DMA and switch back to PIO mode. | |
398 | */ | |
399 | if (status & MCI_RXDATAAVLBLMASK) { | |
400 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
401 | mmci_dma_release(host); | |
402 | } | |
403 | } | |
404 | ||
405 | static void mmci_dma_data_error(struct mmci_host *host) | |
406 | { | |
407 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); | |
408 | dmaengine_terminate_all(host->dma_current); | |
409 | } | |
410 | ||
58c7ccbf PF |
411 | static int mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data, |
412 | struct mmci_host_next *next) | |
c8ebae37 RK |
413 | { |
414 | struct variant_data *variant = host->variant; | |
415 | struct dma_slave_config conf = { | |
416 | .src_addr = host->phybase + MMCIFIFO, | |
417 | .dst_addr = host->phybase + MMCIFIFO, | |
418 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
419 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
420 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
421 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
258aea76 | 422 | .device_fc = false, |
c8ebae37 | 423 | }; |
c8ebae37 RK |
424 | struct dma_chan *chan; |
425 | struct dma_device *device; | |
426 | struct dma_async_tx_descriptor *desc; | |
05f5799c | 427 | enum dma_data_direction buffer_dirn; |
c8ebae37 RK |
428 | int nr_sg; |
429 | ||
58c7ccbf PF |
430 | /* Check if next job is already prepared */ |
431 | if (data->host_cookie && !next && | |
432 | host->dma_current && host->dma_desc_current) | |
433 | return 0; | |
434 | ||
435 | if (!next) { | |
436 | host->dma_current = NULL; | |
437 | host->dma_desc_current = NULL; | |
438 | } | |
c8ebae37 RK |
439 | |
440 | if (data->flags & MMC_DATA_READ) { | |
05f5799c VK |
441 | conf.direction = DMA_DEV_TO_MEM; |
442 | buffer_dirn = DMA_FROM_DEVICE; | |
c8ebae37 RK |
443 | chan = host->dma_rx_channel; |
444 | } else { | |
05f5799c VK |
445 | conf.direction = DMA_MEM_TO_DEV; |
446 | buffer_dirn = DMA_TO_DEVICE; | |
c8ebae37 RK |
447 | chan = host->dma_tx_channel; |
448 | } | |
449 | ||
450 | /* If there's no DMA channel, fall back to PIO */ | |
451 | if (!chan) | |
452 | return -EINVAL; | |
453 | ||
454 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
58c7ccbf | 455 | if (data->blksz * data->blocks <= variant->fifosize) |
c8ebae37 RK |
456 | return -EINVAL; |
457 | ||
458 | device = chan->device; | |
05f5799c | 459 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
c8ebae37 RK |
460 | if (nr_sg == 0) |
461 | return -EINVAL; | |
462 | ||
463 | dmaengine_slave_config(chan, &conf); | |
16052827 | 464 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
c8ebae37 RK |
465 | conf.direction, DMA_CTRL_ACK); |
466 | if (!desc) | |
467 | goto unmap_exit; | |
468 | ||
58c7ccbf PF |
469 | if (next) { |
470 | next->dma_chan = chan; | |
471 | next->dma_desc = desc; | |
472 | } else { | |
473 | host->dma_current = chan; | |
474 | host->dma_desc_current = desc; | |
475 | } | |
476 | ||
477 | return 0; | |
c8ebae37 | 478 | |
58c7ccbf PF |
479 | unmap_exit: |
480 | if (!next) | |
481 | dmaengine_terminate_all(chan); | |
05f5799c | 482 | dma_unmap_sg(device->dev, data->sg, data->sg_len, buffer_dirn); |
58c7ccbf PF |
483 | return -ENOMEM; |
484 | } | |
485 | ||
486 | static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
487 | { | |
488 | int ret; | |
489 | struct mmc_data *data = host->data; | |
490 | ||
491 | ret = mmci_dma_prep_data(host, host->data, NULL); | |
492 | if (ret) | |
493 | return ret; | |
494 | ||
495 | /* Okay, go for it. */ | |
c8ebae37 RK |
496 | dev_vdbg(mmc_dev(host->mmc), |
497 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
498 | data->sg_len, data->blksz, data->blocks, data->flags); | |
58c7ccbf PF |
499 | dmaengine_submit(host->dma_desc_current); |
500 | dma_async_issue_pending(host->dma_current); | |
c8ebae37 RK |
501 | |
502 | datactrl |= MCI_DPSM_DMAENABLE; | |
503 | ||
504 | /* Trigger the DMA transfer */ | |
505 | writel(datactrl, host->base + MMCIDATACTRL); | |
506 | ||
507 | /* | |
508 | * Let the MMCI say when the data is ended and it's time | |
509 | * to fire next DMA request. When that happens, MMCI will | |
510 | * call mmci_data_end() | |
511 | */ | |
512 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
513 | host->base + MMCIMASK0); | |
514 | return 0; | |
58c7ccbf | 515 | } |
c8ebae37 | 516 | |
58c7ccbf PF |
517 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
518 | { | |
519 | struct mmci_host_next *next = &host->next_data; | |
520 | ||
521 | if (data->host_cookie && data->host_cookie != next->cookie) { | |
a3c76eb9 | 522 | pr_warning("[%s] invalid cookie: data->host_cookie %d" |
58c7ccbf PF |
523 | " host->next_data.cookie %d\n", |
524 | __func__, data->host_cookie, host->next_data.cookie); | |
525 | data->host_cookie = 0; | |
526 | } | |
527 | ||
528 | if (!data->host_cookie) | |
529 | return; | |
530 | ||
531 | host->dma_desc_current = next->dma_desc; | |
532 | host->dma_current = next->dma_chan; | |
533 | ||
534 | next->dma_desc = NULL; | |
535 | next->dma_chan = NULL; | |
c8ebae37 | 536 | } |
58c7ccbf PF |
537 | |
538 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
539 | bool is_first_req) | |
540 | { | |
541 | struct mmci_host *host = mmc_priv(mmc); | |
542 | struct mmc_data *data = mrq->data; | |
543 | struct mmci_host_next *nd = &host->next_data; | |
544 | ||
545 | if (!data) | |
546 | return; | |
547 | ||
548 | if (data->host_cookie) { | |
549 | data->host_cookie = 0; | |
550 | return; | |
551 | } | |
552 | ||
553 | /* if config for dma */ | |
554 | if (((data->flags & MMC_DATA_WRITE) && host->dma_tx_channel) || | |
555 | ((data->flags & MMC_DATA_READ) && host->dma_rx_channel)) { | |
556 | if (mmci_dma_prep_data(host, data, nd)) | |
557 | data->host_cookie = 0; | |
558 | else | |
559 | data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie; | |
560 | } | |
561 | } | |
562 | ||
563 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
564 | int err) | |
565 | { | |
566 | struct mmci_host *host = mmc_priv(mmc); | |
567 | struct mmc_data *data = mrq->data; | |
568 | struct dma_chan *chan; | |
569 | enum dma_data_direction dir; | |
570 | ||
571 | if (!data) | |
572 | return; | |
573 | ||
574 | if (data->flags & MMC_DATA_READ) { | |
575 | dir = DMA_FROM_DEVICE; | |
576 | chan = host->dma_rx_channel; | |
577 | } else { | |
578 | dir = DMA_TO_DEVICE; | |
579 | chan = host->dma_tx_channel; | |
580 | } | |
581 | ||
582 | ||
583 | /* if config for dma */ | |
584 | if (chan) { | |
585 | if (err) | |
586 | dmaengine_terminate_all(chan); | |
8e3336b1 | 587 | if (data->host_cookie) |
58c7ccbf PF |
588 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, |
589 | data->sg_len, dir); | |
590 | mrq->data->host_cookie = 0; | |
591 | } | |
592 | } | |
593 | ||
c8ebae37 RK |
594 | #else |
595 | /* Blank functions if the DMA engine is not available */ | |
58c7ccbf PF |
596 | static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
597 | { | |
598 | } | |
c8ebae37 RK |
599 | static inline void mmci_dma_setup(struct mmci_host *host) |
600 | { | |
601 | } | |
602 | ||
603 | static inline void mmci_dma_release(struct mmci_host *host) | |
604 | { | |
605 | } | |
606 | ||
607 | static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
608 | { | |
609 | } | |
610 | ||
611 | static inline void mmci_dma_data_error(struct mmci_host *host) | |
612 | { | |
613 | } | |
614 | ||
615 | static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl) | |
616 | { | |
617 | return -ENOSYS; | |
618 | } | |
58c7ccbf PF |
619 | |
620 | #define mmci_pre_request NULL | |
621 | #define mmci_post_request NULL | |
622 | ||
c8ebae37 RK |
623 | #endif |
624 | ||
1da177e4 LT |
625 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
626 | { | |
8301bb68 | 627 | struct variant_data *variant = host->variant; |
1da177e4 | 628 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 629 | unsigned long long clks; |
1da177e4 | 630 | void __iomem *base; |
3bc87f24 | 631 | int blksz_bits; |
1da177e4 | 632 | |
64de0289 LW |
633 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
634 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
635 | |
636 | host->data = data; | |
528320db | 637 | host->size = data->blksz * data->blocks; |
51d4375d | 638 | data->bytes_xfered = 0; |
1da177e4 | 639 | |
7b09cdac RK |
640 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
641 | do_div(clks, 1000000000UL); | |
642 | ||
643 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
644 | |
645 | base = host->base; | |
646 | writel(timeout, base + MMCIDATATIMER); | |
647 | writel(host->size, base + MMCIDATALENGTH); | |
648 | ||
3bc87f24 RK |
649 | blksz_bits = ffs(data->blksz) - 1; |
650 | BUG_ON(1 << blksz_bits != data->blksz); | |
651 | ||
1784b157 PL |
652 | if (variant->blksz_datactrl16) |
653 | datactrl = MCI_DPSM_ENABLE | (data->blksz << 16); | |
654 | else | |
655 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
c8ebae37 RK |
656 | |
657 | if (data->flags & MMC_DATA_READ) | |
1da177e4 | 658 | datactrl |= MCI_DPSM_DIRECTION; |
c8ebae37 | 659 | |
7258db7e UH |
660 | /* The ST Micro variants has a special bit to enable SDIO */ |
661 | if (variant->sdio && host->mmc->card) | |
06c1a121 UH |
662 | if (mmc_card_sdio(host->mmc->card)) { |
663 | /* | |
664 | * The ST Micro variants has a special bit | |
665 | * to enable SDIO. | |
666 | */ | |
667 | u32 clk; | |
668 | ||
7258db7e UH |
669 | datactrl |= MCI_ST_DPSM_SDIOEN; |
670 | ||
06c1a121 | 671 | /* |
70ac0935 UH |
672 | * The ST Micro variant for SDIO small write transfers |
673 | * needs to have clock H/W flow control disabled, | |
674 | * otherwise the transfer will not start. The threshold | |
675 | * depends on the rate of MCLK. | |
06c1a121 | 676 | */ |
70ac0935 UH |
677 | if (data->flags & MMC_DATA_WRITE && |
678 | (host->size < 8 || | |
679 | (host->size <= 8 && host->mclk > 50000000))) | |
06c1a121 UH |
680 | clk = host->clk_reg & ~variant->clkreg_enable; |
681 | else | |
682 | clk = host->clk_reg | variant->clkreg_enable; | |
683 | ||
684 | mmci_write_clkreg(host, clk); | |
685 | } | |
686 | ||
6dbb6ee0 UH |
687 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) |
688 | datactrl |= MCI_ST_DPSM_DDRMODE; | |
689 | ||
c8ebae37 RK |
690 | /* |
691 | * Attempt to use DMA operation mode, if this | |
692 | * should fail, fall back to PIO mode | |
693 | */ | |
694 | if (!mmci_dma_start_data(host, datactrl)) | |
695 | return; | |
696 | ||
697 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
698 | mmci_init_sg(host, data); | |
699 | ||
700 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 701 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
702 | |
703 | /* | |
c4d877c1 RK |
704 | * If we have less than the fifo 'half-full' threshold to |
705 | * transfer, trigger a PIO interrupt as soon as any data | |
706 | * is available. | |
0425a142 | 707 | */ |
c4d877c1 | 708 | if (host->size < variant->fifohalfsize) |
0425a142 | 709 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
710 | } else { |
711 | /* | |
712 | * We don't actually need to include "FIFO empty" here | |
713 | * since its implicit in "FIFO half empty". | |
714 | */ | |
715 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
716 | } | |
717 | ||
718 | writel(datactrl, base + MMCIDATACTRL); | |
719 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
2686b4b4 | 720 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
721 | } |
722 | ||
723 | static void | |
724 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
725 | { | |
726 | void __iomem *base = host->base; | |
727 | ||
64de0289 | 728 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
729 | cmd->opcode, cmd->arg, cmd->flags); |
730 | ||
731 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
732 | writel(0, base + MMCICOMMAND); | |
733 | udelay(1); | |
734 | } | |
735 | ||
736 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
737 | if (cmd->flags & MMC_RSP_PRESENT) { |
738 | if (cmd->flags & MMC_RSP_136) | |
739 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 740 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
741 | } |
742 | if (/*interrupt*/0) | |
743 | c |= MCI_CPSM_INTERRUPT; | |
744 | ||
745 | host->cmd = cmd; | |
746 | ||
747 | writel(cmd->arg, base + MMCIARGUMENT); | |
748 | writel(c, base + MMCICOMMAND); | |
749 | } | |
750 | ||
751 | static void | |
752 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
753 | unsigned int status) | |
754 | { | |
f20f8f21 | 755 | /* First check for errors */ |
b63038d6 UH |
756 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
757 | MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
8cb28155 | 758 | u32 remain, success; |
f20f8f21 | 759 | |
c8ebae37 RK |
760 | /* Terminate the DMA transfer */ |
761 | if (dma_inprogress(host)) | |
762 | mmci_dma_data_error(host); | |
e9c091b4 RK |
763 | |
764 | /* | |
c8afc9d5 RK |
765 | * Calculate how far we are into the transfer. Note that |
766 | * the data counter gives the number of bytes transferred | |
767 | * on the MMC bus, not on the host side. On reads, this | |
768 | * can be as much as a FIFO-worth of data ahead. This | |
769 | * matters for FIFO overruns only. | |
e9c091b4 | 770 | */ |
f5a106d9 | 771 | remain = readl(host->base + MMCIDATACNT); |
8cb28155 LW |
772 | success = data->blksz * data->blocks - remain; |
773 | ||
c8afc9d5 RK |
774 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
775 | status, success); | |
8cb28155 LW |
776 | if (status & MCI_DATACRCFAIL) { |
777 | /* Last block was not successful */ | |
c8afc9d5 | 778 | success -= 1; |
17b0429d | 779 | data->error = -EILSEQ; |
8cb28155 | 780 | } else if (status & MCI_DATATIMEOUT) { |
17b0429d | 781 | data->error = -ETIMEDOUT; |
757df746 LW |
782 | } else if (status & MCI_STARTBITERR) { |
783 | data->error = -ECOMM; | |
c8afc9d5 RK |
784 | } else if (status & MCI_TXUNDERRUN) { |
785 | data->error = -EIO; | |
786 | } else if (status & MCI_RXOVERRUN) { | |
787 | if (success > host->variant->fifosize) | |
788 | success -= host->variant->fifosize; | |
789 | else | |
790 | success = 0; | |
17b0429d | 791 | data->error = -EIO; |
4ce1d6cb | 792 | } |
51d4375d | 793 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 794 | } |
f20f8f21 | 795 | |
8cb28155 LW |
796 | if (status & MCI_DATABLOCKEND) |
797 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 798 | |
ccff9b51 | 799 | if (status & MCI_DATAEND || data->error) { |
c8ebae37 RK |
800 | if (dma_inprogress(host)) |
801 | mmci_dma_unmap(host, data); | |
1da177e4 LT |
802 | mmci_stop_data(host); |
803 | ||
8cb28155 LW |
804 | if (!data->error) |
805 | /* The error clause is handled above, success! */ | |
51d4375d | 806 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 807 | |
1da177e4 LT |
808 | if (!data->stop) { |
809 | mmci_request_end(host, data->mrq); | |
810 | } else { | |
811 | mmci_start_command(host, data->stop, 0); | |
812 | } | |
813 | } | |
814 | } | |
815 | ||
816 | static void | |
817 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
818 | unsigned int status) | |
819 | { | |
820 | void __iomem *base = host->base; | |
821 | ||
822 | host->cmd = NULL; | |
823 | ||
1da177e4 | 824 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 825 | cmd->error = -ETIMEDOUT; |
1da177e4 | 826 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 827 | cmd->error = -EILSEQ; |
9047b435 RKAL |
828 | } else { |
829 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
830 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
831 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
832 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
833 | } |
834 | ||
17b0429d | 835 | if (!cmd->data || cmd->error) { |
3b6e3c73 UH |
836 | if (host->data) { |
837 | /* Terminate the DMA transfer */ | |
838 | if (dma_inprogress(host)) | |
839 | mmci_dma_data_error(host); | |
e47c222b | 840 | mmci_stop_data(host); |
3b6e3c73 | 841 | } |
1da177e4 LT |
842 | mmci_request_end(host, cmd->mrq); |
843 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
844 | mmci_start_data(host, cmd->data); | |
845 | } | |
846 | } | |
847 | ||
848 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
849 | { | |
850 | void __iomem *base = host->base; | |
851 | char *ptr = buffer; | |
852 | u32 status; | |
26eed9a5 | 853 | int host_remain = host->size; |
1da177e4 LT |
854 | |
855 | do { | |
26eed9a5 | 856 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
857 | |
858 | if (count > remain) | |
859 | count = remain; | |
860 | ||
861 | if (count <= 0) | |
862 | break; | |
863 | ||
393e5e24 UH |
864 | /* |
865 | * SDIO especially may want to send something that is | |
866 | * not divisible by 4 (as opposed to card sectors | |
867 | * etc). Therefore make sure to always read the last bytes | |
868 | * while only doing full 32-bit reads towards the FIFO. | |
869 | */ | |
870 | if (unlikely(count & 0x3)) { | |
871 | if (count < 4) { | |
872 | unsigned char buf[4]; | |
4b85da08 | 873 | ioread32_rep(base + MMCIFIFO, buf, 1); |
393e5e24 UH |
874 | memcpy(ptr, buf, count); |
875 | } else { | |
4b85da08 | 876 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
393e5e24 UH |
877 | count &= ~0x3; |
878 | } | |
879 | } else { | |
4b85da08 | 880 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
393e5e24 | 881 | } |
1da177e4 LT |
882 | |
883 | ptr += count; | |
884 | remain -= count; | |
26eed9a5 | 885 | host_remain -= count; |
1da177e4 LT |
886 | |
887 | if (remain == 0) | |
888 | break; | |
889 | ||
890 | status = readl(base + MMCISTATUS); | |
891 | } while (status & MCI_RXDATAAVLBL); | |
892 | ||
893 | return ptr - buffer; | |
894 | } | |
895 | ||
896 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
897 | { | |
8301bb68 | 898 | struct variant_data *variant = host->variant; |
1da177e4 LT |
899 | void __iomem *base = host->base; |
900 | char *ptr = buffer; | |
901 | ||
902 | do { | |
903 | unsigned int count, maxcnt; | |
904 | ||
8301bb68 RV |
905 | maxcnt = status & MCI_TXFIFOEMPTY ? |
906 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
907 | count = min(remain, maxcnt); |
908 | ||
34177802 LW |
909 | /* |
910 | * SDIO especially may want to send something that is | |
911 | * not divisible by 4 (as opposed to card sectors | |
912 | * etc), and the FIFO only accept full 32-bit writes. | |
913 | * So compensate by adding +3 on the count, a single | |
914 | * byte become a 32bit write, 7 bytes will be two | |
915 | * 32bit writes etc. | |
916 | */ | |
4b85da08 | 917 | iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); |
1da177e4 LT |
918 | |
919 | ptr += count; | |
920 | remain -= count; | |
921 | ||
922 | if (remain == 0) | |
923 | break; | |
924 | ||
925 | status = readl(base + MMCISTATUS); | |
926 | } while (status & MCI_TXFIFOHALFEMPTY); | |
927 | ||
928 | return ptr - buffer; | |
929 | } | |
930 | ||
931 | /* | |
932 | * PIO data transfer IRQ handler. | |
933 | */ | |
7d12e780 | 934 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
935 | { |
936 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 937 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 938 | struct variant_data *variant = host->variant; |
1da177e4 | 939 | void __iomem *base = host->base; |
4ce1d6cb | 940 | unsigned long flags; |
1da177e4 LT |
941 | u32 status; |
942 | ||
943 | status = readl(base + MMCISTATUS); | |
944 | ||
64de0289 | 945 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 946 | |
4ce1d6cb RV |
947 | local_irq_save(flags); |
948 | ||
1da177e4 | 949 | do { |
1da177e4 LT |
950 | unsigned int remain, len; |
951 | char *buffer; | |
952 | ||
953 | /* | |
954 | * For write, we only need to test the half-empty flag | |
955 | * here - if the FIFO is completely empty, then by | |
956 | * definition it is more than half empty. | |
957 | * | |
958 | * For read, check for data available. | |
959 | */ | |
960 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
961 | break; | |
962 | ||
4ce1d6cb RV |
963 | if (!sg_miter_next(sg_miter)) |
964 | break; | |
965 | ||
966 | buffer = sg_miter->addr; | |
967 | remain = sg_miter->length; | |
1da177e4 LT |
968 | |
969 | len = 0; | |
970 | if (status & MCI_RXACTIVE) | |
971 | len = mmci_pio_read(host, buffer, remain); | |
972 | if (status & MCI_TXACTIVE) | |
973 | len = mmci_pio_write(host, buffer, remain, status); | |
974 | ||
4ce1d6cb | 975 | sg_miter->consumed = len; |
1da177e4 | 976 | |
1da177e4 LT |
977 | host->size -= len; |
978 | remain -= len; | |
979 | ||
980 | if (remain) | |
981 | break; | |
982 | ||
1da177e4 LT |
983 | status = readl(base + MMCISTATUS); |
984 | } while (1); | |
985 | ||
4ce1d6cb RV |
986 | sg_miter_stop(sg_miter); |
987 | ||
988 | local_irq_restore(flags); | |
989 | ||
1da177e4 | 990 | /* |
c4d877c1 RK |
991 | * If we have less than the fifo 'half-full' threshold to transfer, |
992 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 993 | */ |
c4d877c1 | 994 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 995 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
996 | |
997 | /* | |
998 | * If we run out of data, disable the data IRQs; this | |
999 | * prevents a race where the FIFO becomes empty before | |
1000 | * the chip itself has disabled the data path, and | |
1001 | * stops us racing with our data end IRQ. | |
1002 | */ | |
1003 | if (host->size == 0) { | |
2686b4b4 | 1004 | mmci_set_mask1(host, 0); |
1da177e4 LT |
1005 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
1006 | } | |
1007 | ||
1008 | return IRQ_HANDLED; | |
1009 | } | |
1010 | ||
1011 | /* | |
1012 | * Handle completion of command and data transfers. | |
1013 | */ | |
7d12e780 | 1014 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
1015 | { |
1016 | struct mmci_host *host = dev_id; | |
1017 | u32 status; | |
1018 | int ret = 0; | |
1019 | ||
1020 | spin_lock(&host->lock); | |
1021 | ||
1022 | do { | |
1023 | struct mmc_command *cmd; | |
1024 | struct mmc_data *data; | |
1025 | ||
1026 | status = readl(host->base + MMCISTATUS); | |
2686b4b4 LW |
1027 | |
1028 | if (host->singleirq) { | |
1029 | if (status & readl(host->base + MMCIMASK1)) | |
1030 | mmci_pio_irq(irq, dev_id); | |
1031 | ||
1032 | status &= ~MCI_IRQ1MASK; | |
1033 | } | |
1034 | ||
1da177e4 LT |
1035 | status &= readl(host->base + MMCIMASK0); |
1036 | writel(status, host->base + MMCICLEAR); | |
1037 | ||
64de0289 | 1038 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
1039 | |
1040 | data = host->data; | |
b63038d6 UH |
1041 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR| |
1042 | MCI_TXUNDERRUN|MCI_RXOVERRUN|MCI_DATAEND| | |
1043 | MCI_DATABLOCKEND) && data) | |
1da177e4 LT |
1044 | mmci_data_irq(host, data, status); |
1045 | ||
1046 | cmd = host->cmd; | |
1047 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
1048 | mmci_cmd_irq(host, cmd, status); | |
1049 | ||
1050 | ret = 1; | |
1051 | } while (status); | |
1052 | ||
1053 | spin_unlock(&host->lock); | |
1054 | ||
1055 | return IRQ_RETVAL(ret); | |
1056 | } | |
1057 | ||
1058 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1059 | { | |
1060 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 1061 | unsigned long flags; |
1da177e4 LT |
1062 | |
1063 | WARN_ON(host->mrq != NULL); | |
1064 | ||
019a5f56 | 1065 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
1066 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
1067 | mrq->data->blksz); | |
255d01af PO |
1068 | mrq->cmd->error = -EINVAL; |
1069 | mmc_request_done(mmc, mrq); | |
1070 | return; | |
1071 | } | |
1072 | ||
1c3be369 RK |
1073 | pm_runtime_get_sync(mmc_dev(mmc)); |
1074 | ||
9e943021 | 1075 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
1076 | |
1077 | host->mrq = mrq; | |
1078 | ||
58c7ccbf PF |
1079 | if (mrq->data) |
1080 | mmci_get_next_data(host, mrq->data); | |
1081 | ||
1da177e4 LT |
1082 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) |
1083 | mmci_start_data(host, mrq->data); | |
1084 | ||
1085 | mmci_start_command(host, mrq->cmd, 0); | |
1086 | ||
9e943021 | 1087 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1088 | } |
1089 | ||
1090 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1091 | { | |
1092 | struct mmci_host *host = mmc_priv(mmc); | |
7d72a1d4 | 1093 | struct variant_data *variant = host->variant; |
a6a6464a LW |
1094 | u32 pwr = 0; |
1095 | unsigned long flags; | |
1da177e4 | 1096 | |
2cd976c4 UH |
1097 | pm_runtime_get_sync(mmc_dev(mmc)); |
1098 | ||
bc521818 UH |
1099 | if (host->plat->ios_handler && |
1100 | host->plat->ios_handler(mmc_dev(mmc), ios)) | |
1101 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); | |
1102 | ||
1da177e4 LT |
1103 | switch (ios->power_mode) { |
1104 | case MMC_POWER_OFF: | |
599c1d5c UH |
1105 | if (!IS_ERR(mmc->supply.vmmc)) |
1106 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
1da177e4 LT |
1107 | break; |
1108 | case MMC_POWER_UP: | |
599c1d5c UH |
1109 | if (!IS_ERR(mmc->supply.vmmc)) |
1110 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); | |
1111 | ||
7d72a1d4 UH |
1112 | /* |
1113 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP | |
1114 | * and instead uses MCI_PWR_ON so apply whatever value is | |
1115 | * configured in the variant data. | |
1116 | */ | |
1117 | pwr |= variant->pwrreg_powerup; | |
1118 | ||
1119 | break; | |
1da177e4 LT |
1120 | case MMC_POWER_ON: |
1121 | pwr |= MCI_PWR_ON; | |
1122 | break; | |
1123 | } | |
1124 | ||
4d1a3a0d UH |
1125 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
1126 | /* | |
1127 | * The ST Micro variant has some additional bits | |
1128 | * indicating signal direction for the signals in | |
1129 | * the SD/MMC bus and feedback-clock usage. | |
1130 | */ | |
1131 | pwr |= host->plat->sigdir; | |
1132 | ||
1133 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1134 | pwr &= ~MCI_ST_DATA74DIREN; | |
1135 | else if (ios->bus_width == MMC_BUS_WIDTH_1) | |
1136 | pwr &= (~MCI_ST_DATA74DIREN & | |
1137 | ~MCI_ST_DATA31DIREN & | |
1138 | ~MCI_ST_DATA2DIREN); | |
1139 | } | |
1140 | ||
cc30d60e | 1141 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 1142 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
1143 | pwr |= MCI_ROD; |
1144 | else { | |
1145 | /* | |
1146 | * The ST Micro variant use the ROD bit for something | |
1147 | * else and only has OD (Open Drain). | |
1148 | */ | |
1149 | pwr |= MCI_OD; | |
1150 | } | |
1151 | } | |
1da177e4 | 1152 | |
a6a6464a LW |
1153 | spin_lock_irqsave(&host->lock, flags); |
1154 | ||
1155 | mmci_set_clkreg(host, ios->clock); | |
7437cfa5 | 1156 | mmci_write_pwrreg(host, pwr); |
a6a6464a LW |
1157 | |
1158 | spin_unlock_irqrestore(&host->lock, flags); | |
2cd976c4 | 1159 | |
2cd976c4 UH |
1160 | pm_runtime_mark_last_busy(mmc_dev(mmc)); |
1161 | pm_runtime_put_autosuspend(mmc_dev(mmc)); | |
1da177e4 LT |
1162 | } |
1163 | ||
89001446 RK |
1164 | static int mmci_get_ro(struct mmc_host *mmc) |
1165 | { | |
1166 | struct mmci_host *host = mmc_priv(mmc); | |
1167 | ||
1168 | if (host->gpio_wp == -ENOSYS) | |
1169 | return -ENOSYS; | |
1170 | ||
18a06301 | 1171 | return gpio_get_value_cansleep(host->gpio_wp); |
89001446 RK |
1172 | } |
1173 | ||
1174 | static int mmci_get_cd(struct mmc_host *mmc) | |
1175 | { | |
1176 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 1177 | struct mmci_platform_data *plat = host->plat; |
89001446 RK |
1178 | unsigned int status; |
1179 | ||
4b8caec0 RV |
1180 | if (host->gpio_cd == -ENOSYS) { |
1181 | if (!plat->status) | |
1182 | return 1; /* Assume always present */ | |
1183 | ||
29719445 | 1184 | status = plat->status(mmc_dev(host->mmc)); |
4b8caec0 | 1185 | } else |
18a06301 LW |
1186 | status = !!gpio_get_value_cansleep(host->gpio_cd) |
1187 | ^ plat->cd_invert; | |
89001446 | 1188 | |
74bc8093 RK |
1189 | /* |
1190 | * Use positive logic throughout - status is zero for no card, | |
1191 | * non-zero for card inserted. | |
1192 | */ | |
1193 | return status; | |
89001446 RK |
1194 | } |
1195 | ||
148b8b39 RV |
1196 | static irqreturn_t mmci_cd_irq(int irq, void *dev_id) |
1197 | { | |
1198 | struct mmci_host *host = dev_id; | |
1199 | ||
1200 | mmc_detect_change(host->mmc, msecs_to_jiffies(500)); | |
1201 | ||
1202 | return IRQ_HANDLED; | |
1203 | } | |
1204 | ||
ab7aefd0 | 1205 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 | 1206 | .request = mmci_request, |
58c7ccbf PF |
1207 | .pre_req = mmci_pre_request, |
1208 | .post_req = mmci_post_request, | |
1da177e4 | 1209 | .set_ios = mmci_set_ios, |
89001446 RK |
1210 | .get_ro = mmci_get_ro, |
1211 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
1212 | }; |
1213 | ||
000bc9d5 LJ |
1214 | #ifdef CONFIG_OF |
1215 | static void mmci_dt_populate_generic_pdata(struct device_node *np, | |
1216 | struct mmci_platform_data *pdata) | |
1217 | { | |
1218 | int bus_width = 0; | |
1219 | ||
9a597016 | 1220 | pdata->gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); |
9a597016 | 1221 | pdata->gpio_cd = of_get_named_gpio(np, "cd-gpios", 0); |
000bc9d5 LJ |
1222 | |
1223 | if (of_get_property(np, "cd-inverted", NULL)) | |
1224 | pdata->cd_invert = true; | |
1225 | else | |
1226 | pdata->cd_invert = false; | |
1227 | ||
1228 | of_property_read_u32(np, "max-frequency", &pdata->f_max); | |
1229 | if (!pdata->f_max) | |
1230 | pr_warn("%s has no 'max-frequency' property\n", np->full_name); | |
1231 | ||
1232 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) | |
1233 | pdata->capabilities |= MMC_CAP_MMC_HIGHSPEED; | |
1234 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) | |
1235 | pdata->capabilities |= MMC_CAP_SD_HIGHSPEED; | |
1236 | ||
1237 | of_property_read_u32(np, "bus-width", &bus_width); | |
1238 | switch (bus_width) { | |
1239 | case 0 : | |
1240 | /* No bus-width supplied. */ | |
1241 | break; | |
1242 | case 4 : | |
1243 | pdata->capabilities |= MMC_CAP_4_BIT_DATA; | |
1244 | break; | |
1245 | case 8 : | |
1246 | pdata->capabilities |= MMC_CAP_8_BIT_DATA; | |
1247 | break; | |
1248 | default : | |
1249 | pr_warn("%s: Unsupported bus width\n", np->full_name); | |
1250 | } | |
1251 | } | |
c0a120a4 LJ |
1252 | #else |
1253 | static void mmci_dt_populate_generic_pdata(struct device_node *np, | |
1254 | struct mmci_platform_data *pdata) | |
1255 | { | |
1256 | return; | |
1257 | } | |
000bc9d5 LJ |
1258 | #endif |
1259 | ||
c3be1efd | 1260 | static int mmci_probe(struct amba_device *dev, |
aa25afad | 1261 | const struct amba_id *id) |
1da177e4 | 1262 | { |
6ef297f8 | 1263 | struct mmci_platform_data *plat = dev->dev.platform_data; |
000bc9d5 | 1264 | struct device_node *np = dev->dev.of_node; |
4956e109 | 1265 | struct variant_data *variant = id->data; |
1da177e4 LT |
1266 | struct mmci_host *host; |
1267 | struct mmc_host *mmc; | |
1268 | int ret; | |
1269 | ||
000bc9d5 LJ |
1270 | /* Must have platform data or Device Tree. */ |
1271 | if (!plat && !np) { | |
1272 | dev_err(&dev->dev, "No plat data or DT found\n"); | |
1273 | return -EINVAL; | |
1da177e4 LT |
1274 | } |
1275 | ||
b9b52918 LJ |
1276 | if (!plat) { |
1277 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); | |
1278 | if (!plat) | |
1279 | return -ENOMEM; | |
1280 | } | |
1281 | ||
000bc9d5 LJ |
1282 | if (np) |
1283 | mmci_dt_populate_generic_pdata(np, plat); | |
1284 | ||
1da177e4 LT |
1285 | ret = amba_request_regions(dev, DRIVER_NAME); |
1286 | if (ret) | |
1287 | goto out; | |
1288 | ||
1289 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
1290 | if (!mmc) { | |
1291 | ret = -ENOMEM; | |
1292 | goto rel_regions; | |
1293 | } | |
1294 | ||
1295 | host = mmc_priv(mmc); | |
4ea580f1 | 1296 | host->mmc = mmc; |
012b7d33 | 1297 | |
89001446 RK |
1298 | host->gpio_wp = -ENOSYS; |
1299 | host->gpio_cd = -ENOSYS; | |
148b8b39 | 1300 | host->gpio_cd_irq = -1; |
89001446 | 1301 | |
012b7d33 RK |
1302 | host->hw_designer = amba_manf(dev); |
1303 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1304 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1305 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1306 | |
ee569c43 | 1307 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
1308 | if (IS_ERR(host->clk)) { |
1309 | ret = PTR_ERR(host->clk); | |
1310 | host->clk = NULL; | |
1311 | goto host_free; | |
1312 | } | |
1313 | ||
ac940938 | 1314 | ret = clk_prepare_enable(host->clk); |
1da177e4 | 1315 | if (ret) |
a8d3584a | 1316 | goto clk_free; |
1da177e4 LT |
1317 | |
1318 | host->plat = plat; | |
4956e109 | 1319 | host->variant = variant; |
1da177e4 | 1320 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1321 | /* |
1322 | * According to the spec, mclk is max 100 MHz, | |
1323 | * so we try to adjust the clock down to this, | |
1324 | * (if possible). | |
1325 | */ | |
1326 | if (host->mclk > 100000000) { | |
1327 | ret = clk_set_rate(host->clk, 100000000); | |
1328 | if (ret < 0) | |
1329 | goto clk_disable; | |
1330 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1331 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1332 | host->mclk); | |
c8df9a53 | 1333 | } |
c8ebae37 | 1334 | host->phybase = dev->res.start; |
dc890c2d | 1335 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
1336 | if (!host->base) { |
1337 | ret = -ENOMEM; | |
1338 | goto clk_disable; | |
1339 | } | |
1340 | ||
1341 | mmc->ops = &mmci_ops; | |
7f294e49 LW |
1342 | /* |
1343 | * The ARM and ST versions of the block have slightly different | |
1344 | * clock divider equations which means that the minimum divider | |
1345 | * differs too. | |
1346 | */ | |
1347 | if (variant->st_clkdiv) | |
1348 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); | |
1349 | else | |
1350 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); | |
808d97cc LW |
1351 | /* |
1352 | * If the platform data supplies a maximum operating | |
1353 | * frequency, this takes precedence. Else, we fall back | |
1354 | * to using the module parameter, which has a (low) | |
1355 | * default value in case it is not specified. Either | |
1356 | * value must not exceed the clock rate into the block, | |
1357 | * of course. | |
1358 | */ | |
1359 | if (plat->f_max) | |
1360 | mmc->f_max = min(host->mclk, plat->f_max); | |
1361 | else | |
1362 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
1363 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1364 | ||
a9a83785 LW |
1365 | host->pinctrl = devm_pinctrl_get(&dev->dev); |
1366 | if (IS_ERR(host->pinctrl)) { | |
1367 | ret = PTR_ERR(host->pinctrl); | |
1368 | goto clk_disable; | |
1369 | } | |
1370 | ||
1371 | host->pins_default = pinctrl_lookup_state(host->pinctrl, | |
1372 | PINCTRL_STATE_DEFAULT); | |
1373 | ||
1374 | /* enable pins to be muxed in and configured */ | |
1375 | if (!IS_ERR(host->pins_default)) { | |
1376 | ret = pinctrl_select_state(host->pinctrl, host->pins_default); | |
1377 | if (ret) | |
1378 | dev_warn(&dev->dev, "could not set default pins\n"); | |
1379 | } else | |
1380 | dev_warn(&dev->dev, "could not get default pinstate\n"); | |
1381 | ||
599c1d5c UH |
1382 | /* Get regulators and the supported OCR mask */ |
1383 | mmc_regulator_get_supply(mmc); | |
1384 | if (!mmc->ocr_avail) | |
34e84f39 | 1385 | mmc->ocr_avail = plat->ocr_mask; |
599c1d5c UH |
1386 | else if (plat->ocr_mask) |
1387 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1388 | ||
9e6c82cd | 1389 | mmc->caps = plat->capabilities; |
5a092627 | 1390 | mmc->caps2 = plat->capabilities2; |
1da177e4 | 1391 | |
70be208f UH |
1392 | /* We support these PM capabilities. */ |
1393 | mmc->pm_caps = MMC_PM_KEEP_POWER; | |
1394 | ||
1da177e4 LT |
1395 | /* |
1396 | * We can do SGIO | |
1397 | */ | |
a36274e0 | 1398 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1399 | |
1400 | /* | |
08458ef6 RV |
1401 | * Since only a certain number of bits are valid in the data length |
1402 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1403 | * single request. | |
1da177e4 | 1404 | */ |
08458ef6 | 1405 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1406 | |
1407 | /* | |
1408 | * Set the maximum segment size. Since we aren't doing DMA | |
1409 | * (yet) we are only limited by the data length register. | |
1410 | */ | |
55db890a | 1411 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1412 | |
fe4a3c7a PO |
1413 | /* |
1414 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1415 | */ | |
8f7f6b7e | 1416 | mmc->max_blk_size = 1 << 11; |
fe4a3c7a | 1417 | |
55db890a | 1418 | /* |
8f7f6b7e WD |
1419 | * Limit the number of blocks transferred so that we don't overflow |
1420 | * the maximum request size. | |
55db890a | 1421 | */ |
8f7f6b7e | 1422 | mmc->max_blk_count = mmc->max_req_size >> 11; |
55db890a | 1423 | |
1da177e4 LT |
1424 | spin_lock_init(&host->lock); |
1425 | ||
1426 | writel(0, host->base + MMCIMASK0); | |
1427 | writel(0, host->base + MMCIMASK1); | |
1428 | writel(0xfff, host->base + MMCICLEAR); | |
1429 | ||
2805b9ab RS |
1430 | if (plat->gpio_cd == -EPROBE_DEFER) { |
1431 | ret = -EPROBE_DEFER; | |
1432 | goto err_gpio_cd; | |
1433 | } | |
89001446 RK |
1434 | if (gpio_is_valid(plat->gpio_cd)) { |
1435 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
1436 | if (ret == 0) | |
1437 | ret = gpio_direction_input(plat->gpio_cd); | |
1438 | if (ret == 0) | |
1439 | host->gpio_cd = plat->gpio_cd; | |
1440 | else if (ret != -ENOSYS) | |
1441 | goto err_gpio_cd; | |
148b8b39 | 1442 | |
17ee083b LW |
1443 | /* |
1444 | * A gpio pin that will detect cards when inserted and removed | |
1445 | * will most likely want to trigger on the edges if it is | |
1446 | * 0 when ejected and 1 when inserted (or mutatis mutandis | |
1447 | * for the inverted case) so we request triggers on both | |
1448 | * edges. | |
1449 | */ | |
148b8b39 | 1450 | ret = request_any_context_irq(gpio_to_irq(plat->gpio_cd), |
17ee083b LW |
1451 | mmci_cd_irq, |
1452 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | |
1453 | DRIVER_NAME " (cd)", host); | |
148b8b39 RV |
1454 | if (ret >= 0) |
1455 | host->gpio_cd_irq = gpio_to_irq(plat->gpio_cd); | |
89001446 | 1456 | } |
2805b9ab RS |
1457 | if (plat->gpio_wp == -EPROBE_DEFER) { |
1458 | ret = -EPROBE_DEFER; | |
1459 | goto err_gpio_wp; | |
1460 | } | |
89001446 RK |
1461 | if (gpio_is_valid(plat->gpio_wp)) { |
1462 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
1463 | if (ret == 0) | |
1464 | ret = gpio_direction_input(plat->gpio_wp); | |
1465 | if (ret == 0) | |
1466 | host->gpio_wp = plat->gpio_wp; | |
1467 | else if (ret != -ENOSYS) | |
1468 | goto err_gpio_wp; | |
1469 | } | |
1470 | ||
4b8caec0 RV |
1471 | if ((host->plat->status || host->gpio_cd != -ENOSYS) |
1472 | && host->gpio_cd_irq < 0) | |
148b8b39 RV |
1473 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1474 | ||
dace1453 | 1475 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
1476 | if (ret) |
1477 | goto unmap; | |
1478 | ||
dfb85185 | 1479 | if (!dev->irq[1]) |
2686b4b4 LW |
1480 | host->singleirq = true; |
1481 | else { | |
1482 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, | |
1483 | DRIVER_NAME " (pio)", host); | |
1484 | if (ret) | |
1485 | goto irq0_free; | |
1486 | } | |
1da177e4 | 1487 | |
8cb28155 | 1488 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); |
1da177e4 LT |
1489 | |
1490 | amba_set_drvdata(dev, mmc); | |
1491 | ||
c8ebae37 RK |
1492 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
1493 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
1494 | amba_rev(dev), (unsigned long long)dev->res.start, | |
1495 | dev->irq[0], dev->irq[1]); | |
1496 | ||
1497 | mmci_dma_setup(host); | |
1da177e4 | 1498 | |
2cd976c4 UH |
1499 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
1500 | pm_runtime_use_autosuspend(&dev->dev); | |
1c3be369 RK |
1501 | pm_runtime_put(&dev->dev); |
1502 | ||
8c11a94d RK |
1503 | mmc_add_host(mmc); |
1504 | ||
1da177e4 LT |
1505 | return 0; |
1506 | ||
1507 | irq0_free: | |
1508 | free_irq(dev->irq[0], host); | |
1509 | unmap: | |
89001446 RK |
1510 | if (host->gpio_wp != -ENOSYS) |
1511 | gpio_free(host->gpio_wp); | |
1512 | err_gpio_wp: | |
148b8b39 RV |
1513 | if (host->gpio_cd_irq >= 0) |
1514 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1515 | if (host->gpio_cd != -ENOSYS) |
1516 | gpio_free(host->gpio_cd); | |
1517 | err_gpio_cd: | |
1da177e4 LT |
1518 | iounmap(host->base); |
1519 | clk_disable: | |
ac940938 | 1520 | clk_disable_unprepare(host->clk); |
1da177e4 LT |
1521 | clk_free: |
1522 | clk_put(host->clk); | |
1523 | host_free: | |
1524 | mmc_free_host(mmc); | |
1525 | rel_regions: | |
1526 | amba_release_regions(dev); | |
1527 | out: | |
1528 | return ret; | |
1529 | } | |
1530 | ||
6e0ee714 | 1531 | static int mmci_remove(struct amba_device *dev) |
1da177e4 LT |
1532 | { |
1533 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
1534 | ||
1535 | amba_set_drvdata(dev, NULL); | |
1536 | ||
1537 | if (mmc) { | |
1538 | struct mmci_host *host = mmc_priv(mmc); | |
1539 | ||
1c3be369 RK |
1540 | /* |
1541 | * Undo pm_runtime_put() in probe. We use the _sync | |
1542 | * version here so that we can access the primecell. | |
1543 | */ | |
1544 | pm_runtime_get_sync(&dev->dev); | |
1545 | ||
1da177e4 LT |
1546 | mmc_remove_host(mmc); |
1547 | ||
1548 | writel(0, host->base + MMCIMASK0); | |
1549 | writel(0, host->base + MMCIMASK1); | |
1550 | ||
1551 | writel(0, host->base + MMCICOMMAND); | |
1552 | writel(0, host->base + MMCIDATACTRL); | |
1553 | ||
c8ebae37 | 1554 | mmci_dma_release(host); |
1da177e4 | 1555 | free_irq(dev->irq[0], host); |
2686b4b4 LW |
1556 | if (!host->singleirq) |
1557 | free_irq(dev->irq[1], host); | |
1da177e4 | 1558 | |
89001446 RK |
1559 | if (host->gpio_wp != -ENOSYS) |
1560 | gpio_free(host->gpio_wp); | |
148b8b39 RV |
1561 | if (host->gpio_cd_irq >= 0) |
1562 | free_irq(host->gpio_cd_irq, host); | |
89001446 RK |
1563 | if (host->gpio_cd != -ENOSYS) |
1564 | gpio_free(host->gpio_cd); | |
1565 | ||
1da177e4 | 1566 | iounmap(host->base); |
ac940938 | 1567 | clk_disable_unprepare(host->clk); |
1da177e4 LT |
1568 | clk_put(host->clk); |
1569 | ||
1570 | mmc_free_host(mmc); | |
1571 | ||
1572 | amba_release_regions(dev); | |
1573 | } | |
1574 | ||
1575 | return 0; | |
1576 | } | |
1577 | ||
48fa7003 UH |
1578 | #ifdef CONFIG_SUSPEND |
1579 | static int mmci_suspend(struct device *dev) | |
1da177e4 | 1580 | { |
48fa7003 UH |
1581 | struct amba_device *adev = to_amba_device(dev); |
1582 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1da177e4 LT |
1583 | int ret = 0; |
1584 | ||
1585 | if (mmc) { | |
1586 | struct mmci_host *host = mmc_priv(mmc); | |
1587 | ||
1a13f8fa | 1588 | ret = mmc_suspend_host(mmc); |
2cd976c4 UH |
1589 | if (ret == 0) { |
1590 | pm_runtime_get_sync(dev); | |
1da177e4 | 1591 | writel(0, host->base + MMCIMASK0); |
2cd976c4 | 1592 | } |
1da177e4 LT |
1593 | } |
1594 | ||
1595 | return ret; | |
1596 | } | |
1597 | ||
48fa7003 | 1598 | static int mmci_resume(struct device *dev) |
1da177e4 | 1599 | { |
48fa7003 UH |
1600 | struct amba_device *adev = to_amba_device(dev); |
1601 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
1da177e4 LT |
1602 | int ret = 0; |
1603 | ||
1604 | if (mmc) { | |
1605 | struct mmci_host *host = mmc_priv(mmc); | |
1606 | ||
1607 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
2cd976c4 | 1608 | pm_runtime_put(dev); |
1da177e4 LT |
1609 | |
1610 | ret = mmc_resume_host(mmc); | |
1611 | } | |
1612 | ||
1613 | return ret; | |
1614 | } | |
1da177e4 LT |
1615 | #endif |
1616 | ||
48fa7003 UH |
1617 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
1618 | SET_SYSTEM_SLEEP_PM_OPS(mmci_suspend, mmci_resume) | |
1619 | }; | |
1620 | ||
1da177e4 LT |
1621 | static struct amba_id mmci_ids[] = { |
1622 | { | |
1623 | .id = 0x00041180, | |
768fbc18 | 1624 | .mask = 0xff0fffff, |
4956e109 | 1625 | .data = &variant_arm, |
1da177e4 | 1626 | }, |
768fbc18 PM |
1627 | { |
1628 | .id = 0x01041180, | |
1629 | .mask = 0xff0fffff, | |
1630 | .data = &variant_arm_extended_fifo, | |
1631 | }, | |
1da177e4 LT |
1632 | { |
1633 | .id = 0x00041181, | |
1634 | .mask = 0x000fffff, | |
4956e109 | 1635 | .data = &variant_arm, |
1da177e4 | 1636 | }, |
cc30d60e LW |
1637 | /* ST Micro variants */ |
1638 | { | |
1639 | .id = 0x00180180, | |
1640 | .mask = 0x00ffffff, | |
4956e109 | 1641 | .data = &variant_u300, |
cc30d60e | 1642 | }, |
34fd4213 LW |
1643 | { |
1644 | .id = 0x10180180, | |
1645 | .mask = 0xf0ffffff, | |
1646 | .data = &variant_nomadik, | |
1647 | }, | |
cc30d60e LW |
1648 | { |
1649 | .id = 0x00280180, | |
1650 | .mask = 0x00ffffff, | |
4956e109 RV |
1651 | .data = &variant_u300, |
1652 | }, | |
1653 | { | |
1654 | .id = 0x00480180, | |
1784b157 | 1655 | .mask = 0xf0ffffff, |
4956e109 | 1656 | .data = &variant_ux500, |
cc30d60e | 1657 | }, |
1784b157 PL |
1658 | { |
1659 | .id = 0x10480180, | |
1660 | .mask = 0xf0ffffff, | |
1661 | .data = &variant_ux500v2, | |
1662 | }, | |
1da177e4 LT |
1663 | { 0, 0 }, |
1664 | }; | |
1665 | ||
9f99835f DM |
1666 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
1667 | ||
1da177e4 LT |
1668 | static struct amba_driver mmci_driver = { |
1669 | .drv = { | |
1670 | .name = DRIVER_NAME, | |
48fa7003 | 1671 | .pm = &mmci_dev_pm_ops, |
1da177e4 LT |
1672 | }, |
1673 | .probe = mmci_probe, | |
0433c143 | 1674 | .remove = mmci_remove, |
1da177e4 LT |
1675 | .id_table = mmci_ids, |
1676 | }; | |
1677 | ||
9e5ed094 | 1678 | module_amba_driver(mmci_driver); |
1da177e4 | 1679 | |
1da177e4 LT |
1680 | module_param(fmax, uint, 0444); |
1681 | ||
1682 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
1683 | MODULE_LICENSE("GPL"); |