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Commit | Line | Data |
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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 | 2 | /* |
70f10482 | 3 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
c8ebae37 | 6 | * Copyright (C) 2010 ST-Ericsson SA |
1da177e4 | 7 | */ |
1da177e4 LT |
8 | #include <linux/module.h> |
9 | #include <linux/moduleparam.h> | |
10 | #include <linux/init.h> | |
11 | #include <linux/ioport.h> | |
12 | #include <linux/device.h> | |
ef289982 | 13 | #include <linux/io.h> |
1da177e4 | 14 | #include <linux/interrupt.h> |
613b152c | 15 | #include <linux/kernel.h> |
000bc9d5 | 16 | #include <linux/slab.h> |
1da177e4 LT |
17 | #include <linux/delay.h> |
18 | #include <linux/err.h> | |
19 | #include <linux/highmem.h> | |
019a5f56 | 20 | #include <linux/log2.h> |
c8073e52 | 21 | #include <linux/mmc/mmc.h> |
70be208f | 22 | #include <linux/mmc/pm.h> |
1da177e4 | 23 | #include <linux/mmc/host.h> |
34177802 | 24 | #include <linux/mmc/card.h> |
d2762090 | 25 | #include <linux/mmc/slot-gpio.h> |
a62c80e5 | 26 | #include <linux/amba/bus.h> |
f8ce2547 | 27 | #include <linux/clk.h> |
bd6dee6f | 28 | #include <linux/scatterlist.h> |
9ef986a6 | 29 | #include <linux/of.h> |
34e84f39 | 30 | #include <linux/regulator/consumer.h> |
c8ebae37 RK |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/dma-mapping.h> | |
33 | #include <linux/amba/mmci.h> | |
1c3be369 | 34 | #include <linux/pm_runtime.h> |
258aea76 | 35 | #include <linux/types.h> |
a9a83785 | 36 | #include <linux/pinctrl/consumer.h> |
15878e58 | 37 | #include <linux/reset.h> |
1da177e4 | 38 | |
7b09cdac | 39 | #include <asm/div64.h> |
1da177e4 | 40 | #include <asm/io.h> |
1da177e4 LT |
41 | |
42 | #include "mmci.h" | |
43 | ||
44 | #define DRIVER_NAME "mmci-pl18x" | |
45 | ||
71953e0e | 46 | static void mmci_variant_init(struct mmci_host *host); |
b3fb9d64 | 47 | static void ux500v2_variant_init(struct mmci_host *host); |
c3647fdc | 48 | |
1da177e4 LT |
49 | static unsigned int fmax = 515633; |
50 | ||
4956e109 | 51 | static struct variant_data variant_arm = { |
8301bb68 RV |
52 | .fifosize = 16 * 4, |
53 | .fifohalfsize = 8 * 4, | |
0f244804 LB |
54 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
55 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, | |
56 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, | |
57 | .cmdreg_srsp = MCI_CPSM_RESPONSE, | |
08458ef6 | 58 | .datalength_bits = 16, |
c931d495 | 59 | .datactrl_blocksz = 11, |
7d72a1d4 | 60 | .pwrreg_powerup = MCI_PWR_UP, |
dc6500bf | 61 | .f_max = 100000000, |
7878289b | 62 | .reversed_irq_handling = true, |
6ea9cdf3 | 63 | .mmcimask1 = true, |
59db5e2d | 64 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
7f7b5503 | 65 | .start_err = MCI_STARTBITERR, |
11dfb970 | 66 | .opendrain = MCI_ROD, |
c3647fdc | 67 | .init = mmci_variant_init, |
4956e109 RV |
68 | }; |
69 | ||
768fbc18 PM |
70 | static struct variant_data variant_arm_extended_fifo = { |
71 | .fifosize = 128 * 4, | |
72 | .fifohalfsize = 64 * 4, | |
0f244804 LB |
73 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
74 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, | |
75 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, | |
76 | .cmdreg_srsp = MCI_CPSM_RESPONSE, | |
768fbc18 | 77 | .datalength_bits = 16, |
c931d495 | 78 | .datactrl_blocksz = 11, |
7d72a1d4 | 79 | .pwrreg_powerup = MCI_PWR_UP, |
dc6500bf | 80 | .f_max = 100000000, |
6ea9cdf3 | 81 | .mmcimask1 = true, |
59db5e2d | 82 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
7f7b5503 | 83 | .start_err = MCI_STARTBITERR, |
11dfb970 | 84 | .opendrain = MCI_ROD, |
c3647fdc | 85 | .init = mmci_variant_init, |
768fbc18 PM |
86 | }; |
87 | ||
3a37298a PM |
88 | static struct variant_data variant_arm_extended_fifo_hwfc = { |
89 | .fifosize = 128 * 4, | |
90 | .fifohalfsize = 64 * 4, | |
91 | .clkreg_enable = MCI_ARM_HWFCEN, | |
0f244804 LB |
92 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
93 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, | |
94 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, | |
95 | .cmdreg_srsp = MCI_CPSM_RESPONSE, | |
3a37298a | 96 | .datalength_bits = 16, |
c931d495 | 97 | .datactrl_blocksz = 11, |
3a37298a | 98 | .pwrreg_powerup = MCI_PWR_UP, |
dc6500bf | 99 | .f_max = 100000000, |
6ea9cdf3 | 100 | .mmcimask1 = true, |
59db5e2d | 101 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
7f7b5503 | 102 | .start_err = MCI_STARTBITERR, |
11dfb970 | 103 | .opendrain = MCI_ROD, |
c3647fdc | 104 | .init = mmci_variant_init, |
3a37298a PM |
105 | }; |
106 | ||
4956e109 | 107 | static struct variant_data variant_u300 = { |
8301bb68 RV |
108 | .fifosize = 16 * 4, |
109 | .fifohalfsize = 8 * 4, | |
49ac215e | 110 | .clkreg_enable = MCI_ST_U300_HWFCEN, |
e1412d85 | 111 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
0f244804 LB |
112 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
113 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, | |
114 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, | |
115 | .cmdreg_srsp = MCI_CPSM_RESPONSE, | |
08458ef6 | 116 | .datalength_bits = 16, |
c931d495 | 117 | .datactrl_blocksz = 11, |
5db3eee7 | 118 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
c7354133 | 119 | .st_sdio = true, |
7d72a1d4 | 120 | .pwrreg_powerup = MCI_PWR_ON, |
dc6500bf | 121 | .f_max = 100000000, |
4d1a3a0d | 122 | .signal_direction = true, |
f4670dae | 123 | .pwrreg_clkgate = true, |
1ff44433 | 124 | .pwrreg_nopower = true, |
6ea9cdf3 | 125 | .mmcimask1 = true, |
59db5e2d | 126 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
7f7b5503 | 127 | .start_err = MCI_STARTBITERR, |
11dfb970 | 128 | .opendrain = MCI_OD, |
c3647fdc | 129 | .init = mmci_variant_init, |
4956e109 RV |
130 | }; |
131 | ||
34fd4213 LW |
132 | static struct variant_data variant_nomadik = { |
133 | .fifosize = 16 * 4, | |
134 | .fifohalfsize = 8 * 4, | |
135 | .clkreg = MCI_CLK_ENABLE, | |
f5abc767 | 136 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
0f244804 LB |
137 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
138 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, | |
139 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, | |
140 | .cmdreg_srsp = MCI_CPSM_RESPONSE, | |
34fd4213 | 141 | .datalength_bits = 24, |
c931d495 | 142 | .datactrl_blocksz = 11, |
5db3eee7 | 143 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
c7354133 | 144 | .st_sdio = true, |
34fd4213 LW |
145 | .st_clkdiv = true, |
146 | .pwrreg_powerup = MCI_PWR_ON, | |
dc6500bf | 147 | .f_max = 100000000, |
34fd4213 | 148 | .signal_direction = true, |
f4670dae | 149 | .pwrreg_clkgate = true, |
1ff44433 | 150 | .pwrreg_nopower = true, |
6ea9cdf3 | 151 | .mmcimask1 = true, |
59db5e2d | 152 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
7f7b5503 | 153 | .start_err = MCI_STARTBITERR, |
11dfb970 | 154 | .opendrain = MCI_OD, |
c3647fdc | 155 | .init = mmci_variant_init, |
34fd4213 LW |
156 | }; |
157 | ||
4956e109 | 158 | static struct variant_data variant_ux500 = { |
8301bb68 RV |
159 | .fifosize = 30 * 4, |
160 | .fifohalfsize = 8 * 4, | |
4956e109 | 161 | .clkreg = MCI_CLK_ENABLE, |
49ac215e | 162 | .clkreg_enable = MCI_ST_UX500_HWFCEN, |
e1412d85 | 163 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
e8740644 | 164 | .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, |
0f244804 LB |
165 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
166 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, | |
167 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, | |
168 | .cmdreg_srsp = MCI_CPSM_RESPONSE, | |
08458ef6 | 169 | .datalength_bits = 24, |
c931d495 | 170 | .datactrl_blocksz = 11, |
5db3eee7 | 171 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
c7354133 | 172 | .st_sdio = true, |
b70a67f9 | 173 | .st_clkdiv = true, |
7d72a1d4 | 174 | .pwrreg_powerup = MCI_PWR_ON, |
dc6500bf | 175 | .f_max = 100000000, |
4d1a3a0d | 176 | .signal_direction = true, |
f4670dae | 177 | .pwrreg_clkgate = true, |
01259620 | 178 | .busy_detect = true, |
49adc0ca LW |
179 | .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, |
180 | .busy_detect_flag = MCI_ST_CARDBUSY, | |
181 | .busy_detect_mask = MCI_ST_BUSYENDMASK, | |
1ff44433 | 182 | .pwrreg_nopower = true, |
6ea9cdf3 | 183 | .mmcimask1 = true, |
59db5e2d | 184 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
7f7b5503 | 185 | .start_err = MCI_STARTBITERR, |
11dfb970 | 186 | .opendrain = MCI_OD, |
c3647fdc | 187 | .init = mmci_variant_init, |
4956e109 | 188 | }; |
b70a67f9 | 189 | |
1784b157 PL |
190 | static struct variant_data variant_ux500v2 = { |
191 | .fifosize = 30 * 4, | |
192 | .fifohalfsize = 8 * 4, | |
193 | .clkreg = MCI_CLK_ENABLE, | |
194 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
e1412d85 | 195 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, |
e8740644 | 196 | .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, |
0f244804 LB |
197 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
198 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, | |
199 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, | |
200 | .cmdreg_srsp = MCI_CPSM_RESPONSE, | |
5db3eee7 | 201 | .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE, |
1784b157 | 202 | .datalength_bits = 24, |
c931d495 | 203 | .datactrl_blocksz = 11, |
5db3eee7 | 204 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
c7354133 | 205 | .st_sdio = true, |
1784b157 | 206 | .st_clkdiv = true, |
7d72a1d4 | 207 | .pwrreg_powerup = MCI_PWR_ON, |
dc6500bf | 208 | .f_max = 100000000, |
4d1a3a0d | 209 | .signal_direction = true, |
f4670dae | 210 | .pwrreg_clkgate = true, |
01259620 | 211 | .busy_detect = true, |
49adc0ca LW |
212 | .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE, |
213 | .busy_detect_flag = MCI_ST_CARDBUSY, | |
214 | .busy_detect_mask = MCI_ST_BUSYENDMASK, | |
1ff44433 | 215 | .pwrreg_nopower = true, |
6ea9cdf3 | 216 | .mmcimask1 = true, |
59db5e2d | 217 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
7f7b5503 | 218 | .start_err = MCI_STARTBITERR, |
11dfb970 | 219 | .opendrain = MCI_OD, |
b3fb9d64 | 220 | .init = ux500v2_variant_init, |
1784b157 PL |
221 | }; |
222 | ||
2a9d6c80 PC |
223 | static struct variant_data variant_stm32 = { |
224 | .fifosize = 32 * 4, | |
225 | .fifohalfsize = 8 * 4, | |
226 | .clkreg = MCI_CLK_ENABLE, | |
227 | .clkreg_enable = MCI_ST_UX500_HWFCEN, | |
228 | .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS, | |
229 | .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE, | |
0f244804 LB |
230 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
231 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, | |
232 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, | |
233 | .cmdreg_srsp = MCI_CPSM_RESPONSE, | |
59db5e2d | 234 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
2a9d6c80 | 235 | .datalength_bits = 24, |
c931d495 | 236 | .datactrl_blocksz = 11, |
2a9d6c80 PC |
237 | .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, |
238 | .st_sdio = true, | |
239 | .st_clkdiv = true, | |
240 | .pwrreg_powerup = MCI_PWR_ON, | |
241 | .f_max = 48000000, | |
242 | .pwrreg_clkgate = true, | |
243 | .pwrreg_nopower = true, | |
c3647fdc | 244 | .init = mmci_variant_init, |
2a9d6c80 PC |
245 | }; |
246 | ||
46b723dd LB |
247 | static struct variant_data variant_stm32_sdmmc = { |
248 | .fifosize = 16 * 4, | |
249 | .fifohalfsize = 8 * 4, | |
250 | .f_max = 208000000, | |
251 | .stm32_clkdiv = true, | |
252 | .cmdreg_cpsm_enable = MCI_CPSM_STM32_ENABLE, | |
253 | .cmdreg_lrsp_crc = MCI_CPSM_STM32_LRSP_CRC, | |
254 | .cmdreg_srsp_crc = MCI_CPSM_STM32_SRSP_CRC, | |
255 | .cmdreg_srsp = MCI_CPSM_STM32_SRSP, | |
c8073e52 | 256 | .cmdreg_stop = MCI_CPSM_STM32_CMDSTOP, |
46b723dd LB |
257 | .data_cmd_enable = MCI_CPSM_STM32_CMDTRANS, |
258 | .irq_pio_mask = MCI_IRQ_PIO_STM32_MASK, | |
259 | .datactrl_first = true, | |
260 | .datacnt_useless = true, | |
261 | .datalength_bits = 25, | |
262 | .datactrl_blocksz = 14, | |
263 | .stm32_idmabsize_mask = GENMASK(12, 5), | |
264 | .init = sdmmc_variant_init, | |
265 | }; | |
266 | ||
55b604ae SK |
267 | static struct variant_data variant_qcom = { |
268 | .fifosize = 16 * 4, | |
269 | .fifohalfsize = 8 * 4, | |
270 | .clkreg = MCI_CLK_ENABLE, | |
271 | .clkreg_enable = MCI_QCOM_CLK_FLOWENA | | |
272 | MCI_QCOM_CLK_SELECT_IN_FBCLK, | |
273 | .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8, | |
274 | .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE, | |
0f244804 LB |
275 | .cmdreg_cpsm_enable = MCI_CPSM_ENABLE, |
276 | .cmdreg_lrsp_crc = MCI_CPSM_RESPONSE | MCI_CPSM_LONGRSP, | |
277 | .cmdreg_srsp_crc = MCI_CPSM_RESPONSE, | |
278 | .cmdreg_srsp = MCI_CPSM_RESPONSE, | |
5db3eee7 | 279 | .data_cmd_enable = MCI_CPSM_QCOM_DATCMD, |
55b604ae | 280 | .datalength_bits = 24, |
c931d495 | 281 | .datactrl_blocksz = 11, |
55b604ae SK |
282 | .pwrreg_powerup = MCI_PWR_UP, |
283 | .f_max = 208000000, | |
284 | .explicit_mclk_control = true, | |
285 | .qcom_fifo = true, | |
9cb15142 | 286 | .qcom_dml = true, |
6ea9cdf3 | 287 | .mmcimask1 = true, |
59db5e2d | 288 | .irq_pio_mask = MCI_IRQ_PIO_MASK, |
7f7b5503 | 289 | .start_err = MCI_STARTBITERR, |
11dfb970 | 290 | .opendrain = MCI_ROD, |
29aba07a | 291 | .init = qcom_variant_init, |
55b604ae SK |
292 | }; |
293 | ||
49adc0ca | 294 | /* Busy detection for the ST Micro variant */ |
01259620 UH |
295 | static int mmci_card_busy(struct mmc_host *mmc) |
296 | { | |
297 | struct mmci_host *host = mmc_priv(mmc); | |
298 | unsigned long flags; | |
299 | int busy = 0; | |
300 | ||
01259620 | 301 | spin_lock_irqsave(&host->lock, flags); |
49adc0ca | 302 | if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag) |
01259620 UH |
303 | busy = 1; |
304 | spin_unlock_irqrestore(&host->lock, flags); | |
305 | ||
01259620 UH |
306 | return busy; |
307 | } | |
308 | ||
f829c042 UH |
309 | static void mmci_reg_delay(struct mmci_host *host) |
310 | { | |
311 | /* | |
312 | * According to the spec, at least three feedback clock cycles | |
313 | * of max 52 MHz must pass between two writes to the MMCICLOCK reg. | |
314 | * Three MCLK clock cycles must pass between two MMCIPOWER reg writes. | |
315 | * Worst delay time during card init is at 100 kHz => 30 us. | |
316 | * Worst delay time when up and running is at 25 MHz => 120 ns. | |
317 | */ | |
318 | if (host->cclk < 25000000) | |
319 | udelay(30); | |
320 | else | |
321 | ndelay(120); | |
322 | } | |
323 | ||
7437cfa5 UH |
324 | /* |
325 | * This must be called with host->lock held | |
326 | */ | |
cd3ee8c5 | 327 | void mmci_write_clkreg(struct mmci_host *host, u32 clk) |
7437cfa5 UH |
328 | { |
329 | if (host->clk_reg != clk) { | |
330 | host->clk_reg = clk; | |
331 | writel(clk, host->base + MMCICLOCK); | |
332 | } | |
333 | } | |
334 | ||
335 | /* | |
336 | * This must be called with host->lock held | |
337 | */ | |
cd3ee8c5 | 338 | void mmci_write_pwrreg(struct mmci_host *host, u32 pwr) |
7437cfa5 UH |
339 | { |
340 | if (host->pwr_reg != pwr) { | |
341 | host->pwr_reg = pwr; | |
342 | writel(pwr, host->base + MMCIPOWER); | |
343 | } | |
344 | } | |
345 | ||
9cc639a2 UH |
346 | /* |
347 | * This must be called with host->lock held | |
348 | */ | |
349 | static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) | |
350 | { | |
49adc0ca LW |
351 | /* Keep busy mode in DPSM if enabled */ |
352 | datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; | |
01259620 | 353 | |
9cc639a2 UH |
354 | if (host->datactrl_reg != datactrl) { |
355 | host->datactrl_reg = datactrl; | |
356 | writel(datactrl, host->base + MMCIDATACTRL); | |
357 | } | |
358 | } | |
359 | ||
a6a6464a LW |
360 | /* |
361 | * This must be called with host->lock held | |
362 | */ | |
363 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
364 | { | |
4956e109 RV |
365 | struct variant_data *variant = host->variant; |
366 | u32 clk = variant->clkreg; | |
a6a6464a | 367 | |
c58a8509 UH |
368 | /* Make sure cclk reflects the current calculated clock */ |
369 | host->cclk = 0; | |
370 | ||
a6a6464a | 371 | if (desired) { |
3f4e6f7b SK |
372 | if (variant->explicit_mclk_control) { |
373 | host->cclk = host->mclk; | |
374 | } else if (desired >= host->mclk) { | |
991a86e1 | 375 | clk = MCI_CLK_BYPASS; |
399bc486 LW |
376 | if (variant->st_clkdiv) |
377 | clk |= MCI_ST_UX500_NEG_EDGE; | |
a6a6464a | 378 | host->cclk = host->mclk; |
b70a67f9 LW |
379 | } else if (variant->st_clkdiv) { |
380 | /* | |
381 | * DB8500 TRM says f = mclk / (clkdiv + 2) | |
382 | * => clkdiv = (mclk / f) - 2 | |
383 | * Round the divider up so we don't exceed the max | |
384 | * frequency | |
385 | */ | |
386 | clk = DIV_ROUND_UP(host->mclk, desired) - 2; | |
387 | if (clk >= 256) | |
388 | clk = 255; | |
389 | host->cclk = host->mclk / (clk + 2); | |
a6a6464a | 390 | } else { |
b70a67f9 LW |
391 | /* |
392 | * PL180 TRM says f = mclk / (2 * (clkdiv + 1)) | |
393 | * => clkdiv = mclk / (2 * f) - 1 | |
394 | */ | |
a6a6464a LW |
395 | clk = host->mclk / (2 * desired) - 1; |
396 | if (clk >= 256) | |
397 | clk = 255; | |
398 | host->cclk = host->mclk / (2 * (clk + 1)); | |
399 | } | |
4380c14f RV |
400 | |
401 | clk |= variant->clkreg_enable; | |
a6a6464a LW |
402 | clk |= MCI_CLK_ENABLE; |
403 | /* This hasn't proven to be worthwhile */ | |
404 | /* clk |= MCI_CLK_PWRSAVE; */ | |
405 | } | |
406 | ||
c58a8509 UH |
407 | /* Set actual clock for debug */ |
408 | host->mmc->actual_clock = host->cclk; | |
409 | ||
9e6c82cd | 410 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
411 | clk |= MCI_4BIT_BUS; |
412 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
e1412d85 | 413 | clk |= variant->clkreg_8bit_bus_enable; |
9e6c82cd | 414 | |
6dad6c95 SJ |
415 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
416 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) | |
e8740644 | 417 | clk |= variant->clkreg_neg_edge_enable; |
6dbb6ee0 | 418 | |
7437cfa5 | 419 | mmci_write_clkreg(host, clk); |
a6a6464a LW |
420 | } |
421 | ||
c3647fdc LB |
422 | void mmci_dma_release(struct mmci_host *host) |
423 | { | |
424 | if (host->ops && host->ops->dma_release) | |
425 | host->ops->dma_release(host); | |
426 | ||
427 | host->use_dma = false; | |
428 | } | |
429 | ||
430 | void mmci_dma_setup(struct mmci_host *host) | |
431 | { | |
432 | if (!host->ops || !host->ops->dma_setup) | |
433 | return; | |
434 | ||
435 | if (host->ops->dma_setup(host)) | |
436 | return; | |
437 | ||
a813f2a2 LB |
438 | /* initialize pre request cookie */ |
439 | host->next_cookie = 1; | |
440 | ||
c3647fdc LB |
441 | host->use_dma = true; |
442 | } | |
443 | ||
e0da1721 LB |
444 | /* |
445 | * Validate mmc prerequisites | |
446 | */ | |
447 | static int mmci_validate_data(struct mmci_host *host, | |
448 | struct mmc_data *data) | |
449 | { | |
450 | if (!data) | |
451 | return 0; | |
452 | ||
453 | if (!is_power_of_2(data->blksz)) { | |
454 | dev_err(mmc_dev(host->mmc), | |
455 | "unsupported block size (%d bytes)\n", data->blksz); | |
456 | return -EINVAL; | |
457 | } | |
458 | ||
459 | if (host->ops && host->ops->validate_data) | |
460 | return host->ops->validate_data(host, data); | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
47983510 LB |
465 | int mmci_prep_data(struct mmci_host *host, struct mmc_data *data, bool next) |
466 | { | |
467 | int err; | |
468 | ||
469 | if (!host->ops || !host->ops->prep_data) | |
470 | return 0; | |
471 | ||
472 | err = host->ops->prep_data(host, data, next); | |
473 | ||
474 | if (next && !err) | |
475 | data->host_cookie = ++host->next_cookie < 0 ? | |
476 | 1 : host->next_cookie; | |
477 | ||
478 | return err; | |
479 | } | |
480 | ||
481 | void mmci_unprep_data(struct mmci_host *host, struct mmc_data *data, | |
482 | int err) | |
483 | { | |
484 | if (host->ops && host->ops->unprep_data) | |
485 | host->ops->unprep_data(host, data, err); | |
486 | ||
487 | data->host_cookie = 0; | |
488 | } | |
489 | ||
02769968 LB |
490 | void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data) |
491 | { | |
492 | WARN_ON(data->host_cookie && data->host_cookie != host->next_cookie); | |
493 | ||
494 | if (host->ops && host->ops->get_next_data) | |
495 | host->ops->get_next_data(host, data); | |
496 | } | |
497 | ||
135ea30e LB |
498 | int mmci_dma_start(struct mmci_host *host, unsigned int datactrl) |
499 | { | |
500 | struct mmc_data *data = host->data; | |
501 | int ret; | |
502 | ||
503 | if (!host->use_dma) | |
504 | return -EINVAL; | |
505 | ||
506 | ret = mmci_prep_data(host, data, false); | |
507 | if (ret) | |
508 | return ret; | |
509 | ||
510 | if (!host->ops || !host->ops->dma_start) | |
511 | return -EINVAL; | |
512 | ||
513 | /* Okay, go for it. */ | |
514 | dev_vdbg(mmc_dev(host->mmc), | |
515 | "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n", | |
516 | data->sg_len, data->blksz, data->blocks, data->flags); | |
517 | ||
518 | host->ops->dma_start(host, &datactrl); | |
519 | ||
520 | /* Trigger the DMA transfer */ | |
521 | mmci_write_datactrlreg(host, datactrl); | |
522 | ||
523 | /* | |
524 | * Let the MMCI say when the data is ended and it's time | |
525 | * to fire next DMA request. When that happens, MMCI will | |
526 | * call mmci_data_end() | |
527 | */ | |
528 | writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK, | |
529 | host->base + MMCIMASK0); | |
530 | return 0; | |
531 | } | |
532 | ||
5a9f10c3 LB |
533 | void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data) |
534 | { | |
535 | if (!host->use_dma) | |
536 | return; | |
537 | ||
538 | if (host->ops && host->ops->dma_finalize) | |
539 | host->ops->dma_finalize(host, data); | |
540 | } | |
541 | ||
cfccc6ac LB |
542 | void mmci_dma_error(struct mmci_host *host) |
543 | { | |
544 | if (!host->use_dma) | |
545 | return; | |
546 | ||
547 | if (host->ops && host->ops->dma_error) | |
548 | host->ops->dma_error(host); | |
549 | } | |
550 | ||
1da177e4 LT |
551 | static void |
552 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
553 | { | |
554 | writel(0, host->base + MMCICOMMAND); | |
555 | ||
e47c222b RK |
556 | BUG_ON(host->data); |
557 | ||
1da177e4 LT |
558 | host->mrq = NULL; |
559 | host->cmd = NULL; | |
560 | ||
1da177e4 | 561 | mmc_request_done(host->mmc, mrq); |
1da177e4 LT |
562 | } |
563 | ||
2686b4b4 LW |
564 | static void mmci_set_mask1(struct mmci_host *host, unsigned int mask) |
565 | { | |
566 | void __iomem *base = host->base; | |
6ea9cdf3 | 567 | struct variant_data *variant = host->variant; |
2686b4b4 LW |
568 | |
569 | if (host->singleirq) { | |
570 | unsigned int mask0 = readl(base + MMCIMASK0); | |
571 | ||
59db5e2d | 572 | mask0 &= ~variant->irq_pio_mask; |
2686b4b4 LW |
573 | mask0 |= mask; |
574 | ||
575 | writel(mask0, base + MMCIMASK0); | |
576 | } | |
577 | ||
6ea9cdf3 PC |
578 | if (variant->mmcimask1) |
579 | writel(mask, base + MMCIMASK1); | |
580 | ||
581 | host->mask1_reg = mask; | |
2686b4b4 LW |
582 | } |
583 | ||
1da177e4 LT |
584 | static void mmci_stop_data(struct mmci_host *host) |
585 | { | |
9cc639a2 | 586 | mmci_write_datactrlreg(host, 0); |
2686b4b4 | 587 | mmci_set_mask1(host, 0); |
1da177e4 LT |
588 | host->data = NULL; |
589 | } | |
590 | ||
4ce1d6cb RV |
591 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
592 | { | |
593 | unsigned int flags = SG_MITER_ATOMIC; | |
594 | ||
595 | if (data->flags & MMC_DATA_READ) | |
596 | flags |= SG_MITER_TO_SG; | |
597 | else | |
598 | flags |= SG_MITER_FROM_SG; | |
599 | ||
600 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
601 | } | |
602 | ||
b3fb9d64 LB |
603 | static u32 mmci_get_dctrl_cfg(struct mmci_host *host) |
604 | { | |
605 | return MCI_DPSM_ENABLE | mmci_dctrl_blksz(host); | |
606 | } | |
607 | ||
608 | static u32 ux500v2_get_dctrl_cfg(struct mmci_host *host) | |
609 | { | |
610 | return MCI_DPSM_ENABLE | (host->data->blksz << 16); | |
611 | } | |
612 | ||
c8ebae37 RK |
613 | /* |
614 | * All the DMA operation mode stuff goes inside this ifdef. | |
615 | * This assumes that you have a generic DMA device interface, | |
616 | * no custom DMA interfaces are supported. | |
617 | */ | |
618 | #ifdef CONFIG_DMA_ENGINE | |
a813f2a2 LB |
619 | struct mmci_dmae_next { |
620 | struct dma_async_tx_descriptor *desc; | |
621 | struct dma_chan *chan; | |
622 | }; | |
623 | ||
624 | struct mmci_dmae_priv { | |
625 | struct dma_chan *cur; | |
626 | struct dma_chan *rx_channel; | |
627 | struct dma_chan *tx_channel; | |
628 | struct dma_async_tx_descriptor *desc_current; | |
629 | struct mmci_dmae_next next_data; | |
630 | }; | |
631 | ||
c3647fdc | 632 | int mmci_dmae_setup(struct mmci_host *host) |
c8ebae37 | 633 | { |
c8ebae37 | 634 | const char *rxname, *txname; |
a813f2a2 | 635 | struct mmci_dmae_priv *dmae; |
c8ebae37 | 636 | |
a813f2a2 LB |
637 | dmae = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dmae), GFP_KERNEL); |
638 | if (!dmae) | |
639 | return -ENOMEM; | |
c8ebae37 | 640 | |
a813f2a2 LB |
641 | host->dma_priv = dmae; |
642 | ||
643 | dmae->rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), | |
644 | "rx"); | |
645 | dmae->tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), | |
646 | "tx"); | |
58c7ccbf | 647 | |
1fd83f0e LJ |
648 | /* |
649 | * If only an RX channel is specified, the driver will | |
650 | * attempt to use it bidirectionally, however if it is | |
651 | * is specified but cannot be located, DMA will be disabled. | |
652 | */ | |
a813f2a2 LB |
653 | if (dmae->rx_channel && !dmae->tx_channel) |
654 | dmae->tx_channel = dmae->rx_channel; | |
1fd83f0e | 655 | |
a813f2a2 LB |
656 | if (dmae->rx_channel) |
657 | rxname = dma_chan_name(dmae->rx_channel); | |
c8ebae37 RK |
658 | else |
659 | rxname = "none"; | |
660 | ||
a813f2a2 LB |
661 | if (dmae->tx_channel) |
662 | txname = dma_chan_name(dmae->tx_channel); | |
c8ebae37 RK |
663 | else |
664 | txname = "none"; | |
665 | ||
666 | dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n", | |
667 | rxname, txname); | |
668 | ||
669 | /* | |
670 | * Limit the maximum segment size in any SG entry according to | |
671 | * the parameters of the DMA engine device. | |
672 | */ | |
a813f2a2 LB |
673 | if (dmae->tx_channel) { |
674 | struct device *dev = dmae->tx_channel->device->dev; | |
c8ebae37 RK |
675 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
676 | ||
677 | if (max_seg_size < host->mmc->max_seg_size) | |
678 | host->mmc->max_seg_size = max_seg_size; | |
679 | } | |
a813f2a2 LB |
680 | if (dmae->rx_channel) { |
681 | struct device *dev = dmae->rx_channel->device->dev; | |
c8ebae37 RK |
682 | unsigned int max_seg_size = dma_get_max_seg_size(dev); |
683 | ||
684 | if (max_seg_size < host->mmc->max_seg_size) | |
685 | host->mmc->max_seg_size = max_seg_size; | |
686 | } | |
9cb15142 | 687 | |
a813f2a2 | 688 | if (!dmae->tx_channel || !dmae->rx_channel) { |
c3647fdc LB |
689 | mmci_dmae_release(host); |
690 | return -EINVAL; | |
691 | } | |
692 | ||
693 | return 0; | |
c8ebae37 RK |
694 | } |
695 | ||
696 | /* | |
6e0ee714 | 697 | * This is used in or so inline it |
c8ebae37 RK |
698 | * so it can be discarded. |
699 | */ | |
c3647fdc | 700 | void mmci_dmae_release(struct mmci_host *host) |
c8ebae37 | 701 | { |
a813f2a2 LB |
702 | struct mmci_dmae_priv *dmae = host->dma_priv; |
703 | ||
704 | if (dmae->rx_channel) | |
705 | dma_release_channel(dmae->rx_channel); | |
706 | if (dmae->tx_channel) | |
707 | dma_release_channel(dmae->tx_channel); | |
708 | dmae->rx_channel = dmae->tx_channel = NULL; | |
c8ebae37 RK |
709 | } |
710 | ||
711 | static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data) | |
712 | { | |
a813f2a2 | 713 | struct mmci_dmae_priv *dmae = host->dma_priv; |
653a761e | 714 | struct dma_chan *chan; |
653a761e | 715 | |
feeef096 | 716 | if (data->flags & MMC_DATA_READ) |
a813f2a2 | 717 | chan = dmae->rx_channel; |
feeef096 | 718 | else |
a813f2a2 | 719 | chan = dmae->tx_channel; |
653a761e | 720 | |
feeef096 HK |
721 | dma_unmap_sg(chan->device->dev, data->sg, data->sg_len, |
722 | mmc_get_dma_dir(data)); | |
653a761e UH |
723 | } |
724 | ||
cfccc6ac | 725 | void mmci_dmae_error(struct mmci_host *host) |
7b2a6d51 | 726 | { |
a813f2a2 LB |
727 | struct mmci_dmae_priv *dmae = host->dma_priv; |
728 | ||
cfccc6ac | 729 | if (!dma_inprogress(host)) |
cdea1947 LB |
730 | return; |
731 | ||
7b2a6d51 | 732 | dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n"); |
a813f2a2 | 733 | dmaengine_terminate_all(dmae->cur); |
7b2a6d51 | 734 | host->dma_in_progress = false; |
a813f2a2 LB |
735 | dmae->cur = NULL; |
736 | dmae->desc_current = NULL; | |
7b2a6d51 LB |
737 | host->data->host_cookie = 0; |
738 | ||
739 | mmci_dma_unmap(host, host->data); | |
740 | } | |
741 | ||
5a9f10c3 | 742 | void mmci_dmae_finalize(struct mmci_host *host, struct mmc_data *data) |
653a761e | 743 | { |
a813f2a2 | 744 | struct mmci_dmae_priv *dmae = host->dma_priv; |
c8ebae37 RK |
745 | u32 status; |
746 | int i; | |
747 | ||
5a9f10c3 | 748 | if (!dma_inprogress(host)) |
cdea1947 LB |
749 | return; |
750 | ||
c8ebae37 RK |
751 | /* Wait up to 1ms for the DMA to complete */ |
752 | for (i = 0; ; i++) { | |
753 | status = readl(host->base + MMCISTATUS); | |
754 | if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100) | |
755 | break; | |
756 | udelay(10); | |
757 | } | |
758 | ||
759 | /* | |
760 | * Check to see whether we still have some data left in the FIFO - | |
761 | * this catches DMA controllers which are unable to monitor the | |
762 | * DMALBREQ and DMALSREQ signals while allowing us to DMA to non- | |
763 | * contiguous buffers. On TX, we'll get a FIFO underrun error. | |
764 | */ | |
765 | if (status & MCI_RXDATAAVLBLMASK) { | |
cfccc6ac | 766 | mmci_dma_error(host); |
c8ebae37 RK |
767 | if (!data->error) |
768 | data->error = -EIO; | |
7b2a6d51 | 769 | } else if (!data->host_cookie) { |
653a761e | 770 | mmci_dma_unmap(host, data); |
7b2a6d51 | 771 | } |
c8ebae37 RK |
772 | |
773 | /* | |
774 | * Use of DMA with scatter-gather is impossible. | |
775 | * Give up with DMA and switch back to PIO mode. | |
776 | */ | |
777 | if (status & MCI_RXDATAAVLBLMASK) { | |
778 | dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n"); | |
779 | mmci_dma_release(host); | |
780 | } | |
c8ebae37 | 781 | |
e13934bd | 782 | host->dma_in_progress = false; |
a813f2a2 LB |
783 | dmae->cur = NULL; |
784 | dmae->desc_current = NULL; | |
c8ebae37 RK |
785 | } |
786 | ||
653a761e | 787 | /* prepares DMA channel and DMA descriptor, returns non-zero on failure */ |
47983510 | 788 | static int _mmci_dmae_prep_data(struct mmci_host *host, struct mmc_data *data, |
653a761e UH |
789 | struct dma_chan **dma_chan, |
790 | struct dma_async_tx_descriptor **dma_desc) | |
c8ebae37 | 791 | { |
a813f2a2 | 792 | struct mmci_dmae_priv *dmae = host->dma_priv; |
c8ebae37 RK |
793 | struct variant_data *variant = host->variant; |
794 | struct dma_slave_config conf = { | |
795 | .src_addr = host->phybase + MMCIFIFO, | |
796 | .dst_addr = host->phybase + MMCIFIFO, | |
797 | .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
798 | .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, | |
799 | .src_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
800 | .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */ | |
258aea76 | 801 | .device_fc = false, |
c8ebae37 | 802 | }; |
c8ebae37 RK |
803 | struct dma_chan *chan; |
804 | struct dma_device *device; | |
805 | struct dma_async_tx_descriptor *desc; | |
806 | int nr_sg; | |
9cb15142 | 807 | unsigned long flags = DMA_CTRL_ACK; |
c8ebae37 | 808 | |
c8ebae37 | 809 | if (data->flags & MMC_DATA_READ) { |
05f5799c | 810 | conf.direction = DMA_DEV_TO_MEM; |
a813f2a2 | 811 | chan = dmae->rx_channel; |
c8ebae37 | 812 | } else { |
05f5799c | 813 | conf.direction = DMA_MEM_TO_DEV; |
a813f2a2 | 814 | chan = dmae->tx_channel; |
c8ebae37 RK |
815 | } |
816 | ||
817 | /* If there's no DMA channel, fall back to PIO */ | |
818 | if (!chan) | |
819 | return -EINVAL; | |
820 | ||
821 | /* If less than or equal to the fifo size, don't bother with DMA */ | |
58c7ccbf | 822 | if (data->blksz * data->blocks <= variant->fifosize) |
c8ebae37 RK |
823 | return -EINVAL; |
824 | ||
825 | device = chan->device; | |
feeef096 HK |
826 | nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len, |
827 | mmc_get_dma_dir(data)); | |
c8ebae37 RK |
828 | if (nr_sg == 0) |
829 | return -EINVAL; | |
830 | ||
9cb15142 SK |
831 | if (host->variant->qcom_dml) |
832 | flags |= DMA_PREP_INTERRUPT; | |
833 | ||
c8ebae37 | 834 | dmaengine_slave_config(chan, &conf); |
16052827 | 835 | desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg, |
9cb15142 | 836 | conf.direction, flags); |
c8ebae37 RK |
837 | if (!desc) |
838 | goto unmap_exit; | |
839 | ||
653a761e UH |
840 | *dma_chan = chan; |
841 | *dma_desc = desc; | |
58c7ccbf PF |
842 | |
843 | return 0; | |
c8ebae37 | 844 | |
58c7ccbf | 845 | unmap_exit: |
feeef096 HK |
846 | dma_unmap_sg(device->dev, data->sg, data->sg_len, |
847 | mmc_get_dma_dir(data)); | |
58c7ccbf PF |
848 | return -ENOMEM; |
849 | } | |
850 | ||
47983510 LB |
851 | int mmci_dmae_prep_data(struct mmci_host *host, |
852 | struct mmc_data *data, | |
853 | bool next) | |
653a761e | 854 | { |
a813f2a2 | 855 | struct mmci_dmae_priv *dmae = host->dma_priv; |
ad7b8918 | 856 | struct mmci_dmae_next *nd = &dmae->next_data; |
a813f2a2 | 857 | |
47983510 LB |
858 | if (!host->use_dma) |
859 | return -EINVAL; | |
860 | ||
ad7b8918 | 861 | if (next) |
47983510 | 862 | return _mmci_dmae_prep_data(host, data, &nd->chan, &nd->desc); |
653a761e | 863 | /* Check if next job is already prepared. */ |
a813f2a2 | 864 | if (dmae->cur && dmae->desc_current) |
653a761e UH |
865 | return 0; |
866 | ||
867 | /* No job were prepared thus do it now. */ | |
47983510 | 868 | return _mmci_dmae_prep_data(host, data, &dmae->cur, |
a813f2a2 | 869 | &dmae->desc_current); |
653a761e UH |
870 | } |
871 | ||
135ea30e | 872 | int mmci_dmae_start(struct mmci_host *host, unsigned int *datactrl) |
58c7ccbf | 873 | { |
a813f2a2 | 874 | struct mmci_dmae_priv *dmae = host->dma_priv; |
58c7ccbf | 875 | |
e13934bd | 876 | host->dma_in_progress = true; |
a813f2a2 LB |
877 | dmaengine_submit(dmae->desc_current); |
878 | dma_async_issue_pending(dmae->cur); | |
c8ebae37 | 879 | |
135ea30e | 880 | *datactrl |= MCI_DPSM_DMAENABLE; |
c8ebae37 | 881 | |
c8ebae37 | 882 | return 0; |
58c7ccbf | 883 | } |
c8ebae37 | 884 | |
02769968 | 885 | void mmci_dmae_get_next_data(struct mmci_host *host, struct mmc_data *data) |
58c7ccbf | 886 | { |
a813f2a2 LB |
887 | struct mmci_dmae_priv *dmae = host->dma_priv; |
888 | struct mmci_dmae_next *next = &dmae->next_data; | |
58c7ccbf | 889 | |
c3647fdc LB |
890 | if (!host->use_dma) |
891 | return; | |
892 | ||
a813f2a2 | 893 | WARN_ON(!data->host_cookie && (next->desc || next->chan)); |
58c7ccbf | 894 | |
a813f2a2 LB |
895 | dmae->desc_current = next->desc; |
896 | dmae->cur = next->chan; | |
897 | next->desc = NULL; | |
898 | next->chan = NULL; | |
c8ebae37 | 899 | } |
58c7ccbf | 900 | |
47983510 LB |
901 | void mmci_dmae_unprep_data(struct mmci_host *host, |
902 | struct mmc_data *data, int err) | |
58c7ccbf | 903 | |
58c7ccbf | 904 | { |
a813f2a2 | 905 | struct mmci_dmae_priv *dmae = host->dma_priv; |
58c7ccbf | 906 | |
47983510 | 907 | if (!host->use_dma) |
58c7ccbf PF |
908 | return; |
909 | ||
653a761e | 910 | mmci_dma_unmap(host, data); |
58c7ccbf | 911 | |
653a761e | 912 | if (err) { |
a813f2a2 | 913 | struct mmci_dmae_next *next = &dmae->next_data; |
653a761e UH |
914 | struct dma_chan *chan; |
915 | if (data->flags & MMC_DATA_READ) | |
a813f2a2 | 916 | chan = dmae->rx_channel; |
653a761e | 917 | else |
a813f2a2 | 918 | chan = dmae->tx_channel; |
653a761e | 919 | dmaengine_terminate_all(chan); |
58c7ccbf | 920 | |
a813f2a2 LB |
921 | if (dmae->desc_current == next->desc) |
922 | dmae->desc_current = NULL; | |
b5c16a60 | 923 | |
a813f2a2 | 924 | if (dmae->cur == next->chan) { |
e13934bd | 925 | host->dma_in_progress = false; |
a813f2a2 | 926 | dmae->cur = NULL; |
e13934bd | 927 | } |
b5c16a60 | 928 | |
a813f2a2 LB |
929 | next->desc = NULL; |
930 | next->chan = NULL; | |
58c7ccbf PF |
931 | } |
932 | } | |
933 | ||
c3647fdc | 934 | static struct mmci_host_ops mmci_variant_ops = { |
47983510 LB |
935 | .prep_data = mmci_dmae_prep_data, |
936 | .unprep_data = mmci_dmae_unprep_data, | |
b3fb9d64 | 937 | .get_datactrl_cfg = mmci_get_dctrl_cfg, |
02769968 | 938 | .get_next_data = mmci_dmae_get_next_data, |
c3647fdc LB |
939 | .dma_setup = mmci_dmae_setup, |
940 | .dma_release = mmci_dmae_release, | |
135ea30e | 941 | .dma_start = mmci_dmae_start, |
5a9f10c3 | 942 | .dma_finalize = mmci_dmae_finalize, |
cfccc6ac | 943 | .dma_error = mmci_dmae_error, |
c3647fdc | 944 | }; |
b3fb9d64 LB |
945 | #else |
946 | static struct mmci_host_ops mmci_variant_ops = { | |
947 | .get_datactrl_cfg = mmci_get_dctrl_cfg, | |
948 | }; | |
949 | #endif | |
c3647fdc LB |
950 | |
951 | void mmci_variant_init(struct mmci_host *host) | |
952 | { | |
953 | host->ops = &mmci_variant_ops; | |
954 | } | |
b3fb9d64 LB |
955 | |
956 | void ux500v2_variant_init(struct mmci_host *host) | |
957 | { | |
958 | host->ops = &mmci_variant_ops; | |
959 | host->ops->get_datactrl_cfg = ux500v2_get_dctrl_cfg; | |
960 | } | |
c8ebae37 | 961 | |
47983510 LB |
962 | static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq) |
963 | { | |
964 | struct mmci_host *host = mmc_priv(mmc); | |
965 | struct mmc_data *data = mrq->data; | |
966 | ||
967 | if (!data) | |
968 | return; | |
969 | ||
970 | WARN_ON(data->host_cookie); | |
971 | ||
972 | if (mmci_validate_data(host, data)) | |
973 | return; | |
974 | ||
975 | mmci_prep_data(host, data, true); | |
976 | } | |
977 | ||
978 | static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq, | |
979 | int err) | |
980 | { | |
981 | struct mmci_host *host = mmc_priv(mmc); | |
982 | struct mmc_data *data = mrq->data; | |
983 | ||
984 | if (!data || !data->host_cookie) | |
985 | return; | |
986 | ||
987 | mmci_unprep_data(host, data, err); | |
988 | } | |
989 | ||
1da177e4 LT |
990 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
991 | { | |
8301bb68 | 992 | struct variant_data *variant = host->variant; |
1da177e4 | 993 | unsigned int datactrl, timeout, irqmask; |
7b09cdac | 994 | unsigned long long clks; |
1da177e4 LT |
995 | void __iomem *base; |
996 | ||
64de0289 LW |
997 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
998 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
999 | |
1000 | host->data = data; | |
528320db | 1001 | host->size = data->blksz * data->blocks; |
51d4375d | 1002 | data->bytes_xfered = 0; |
1da177e4 | 1003 | |
7b09cdac | 1004 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
c4a35769 | 1005 | do_div(clks, NSEC_PER_SEC); |
7b09cdac RK |
1006 | |
1007 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
1008 | |
1009 | base = host->base; | |
1010 | writel(timeout, base + MMCIDATATIMER); | |
1011 | writel(host->size, base + MMCIDATALENGTH); | |
1012 | ||
41ed65e7 LB |
1013 | datactrl = host->ops->get_datactrl_cfg(host); |
1014 | datactrl |= host->data->flags & MMC_DATA_READ ? MCI_DPSM_DIRECTION : 0; | |
c8ebae37 | 1015 | |
c7354133 SK |
1016 | if (host->mmc->card && mmc_card_sdio(host->mmc->card)) { |
1017 | u32 clk; | |
7258db7e | 1018 | |
c7354133 SK |
1019 | datactrl |= variant->datactrl_mask_sdio; |
1020 | ||
1021 | /* | |
1022 | * The ST Micro variant for SDIO small write transfers | |
1023 | * needs to have clock H/W flow control disabled, | |
1024 | * otherwise the transfer will not start. The threshold | |
1025 | * depends on the rate of MCLK. | |
1026 | */ | |
1027 | if (variant->st_sdio && data->flags & MMC_DATA_WRITE && | |
1028 | (host->size < 8 || | |
1029 | (host->size <= 8 && host->mclk > 50000000))) | |
1030 | clk = host->clk_reg & ~variant->clkreg_enable; | |
1031 | else | |
1032 | clk = host->clk_reg | variant->clkreg_enable; | |
1033 | ||
1034 | mmci_write_clkreg(host, clk); | |
1035 | } | |
06c1a121 | 1036 | |
6dad6c95 SJ |
1037 | if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || |
1038 | host->mmc->ios.timing == MMC_TIMING_MMC_DDR52) | |
e17dca2b | 1039 | datactrl |= variant->datactrl_mask_ddrmode; |
6dbb6ee0 | 1040 | |
c8ebae37 RK |
1041 | /* |
1042 | * Attempt to use DMA operation mode, if this | |
1043 | * should fail, fall back to PIO mode | |
1044 | */ | |
135ea30e | 1045 | if (!mmci_dma_start(host, datactrl)) |
c8ebae37 RK |
1046 | return; |
1047 | ||
1048 | /* IRQ mode, map the SG list for CPU reading/writing */ | |
1049 | mmci_init_sg(host, data); | |
1050 | ||
1051 | if (data->flags & MMC_DATA_READ) { | |
1da177e4 | 1052 | irqmask = MCI_RXFIFOHALFFULLMASK; |
0425a142 RK |
1053 | |
1054 | /* | |
c4d877c1 RK |
1055 | * If we have less than the fifo 'half-full' threshold to |
1056 | * transfer, trigger a PIO interrupt as soon as any data | |
1057 | * is available. | |
0425a142 | 1058 | */ |
c4d877c1 | 1059 | if (host->size < variant->fifohalfsize) |
0425a142 | 1060 | irqmask |= MCI_RXDATAAVLBLMASK; |
1da177e4 LT |
1061 | } else { |
1062 | /* | |
1063 | * We don't actually need to include "FIFO empty" here | |
1064 | * since its implicit in "FIFO half empty". | |
1065 | */ | |
1066 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
1067 | } | |
1068 | ||
9cc639a2 | 1069 | mmci_write_datactrlreg(host, datactrl); |
1da177e4 | 1070 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); |
2686b4b4 | 1071 | mmci_set_mask1(host, irqmask); |
1da177e4 LT |
1072 | } |
1073 | ||
1074 | static void | |
1075 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
1076 | { | |
1077 | void __iomem *base = host->base; | |
1078 | ||
64de0289 | 1079 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
1080 | cmd->opcode, cmd->arg, cmd->flags); |
1081 | ||
0f244804 | 1082 | if (readl(base + MMCICOMMAND) & host->variant->cmdreg_cpsm_enable) { |
1da177e4 | 1083 | writel(0, base + MMCICOMMAND); |
6adb2a80 | 1084 | mmci_reg_delay(host); |
1da177e4 LT |
1085 | } |
1086 | ||
c8073e52 LB |
1087 | if (host->variant->cmdreg_stop && |
1088 | cmd->opcode == MMC_STOP_TRANSMISSION) | |
1089 | c |= host->variant->cmdreg_stop; | |
1090 | ||
0f244804 | 1091 | c |= cmd->opcode | host->variant->cmdreg_cpsm_enable; |
e9225176 RK |
1092 | if (cmd->flags & MMC_RSP_PRESENT) { |
1093 | if (cmd->flags & MMC_RSP_136) | |
0f244804 LB |
1094 | c |= host->variant->cmdreg_lrsp_crc; |
1095 | else if (cmd->flags & MMC_RSP_CRC) | |
1096 | c |= host->variant->cmdreg_srsp_crc; | |
1097 | else | |
1098 | c |= host->variant->cmdreg_srsp; | |
1da177e4 LT |
1099 | } |
1100 | if (/*interrupt*/0) | |
1101 | c |= MCI_CPSM_INTERRUPT; | |
1102 | ||
ae7b0061 SK |
1103 | if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) |
1104 | c |= host->variant->data_cmd_enable; | |
1105 | ||
1da177e4 LT |
1106 | host->cmd = cmd; |
1107 | ||
1108 | writel(cmd->arg, base + MMCIARGUMENT); | |
1109 | writel(c, base + MMCICOMMAND); | |
1110 | } | |
1111 | ||
e9968c6f UH |
1112 | static void mmci_stop_command(struct mmci_host *host) |
1113 | { | |
1114 | host->stop_abort.error = 0; | |
1115 | mmci_start_command(host, &host->stop_abort, 0); | |
1116 | } | |
1117 | ||
1da177e4 LT |
1118 | static void |
1119 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
1120 | unsigned int status) | |
1121 | { | |
daf9713c LB |
1122 | unsigned int status_err; |
1123 | ||
1cb9da50 UH |
1124 | /* Make sure we have data to handle */ |
1125 | if (!data) | |
1126 | return; | |
1127 | ||
f20f8f21 | 1128 | /* First check for errors */ |
daf9713c LB |
1129 | status_err = status & (host->variant->start_err | |
1130 | MCI_DATACRCFAIL | MCI_DATATIMEOUT | | |
1131 | MCI_TXUNDERRUN | MCI_RXOVERRUN); | |
1132 | ||
1133 | if (status_err) { | |
8cb28155 | 1134 | u32 remain, success; |
f20f8f21 | 1135 | |
c8ebae37 | 1136 | /* Terminate the DMA transfer */ |
cfccc6ac | 1137 | mmci_dma_error(host); |
e9c091b4 RK |
1138 | |
1139 | /* | |
c8afc9d5 RK |
1140 | * Calculate how far we are into the transfer. Note that |
1141 | * the data counter gives the number of bytes transferred | |
1142 | * on the MMC bus, not on the host side. On reads, this | |
1143 | * can be as much as a FIFO-worth of data ahead. This | |
1144 | * matters for FIFO overruns only. | |
e9c091b4 | 1145 | */ |
b79220b3 LB |
1146 | if (!host->variant->datacnt_useless) { |
1147 | remain = readl(host->base + MMCIDATACNT); | |
1148 | success = data->blksz * data->blocks - remain; | |
1149 | } else { | |
1150 | success = 0; | |
1151 | } | |
8cb28155 | 1152 | |
c8afc9d5 | 1153 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n", |
daf9713c LB |
1154 | status_err, success); |
1155 | if (status_err & MCI_DATACRCFAIL) { | |
8cb28155 | 1156 | /* Last block was not successful */ |
c8afc9d5 | 1157 | success -= 1; |
17b0429d | 1158 | data->error = -EILSEQ; |
daf9713c | 1159 | } else if (status_err & MCI_DATATIMEOUT) { |
17b0429d | 1160 | data->error = -ETIMEDOUT; |
daf9713c | 1161 | } else if (status_err & MCI_STARTBITERR) { |
757df746 | 1162 | data->error = -ECOMM; |
daf9713c | 1163 | } else if (status_err & MCI_TXUNDERRUN) { |
c8afc9d5 | 1164 | data->error = -EIO; |
daf9713c | 1165 | } else if (status_err & MCI_RXOVERRUN) { |
c8afc9d5 RK |
1166 | if (success > host->variant->fifosize) |
1167 | success -= host->variant->fifosize; | |
1168 | else | |
1169 | success = 0; | |
17b0429d | 1170 | data->error = -EIO; |
4ce1d6cb | 1171 | } |
51d4375d | 1172 | data->bytes_xfered = round_down(success, data->blksz); |
1da177e4 | 1173 | } |
f20f8f21 | 1174 | |
8cb28155 LW |
1175 | if (status & MCI_DATABLOCKEND) |
1176 | dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n"); | |
f20f8f21 | 1177 | |
ccff9b51 | 1178 | if (status & MCI_DATAEND || data->error) { |
cdea1947 LB |
1179 | mmci_dma_finalize(host, data); |
1180 | ||
1da177e4 LT |
1181 | mmci_stop_data(host); |
1182 | ||
8cb28155 LW |
1183 | if (!data->error) |
1184 | /* The error clause is handled above, success! */ | |
51d4375d | 1185 | data->bytes_xfered = data->blksz * data->blocks; |
f20f8f21 | 1186 | |
e9968c6f UH |
1187 | if (!data->stop) { |
1188 | if (host->variant->cmdreg_stop && data->error) | |
1189 | mmci_stop_command(host); | |
1190 | else | |
1191 | mmci_request_end(host, data->mrq); | |
1192 | } else if (host->mrq->sbc && !data->error) { | |
1da177e4 | 1193 | mmci_request_end(host, data->mrq); |
e9968c6f | 1194 | } else { |
1da177e4 | 1195 | mmci_start_command(host, data->stop, 0); |
e9968c6f | 1196 | } |
1da177e4 LT |
1197 | } |
1198 | } | |
1199 | ||
1200 | static void | |
1201 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
1202 | unsigned int status) | |
1203 | { | |
1204 | void __iomem *base = host->base; | |
812513c7 | 1205 | bool sbc, busy_resp; |
ad82bfea UH |
1206 | |
1207 | if (!cmd) | |
1208 | return; | |
1209 | ||
1210 | sbc = (cmd == host->mrq->sbc); | |
812513c7 | 1211 | busy_resp = !!(cmd->flags & MMC_RSP_BUSY); |
ad82bfea | 1212 | |
49adc0ca LW |
1213 | /* |
1214 | * We need to be one of these interrupts to be considered worth | |
1215 | * handling. Note that we tag on any latent IRQs postponed | |
1216 | * due to waiting for busy status. | |
1217 | */ | |
1218 | if (!((status|host->busy_status) & | |
1219 | (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND))) | |
ad82bfea | 1220 | return; |
8d94b54d | 1221 | |
49adc0ca LW |
1222 | /* |
1223 | * ST Micro variant: handle busy detection. | |
1224 | */ | |
812513c7 | 1225 | if (busy_resp && host->variant->busy_detect) { |
8d94b54d | 1226 | |
49adc0ca LW |
1227 | /* We are busy with a command, return */ |
1228 | if (host->busy_status && | |
1229 | (status & host->variant->busy_detect_flag)) | |
1230 | return; | |
1231 | ||
1232 | /* | |
1233 | * We were not busy, but we now got a busy response on | |
1234 | * something that was not an error, and we double-check | |
1235 | * that the special busy status bit is still set before | |
1236 | * proceeding. | |
1237 | */ | |
812513c7 | 1238 | if (!host->busy_status && |
49adc0ca LW |
1239 | !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) && |
1240 | (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) { | |
5cad24d8 JNG |
1241 | |
1242 | /* Clear the busy start IRQ */ | |
1243 | writel(host->variant->busy_detect_mask, | |
1244 | host->base + MMCICLEAR); | |
1245 | ||
1246 | /* Unmask the busy end IRQ */ | |
49adc0ca LW |
1247 | writel(readl(base + MMCIMASK0) | |
1248 | host->variant->busy_detect_mask, | |
1249 | base + MMCIMASK0); | |
1250 | /* | |
1251 | * Now cache the last response status code (until | |
1252 | * the busy bit goes low), and return. | |
1253 | */ | |
1254 | host->busy_status = | |
1255 | status & (MCI_CMDSENT|MCI_CMDRESPEND); | |
1256 | return; | |
1257 | } | |
8d94b54d | 1258 | |
49adc0ca LW |
1259 | /* |
1260 | * At this point we are not busy with a command, we have | |
5cad24d8 JNG |
1261 | * not received a new busy request, clear and mask the busy |
1262 | * end IRQ and fall through to process the IRQ. | |
49adc0ca LW |
1263 | */ |
1264 | if (host->busy_status) { | |
5cad24d8 JNG |
1265 | |
1266 | writel(host->variant->busy_detect_mask, | |
1267 | host->base + MMCICLEAR); | |
1268 | ||
49adc0ca LW |
1269 | writel(readl(base + MMCIMASK0) & |
1270 | ~host->variant->busy_detect_mask, | |
1271 | base + MMCIMASK0); | |
1272 | host->busy_status = 0; | |
1273 | } | |
8d94b54d | 1274 | } |
1da177e4 LT |
1275 | |
1276 | host->cmd = NULL; | |
1277 | ||
1da177e4 | 1278 | if (status & MCI_CMDTIMEOUT) { |
17b0429d | 1279 | cmd->error = -ETIMEDOUT; |
1da177e4 | 1280 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 1281 | cmd->error = -EILSEQ; |
9047b435 RKAL |
1282 | } else { |
1283 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
1284 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
1285 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
1286 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
1da177e4 LT |
1287 | } |
1288 | ||
024629c6 | 1289 | if ((!sbc && !cmd->data) || cmd->error) { |
3b6e3c73 UH |
1290 | if (host->data) { |
1291 | /* Terminate the DMA transfer */ | |
cfccc6ac | 1292 | mmci_dma_error(host); |
7b2a6d51 | 1293 | |
e47c222b | 1294 | mmci_stop_data(host); |
e9968c6f UH |
1295 | if (host->variant->cmdreg_stop && cmd->error) { |
1296 | mmci_stop_command(host); | |
1297 | return; | |
1298 | } | |
3b6e3c73 | 1299 | } |
024629c6 UH |
1300 | mmci_request_end(host, host->mrq); |
1301 | } else if (sbc) { | |
1302 | mmci_start_command(host, host->mrq->cmd, 0); | |
d2141547 LB |
1303 | } else if (!host->variant->datactrl_first && |
1304 | !(cmd->data->flags & MMC_DATA_READ)) { | |
1da177e4 LT |
1305 | mmci_start_data(host, cmd->data); |
1306 | } | |
1307 | } | |
1308 | ||
9c34b73d SK |
1309 | static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain) |
1310 | { | |
1311 | return remain - (readl(host->base + MMCIFIFOCNT) << 2); | |
1312 | } | |
1313 | ||
1314 | static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r) | |
1315 | { | |
1316 | /* | |
1317 | * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses | |
1318 | * from the fifo range should be used | |
1319 | */ | |
1320 | if (status & MCI_RXFIFOHALFFULL) | |
1321 | return host->variant->fifohalfsize; | |
1322 | else if (status & MCI_RXDATAAVLBL) | |
1323 | return 4; | |
1324 | ||
1325 | return 0; | |
1326 | } | |
1327 | ||
1da177e4 LT |
1328 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) |
1329 | { | |
1330 | void __iomem *base = host->base; | |
1331 | char *ptr = buffer; | |
9c34b73d | 1332 | u32 status = readl(host->base + MMCISTATUS); |
26eed9a5 | 1333 | int host_remain = host->size; |
1da177e4 LT |
1334 | |
1335 | do { | |
9c34b73d | 1336 | int count = host->get_rx_fifocnt(host, status, host_remain); |
1da177e4 LT |
1337 | |
1338 | if (count > remain) | |
1339 | count = remain; | |
1340 | ||
1341 | if (count <= 0) | |
1342 | break; | |
1343 | ||
393e5e24 UH |
1344 | /* |
1345 | * SDIO especially may want to send something that is | |
1346 | * not divisible by 4 (as opposed to card sectors | |
1347 | * etc). Therefore make sure to always read the last bytes | |
1348 | * while only doing full 32-bit reads towards the FIFO. | |
1349 | */ | |
1350 | if (unlikely(count & 0x3)) { | |
1351 | if (count < 4) { | |
1352 | unsigned char buf[4]; | |
4b85da08 | 1353 | ioread32_rep(base + MMCIFIFO, buf, 1); |
393e5e24 UH |
1354 | memcpy(ptr, buf, count); |
1355 | } else { | |
4b85da08 | 1356 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
393e5e24 UH |
1357 | count &= ~0x3; |
1358 | } | |
1359 | } else { | |
4b85da08 | 1360 | ioread32_rep(base + MMCIFIFO, ptr, count >> 2); |
393e5e24 | 1361 | } |
1da177e4 LT |
1362 | |
1363 | ptr += count; | |
1364 | remain -= count; | |
26eed9a5 | 1365 | host_remain -= count; |
1da177e4 LT |
1366 | |
1367 | if (remain == 0) | |
1368 | break; | |
1369 | ||
1370 | status = readl(base + MMCISTATUS); | |
1371 | } while (status & MCI_RXDATAAVLBL); | |
1372 | ||
1373 | return ptr - buffer; | |
1374 | } | |
1375 | ||
1376 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
1377 | { | |
8301bb68 | 1378 | struct variant_data *variant = host->variant; |
1da177e4 LT |
1379 | void __iomem *base = host->base; |
1380 | char *ptr = buffer; | |
1381 | ||
1382 | do { | |
1383 | unsigned int count, maxcnt; | |
1384 | ||
8301bb68 RV |
1385 | maxcnt = status & MCI_TXFIFOEMPTY ? |
1386 | variant->fifosize : variant->fifohalfsize; | |
1da177e4 LT |
1387 | count = min(remain, maxcnt); |
1388 | ||
34177802 LW |
1389 | /* |
1390 | * SDIO especially may want to send something that is | |
1391 | * not divisible by 4 (as opposed to card sectors | |
1392 | * etc), and the FIFO only accept full 32-bit writes. | |
1393 | * So compensate by adding +3 on the count, a single | |
1394 | * byte become a 32bit write, 7 bytes will be two | |
1395 | * 32bit writes etc. | |
1396 | */ | |
4b85da08 | 1397 | iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2); |
1da177e4 LT |
1398 | |
1399 | ptr += count; | |
1400 | remain -= count; | |
1401 | ||
1402 | if (remain == 0) | |
1403 | break; | |
1404 | ||
1405 | status = readl(base + MMCISTATUS); | |
1406 | } while (status & MCI_TXFIFOHALFEMPTY); | |
1407 | ||
1408 | return ptr - buffer; | |
1409 | } | |
1410 | ||
1411 | /* | |
1412 | * PIO data transfer IRQ handler. | |
1413 | */ | |
7d12e780 | 1414 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
1415 | { |
1416 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 1417 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
8301bb68 | 1418 | struct variant_data *variant = host->variant; |
1da177e4 LT |
1419 | void __iomem *base = host->base; |
1420 | u32 status; | |
1421 | ||
1422 | status = readl(base + MMCISTATUS); | |
1423 | ||
64de0289 | 1424 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 LT |
1425 | |
1426 | do { | |
1da177e4 LT |
1427 | unsigned int remain, len; |
1428 | char *buffer; | |
1429 | ||
1430 | /* | |
1431 | * For write, we only need to test the half-empty flag | |
1432 | * here - if the FIFO is completely empty, then by | |
1433 | * definition it is more than half empty. | |
1434 | * | |
1435 | * For read, check for data available. | |
1436 | */ | |
1437 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
1438 | break; | |
1439 | ||
4ce1d6cb RV |
1440 | if (!sg_miter_next(sg_miter)) |
1441 | break; | |
1442 | ||
1443 | buffer = sg_miter->addr; | |
1444 | remain = sg_miter->length; | |
1da177e4 LT |
1445 | |
1446 | len = 0; | |
1447 | if (status & MCI_RXACTIVE) | |
1448 | len = mmci_pio_read(host, buffer, remain); | |
1449 | if (status & MCI_TXACTIVE) | |
1450 | len = mmci_pio_write(host, buffer, remain, status); | |
1451 | ||
4ce1d6cb | 1452 | sg_miter->consumed = len; |
1da177e4 | 1453 | |
1da177e4 LT |
1454 | host->size -= len; |
1455 | remain -= len; | |
1456 | ||
1457 | if (remain) | |
1458 | break; | |
1459 | ||
1da177e4 LT |
1460 | status = readl(base + MMCISTATUS); |
1461 | } while (1); | |
1462 | ||
4ce1d6cb RV |
1463 | sg_miter_stop(sg_miter); |
1464 | ||
1da177e4 | 1465 | /* |
c4d877c1 RK |
1466 | * If we have less than the fifo 'half-full' threshold to transfer, |
1467 | * trigger a PIO interrupt as soon as any data is available. | |
1da177e4 | 1468 | */ |
c4d877c1 | 1469 | if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize) |
2686b4b4 | 1470 | mmci_set_mask1(host, MCI_RXDATAAVLBLMASK); |
1da177e4 LT |
1471 | |
1472 | /* | |
1473 | * If we run out of data, disable the data IRQs; this | |
1474 | * prevents a race where the FIFO becomes empty before | |
1475 | * the chip itself has disabled the data path, and | |
1476 | * stops us racing with our data end IRQ. | |
1477 | */ | |
1478 | if (host->size == 0) { | |
2686b4b4 | 1479 | mmci_set_mask1(host, 0); |
1da177e4 LT |
1480 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); |
1481 | } | |
1482 | ||
1483 | return IRQ_HANDLED; | |
1484 | } | |
1485 | ||
1486 | /* | |
1487 | * Handle completion of command and data transfers. | |
1488 | */ | |
7d12e780 | 1489 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
1490 | { |
1491 | struct mmci_host *host = dev_id; | |
1492 | u32 status; | |
1493 | int ret = 0; | |
1494 | ||
1495 | spin_lock(&host->lock); | |
1496 | ||
1497 | do { | |
1da177e4 | 1498 | status = readl(host->base + MMCISTATUS); |
2686b4b4 LW |
1499 | |
1500 | if (host->singleirq) { | |
6ea9cdf3 | 1501 | if (status & host->mask1_reg) |
2686b4b4 LW |
1502 | mmci_pio_irq(irq, dev_id); |
1503 | ||
59db5e2d | 1504 | status &= ~host->variant->irq_pio_mask; |
2686b4b4 LW |
1505 | } |
1506 | ||
8d94b54d | 1507 | /* |
5cad24d8 JNG |
1508 | * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's |
1509 | * enabled) in mmci_cmd_irq() function where ST Micro busy | |
1510 | * detection variant is handled. Considering the HW seems to be | |
1511 | * triggering the IRQ on both edges while monitoring DAT0 for | |
1512 | * busy completion and that same status bit is used to monitor | |
1513 | * start and end of busy detection, special care must be taken | |
1514 | * to make sure that both start and end interrupts are always | |
1515 | * cleared one after the other. | |
8d94b54d | 1516 | */ |
1da177e4 | 1517 | status &= readl(host->base + MMCIMASK0); |
5cad24d8 JNG |
1518 | if (host->variant->busy_detect) |
1519 | writel(status & ~host->variant->busy_detect_mask, | |
1520 | host->base + MMCICLEAR); | |
1521 | else | |
1522 | writel(status, host->base + MMCICLEAR); | |
1da177e4 | 1523 | |
64de0289 | 1524 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 | 1525 | |
7878289b UH |
1526 | if (host->variant->reversed_irq_handling) { |
1527 | mmci_data_irq(host, host->data, status); | |
1528 | mmci_cmd_irq(host, host->cmd, status); | |
1529 | } else { | |
1530 | mmci_cmd_irq(host, host->cmd, status); | |
1531 | mmci_data_irq(host, host->data, status); | |
1532 | } | |
1da177e4 | 1533 | |
49adc0ca | 1534 | /* |
8520ce1e LB |
1535 | * Busy detection has been handled by mmci_cmd_irq() above. |
1536 | * Clear the status bit to prevent polling in IRQ context. | |
49adc0ca | 1537 | */ |
8520ce1e | 1538 | if (host->variant->busy_detect_flag) |
49adc0ca | 1539 | status &= ~host->variant->busy_detect_flag; |
8d94b54d | 1540 | |
1da177e4 LT |
1541 | ret = 1; |
1542 | } while (status); | |
1543 | ||
1544 | spin_unlock(&host->lock); | |
1545 | ||
1546 | return IRQ_RETVAL(ret); | |
1547 | } | |
1548 | ||
1549 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
1550 | { | |
1551 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 1552 | unsigned long flags; |
1da177e4 LT |
1553 | |
1554 | WARN_ON(host->mrq != NULL); | |
1555 | ||
653a761e UH |
1556 | mrq->cmd->error = mmci_validate_data(host, mrq->data); |
1557 | if (mrq->cmd->error) { | |
255d01af PO |
1558 | mmc_request_done(mmc, mrq); |
1559 | return; | |
1560 | } | |
1561 | ||
9e943021 | 1562 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
1563 | |
1564 | host->mrq = mrq; | |
1565 | ||
58c7ccbf PF |
1566 | if (mrq->data) |
1567 | mmci_get_next_data(host, mrq->data); | |
1568 | ||
d2141547 LB |
1569 | if (mrq->data && |
1570 | (host->variant->datactrl_first || mrq->data->flags & MMC_DATA_READ)) | |
1da177e4 LT |
1571 | mmci_start_data(host, mrq->data); |
1572 | ||
024629c6 UH |
1573 | if (mrq->sbc) |
1574 | mmci_start_command(host, mrq->sbc, 0); | |
1575 | else | |
1576 | mmci_start_command(host, mrq->cmd, 0); | |
1da177e4 | 1577 | |
9e943021 | 1578 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
1579 | } |
1580 | ||
1581 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1582 | { | |
1583 | struct mmci_host *host = mmc_priv(mmc); | |
7d72a1d4 | 1584 | struct variant_data *variant = host->variant; |
a6a6464a LW |
1585 | u32 pwr = 0; |
1586 | unsigned long flags; | |
db90f91f | 1587 | int ret; |
1da177e4 | 1588 | |
bc521818 UH |
1589 | if (host->plat->ios_handler && |
1590 | host->plat->ios_handler(mmc_dev(mmc), ios)) | |
1591 | dev_err(mmc_dev(mmc), "platform ios_handler failed\n"); | |
1592 | ||
1da177e4 LT |
1593 | switch (ios->power_mode) { |
1594 | case MMC_POWER_OFF: | |
599c1d5c UH |
1595 | if (!IS_ERR(mmc->supply.vmmc)) |
1596 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); | |
237fb5e6 | 1597 | |
7c0136ef | 1598 | if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { |
237fb5e6 | 1599 | regulator_disable(mmc->supply.vqmmc); |
7c0136ef UH |
1600 | host->vqmmc_enabled = false; |
1601 | } | |
237fb5e6 | 1602 | |
1da177e4 LT |
1603 | break; |
1604 | case MMC_POWER_UP: | |
599c1d5c UH |
1605 | if (!IS_ERR(mmc->supply.vmmc)) |
1606 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); | |
1607 | ||
7d72a1d4 UH |
1608 | /* |
1609 | * The ST Micro variant doesn't have the PL180s MCI_PWR_UP | |
1610 | * and instead uses MCI_PWR_ON so apply whatever value is | |
1611 | * configured in the variant data. | |
1612 | */ | |
1613 | pwr |= variant->pwrreg_powerup; | |
1614 | ||
1615 | break; | |
1da177e4 | 1616 | case MMC_POWER_ON: |
7c0136ef | 1617 | if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { |
db90f91f LJ |
1618 | ret = regulator_enable(mmc->supply.vqmmc); |
1619 | if (ret < 0) | |
1620 | dev_err(mmc_dev(mmc), | |
1621 | "failed to enable vqmmc regulator\n"); | |
7c0136ef UH |
1622 | else |
1623 | host->vqmmc_enabled = true; | |
db90f91f | 1624 | } |
237fb5e6 | 1625 | |
1da177e4 LT |
1626 | pwr |= MCI_PWR_ON; |
1627 | break; | |
1628 | } | |
1629 | ||
4d1a3a0d UH |
1630 | if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) { |
1631 | /* | |
1632 | * The ST Micro variant has some additional bits | |
1633 | * indicating signal direction for the signals in | |
1634 | * the SD/MMC bus and feedback-clock usage. | |
1635 | */ | |
4593df29 | 1636 | pwr |= host->pwr_reg_add; |
4d1a3a0d UH |
1637 | |
1638 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
1639 | pwr &= ~MCI_ST_DATA74DIREN; | |
1640 | else if (ios->bus_width == MMC_BUS_WIDTH_1) | |
1641 | pwr &= (~MCI_ST_DATA74DIREN & | |
1642 | ~MCI_ST_DATA31DIREN & | |
1643 | ~MCI_ST_DATA2DIREN); | |
1644 | } | |
1645 | ||
f9bb304c PC |
1646 | if (variant->opendrain) { |
1647 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
1648 | pwr |= variant->opendrain; | |
1649 | } else { | |
1650 | /* | |
1651 | * If the variant cannot configure the pads by its own, then we | |
1652 | * expect the pinctrl to be able to do that for us | |
1653 | */ | |
1654 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
1655 | pinctrl_select_state(host->pinctrl, host->pins_opendrain); | |
1656 | else | |
1657 | pinctrl_select_state(host->pinctrl, host->pins_default); | |
1658 | } | |
1da177e4 | 1659 | |
f4670dae UH |
1660 | /* |
1661 | * If clock = 0 and the variant requires the MMCIPOWER to be used for | |
1662 | * gating the clock, the MCI_PWR_ON bit is cleared. | |
1663 | */ | |
1664 | if (!ios->clock && variant->pwrreg_clkgate) | |
1665 | pwr &= ~MCI_PWR_ON; | |
1666 | ||
3f4e6f7b SK |
1667 | if (host->variant->explicit_mclk_control && |
1668 | ios->clock != host->clock_cache) { | |
1669 | ret = clk_set_rate(host->clk, ios->clock); | |
1670 | if (ret < 0) | |
1671 | dev_err(mmc_dev(host->mmc), | |
1672 | "Error setting clock rate (%d)\n", ret); | |
1673 | else | |
1674 | host->mclk = clk_get_rate(host->clk); | |
1675 | } | |
1676 | host->clock_cache = ios->clock; | |
1677 | ||
a6a6464a LW |
1678 | spin_lock_irqsave(&host->lock, flags); |
1679 | ||
cd3ee8c5 LB |
1680 | if (host->ops && host->ops->set_clkreg) |
1681 | host->ops->set_clkreg(host, ios->clock); | |
1682 | else | |
1683 | mmci_set_clkreg(host, ios->clock); | |
1684 | ||
1685 | if (host->ops && host->ops->set_pwrreg) | |
1686 | host->ops->set_pwrreg(host, pwr); | |
1687 | else | |
1688 | mmci_write_pwrreg(host, pwr); | |
1689 | ||
f829c042 | 1690 | mmci_reg_delay(host); |
a6a6464a LW |
1691 | |
1692 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
1693 | } |
1694 | ||
89001446 RK |
1695 | static int mmci_get_cd(struct mmc_host *mmc) |
1696 | { | |
1697 | struct mmci_host *host = mmc_priv(mmc); | |
29719445 | 1698 | struct mmci_platform_data *plat = host->plat; |
d2762090 | 1699 | unsigned int status = mmc_gpio_get_cd(mmc); |
89001446 | 1700 | |
d2762090 | 1701 | if (status == -ENOSYS) { |
4b8caec0 RV |
1702 | if (!plat->status) |
1703 | return 1; /* Assume always present */ | |
1704 | ||
29719445 | 1705 | status = plat->status(mmc_dev(host->mmc)); |
d2762090 | 1706 | } |
74bc8093 | 1707 | return status; |
89001446 RK |
1708 | } |
1709 | ||
0f3ed7f7 UH |
1710 | static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) |
1711 | { | |
1712 | int ret = 0; | |
1713 | ||
1714 | if (!IS_ERR(mmc->supply.vqmmc)) { | |
1715 | ||
0f3ed7f7 UH |
1716 | switch (ios->signal_voltage) { |
1717 | case MMC_SIGNAL_VOLTAGE_330: | |
1718 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
1719 | 2700000, 3600000); | |
1720 | break; | |
1721 | case MMC_SIGNAL_VOLTAGE_180: | |
1722 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
1723 | 1700000, 1950000); | |
1724 | break; | |
1725 | case MMC_SIGNAL_VOLTAGE_120: | |
1726 | ret = regulator_set_voltage(mmc->supply.vqmmc, | |
1727 | 1100000, 1300000); | |
1728 | break; | |
1729 | } | |
1730 | ||
1731 | if (ret) | |
1732 | dev_warn(mmc_dev(mmc), "Voltage switch failed\n"); | |
0f3ed7f7 UH |
1733 | } |
1734 | ||
1735 | return ret; | |
1736 | } | |
1737 | ||
01259620 | 1738 | static struct mmc_host_ops mmci_ops = { |
1da177e4 | 1739 | .request = mmci_request, |
58c7ccbf PF |
1740 | .pre_req = mmci_pre_request, |
1741 | .post_req = mmci_post_request, | |
1da177e4 | 1742 | .set_ios = mmci_set_ios, |
d2762090 | 1743 | .get_ro = mmc_gpio_get_ro, |
89001446 | 1744 | .get_cd = mmci_get_cd, |
0f3ed7f7 | 1745 | .start_signal_voltage_switch = mmci_sig_volt_switch, |
1da177e4 LT |
1746 | }; |
1747 | ||
4593df29 | 1748 | static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc) |
000bc9d5 | 1749 | { |
4593df29 UH |
1750 | struct mmci_host *host = mmc_priv(mmc); |
1751 | int ret = mmc_of_parse(mmc); | |
1752 | ||
1753 | if (ret) | |
1754 | return ret; | |
1755 | ||
ae94cafe | 1756 | if (of_get_property(np, "st,sig-dir-dat0", NULL)) |
4593df29 | 1757 | host->pwr_reg_add |= MCI_ST_DATA0DIREN; |
ae94cafe | 1758 | if (of_get_property(np, "st,sig-dir-dat2", NULL)) |
4593df29 | 1759 | host->pwr_reg_add |= MCI_ST_DATA2DIREN; |
ae94cafe | 1760 | if (of_get_property(np, "st,sig-dir-dat31", NULL)) |
4593df29 | 1761 | host->pwr_reg_add |= MCI_ST_DATA31DIREN; |
ae94cafe | 1762 | if (of_get_property(np, "st,sig-dir-dat74", NULL)) |
4593df29 | 1763 | host->pwr_reg_add |= MCI_ST_DATA74DIREN; |
ae94cafe | 1764 | if (of_get_property(np, "st,sig-dir-cmd", NULL)) |
4593df29 | 1765 | host->pwr_reg_add |= MCI_ST_CMDDIREN; |
1a7e99c1 | 1766 | if (of_get_property(np, "st,sig-pin-fbclk", NULL)) |
4593df29 | 1767 | host->pwr_reg_add |= MCI_ST_FBCLKEN; |
46b723dd LB |
1768 | if (of_get_property(np, "st,sig-dir", NULL)) |
1769 | host->pwr_reg_add |= MCI_STM32_DIRPOL; | |
1770 | if (of_get_property(np, "st,neg-edge", NULL)) | |
1771 | host->clk_reg_add |= MCI_STM32_CLK_NEGEDGE; | |
1772 | if (of_get_property(np, "st,use-ckin", NULL)) | |
1773 | host->clk_reg_add |= MCI_STM32_CLK_SELCKIN; | |
000bc9d5 LJ |
1774 | |
1775 | if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL)) | |
78f87df2 | 1776 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED; |
000bc9d5 | 1777 | if (of_get_property(np, "mmc-cap-sd-highspeed", NULL)) |
78f87df2 | 1778 | mmc->caps |= MMC_CAP_SD_HIGHSPEED; |
000bc9d5 | 1779 | |
78f87df2 | 1780 | return 0; |
c0a120a4 | 1781 | } |
000bc9d5 | 1782 | |
c3be1efd | 1783 | static int mmci_probe(struct amba_device *dev, |
aa25afad | 1784 | const struct amba_id *id) |
1da177e4 | 1785 | { |
6ef297f8 | 1786 | struct mmci_platform_data *plat = dev->dev.platform_data; |
000bc9d5 | 1787 | struct device_node *np = dev->dev.of_node; |
4956e109 | 1788 | struct variant_data *variant = id->data; |
1da177e4 LT |
1789 | struct mmci_host *host; |
1790 | struct mmc_host *mmc; | |
1791 | int ret; | |
1792 | ||
000bc9d5 LJ |
1793 | /* Must have platform data or Device Tree. */ |
1794 | if (!plat && !np) { | |
1795 | dev_err(&dev->dev, "No plat data or DT found\n"); | |
1796 | return -EINVAL; | |
1da177e4 LT |
1797 | } |
1798 | ||
b9b52918 LJ |
1799 | if (!plat) { |
1800 | plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL); | |
1801 | if (!plat) | |
1802 | return -ENOMEM; | |
1803 | } | |
1804 | ||
1da177e4 | 1805 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); |
ef289982 UH |
1806 | if (!mmc) |
1807 | return -ENOMEM; | |
1da177e4 | 1808 | |
78f87df2 UH |
1809 | ret = mmci_of_parse(np, mmc); |
1810 | if (ret) | |
1811 | goto host_free; | |
1812 | ||
1da177e4 | 1813 | host = mmc_priv(mmc); |
4ea580f1 | 1814 | host->mmc = mmc; |
012b7d33 | 1815 | |
f9bb304c PC |
1816 | /* |
1817 | * Some variant (STM32) doesn't have opendrain bit, nevertheless | |
1818 | * pins can be set accordingly using pinctrl | |
1819 | */ | |
1820 | if (!variant->opendrain) { | |
1821 | host->pinctrl = devm_pinctrl_get(&dev->dev); | |
1822 | if (IS_ERR(host->pinctrl)) { | |
1823 | dev_err(&dev->dev, "failed to get pinctrl"); | |
310eb252 | 1824 | ret = PTR_ERR(host->pinctrl); |
f9bb304c PC |
1825 | goto host_free; |
1826 | } | |
1827 | ||
1828 | host->pins_default = pinctrl_lookup_state(host->pinctrl, | |
1829 | PINCTRL_STATE_DEFAULT); | |
1830 | if (IS_ERR(host->pins_default)) { | |
1831 | dev_err(mmc_dev(mmc), "Can't select default pins\n"); | |
310eb252 | 1832 | ret = PTR_ERR(host->pins_default); |
f9bb304c PC |
1833 | goto host_free; |
1834 | } | |
1835 | ||
1836 | host->pins_opendrain = pinctrl_lookup_state(host->pinctrl, | |
1837 | MMCI_PINCTRL_STATE_OPENDRAIN); | |
1838 | if (IS_ERR(host->pins_opendrain)) { | |
1839 | dev_err(mmc_dev(mmc), "Can't select opendrain pins\n"); | |
310eb252 | 1840 | ret = PTR_ERR(host->pins_opendrain); |
f9bb304c PC |
1841 | goto host_free; |
1842 | } | |
1843 | } | |
1844 | ||
012b7d33 RK |
1845 | host->hw_designer = amba_manf(dev); |
1846 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
1847 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
1848 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 1849 | |
665ba56f | 1850 | host->clk = devm_clk_get(&dev->dev, NULL); |
1da177e4 LT |
1851 | if (IS_ERR(host->clk)) { |
1852 | ret = PTR_ERR(host->clk); | |
1da177e4 LT |
1853 | goto host_free; |
1854 | } | |
1855 | ||
ac940938 | 1856 | ret = clk_prepare_enable(host->clk); |
1da177e4 | 1857 | if (ret) |
665ba56f | 1858 | goto host_free; |
1da177e4 | 1859 | |
9c34b73d SK |
1860 | if (variant->qcom_fifo) |
1861 | host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt; | |
1862 | else | |
1863 | host->get_rx_fifocnt = mmci_get_rx_fifocnt; | |
1864 | ||
1da177e4 | 1865 | host->plat = plat; |
4956e109 | 1866 | host->variant = variant; |
1da177e4 | 1867 | host->mclk = clk_get_rate(host->clk); |
c8df9a53 LW |
1868 | /* |
1869 | * According to the spec, mclk is max 100 MHz, | |
1870 | * so we try to adjust the clock down to this, | |
1871 | * (if possible). | |
1872 | */ | |
dc6500bf SK |
1873 | if (host->mclk > variant->f_max) { |
1874 | ret = clk_set_rate(host->clk, variant->f_max); | |
c8df9a53 LW |
1875 | if (ret < 0) |
1876 | goto clk_disable; | |
1877 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
1878 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
1879 | host->mclk); | |
c8df9a53 | 1880 | } |
ef289982 | 1881 | |
c8ebae37 | 1882 | host->phybase = dev->res.start; |
ef289982 UH |
1883 | host->base = devm_ioremap_resource(&dev->dev, &dev->res); |
1884 | if (IS_ERR(host->base)) { | |
1885 | ret = PTR_ERR(host->base); | |
1da177e4 LT |
1886 | goto clk_disable; |
1887 | } | |
1888 | ||
ed9067fd UH |
1889 | if (variant->init) |
1890 | variant->init(host); | |
1891 | ||
7f294e49 LW |
1892 | /* |
1893 | * The ARM and ST versions of the block have slightly different | |
1894 | * clock divider equations which means that the minimum divider | |
1895 | * differs too. | |
3f4e6f7b | 1896 | * on Qualcomm like controllers get the nearest minimum clock to 100Khz |
7f294e49 LW |
1897 | */ |
1898 | if (variant->st_clkdiv) | |
1899 | mmc->f_min = DIV_ROUND_UP(host->mclk, 257); | |
00e930d8 LB |
1900 | else if (variant->stm32_clkdiv) |
1901 | mmc->f_min = DIV_ROUND_UP(host->mclk, 2046); | |
3f4e6f7b SK |
1902 | else if (variant->explicit_mclk_control) |
1903 | mmc->f_min = clk_round_rate(host->clk, 100000); | |
7f294e49 LW |
1904 | else |
1905 | mmc->f_min = DIV_ROUND_UP(host->mclk, 512); | |
808d97cc | 1906 | /* |
78f87df2 UH |
1907 | * If no maximum operating frequency is supplied, fall back to use |
1908 | * the module parameter, which has a (low) default value in case it | |
1909 | * is not specified. Either value must not exceed the clock rate into | |
5080a08d | 1910 | * the block, of course. |
808d97cc | 1911 | */ |
78f87df2 | 1912 | if (mmc->f_max) |
3f4e6f7b SK |
1913 | mmc->f_max = variant->explicit_mclk_control ? |
1914 | min(variant->f_max, mmc->f_max) : | |
1915 | min(host->mclk, mmc->f_max); | |
808d97cc | 1916 | else |
3f4e6f7b SK |
1917 | mmc->f_max = variant->explicit_mclk_control ? |
1918 | fmax : min(host->mclk, fmax); | |
1919 | ||
1920 | ||
64de0289 LW |
1921 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
1922 | ||
15878e58 LB |
1923 | host->rst = devm_reset_control_get_optional_exclusive(&dev->dev, NULL); |
1924 | if (IS_ERR(host->rst)) { | |
1925 | ret = PTR_ERR(host->rst); | |
1926 | goto clk_disable; | |
1927 | } | |
1928 | ||
599c1d5c | 1929 | /* Get regulators and the supported OCR mask */ |
9369c97c | 1930 | ret = mmc_regulator_get_supply(mmc); |
51006952 | 1931 | if (ret) |
9369c97c BA |
1932 | goto clk_disable; |
1933 | ||
599c1d5c | 1934 | if (!mmc->ocr_avail) |
34e84f39 | 1935 | mmc->ocr_avail = plat->ocr_mask; |
599c1d5c UH |
1936 | else if (plat->ocr_mask) |
1937 | dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); | |
1938 | ||
9dd8a8b8 UH |
1939 | /* We support these capabilities. */ |
1940 | mmc->caps |= MMC_CAP_CMD23; | |
1941 | ||
49adc0ca LW |
1942 | /* |
1943 | * Enable busy detection. | |
1944 | */ | |
8d94b54d UH |
1945 | if (variant->busy_detect) { |
1946 | mmci_ops.card_busy = mmci_card_busy; | |
49adc0ca LW |
1947 | /* |
1948 | * Not all variants have a flag to enable busy detection | |
1949 | * in the DPSM, but if they do, set it here. | |
1950 | */ | |
1951 | if (variant->busy_dpsm_flag) | |
1952 | mmci_write_datactrlreg(host, | |
1953 | host->variant->busy_dpsm_flag); | |
8d94b54d UH |
1954 | mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; |
1955 | mmc->max_busy_timeout = 0; | |
1956 | } | |
1957 | ||
e9968c6f UH |
1958 | /* Prepare a CMD12 - needed to clear the DPSM on some variants. */ |
1959 | host->stop_abort.opcode = MMC_STOP_TRANSMISSION; | |
1960 | host->stop_abort.arg = 0; | |
1961 | host->stop_abort.flags = MMC_RSP_R1B | MMC_CMD_AC; | |
1962 | ||
8d94b54d UH |
1963 | mmc->ops = &mmci_ops; |
1964 | ||
70be208f | 1965 | /* We support these PM capabilities. */ |
78f87df2 | 1966 | mmc->pm_caps |= MMC_PM_KEEP_POWER; |
70be208f | 1967 | |
1da177e4 LT |
1968 | /* |
1969 | * We can do SGIO | |
1970 | */ | |
a36274e0 | 1971 | mmc->max_segs = NR_SG; |
1da177e4 LT |
1972 | |
1973 | /* | |
08458ef6 RV |
1974 | * Since only a certain number of bits are valid in the data length |
1975 | * register, we must ensure that we don't exceed 2^num-1 bytes in a | |
1976 | * single request. | |
1da177e4 | 1977 | */ |
08458ef6 | 1978 | mmc->max_req_size = (1 << variant->datalength_bits) - 1; |
1da177e4 LT |
1979 | |
1980 | /* | |
1981 | * Set the maximum segment size. Since we aren't doing DMA | |
1982 | * (yet) we are only limited by the data length register. | |
1983 | */ | |
55db890a | 1984 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 1985 | |
fe4a3c7a PO |
1986 | /* |
1987 | * Block size can be up to 2048 bytes, but must be a power of two. | |
1988 | */ | |
c931d495 | 1989 | mmc->max_blk_size = 1 << variant->datactrl_blocksz; |
fe4a3c7a | 1990 | |
55db890a | 1991 | /* |
8f7f6b7e WD |
1992 | * Limit the number of blocks transferred so that we don't overflow |
1993 | * the maximum request size. | |
55db890a | 1994 | */ |
c931d495 | 1995 | mmc->max_blk_count = mmc->max_req_size >> variant->datactrl_blocksz; |
55db890a | 1996 | |
1da177e4 LT |
1997 | spin_lock_init(&host->lock); |
1998 | ||
1999 | writel(0, host->base + MMCIMASK0); | |
6ea9cdf3 PC |
2000 | |
2001 | if (variant->mmcimask1) | |
2002 | writel(0, host->base + MMCIMASK1); | |
2003 | ||
1da177e4 LT |
2004 | writel(0xfff, host->base + MMCICLEAR); |
2005 | ||
ce437aa4 LW |
2006 | /* |
2007 | * If: | |
2008 | * - not using DT but using a descriptor table, or | |
2009 | * - using a table of descriptors ALONGSIDE DT, or | |
2010 | * look up these descriptors named "cd" and "wp" right here, fail | |
9ef986a6 | 2011 | * silently of these do not exist |
ce437aa4 LW |
2012 | */ |
2013 | if (!np) { | |
89168b48 | 2014 | ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); |
9ef986a6 LW |
2015 | if (ret == -EPROBE_DEFER) |
2016 | goto clk_disable; | |
ce437aa4 | 2017 | |
a2b760a6 | 2018 | ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0, NULL); |
9ef986a6 LW |
2019 | if (ret == -EPROBE_DEFER) |
2020 | goto clk_disable; | |
89001446 RK |
2021 | } |
2022 | ||
ef289982 UH |
2023 | ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED, |
2024 | DRIVER_NAME " (cmd)", host); | |
1da177e4 | 2025 | if (ret) |
ef289982 | 2026 | goto clk_disable; |
1da177e4 | 2027 | |
dfb85185 | 2028 | if (!dev->irq[1]) |
2686b4b4 LW |
2029 | host->singleirq = true; |
2030 | else { | |
ef289982 UH |
2031 | ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq, |
2032 | IRQF_SHARED, DRIVER_NAME " (pio)", host); | |
2686b4b4 | 2033 | if (ret) |
ef289982 | 2034 | goto clk_disable; |
2686b4b4 | 2035 | } |
1da177e4 | 2036 | |
daf9713c | 2037 | writel(MCI_IRQENABLE | variant->start_err, host->base + MMCIMASK0); |
1da177e4 LT |
2038 | |
2039 | amba_set_drvdata(dev, mmc); | |
2040 | ||
c8ebae37 RK |
2041 | dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n", |
2042 | mmc_hostname(mmc), amba_part(dev), amba_manf(dev), | |
2043 | amba_rev(dev), (unsigned long long)dev->res.start, | |
2044 | dev->irq[0], dev->irq[1]); | |
2045 | ||
2046 | mmci_dma_setup(host); | |
1da177e4 | 2047 | |
2cd976c4 UH |
2048 | pm_runtime_set_autosuspend_delay(&dev->dev, 50); |
2049 | pm_runtime_use_autosuspend(&dev->dev); | |
1c3be369 | 2050 | |
8c11a94d RK |
2051 | mmc_add_host(mmc); |
2052 | ||
6f2d3c89 | 2053 | pm_runtime_put(&dev->dev); |
1da177e4 LT |
2054 | return 0; |
2055 | ||
1da177e4 | 2056 | clk_disable: |
ac940938 | 2057 | clk_disable_unprepare(host->clk); |
1da177e4 LT |
2058 | host_free: |
2059 | mmc_free_host(mmc); | |
1da177e4 LT |
2060 | return ret; |
2061 | } | |
2062 | ||
6e0ee714 | 2063 | static int mmci_remove(struct amba_device *dev) |
1da177e4 LT |
2064 | { |
2065 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
2066 | ||
1da177e4 LT |
2067 | if (mmc) { |
2068 | struct mmci_host *host = mmc_priv(mmc); | |
6ea9cdf3 | 2069 | struct variant_data *variant = host->variant; |
1da177e4 | 2070 | |
1c3be369 RK |
2071 | /* |
2072 | * Undo pm_runtime_put() in probe. We use the _sync | |
2073 | * version here so that we can access the primecell. | |
2074 | */ | |
2075 | pm_runtime_get_sync(&dev->dev); | |
2076 | ||
1da177e4 LT |
2077 | mmc_remove_host(mmc); |
2078 | ||
2079 | writel(0, host->base + MMCIMASK0); | |
6ea9cdf3 PC |
2080 | |
2081 | if (variant->mmcimask1) | |
2082 | writel(0, host->base + MMCIMASK1); | |
1da177e4 LT |
2083 | |
2084 | writel(0, host->base + MMCICOMMAND); | |
2085 | writel(0, host->base + MMCIDATACTRL); | |
2086 | ||
c8ebae37 | 2087 | mmci_dma_release(host); |
ac940938 | 2088 | clk_disable_unprepare(host->clk); |
1da177e4 | 2089 | mmc_free_host(mmc); |
1da177e4 LT |
2090 | } |
2091 | ||
2092 | return 0; | |
2093 | } | |
2094 | ||
571dce4f | 2095 | #ifdef CONFIG_PM |
1ff44433 UH |
2096 | static void mmci_save(struct mmci_host *host) |
2097 | { | |
2098 | unsigned long flags; | |
2099 | ||
42dcc89a | 2100 | spin_lock_irqsave(&host->lock, flags); |
1ff44433 | 2101 | |
42dcc89a UH |
2102 | writel(0, host->base + MMCIMASK0); |
2103 | if (host->variant->pwrreg_nopower) { | |
1ff44433 UH |
2104 | writel(0, host->base + MMCIDATACTRL); |
2105 | writel(0, host->base + MMCIPOWER); | |
2106 | writel(0, host->base + MMCICLOCK); | |
1ff44433 | 2107 | } |
42dcc89a | 2108 | mmci_reg_delay(host); |
1ff44433 | 2109 | |
42dcc89a | 2110 | spin_unlock_irqrestore(&host->lock, flags); |
1ff44433 UH |
2111 | } |
2112 | ||
2113 | static void mmci_restore(struct mmci_host *host) | |
2114 | { | |
2115 | unsigned long flags; | |
2116 | ||
42dcc89a | 2117 | spin_lock_irqsave(&host->lock, flags); |
1ff44433 | 2118 | |
42dcc89a | 2119 | if (host->variant->pwrreg_nopower) { |
1ff44433 UH |
2120 | writel(host->clk_reg, host->base + MMCICLOCK); |
2121 | writel(host->datactrl_reg, host->base + MMCIDATACTRL); | |
2122 | writel(host->pwr_reg, host->base + MMCIPOWER); | |
1ff44433 | 2123 | } |
daf9713c LB |
2124 | writel(MCI_IRQENABLE | host->variant->start_err, |
2125 | host->base + MMCIMASK0); | |
42dcc89a UH |
2126 | mmci_reg_delay(host); |
2127 | ||
2128 | spin_unlock_irqrestore(&host->lock, flags); | |
1ff44433 UH |
2129 | } |
2130 | ||
8259293a UH |
2131 | static int mmci_runtime_suspend(struct device *dev) |
2132 | { | |
2133 | struct amba_device *adev = to_amba_device(dev); | |
2134 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
2135 | ||
2136 | if (mmc) { | |
2137 | struct mmci_host *host = mmc_priv(mmc); | |
e36bd9c6 | 2138 | pinctrl_pm_select_sleep_state(dev); |
1ff44433 | 2139 | mmci_save(host); |
8259293a UH |
2140 | clk_disable_unprepare(host->clk); |
2141 | } | |
2142 | ||
2143 | return 0; | |
2144 | } | |
2145 | ||
2146 | static int mmci_runtime_resume(struct device *dev) | |
2147 | { | |
2148 | struct amba_device *adev = to_amba_device(dev); | |
2149 | struct mmc_host *mmc = amba_get_drvdata(adev); | |
2150 | ||
2151 | if (mmc) { | |
2152 | struct mmci_host *host = mmc_priv(mmc); | |
2153 | clk_prepare_enable(host->clk); | |
1ff44433 | 2154 | mmci_restore(host); |
e36bd9c6 | 2155 | pinctrl_pm_select_default_state(dev); |
8259293a UH |
2156 | } |
2157 | ||
2158 | return 0; | |
2159 | } | |
2160 | #endif | |
2161 | ||
48fa7003 | 2162 | static const struct dev_pm_ops mmci_dev_pm_ops = { |
f3737fa3 UH |
2163 | SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, |
2164 | pm_runtime_force_resume) | |
6ed23b80 | 2165 | SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL) |
48fa7003 UH |
2166 | }; |
2167 | ||
88411dea | 2168 | static const struct amba_id mmci_ids[] = { |
1da177e4 LT |
2169 | { |
2170 | .id = 0x00041180, | |
768fbc18 | 2171 | .mask = 0xff0fffff, |
4956e109 | 2172 | .data = &variant_arm, |
1da177e4 | 2173 | }, |
768fbc18 PM |
2174 | { |
2175 | .id = 0x01041180, | |
2176 | .mask = 0xff0fffff, | |
2177 | .data = &variant_arm_extended_fifo, | |
2178 | }, | |
3a37298a PM |
2179 | { |
2180 | .id = 0x02041180, | |
2181 | .mask = 0xff0fffff, | |
2182 | .data = &variant_arm_extended_fifo_hwfc, | |
2183 | }, | |
1da177e4 LT |
2184 | { |
2185 | .id = 0x00041181, | |
2186 | .mask = 0x000fffff, | |
4956e109 | 2187 | .data = &variant_arm, |
1da177e4 | 2188 | }, |
cc30d60e LW |
2189 | /* ST Micro variants */ |
2190 | { | |
2191 | .id = 0x00180180, | |
2192 | .mask = 0x00ffffff, | |
4956e109 | 2193 | .data = &variant_u300, |
cc30d60e | 2194 | }, |
34fd4213 LW |
2195 | { |
2196 | .id = 0x10180180, | |
2197 | .mask = 0xf0ffffff, | |
2198 | .data = &variant_nomadik, | |
2199 | }, | |
cc30d60e LW |
2200 | { |
2201 | .id = 0x00280180, | |
2202 | .mask = 0x00ffffff, | |
0bcb7efd | 2203 | .data = &variant_nomadik, |
4956e109 RV |
2204 | }, |
2205 | { | |
2206 | .id = 0x00480180, | |
1784b157 | 2207 | .mask = 0xf0ffffff, |
4956e109 | 2208 | .data = &variant_ux500, |
cc30d60e | 2209 | }, |
1784b157 PL |
2210 | { |
2211 | .id = 0x10480180, | |
2212 | .mask = 0xf0ffffff, | |
2213 | .data = &variant_ux500v2, | |
2214 | }, | |
2a9d6c80 PC |
2215 | { |
2216 | .id = 0x00880180, | |
2217 | .mask = 0x00ffffff, | |
2218 | .data = &variant_stm32, | |
2219 | }, | |
46b723dd LB |
2220 | { |
2221 | .id = 0x10153180, | |
2222 | .mask = 0xf0ffffff, | |
2223 | .data = &variant_stm32_sdmmc, | |
2224 | }, | |
55b604ae SK |
2225 | /* Qualcomm variants */ |
2226 | { | |
2227 | .id = 0x00051180, | |
2228 | .mask = 0x000fffff, | |
2229 | .data = &variant_qcom, | |
2230 | }, | |
1da177e4 LT |
2231 | { 0, 0 }, |
2232 | }; | |
2233 | ||
9f99835f DM |
2234 | MODULE_DEVICE_TABLE(amba, mmci_ids); |
2235 | ||
1da177e4 LT |
2236 | static struct amba_driver mmci_driver = { |
2237 | .drv = { | |
2238 | .name = DRIVER_NAME, | |
48fa7003 | 2239 | .pm = &mmci_dev_pm_ops, |
1da177e4 LT |
2240 | }, |
2241 | .probe = mmci_probe, | |
0433c143 | 2242 | .remove = mmci_remove, |
1da177e4 LT |
2243 | .id_table = mmci_ids, |
2244 | }; | |
2245 | ||
9e5ed094 | 2246 | module_amba_driver(mmci_driver); |
1da177e4 | 2247 | |
1da177e4 LT |
2248 | module_param(fmax, uint, 0444); |
2249 | ||
2250 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
2251 | MODULE_LICENSE("GPL"); |