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Commit | Line | Data |
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1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
64de0289 | 5 | * Copyright (C) 2010 ST-Ericsson AB. |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
1da177e4 LT |
11 | #include <linux/module.h> |
12 | #include <linux/moduleparam.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/ioport.h> | |
15 | #include <linux/device.h> | |
16 | #include <linux/interrupt.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/err.h> | |
19 | #include <linux/highmem.h> | |
019a5f56 | 20 | #include <linux/log2.h> |
1da177e4 | 21 | #include <linux/mmc/host.h> |
a62c80e5 | 22 | #include <linux/amba/bus.h> |
f8ce2547 | 23 | #include <linux/clk.h> |
bd6dee6f | 24 | #include <linux/scatterlist.h> |
89001446 | 25 | #include <linux/gpio.h> |
6ef297f8 | 26 | #include <linux/amba/mmci.h> |
34e84f39 | 27 | #include <linux/regulator/consumer.h> |
1da177e4 | 28 | |
7b09cdac | 29 | #include <asm/div64.h> |
1da177e4 | 30 | #include <asm/io.h> |
c6b8fdad | 31 | #include <asm/sizes.h> |
1da177e4 LT |
32 | |
33 | #include "mmci.h" | |
34 | ||
35 | #define DRIVER_NAME "mmci-pl18x" | |
36 | ||
1da177e4 LT |
37 | static unsigned int fmax = 515633; |
38 | ||
a6a6464a LW |
39 | /* |
40 | * This must be called with host->lock held | |
41 | */ | |
42 | static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired) | |
43 | { | |
44 | u32 clk = 0; | |
45 | ||
46 | if (desired) { | |
47 | if (desired >= host->mclk) { | |
48 | clk = MCI_CLK_BYPASS; | |
49 | host->cclk = host->mclk; | |
50 | } else { | |
51 | clk = host->mclk / (2 * desired) - 1; | |
52 | if (clk >= 256) | |
53 | clk = 255; | |
54 | host->cclk = host->mclk / (2 * (clk + 1)); | |
55 | } | |
b43149c1 | 56 | if (host->hw_designer == AMBA_VENDOR_ST) |
771dc157 | 57 | clk |= MCI_ST_FCEN; /* Bug fix in ST IP block */ |
a6a6464a LW |
58 | clk |= MCI_CLK_ENABLE; |
59 | /* This hasn't proven to be worthwhile */ | |
60 | /* clk |= MCI_CLK_PWRSAVE; */ | |
61 | } | |
62 | ||
9e6c82cd | 63 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
771dc157 LW |
64 | clk |= MCI_4BIT_BUS; |
65 | if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) | |
66 | clk |= MCI_ST_8BIT_BUS; | |
9e6c82cd | 67 | |
a6a6464a LW |
68 | writel(clk, host->base + MMCICLOCK); |
69 | } | |
70 | ||
1da177e4 LT |
71 | static void |
72 | mmci_request_end(struct mmci_host *host, struct mmc_request *mrq) | |
73 | { | |
74 | writel(0, host->base + MMCICOMMAND); | |
75 | ||
e47c222b RK |
76 | BUG_ON(host->data); |
77 | ||
1da177e4 LT |
78 | host->mrq = NULL; |
79 | host->cmd = NULL; | |
80 | ||
81 | if (mrq->data) | |
82 | mrq->data->bytes_xfered = host->data_xfered; | |
83 | ||
84 | /* | |
85 | * Need to drop the host lock here; mmc_request_done may call | |
86 | * back into the driver... | |
87 | */ | |
88 | spin_unlock(&host->lock); | |
89 | mmc_request_done(host->mmc, mrq); | |
90 | spin_lock(&host->lock); | |
91 | } | |
92 | ||
93 | static void mmci_stop_data(struct mmci_host *host) | |
94 | { | |
95 | writel(0, host->base + MMCIDATACTRL); | |
96 | writel(0, host->base + MMCIMASK1); | |
97 | host->data = NULL; | |
98 | } | |
99 | ||
4ce1d6cb RV |
100 | static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data) |
101 | { | |
102 | unsigned int flags = SG_MITER_ATOMIC; | |
103 | ||
104 | if (data->flags & MMC_DATA_READ) | |
105 | flags |= SG_MITER_TO_SG; | |
106 | else | |
107 | flags |= SG_MITER_FROM_SG; | |
108 | ||
109 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); | |
110 | } | |
111 | ||
1da177e4 LT |
112 | static void mmci_start_data(struct mmci_host *host, struct mmc_data *data) |
113 | { | |
114 | unsigned int datactrl, timeout, irqmask; | |
7b09cdac | 115 | unsigned long long clks; |
1da177e4 | 116 | void __iomem *base; |
3bc87f24 | 117 | int blksz_bits; |
1da177e4 | 118 | |
64de0289 LW |
119 | dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n", |
120 | data->blksz, data->blocks, data->flags); | |
1da177e4 LT |
121 | |
122 | host->data = data; | |
528320db | 123 | host->size = data->blksz * data->blocks; |
1da177e4 LT |
124 | host->data_xfered = 0; |
125 | ||
126 | mmci_init_sg(host, data); | |
127 | ||
7b09cdac RK |
128 | clks = (unsigned long long)data->timeout_ns * host->cclk; |
129 | do_div(clks, 1000000000UL); | |
130 | ||
131 | timeout = data->timeout_clks + (unsigned int)clks; | |
1da177e4 LT |
132 | |
133 | base = host->base; | |
134 | writel(timeout, base + MMCIDATATIMER); | |
135 | writel(host->size, base + MMCIDATALENGTH); | |
136 | ||
3bc87f24 RK |
137 | blksz_bits = ffs(data->blksz) - 1; |
138 | BUG_ON(1 << blksz_bits != data->blksz); | |
139 | ||
140 | datactrl = MCI_DPSM_ENABLE | blksz_bits << 4; | |
1da177e4 LT |
141 | if (data->flags & MMC_DATA_READ) { |
142 | datactrl |= MCI_DPSM_DIRECTION; | |
143 | irqmask = MCI_RXFIFOHALFFULLMASK; | |
0425a142 RK |
144 | |
145 | /* | |
146 | * If we have less than a FIFOSIZE of bytes to transfer, | |
147 | * trigger a PIO interrupt as soon as any data is available. | |
148 | */ | |
149 | if (host->size < MCI_FIFOSIZE) | |
150 | irqmask |= MCI_RXDATAAVLBLMASK; | |
1da177e4 LT |
151 | } else { |
152 | /* | |
153 | * We don't actually need to include "FIFO empty" here | |
154 | * since its implicit in "FIFO half empty". | |
155 | */ | |
156 | irqmask = MCI_TXFIFOHALFEMPTYMASK; | |
157 | } | |
158 | ||
159 | writel(datactrl, base + MMCIDATACTRL); | |
160 | writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0); | |
161 | writel(irqmask, base + MMCIMASK1); | |
162 | } | |
163 | ||
164 | static void | |
165 | mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c) | |
166 | { | |
167 | void __iomem *base = host->base; | |
168 | ||
64de0289 | 169 | dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n", |
1da177e4 LT |
170 | cmd->opcode, cmd->arg, cmd->flags); |
171 | ||
172 | if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) { | |
173 | writel(0, base + MMCICOMMAND); | |
174 | udelay(1); | |
175 | } | |
176 | ||
177 | c |= cmd->opcode | MCI_CPSM_ENABLE; | |
e9225176 RK |
178 | if (cmd->flags & MMC_RSP_PRESENT) { |
179 | if (cmd->flags & MMC_RSP_136) | |
180 | c |= MCI_CPSM_LONGRSP; | |
1da177e4 | 181 | c |= MCI_CPSM_RESPONSE; |
1da177e4 LT |
182 | } |
183 | if (/*interrupt*/0) | |
184 | c |= MCI_CPSM_INTERRUPT; | |
185 | ||
186 | host->cmd = cmd; | |
187 | ||
188 | writel(cmd->arg, base + MMCIARGUMENT); | |
189 | writel(c, base + MMCICOMMAND); | |
190 | } | |
191 | ||
192 | static void | |
193 | mmci_data_irq(struct mmci_host *host, struct mmc_data *data, | |
194 | unsigned int status) | |
195 | { | |
196 | if (status & MCI_DATABLOCKEND) { | |
3bc87f24 | 197 | host->data_xfered += data->blksz; |
f28e8a4d LW |
198 | #ifdef CONFIG_ARCH_U300 |
199 | /* | |
200 | * On the U300 some signal or other is | |
201 | * badly routed so that a data write does | |
202 | * not properly terminate with a MCI_DATAEND | |
203 | * status flag. This quirk will make writes | |
204 | * work again. | |
205 | */ | |
206 | if (data->flags & MMC_DATA_WRITE) | |
207 | status |= MCI_DATAEND; | |
208 | #endif | |
1da177e4 LT |
209 | } |
210 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) { | |
64de0289 | 211 | dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ (status %08x)\n", status); |
1da177e4 | 212 | if (status & MCI_DATACRCFAIL) |
17b0429d | 213 | data->error = -EILSEQ; |
1da177e4 | 214 | else if (status & MCI_DATATIMEOUT) |
17b0429d | 215 | data->error = -ETIMEDOUT; |
1da177e4 | 216 | else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN)) |
17b0429d | 217 | data->error = -EIO; |
1da177e4 | 218 | status |= MCI_DATAEND; |
e9c091b4 RK |
219 | |
220 | /* | |
221 | * We hit an error condition. Ensure that any data | |
222 | * partially written to a page is properly coherent. | |
223 | */ | |
4ce1d6cb RV |
224 | if (data->flags & MMC_DATA_READ) { |
225 | struct sg_mapping_iter *sg_miter = &host->sg_miter; | |
226 | unsigned long flags; | |
227 | ||
228 | local_irq_save(flags); | |
229 | if (sg_miter_next(sg_miter)) { | |
230 | flush_dcache_page(sg_miter->page); | |
231 | sg_miter_stop(sg_miter); | |
232 | } | |
233 | local_irq_restore(flags); | |
234 | } | |
1da177e4 LT |
235 | } |
236 | if (status & MCI_DATAEND) { | |
237 | mmci_stop_data(host); | |
238 | ||
239 | if (!data->stop) { | |
240 | mmci_request_end(host, data->mrq); | |
241 | } else { | |
242 | mmci_start_command(host, data->stop, 0); | |
243 | } | |
244 | } | |
245 | } | |
246 | ||
247 | static void | |
248 | mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd, | |
249 | unsigned int status) | |
250 | { | |
251 | void __iomem *base = host->base; | |
252 | ||
253 | host->cmd = NULL; | |
254 | ||
255 | cmd->resp[0] = readl(base + MMCIRESPONSE0); | |
256 | cmd->resp[1] = readl(base + MMCIRESPONSE1); | |
257 | cmd->resp[2] = readl(base + MMCIRESPONSE2); | |
258 | cmd->resp[3] = readl(base + MMCIRESPONSE3); | |
259 | ||
260 | if (status & MCI_CMDTIMEOUT) { | |
17b0429d | 261 | cmd->error = -ETIMEDOUT; |
1da177e4 | 262 | } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) { |
17b0429d | 263 | cmd->error = -EILSEQ; |
1da177e4 LT |
264 | } |
265 | ||
17b0429d | 266 | if (!cmd->data || cmd->error) { |
e47c222b RK |
267 | if (host->data) |
268 | mmci_stop_data(host); | |
1da177e4 LT |
269 | mmci_request_end(host, cmd->mrq); |
270 | } else if (!(cmd->data->flags & MMC_DATA_READ)) { | |
271 | mmci_start_data(host, cmd->data); | |
272 | } | |
273 | } | |
274 | ||
275 | static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain) | |
276 | { | |
277 | void __iomem *base = host->base; | |
278 | char *ptr = buffer; | |
279 | u32 status; | |
26eed9a5 | 280 | int host_remain = host->size; |
1da177e4 LT |
281 | |
282 | do { | |
26eed9a5 | 283 | int count = host_remain - (readl(base + MMCIFIFOCNT) << 2); |
1da177e4 LT |
284 | |
285 | if (count > remain) | |
286 | count = remain; | |
287 | ||
288 | if (count <= 0) | |
289 | break; | |
290 | ||
291 | readsl(base + MMCIFIFO, ptr, count >> 2); | |
292 | ||
293 | ptr += count; | |
294 | remain -= count; | |
26eed9a5 | 295 | host_remain -= count; |
1da177e4 LT |
296 | |
297 | if (remain == 0) | |
298 | break; | |
299 | ||
300 | status = readl(base + MMCISTATUS); | |
301 | } while (status & MCI_RXDATAAVLBL); | |
302 | ||
303 | return ptr - buffer; | |
304 | } | |
305 | ||
306 | static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status) | |
307 | { | |
308 | void __iomem *base = host->base; | |
309 | char *ptr = buffer; | |
310 | ||
311 | do { | |
312 | unsigned int count, maxcnt; | |
313 | ||
314 | maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE; | |
315 | count = min(remain, maxcnt); | |
316 | ||
317 | writesl(base + MMCIFIFO, ptr, count >> 2); | |
318 | ||
319 | ptr += count; | |
320 | remain -= count; | |
321 | ||
322 | if (remain == 0) | |
323 | break; | |
324 | ||
325 | status = readl(base + MMCISTATUS); | |
326 | } while (status & MCI_TXFIFOHALFEMPTY); | |
327 | ||
328 | return ptr - buffer; | |
329 | } | |
330 | ||
331 | /* | |
332 | * PIO data transfer IRQ handler. | |
333 | */ | |
7d12e780 | 334 | static irqreturn_t mmci_pio_irq(int irq, void *dev_id) |
1da177e4 LT |
335 | { |
336 | struct mmci_host *host = dev_id; | |
4ce1d6cb | 337 | struct sg_mapping_iter *sg_miter = &host->sg_miter; |
1da177e4 | 338 | void __iomem *base = host->base; |
4ce1d6cb | 339 | unsigned long flags; |
1da177e4 LT |
340 | u32 status; |
341 | ||
342 | status = readl(base + MMCISTATUS); | |
343 | ||
64de0289 | 344 | dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status); |
1da177e4 | 345 | |
4ce1d6cb RV |
346 | local_irq_save(flags); |
347 | ||
1da177e4 | 348 | do { |
1da177e4 LT |
349 | unsigned int remain, len; |
350 | char *buffer; | |
351 | ||
352 | /* | |
353 | * For write, we only need to test the half-empty flag | |
354 | * here - if the FIFO is completely empty, then by | |
355 | * definition it is more than half empty. | |
356 | * | |
357 | * For read, check for data available. | |
358 | */ | |
359 | if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL))) | |
360 | break; | |
361 | ||
4ce1d6cb RV |
362 | if (!sg_miter_next(sg_miter)) |
363 | break; | |
364 | ||
365 | buffer = sg_miter->addr; | |
366 | remain = sg_miter->length; | |
1da177e4 LT |
367 | |
368 | len = 0; | |
369 | if (status & MCI_RXACTIVE) | |
370 | len = mmci_pio_read(host, buffer, remain); | |
371 | if (status & MCI_TXACTIVE) | |
372 | len = mmci_pio_write(host, buffer, remain, status); | |
373 | ||
4ce1d6cb | 374 | sg_miter->consumed = len; |
1da177e4 | 375 | |
1da177e4 LT |
376 | host->size -= len; |
377 | remain -= len; | |
378 | ||
379 | if (remain) | |
380 | break; | |
381 | ||
e9c091b4 | 382 | if (status & MCI_RXACTIVE) |
4ce1d6cb | 383 | flush_dcache_page(sg_miter->page); |
1da177e4 LT |
384 | |
385 | status = readl(base + MMCISTATUS); | |
386 | } while (1); | |
387 | ||
4ce1d6cb RV |
388 | sg_miter_stop(sg_miter); |
389 | ||
390 | local_irq_restore(flags); | |
391 | ||
1da177e4 LT |
392 | /* |
393 | * If we're nearing the end of the read, switch to | |
394 | * "any data available" mode. | |
395 | */ | |
396 | if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE) | |
397 | writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1); | |
398 | ||
399 | /* | |
400 | * If we run out of data, disable the data IRQs; this | |
401 | * prevents a race where the FIFO becomes empty before | |
402 | * the chip itself has disabled the data path, and | |
403 | * stops us racing with our data end IRQ. | |
404 | */ | |
405 | if (host->size == 0) { | |
406 | writel(0, base + MMCIMASK1); | |
407 | writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0); | |
408 | } | |
409 | ||
410 | return IRQ_HANDLED; | |
411 | } | |
412 | ||
413 | /* | |
414 | * Handle completion of command and data transfers. | |
415 | */ | |
7d12e780 | 416 | static irqreturn_t mmci_irq(int irq, void *dev_id) |
1da177e4 LT |
417 | { |
418 | struct mmci_host *host = dev_id; | |
419 | u32 status; | |
420 | int ret = 0; | |
421 | ||
422 | spin_lock(&host->lock); | |
423 | ||
424 | do { | |
425 | struct mmc_command *cmd; | |
426 | struct mmc_data *data; | |
427 | ||
428 | status = readl(host->base + MMCISTATUS); | |
429 | status &= readl(host->base + MMCIMASK0); | |
430 | writel(status, host->base + MMCICLEAR); | |
431 | ||
64de0289 | 432 | dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status); |
1da177e4 LT |
433 | |
434 | data = host->data; | |
435 | if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN| | |
436 | MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data) | |
437 | mmci_data_irq(host, data, status); | |
438 | ||
439 | cmd = host->cmd; | |
440 | if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd) | |
441 | mmci_cmd_irq(host, cmd, status); | |
442 | ||
443 | ret = 1; | |
444 | } while (status); | |
445 | ||
446 | spin_unlock(&host->lock); | |
447 | ||
448 | return IRQ_RETVAL(ret); | |
449 | } | |
450 | ||
451 | static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
452 | { | |
453 | struct mmci_host *host = mmc_priv(mmc); | |
9e943021 | 454 | unsigned long flags; |
1da177e4 LT |
455 | |
456 | WARN_ON(host->mrq != NULL); | |
457 | ||
019a5f56 | 458 | if (mrq->data && !is_power_of_2(mrq->data->blksz)) { |
64de0289 LW |
459 | dev_err(mmc_dev(mmc), "unsupported block size (%d bytes)\n", |
460 | mrq->data->blksz); | |
255d01af PO |
461 | mrq->cmd->error = -EINVAL; |
462 | mmc_request_done(mmc, mrq); | |
463 | return; | |
464 | } | |
465 | ||
9e943021 | 466 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 LT |
467 | |
468 | host->mrq = mrq; | |
469 | ||
470 | if (mrq->data && mrq->data->flags & MMC_DATA_READ) | |
471 | mmci_start_data(host, mrq->data); | |
472 | ||
473 | mmci_start_command(host, mrq->cmd, 0); | |
474 | ||
9e943021 | 475 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
476 | } |
477 | ||
478 | static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
479 | { | |
480 | struct mmci_host *host = mmc_priv(mmc); | |
a6a6464a LW |
481 | u32 pwr = 0; |
482 | unsigned long flags; | |
1da177e4 | 483 | |
1da177e4 LT |
484 | switch (ios->power_mode) { |
485 | case MMC_POWER_OFF: | |
34e84f39 LW |
486 | if(host->vcc && |
487 | regulator_is_enabled(host->vcc)) | |
488 | regulator_disable(host->vcc); | |
1da177e4 LT |
489 | break; |
490 | case MMC_POWER_UP: | |
34e84f39 LW |
491 | #ifdef CONFIG_REGULATOR |
492 | if (host->vcc) | |
493 | /* This implicitly enables the regulator */ | |
494 | mmc_regulator_set_ocr(host->vcc, ios->vdd); | |
495 | #endif | |
496 | /* | |
497 | * The translate_vdd function is not used if you have | |
498 | * an external regulator, or your design is really weird. | |
499 | * Using it would mean sending in power control BOTH using | |
500 | * a regulator AND the 4 MMCIPWR bits. If we don't have | |
501 | * a regulator, we might have some other platform specific | |
502 | * power control behind this translate function. | |
503 | */ | |
504 | if (!host->vcc && host->plat->translate_vdd) | |
505 | pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd); | |
cc30d60e | 506 | /* The ST version does not have this, fall through to POWER_ON */ |
f17a1f06 | 507 | if (host->hw_designer != AMBA_VENDOR_ST) { |
cc30d60e LW |
508 | pwr |= MCI_PWR_UP; |
509 | break; | |
510 | } | |
1da177e4 LT |
511 | case MMC_POWER_ON: |
512 | pwr |= MCI_PWR_ON; | |
513 | break; | |
514 | } | |
515 | ||
cc30d60e | 516 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) { |
f17a1f06 | 517 | if (host->hw_designer != AMBA_VENDOR_ST) |
cc30d60e LW |
518 | pwr |= MCI_ROD; |
519 | else { | |
520 | /* | |
521 | * The ST Micro variant use the ROD bit for something | |
522 | * else and only has OD (Open Drain). | |
523 | */ | |
524 | pwr |= MCI_OD; | |
525 | } | |
526 | } | |
1da177e4 | 527 | |
a6a6464a LW |
528 | spin_lock_irqsave(&host->lock, flags); |
529 | ||
530 | mmci_set_clkreg(host, ios->clock); | |
1da177e4 LT |
531 | |
532 | if (host->pwr != pwr) { | |
533 | host->pwr = pwr; | |
534 | writel(pwr, host->base + MMCIPOWER); | |
535 | } | |
a6a6464a LW |
536 | |
537 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
538 | } |
539 | ||
89001446 RK |
540 | static int mmci_get_ro(struct mmc_host *mmc) |
541 | { | |
542 | struct mmci_host *host = mmc_priv(mmc); | |
543 | ||
544 | if (host->gpio_wp == -ENOSYS) | |
545 | return -ENOSYS; | |
546 | ||
547 | return gpio_get_value(host->gpio_wp); | |
548 | } | |
549 | ||
550 | static int mmci_get_cd(struct mmc_host *mmc) | |
551 | { | |
552 | struct mmci_host *host = mmc_priv(mmc); | |
553 | unsigned int status; | |
554 | ||
555 | if (host->gpio_cd == -ENOSYS) | |
556 | status = host->plat->status(mmc_dev(host->mmc)); | |
557 | else | |
558 | status = gpio_get_value(host->gpio_cd); | |
559 | ||
560 | return !status; | |
561 | } | |
562 | ||
ab7aefd0 | 563 | static const struct mmc_host_ops mmci_ops = { |
1da177e4 LT |
564 | .request = mmci_request, |
565 | .set_ios = mmci_set_ios, | |
89001446 RK |
566 | .get_ro = mmci_get_ro, |
567 | .get_cd = mmci_get_cd, | |
1da177e4 LT |
568 | }; |
569 | ||
03fbdb15 | 570 | static int __devinit mmci_probe(struct amba_device *dev, struct amba_id *id) |
1da177e4 | 571 | { |
6ef297f8 | 572 | struct mmci_platform_data *plat = dev->dev.platform_data; |
1da177e4 LT |
573 | struct mmci_host *host; |
574 | struct mmc_host *mmc; | |
575 | int ret; | |
576 | ||
577 | /* must have platform data */ | |
578 | if (!plat) { | |
579 | ret = -EINVAL; | |
580 | goto out; | |
581 | } | |
582 | ||
583 | ret = amba_request_regions(dev, DRIVER_NAME); | |
584 | if (ret) | |
585 | goto out; | |
586 | ||
587 | mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev); | |
588 | if (!mmc) { | |
589 | ret = -ENOMEM; | |
590 | goto rel_regions; | |
591 | } | |
592 | ||
593 | host = mmc_priv(mmc); | |
4ea580f1 | 594 | host->mmc = mmc; |
012b7d33 | 595 | |
89001446 RK |
596 | host->gpio_wp = -ENOSYS; |
597 | host->gpio_cd = -ENOSYS; | |
598 | ||
012b7d33 RK |
599 | host->hw_designer = amba_manf(dev); |
600 | host->hw_revision = amba_rev(dev); | |
64de0289 LW |
601 | dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer); |
602 | dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision); | |
012b7d33 | 603 | |
ee569c43 | 604 | host->clk = clk_get(&dev->dev, NULL); |
1da177e4 LT |
605 | if (IS_ERR(host->clk)) { |
606 | ret = PTR_ERR(host->clk); | |
607 | host->clk = NULL; | |
608 | goto host_free; | |
609 | } | |
610 | ||
1da177e4 LT |
611 | ret = clk_enable(host->clk); |
612 | if (ret) | |
a8d3584a | 613 | goto clk_free; |
1da177e4 LT |
614 | |
615 | host->plat = plat; | |
616 | host->mclk = clk_get_rate(host->clk); | |
c8df9a53 LW |
617 | /* |
618 | * According to the spec, mclk is max 100 MHz, | |
619 | * so we try to adjust the clock down to this, | |
620 | * (if possible). | |
621 | */ | |
622 | if (host->mclk > 100000000) { | |
623 | ret = clk_set_rate(host->clk, 100000000); | |
624 | if (ret < 0) | |
625 | goto clk_disable; | |
626 | host->mclk = clk_get_rate(host->clk); | |
64de0289 LW |
627 | dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n", |
628 | host->mclk); | |
c8df9a53 | 629 | } |
dc890c2d | 630 | host->base = ioremap(dev->res.start, resource_size(&dev->res)); |
1da177e4 LT |
631 | if (!host->base) { |
632 | ret = -ENOMEM; | |
633 | goto clk_disable; | |
634 | } | |
635 | ||
636 | mmc->ops = &mmci_ops; | |
637 | mmc->f_min = (host->mclk + 511) / 512; | |
808d97cc LW |
638 | /* |
639 | * If the platform data supplies a maximum operating | |
640 | * frequency, this takes precedence. Else, we fall back | |
641 | * to using the module parameter, which has a (low) | |
642 | * default value in case it is not specified. Either | |
643 | * value must not exceed the clock rate into the block, | |
644 | * of course. | |
645 | */ | |
646 | if (plat->f_max) | |
647 | mmc->f_max = min(host->mclk, plat->f_max); | |
648 | else | |
649 | mmc->f_max = min(host->mclk, fmax); | |
64de0289 LW |
650 | dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max); |
651 | ||
34e84f39 LW |
652 | #ifdef CONFIG_REGULATOR |
653 | /* If we're using the regulator framework, try to fetch a regulator */ | |
654 | host->vcc = regulator_get(&dev->dev, "vmmc"); | |
655 | if (IS_ERR(host->vcc)) | |
656 | host->vcc = NULL; | |
657 | else { | |
658 | int mask = mmc_regulator_get_ocrmask(host->vcc); | |
659 | ||
660 | if (mask < 0) | |
661 | dev_err(&dev->dev, "error getting OCR mask (%d)\n", | |
662 | mask); | |
663 | else { | |
664 | host->mmc->ocr_avail = (u32) mask; | |
665 | if (plat->ocr_mask) | |
666 | dev_warn(&dev->dev, | |
667 | "Provided ocr_mask/setpower will not be used " | |
668 | "(using regulator instead)\n"); | |
669 | } | |
670 | } | |
671 | #endif | |
672 | /* Fall back to platform data if no regulator is found */ | |
673 | if (host->vcc == NULL) | |
674 | mmc->ocr_avail = plat->ocr_mask; | |
9e6c82cd | 675 | mmc->caps = plat->capabilities; |
f5e2574e | 676 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
1da177e4 LT |
677 | |
678 | /* | |
679 | * We can do SGIO | |
680 | */ | |
681 | mmc->max_hw_segs = 16; | |
682 | mmc->max_phys_segs = NR_SG; | |
683 | ||
684 | /* | |
685 | * Since we only have a 16-bit data length register, we must | |
686 | * ensure that we don't exceed 2^16-1 bytes in a single request. | |
1da177e4 | 687 | */ |
55db890a | 688 | mmc->max_req_size = 65535; |
1da177e4 LT |
689 | |
690 | /* | |
691 | * Set the maximum segment size. Since we aren't doing DMA | |
692 | * (yet) we are only limited by the data length register. | |
693 | */ | |
55db890a | 694 | mmc->max_seg_size = mmc->max_req_size; |
1da177e4 | 695 | |
fe4a3c7a PO |
696 | /* |
697 | * Block size can be up to 2048 bytes, but must be a power of two. | |
698 | */ | |
699 | mmc->max_blk_size = 2048; | |
700 | ||
55db890a PO |
701 | /* |
702 | * No limit on the number of blocks transferred. | |
703 | */ | |
704 | mmc->max_blk_count = mmc->max_req_size; | |
705 | ||
1da177e4 LT |
706 | spin_lock_init(&host->lock); |
707 | ||
708 | writel(0, host->base + MMCIMASK0); | |
709 | writel(0, host->base + MMCIMASK1); | |
710 | writel(0xfff, host->base + MMCICLEAR); | |
711 | ||
89001446 RK |
712 | if (gpio_is_valid(plat->gpio_cd)) { |
713 | ret = gpio_request(plat->gpio_cd, DRIVER_NAME " (cd)"); | |
714 | if (ret == 0) | |
715 | ret = gpio_direction_input(plat->gpio_cd); | |
716 | if (ret == 0) | |
717 | host->gpio_cd = plat->gpio_cd; | |
718 | else if (ret != -ENOSYS) | |
719 | goto err_gpio_cd; | |
720 | } | |
721 | if (gpio_is_valid(plat->gpio_wp)) { | |
722 | ret = gpio_request(plat->gpio_wp, DRIVER_NAME " (wp)"); | |
723 | if (ret == 0) | |
724 | ret = gpio_direction_input(plat->gpio_wp); | |
725 | if (ret == 0) | |
726 | host->gpio_wp = plat->gpio_wp; | |
727 | else if (ret != -ENOSYS) | |
728 | goto err_gpio_wp; | |
729 | } | |
730 | ||
dace1453 | 731 | ret = request_irq(dev->irq[0], mmci_irq, IRQF_SHARED, DRIVER_NAME " (cmd)", host); |
1da177e4 LT |
732 | if (ret) |
733 | goto unmap; | |
734 | ||
dace1453 | 735 | ret = request_irq(dev->irq[1], mmci_pio_irq, IRQF_SHARED, DRIVER_NAME " (pio)", host); |
1da177e4 LT |
736 | if (ret) |
737 | goto irq0_free; | |
738 | ||
739 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
740 | ||
741 | amba_set_drvdata(dev, mmc); | |
742 | ||
743 | mmc_add_host(mmc); | |
744 | ||
64de0289 | 745 | dev_info(&dev->dev, "%s: MMCI rev %x cfg %02x at 0x%016llx irq %d,%d\n", |
d366b643 | 746 | mmc_hostname(mmc), amba_rev(dev), amba_config(dev), |
e29419ff | 747 | (unsigned long long)dev->res.start, dev->irq[0], dev->irq[1]); |
1da177e4 | 748 | |
1da177e4 LT |
749 | return 0; |
750 | ||
751 | irq0_free: | |
752 | free_irq(dev->irq[0], host); | |
753 | unmap: | |
89001446 RK |
754 | if (host->gpio_wp != -ENOSYS) |
755 | gpio_free(host->gpio_wp); | |
756 | err_gpio_wp: | |
757 | if (host->gpio_cd != -ENOSYS) | |
758 | gpio_free(host->gpio_cd); | |
759 | err_gpio_cd: | |
1da177e4 LT |
760 | iounmap(host->base); |
761 | clk_disable: | |
762 | clk_disable(host->clk); | |
1da177e4 LT |
763 | clk_free: |
764 | clk_put(host->clk); | |
765 | host_free: | |
766 | mmc_free_host(mmc); | |
767 | rel_regions: | |
768 | amba_release_regions(dev); | |
769 | out: | |
770 | return ret; | |
771 | } | |
772 | ||
6dc4a47a | 773 | static int __devexit mmci_remove(struct amba_device *dev) |
1da177e4 LT |
774 | { |
775 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
776 | ||
777 | amba_set_drvdata(dev, NULL); | |
778 | ||
779 | if (mmc) { | |
780 | struct mmci_host *host = mmc_priv(mmc); | |
781 | ||
1da177e4 LT |
782 | mmc_remove_host(mmc); |
783 | ||
784 | writel(0, host->base + MMCIMASK0); | |
785 | writel(0, host->base + MMCIMASK1); | |
786 | ||
787 | writel(0, host->base + MMCICOMMAND); | |
788 | writel(0, host->base + MMCIDATACTRL); | |
789 | ||
790 | free_irq(dev->irq[0], host); | |
791 | free_irq(dev->irq[1], host); | |
792 | ||
89001446 RK |
793 | if (host->gpio_wp != -ENOSYS) |
794 | gpio_free(host->gpio_wp); | |
795 | if (host->gpio_cd != -ENOSYS) | |
796 | gpio_free(host->gpio_cd); | |
797 | ||
1da177e4 LT |
798 | iounmap(host->base); |
799 | clk_disable(host->clk); | |
1da177e4 LT |
800 | clk_put(host->clk); |
801 | ||
34e84f39 LW |
802 | if (regulator_is_enabled(host->vcc)) |
803 | regulator_disable(host->vcc); | |
804 | regulator_put(host->vcc); | |
805 | ||
1da177e4 LT |
806 | mmc_free_host(mmc); |
807 | ||
808 | amba_release_regions(dev); | |
809 | } | |
810 | ||
811 | return 0; | |
812 | } | |
813 | ||
814 | #ifdef CONFIG_PM | |
e5378ca8 | 815 | static int mmci_suspend(struct amba_device *dev, pm_message_t state) |
1da177e4 LT |
816 | { |
817 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
818 | int ret = 0; | |
819 | ||
820 | if (mmc) { | |
821 | struct mmci_host *host = mmc_priv(mmc); | |
822 | ||
1a13f8fa | 823 | ret = mmc_suspend_host(mmc); |
1da177e4 LT |
824 | if (ret == 0) |
825 | writel(0, host->base + MMCIMASK0); | |
826 | } | |
827 | ||
828 | return ret; | |
829 | } | |
830 | ||
831 | static int mmci_resume(struct amba_device *dev) | |
832 | { | |
833 | struct mmc_host *mmc = amba_get_drvdata(dev); | |
834 | int ret = 0; | |
835 | ||
836 | if (mmc) { | |
837 | struct mmci_host *host = mmc_priv(mmc); | |
838 | ||
839 | writel(MCI_IRQENABLE, host->base + MMCIMASK0); | |
840 | ||
841 | ret = mmc_resume_host(mmc); | |
842 | } | |
843 | ||
844 | return ret; | |
845 | } | |
846 | #else | |
847 | #define mmci_suspend NULL | |
848 | #define mmci_resume NULL | |
849 | #endif | |
850 | ||
851 | static struct amba_id mmci_ids[] = { | |
852 | { | |
853 | .id = 0x00041180, | |
854 | .mask = 0x000fffff, | |
855 | }, | |
856 | { | |
857 | .id = 0x00041181, | |
858 | .mask = 0x000fffff, | |
859 | }, | |
cc30d60e LW |
860 | /* ST Micro variants */ |
861 | { | |
862 | .id = 0x00180180, | |
863 | .mask = 0x00ffffff, | |
864 | }, | |
865 | { | |
866 | .id = 0x00280180, | |
867 | .mask = 0x00ffffff, | |
868 | }, | |
1da177e4 LT |
869 | { 0, 0 }, |
870 | }; | |
871 | ||
872 | static struct amba_driver mmci_driver = { | |
873 | .drv = { | |
874 | .name = DRIVER_NAME, | |
875 | }, | |
876 | .probe = mmci_probe, | |
6dc4a47a | 877 | .remove = __devexit_p(mmci_remove), |
1da177e4 LT |
878 | .suspend = mmci_suspend, |
879 | .resume = mmci_resume, | |
880 | .id_table = mmci_ids, | |
881 | }; | |
882 | ||
883 | static int __init mmci_init(void) | |
884 | { | |
885 | return amba_driver_register(&mmci_driver); | |
886 | } | |
887 | ||
888 | static void __exit mmci_exit(void) | |
889 | { | |
890 | amba_driver_unregister(&mmci_driver); | |
891 | } | |
892 | ||
893 | module_init(mmci_init); | |
894 | module_exit(mmci_exit); | |
895 | module_param(fmax, uint, 0444); | |
896 | ||
897 | MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver"); | |
898 | MODULE_LICENSE("GPL"); |