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1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | #define MMCIPOWER 0x000 | |
11 | #define MCI_PWR_OFF 0x00 | |
12 | #define MCI_PWR_UP 0x02 | |
13 | #define MCI_PWR_ON 0x03 | |
14 | #define MCI_OD (1 << 6) | |
15 | #define MCI_ROD (1 << 7) | |
16 | ||
17 | #define MMCICLOCK 0x004 | |
18 | #define MCI_CLK_ENABLE (1 << 8) | |
19 | #define MCI_CLK_PWRSAVE (1 << 9) | |
20 | #define MCI_CLK_BYPASS (1 << 10) | |
771dc157 | 21 | #define MCI_4BIT_BUS (1 << 11) |
49ac215e LW |
22 | /* |
23 | * 8bit wide buses, hardware flow contronl, negative edges and clock inversion | |
24 | * supported in ST Micro U300 and Ux500 versions | |
25 | */ | |
771dc157 | 26 | #define MCI_ST_8BIT_BUS (1 << 12) |
49ac215e LW |
27 | #define MCI_ST_U300_HWFCEN (1 << 13) |
28 | #define MCI_ST_UX500_NEG_EDGE (1 << 13) | |
29 | #define MCI_ST_UX500_HWFCEN (1 << 14) | |
30 | #define MCI_ST_UX500_CLK_INV (1 << 15) | |
3a37298a PM |
31 | /* Modified PL180 on Versatile Express platform */ |
32 | #define MCI_ARM_HWFCEN (1 << 12) | |
1da177e4 LT |
33 | |
34 | #define MMCIARGUMENT 0x008 | |
35 | #define MMCICOMMAND 0x00c | |
36 | #define MCI_CPSM_RESPONSE (1 << 6) | |
37 | #define MCI_CPSM_LONGRSP (1 << 7) | |
38 | #define MCI_CPSM_INTERRUPT (1 << 8) | |
39 | #define MCI_CPSM_PENDING (1 << 9) | |
40 | #define MCI_CPSM_ENABLE (1 << 10) | |
dfdf5f63 LW |
41 | /* Argument flag extenstions in the ST Micro versions */ |
42 | #define MCI_ST_SDIO_SUSP (1 << 11) | |
43 | #define MCI_ST_ENCMD_COMPL (1 << 12) | |
44 | #define MCI_ST_NIEN (1 << 13) | |
45 | #define MCI_ST_CE_ATACMD (1 << 14) | |
1da177e4 LT |
46 | |
47 | #define MMCIRESPCMD 0x010 | |
48 | #define MMCIRESPONSE0 0x014 | |
49 | #define MMCIRESPONSE1 0x018 | |
50 | #define MMCIRESPONSE2 0x01c | |
51 | #define MMCIRESPONSE3 0x020 | |
52 | #define MMCIDATATIMER 0x024 | |
53 | #define MMCIDATALENGTH 0x028 | |
54 | #define MMCIDATACTRL 0x02c | |
55 | #define MCI_DPSM_ENABLE (1 << 0) | |
56 | #define MCI_DPSM_DIRECTION (1 << 1) | |
57 | #define MCI_DPSM_MODE (1 << 2) | |
58 | #define MCI_DPSM_DMAENABLE (1 << 3) | |
cc30d60e | 59 | #define MCI_DPSM_BLOCKSIZE (1 << 4) |
725343fa LW |
60 | /* Control register extensions in the ST Micro U300 and Ux500 versions */ |
61 | #define MCI_ST_DPSM_RWSTART (1 << 8) | |
62 | #define MCI_ST_DPSM_RWSTOP (1 << 9) | |
63 | #define MCI_ST_DPSM_RWMOD (1 << 10) | |
64 | #define MCI_ST_DPSM_SDIOEN (1 << 11) | |
65 | /* Control register extensions in the ST Micro Ux500 versions */ | |
66 | #define MCI_ST_DPSM_DMAREQCTL (1 << 12) | |
67 | #define MCI_ST_DPSM_DBOOTMODEEN (1 << 13) | |
68 | #define MCI_ST_DPSM_BUSYMODE (1 << 14) | |
69 | #define MCI_ST_DPSM_DDRMODE (1 << 15) | |
1da177e4 LT |
70 | |
71 | #define MMCIDATACNT 0x030 | |
72 | #define MMCISTATUS 0x034 | |
73 | #define MCI_CMDCRCFAIL (1 << 0) | |
74 | #define MCI_DATACRCFAIL (1 << 1) | |
75 | #define MCI_CMDTIMEOUT (1 << 2) | |
76 | #define MCI_DATATIMEOUT (1 << 3) | |
77 | #define MCI_TXUNDERRUN (1 << 4) | |
78 | #define MCI_RXOVERRUN (1 << 5) | |
79 | #define MCI_CMDRESPEND (1 << 6) | |
80 | #define MCI_CMDSENT (1 << 7) | |
81 | #define MCI_DATAEND (1 << 8) | |
757df746 | 82 | #define MCI_STARTBITERR (1 << 9) |
1da177e4 LT |
83 | #define MCI_DATABLOCKEND (1 << 10) |
84 | #define MCI_CMDACTIVE (1 << 11) | |
85 | #define MCI_TXACTIVE (1 << 12) | |
86 | #define MCI_RXACTIVE (1 << 13) | |
87 | #define MCI_TXFIFOHALFEMPTY (1 << 14) | |
88 | #define MCI_RXFIFOHALFFULL (1 << 15) | |
89 | #define MCI_TXFIFOFULL (1 << 16) | |
90 | #define MCI_RXFIFOFULL (1 << 17) | |
91 | #define MCI_TXFIFOEMPTY (1 << 18) | |
92 | #define MCI_RXFIFOEMPTY (1 << 19) | |
93 | #define MCI_TXDATAAVLBL (1 << 20) | |
94 | #define MCI_RXDATAAVLBL (1 << 21) | |
49ac215e LW |
95 | /* Extended status bits for the ST Micro variants */ |
96 | #define MCI_ST_SDIOIT (1 << 22) | |
97 | #define MCI_ST_CEATAEND (1 << 23) | |
01259620 | 98 | #define MCI_ST_CARDBUSY (1 << 24) |
1da177e4 LT |
99 | |
100 | #define MMCICLEAR 0x038 | |
101 | #define MCI_CMDCRCFAILCLR (1 << 0) | |
102 | #define MCI_DATACRCFAILCLR (1 << 1) | |
103 | #define MCI_CMDTIMEOUTCLR (1 << 2) | |
104 | #define MCI_DATATIMEOUTCLR (1 << 3) | |
105 | #define MCI_TXUNDERRUNCLR (1 << 4) | |
106 | #define MCI_RXOVERRUNCLR (1 << 5) | |
107 | #define MCI_CMDRESPENDCLR (1 << 6) | |
108 | #define MCI_CMDSENTCLR (1 << 7) | |
109 | #define MCI_DATAENDCLR (1 << 8) | |
757df746 | 110 | #define MCI_STARTBITERRCLR (1 << 9) |
1da177e4 | 111 | #define MCI_DATABLOCKENDCLR (1 << 10) |
49ac215e LW |
112 | /* Extended status bits for the ST Micro variants */ |
113 | #define MCI_ST_SDIOITC (1 << 22) | |
114 | #define MCI_ST_CEATAENDC (1 << 23) | |
01259620 | 115 | #define MCI_ST_BUSYENDC (1 << 24) |
1da177e4 LT |
116 | |
117 | #define MMCIMASK0 0x03c | |
118 | #define MCI_CMDCRCFAILMASK (1 << 0) | |
119 | #define MCI_DATACRCFAILMASK (1 << 1) | |
120 | #define MCI_CMDTIMEOUTMASK (1 << 2) | |
121 | #define MCI_DATATIMEOUTMASK (1 << 3) | |
122 | #define MCI_TXUNDERRUNMASK (1 << 4) | |
123 | #define MCI_RXOVERRUNMASK (1 << 5) | |
124 | #define MCI_CMDRESPENDMASK (1 << 6) | |
125 | #define MCI_CMDSENTMASK (1 << 7) | |
126 | #define MCI_DATAENDMASK (1 << 8) | |
757df746 | 127 | #define MCI_STARTBITERRMASK (1 << 9) |
1da177e4 LT |
128 | #define MCI_DATABLOCKENDMASK (1 << 10) |
129 | #define MCI_CMDACTIVEMASK (1 << 11) | |
130 | #define MCI_TXACTIVEMASK (1 << 12) | |
131 | #define MCI_RXACTIVEMASK (1 << 13) | |
132 | #define MCI_TXFIFOHALFEMPTYMASK (1 << 14) | |
133 | #define MCI_RXFIFOHALFFULLMASK (1 << 15) | |
134 | #define MCI_TXFIFOFULLMASK (1 << 16) | |
135 | #define MCI_RXFIFOFULLMASK (1 << 17) | |
136 | #define MCI_TXFIFOEMPTYMASK (1 << 18) | |
137 | #define MCI_RXFIFOEMPTYMASK (1 << 19) | |
138 | #define MCI_TXDATAAVLBLMASK (1 << 20) | |
139 | #define MCI_RXDATAAVLBLMASK (1 << 21) | |
49ac215e LW |
140 | /* Extended status bits for the ST Micro variants */ |
141 | #define MCI_ST_SDIOITMASK (1 << 22) | |
142 | #define MCI_ST_CEATAENDMASK (1 << 23) | |
8d94b54d | 143 | #define MCI_ST_BUSYEND (1 << 24) |
1da177e4 LT |
144 | |
145 | #define MMCIMASK1 0x040 | |
146 | #define MMCIFIFOCNT 0x048 | |
147 | #define MMCIFIFO 0x080 /* to 0x0bc */ | |
148 | ||
149 | #define MCI_IRQENABLE \ | |
150 | (MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \ | |
151 | MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \ | |
757df746 | 152 | MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK) |
1da177e4 | 153 | |
2686b4b4 LW |
154 | /* These interrupts are directed to IRQ1 when two IRQ lines are available */ |
155 | #define MCI_IRQ1MASK \ | |
156 | (MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \ | |
157 | MCI_TXFIFOHALFEMPTYMASK) | |
158 | ||
859dd55d | 159 | #define NR_SG 128 |
1da177e4 LT |
160 | |
161 | struct clk; | |
4956e109 | 162 | struct variant_data; |
c8ebae37 | 163 | struct dma_chan; |
1da177e4 | 164 | |
58c7ccbf PF |
165 | struct mmci_host_next { |
166 | struct dma_async_tx_descriptor *dma_desc; | |
167 | struct dma_chan *dma_chan; | |
168 | s32 cookie; | |
169 | }; | |
170 | ||
1da177e4 | 171 | struct mmci_host { |
c8ebae37 | 172 | phys_addr_t phybase; |
1da177e4 LT |
173 | void __iomem *base; |
174 | struct mmc_request *mrq; | |
175 | struct mmc_command *cmd; | |
176 | struct mmc_data *data; | |
177 | struct mmc_host *mmc; | |
178 | struct clk *clk; | |
89001446 RK |
179 | int gpio_cd; |
180 | int gpio_wp; | |
148b8b39 | 181 | int gpio_cd_irq; |
2686b4b4 | 182 | bool singleirq; |
1da177e4 | 183 | |
1da177e4 LT |
184 | spinlock_t lock; |
185 | ||
186 | unsigned int mclk; | |
187 | unsigned int cclk; | |
7437cfa5 UH |
188 | u32 pwr_reg; |
189 | u32 clk_reg; | |
9cc639a2 | 190 | u32 datactrl_reg; |
8d94b54d | 191 | u32 busy_status; |
7c0136ef | 192 | bool vqmmc_enabled; |
6ef297f8 | 193 | struct mmci_platform_data *plat; |
4956e109 | 194 | struct variant_data *variant; |
1da177e4 | 195 | |
cc30d60e LW |
196 | u8 hw_designer; |
197 | u8 hw_revision:4; | |
198 | ||
1da177e4 LT |
199 | struct timer_list timer; |
200 | unsigned int oldstat; | |
201 | ||
1da177e4 | 202 | /* pio stuff */ |
4ce1d6cb | 203 | struct sg_mapping_iter sg_miter; |
1da177e4 | 204 | unsigned int size; |
c8ebae37 RK |
205 | |
206 | #ifdef CONFIG_DMA_ENGINE | |
207 | /* DMA stuff */ | |
208 | struct dma_chan *dma_current; | |
209 | struct dma_chan *dma_rx_channel; | |
210 | struct dma_chan *dma_tx_channel; | |
58c7ccbf PF |
211 | struct dma_async_tx_descriptor *dma_desc_current; |
212 | struct mmci_host_next next_data; | |
c8ebae37 RK |
213 | |
214 | #define dma_inprogress(host) ((host)->dma_current) | |
215 | #else | |
216 | #define dma_inprogress(host) (0) | |
217 | #endif | |
1da177e4 LT |
218 | }; |
219 |