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Merge branch 'msm-mmc_sdcc' of git://codeaurora.org/quic/kernel/dwalker/linux-msm
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / msm_sdcc.c
CommitLineData
9d2bd738
SM		 1/*
2 * linux/drivers/mmc/host/msm_sdcc.c - Qualcomm MSM 7X00A SDCC Driver
3 *
4 * Copyright (C) 2007 Google Inc,
5 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
56a8b5b8 6 * Copyright (C) 2009, Code Aurora Forum. All Rights Reserved.
9d2bd738
SM		 7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * Based on mmci.c
13 *
14 * Author: San Mehat (san@android.com)
15 *
16 */
17
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/init.h>
21#include <linux/ioport.h>
22#include <linux/device.h>
23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/err.h>
26#include <linux/highmem.h>
27#include <linux/log2.h>
28#include <linux/mmc/host.h>
29#include <linux/mmc/card.h>
b3fa5791 30#include <linux/mmc/sdio.h>
9d2bd738
SM		 31#include <linux/clk.h>
32#include <linux/scatterlist.h>
33#include <linux/platform_device.h>
34#include <linux/dma-mapping.h>
35#include <linux/debugfs.h>
36#include <linux/io.h>
37#include <linux/memory.h>
5a0e3ad6 38#include <linux/gfp.h>
9d2bd738
SM		 39
40#include <asm/cacheflush.h>
41#include <asm/div64.h>
42#include <asm/sizes.h>
43
3989d178 44#include <mach/mmc.h>
9d2bd738
SM		 45#include <mach/msm_iomap.h>
46#include <mach/dma.h>
9d2bd738 47
9d2bd738
SM		 48#include "msm_sdcc.h"
49
50#define DRIVER_NAME "msm-sdcc"
51
24bbd7d5 52#define BUSCLK_PWRSAVE 1
c7fc9370 53#define BUSCLK_TIMEOUT (HZ)
9d2bd738
SM		 54static unsigned int msmsdcc_fmin = 144000;
55static unsigned int msmsdcc_fmax = 50000000;
56static unsigned int msmsdcc_4bit = 1;
57static unsigned int msmsdcc_pwrsave = 1;
58static unsigned int msmsdcc_piopoll = 1;
59static unsigned int msmsdcc_sdioirq;
60
61#define PIO_SPINMAX 30
62#define CMD_SPINMAX 20
63
865c8064 64
d0719e59 65static inline void
c7fc9370 66msmsdcc_disable_clocks(struct msmsdcc_host *host, int deferr)
865c8064 67{
c7fc9370 68 WARN_ON(!host->clks_on);
8b1c2ba2 69
f4748499
SM		 70 BUG_ON(host->curr.mrq);
71
c7fc9370
SM		 72 if (deferr) {
73 mod_timer(&host->busclk_timer, jiffies + BUSCLK_TIMEOUT);
865c8064 74 } else {
c7fc9370 75 del_timer_sync(&host->busclk_timer);
d0719e59
SM		 76 /* Need to check clks_on again in case the busclk
77 * timer fired
78 */
79 if (host->clks_on) {
80 clk_disable(host->clk);
81 clk_disable(host->pclk);
82 host->clks_on = 0;
83 }
865c8064 84 }
c7fc9370
SM		 85}
86
87static inline int
88msmsdcc_enable_clocks(struct msmsdcc_host *host)
89{
90 int rc;
91
c7fc9370
SM		 92 del_timer_sync(&host->busclk_timer);
93
d0719e59
SM		 94 if (!host->clks_on) {
95 rc = clk_enable(host->pclk);
96 if (rc)
97 return rc;
98 rc = clk_enable(host->clk);
99 if (rc) {
100 clk_disable(host->pclk);
101 return rc;
102 }
103 udelay(1 + ((3 * USEC_PER_SEC) /
104 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
105 host->clks_on = 1;
c7fc9370 106 }
865c8064
SM		 107 return 0;
108}
109
8b1c2ba2
SM		 110static inline unsigned int
111msmsdcc_readl(struct msmsdcc_host *host, unsigned int reg)
112{
113 return readl(host->base + reg);
114}
115
116static inline void
117msmsdcc_writel(struct msmsdcc_host *host, u32 data, unsigned int reg)
118{
119 writel(data, host->base + reg);
120 /* 3 clk delay required! */
121 udelay(1 + ((3 * USEC_PER_SEC) /
122 (host->clk_rate ? host->clk_rate : msmsdcc_fmin)));
123}
865c8064 124
9d2bd738
SM		 125static void
126msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd,
127 u32 c);
128
129static void
130msmsdcc_request_end(struct msmsdcc_host *host, struct mmc_request *mrq)
131{
9d2bd738
SM		 132 BUG_ON(host->curr.data);
133
134 host->curr.mrq = NULL;
135 host->curr.cmd = NULL;
136
137 if (mrq->data)
138 mrq->data->bytes_xfered = host->curr.data_xfered;
139 if (mrq->cmd->error == -ETIMEDOUT)
140 mdelay(5);
141
f4748499 142#if BUSCLK_PWRSAVE
c7fc9370 143 msmsdcc_disable_clocks(host, 1);
f4748499 144#endif
9d2bd738
SM		 145 /*
146 * Need to drop the host lock here; mmc_request_done may call
147 * back into the driver...
148 */
149 spin_unlock(&host->lock);
150 mmc_request_done(host->mmc, mrq);
151 spin_lock(&host->lock);
152}
153
154static void
155msmsdcc_stop_data(struct msmsdcc_host *host)
156{
9d2bd738
SM		 157 host->curr.data = NULL;
158 host->curr.got_dataend = host->curr.got_datablkend = 0;
159}
160
161uint32_t msmsdcc_fifo_addr(struct msmsdcc_host *host)
162{
edd4dd0e 163 return host->memres->start + MMCIFIFO;
9d2bd738
SM		 164}
165
56a8b5b8
SM		 166static inline void
167msmsdcc_start_command_exec(struct msmsdcc_host *host, u32 arg, u32 c) {
168 msmsdcc_writel(host, arg, MMCIARGUMENT);
169 msmsdcc_writel(host, c, MMCICOMMAND);
170}
171
172static void
173msmsdcc_dma_exec_func(struct msm_dmov_cmd *cmd)
174{
6ac9ea69 175 struct msmsdcc_host *host = (struct msmsdcc_host *)cmd->data;
56a8b5b8 176
6ac9ea69 177 msmsdcc_writel(host, host->cmd_timeout, MMCIDATATIMER);
d0719e59
SM		 178 msmsdcc_writel(host, (unsigned int)host->curr.xfer_size,
179 MMCIDATALENGTH);
6ac9ea69
SM		 180 msmsdcc_writel(host, host->cmd_pio_irqmask, MMCIMASK1);
181 msmsdcc_writel(host, host->cmd_datactrl, MMCIDATACTRL);
56a8b5b8 182
6ac9ea69
SM		 183 if (host->cmd_cmd) {
184 msmsdcc_start_command_exec(host,
185 (u32) host->cmd_cmd->arg,
186 (u32) host->cmd_c);
187 }
56a8b5b8
SM		 188 host->dma.active = 1;
189}
190
9d2bd738
SM		 191static void
192msmsdcc_dma_complete_func(struct msm_dmov_cmd *cmd,
193 unsigned int result,
194 struct msm_dmov_errdata *err)
195{
196 struct msmsdcc_dma_data *dma_data =
197 container_of(cmd, struct msmsdcc_dma_data, hdr);
198 struct msmsdcc_host *host = dma_data->host;
199 unsigned long flags;
200 struct mmc_request *mrq;
201
202 spin_lock_irqsave(&host->lock, flags);
56a8b5b8
SM		 203 host->dma.active = 0;
204
9d2bd738
SM		 205 mrq = host->curr.mrq;
206 BUG_ON(!mrq);
b3b0ca84 207 WARN_ON(!mrq->data);
9d2bd738
SM		 208
209 if (!(result & DMOV_RSLT_VALID)) {
0a7ff7c7 210 pr_err("msmsdcc: Invalid DataMover result\n");
9d2bd738
SM		 211 goto out;
212 }
213
214 if (result & DMOV_RSLT_DONE) {
215 host->curr.data_xfered = host->curr.xfer_size;
216 } else {
217 /* Error or flush */
218 if (result & DMOV_RSLT_ERROR)
0a7ff7c7 219 pr_err("%s: DMA error (0x%.8x)\n",
9d2bd738
SM		 220 mmc_hostname(host->mmc), result);
221 if (result & DMOV_RSLT_FLUSH)
0a7ff7c7 222 pr_err("%s: DMA channel flushed (0x%.8x)\n",
9d2bd738
SM		 223 mmc_hostname(host->mmc), result);
224 if (err)
0a7ff7c7 225 pr_err("Flush data: %.8x %.8x %.8x %.8x %.8x %.8x\n",
9d2bd738
SM		 226 err->flush[0], err->flush[1], err->flush[2],
227 err->flush[3], err->flush[4], err->flush[5]);
228 if (!mrq->data->error)
229 mrq->data->error = -EIO;
230 }
9d2bd738
SM		 231 dma_unmap_sg(mmc_dev(host->mmc), host->dma.sg, host->dma.num_ents,
232 host->dma.dir);
233
234 if (host->curr.user_pages) {
235 struct scatterlist *sg = host->dma.sg;
236 int i;
237
75d14528
JP		 238 for (i = 0; i < host->dma.num_ents; i++)
239 flush_dcache_page(sg_page(sg++));
9d2bd738
SM		 240 }
241
242 host->dma.sg = NULL;
56a8b5b8 243 host->dma.busy = 0;
9d2bd738
SM		 244
245 if ((host->curr.got_dataend && host->curr.got_datablkend)
246 || mrq->data->error) {
247
248 /*
249 * If we've already gotten our DATAEND / DATABLKEND
250 * for this request, then complete it through here.
251 */
252 msmsdcc_stop_data(host);
253
254 if (!mrq->data->error)
255 host->curr.data_xfered = host->curr.xfer_size;
256 if (!mrq->data->stop || mrq->cmd->error) {
9d2bd738
SM		 257 host->curr.mrq = NULL;
258 host->curr.cmd = NULL;
259 mrq->data->bytes_xfered = host->curr.data_xfered;
260
261 spin_unlock_irqrestore(&host->lock, flags);
f4748499 262#if BUSCLK_PWRSAVE
c7fc9370 263 msmsdcc_disable_clocks(host, 1);
f4748499 264#endif
9d2bd738
SM		 265 mmc_request_done(host->mmc, mrq);
266 return;
267 } else
268 msmsdcc_start_command(host, mrq->data->stop, 0);
269 }
270
271out:
272 spin_unlock_irqrestore(&host->lock, flags);
273 return;
274}
275
276static int validate_dma(struct msmsdcc_host *host, struct mmc_data *data)
277{
278 if (host->dma.channel == -1)
279 return -ENOENT;
280
281 if ((data->blksz * data->blocks) < MCI_FIFOSIZE)
282 return -EINVAL;
283 if ((data->blksz * data->blocks) % MCI_FIFOSIZE)
284 return -EINVAL;
285 return 0;
286}
287
288static int msmsdcc_config_dma(struct msmsdcc_host *host, struct mmc_data *data)
289{
290 struct msmsdcc_nc_dmadata *nc;
291 dmov_box *box;
292 uint32_t rows;
293 uint32_t crci;
294 unsigned int n;
295 int i, rc;
296 struct scatterlist *sg = data->sg;
297
298 rc = validate_dma(host, data);
299 if (rc)
300 return rc;
301
302 host->dma.sg = data->sg;
303 host->dma.num_ents = data->sg_len;
304
56a8b5b8
SM		 305 BUG_ON(host->dma.num_ents > NR_SG); /* Prevent memory corruption */
306
9d2bd738
SM		 307 nc = host->dma.nc;
308
75d14528
JP		 309 switch (host->pdev_id) {
310 case 1:
9d2bd738 311 crci = MSMSDCC_CRCI_SDC1;
75d14528
JP		 312 break;
313 case 2:
9d2bd738 314 crci = MSMSDCC_CRCI_SDC2;
75d14528
JP		 315 break;
316 case 3:
9d2bd738 317 crci = MSMSDCC_CRCI_SDC3;
75d14528
JP		 318 break;
319 case 4:
9d2bd738 320 crci = MSMSDCC_CRCI_SDC4;
75d14528
JP		 321 break;
322 default:
9d2bd738
SM		 323 host->dma.sg = NULL;
324 host->dma.num_ents = 0;
325 return -ENOENT;
326 }
327
328 if (data->flags & MMC_DATA_READ)
329 host->dma.dir = DMA_FROM_DEVICE;
330 else
331 host->dma.dir = DMA_TO_DEVICE;
332
333 host->curr.user_pages = 0;
334
9d2bd738
SM		 335 box = &nc->cmd[0];
336 for (i = 0; i < host->dma.num_ents; i++) {
337 box->cmd = CMD_MODE_BOX;
338
56a8b5b8
SM		 339 /* Initialize sg dma address */
340 sg->dma_address = page_to_dma(mmc_dev(host->mmc), sg_page(sg))
341 + sg->offset;
342
343 if (i == (host->dma.num_ents - 1))
9d2bd738
SM		 344 box->cmd |= CMD_LC;
345 rows = (sg_dma_len(sg) % MCI_FIFOSIZE) ?
346 (sg_dma_len(sg) / MCI_FIFOSIZE) + 1 :
347 (sg_dma_len(sg) / MCI_FIFOSIZE) ;
348
349 if (data->flags & MMC_DATA_READ) {
350 box->src_row_addr = msmsdcc_fifo_addr(host);
351 box->dst_row_addr = sg_dma_address(sg);
352
353 box->src_dst_len = (MCI_FIFOSIZE << 16) |
354 (MCI_FIFOSIZE);
355 box->row_offset = MCI_FIFOSIZE;
356
357 box->num_rows = rows * ((1 << 16) + 1);
358 box->cmd |= CMD_SRC_CRCI(crci);
359 } else {
360 box->src_row_addr = sg_dma_address(sg);
361 box->dst_row_addr = msmsdcc_fifo_addr(host);
362
363 box->src_dst_len = (MCI_FIFOSIZE << 16) |
364 (MCI_FIFOSIZE);
365 box->row_offset = (MCI_FIFOSIZE << 16);
366
367 box->num_rows = rows * ((1 << 16) + 1);
368 box->cmd |= CMD_DST_CRCI(crci);
369 }
370 box++;
371 sg++;
372 }
373
374 /* location of command block must be 64 bit aligned */
375 BUG_ON(host->dma.cmd_busaddr & 0x07);
376
377 nc->cmdptr = (host->dma.cmd_busaddr >> 3) | CMD_PTR_LP;
378 host->dma.hdr.cmdptr = DMOV_CMD_PTR_LIST |
379 DMOV_CMD_ADDR(host->dma.cmdptr_busaddr);
380 host->dma.hdr.complete_func = msmsdcc_dma_complete_func;
381
56a8b5b8
SM		 382 n = dma_map_sg(mmc_dev(host->mmc), host->dma.sg,
383 host->dma.num_ents, host->dma.dir);
384/* dsb inside dma_map_sg will write nc out to mem as well */
385
386 if (n != host->dma.num_ents) {
387 printk(KERN_ERR "%s: Unable to map in all sg elements\n",
388 mmc_hostname(host->mmc));
389 host->dma.sg = NULL;
390 host->dma.num_ents = 0;
391 return -ENOMEM;
392 }
393
394 return 0;
395}
396
397static int
398snoop_cccr_abort(struct mmc_command *cmd)
399{
400 if ((cmd->opcode == 52) &&
401 (cmd->arg & 0x80000000) &&
402 (((cmd->arg >> 9) & 0x1ffff) == SDIO_CCCR_ABORT))
403 return 1;
9d2bd738
SM		 404 return 0;
405}
406
407static void
56a8b5b8
SM		 408msmsdcc_start_command_deferred(struct msmsdcc_host *host,
409 struct mmc_command *cmd, u32 *c)
410{
411 *c |= (cmd->opcode | MCI_CPSM_ENABLE);
412
413 if (cmd->flags & MMC_RSP_PRESENT) {
414 if (cmd->flags & MMC_RSP_136)
415 *c |= MCI_CPSM_LONGRSP;
416 *c |= MCI_CPSM_RESPONSE;
417 }
418
419 if (/*interrupt*/0)
420 *c |= MCI_CPSM_INTERRUPT;
421
422 if ((((cmd->opcode == 17) || (cmd->opcode == 18)) ||
423 ((cmd->opcode == 24) || (cmd->opcode == 25))) ||
424 (cmd->opcode == 53))
425 *c |= MCI_CSPM_DATCMD;
426
427 if (cmd == cmd->mrq->stop)
428 *c |= MCI_CSPM_MCIABORT;
429
430 if (snoop_cccr_abort(cmd))
431 *c |= MCI_CSPM_MCIABORT;
432
433 if (host->curr.cmd != NULL) {
434 printk(KERN_ERR "%s: Overlapping command requests\n",
435 mmc_hostname(host->mmc));
436 }
437 host->curr.cmd = cmd;
438}
439
440static void
441msmsdcc_start_data(struct msmsdcc_host *host, struct mmc_data *data,
442 struct mmc_command *cmd, u32 c)
9d2bd738
SM		 443{
444 unsigned int datactrl, timeout;
445 unsigned long long clks;
9d2bd738
SM		 446 unsigned int pio_irqmask = 0;
447
448 host->curr.data = data;
449 host->curr.xfer_size = data->blksz * data->blocks;
450 host->curr.xfer_remain = host->curr.xfer_size;
451 host->curr.data_xfered = 0;
452 host->curr.got_dataend = 0;
453 host->curr.got_datablkend = 0;
454
455 memset(&host->pio, 0, sizeof(host->pio));
456
9d2bd738
SM		 457 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
458
459 if (!msmsdcc_config_dma(host, data))
460 datactrl |= MCI_DPSM_DMAENABLE;
461 else {
462 host->pio.sg = data->sg;
463 host->pio.sg_len = data->sg_len;
464 host->pio.sg_off = 0;
465
466 if (data->flags & MMC_DATA_READ) {
467 pio_irqmask = MCI_RXFIFOHALFFULLMASK;
468 if (host->curr.xfer_remain < MCI_FIFOSIZE)
469 pio_irqmask |= MCI_RXDATAAVLBLMASK;
470 } else
471 pio_irqmask = MCI_TXFIFOHALFEMPTYMASK;
472 }
473
474 if (data->flags & MMC_DATA_READ)
475 datactrl |= MCI_DPSM_DIRECTION;
476
56a8b5b8
SM		 477 clks = (unsigned long long)data->timeout_ns * host->clk_rate;
478 do_div(clks, NSEC_PER_SEC);
479 timeout = data->timeout_clks + (unsigned int)clks*2 ;
9d2bd738
SM		 480
481 if (datactrl & MCI_DPSM_DMAENABLE) {
56a8b5b8
SM		 482 /* Save parameters for the exec function */
483 host->cmd_timeout = timeout;
484 host->cmd_pio_irqmask = pio_irqmask;
485 host->cmd_datactrl = datactrl;
486 host->cmd_cmd = cmd;
487
488 host->dma.hdr.execute_func = msmsdcc_dma_exec_func;
489 host->dma.hdr.data = (void *)host;
9d2bd738 490 host->dma.busy = 1;
56a8b5b8
SM		 491
492 if (cmd) {
493 msmsdcc_start_command_deferred(host, cmd, &c);
494 host->cmd_c = c;
495 }
9d2bd738 496 msm_dmov_enqueue_cmd(host->dma.channel, &host->dma.hdr);
56a8b5b8
SM		 497 } else {
498 msmsdcc_writel(host, timeout, MMCIDATATIMER);
9d2bd738 499
56a8b5b8
SM		 500 msmsdcc_writel(host, host->curr.xfer_size, MMCIDATALENGTH);
501
502 msmsdcc_writel(host, pio_irqmask, MMCIMASK1);
503 msmsdcc_writel(host, datactrl, MMCIDATACTRL);
504
505 if (cmd) {
506 /* Daisy-chain the command if requested */
507 msmsdcc_start_command(host, cmd, c);
508 }
9d2bd738
SM		 509 }
510}
511
512static void
513msmsdcc_start_command(struct msmsdcc_host *host, struct mmc_command *cmd, u32 c)
514{
9d2bd738
SM		 515 if (cmd == cmd->mrq->stop)
516 c |= MCI_CSPM_MCIABORT;
517
9d2bd738
SM		 518 host->stats.cmds++;
519
56a8b5b8
SM		 520 msmsdcc_start_command_deferred(host, cmd, &c);
521 msmsdcc_start_command_exec(host, cmd->arg, c);
9d2bd738
SM		 522}
523
524static void
525msmsdcc_data_err(struct msmsdcc_host *host, struct mmc_data *data,
526 unsigned int status)
527{
528 if (status & MCI_DATACRCFAIL) {
0a7ff7c7
JP		 529 pr_err("%s: Data CRC error\n", mmc_hostname(host->mmc));
530 pr_err("%s: opcode 0x%.8x\n", __func__,
9d2bd738 531 data->mrq->cmd->opcode);
0a7ff7c7 532 pr_err("%s: blksz %d, blocks %d\n", __func__,
9d2bd738
SM		 533 data->blksz, data->blocks);
534 data->error = -EILSEQ;
535 } else if (status & MCI_DATATIMEOUT) {
0a7ff7c7 536 pr_err("%s: Data timeout\n", mmc_hostname(host->mmc));
9d2bd738
SM		 537 data->error = -ETIMEDOUT;
538 } else if (status & MCI_RXOVERRUN) {
0a7ff7c7 539 pr_err("%s: RX overrun\n", mmc_hostname(host->mmc));
9d2bd738
SM		 540 data->error = -EIO;
541 } else if (status & MCI_TXUNDERRUN) {
0a7ff7c7 542 pr_err("%s: TX underrun\n", mmc_hostname(host->mmc));
9d2bd738
SM		 543 data->error = -EIO;
544 } else {
0a7ff7c7
JP		 545 pr_err("%s: Unknown error (0x%.8x)\n",
546 mmc_hostname(host->mmc), status);
9d2bd738
SM		 547 data->error = -EIO;
548 }
549}
550
551
552static int
553msmsdcc_pio_read(struct msmsdcc_host *host, char *buffer, unsigned int remain)
554{
9d2bd738
SM		 555 uint32_t *ptr = (uint32_t *) buffer;
556 int count = 0;
557
8b1c2ba2
SM		 558 while (msmsdcc_readl(host, MMCISTATUS) & MCI_RXDATAAVLBL) {
559 *ptr = msmsdcc_readl(host, MMCIFIFO + (count % MCI_FIFOSIZE));
9d2bd738
SM		 560 ptr++;
561 count += sizeof(uint32_t);
562
563 remain -= sizeof(uint32_t);
564 if (remain == 0)
565 break;
566 }
567 return count;
568}
569
570static int
571msmsdcc_pio_write(struct msmsdcc_host *host, char *buffer,
572 unsigned int remain, u32 status)
573{
574 void __iomem *base = host->base;
575 char *ptr = buffer;
576
577 do {
578 unsigned int count, maxcnt;
579
580 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE :
581 MCI_FIFOHALFSIZE;
582 count = min(remain, maxcnt);
583
584 writesl(base + MMCIFIFO, ptr, count >> 2);
585 ptr += count;
586 remain -= count;
587
588 if (remain == 0)
589 break;
590
8b1c2ba2 591 status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738
SM		 592 } while (status & MCI_TXFIFOHALFEMPTY);
593
594 return ptr - buffer;
595}
596
597static int
598msmsdcc_spin_on_status(struct msmsdcc_host *host, uint32_t mask, int maxspin)
599{
600 while (maxspin) {
8b1c2ba2 601 if ((msmsdcc_readl(host, MMCISTATUS) & mask))
9d2bd738
SM		 602 return 0;
603 udelay(1);
604 --maxspin;
605 }
606 return -ETIMEDOUT;
607}
608
1cd22969 609static irqreturn_t
9d2bd738
SM		 610msmsdcc_pio_irq(int irq, void *dev_id)
611{
612 struct msmsdcc_host *host = dev_id;
9d2bd738
SM		 613 uint32_t status;
614
8b1c2ba2 615 status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738
SM		 616
617 do {
618 unsigned long flags;
619 unsigned int remain, len;
620 char *buffer;
621
622 if (!(status & (MCI_TXFIFOHALFEMPTY | MCI_RXDATAAVLBL))) {
623 if (host->curr.xfer_remain == 0 || !msmsdcc_piopoll)
624 break;
625
626 if (msmsdcc_spin_on_status(host,
627 (MCI_TXFIFOHALFEMPTY |
628 MCI_RXDATAAVLBL),
629 PIO_SPINMAX)) {
630 break;
631 }
632 }
633
634 /* Map the current scatter buffer */
635 local_irq_save(flags);
636 buffer = kmap_atomic(sg_page(host->pio.sg),
637 KM_BIO_SRC_IRQ) + host->pio.sg->offset;
638 buffer += host->pio.sg_off;
639 remain = host->pio.sg->length - host->pio.sg_off;
640 len = 0;
641 if (status & MCI_RXACTIVE)
642 len = msmsdcc_pio_read(host, buffer, remain);
643 if (status & MCI_TXACTIVE)
644 len = msmsdcc_pio_write(host, buffer, remain, status);
645
646 /* Unmap the buffer */
647 kunmap_atomic(buffer, KM_BIO_SRC_IRQ);
648 local_irq_restore(flags);
649
650 host->pio.sg_off += len;
651 host->curr.xfer_remain -= len;
652 host->curr.data_xfered += len;
653 remain -= len;
654
655 if (remain == 0) {
656 /* This sg page is full - do some housekeeping */
657 if (status & MCI_RXACTIVE && host->curr.user_pages)
658 flush_dcache_page(sg_page(host->pio.sg));
659
660 if (!--host->pio.sg_len) {
661 memset(&host->pio, 0, sizeof(host->pio));
662 break;
663 }
664
665 /* Advance to next sg */
666 host->pio.sg++;
667 host->pio.sg_off = 0;
668 }
669
8b1c2ba2 670 status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738
SM		 671 } while (1);
672
673 if (status & MCI_RXACTIVE && host->curr.xfer_remain < MCI_FIFOSIZE)
8b1c2ba2 674 msmsdcc_writel(host, MCI_RXDATAAVLBLMASK, MMCIMASK1);
9d2bd738
SM		 675
676 if (!host->curr.xfer_remain)
8b1c2ba2 677 msmsdcc_writel(host, 0, MMCIMASK1);
9d2bd738
SM		 678
679 return IRQ_HANDLED;
680}
681
682static void msmsdcc_do_cmdirq(struct msmsdcc_host *host, uint32_t status)
683{
684 struct mmc_command *cmd = host->curr.cmd;
9d2bd738
SM		 685
686 host->curr.cmd = NULL;
8b1c2ba2
SM		 687 cmd->resp[0] = msmsdcc_readl(host, MMCIRESPONSE0);
688 cmd->resp[1] = msmsdcc_readl(host, MMCIRESPONSE1);
689 cmd->resp[2] = msmsdcc_readl(host, MMCIRESPONSE2);
690 cmd->resp[3] = msmsdcc_readl(host, MMCIRESPONSE3);
9d2bd738 691
9d2bd738
SM		 692 if (status & MCI_CMDTIMEOUT) {
693 cmd->error = -ETIMEDOUT;
694 } else if (status & MCI_CMDCRCFAIL &&
695 cmd->flags & MMC_RSP_CRC) {
0a7ff7c7 696 pr_err("%s: Command CRC error\n", mmc_hostname(host->mmc));
9d2bd738
SM		 697 cmd->error = -EILSEQ;
698 }
699
700 if (!cmd->data || cmd->error) {
701 if (host->curr.data && host->dma.sg)
702 msm_dmov_stop_cmd(host->dma.channel,
703 &host->dma.hdr, 0);
704 else if (host->curr.data) { /* Non DMA */
705 msmsdcc_stop_data(host);
706 msmsdcc_request_end(host, cmd->mrq);
707 } else /* host->data == NULL */
708 msmsdcc_request_end(host, cmd->mrq);
56a8b5b8
SM		 709 } else if (cmd->data)
710 if (!(cmd->data->flags & MMC_DATA_READ))
711 msmsdcc_start_data(host, cmd->data,
712 NULL, 0);
9d2bd738
SM		 713}
714
b5a74d60
JP		 715static void
716msmsdcc_handle_irq_data(struct msmsdcc_host *host, u32 status,
717 void __iomem *base)
718{
719 struct mmc_data *data = host->curr.data;
720
56a8b5b8
SM		 721 if (status & (MCI_CMDSENT | MCI_CMDRESPEND | MCI_CMDCRCFAIL |
722 MCI_CMDTIMEOUT) && host->curr.cmd) {
723 msmsdcc_do_cmdirq(host, status);
724 }
725
b5a74d60
JP		 726 if (!data)
727 return;
728
729 /* Check for data errors */
730 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
731 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
732 msmsdcc_data_err(host, data, status);
733 host->curr.data_xfered = 0;
734 if (host->dma.sg)
735 msm_dmov_stop_cmd(host->dma.channel,
736 &host->dma.hdr, 0);
737 else {
b3b0ca84
SM		 738 if (host->curr.data)
739 msmsdcc_stop_data(host);
b5a74d60
JP		 740 if (!data->stop)
741 msmsdcc_request_end(host, data->mrq);
742 else
743 msmsdcc_start_command(host, data->stop, 0);
744 }
745 }
746
747 /* Check for data done */
748 if (!host->curr.got_dataend && (status & MCI_DATAEND))
749 host->curr.got_dataend = 1;
750
751 if (!host->curr.got_datablkend && (status & MCI_DATABLOCKEND))
752 host->curr.got_datablkend = 1;
753
754 /*
755 * If DMA is still in progress, we complete via the completion handler
756 */
757 if (host->curr.got_dataend && host->curr.got_datablkend &&
758 !host->dma.busy) {
759 /*
760 * There appears to be an issue in the controller where
761 * if you request a small block transfer (< fifo size),
762 * you may get your DATAEND/DATABLKEND irq without the
763 * PIO data irq.
764 *
765 * Check to see if there is still data to be read,
766 * and simulate a PIO irq.
767 */
768 if (readl(base + MMCISTATUS) & MCI_RXDATAAVLBL)
769 msmsdcc_pio_irq(1, host);
770
771 msmsdcc_stop_data(host);
772 if (!data->error)
773 host->curr.data_xfered = host->curr.xfer_size;
774
775 if (!data->stop)
776 msmsdcc_request_end(host, data->mrq);
777 else
778 msmsdcc_start_command(host, data->stop, 0);
779 }
780}
781
9d2bd738
SM		 782static irqreturn_t
783msmsdcc_irq(int irq, void *dev_id)
784{
785 struct msmsdcc_host *host = dev_id;
786 void __iomem *base = host->base;
787 u32 status;
788 int ret = 0;
789 int cardint = 0;
790
791 spin_lock(&host->lock);
792
793 do {
8b1c2ba2
SM		 794 status = msmsdcc_readl(host, MMCISTATUS);
795 status &= (msmsdcc_readl(host, MMCIMASK0) |
796 MCI_DATABLOCKENDMASK);
797 msmsdcc_writel(host, status, MMCICLEAR);
9d2bd738 798
865c8064
SM		 799 if (status & MCI_SDIOINTR)
800 status &= ~MCI_SDIOINTR;
9d2bd738 801
865c8064
SM		 802 if (!status)
803 break;
9d2bd738 804
b5a74d60 805 msmsdcc_handle_irq_data(host, status, base);
9d2bd738
SM		 806
807 if (status & MCI_SDIOINTOPER) {
808 cardint = 1;
809 status &= ~MCI_SDIOINTOPER;
810 }
811 ret = 1;
812 } while (status);
813
814 spin_unlock(&host->lock);
815
816 /*
817 * We have to delay handling the card interrupt as it calls
818 * back into the driver.
819 */
820 if (cardint)
821 mmc_signal_sdio_irq(host->mmc);
822
823 return IRQ_RETVAL(ret);
824}
825
826static void
827msmsdcc_request(struct mmc_host *mmc, struct mmc_request *mrq)
828{
829 struct msmsdcc_host *host = mmc_priv(mmc);
830 unsigned long flags;
831
832 WARN_ON(host->curr.mrq != NULL);
833 WARN_ON(host->pwr == 0);
834
835 spin_lock_irqsave(&host->lock, flags);
836
837 host->stats.reqs++;
838
839 if (host->eject) {
840 if (mrq->data && !(mrq->data->flags & MMC_DATA_READ)) {
841 mrq->cmd->error = 0;
842 mrq->data->bytes_xfered = mrq->data->blksz *
843 mrq->data->blocks;
844 } else
845 mrq->cmd->error = -ENOMEDIUM;
846
847 spin_unlock_irqrestore(&host->lock, flags);
848 mmc_request_done(mmc, mrq);
849 return;
850 }
851
d0719e59 852 msmsdcc_enable_clocks(host);
9d2bd738 853
9d2bd738
SM		 854 host->curr.mrq = mrq;
855
856 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
56a8b5b8
SM		 857 /* Queue/read data, daisy-chain command when data starts */
858 msmsdcc_start_data(host, mrq->data, mrq->cmd, 0);
859 else
860 msmsdcc_start_command(host, mrq->cmd, 0);
9d2bd738
SM		 861
862 if (host->cmdpoll && !msmsdcc_spin_on_status(host,
863 MCI_CMDRESPEND|MCI_CMDCRCFAIL|MCI_CMDTIMEOUT,
864 CMD_SPINMAX)) {
8b1c2ba2 865 uint32_t status = msmsdcc_readl(host, MMCISTATUS);
9d2bd738 866 msmsdcc_do_cmdirq(host, status);
8b1c2ba2
SM		 867 msmsdcc_writel(host,
868 MCI_CMDRESPEND | MCI_CMDCRCFAIL | MCI_CMDTIMEOUT,
869 MMCICLEAR);
9d2bd738
SM		 870 host->stats.cmdpoll_hits++;
871 } else {
872 host->stats.cmdpoll_misses++;
9d2bd738
SM		 873 }
874 spin_unlock_irqrestore(&host->lock, flags);
875}
876
877static void
878msmsdcc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
879{
880 struct msmsdcc_host *host = mmc_priv(mmc);
881 u32 clk = 0, pwr = 0;
882 int rc;
4adbbcc7 883 unsigned long flags;
9d2bd738 884
c7fc9370 885 spin_lock_irqsave(&host->lock, flags);
9d2bd738 886
d0719e59
SM		 887 msmsdcc_enable_clocks(host);
888
865c8064 889 if (ios->clock) {
9d2bd738
SM		 890 if (ios->clock != host->clk_rate) {
891 rc = clk_set_rate(host->clk, ios->clock);
892 if (rc < 0)
0a7ff7c7
JP		 893 pr_err("%s: Error setting clock rate (%d)\n",
894 mmc_hostname(host->mmc), rc);
9d2bd738
SM		 895 else
896 host->clk_rate = ios->clock;
897 }
898 clk |= MCI_CLK_ENABLE;
899 }
900
901 if (ios->bus_width == MMC_BUS_WIDTH_4)
902 clk |= (2 << 10); /* Set WIDEBUS */
903
904 if (ios->clock > 400000 && msmsdcc_pwrsave)
905 clk |= (1 << 9); /* PWRSAVE */
906
907 clk |= (1 << 12); /* FLOW_ENA */
908 clk |= (1 << 15); /* feedback clock */
909
910 if (host->plat->translate_vdd)
911 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
912
913 switch (ios->power_mode) {
914 case MMC_POWER_OFF:
9d2bd738
SM		 915 break;
916 case MMC_POWER_UP:
917 pwr |= MCI_PWR_UP;
918 break;
919 case MMC_POWER_ON:
9d2bd738
SM		 920 pwr |= MCI_PWR_ON;
921 break;
922 }
923
924 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
925 pwr |= MCI_OD;
926
8b1c2ba2 927 msmsdcc_writel(host, clk, MMCICLOCK);
9d2bd738
SM		 928
929 if (host->pwr != pwr) {
930 host->pwr = pwr;
8b1c2ba2 931 msmsdcc_writel(host, pwr, MMCIPOWER);
9d2bd738 932 }
f4748499 933#if BUSCLK_PWRSAVE
c7fc9370 934 msmsdcc_disable_clocks(host, 1);
f4748499 935#endif
4adbbcc7 936 spin_unlock_irqrestore(&host->lock, flags);
9d2bd738
SM		 937}
938
939static void msmsdcc_enable_sdio_irq(struct mmc_host *mmc, int enable)
940{
941 struct msmsdcc_host *host = mmc_priv(mmc);
942 unsigned long flags;
943 u32 status;
944
945 spin_lock_irqsave(&host->lock, flags);
946 if (msmsdcc_sdioirq == 1) {
8b1c2ba2 947 status = msmsdcc_readl(host, MMCIMASK0);
9d2bd738
SM		 948 if (enable)
949 status |= MCI_SDIOINTOPERMASK;
950 else
951 status &= ~MCI_SDIOINTOPERMASK;
952 host->saved_irq0mask = status;
8b1c2ba2 953 msmsdcc_writel(host, status, MMCIMASK0);
9d2bd738
SM		 954 }
955 spin_unlock_irqrestore(&host->lock, flags);
956}
957
958static const struct mmc_host_ops msmsdcc_ops = {
959 .request = msmsdcc_request,
960 .set_ios = msmsdcc_set_ios,
961 .enable_sdio_irq = msmsdcc_enable_sdio_irq,
962};
963
964static void
965msmsdcc_check_status(unsigned long data)
966{
967 struct msmsdcc_host *host = (struct msmsdcc_host *)data;
968 unsigned int status;
969
970 if (!host->plat->status) {
971 mmc_detect_change(host->mmc, 0);
972 goto out;
973 }
974
975 status = host->plat->status(mmc_dev(host->mmc));
976 host->eject = !status;
977 if (status ^ host->oldstat) {
0a7ff7c7
JP		 978 pr_info("%s: Slot status change detected (%d -> %d)\n",
979 mmc_hostname(host->mmc), host->oldstat, status);
9d2bd738
SM		 980 if (status)
981 mmc_detect_change(host->mmc, (5 * HZ) / 2);
982 else
983 mmc_detect_change(host->mmc, 0);
984 }
985
986 host->oldstat = status;
987
988out:
989 if (host->timer.function)
990 mod_timer(&host->timer, jiffies + HZ);
991}
992
993static irqreturn_t
994msmsdcc_platform_status_irq(int irq, void *dev_id)
995{
996 struct msmsdcc_host *host = dev_id;
997
998 printk(KERN_DEBUG "%s: %d\n", __func__, irq);
999 msmsdcc_check_status((unsigned long) host);
1000 return IRQ_HANDLED;
1001}
1002
1003static void
1004msmsdcc_status_notify_cb(int card_present, void *dev_id)
1005{
1006 struct msmsdcc_host *host = dev_id;
1007
1008 printk(KERN_DEBUG "%s: card_present %d\n", mmc_hostname(host->mmc),
1009 card_present);
1010 msmsdcc_check_status((unsigned long) host);
1011}
1012
9d2bd738 1013static void
865c8064 1014msmsdcc_busclk_expired(unsigned long _data)
9d2bd738
SM		 1015{
1016 struct msmsdcc_host *host = (struct msmsdcc_host *) _data;
9d2bd738 1017
865c8064 1018 if (host->clks_on)
c7fc9370 1019 msmsdcc_disable_clocks(host, 0);
9d2bd738
SM		 1020}
1021
1022static int
1023msmsdcc_init_dma(struct msmsdcc_host *host)
1024{
1025 memset(&host->dma, 0, sizeof(struct msmsdcc_dma_data));
1026 host->dma.host = host;
1027 host->dma.channel = -1;
1028
1029 if (!host->dmares)
1030 return -ENODEV;
1031
1032 host->dma.nc = dma_alloc_coherent(NULL,
1033 sizeof(struct msmsdcc_nc_dmadata),
1034 &host->dma.nc_busaddr,
1035 GFP_KERNEL);
1036 if (host->dma.nc == NULL) {
0a7ff7c7 1037 pr_err("Unable to allocate DMA buffer\n");
9d2bd738
SM		 1038 return -ENOMEM;
1039 }
1040 memset(host->dma.nc, 0x00, sizeof(struct msmsdcc_nc_dmadata));
1041 host->dma.cmd_busaddr = host->dma.nc_busaddr;
1042 host->dma.cmdptr_busaddr = host->dma.nc_busaddr +
1043 offsetof(struct msmsdcc_nc_dmadata, cmdptr);
1044 host->dma.channel = host->dmares->start;
1045
1046 return 0;
1047}
1048
9d2bd738
SM		 1049static int
1050msmsdcc_probe(struct platform_device *pdev)
1051{
b5d643de 1052 struct msm_mmc_platform_data *plat = pdev->dev.platform_data;
9d2bd738
SM		 1053 struct msmsdcc_host *host;
1054 struct mmc_host *mmc;
1055 struct resource *cmd_irqres = NULL;
1056 struct resource *pio_irqres = NULL;
1057 struct resource *stat_irqres = NULL;
1058 struct resource *memres = NULL;
1059 struct resource *dmares = NULL;
1060 int ret;
1061
1062 /* must have platform data */
1063 if (!plat) {
0a7ff7c7 1064 pr_err("%s: Platform data not available\n", __func__);
9d2bd738
SM		 1065 ret = -EINVAL;
1066 goto out;
1067 }
1068
1069 if (pdev->id < 1 || pdev->id > 4)
1070 return -EINVAL;
1071
1072 if (pdev->resource == NULL || pdev->num_resources < 2) {
0a7ff7c7 1073 pr_err("%s: Invalid resource\n", __func__);
9d2bd738
SM		 1074 return -ENXIO;
1075 }
1076
1077 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1078 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1079 cmd_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1080 "cmd_irq");
1081 pio_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1082 "pio_irq");
1083 stat_irqres = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1084 "status_irq");
1085
1086 if (!cmd_irqres || !pio_irqres || !memres) {
0a7ff7c7 1087 pr_err("%s: Invalid resource\n", __func__);
9d2bd738
SM		 1088 return -ENXIO;
1089 }
1090
1091 /*
1092 * Setup our host structure
1093 */
1094
1095 mmc = mmc_alloc_host(sizeof(struct msmsdcc_host), &pdev->dev);
1096 if (!mmc) {
1097 ret = -ENOMEM;
1098 goto out;
1099 }
1100
1101 host = mmc_priv(mmc);
1102 host->pdev_id = pdev->id;
1103 host->plat = plat;
1104 host->mmc = mmc;
56a8b5b8 1105 host->curr.cmd = NULL;
9d2bd738
SM		 1106
1107 host->cmdpoll = 1;
1108
1109 host->base = ioremap(memres->start, PAGE_SIZE);
1110 if (!host->base) {
1111 ret = -ENOMEM;
1112 goto out;
1113 }
1114
1115 host->cmd_irqres = cmd_irqres;
1116 host->pio_irqres = pio_irqres;
1117 host->memres = memres;
1118 host->dmares = dmares;
1119 spin_lock_init(&host->lock);
1120
1121 /*
1122 * Setup DMA
1123 */
1124 msmsdcc_init_dma(host);
1125
4adbbcc7 1126 /* Get our clocks */
9d2bd738
SM		 1127 host->pclk = clk_get(&pdev->dev, "sdc_pclk");
1128 if (IS_ERR(host->pclk)) {
1129 ret = PTR_ERR(host->pclk);
1130 goto host_free;
1131 }
1132
9d2bd738
SM		 1133 host->clk = clk_get(&pdev->dev, "sdc_clk");
1134 if (IS_ERR(host->clk)) {
1135 ret = PTR_ERR(host->clk);
4adbbcc7 1136 goto pclk_put;
9d2bd738
SM		 1137 }
1138
4adbbcc7 1139 /* Enable clocks */
c7fc9370 1140 ret = msmsdcc_enable_clocks(host);
9d2bd738
SM		 1141 if (ret)
1142 goto clk_put;
1143
1144 ret = clk_set_rate(host->clk, msmsdcc_fmin);
1145 if (ret) {
0a7ff7c7 1146 pr_err("%s: Clock rate set failed (%d)\n", __func__, ret);
9d2bd738
SM		 1147 goto clk_disable;
1148 }
1149
4adbbcc7 1150 host->pclk_rate = clk_get_rate(host->pclk);
9d2bd738
SM		 1151 host->clk_rate = clk_get_rate(host->clk);
1152
9d2bd738
SM		 1153 /*
1154 * Setup MMC host structure
1155 */
1156 mmc->ops = &msmsdcc_ops;
1157 mmc->f_min = msmsdcc_fmin;
1158 mmc->f_max = msmsdcc_fmax;
1159 mmc->ocr_avail = plat->ocr_mask;
1160
1161 if (msmsdcc_4bit)
1162 mmc->caps |= MMC_CAP_4_BIT_DATA;
1163 if (msmsdcc_sdioirq)
1164 mmc->caps |= MMC_CAP_SDIO_IRQ;
1165 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1166
1167 mmc->max_phys_segs = NR_SG;
1168 mmc->max_hw_segs = NR_SG;
1169 mmc->max_blk_size = 4096; /* MCI_DATA_CTL BLOCKSIZE up to 4096 */
1170 mmc->max_blk_count = 65536;
1171
1172 mmc->max_req_size = 33554432; /* MCI_DATA_LENGTH is 25 bits */
1173 mmc->max_seg_size = mmc->max_req_size;
1174
8b1c2ba2
SM		 1175 msmsdcc_writel(host, 0, MMCIMASK0);
1176 msmsdcc_writel(host, 0x5e007ff, MMCICLEAR);
9d2bd738 1177
8b1c2ba2 1178 msmsdcc_writel(host, MCI_IRQENABLE, MMCIMASK0);
9d2bd738
SM		 1179 host->saved_irq0mask = MCI_IRQENABLE;
1180
1181 /*
1182 * Setup card detect change
1183 */
1184
1185 memset(&host->timer, 0, sizeof(host->timer));
1186
1187 if (stat_irqres && !(stat_irqres->flags & IORESOURCE_DISABLED)) {
1188 unsigned long irqflags = IRQF_SHARED |
1189 (stat_irqres->flags & IRQF_TRIGGER_MASK);
1190
1191 host->stat_irq = stat_irqres->start;
1192 ret = request_irq(host->stat_irq,
1193 msmsdcc_platform_status_irq,
1194 irqflags,
1195 DRIVER_NAME " (slot)",
1196 host);
1197 if (ret) {
0a7ff7c7
JP		 1198 pr_err("%s: Unable to get slot IRQ %d (%d)\n",
1199 mmc_hostname(mmc), host->stat_irq, ret);
9d2bd738
SM		 1200 goto clk_disable;
1201 }
1202 } else if (plat->register_status_notify) {
1203 plat->register_status_notify(msmsdcc_status_notify_cb, host);
1204 } else if (!plat->status)
0a7ff7c7 1205 pr_err("%s: No card detect facilities available\n",
9d2bd738
SM		 1206 mmc_hostname(mmc));
1207 else {
1208 init_timer(&host->timer);
1209 host->timer.data = (unsigned long)host;
1210 host->timer.function = msmsdcc_check_status;
1211 host->timer.expires = jiffies + HZ;
1212 add_timer(&host->timer);
1213 }
1214
1215 if (plat->status) {
1216 host->oldstat = host->plat->status(mmc_dev(host->mmc));
1217 host->eject = !host->oldstat;
1218 }
1219
865c8064
SM		 1220 init_timer(&host->busclk_timer);
1221 host->busclk_timer.data = (unsigned long) host;
1222 host->busclk_timer.function = msmsdcc_busclk_expired;
9d2bd738
SM		 1223
1224 ret = request_irq(cmd_irqres->start, msmsdcc_irq, IRQF_SHARED,
1225 DRIVER_NAME " (cmd)", host);
1226 if (ret)
1227 goto stat_irq_free;
1228
1229 ret = request_irq(pio_irqres->start, msmsdcc_pio_irq, IRQF_SHARED,
1230 DRIVER_NAME " (pio)", host);
1231 if (ret)
1232 goto cmd_irq_free;
1233
1234 mmc_set_drvdata(pdev, mmc);
1235 mmc_add_host(mmc);
1236
0a7ff7c7
JP		 1237 pr_info("%s: Qualcomm MSM SDCC at 0x%016llx irq %d,%d dma %d\n",
1238 mmc_hostname(mmc), (unsigned long long)memres->start,
1239 (unsigned int) cmd_irqres->start,
1240 (unsigned int) host->stat_irq, host->dma.channel);
1241 pr_info("%s: 4 bit data mode %s\n", mmc_hostname(mmc),
1242 (mmc->caps & MMC_CAP_4_BIT_DATA ? "enabled" : "disabled"));
1243 pr_info("%s: MMC clock %u -> %u Hz, PCLK %u Hz\n",
1244 mmc_hostname(mmc), msmsdcc_fmin, msmsdcc_fmax, host->pclk_rate);
1245 pr_info("%s: Slot eject status = %d\n", mmc_hostname(mmc), host->eject);
1246 pr_info("%s: Power save feature enable = %d\n",
1247 mmc_hostname(mmc), msmsdcc_pwrsave);
9d2bd738
SM		 1248
1249 if (host->dma.channel != -1) {
0a7ff7c7
JP		 1250 pr_info("%s: DM non-cached buffer at %p, dma_addr 0x%.8x\n",
1251 mmc_hostname(mmc), host->dma.nc, host->dma.nc_busaddr);
1252 pr_info("%s: DM cmd busaddr 0x%.8x, cmdptr busaddr 0x%.8x\n",
1253 mmc_hostname(mmc), host->dma.cmd_busaddr,
1254 host->dma.cmdptr_busaddr);
9d2bd738 1255 } else
0a7ff7c7 1256 pr_info("%s: PIO transfer enabled\n", mmc_hostname(mmc));
9d2bd738 1257 if (host->timer.function)
0a7ff7c7 1258 pr_info("%s: Polling status mode enabled\n", mmc_hostname(mmc));
9d2bd738 1259
f4748499 1260#if BUSCLK_PWRSAVE
c7fc9370 1261 msmsdcc_disable_clocks(host, 1);
f4748499 1262#endif
9d2bd738
SM		 1263 return 0;
1264 cmd_irq_free:
1265 free_irq(cmd_irqres->start, host);
1266 stat_irq_free:
1267 if (host->stat_irq)
1268 free_irq(host->stat_irq, host);
1269 clk_disable:
c7fc9370 1270 msmsdcc_disable_clocks(host, 0);
9d2bd738
SM		 1271 clk_put:
1272 clk_put(host->clk);
9d2bd738
SM		 1273 pclk_put:
1274 clk_put(host->pclk);
1275 host_free:
1276 mmc_free_host(mmc);
1277 out:
1278 return ret;
1279}
1280
08ecfde4
DW		 1281#ifdef CONFIG_PM
1282#ifdef CONFIG_MMC_MSM7X00A_RESUME_IN_WQ
1283static void
1284do_resume_work(struct work_struct *work)
1285{
1286 struct msmsdcc_host *host =
1287 container_of(work, struct msmsdcc_host, resume_task);
1288 struct mmc_host *mmc = host->mmc;
1289
1290 if (mmc) {
1291 mmc_resume_host(mmc);
1292 if (host->stat_irq)
1293 enable_irq(host->stat_irq);
1294 }
1295}
1296#endif
1297
1298
9d2bd738
SM		 1299static int
1300msmsdcc_suspend(struct platform_device *dev, pm_message_t state)
1301{
1302 struct mmc_host *mmc = mmc_get_drvdata(dev);
1303 int rc = 0;
1304
1305 if (mmc) {
1306 struct msmsdcc_host *host = mmc_priv(mmc);
1307
1308 if (host->stat_irq)
1309 disable_irq(host->stat_irq);
1310
1311 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1a13f8fa 1312 rc = mmc_suspend_host(mmc);
d0719e59 1313 if (!rc)
8b1c2ba2 1314 msmsdcc_writel(host, 0, MMCIMASK0);
c7fc9370
SM		 1315 if (host->clks_on)
1316 msmsdcc_disable_clocks(host, 0);
9d2bd738
SM		 1317 }
1318 return rc;
1319}
1320
1321static int
1322msmsdcc_resume(struct platform_device *dev)
1323{
1324 struct mmc_host *mmc = mmc_get_drvdata(dev);
9d2bd738
SM		 1325
1326 if (mmc) {
1327 struct msmsdcc_host *host = mmc_priv(mmc);
1328
c7fc9370 1329 msmsdcc_enable_clocks(host);
9d2bd738 1330
8b1c2ba2 1331 msmsdcc_writel(host, host->saved_irq0mask, MMCIMASK0);
9d2bd738
SM		 1332
1333 if (mmc->card && mmc->card->type != MMC_TYPE_SDIO)
1334 mmc_resume_host(mmc);
5b8a2fb3 1335 if (host->stat_irq)
9d2bd738 1336 enable_irq(host->stat_irq);
f4748499 1337#if BUSCLK_PWRSAVE
c7fc9370 1338 msmsdcc_disable_clocks(host, 1);
f4748499 1339#endif
9d2bd738
SM		 1340 }
1341 return 0;
1342}
08ecfde4
DW		 1343#else
1344#define msmsdcc_suspend 0
1345#define msmsdcc_resume 0
1346#endif
9d2bd738
SM		 1347
1348static struct platform_driver msmsdcc_driver = {
1349 .probe = msmsdcc_probe,
1350 .suspend = msmsdcc_suspend,
1351 .resume = msmsdcc_resume,
1352 .driver = {
1353 .name = "msm_sdcc",
1354 },
1355};
1356
1357static int __init msmsdcc_init(void)
1358{
1359 return platform_driver_register(&msmsdcc_driver);
1360}
1361
1362static void __exit msmsdcc_exit(void)
1363{
1364 platform_driver_unregister(&msmsdcc_driver);
1365}
1366
1367module_init(msmsdcc_init);
1368module_exit(msmsdcc_exit);
1369
1370MODULE_DESCRIPTION("Qualcomm MSM 7X00A Multimedia Card Interface driver");
1371MODULE_LICENSE("GPL");
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