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236caa7c MS |
1 | /* |
2 | * Marvell MMC/SD/SDIO driver | |
3 | * | |
4 | * Authors: Maen Suleiman, Nicolas Pitre | |
5 | * Copyright (C) 2008-2009 Marvell Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/mbus.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/scatterlist.h> | |
21 | #include <linux/irq.h> | |
f4f7561e | 22 | #include <linux/clk.h> |
111936ff | 23 | #include <linux/of_irq.h> |
236caa7c | 24 | #include <linux/mmc/host.h> |
3724482d | 25 | #include <linux/mmc/slot-gpio.h> |
236caa7c MS |
26 | |
27 | #include <asm/sizes.h> | |
28 | #include <asm/unaligned.h> | |
236caa7c MS |
29 | |
30 | #include "mvsdio.h" | |
31 | ||
32 | #define DRIVER_NAME "mvsdio" | |
33 | ||
2cd17224 | 34 | static int maxfreq; |
236caa7c MS |
35 | static int nodma; |
36 | ||
37 | struct mvsd_host { | |
38 | void __iomem *base; | |
39 | struct mmc_request *mrq; | |
40 | spinlock_t lock; | |
41 | unsigned int xfer_mode; | |
42 | unsigned int intr_en; | |
43 | unsigned int ctrl; | |
44 | unsigned int pio_size; | |
45 | void *pio_ptr; | |
46 | unsigned int sg_frags; | |
47 | unsigned int ns_per_clk; | |
48 | unsigned int clock; | |
49 | unsigned int base_clock; | |
50 | struct timer_list timer; | |
51 | struct mmc_host *mmc; | |
52 | struct device *dev; | |
f4f7561e | 53 | struct clk *clk; |
236caa7c MS |
54 | }; |
55 | ||
56 | #define mvsd_write(offs, val) writel(val, iobase + (offs)) | |
57 | #define mvsd_read(offs) readl(iobase + (offs)) | |
58 | ||
59 | static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data) | |
60 | { | |
61 | void __iomem *iobase = host->base; | |
62 | unsigned int tmout; | |
63 | int tmout_index; | |
64 | ||
a6d297f0 NP |
65 | /* |
66 | * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE | |
67 | * register is sometimes not set before a while when some | |
68 | * "unusual" data block sizes are used (such as with the SWITCH | |
69 | * command), even despite the fact that the XFER_DONE interrupt | |
70 | * was raised. And if another data transfer starts before | |
71 | * this bit comes to good sense (which eventually happens by | |
72 | * itself) then the new transfer simply fails with a timeout. | |
73 | */ | |
74 | if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) { | |
75 | unsigned long t = jiffies + HZ; | |
76 | unsigned int hw_state, count = 0; | |
77 | do { | |
d7fe833f | 78 | hw_state = mvsd_read(MVSD_HW_STATE); |
a6d297f0 NP |
79 | if (time_after(jiffies, t)) { |
80 | dev_warn(host->dev, "FIFO_EMPTY bit missing\n"); | |
81 | break; | |
82 | } | |
a6d297f0 NP |
83 | count++; |
84 | } while (!(hw_state & (1 << 13))); | |
85 | dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit " | |
86 | "(hw=0x%04x, count=%d, jiffies=%ld)\n", | |
87 | hw_state, count, jiffies - (t - HZ)); | |
88 | } | |
89 | ||
236caa7c MS |
90 | /* If timeout=0 then maximum timeout index is used. */ |
91 | tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk); | |
92 | tmout += data->timeout_clks; | |
93 | tmout_index = fls(tmout - 1) - 12; | |
94 | if (tmout_index < 0) | |
95 | tmout_index = 0; | |
96 | if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX) | |
97 | tmout_index = MVSD_HOST_CTRL_TMOUT_MAX; | |
98 | ||
99 | dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n", | |
100 | (data->flags & MMC_DATA_READ) ? "read" : "write", | |
101 | (u32)sg_virt(data->sg), data->blocks, data->blksz, | |
102 | tmout, tmout_index); | |
103 | ||
104 | host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK; | |
105 | host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index); | |
106 | mvsd_write(MVSD_HOST_CTRL, host->ctrl); | |
107 | mvsd_write(MVSD_BLK_COUNT, data->blocks); | |
108 | mvsd_write(MVSD_BLK_SIZE, data->blksz); | |
109 | ||
3c583f70 AL |
110 | if (nodma || (data->blksz | data->sg->offset) & 3 || |
111 | ((!(data->flags & MMC_DATA_READ) && data->sg->offset & 0x3f))) { | |
236caa7c MS |
112 | /* |
113 | * We cannot do DMA on a buffer which offset or size | |
114 | * is not aligned on a 4-byte boundary. | |
3c583f70 AL |
115 | * |
116 | * It also appears the host to card DMA can corrupt | |
117 | * data when the buffer is not aligned on a 64 byte | |
118 | * boundary. | |
236caa7c MS |
119 | */ |
120 | host->pio_size = data->blocks * data->blksz; | |
121 | host->pio_ptr = sg_virt(data->sg); | |
122 | if (!nodma) | |
e573d698 TP |
123 | dev_dbg(host->dev, "fallback to PIO for data at 0x%p size %d\n", |
124 | host->pio_ptr, host->pio_size); | |
236caa7c MS |
125 | return 1; |
126 | } else { | |
127 | dma_addr_t phys_addr; | |
feeef096 HK |
128 | |
129 | host->sg_frags = dma_map_sg(mmc_dev(host->mmc), | |
130 | data->sg, data->sg_len, | |
131 | mmc_get_dma_dir(data)); | |
236caa7c MS |
132 | phys_addr = sg_dma_address(data->sg); |
133 | mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff); | |
134 | mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16); | |
135 | return 0; | |
136 | } | |
137 | } | |
138 | ||
139 | static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
140 | { | |
141 | struct mvsd_host *host = mmc_priv(mmc); | |
142 | void __iomem *iobase = host->base; | |
143 | struct mmc_command *cmd = mrq->cmd; | |
144 | u32 cmdreg = 0, xfer = 0, intr = 0; | |
145 | unsigned long flags; | |
146 | ||
147 | BUG_ON(host->mrq != NULL); | |
148 | host->mrq = mrq; | |
149 | ||
150 | dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n", | |
151 | cmd->opcode, mvsd_read(MVSD_HW_STATE)); | |
152 | ||
153 | cmdreg = MVSD_CMD_INDEX(cmd->opcode); | |
154 | ||
155 | if (cmd->flags & MMC_RSP_BUSY) | |
156 | cmdreg |= MVSD_CMD_RSP_48BUSY; | |
157 | else if (cmd->flags & MMC_RSP_136) | |
158 | cmdreg |= MVSD_CMD_RSP_136; | |
159 | else if (cmd->flags & MMC_RSP_PRESENT) | |
160 | cmdreg |= MVSD_CMD_RSP_48; | |
161 | else | |
162 | cmdreg |= MVSD_CMD_RSP_NONE; | |
163 | ||
164 | if (cmd->flags & MMC_RSP_CRC) | |
165 | cmdreg |= MVSD_CMD_CHECK_CMDCRC; | |
166 | ||
167 | if (cmd->flags & MMC_RSP_OPCODE) | |
168 | cmdreg |= MVSD_CMD_INDX_CHECK; | |
169 | ||
170 | if (cmd->flags & MMC_RSP_PRESENT) { | |
171 | cmdreg |= MVSD_UNEXPECTED_RESP; | |
172 | intr |= MVSD_NOR_UNEXP_RSP; | |
173 | } | |
174 | ||
175 | if (mrq->data) { | |
176 | struct mmc_data *data = mrq->data; | |
177 | int pio; | |
178 | ||
179 | cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16; | |
180 | xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN; | |
181 | if (data->flags & MMC_DATA_READ) | |
182 | xfer |= MVSD_XFER_MODE_TO_HOST; | |
183 | ||
184 | pio = mvsd_setup_data(host, data); | |
185 | if (pio) { | |
186 | xfer |= MVSD_XFER_MODE_PIO; | |
187 | /* PIO section of mvsd_irq has comments on those bits */ | |
188 | if (data->flags & MMC_DATA_WRITE) | |
189 | intr |= MVSD_NOR_TX_AVAIL; | |
190 | else if (host->pio_size > 32) | |
191 | intr |= MVSD_NOR_RX_FIFO_8W; | |
192 | else | |
193 | intr |= MVSD_NOR_RX_READY; | |
194 | } | |
195 | ||
196 | if (data->stop) { | |
197 | struct mmc_command *stop = data->stop; | |
198 | u32 cmd12reg = 0; | |
199 | ||
200 | mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff); | |
201 | mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16); | |
202 | ||
203 | if (stop->flags & MMC_RSP_BUSY) | |
204 | cmd12reg |= MVSD_AUTOCMD12_BUSY; | |
205 | if (stop->flags & MMC_RSP_OPCODE) | |
206 | cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK; | |
207 | cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode); | |
208 | mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg); | |
209 | ||
210 | xfer |= MVSD_XFER_MODE_AUTO_CMD12; | |
211 | intr |= MVSD_NOR_AUTOCMD12_DONE; | |
212 | } else { | |
213 | intr |= MVSD_NOR_XFER_DONE; | |
214 | } | |
215 | } else { | |
216 | intr |= MVSD_NOR_CMD_DONE; | |
217 | } | |
218 | ||
219 | mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff); | |
220 | mvsd_write(MVSD_ARG_HI, cmd->arg >> 16); | |
221 | ||
222 | spin_lock_irqsave(&host->lock, flags); | |
223 | ||
224 | host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; | |
225 | host->xfer_mode |= xfer; | |
226 | mvsd_write(MVSD_XFER_MODE, host->xfer_mode); | |
227 | ||
228 | mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT); | |
229 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
230 | mvsd_write(MVSD_CMD, cmdreg); | |
231 | ||
232 | host->intr_en &= MVSD_NOR_CARD_INT; | |
233 | host->intr_en |= intr | MVSD_NOR_ERROR; | |
234 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
235 | mvsd_write(MVSD_ERR_INTR_EN, 0xffff); | |
236 | ||
237 | mod_timer(&host->timer, jiffies + 5 * HZ); | |
238 | ||
239 | spin_unlock_irqrestore(&host->lock, flags); | |
240 | } | |
241 | ||
242 | static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd, | |
243 | u32 err_status) | |
244 | { | |
245 | void __iomem *iobase = host->base; | |
246 | ||
247 | if (cmd->flags & MMC_RSP_136) { | |
248 | unsigned int response[8], i; | |
249 | for (i = 0; i < 8; i++) | |
250 | response[i] = mvsd_read(MVSD_RSP(i)); | |
251 | cmd->resp[0] = ((response[0] & 0x03ff) << 22) | | |
252 | ((response[1] & 0xffff) << 6) | | |
253 | ((response[2] & 0xfc00) >> 10); | |
254 | cmd->resp[1] = ((response[2] & 0x03ff) << 22) | | |
255 | ((response[3] & 0xffff) << 6) | | |
256 | ((response[4] & 0xfc00) >> 10); | |
257 | cmd->resp[2] = ((response[4] & 0x03ff) << 22) | | |
258 | ((response[5] & 0xffff) << 6) | | |
259 | ((response[6] & 0xfc00) >> 10); | |
260 | cmd->resp[3] = ((response[6] & 0x03ff) << 22) | | |
261 | ((response[7] & 0x3fff) << 8); | |
262 | } else if (cmd->flags & MMC_RSP_PRESENT) { | |
263 | unsigned int response[3], i; | |
264 | for (i = 0; i < 3; i++) | |
265 | response[i] = mvsd_read(MVSD_RSP(i)); | |
266 | cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | | |
267 | ((response[1] & 0xffff) << (14 - 8)) | | |
268 | ((response[0] & 0x03ff) << (30 - 8)); | |
269 | cmd->resp[1] = ((response[0] & 0xfc00) >> 10); | |
270 | cmd->resp[2] = 0; | |
271 | cmd->resp[3] = 0; | |
272 | } | |
273 | ||
274 | if (err_status & MVSD_ERR_CMD_TIMEOUT) { | |
275 | cmd->error = -ETIMEDOUT; | |
276 | } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT | | |
277 | MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) { | |
278 | cmd->error = -EILSEQ; | |
279 | } | |
280 | err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC | | |
281 | MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX | | |
282 | MVSD_ERR_CMD_STARTBIT); | |
283 | ||
284 | return err_status; | |
285 | } | |
286 | ||
287 | static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data, | |
288 | u32 err_status) | |
289 | { | |
290 | void __iomem *iobase = host->base; | |
291 | ||
292 | if (host->pio_ptr) { | |
293 | host->pio_ptr = NULL; | |
294 | host->pio_size = 0; | |
295 | } else { | |
296 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags, | |
feeef096 | 297 | mmc_get_dma_dir(data)); |
236caa7c MS |
298 | } |
299 | ||
300 | if (err_status & MVSD_ERR_DATA_TIMEOUT) | |
301 | data->error = -ETIMEDOUT; | |
302 | else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT)) | |
303 | data->error = -EILSEQ; | |
304 | else if (err_status & MVSD_ERR_XFER_SIZE) | |
305 | data->error = -EBADE; | |
306 | err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC | | |
307 | MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE); | |
308 | ||
309 | dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n", | |
310 | mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT)); | |
311 | data->bytes_xfered = | |
312 | (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz; | |
313 | /* We can't be sure about the last block when errors are detected */ | |
314 | if (data->bytes_xfered && data->error) | |
315 | data->bytes_xfered -= data->blksz; | |
316 | ||
317 | /* Handle Auto cmd 12 response */ | |
318 | if (data->stop) { | |
319 | unsigned int response[3], i; | |
320 | for (i = 0; i < 3; i++) | |
321 | response[i] = mvsd_read(MVSD_AUTO_RSP(i)); | |
322 | data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | | |
323 | ((response[1] & 0xffff) << (14 - 8)) | | |
324 | ((response[0] & 0x03ff) << (30 - 8)); | |
325 | data->stop->resp[1] = ((response[0] & 0xfc00) >> 10); | |
326 | data->stop->resp[2] = 0; | |
327 | data->stop->resp[3] = 0; | |
328 | ||
329 | if (err_status & MVSD_ERR_AUTOCMD12) { | |
330 | u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS); | |
331 | dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12); | |
332 | if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE) | |
333 | data->stop->error = -ENOEXEC; | |
334 | else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT) | |
335 | data->stop->error = -ETIMEDOUT; | |
336 | else if (err_cmd12) | |
337 | data->stop->error = -EILSEQ; | |
338 | err_status &= ~MVSD_ERR_AUTOCMD12; | |
339 | } | |
340 | } | |
341 | ||
342 | return err_status; | |
343 | } | |
344 | ||
345 | static irqreturn_t mvsd_irq(int irq, void *dev) | |
346 | { | |
347 | struct mvsd_host *host = dev; | |
348 | void __iomem *iobase = host->base; | |
349 | u32 intr_status, intr_done_mask; | |
350 | int irq_handled = 0; | |
351 | ||
352 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
353 | dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n", | |
354 | intr_status, mvsd_read(MVSD_NOR_INTR_EN), | |
355 | mvsd_read(MVSD_HW_STATE)); | |
356 | ||
b78871d0 SH |
357 | /* |
358 | * It looks like, SDIO IP can issue one late, spurious irq | |
359 | * although all irqs should be disabled. To work around this, | |
360 | * bail out early, if we didn't expect any irqs to occur. | |
361 | */ | |
362 | if (!mvsd_read(MVSD_NOR_INTR_EN) && !mvsd_read(MVSD_ERR_INTR_EN)) { | |
363 | dev_dbg(host->dev, "spurious irq detected intr 0x%04x intr_en 0x%04x erri 0x%04x erri_en 0x%04x\n", | |
364 | mvsd_read(MVSD_NOR_INTR_STATUS), | |
365 | mvsd_read(MVSD_NOR_INTR_EN), | |
366 | mvsd_read(MVSD_ERR_INTR_STATUS), | |
367 | mvsd_read(MVSD_ERR_INTR_EN)); | |
368 | return IRQ_HANDLED; | |
369 | } | |
370 | ||
236caa7c MS |
371 | spin_lock(&host->lock); |
372 | ||
373 | /* PIO handling, if needed. Messy business... */ | |
374 | if (host->pio_size && | |
375 | (intr_status & host->intr_en & | |
376 | (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) { | |
377 | u16 *p = host->pio_ptr; | |
378 | int s = host->pio_size; | |
379 | while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) { | |
380 | readsw(iobase + MVSD_FIFO, p, 16); | |
381 | p += 16; | |
382 | s -= 32; | |
383 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
384 | } | |
385 | /* | |
386 | * Normally we'd use < 32 here, but the RX_FIFO_8W bit | |
387 | * doesn't appear to assert when there is exactly 32 bytes | |
388 | * (8 words) left to fetch in a transfer. | |
389 | */ | |
390 | if (s <= 32) { | |
391 | while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) { | |
392 | put_unaligned(mvsd_read(MVSD_FIFO), p++); | |
393 | put_unaligned(mvsd_read(MVSD_FIFO), p++); | |
394 | s -= 4; | |
395 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
396 | } | |
397 | if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) { | |
398 | u16 val[2] = {0, 0}; | |
399 | val[0] = mvsd_read(MVSD_FIFO); | |
400 | val[1] = mvsd_read(MVSD_FIFO); | |
6cdbf734 | 401 | memcpy(p, ((void *)&val) + 4 - s, s); |
236caa7c MS |
402 | s = 0; |
403 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
404 | } | |
405 | if (s == 0) { | |
406 | host->intr_en &= | |
407 | ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W); | |
408 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
409 | } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) { | |
410 | host->intr_en &= ~MVSD_NOR_RX_FIFO_8W; | |
411 | host->intr_en |= MVSD_NOR_RX_READY; | |
412 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
413 | } | |
414 | } | |
415 | dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", | |
416 | s, intr_status, mvsd_read(MVSD_HW_STATE)); | |
417 | host->pio_ptr = p; | |
418 | host->pio_size = s; | |
419 | irq_handled = 1; | |
420 | } else if (host->pio_size && | |
421 | (intr_status & host->intr_en & | |
422 | (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) { | |
423 | u16 *p = host->pio_ptr; | |
424 | int s = host->pio_size; | |
425 | /* | |
426 | * The TX_FIFO_8W bit is unreliable. When set, bursting | |
427 | * 16 halfwords all at once in the FIFO drops data. Actually | |
428 | * TX_AVAIL does go off after only one word is pushed even if | |
429 | * TX_FIFO_8W remains set. | |
430 | */ | |
431 | while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) { | |
432 | mvsd_write(MVSD_FIFO, get_unaligned(p++)); | |
433 | mvsd_write(MVSD_FIFO, get_unaligned(p++)); | |
434 | s -= 4; | |
435 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
436 | } | |
437 | if (s < 4) { | |
438 | if (s && (intr_status & MVSD_NOR_TX_AVAIL)) { | |
439 | u16 val[2] = {0, 0}; | |
6cdbf734 | 440 | memcpy(((void *)&val) + 4 - s, p, s); |
236caa7c MS |
441 | mvsd_write(MVSD_FIFO, val[0]); |
442 | mvsd_write(MVSD_FIFO, val[1]); | |
443 | s = 0; | |
444 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
445 | } | |
446 | if (s == 0) { | |
447 | host->intr_en &= | |
448 | ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W); | |
449 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
450 | } | |
451 | } | |
452 | dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", | |
453 | s, intr_status, mvsd_read(MVSD_HW_STATE)); | |
454 | host->pio_ptr = p; | |
455 | host->pio_size = s; | |
456 | irq_handled = 1; | |
457 | } | |
458 | ||
459 | mvsd_write(MVSD_NOR_INTR_STATUS, intr_status); | |
460 | ||
461 | intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY | | |
462 | MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W; | |
463 | if (intr_status & host->intr_en & ~intr_done_mask) { | |
464 | struct mmc_request *mrq = host->mrq; | |
465 | struct mmc_command *cmd = mrq->cmd; | |
466 | u32 err_status = 0; | |
467 | ||
468 | del_timer(&host->timer); | |
469 | host->mrq = NULL; | |
470 | ||
471 | host->intr_en &= MVSD_NOR_CARD_INT; | |
472 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
473 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
474 | ||
475 | spin_unlock(&host->lock); | |
476 | ||
477 | if (intr_status & MVSD_NOR_UNEXP_RSP) { | |
478 | cmd->error = -EPROTO; | |
479 | } else if (intr_status & MVSD_NOR_ERROR) { | |
480 | err_status = mvsd_read(MVSD_ERR_INTR_STATUS); | |
481 | dev_dbg(host->dev, "err 0x%04x\n", err_status); | |
482 | } | |
483 | ||
484 | err_status = mvsd_finish_cmd(host, cmd, err_status); | |
485 | if (mrq->data) | |
486 | err_status = mvsd_finish_data(host, mrq->data, err_status); | |
487 | if (err_status) { | |
e573d698 TP |
488 | dev_err(host->dev, "unhandled error status %#04x\n", |
489 | err_status); | |
236caa7c MS |
490 | cmd->error = -ENOMSG; |
491 | } | |
492 | ||
493 | mmc_request_done(host->mmc, mrq); | |
494 | irq_handled = 1; | |
495 | } else | |
496 | spin_unlock(&host->lock); | |
497 | ||
498 | if (intr_status & MVSD_NOR_CARD_INT) { | |
499 | mmc_signal_sdio_irq(host->mmc); | |
500 | irq_handled = 1; | |
501 | } | |
502 | ||
503 | if (irq_handled) | |
504 | return IRQ_HANDLED; | |
505 | ||
e573d698 TP |
506 | dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n", |
507 | intr_status, host->intr_en, host->pio_size); | |
236caa7c MS |
508 | return IRQ_NONE; |
509 | } | |
510 | ||
511 | static void mvsd_timeout_timer(unsigned long data) | |
512 | { | |
513 | struct mvsd_host *host = (struct mvsd_host *)data; | |
514 | void __iomem *iobase = host->base; | |
515 | struct mmc_request *mrq; | |
516 | unsigned long flags; | |
517 | ||
518 | spin_lock_irqsave(&host->lock, flags); | |
519 | mrq = host->mrq; | |
520 | if (mrq) { | |
e573d698 TP |
521 | dev_err(host->dev, "Timeout waiting for hardware interrupt.\n"); |
522 | dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n", | |
523 | mvsd_read(MVSD_HW_STATE), | |
524 | mvsd_read(MVSD_NOR_INTR_STATUS), | |
525 | mvsd_read(MVSD_NOR_INTR_EN)); | |
236caa7c MS |
526 | |
527 | host->mrq = NULL; | |
528 | ||
529 | mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); | |
530 | ||
531 | host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; | |
532 | mvsd_write(MVSD_XFER_MODE, host->xfer_mode); | |
533 | ||
534 | host->intr_en &= MVSD_NOR_CARD_INT; | |
535 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
536 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
537 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
538 | ||
539 | mrq->cmd->error = -ETIMEDOUT; | |
540 | mvsd_finish_cmd(host, mrq->cmd, 0); | |
541 | if (mrq->data) { | |
542 | mrq->data->error = -ETIMEDOUT; | |
543 | mvsd_finish_data(host, mrq->data, 0); | |
544 | } | |
545 | } | |
546 | spin_unlock_irqrestore(&host->lock, flags); | |
547 | ||
548 | if (mrq) | |
549 | mmc_request_done(host->mmc, mrq); | |
550 | } | |
551 | ||
236caa7c MS |
552 | static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable) |
553 | { | |
554 | struct mvsd_host *host = mmc_priv(mmc); | |
555 | void __iomem *iobase = host->base; | |
556 | unsigned long flags; | |
557 | ||
558 | spin_lock_irqsave(&host->lock, flags); | |
559 | if (enable) { | |
560 | host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN; | |
561 | host->intr_en |= MVSD_NOR_CARD_INT; | |
562 | } else { | |
563 | host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN; | |
564 | host->intr_en &= ~MVSD_NOR_CARD_INT; | |
565 | } | |
566 | mvsd_write(MVSD_XFER_MODE, host->xfer_mode); | |
567 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
568 | spin_unlock_irqrestore(&host->lock, flags); | |
569 | } | |
570 | ||
236caa7c MS |
571 | static void mvsd_power_up(struct mvsd_host *host) |
572 | { | |
573 | void __iomem *iobase = host->base; | |
574 | dev_dbg(host->dev, "power up\n"); | |
575 | mvsd_write(MVSD_NOR_INTR_EN, 0); | |
576 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
577 | mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); | |
578 | mvsd_write(MVSD_XFER_MODE, 0); | |
579 | mvsd_write(MVSD_NOR_STATUS_EN, 0xffff); | |
580 | mvsd_write(MVSD_ERR_STATUS_EN, 0xffff); | |
581 | mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); | |
582 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
583 | } | |
584 | ||
585 | static void mvsd_power_down(struct mvsd_host *host) | |
586 | { | |
587 | void __iomem *iobase = host->base; | |
588 | dev_dbg(host->dev, "power down\n"); | |
589 | mvsd_write(MVSD_NOR_INTR_EN, 0); | |
590 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
591 | mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); | |
592 | mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); | |
593 | mvsd_write(MVSD_NOR_STATUS_EN, 0); | |
594 | mvsd_write(MVSD_ERR_STATUS_EN, 0); | |
595 | mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); | |
596 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
597 | } | |
598 | ||
599 | static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
600 | { | |
601 | struct mvsd_host *host = mmc_priv(mmc); | |
602 | void __iomem *iobase = host->base; | |
603 | u32 ctrl_reg = 0; | |
604 | ||
605 | if (ios->power_mode == MMC_POWER_UP) | |
606 | mvsd_power_up(host); | |
607 | ||
608 | if (ios->clock == 0) { | |
609 | mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); | |
610 | mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX); | |
611 | host->clock = 0; | |
612 | dev_dbg(host->dev, "clock off\n"); | |
613 | } else if (ios->clock != host->clock) { | |
614 | u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1; | |
615 | if (m > MVSD_BASE_DIV_MAX) | |
616 | m = MVSD_BASE_DIV_MAX; | |
617 | mvsd_write(MVSD_CLK_DIV, m); | |
618 | host->clock = ios->clock; | |
619 | host->ns_per_clk = 1000000000 / (host->base_clock / (m+1)); | |
620 | dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n", | |
621 | ios->clock, host->base_clock / (m+1), m); | |
622 | } | |
623 | ||
624 | /* default transfer mode */ | |
625 | ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN; | |
626 | ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST; | |
627 | ||
628 | /* default to maximum timeout */ | |
629 | ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK; | |
630 | ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN; | |
631 | ||
632 | if (ios->bus_mode == MMC_BUSMODE_PUSHPULL) | |
633 | ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN; | |
634 | ||
635 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
636 | ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS; | |
637 | ||
9ca6944c NP |
638 | /* |
639 | * The HI_SPEED_EN bit is causing trouble with many (but not all) | |
640 | * high speed SD, SDHC and SDIO cards. Not enabling that bit | |
641 | * makes all cards work. So let's just ignore that bit for now | |
642 | * and revisit this issue if problems for not enabling this bit | |
643 | * are ever reported. | |
644 | */ | |
645 | #if 0 | |
236caa7c MS |
646 | if (ios->timing == MMC_TIMING_MMC_HS || |
647 | ios->timing == MMC_TIMING_SD_HS) | |
648 | ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; | |
9ca6944c | 649 | #endif |
236caa7c MS |
650 | |
651 | host->ctrl = ctrl_reg; | |
652 | mvsd_write(MVSD_HOST_CTRL, ctrl_reg); | |
653 | dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg, | |
654 | (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ? | |
655 | "push-pull" : "open-drain", | |
656 | (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ? | |
657 | "4bit-width" : "1bit-width", | |
658 | (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ? | |
659 | "high-speed" : ""); | |
660 | ||
661 | if (ios->power_mode == MMC_POWER_OFF) | |
662 | mvsd_power_down(host); | |
663 | } | |
664 | ||
665 | static const struct mmc_host_ops mvsd_ops = { | |
666 | .request = mvsd_request, | |
3724482d | 667 | .get_ro = mmc_gpio_get_ro, |
236caa7c MS |
668 | .set_ios = mvsd_set_ios, |
669 | .enable_sdio_irq = mvsd_enable_sdio_irq, | |
670 | }; | |
671 | ||
1867adee | 672 | static void |
63a9332b AL |
673 | mv_conf_mbus_windows(struct mvsd_host *host, |
674 | const struct mbus_dram_target_info *dram) | |
236caa7c MS |
675 | { |
676 | void __iomem *iobase = host->base; | |
677 | int i; | |
678 | ||
679 | for (i = 0; i < 4; i++) { | |
680 | writel(0, iobase + MVSD_WINDOW_CTRL(i)); | |
681 | writel(0, iobase + MVSD_WINDOW_BASE(i)); | |
682 | } | |
683 | ||
684 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 685 | const struct mbus_dram_window *cs = dram->cs + i; |
236caa7c MS |
686 | writel(((cs->size - 1) & 0xffff0000) | |
687 | (cs->mbus_attr << 8) | | |
688 | (dram->mbus_dram_target_id << 4) | 1, | |
689 | iobase + MVSD_WINDOW_CTRL(i)); | |
690 | writel(cs->base, iobase + MVSD_WINDOW_BASE(i)); | |
691 | } | |
692 | } | |
693 | ||
1867adee | 694 | static int mvsd_probe(struct platform_device *pdev) |
236caa7c | 695 | { |
111936ff | 696 | struct device_node *np = pdev->dev.of_node; |
236caa7c MS |
697 | struct mmc_host *mmc = NULL; |
698 | struct mvsd_host *host = NULL; | |
63a9332b | 699 | const struct mbus_dram_target_info *dram; |
236caa7c MS |
700 | struct resource *r; |
701 | int ret, irq; | |
702 | ||
17da6783 LW |
703 | if (!np) { |
704 | dev_err(&pdev->dev, "no DT node\n"); | |
705 | return -ENODEV; | |
706 | } | |
236caa7c MS |
707 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
708 | irq = platform_get_irq(pdev, 0); | |
111936ff | 709 | if (!r || irq < 0) |
236caa7c MS |
710 | return -ENXIO; |
711 | ||
236caa7c MS |
712 | mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); |
713 | if (!mmc) { | |
714 | ret = -ENOMEM; | |
715 | goto out; | |
716 | } | |
717 | ||
718 | host = mmc_priv(mmc); | |
719 | host->mmc = mmc; | |
720 | host->dev = &pdev->dev; | |
111936ff TP |
721 | |
722 | /* | |
723 | * Some non-DT platforms do not pass a clock, and the clock | |
724 | * frequency is passed through platform_data. On DT platforms, | |
725 | * a clock must always be passed, even if there is no gatable | |
726 | * clock associated to the SDIO interface (it can simply be a | |
727 | * fixed rate clock). | |
728 | */ | |
729 | host->clk = devm_clk_get(&pdev->dev, NULL); | |
17da6783 LW |
730 | if (IS_ERR(host->clk)) { |
731 | dev_err(&pdev->dev, "no clock associated\n"); | |
732 | ret = -EINVAL; | |
733 | goto out; | |
734 | } | |
735 | clk_prepare_enable(host->clk); | |
111936ff | 736 | |
2cd17224 SB |
737 | mmc->ops = &mvsd_ops; |
738 | ||
739 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
740 | ||
741 | mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX); | |
742 | mmc->f_max = MVSD_CLOCKRATE_MAX; | |
743 | ||
744 | mmc->max_blk_size = 2048; | |
745 | mmc->max_blk_count = 65535; | |
746 | ||
747 | mmc->max_segs = 1; | |
748 | mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; | |
749 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
750 | ||
17da6783 LW |
751 | host->base_clock = clk_get_rate(host->clk) / 2; |
752 | ret = mmc_of_parse(mmc); | |
753 | if (ret < 0) | |
754 | goto out; | |
2cd17224 SB |
755 | if (maxfreq) |
756 | mmc->f_max = maxfreq; | |
236caa7c MS |
757 | |
758 | spin_lock_init(&host->lock); | |
759 | ||
e02d2930 SK |
760 | host->base = devm_ioremap_resource(&pdev->dev, r); |
761 | if (IS_ERR(host->base)) { | |
762 | ret = PTR_ERR(host->base); | |
236caa7c MS |
763 | goto out; |
764 | } | |
765 | ||
766 | /* (Re-)program MBUS remapping windows if we are asked to. */ | |
63a9332b AL |
767 | dram = mv_mbus_dram_info(); |
768 | if (dram) | |
769 | mv_conf_mbus_windows(host, dram); | |
236caa7c MS |
770 | |
771 | mvsd_power_down(host); | |
772 | ||
f42abc72 | 773 | ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host); |
236caa7c | 774 | if (ret) { |
e573d698 | 775 | dev_err(&pdev->dev, "cannot assign irq %d\n", irq); |
236caa7c | 776 | goto out; |
f42abc72 | 777 | } |
236caa7c | 778 | |
236caa7c MS |
779 | setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host); |
780 | platform_set_drvdata(pdev, mmc); | |
781 | ret = mmc_add_host(mmc); | |
782 | if (ret) | |
783 | goto out; | |
784 | ||
07728b77 | 785 | if (!(mmc->caps & MMC_CAP_NEEDS_POLL)) |
fcf902be | 786 | dev_dbg(&pdev->dev, "using GPIO for card detection\n"); |
236caa7c | 787 | else |
fcf902be SH |
788 | dev_dbg(&pdev->dev, "lacking card detect (fall back to polling)\n"); |
789 | ||
236caa7c MS |
790 | return 0; |
791 | ||
792 | out: | |
f42abc72 AL |
793 | if (mmc) { |
794 | if (!IS_ERR(host->clk)) | |
baffab28 | 795 | clk_disable_unprepare(host->clk); |
236caa7c | 796 | mmc_free_host(mmc); |
f42abc72 | 797 | } |
236caa7c MS |
798 | |
799 | return ret; | |
800 | } | |
801 | ||
1867adee | 802 | static int mvsd_remove(struct platform_device *pdev) |
236caa7c MS |
803 | { |
804 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
805 | ||
f42abc72 | 806 | struct mvsd_host *host = mmc_priv(mmc); |
236caa7c | 807 | |
f42abc72 AL |
808 | mmc_remove_host(mmc); |
809 | del_timer_sync(&host->timer); | |
810 | mvsd_power_down(host); | |
811 | ||
812 | if (!IS_ERR(host->clk)) | |
813 | clk_disable_unprepare(host->clk); | |
814 | mmc_free_host(mmc); | |
f4f7561e | 815 | |
236caa7c MS |
816 | return 0; |
817 | } | |
818 | ||
111936ff TP |
819 | static const struct of_device_id mvsdio_dt_ids[] = { |
820 | { .compatible = "marvell,orion-sdio" }, | |
821 | { /* sentinel */ } | |
822 | }; | |
823 | MODULE_DEVICE_TABLE(of, mvsdio_dt_ids); | |
824 | ||
236caa7c | 825 | static struct platform_driver mvsd_driver = { |
1867adee JH |
826 | .probe = mvsd_probe, |
827 | .remove = mvsd_remove, | |
236caa7c MS |
828 | .driver = { |
829 | .name = DRIVER_NAME, | |
111936ff | 830 | .of_match_table = mvsdio_dt_ids, |
236caa7c MS |
831 | }, |
832 | }; | |
833 | ||
1867adee | 834 | module_platform_driver(mvsd_driver); |
236caa7c MS |
835 | |
836 | /* maximum card clock frequency (default 50MHz) */ | |
837 | module_param(maxfreq, int, 0); | |
838 | ||
839 | /* force PIO transfers all the time */ | |
840 | module_param(nodma, int, 0); | |
841 | ||
842 | MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre"); | |
843 | MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver"); | |
844 | MODULE_LICENSE("GPL"); | |
703aaced | 845 | MODULE_ALIAS("platform:mvsdio"); |