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236caa7c MS |
1 | /* |
2 | * Marvell MMC/SD/SDIO driver | |
3 | * | |
4 | * Authors: Maen Suleiman, Nicolas Pitre | |
5 | * Copyright (C) 2008-2009 Marvell Ltd. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/io.h> | |
15 | #include <linux/platform_device.h> | |
16 | #include <linux/mbus.h> | |
17 | #include <linux/delay.h> | |
18 | #include <linux/interrupt.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | #include <linux/scatterlist.h> | |
21 | #include <linux/irq.h> | |
f4f7561e | 22 | #include <linux/clk.h> |
236caa7c MS |
23 | #include <linux/gpio.h> |
24 | #include <linux/mmc/host.h> | |
3724482d | 25 | #include <linux/mmc/slot-gpio.h> |
236caa7c MS |
26 | |
27 | #include <asm/sizes.h> | |
28 | #include <asm/unaligned.h> | |
c02cecb9 | 29 | #include <linux/platform_data/mmc-mvsdio.h> |
236caa7c MS |
30 | |
31 | #include "mvsdio.h" | |
32 | ||
33 | #define DRIVER_NAME "mvsdio" | |
34 | ||
35 | static int maxfreq = MVSD_CLOCKRATE_MAX; | |
36 | static int nodma; | |
37 | ||
38 | struct mvsd_host { | |
39 | void __iomem *base; | |
40 | struct mmc_request *mrq; | |
41 | spinlock_t lock; | |
42 | unsigned int xfer_mode; | |
43 | unsigned int intr_en; | |
44 | unsigned int ctrl; | |
45 | unsigned int pio_size; | |
46 | void *pio_ptr; | |
47 | unsigned int sg_frags; | |
48 | unsigned int ns_per_clk; | |
49 | unsigned int clock; | |
50 | unsigned int base_clock; | |
51 | struct timer_list timer; | |
52 | struct mmc_host *mmc; | |
53 | struct device *dev; | |
f4f7561e | 54 | struct clk *clk; |
236caa7c | 55 | int gpio_card_detect; |
236caa7c MS |
56 | }; |
57 | ||
58 | #define mvsd_write(offs, val) writel(val, iobase + (offs)) | |
59 | #define mvsd_read(offs) readl(iobase + (offs)) | |
60 | ||
61 | static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data) | |
62 | { | |
63 | void __iomem *iobase = host->base; | |
64 | unsigned int tmout; | |
65 | int tmout_index; | |
66 | ||
a6d297f0 NP |
67 | /* |
68 | * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE | |
69 | * register is sometimes not set before a while when some | |
70 | * "unusual" data block sizes are used (such as with the SWITCH | |
71 | * command), even despite the fact that the XFER_DONE interrupt | |
72 | * was raised. And if another data transfer starts before | |
73 | * this bit comes to good sense (which eventually happens by | |
74 | * itself) then the new transfer simply fails with a timeout. | |
75 | */ | |
76 | if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) { | |
77 | unsigned long t = jiffies + HZ; | |
78 | unsigned int hw_state, count = 0; | |
79 | do { | |
80 | if (time_after(jiffies, t)) { | |
81 | dev_warn(host->dev, "FIFO_EMPTY bit missing\n"); | |
82 | break; | |
83 | } | |
84 | hw_state = mvsd_read(MVSD_HW_STATE); | |
85 | count++; | |
86 | } while (!(hw_state & (1 << 13))); | |
87 | dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit " | |
88 | "(hw=0x%04x, count=%d, jiffies=%ld)\n", | |
89 | hw_state, count, jiffies - (t - HZ)); | |
90 | } | |
91 | ||
236caa7c MS |
92 | /* If timeout=0 then maximum timeout index is used. */ |
93 | tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk); | |
94 | tmout += data->timeout_clks; | |
95 | tmout_index = fls(tmout - 1) - 12; | |
96 | if (tmout_index < 0) | |
97 | tmout_index = 0; | |
98 | if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX) | |
99 | tmout_index = MVSD_HOST_CTRL_TMOUT_MAX; | |
100 | ||
101 | dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n", | |
102 | (data->flags & MMC_DATA_READ) ? "read" : "write", | |
103 | (u32)sg_virt(data->sg), data->blocks, data->blksz, | |
104 | tmout, tmout_index); | |
105 | ||
106 | host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK; | |
107 | host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index); | |
108 | mvsd_write(MVSD_HOST_CTRL, host->ctrl); | |
109 | mvsd_write(MVSD_BLK_COUNT, data->blocks); | |
110 | mvsd_write(MVSD_BLK_SIZE, data->blksz); | |
111 | ||
112 | if (nodma || (data->blksz | data->sg->offset) & 3) { | |
113 | /* | |
114 | * We cannot do DMA on a buffer which offset or size | |
115 | * is not aligned on a 4-byte boundary. | |
116 | */ | |
117 | host->pio_size = data->blocks * data->blksz; | |
118 | host->pio_ptr = sg_virt(data->sg); | |
119 | if (!nodma) | |
a3c76eb9 | 120 | pr_debug("%s: fallback to PIO for data " |
236caa7c MS |
121 | "at 0x%p size %d\n", |
122 | mmc_hostname(host->mmc), | |
123 | host->pio_ptr, host->pio_size); | |
124 | return 1; | |
125 | } else { | |
126 | dma_addr_t phys_addr; | |
127 | int dma_dir = (data->flags & MMC_DATA_READ) ? | |
128 | DMA_FROM_DEVICE : DMA_TO_DEVICE; | |
129 | host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
130 | data->sg_len, dma_dir); | |
131 | phys_addr = sg_dma_address(data->sg); | |
132 | mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff); | |
133 | mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16); | |
134 | return 0; | |
135 | } | |
136 | } | |
137 | ||
138 | static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
139 | { | |
140 | struct mvsd_host *host = mmc_priv(mmc); | |
141 | void __iomem *iobase = host->base; | |
142 | struct mmc_command *cmd = mrq->cmd; | |
143 | u32 cmdreg = 0, xfer = 0, intr = 0; | |
144 | unsigned long flags; | |
145 | ||
146 | BUG_ON(host->mrq != NULL); | |
147 | host->mrq = mrq; | |
148 | ||
149 | dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n", | |
150 | cmd->opcode, mvsd_read(MVSD_HW_STATE)); | |
151 | ||
152 | cmdreg = MVSD_CMD_INDEX(cmd->opcode); | |
153 | ||
154 | if (cmd->flags & MMC_RSP_BUSY) | |
155 | cmdreg |= MVSD_CMD_RSP_48BUSY; | |
156 | else if (cmd->flags & MMC_RSP_136) | |
157 | cmdreg |= MVSD_CMD_RSP_136; | |
158 | else if (cmd->flags & MMC_RSP_PRESENT) | |
159 | cmdreg |= MVSD_CMD_RSP_48; | |
160 | else | |
161 | cmdreg |= MVSD_CMD_RSP_NONE; | |
162 | ||
163 | if (cmd->flags & MMC_RSP_CRC) | |
164 | cmdreg |= MVSD_CMD_CHECK_CMDCRC; | |
165 | ||
166 | if (cmd->flags & MMC_RSP_OPCODE) | |
167 | cmdreg |= MVSD_CMD_INDX_CHECK; | |
168 | ||
169 | if (cmd->flags & MMC_RSP_PRESENT) { | |
170 | cmdreg |= MVSD_UNEXPECTED_RESP; | |
171 | intr |= MVSD_NOR_UNEXP_RSP; | |
172 | } | |
173 | ||
174 | if (mrq->data) { | |
175 | struct mmc_data *data = mrq->data; | |
176 | int pio; | |
177 | ||
178 | cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16; | |
179 | xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN; | |
180 | if (data->flags & MMC_DATA_READ) | |
181 | xfer |= MVSD_XFER_MODE_TO_HOST; | |
182 | ||
183 | pio = mvsd_setup_data(host, data); | |
184 | if (pio) { | |
185 | xfer |= MVSD_XFER_MODE_PIO; | |
186 | /* PIO section of mvsd_irq has comments on those bits */ | |
187 | if (data->flags & MMC_DATA_WRITE) | |
188 | intr |= MVSD_NOR_TX_AVAIL; | |
189 | else if (host->pio_size > 32) | |
190 | intr |= MVSD_NOR_RX_FIFO_8W; | |
191 | else | |
192 | intr |= MVSD_NOR_RX_READY; | |
193 | } | |
194 | ||
195 | if (data->stop) { | |
196 | struct mmc_command *stop = data->stop; | |
197 | u32 cmd12reg = 0; | |
198 | ||
199 | mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff); | |
200 | mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16); | |
201 | ||
202 | if (stop->flags & MMC_RSP_BUSY) | |
203 | cmd12reg |= MVSD_AUTOCMD12_BUSY; | |
204 | if (stop->flags & MMC_RSP_OPCODE) | |
205 | cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK; | |
206 | cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode); | |
207 | mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg); | |
208 | ||
209 | xfer |= MVSD_XFER_MODE_AUTO_CMD12; | |
210 | intr |= MVSD_NOR_AUTOCMD12_DONE; | |
211 | } else { | |
212 | intr |= MVSD_NOR_XFER_DONE; | |
213 | } | |
214 | } else { | |
215 | intr |= MVSD_NOR_CMD_DONE; | |
216 | } | |
217 | ||
218 | mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff); | |
219 | mvsd_write(MVSD_ARG_HI, cmd->arg >> 16); | |
220 | ||
221 | spin_lock_irqsave(&host->lock, flags); | |
222 | ||
223 | host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; | |
224 | host->xfer_mode |= xfer; | |
225 | mvsd_write(MVSD_XFER_MODE, host->xfer_mode); | |
226 | ||
227 | mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT); | |
228 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
229 | mvsd_write(MVSD_CMD, cmdreg); | |
230 | ||
231 | host->intr_en &= MVSD_NOR_CARD_INT; | |
232 | host->intr_en |= intr | MVSD_NOR_ERROR; | |
233 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
234 | mvsd_write(MVSD_ERR_INTR_EN, 0xffff); | |
235 | ||
236 | mod_timer(&host->timer, jiffies + 5 * HZ); | |
237 | ||
238 | spin_unlock_irqrestore(&host->lock, flags); | |
239 | } | |
240 | ||
241 | static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd, | |
242 | u32 err_status) | |
243 | { | |
244 | void __iomem *iobase = host->base; | |
245 | ||
246 | if (cmd->flags & MMC_RSP_136) { | |
247 | unsigned int response[8], i; | |
248 | for (i = 0; i < 8; i++) | |
249 | response[i] = mvsd_read(MVSD_RSP(i)); | |
250 | cmd->resp[0] = ((response[0] & 0x03ff) << 22) | | |
251 | ((response[1] & 0xffff) << 6) | | |
252 | ((response[2] & 0xfc00) >> 10); | |
253 | cmd->resp[1] = ((response[2] & 0x03ff) << 22) | | |
254 | ((response[3] & 0xffff) << 6) | | |
255 | ((response[4] & 0xfc00) >> 10); | |
256 | cmd->resp[2] = ((response[4] & 0x03ff) << 22) | | |
257 | ((response[5] & 0xffff) << 6) | | |
258 | ((response[6] & 0xfc00) >> 10); | |
259 | cmd->resp[3] = ((response[6] & 0x03ff) << 22) | | |
260 | ((response[7] & 0x3fff) << 8); | |
261 | } else if (cmd->flags & MMC_RSP_PRESENT) { | |
262 | unsigned int response[3], i; | |
263 | for (i = 0; i < 3; i++) | |
264 | response[i] = mvsd_read(MVSD_RSP(i)); | |
265 | cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | | |
266 | ((response[1] & 0xffff) << (14 - 8)) | | |
267 | ((response[0] & 0x03ff) << (30 - 8)); | |
268 | cmd->resp[1] = ((response[0] & 0xfc00) >> 10); | |
269 | cmd->resp[2] = 0; | |
270 | cmd->resp[3] = 0; | |
271 | } | |
272 | ||
273 | if (err_status & MVSD_ERR_CMD_TIMEOUT) { | |
274 | cmd->error = -ETIMEDOUT; | |
275 | } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT | | |
276 | MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) { | |
277 | cmd->error = -EILSEQ; | |
278 | } | |
279 | err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC | | |
280 | MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX | | |
281 | MVSD_ERR_CMD_STARTBIT); | |
282 | ||
283 | return err_status; | |
284 | } | |
285 | ||
286 | static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data, | |
287 | u32 err_status) | |
288 | { | |
289 | void __iomem *iobase = host->base; | |
290 | ||
291 | if (host->pio_ptr) { | |
292 | host->pio_ptr = NULL; | |
293 | host->pio_size = 0; | |
294 | } else { | |
295 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags, | |
296 | (data->flags & MMC_DATA_READ) ? | |
297 | DMA_FROM_DEVICE : DMA_TO_DEVICE); | |
298 | } | |
299 | ||
300 | if (err_status & MVSD_ERR_DATA_TIMEOUT) | |
301 | data->error = -ETIMEDOUT; | |
302 | else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT)) | |
303 | data->error = -EILSEQ; | |
304 | else if (err_status & MVSD_ERR_XFER_SIZE) | |
305 | data->error = -EBADE; | |
306 | err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC | | |
307 | MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE); | |
308 | ||
309 | dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n", | |
310 | mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT)); | |
311 | data->bytes_xfered = | |
312 | (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz; | |
313 | /* We can't be sure about the last block when errors are detected */ | |
314 | if (data->bytes_xfered && data->error) | |
315 | data->bytes_xfered -= data->blksz; | |
316 | ||
317 | /* Handle Auto cmd 12 response */ | |
318 | if (data->stop) { | |
319 | unsigned int response[3], i; | |
320 | for (i = 0; i < 3; i++) | |
321 | response[i] = mvsd_read(MVSD_AUTO_RSP(i)); | |
322 | data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) | | |
323 | ((response[1] & 0xffff) << (14 - 8)) | | |
324 | ((response[0] & 0x03ff) << (30 - 8)); | |
325 | data->stop->resp[1] = ((response[0] & 0xfc00) >> 10); | |
326 | data->stop->resp[2] = 0; | |
327 | data->stop->resp[3] = 0; | |
328 | ||
329 | if (err_status & MVSD_ERR_AUTOCMD12) { | |
330 | u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS); | |
331 | dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12); | |
332 | if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE) | |
333 | data->stop->error = -ENOEXEC; | |
334 | else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT) | |
335 | data->stop->error = -ETIMEDOUT; | |
336 | else if (err_cmd12) | |
337 | data->stop->error = -EILSEQ; | |
338 | err_status &= ~MVSD_ERR_AUTOCMD12; | |
339 | } | |
340 | } | |
341 | ||
342 | return err_status; | |
343 | } | |
344 | ||
345 | static irqreturn_t mvsd_irq(int irq, void *dev) | |
346 | { | |
347 | struct mvsd_host *host = dev; | |
348 | void __iomem *iobase = host->base; | |
349 | u32 intr_status, intr_done_mask; | |
350 | int irq_handled = 0; | |
351 | ||
352 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
353 | dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n", | |
354 | intr_status, mvsd_read(MVSD_NOR_INTR_EN), | |
355 | mvsd_read(MVSD_HW_STATE)); | |
356 | ||
357 | spin_lock(&host->lock); | |
358 | ||
359 | /* PIO handling, if needed. Messy business... */ | |
360 | if (host->pio_size && | |
361 | (intr_status & host->intr_en & | |
362 | (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) { | |
363 | u16 *p = host->pio_ptr; | |
364 | int s = host->pio_size; | |
365 | while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) { | |
366 | readsw(iobase + MVSD_FIFO, p, 16); | |
367 | p += 16; | |
368 | s -= 32; | |
369 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
370 | } | |
371 | /* | |
372 | * Normally we'd use < 32 here, but the RX_FIFO_8W bit | |
373 | * doesn't appear to assert when there is exactly 32 bytes | |
374 | * (8 words) left to fetch in a transfer. | |
375 | */ | |
376 | if (s <= 32) { | |
377 | while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) { | |
378 | put_unaligned(mvsd_read(MVSD_FIFO), p++); | |
379 | put_unaligned(mvsd_read(MVSD_FIFO), p++); | |
380 | s -= 4; | |
381 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
382 | } | |
383 | if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) { | |
384 | u16 val[2] = {0, 0}; | |
385 | val[0] = mvsd_read(MVSD_FIFO); | |
386 | val[1] = mvsd_read(MVSD_FIFO); | |
6cdbf734 | 387 | memcpy(p, ((void *)&val) + 4 - s, s); |
236caa7c MS |
388 | s = 0; |
389 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
390 | } | |
391 | if (s == 0) { | |
392 | host->intr_en &= | |
393 | ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W); | |
394 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
395 | } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) { | |
396 | host->intr_en &= ~MVSD_NOR_RX_FIFO_8W; | |
397 | host->intr_en |= MVSD_NOR_RX_READY; | |
398 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
399 | } | |
400 | } | |
401 | dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", | |
402 | s, intr_status, mvsd_read(MVSD_HW_STATE)); | |
403 | host->pio_ptr = p; | |
404 | host->pio_size = s; | |
405 | irq_handled = 1; | |
406 | } else if (host->pio_size && | |
407 | (intr_status & host->intr_en & | |
408 | (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) { | |
409 | u16 *p = host->pio_ptr; | |
410 | int s = host->pio_size; | |
411 | /* | |
412 | * The TX_FIFO_8W bit is unreliable. When set, bursting | |
413 | * 16 halfwords all at once in the FIFO drops data. Actually | |
414 | * TX_AVAIL does go off after only one word is pushed even if | |
415 | * TX_FIFO_8W remains set. | |
416 | */ | |
417 | while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) { | |
418 | mvsd_write(MVSD_FIFO, get_unaligned(p++)); | |
419 | mvsd_write(MVSD_FIFO, get_unaligned(p++)); | |
420 | s -= 4; | |
421 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
422 | } | |
423 | if (s < 4) { | |
424 | if (s && (intr_status & MVSD_NOR_TX_AVAIL)) { | |
425 | u16 val[2] = {0, 0}; | |
6cdbf734 | 426 | memcpy(((void *)&val) + 4 - s, p, s); |
236caa7c MS |
427 | mvsd_write(MVSD_FIFO, val[0]); |
428 | mvsd_write(MVSD_FIFO, val[1]); | |
429 | s = 0; | |
430 | intr_status = mvsd_read(MVSD_NOR_INTR_STATUS); | |
431 | } | |
432 | if (s == 0) { | |
433 | host->intr_en &= | |
434 | ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W); | |
435 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
436 | } | |
437 | } | |
438 | dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n", | |
439 | s, intr_status, mvsd_read(MVSD_HW_STATE)); | |
440 | host->pio_ptr = p; | |
441 | host->pio_size = s; | |
442 | irq_handled = 1; | |
443 | } | |
444 | ||
445 | mvsd_write(MVSD_NOR_INTR_STATUS, intr_status); | |
446 | ||
447 | intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY | | |
448 | MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W; | |
449 | if (intr_status & host->intr_en & ~intr_done_mask) { | |
450 | struct mmc_request *mrq = host->mrq; | |
451 | struct mmc_command *cmd = mrq->cmd; | |
452 | u32 err_status = 0; | |
453 | ||
454 | del_timer(&host->timer); | |
455 | host->mrq = NULL; | |
456 | ||
457 | host->intr_en &= MVSD_NOR_CARD_INT; | |
458 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
459 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
460 | ||
461 | spin_unlock(&host->lock); | |
462 | ||
463 | if (intr_status & MVSD_NOR_UNEXP_RSP) { | |
464 | cmd->error = -EPROTO; | |
465 | } else if (intr_status & MVSD_NOR_ERROR) { | |
466 | err_status = mvsd_read(MVSD_ERR_INTR_STATUS); | |
467 | dev_dbg(host->dev, "err 0x%04x\n", err_status); | |
468 | } | |
469 | ||
470 | err_status = mvsd_finish_cmd(host, cmd, err_status); | |
471 | if (mrq->data) | |
472 | err_status = mvsd_finish_data(host, mrq->data, err_status); | |
473 | if (err_status) { | |
a3c76eb9 | 474 | pr_err("%s: unhandled error status %#04x\n", |
236caa7c MS |
475 | mmc_hostname(host->mmc), err_status); |
476 | cmd->error = -ENOMSG; | |
477 | } | |
478 | ||
479 | mmc_request_done(host->mmc, mrq); | |
480 | irq_handled = 1; | |
481 | } else | |
482 | spin_unlock(&host->lock); | |
483 | ||
484 | if (intr_status & MVSD_NOR_CARD_INT) { | |
485 | mmc_signal_sdio_irq(host->mmc); | |
486 | irq_handled = 1; | |
487 | } | |
488 | ||
489 | if (irq_handled) | |
490 | return IRQ_HANDLED; | |
491 | ||
a3c76eb9 | 492 | pr_err("%s: unhandled interrupt status=0x%04x en=0x%04x " |
236caa7c MS |
493 | "pio=%d\n", mmc_hostname(host->mmc), intr_status, |
494 | host->intr_en, host->pio_size); | |
495 | return IRQ_NONE; | |
496 | } | |
497 | ||
498 | static void mvsd_timeout_timer(unsigned long data) | |
499 | { | |
500 | struct mvsd_host *host = (struct mvsd_host *)data; | |
501 | void __iomem *iobase = host->base; | |
502 | struct mmc_request *mrq; | |
503 | unsigned long flags; | |
504 | ||
505 | spin_lock_irqsave(&host->lock, flags); | |
506 | mrq = host->mrq; | |
507 | if (mrq) { | |
a3c76eb9 | 508 | pr_err("%s: Timeout waiting for hardware interrupt.\n", |
236caa7c | 509 | mmc_hostname(host->mmc)); |
a3c76eb9 | 510 | pr_err("%s: hw_state=0x%04x, intr_status=0x%04x " |
236caa7c MS |
511 | "intr_en=0x%04x\n", mmc_hostname(host->mmc), |
512 | mvsd_read(MVSD_HW_STATE), | |
513 | mvsd_read(MVSD_NOR_INTR_STATUS), | |
514 | mvsd_read(MVSD_NOR_INTR_EN)); | |
515 | ||
516 | host->mrq = NULL; | |
517 | ||
518 | mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); | |
519 | ||
520 | host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN; | |
521 | mvsd_write(MVSD_XFER_MODE, host->xfer_mode); | |
522 | ||
523 | host->intr_en &= MVSD_NOR_CARD_INT; | |
524 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
525 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
526 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
527 | ||
528 | mrq->cmd->error = -ETIMEDOUT; | |
529 | mvsd_finish_cmd(host, mrq->cmd, 0); | |
530 | if (mrq->data) { | |
531 | mrq->data->error = -ETIMEDOUT; | |
532 | mvsd_finish_data(host, mrq->data, 0); | |
533 | } | |
534 | } | |
535 | spin_unlock_irqrestore(&host->lock, flags); | |
536 | ||
537 | if (mrq) | |
538 | mmc_request_done(host->mmc, mrq); | |
539 | } | |
540 | ||
541 | static irqreturn_t mvsd_card_detect_irq(int irq, void *dev) | |
542 | { | |
543 | struct mvsd_host *host = dev; | |
544 | mmc_detect_change(host->mmc, msecs_to_jiffies(100)); | |
545 | return IRQ_HANDLED; | |
546 | } | |
547 | ||
548 | static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable) | |
549 | { | |
550 | struct mvsd_host *host = mmc_priv(mmc); | |
551 | void __iomem *iobase = host->base; | |
552 | unsigned long flags; | |
553 | ||
554 | spin_lock_irqsave(&host->lock, flags); | |
555 | if (enable) { | |
556 | host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN; | |
557 | host->intr_en |= MVSD_NOR_CARD_INT; | |
558 | } else { | |
559 | host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN; | |
560 | host->intr_en &= ~MVSD_NOR_CARD_INT; | |
561 | } | |
562 | mvsd_write(MVSD_XFER_MODE, host->xfer_mode); | |
563 | mvsd_write(MVSD_NOR_INTR_EN, host->intr_en); | |
564 | spin_unlock_irqrestore(&host->lock, flags); | |
565 | } | |
566 | ||
236caa7c MS |
567 | static void mvsd_power_up(struct mvsd_host *host) |
568 | { | |
569 | void __iomem *iobase = host->base; | |
570 | dev_dbg(host->dev, "power up\n"); | |
571 | mvsd_write(MVSD_NOR_INTR_EN, 0); | |
572 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
573 | mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); | |
574 | mvsd_write(MVSD_XFER_MODE, 0); | |
575 | mvsd_write(MVSD_NOR_STATUS_EN, 0xffff); | |
576 | mvsd_write(MVSD_ERR_STATUS_EN, 0xffff); | |
577 | mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); | |
578 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
579 | } | |
580 | ||
581 | static void mvsd_power_down(struct mvsd_host *host) | |
582 | { | |
583 | void __iomem *iobase = host->base; | |
584 | dev_dbg(host->dev, "power down\n"); | |
585 | mvsd_write(MVSD_NOR_INTR_EN, 0); | |
586 | mvsd_write(MVSD_ERR_INTR_EN, 0); | |
587 | mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW); | |
588 | mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); | |
589 | mvsd_write(MVSD_NOR_STATUS_EN, 0); | |
590 | mvsd_write(MVSD_ERR_STATUS_EN, 0); | |
591 | mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff); | |
592 | mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff); | |
593 | } | |
594 | ||
595 | static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
596 | { | |
597 | struct mvsd_host *host = mmc_priv(mmc); | |
598 | void __iomem *iobase = host->base; | |
599 | u32 ctrl_reg = 0; | |
600 | ||
601 | if (ios->power_mode == MMC_POWER_UP) | |
602 | mvsd_power_up(host); | |
603 | ||
604 | if (ios->clock == 0) { | |
605 | mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK); | |
606 | mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX); | |
607 | host->clock = 0; | |
608 | dev_dbg(host->dev, "clock off\n"); | |
609 | } else if (ios->clock != host->clock) { | |
610 | u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1; | |
611 | if (m > MVSD_BASE_DIV_MAX) | |
612 | m = MVSD_BASE_DIV_MAX; | |
613 | mvsd_write(MVSD_CLK_DIV, m); | |
614 | host->clock = ios->clock; | |
615 | host->ns_per_clk = 1000000000 / (host->base_clock / (m+1)); | |
616 | dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n", | |
617 | ios->clock, host->base_clock / (m+1), m); | |
618 | } | |
619 | ||
620 | /* default transfer mode */ | |
621 | ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN; | |
622 | ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST; | |
623 | ||
624 | /* default to maximum timeout */ | |
625 | ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK; | |
626 | ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN; | |
627 | ||
628 | if (ios->bus_mode == MMC_BUSMODE_PUSHPULL) | |
629 | ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN; | |
630 | ||
631 | if (ios->bus_width == MMC_BUS_WIDTH_4) | |
632 | ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS; | |
633 | ||
9ca6944c NP |
634 | /* |
635 | * The HI_SPEED_EN bit is causing trouble with many (but not all) | |
636 | * high speed SD, SDHC and SDIO cards. Not enabling that bit | |
637 | * makes all cards work. So let's just ignore that bit for now | |
638 | * and revisit this issue if problems for not enabling this bit | |
639 | * are ever reported. | |
640 | */ | |
641 | #if 0 | |
236caa7c MS |
642 | if (ios->timing == MMC_TIMING_MMC_HS || |
643 | ios->timing == MMC_TIMING_SD_HS) | |
644 | ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN; | |
9ca6944c | 645 | #endif |
236caa7c MS |
646 | |
647 | host->ctrl = ctrl_reg; | |
648 | mvsd_write(MVSD_HOST_CTRL, ctrl_reg); | |
649 | dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg, | |
650 | (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ? | |
651 | "push-pull" : "open-drain", | |
652 | (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ? | |
653 | "4bit-width" : "1bit-width", | |
654 | (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ? | |
655 | "high-speed" : ""); | |
656 | ||
657 | if (ios->power_mode == MMC_POWER_OFF) | |
658 | mvsd_power_down(host); | |
659 | } | |
660 | ||
661 | static const struct mmc_host_ops mvsd_ops = { | |
662 | .request = mvsd_request, | |
3724482d | 663 | .get_ro = mmc_gpio_get_ro, |
236caa7c MS |
664 | .set_ios = mvsd_set_ios, |
665 | .enable_sdio_irq = mvsd_enable_sdio_irq, | |
666 | }; | |
667 | ||
63a9332b AL |
668 | static void __init |
669 | mv_conf_mbus_windows(struct mvsd_host *host, | |
670 | const struct mbus_dram_target_info *dram) | |
236caa7c MS |
671 | { |
672 | void __iomem *iobase = host->base; | |
673 | int i; | |
674 | ||
675 | for (i = 0; i < 4; i++) { | |
676 | writel(0, iobase + MVSD_WINDOW_CTRL(i)); | |
677 | writel(0, iobase + MVSD_WINDOW_BASE(i)); | |
678 | } | |
679 | ||
680 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 681 | const struct mbus_dram_window *cs = dram->cs + i; |
236caa7c MS |
682 | writel(((cs->size - 1) & 0xffff0000) | |
683 | (cs->mbus_attr << 8) | | |
684 | (dram->mbus_dram_target_id << 4) | 1, | |
685 | iobase + MVSD_WINDOW_CTRL(i)); | |
686 | writel(cs->base, iobase + MVSD_WINDOW_BASE(i)); | |
687 | } | |
688 | } | |
689 | ||
690 | static int __init mvsd_probe(struct platform_device *pdev) | |
691 | { | |
692 | struct mmc_host *mmc = NULL; | |
693 | struct mvsd_host *host = NULL; | |
694 | const struct mvsdio_platform_data *mvsd_data; | |
63a9332b | 695 | const struct mbus_dram_target_info *dram; |
236caa7c MS |
696 | struct resource *r; |
697 | int ret, irq; | |
698 | ||
699 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
700 | irq = platform_get_irq(pdev, 0); | |
701 | mvsd_data = pdev->dev.platform_data; | |
702 | if (!r || irq < 0 || !mvsd_data) | |
703 | return -ENXIO; | |
704 | ||
236caa7c MS |
705 | mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev); |
706 | if (!mmc) { | |
707 | ret = -ENOMEM; | |
708 | goto out; | |
709 | } | |
710 | ||
711 | host = mmc_priv(mmc); | |
712 | host->mmc = mmc; | |
713 | host->dev = &pdev->dev; | |
236caa7c | 714 | host->base_clock = mvsd_data->clock / 2; |
f42abc72 | 715 | host->clk = ERR_PTR(-EINVAL); |
236caa7c MS |
716 | |
717 | mmc->ops = &mvsd_ops; | |
718 | ||
719 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; | |
720 | mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ | | |
721 | MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; | |
722 | ||
723 | mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX); | |
724 | mmc->f_max = maxfreq; | |
725 | ||
726 | mmc->max_blk_size = 2048; | |
727 | mmc->max_blk_count = 65535; | |
728 | ||
a36274e0 | 729 | mmc->max_segs = 1; |
236caa7c MS |
730 | mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count; |
731 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
732 | ||
733 | spin_lock_init(&host->lock); | |
734 | ||
f42abc72 | 735 | host->base = devm_request_and_ioremap(&pdev->dev, r); |
236caa7c MS |
736 | if (!host->base) { |
737 | ret = -ENOMEM; | |
738 | goto out; | |
739 | } | |
740 | ||
741 | /* (Re-)program MBUS remapping windows if we are asked to. */ | |
63a9332b AL |
742 | dram = mv_mbus_dram_info(); |
743 | if (dram) | |
744 | mv_conf_mbus_windows(host, dram); | |
236caa7c MS |
745 | |
746 | mvsd_power_down(host); | |
747 | ||
f42abc72 | 748 | ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host); |
236caa7c | 749 | if (ret) { |
a3c76eb9 | 750 | pr_err("%s: cannot assign irq %d\n", DRIVER_NAME, irq); |
236caa7c | 751 | goto out; |
f42abc72 | 752 | } |
236caa7c | 753 | |
f4f7561e AL |
754 | /* Not all platforms can gate the clock, so it is not |
755 | an error if the clock does not exists. */ | |
f42abc72 AL |
756 | host->clk = devm_clk_get(&pdev->dev, NULL); |
757 | if (!IS_ERR(host->clk)) | |
f4f7561e | 758 | clk_prepare_enable(host->clk); |
f4f7561e | 759 | |
236caa7c | 760 | if (mvsd_data->gpio_card_detect) { |
f42abc72 AL |
761 | ret = devm_gpio_request_one(&pdev->dev, |
762 | mvsd_data->gpio_card_detect, | |
763 | GPIOF_IN, DRIVER_NAME " cd"); | |
236caa7c | 764 | if (ret == 0) { |
236caa7c | 765 | irq = gpio_to_irq(mvsd_data->gpio_card_detect); |
f42abc72 AL |
766 | ret = devm_request_irq(&pdev->dev, irq, |
767 | mvsd_card_detect_irq, | |
768 | IRQ_TYPE_EDGE_RISING | | |
769 | IRQ_TYPE_EDGE_FALLING, | |
770 | DRIVER_NAME " cd", host); | |
236caa7c MS |
771 | if (ret == 0) |
772 | host->gpio_card_detect = | |
773 | mvsd_data->gpio_card_detect; | |
774 | else | |
f42abc72 AL |
775 | devm_gpio_free(&pdev->dev, |
776 | mvsd_data->gpio_card_detect); | |
236caa7c MS |
777 | } |
778 | } | |
779 | if (!host->gpio_card_detect) | |
780 | mmc->caps |= MMC_CAP_NEEDS_POLL; | |
781 | ||
3724482d | 782 | mmc_gpio_request_ro(mmc, mvsd_data->gpio_write_protect); |
236caa7c MS |
783 | |
784 | setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host); | |
785 | platform_set_drvdata(pdev, mmc); | |
786 | ret = mmc_add_host(mmc); | |
787 | if (ret) | |
788 | goto out; | |
789 | ||
a3c76eb9 | 790 | pr_notice("%s: %s driver initialized, ", |
236caa7c MS |
791 | mmc_hostname(mmc), DRIVER_NAME); |
792 | if (host->gpio_card_detect) | |
793 | printk("using GPIO %d for card detection\n", | |
794 | host->gpio_card_detect); | |
795 | else | |
796 | printk("lacking card detect (fall back to polling)\n"); | |
797 | return 0; | |
798 | ||
799 | out: | |
f42abc72 | 800 | if (mmc) { |
3724482d | 801 | mmc_gpio_free_ro(mmc); |
f42abc72 | 802 | if (!IS_ERR(host->clk)) |
baffab28 | 803 | clk_disable_unprepare(host->clk); |
236caa7c | 804 | mmc_free_host(mmc); |
f42abc72 | 805 | } |
236caa7c MS |
806 | |
807 | return ret; | |
808 | } | |
809 | ||
810 | static int __exit mvsd_remove(struct platform_device *pdev) | |
811 | { | |
812 | struct mmc_host *mmc = platform_get_drvdata(pdev); | |
813 | ||
f42abc72 | 814 | struct mvsd_host *host = mmc_priv(mmc); |
236caa7c | 815 | |
3724482d | 816 | mmc_gpio_free_ro(mmc); |
f42abc72 AL |
817 | mmc_remove_host(mmc); |
818 | del_timer_sync(&host->timer); | |
819 | mvsd_power_down(host); | |
820 | ||
821 | if (!IS_ERR(host->clk)) | |
822 | clk_disable_unprepare(host->clk); | |
823 | mmc_free_host(mmc); | |
f4f7561e | 824 | |
236caa7c MS |
825 | platform_set_drvdata(pdev, NULL); |
826 | return 0; | |
827 | } | |
828 | ||
829 | #ifdef CONFIG_PM | |
2e058a6f | 830 | static int mvsd_suspend(struct platform_device *dev, pm_message_t state) |
236caa7c MS |
831 | { |
832 | struct mmc_host *mmc = platform_get_drvdata(dev); | |
833 | int ret = 0; | |
834 | ||
2e058a6f | 835 | if (mmc) |
1a13f8fa | 836 | ret = mmc_suspend_host(mmc); |
236caa7c MS |
837 | |
838 | return ret; | |
839 | } | |
840 | ||
2e058a6f | 841 | static int mvsd_resume(struct platform_device *dev) |
236caa7c | 842 | { |
2e058a6f | 843 | struct mmc_host *mmc = platform_get_drvdata(dev); |
236caa7c MS |
844 | int ret = 0; |
845 | ||
2e058a6f | 846 | if (mmc) |
236caa7c MS |
847 | ret = mmc_resume_host(mmc); |
848 | ||
849 | return ret; | |
850 | } | |
851 | #else | |
852 | #define mvsd_suspend NULL | |
853 | #define mvsd_resume NULL | |
854 | #endif | |
855 | ||
856 | static struct platform_driver mvsd_driver = { | |
857 | .remove = __exit_p(mvsd_remove), | |
858 | .suspend = mvsd_suspend, | |
859 | .resume = mvsd_resume, | |
860 | .driver = { | |
861 | .name = DRIVER_NAME, | |
862 | }, | |
863 | }; | |
864 | ||
865 | static int __init mvsd_init(void) | |
866 | { | |
867 | return platform_driver_probe(&mvsd_driver, mvsd_probe); | |
868 | } | |
869 | ||
870 | static void __exit mvsd_exit(void) | |
871 | { | |
872 | platform_driver_unregister(&mvsd_driver); | |
873 | } | |
874 | ||
875 | module_init(mvsd_init); | |
876 | module_exit(mvsd_exit); | |
877 | ||
878 | /* maximum card clock frequency (default 50MHz) */ | |
879 | module_param(maxfreq, int, 0); | |
880 | ||
881 | /* force PIO transfers all the time */ | |
882 | module_param(nodma, int, 0); | |
883 | ||
884 | MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre"); | |
885 | MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver"); | |
886 | MODULE_LICENSE("GPL"); | |
703aaced | 887 | MODULE_ALIAS("platform:mvsdio"); |