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mmc: mvsdio: use dev_*() API instead of pr_*() API
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / mvsdio.c
CommitLineData
236caa7c
MS		 1/*
2 * Marvell MMC/SD/SDIO driver
3 *
4 * Authors: Maen Suleiman, Nicolas Pitre
5 * Copyright (C) 2008-2009 Marvell Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/io.h>
15#include <linux/platform_device.h>
16#include <linux/mbus.h>
17#include <linux/delay.h>
18#include <linux/interrupt.h>
19#include <linux/dma-mapping.h>
20#include <linux/scatterlist.h>
21#include <linux/irq.h>
f4f7561e 22#include <linux/clk.h>
236caa7c 23#include <linux/gpio.h>
111936ff
TP		 24#include <linux/of_gpio.h>
25#include <linux/of_irq.h>
236caa7c 26#include <linux/mmc/host.h>
3724482d 27#include <linux/mmc/slot-gpio.h>
6f1989bc 28#include <linux/pinctrl/consumer.h>
236caa7c
MS		 29
30#include <asm/sizes.h>
31#include <asm/unaligned.h>
c02cecb9 32#include <linux/platform_data/mmc-mvsdio.h>
236caa7c
MS		 33
34#include "mvsdio.h"
35
36#define DRIVER_NAME "mvsdio"
37
38static int maxfreq = MVSD_CLOCKRATE_MAX;
39static int nodma;
40
41struct mvsd_host {
42 void __iomem *base;
43 struct mmc_request *mrq;
44 spinlock_t lock;
45 unsigned int xfer_mode;
46 unsigned int intr_en;
47 unsigned int ctrl;
48 unsigned int pio_size;
49 void *pio_ptr;
50 unsigned int sg_frags;
51 unsigned int ns_per_clk;
52 unsigned int clock;
53 unsigned int base_clock;
54 struct timer_list timer;
55 struct mmc_host *mmc;
56 struct device *dev;
f4f7561e 57 struct clk *clk;
236caa7c
MS		 58};
59
60#define mvsd_write(offs, val) writel(val, iobase + (offs))
61#define mvsd_read(offs) readl(iobase + (offs))
62
63static int mvsd_setup_data(struct mvsd_host *host, struct mmc_data *data)
64{
65 void __iomem *iobase = host->base;
66 unsigned int tmout;
67 int tmout_index;
68
a6d297f0
NP		 69 /*
70 * Hardware weirdness. The FIFO_EMPTY bit of the HW_STATE
71 * register is sometimes not set before a while when some
72 * "unusual" data block sizes are used (such as with the SWITCH
73 * command), even despite the fact that the XFER_DONE interrupt
74 * was raised. And if another data transfer starts before
75 * this bit comes to good sense (which eventually happens by
76 * itself) then the new transfer simply fails with a timeout.
77 */
78 if (!(mvsd_read(MVSD_HW_STATE) & (1 << 13))) {
79 unsigned long t = jiffies + HZ;
80 unsigned int hw_state, count = 0;
81 do {
82 if (time_after(jiffies, t)) {
83 dev_warn(host->dev, "FIFO_EMPTY bit missing\n");
84 break;
85 }
86 hw_state = mvsd_read(MVSD_HW_STATE);
87 count++;
88 } while (!(hw_state & (1 << 13)));
89 dev_dbg(host->dev, "*** wait for FIFO_EMPTY bit "
90 "(hw=0x%04x, count=%d, jiffies=%ld)\n",
91 hw_state, count, jiffies - (t - HZ));
92 }
93
236caa7c
MS		 94 /* If timeout=0 then maximum timeout index is used. */
95 tmout = DIV_ROUND_UP(data->timeout_ns, host->ns_per_clk);
96 tmout += data->timeout_clks;
97 tmout_index = fls(tmout - 1) - 12;
98 if (tmout_index < 0)
99 tmout_index = 0;
100 if (tmout_index > MVSD_HOST_CTRL_TMOUT_MAX)
101 tmout_index = MVSD_HOST_CTRL_TMOUT_MAX;
102
103 dev_dbg(host->dev, "data %s at 0x%08x: blocks=%d blksz=%d tmout=%u (%d)\n",
104 (data->flags & MMC_DATA_READ) ? "read" : "write",
105 (u32)sg_virt(data->sg), data->blocks, data->blksz,
106 tmout, tmout_index);
107
108 host->ctrl &= ~MVSD_HOST_CTRL_TMOUT_MASK;
109 host->ctrl |= MVSD_HOST_CTRL_TMOUT(tmout_index);
110 mvsd_write(MVSD_HOST_CTRL, host->ctrl);
111 mvsd_write(MVSD_BLK_COUNT, data->blocks);
112 mvsd_write(MVSD_BLK_SIZE, data->blksz);
113
114 if (nodma || (data->blksz | data->sg->offset) & 3) {
115 /*
116 * We cannot do DMA on a buffer which offset or size
117 * is not aligned on a 4-byte boundary.
118 */
119 host->pio_size = data->blocks * data->blksz;
120 host->pio_ptr = sg_virt(data->sg);
121 if (!nodma)
e573d698
TP		 122 dev_dbg(host->dev, "fallback to PIO for data at 0x%p size %d\n",
123 host->pio_ptr, host->pio_size);
236caa7c
MS		 124 return 1;
125 } else {
126 dma_addr_t phys_addr;
127 int dma_dir = (data->flags & MMC_DATA_READ) ?
128 DMA_FROM_DEVICE : DMA_TO_DEVICE;
129 host->sg_frags = dma_map_sg(mmc_dev(host->mmc), data->sg,
130 data->sg_len, dma_dir);
131 phys_addr = sg_dma_address(data->sg);
132 mvsd_write(MVSD_SYS_ADDR_LOW, (u32)phys_addr & 0xffff);
133 mvsd_write(MVSD_SYS_ADDR_HI, (u32)phys_addr >> 16);
134 return 0;
135 }
136}
137
138static void mvsd_request(struct mmc_host *mmc, struct mmc_request *mrq)
139{
140 struct mvsd_host *host = mmc_priv(mmc);
141 void __iomem *iobase = host->base;
142 struct mmc_command *cmd = mrq->cmd;
143 u32 cmdreg = 0, xfer = 0, intr = 0;
144 unsigned long flags;
145
146 BUG_ON(host->mrq != NULL);
147 host->mrq = mrq;
148
149 dev_dbg(host->dev, "cmd %d (hw state 0x%04x)\n",
150 cmd->opcode, mvsd_read(MVSD_HW_STATE));
151
152 cmdreg = MVSD_CMD_INDEX(cmd->opcode);
153
154 if (cmd->flags & MMC_RSP_BUSY)
155 cmdreg |= MVSD_CMD_RSP_48BUSY;
156 else if (cmd->flags & MMC_RSP_136)
157 cmdreg |= MVSD_CMD_RSP_136;
158 else if (cmd->flags & MMC_RSP_PRESENT)
159 cmdreg |= MVSD_CMD_RSP_48;
160 else
161 cmdreg |= MVSD_CMD_RSP_NONE;
162
163 if (cmd->flags & MMC_RSP_CRC)
164 cmdreg |= MVSD_CMD_CHECK_CMDCRC;
165
166 if (cmd->flags & MMC_RSP_OPCODE)
167 cmdreg |= MVSD_CMD_INDX_CHECK;
168
169 if (cmd->flags & MMC_RSP_PRESENT) {
170 cmdreg |= MVSD_UNEXPECTED_RESP;
171 intr |= MVSD_NOR_UNEXP_RSP;
172 }
173
174 if (mrq->data) {
175 struct mmc_data *data = mrq->data;
176 int pio;
177
178 cmdreg |= MVSD_CMD_DATA_PRESENT | MVSD_CMD_CHECK_DATACRC16;
179 xfer |= MVSD_XFER_MODE_HW_WR_DATA_EN;
180 if (data->flags & MMC_DATA_READ)
181 xfer |= MVSD_XFER_MODE_TO_HOST;
182
183 pio = mvsd_setup_data(host, data);
184 if (pio) {
185 xfer |= MVSD_XFER_MODE_PIO;
186 /* PIO section of mvsd_irq has comments on those bits */
187 if (data->flags & MMC_DATA_WRITE)
188 intr |= MVSD_NOR_TX_AVAIL;
189 else if (host->pio_size > 32)
190 intr |= MVSD_NOR_RX_FIFO_8W;
191 else
192 intr |= MVSD_NOR_RX_READY;
193 }
194
195 if (data->stop) {
196 struct mmc_command *stop = data->stop;
197 u32 cmd12reg = 0;
198
199 mvsd_write(MVSD_AUTOCMD12_ARG_LOW, stop->arg & 0xffff);
200 mvsd_write(MVSD_AUTOCMD12_ARG_HI, stop->arg >> 16);
201
202 if (stop->flags & MMC_RSP_BUSY)
203 cmd12reg |= MVSD_AUTOCMD12_BUSY;
204 if (stop->flags & MMC_RSP_OPCODE)
205 cmd12reg |= MVSD_AUTOCMD12_INDX_CHECK;
206 cmd12reg |= MVSD_AUTOCMD12_INDEX(stop->opcode);
207 mvsd_write(MVSD_AUTOCMD12_CMD, cmd12reg);
208
209 xfer |= MVSD_XFER_MODE_AUTO_CMD12;
210 intr |= MVSD_NOR_AUTOCMD12_DONE;
211 } else {
212 intr |= MVSD_NOR_XFER_DONE;
213 }
214 } else {
215 intr |= MVSD_NOR_CMD_DONE;
216 }
217
218 mvsd_write(MVSD_ARG_LOW, cmd->arg & 0xffff);
219 mvsd_write(MVSD_ARG_HI, cmd->arg >> 16);
220
221 spin_lock_irqsave(&host->lock, flags);
222
223 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
224 host->xfer_mode |= xfer;
225 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
226
227 mvsd_write(MVSD_NOR_INTR_STATUS, ~MVSD_NOR_CARD_INT);
228 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
229 mvsd_write(MVSD_CMD, cmdreg);
230
231 host->intr_en &= MVSD_NOR_CARD_INT;
232 host->intr_en |= intr | MVSD_NOR_ERROR;
233 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
234 mvsd_write(MVSD_ERR_INTR_EN, 0xffff);
235
236 mod_timer(&host->timer, jiffies + 5 * HZ);
237
238 spin_unlock_irqrestore(&host->lock, flags);
239}
240
241static u32 mvsd_finish_cmd(struct mvsd_host *host, struct mmc_command *cmd,
242 u32 err_status)
243{
244 void __iomem *iobase = host->base;
245
246 if (cmd->flags & MMC_RSP_136) {
247 unsigned int response[8], i;
248 for (i = 0; i < 8; i++)
249 response[i] = mvsd_read(MVSD_RSP(i));
250 cmd->resp[0] = ((response[0] & 0x03ff) << 22) |
251 ((response[1] & 0xffff) << 6) |
252 ((response[2] & 0xfc00) >> 10);
253 cmd->resp[1] = ((response[2] & 0x03ff) << 22) |
254 ((response[3] & 0xffff) << 6) |
255 ((response[4] & 0xfc00) >> 10);
256 cmd->resp[2] = ((response[4] & 0x03ff) << 22) |
257 ((response[5] & 0xffff) << 6) |
258 ((response[6] & 0xfc00) >> 10);
259 cmd->resp[3] = ((response[6] & 0x03ff) << 22) |
260 ((response[7] & 0x3fff) << 8);
261 } else if (cmd->flags & MMC_RSP_PRESENT) {
262 unsigned int response[3], i;
263 for (i = 0; i < 3; i++)
264 response[i] = mvsd_read(MVSD_RSP(i));
265 cmd->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
266 ((response[1] & 0xffff) << (14 - 8)) |
267 ((response[0] & 0x03ff) << (30 - 8));
268 cmd->resp[1] = ((response[0] & 0xfc00) >> 10);
269 cmd->resp[2] = 0;
270 cmd->resp[3] = 0;
271 }
272
273 if (err_status & MVSD_ERR_CMD_TIMEOUT) {
274 cmd->error = -ETIMEDOUT;
275 } else if (err_status & (MVSD_ERR_CMD_CRC | MVSD_ERR_CMD_ENDBIT |
276 MVSD_ERR_CMD_INDEX | MVSD_ERR_CMD_STARTBIT)) {
277 cmd->error = -EILSEQ;
278 }
279 err_status &= ~(MVSD_ERR_CMD_TIMEOUT | MVSD_ERR_CMD_CRC |
280 MVSD_ERR_CMD_ENDBIT | MVSD_ERR_CMD_INDEX |
281 MVSD_ERR_CMD_STARTBIT);
282
283 return err_status;
284}
285
286static u32 mvsd_finish_data(struct mvsd_host *host, struct mmc_data *data,
287 u32 err_status)
288{
289 void __iomem *iobase = host->base;
290
291 if (host->pio_ptr) {
292 host->pio_ptr = NULL;
293 host->pio_size = 0;
294 } else {
295 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->sg_frags,
296 (data->flags & MMC_DATA_READ) ?
297 DMA_FROM_DEVICE : DMA_TO_DEVICE);
298 }
299
300 if (err_status & MVSD_ERR_DATA_TIMEOUT)
301 data->error = -ETIMEDOUT;
302 else if (err_status & (MVSD_ERR_DATA_CRC | MVSD_ERR_DATA_ENDBIT))
303 data->error = -EILSEQ;
304 else if (err_status & MVSD_ERR_XFER_SIZE)
305 data->error = -EBADE;
306 err_status &= ~(MVSD_ERR_DATA_TIMEOUT | MVSD_ERR_DATA_CRC |
307 MVSD_ERR_DATA_ENDBIT | MVSD_ERR_XFER_SIZE);
308
309 dev_dbg(host->dev, "data done: blocks_left=%d, bytes_left=%d\n",
310 mvsd_read(MVSD_CURR_BLK_LEFT), mvsd_read(MVSD_CURR_BYTE_LEFT));
311 data->bytes_xfered =
312 (data->blocks - mvsd_read(MVSD_CURR_BLK_LEFT)) * data->blksz;
313 /* We can't be sure about the last block when errors are detected */
314 if (data->bytes_xfered && data->error)
315 data->bytes_xfered -= data->blksz;
316
317 /* Handle Auto cmd 12 response */
318 if (data->stop) {
319 unsigned int response[3], i;
320 for (i = 0; i < 3; i++)
321 response[i] = mvsd_read(MVSD_AUTO_RSP(i));
322 data->stop->resp[0] = ((response[2] & 0x003f) << (8 - 8)) |
323 ((response[1] & 0xffff) << (14 - 8)) |
324 ((response[0] & 0x03ff) << (30 - 8));
325 data->stop->resp[1] = ((response[0] & 0xfc00) >> 10);
326 data->stop->resp[2] = 0;
327 data->stop->resp[3] = 0;
328
329 if (err_status & MVSD_ERR_AUTOCMD12) {
330 u32 err_cmd12 = mvsd_read(MVSD_AUTOCMD12_ERR_STATUS);
331 dev_dbg(host->dev, "c12err 0x%04x\n", err_cmd12);
332 if (err_cmd12 & MVSD_AUTOCMD12_ERR_NOTEXE)
333 data->stop->error = -ENOEXEC;
334 else if (err_cmd12 & MVSD_AUTOCMD12_ERR_TIMEOUT)
335 data->stop->error = -ETIMEDOUT;
336 else if (err_cmd12)
337 data->stop->error = -EILSEQ;
338 err_status &= ~MVSD_ERR_AUTOCMD12;
339 }
340 }
341
342 return err_status;
343}
344
345static irqreturn_t mvsd_irq(int irq, void *dev)
346{
347 struct mvsd_host *host = dev;
348 void __iomem *iobase = host->base;
349 u32 intr_status, intr_done_mask;
350 int irq_handled = 0;
351
352 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
353 dev_dbg(host->dev, "intr 0x%04x intr_en 0x%04x hw_state 0x%04x\n",
354 intr_status, mvsd_read(MVSD_NOR_INTR_EN),
355 mvsd_read(MVSD_HW_STATE));
356
357 spin_lock(&host->lock);
358
359 /* PIO handling, if needed. Messy business... */
360 if (host->pio_size &&
361 (intr_status & host->intr_en &
362 (MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W))) {
363 u16 *p = host->pio_ptr;
364 int s = host->pio_size;
365 while (s >= 32 && (intr_status & MVSD_NOR_RX_FIFO_8W)) {
366 readsw(iobase + MVSD_FIFO, p, 16);
367 p += 16;
368 s -= 32;
369 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
370 }
371 /*
372 * Normally we'd use < 32 here, but the RX_FIFO_8W bit
373 * doesn't appear to assert when there is exactly 32 bytes
374 * (8 words) left to fetch in a transfer.
375 */
376 if (s <= 32) {
377 while (s >= 4 && (intr_status & MVSD_NOR_RX_READY)) {
378 put_unaligned(mvsd_read(MVSD_FIFO), p++);
379 put_unaligned(mvsd_read(MVSD_FIFO), p++);
380 s -= 4;
381 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
382 }
383 if (s && s < 4 && (intr_status & MVSD_NOR_RX_READY)) {
384 u16 val[2] = {0, 0};
385 val[0] = mvsd_read(MVSD_FIFO);
386 val[1] = mvsd_read(MVSD_FIFO);
6cdbf734 387 memcpy(p, ((void *)&val) + 4 - s, s);
236caa7c
MS		 388 s = 0;
389 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
390 }
391 if (s == 0) {
392 host->intr_en &=
393 ~(MVSD_NOR_RX_READY | MVSD_NOR_RX_FIFO_8W);
394 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
395 } else if (host->intr_en & MVSD_NOR_RX_FIFO_8W) {
396 host->intr_en &= ~MVSD_NOR_RX_FIFO_8W;
397 host->intr_en |= MVSD_NOR_RX_READY;
398 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
399 }
400 }
401 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
402 s, intr_status, mvsd_read(MVSD_HW_STATE));
403 host->pio_ptr = p;
404 host->pio_size = s;
405 irq_handled = 1;
406 } else if (host->pio_size &&
407 (intr_status & host->intr_en &
408 (MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W))) {
409 u16 *p = host->pio_ptr;
410 int s = host->pio_size;
411 /*
412 * The TX_FIFO_8W bit is unreliable. When set, bursting
413 * 16 halfwords all at once in the FIFO drops data. Actually
414 * TX_AVAIL does go off after only one word is pushed even if
415 * TX_FIFO_8W remains set.
416 */
417 while (s >= 4 && (intr_status & MVSD_NOR_TX_AVAIL)) {
418 mvsd_write(MVSD_FIFO, get_unaligned(p++));
419 mvsd_write(MVSD_FIFO, get_unaligned(p++));
420 s -= 4;
421 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
422 }
423 if (s < 4) {
424 if (s && (intr_status & MVSD_NOR_TX_AVAIL)) {
425 u16 val[2] = {0, 0};
6cdbf734 426 memcpy(((void *)&val) + 4 - s, p, s);
236caa7c
MS		 427 mvsd_write(MVSD_FIFO, val[0]);
428 mvsd_write(MVSD_FIFO, val[1]);
429 s = 0;
430 intr_status = mvsd_read(MVSD_NOR_INTR_STATUS);
431 }
432 if (s == 0) {
433 host->intr_en &=
434 ~(MVSD_NOR_TX_AVAIL | MVSD_NOR_TX_FIFO_8W);
435 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
436 }
437 }
438 dev_dbg(host->dev, "pio %d intr 0x%04x hw_state 0x%04x\n",
439 s, intr_status, mvsd_read(MVSD_HW_STATE));
440 host->pio_ptr = p;
441 host->pio_size = s;
442 irq_handled = 1;
443 }
444
445 mvsd_write(MVSD_NOR_INTR_STATUS, intr_status);
446
447 intr_done_mask = MVSD_NOR_CARD_INT | MVSD_NOR_RX_READY |
448 MVSD_NOR_RX_FIFO_8W | MVSD_NOR_TX_FIFO_8W;
449 if (intr_status & host->intr_en & ~intr_done_mask) {
450 struct mmc_request *mrq = host->mrq;
451 struct mmc_command *cmd = mrq->cmd;
452 u32 err_status = 0;
453
454 del_timer(&host->timer);
455 host->mrq = NULL;
456
457 host->intr_en &= MVSD_NOR_CARD_INT;
458 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
459 mvsd_write(MVSD_ERR_INTR_EN, 0);
460
461 spin_unlock(&host->lock);
462
463 if (intr_status & MVSD_NOR_UNEXP_RSP) {
464 cmd->error = -EPROTO;
465 } else if (intr_status & MVSD_NOR_ERROR) {
466 err_status = mvsd_read(MVSD_ERR_INTR_STATUS);
467 dev_dbg(host->dev, "err 0x%04x\n", err_status);
468 }
469
470 err_status = mvsd_finish_cmd(host, cmd, err_status);
471 if (mrq->data)
472 err_status = mvsd_finish_data(host, mrq->data, err_status);
473 if (err_status) {
e573d698
TP		 474 dev_err(host->dev, "unhandled error status %#04x\n",
475 err_status);
236caa7c
MS		 476 cmd->error = -ENOMSG;
477 }
478
479 mmc_request_done(host->mmc, mrq);
480 irq_handled = 1;
481 } else
482 spin_unlock(&host->lock);
483
484 if (intr_status & MVSD_NOR_CARD_INT) {
485 mmc_signal_sdio_irq(host->mmc);
486 irq_handled = 1;
487 }
488
489 if (irq_handled)
490 return IRQ_HANDLED;
491
e573d698
TP		 492 dev_err(host->dev, "unhandled interrupt status=0x%04x en=0x%04x pio=%d\n",
493 intr_status, host->intr_en, host->pio_size);
236caa7c
MS		 494 return IRQ_NONE;
495}
496
497static void mvsd_timeout_timer(unsigned long data)
498{
499 struct mvsd_host *host = (struct mvsd_host *)data;
500 void __iomem *iobase = host->base;
501 struct mmc_request *mrq;
502 unsigned long flags;
503
504 spin_lock_irqsave(&host->lock, flags);
505 mrq = host->mrq;
506 if (mrq) {
e573d698
TP		 507 dev_err(host->dev, "Timeout waiting for hardware interrupt.\n");
508 dev_err(host->dev, "hw_state=0x%04x, intr_status=0x%04x intr_en=0x%04x\n",
509 mvsd_read(MVSD_HW_STATE),
510 mvsd_read(MVSD_NOR_INTR_STATUS),
511 mvsd_read(MVSD_NOR_INTR_EN));
236caa7c
MS		 512
513 host->mrq = NULL;
514
515 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
516
517 host->xfer_mode &= MVSD_XFER_MODE_INT_CHK_EN;
518 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
519
520 host->intr_en &= MVSD_NOR_CARD_INT;
521 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
522 mvsd_write(MVSD_ERR_INTR_EN, 0);
523 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
524
525 mrq->cmd->error = -ETIMEDOUT;
526 mvsd_finish_cmd(host, mrq->cmd, 0);
527 if (mrq->data) {
528 mrq->data->error = -ETIMEDOUT;
529 mvsd_finish_data(host, mrq->data, 0);
530 }
531 }
532 spin_unlock_irqrestore(&host->lock, flags);
533
534 if (mrq)
535 mmc_request_done(host->mmc, mrq);
536}
537
236caa7c
MS		 538static void mvsd_enable_sdio_irq(struct mmc_host *mmc, int enable)
539{
540 struct mvsd_host *host = mmc_priv(mmc);
541 void __iomem *iobase = host->base;
542 unsigned long flags;
543
544 spin_lock_irqsave(&host->lock, flags);
545 if (enable) {
546 host->xfer_mode |= MVSD_XFER_MODE_INT_CHK_EN;
547 host->intr_en |= MVSD_NOR_CARD_INT;
548 } else {
549 host->xfer_mode &= ~MVSD_XFER_MODE_INT_CHK_EN;
550 host->intr_en &= ~MVSD_NOR_CARD_INT;
551 }
552 mvsd_write(MVSD_XFER_MODE, host->xfer_mode);
553 mvsd_write(MVSD_NOR_INTR_EN, host->intr_en);
554 spin_unlock_irqrestore(&host->lock, flags);
555}
556
236caa7c
MS		 557static void mvsd_power_up(struct mvsd_host *host)
558{
559 void __iomem *iobase = host->base;
560 dev_dbg(host->dev, "power up\n");
561 mvsd_write(MVSD_NOR_INTR_EN, 0);
562 mvsd_write(MVSD_ERR_INTR_EN, 0);
563 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
564 mvsd_write(MVSD_XFER_MODE, 0);
565 mvsd_write(MVSD_NOR_STATUS_EN, 0xffff);
566 mvsd_write(MVSD_ERR_STATUS_EN, 0xffff);
567 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
568 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
569}
570
571static void mvsd_power_down(struct mvsd_host *host)
572{
573 void __iomem *iobase = host->base;
574 dev_dbg(host->dev, "power down\n");
575 mvsd_write(MVSD_NOR_INTR_EN, 0);
576 mvsd_write(MVSD_ERR_INTR_EN, 0);
577 mvsd_write(MVSD_SW_RESET, MVSD_SW_RESET_NOW);
578 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
579 mvsd_write(MVSD_NOR_STATUS_EN, 0);
580 mvsd_write(MVSD_ERR_STATUS_EN, 0);
581 mvsd_write(MVSD_NOR_INTR_STATUS, 0xffff);
582 mvsd_write(MVSD_ERR_INTR_STATUS, 0xffff);
583}
584
585static void mvsd_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
586{
587 struct mvsd_host *host = mmc_priv(mmc);
588 void __iomem *iobase = host->base;
589 u32 ctrl_reg = 0;
590
591 if (ios->power_mode == MMC_POWER_UP)
592 mvsd_power_up(host);
593
594 if (ios->clock == 0) {
595 mvsd_write(MVSD_XFER_MODE, MVSD_XFER_MODE_STOP_CLK);
596 mvsd_write(MVSD_CLK_DIV, MVSD_BASE_DIV_MAX);
597 host->clock = 0;
598 dev_dbg(host->dev, "clock off\n");
599 } else if (ios->clock != host->clock) {
600 u32 m = DIV_ROUND_UP(host->base_clock, ios->clock) - 1;
601 if (m > MVSD_BASE_DIV_MAX)
602 m = MVSD_BASE_DIV_MAX;
603 mvsd_write(MVSD_CLK_DIV, m);
604 host->clock = ios->clock;
605 host->ns_per_clk = 1000000000 / (host->base_clock / (m+1));
606 dev_dbg(host->dev, "clock=%d (%d), div=0x%04x\n",
607 ios->clock, host->base_clock / (m+1), m);
608 }
609
610 /* default transfer mode */
611 ctrl_reg |= MVSD_HOST_CTRL_BIG_ENDIAN;
612 ctrl_reg &= ~MVSD_HOST_CTRL_LSB_FIRST;
613
614 /* default to maximum timeout */
615 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_MASK;
616 ctrl_reg |= MVSD_HOST_CTRL_TMOUT_EN;
617
618 if (ios->bus_mode == MMC_BUSMODE_PUSHPULL)
619 ctrl_reg |= MVSD_HOST_CTRL_PUSH_PULL_EN;
620
621 if (ios->bus_width == MMC_BUS_WIDTH_4)
622 ctrl_reg |= MVSD_HOST_CTRL_DATA_WIDTH_4_BITS;
623
9ca6944c
NP		 624 /*
625 * The HI_SPEED_EN bit is causing trouble with many (but not all)
626 * high speed SD, SDHC and SDIO cards. Not enabling that bit
627 * makes all cards work. So let's just ignore that bit for now
628 * and revisit this issue if problems for not enabling this bit
629 * are ever reported.
630 */
631#if 0
236caa7c
MS		 632 if (ios->timing == MMC_TIMING_MMC_HS ||
633 ios->timing == MMC_TIMING_SD_HS)
634 ctrl_reg |= MVSD_HOST_CTRL_HI_SPEED_EN;
9ca6944c 635#endif
236caa7c
MS		 636
637 host->ctrl = ctrl_reg;
638 mvsd_write(MVSD_HOST_CTRL, ctrl_reg);
639 dev_dbg(host->dev, "ctrl 0x%04x: %s %s %s\n", ctrl_reg,
640 (ctrl_reg & MVSD_HOST_CTRL_PUSH_PULL_EN) ?
641 "push-pull" : "open-drain",
642 (ctrl_reg & MVSD_HOST_CTRL_DATA_WIDTH_4_BITS) ?
643 "4bit-width" : "1bit-width",
644 (ctrl_reg & MVSD_HOST_CTRL_HI_SPEED_EN) ?
645 "high-speed" : "");
646
647 if (ios->power_mode == MMC_POWER_OFF)
648 mvsd_power_down(host);
649}
650
651static const struct mmc_host_ops mvsd_ops = {
652 .request = mvsd_request,
3724482d 653 .get_ro = mmc_gpio_get_ro,
236caa7c
MS		 654 .set_ios = mvsd_set_ios,
655 .enable_sdio_irq = mvsd_enable_sdio_irq,
656};
657
63a9332b
AL		 658static void __init
659mv_conf_mbus_windows(struct mvsd_host *host,
660 const struct mbus_dram_target_info *dram)
236caa7c
MS		 661{
662 void __iomem *iobase = host->base;
663 int i;
664
665 for (i = 0; i < 4; i++) {
666 writel(0, iobase + MVSD_WINDOW_CTRL(i));
667 writel(0, iobase + MVSD_WINDOW_BASE(i));
668 }
669
670 for (i = 0; i < dram->num_cs; i++) {
63a9332b 671 const struct mbus_dram_window *cs = dram->cs + i;
236caa7c
MS		 672 writel(((cs->size - 1) & 0xffff0000) |
673 (cs->mbus_attr << 8) |
674 (dram->mbus_dram_target_id << 4) | 1,
675 iobase + MVSD_WINDOW_CTRL(i));
676 writel(cs->base, iobase + MVSD_WINDOW_BASE(i));
677 }
678}
679
680static int __init mvsd_probe(struct platform_device *pdev)
681{
111936ff 682 struct device_node *np = pdev->dev.of_node;
236caa7c
MS		 683 struct mmc_host *mmc = NULL;
684 struct mvsd_host *host = NULL;
63a9332b 685 const struct mbus_dram_target_info *dram;
236caa7c
MS		 686 struct resource *r;
687 int ret, irq;
111936ff 688 int gpio_card_detect, gpio_write_protect;
6f1989bc 689 struct pinctrl *pinctrl;
236caa7c
MS		 690
691 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
692 irq = platform_get_irq(pdev, 0);
111936ff 693 if (!r || irq < 0)
236caa7c
MS		 694 return -ENXIO;
695
236caa7c
MS		 696 mmc = mmc_alloc_host(sizeof(struct mvsd_host), &pdev->dev);
697 if (!mmc) {
698 ret = -ENOMEM;
699 goto out;
700 }
701
702 host = mmc_priv(mmc);
703 host->mmc = mmc;
704 host->dev = &pdev->dev;
111936ff 705
6f1989bc
TP		 706 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
707 if (IS_ERR(pinctrl))
708 dev_warn(&pdev->dev, "no pins associated\n");
709
111936ff
TP		 710 /*
711 * Some non-DT platforms do not pass a clock, and the clock
712 * frequency is passed through platform_data. On DT platforms,
713 * a clock must always be passed, even if there is no gatable
714 * clock associated to the SDIO interface (it can simply be a
715 * fixed rate clock).
716 */
717 host->clk = devm_clk_get(&pdev->dev, NULL);
718 if (!IS_ERR(host->clk))
719 clk_prepare_enable(host->clk);
720
721 if (np) {
722 if (IS_ERR(host->clk)) {
723 dev_err(&pdev->dev, "DT platforms must have a clock associated\n");
724 ret = -EINVAL;
725 goto out;
726 }
727
728 host->base_clock = clk_get_rate(host->clk) / 2;
729 gpio_card_detect = of_get_named_gpio(np, "cd-gpios", 0);
730 gpio_write_protect = of_get_named_gpio(np, "wp-gpios", 0);
731 } else {
732 const struct mvsdio_platform_data *mvsd_data;
733 mvsd_data = pdev->dev.platform_data;
734 if (!mvsd_data) {
735 ret = -ENXIO;
736 goto out;
737 }
738 host->base_clock = mvsd_data->clock / 2;
5e81441e
TP		 739 gpio_card_detect = mvsd_data->gpio_card_detect ? : -EINVAL;
740 gpio_write_protect = mvsd_data->gpio_write_protect ? : -EINVAL;
111936ff 741 }
236caa7c
MS		 742
743 mmc->ops = &mvsd_ops;
744
745 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
746 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ |
747 MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
748
749 mmc->f_min = DIV_ROUND_UP(host->base_clock, MVSD_BASE_DIV_MAX);
750 mmc->f_max = maxfreq;
751
752 mmc->max_blk_size = 2048;
753 mmc->max_blk_count = 65535;
754
a36274e0 755 mmc->max_segs = 1;
236caa7c
MS		 756 mmc->max_seg_size = mmc->max_blk_size * mmc->max_blk_count;
757 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
758
759 spin_lock_init(&host->lock);
760
f42abc72 761 host->base = devm_request_and_ioremap(&pdev->dev, r);
236caa7c
MS		 762 if (!host->base) {
763 ret = -ENOMEM;
764 goto out;
765 }
766
767 /* (Re-)program MBUS remapping windows if we are asked to. */
63a9332b
AL		 768 dram = mv_mbus_dram_info();
769 if (dram)
770 mv_conf_mbus_windows(host, dram);
236caa7c
MS		 771
772 mvsd_power_down(host);
773
f42abc72 774 ret = devm_request_irq(&pdev->dev, irq, mvsd_irq, 0, DRIVER_NAME, host);
236caa7c 775 if (ret) {
e573d698 776 dev_err(&pdev->dev, "cannot assign irq %d\n", irq);
236caa7c 777 goto out;
f42abc72 778 }
236caa7c 779
111936ff
TP		 780 if (gpio_is_valid(gpio_card_detect)) {
781 ret = mmc_gpio_request_cd(mmc, gpio_card_detect);
07728b77
TP		 782 if (ret)
783 goto out;
784 } else
236caa7c
MS		 785 mmc->caps |= MMC_CAP_NEEDS_POLL;
786
111936ff 787 mmc_gpio_request_ro(mmc, gpio_write_protect);
236caa7c
MS		 788
789 setup_timer(&host->timer, mvsd_timeout_timer, (unsigned long)host);
790 platform_set_drvdata(pdev, mmc);
791 ret = mmc_add_host(mmc);
792 if (ret)
793 goto out;
794
07728b77 795 if (!(mmc->caps & MMC_CAP_NEEDS_POLL))
e573d698
TP		 796 dev_notice(&pdev->dev, "using GPIO %d for card detection\n",
797 gpio_card_detect);
236caa7c 798 else
e573d698 799 dev_notice(&pdev->dev, "lacking card detect (fall back to polling)\n");
236caa7c
MS		 800 return 0;
801
802out:
f42abc72 803 if (mmc) {
07728b77 804 mmc_gpio_free_cd(mmc);
3724482d 805 mmc_gpio_free_ro(mmc);
f42abc72 806 if (!IS_ERR(host->clk))
baffab28 807 clk_disable_unprepare(host->clk);
236caa7c 808 mmc_free_host(mmc);
f42abc72 809 }
236caa7c
MS		 810
811 return ret;
812}
813
814static int __exit mvsd_remove(struct platform_device *pdev)
815{
816 struct mmc_host *mmc = platform_get_drvdata(pdev);
817
f42abc72 818 struct mvsd_host *host = mmc_priv(mmc);
236caa7c 819
07728b77 820 mmc_gpio_free_cd(mmc);
3724482d 821 mmc_gpio_free_ro(mmc);
f42abc72
AL		 822 mmc_remove_host(mmc);
823 del_timer_sync(&host->timer);
824 mvsd_power_down(host);
825
826 if (!IS_ERR(host->clk))
827 clk_disable_unprepare(host->clk);
828 mmc_free_host(mmc);
f4f7561e 829
236caa7c
MS		 830 platform_set_drvdata(pdev, NULL);
831 return 0;
832}
833
834#ifdef CONFIG_PM
2e058a6f 835static int mvsd_suspend(struct platform_device *dev, pm_message_t state)
236caa7c
MS		 836{
837 struct mmc_host *mmc = platform_get_drvdata(dev);
838 int ret = 0;
839
2e058a6f 840 if (mmc)
1a13f8fa 841 ret = mmc_suspend_host(mmc);
236caa7c
MS		 842
843 return ret;
844}
845
2e058a6f 846static int mvsd_resume(struct platform_device *dev)
236caa7c 847{
2e058a6f 848 struct mmc_host *mmc = platform_get_drvdata(dev);
236caa7c
MS		 849 int ret = 0;
850
2e058a6f 851 if (mmc)
236caa7c
MS		 852 ret = mmc_resume_host(mmc);
853
854 return ret;
855}
856#else
857#define mvsd_suspend NULL
858#define mvsd_resume NULL
859#endif
860
111936ff
TP		 861static const struct of_device_id mvsdio_dt_ids[] = {
862 { .compatible = "marvell,orion-sdio" },
863 { /* sentinel */ }
864};
865MODULE_DEVICE_TABLE(of, mvsdio_dt_ids);
866
236caa7c
MS		 867static struct platform_driver mvsd_driver = {
868 .remove = __exit_p(mvsd_remove),
869 .suspend = mvsd_suspend,
870 .resume = mvsd_resume,
871 .driver = {
872 .name = DRIVER_NAME,
111936ff 873 .of_match_table = mvsdio_dt_ids,
236caa7c
MS		 874 },
875};
876
4a2d8ecc 877module_platform_driver_probe(mvsd_driver, mvsd_probe);
236caa7c
MS		 878
879/* maximum card clock frequency (default 50MHz) */
880module_param(maxfreq, int, 0);
881
882/* force PIO transfers all the time */
883module_param(nodma, int, 0);
884
885MODULE_AUTHOR("Maen Suleiman, Nicolas Pitre");
886MODULE_DESCRIPTION("Marvell MMC,SD,SDIO Host Controller driver");
887MODULE_LICENSE("GPL");
703aaced 888MODULE_ALIAS("platform:mvsdio");
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