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[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / mxs-mmc.c
CommitLineData
e4243f13
SG		 1/*
2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
4 *
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/platform_device.h>
27#include <linux/delay.h>
28#include <linux/interrupt.h>
29#include <linux/dma-mapping.h>
30#include <linux/dmaengine.h>
31#include <linux/highmem.h>
32#include <linux/clk.h>
33#include <linux/err.h>
34#include <linux/completion.h>
35#include <linux/mmc/host.h>
36#include <linux/mmc/mmc.h>
37#include <linux/mmc/sdio.h>
38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
88b47679 40#include <linux/module.h>
39468604 41#include <linux/fsl/mxs-dma.h>
e4243f13
SG		 42
43#include <mach/mxs.h>
44#include <mach/common.h>
e4243f13
SG		 45#include <mach/mmc.h>
46
47#define DRIVER_NAME "mxs-mmc"
48
49/* card detect polling timeout */
50#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
51
52#define SSP_VERSION_LATEST 4
53#define ssp_is_old() (host->version < SSP_VERSION_LATEST)
54
55/* SSP registers */
56#define HW_SSP_CTRL0 0x000
57#define BM_SSP_CTRL0_RUN (1 << 29)
58#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
59#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
60#define BM_SSP_CTRL0_READ (1 << 25)
61#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
62#define BP_SSP_CTRL0_BUS_WIDTH (22)
63#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
64#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
65#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
66#define BM_SSP_CTRL0_GET_RESP (1 << 17)
67#define BM_SSP_CTRL0_ENABLE (1 << 16)
68#define BP_SSP_CTRL0_XFER_COUNT (0)
69#define BM_SSP_CTRL0_XFER_COUNT (0xffff)
70#define HW_SSP_CMD0 0x010
71#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
72#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
73#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
74#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
75#define BP_SSP_CMD0_BLOCK_SIZE (16)
76#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
77#define BP_SSP_CMD0_BLOCK_COUNT (8)
78#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
79#define BP_SSP_CMD0_CMD (0)
80#define BM_SSP_CMD0_CMD (0xff)
81#define HW_SSP_CMD1 0x020
82#define HW_SSP_XFER_SIZE 0x030
83#define HW_SSP_BLOCK_SIZE 0x040
84#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
85#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
86#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
87#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
88#define HW_SSP_TIMING (ssp_is_old() ? 0x050 : 0x070)
89#define BP_SSP_TIMING_TIMEOUT (16)
90#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
91#define BP_SSP_TIMING_CLOCK_DIVIDE (8)
92#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
93#define BP_SSP_TIMING_CLOCK_RATE (0)
94#define BM_SSP_TIMING_CLOCK_RATE (0xff)
95#define HW_SSP_CTRL1 (ssp_is_old() ? 0x060 : 0x080)
96#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
97#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
98#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
99#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
100#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
101#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
102#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
103#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
104#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
105#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
106#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
107#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
108#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
109#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
110#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
111#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
112#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
113#define BM_SSP_CTRL1_POLARITY (1 << 9)
114#define BP_SSP_CTRL1_WORD_LENGTH (4)
115#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
116#define BP_SSP_CTRL1_SSP_MODE (0)
117#define BM_SSP_CTRL1_SSP_MODE (0xf)
118#define HW_SSP_SDRESP0 (ssp_is_old() ? 0x080 : 0x0a0)
119#define HW_SSP_SDRESP1 (ssp_is_old() ? 0x090 : 0x0b0)
120#define HW_SSP_SDRESP2 (ssp_is_old() ? 0x0a0 : 0x0c0)
121#define HW_SSP_SDRESP3 (ssp_is_old() ? 0x0b0 : 0x0d0)
122#define HW_SSP_STATUS (ssp_is_old() ? 0x0c0 : 0x100)
123#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
124#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
125#define HW_SSP_VERSION (cpu_is_mx23() ? 0x110 : 0x130)
126#define BP_SSP_VERSION_MAJOR (24)
127
128#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
129
130#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
131 BM_SSP_CTRL1_RESP_ERR_IRQ | \
132 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
133 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
134 BM_SSP_CTRL1_DATA_CRC_IRQ | \
135 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
136 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
137 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
138
139#define SSP_PIO_NUM 3
140
141struct mxs_mmc_host {
142 struct mmc_host *mmc;
143 struct mmc_request *mrq;
144 struct mmc_command *cmd;
145 struct mmc_data *data;
146
147 void __iomem *base;
148 int irq;
149 struct resource *res;
150 struct resource *dma_res;
151 struct clk *clk;
152 unsigned int clk_rate;
153
154 struct dma_chan *dmach;
155 struct mxs_dma_data dma_data;
156 unsigned int dma_dir;
05f5799c 157 enum dma_transfer_direction slave_dirn;
e4243f13
SG		 158 u32 ssp_pio_words[SSP_PIO_NUM];
159
160 unsigned int version;
161 unsigned char bus_width;
162 spinlock_t lock;
163 int sdio_irq_en;
164};
165
166static int mxs_mmc_get_ro(struct mmc_host *mmc)
167{
168 struct mxs_mmc_host *host = mmc_priv(mmc);
169 struct mxs_mmc_platform_data *pdata =
170 mmc_dev(host->mmc)->platform_data;
171
172 if (!pdata)
173 return -EFAULT;
174
175 if (!gpio_is_valid(pdata->wp_gpio))
176 return -EINVAL;
177
178 return gpio_get_value(pdata->wp_gpio);
179}
180
181static int mxs_mmc_get_cd(struct mmc_host *mmc)
182{
183 struct mxs_mmc_host *host = mmc_priv(mmc);
184
185 return !(readl(host->base + HW_SSP_STATUS) &
186 BM_SSP_STATUS_CARD_DETECT);
187}
188
189static void mxs_mmc_reset(struct mxs_mmc_host *host)
190{
191 u32 ctrl0, ctrl1;
192
193 mxs_reset_block(host->base);
194
195 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
196 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
197 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
198 BM_SSP_CTRL1_DMA_ENABLE |
199 BM_SSP_CTRL1_POLARITY |
200 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
201 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
202 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
203 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
204 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
205
206 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
207 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
208 BF_SSP(0, TIMING_CLOCK_RATE),
209 host->base + HW_SSP_TIMING);
210
211 if (host->sdio_irq_en) {
212 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
213 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
214 }
215
216 writel(ctrl0, host->base + HW_SSP_CTRL0);
217 writel(ctrl1, host->base + HW_SSP_CTRL1);
218}
219
220static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
221 struct mmc_command *cmd);
222
223static void mxs_mmc_request_done(struct mxs_mmc_host *host)
224{
225 struct mmc_command *cmd = host->cmd;
226 struct mmc_data *data = host->data;
227 struct mmc_request *mrq = host->mrq;
228
229 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
230 if (mmc_resp_type(cmd) & MMC_RSP_136) {
231 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0);
232 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1);
233 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2);
234 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3);
235 } else {
236 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0);
237 }
238 }
239
240 if (data) {
241 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
242 data->sg_len, host->dma_dir);
243 /*
244 * If there was an error on any block, we mark all
245 * data blocks as being in error.
246 */
247 if (!data->error)
248 data->bytes_xfered = data->blocks * data->blksz;
249 else
250 data->bytes_xfered = 0;
251
252 host->data = NULL;
253 if (mrq->stop) {
254 mxs_mmc_start_cmd(host, mrq->stop);
255 return;
256 }
257 }
258
259 host->mrq = NULL;
260 mmc_request_done(host->mmc, mrq);
261}
262
263static void mxs_mmc_dma_irq_callback(void *param)
264{
265 struct mxs_mmc_host *host = param;
266
267 mxs_mmc_request_done(host);
268}
269
270static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
271{
272 struct mxs_mmc_host *host = dev_id;
273 struct mmc_command *cmd = host->cmd;
274 struct mmc_data *data = host->data;
275 u32 stat;
276
277 spin_lock(&host->lock);
278
279 stat = readl(host->base + HW_SSP_CTRL1);
280 writel(stat & MXS_MMC_IRQ_BITS,
281 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
282
283 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
284 mmc_signal_sdio_irq(host->mmc);
285
286 spin_unlock(&host->lock);
287
288 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
289 cmd->error = -ETIMEDOUT;
290 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
291 cmd->error = -EIO;
292
293 if (data) {
294 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
295 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
296 data->error = -ETIMEDOUT;
297 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
298 data->error = -EILSEQ;
299 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
300 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
301 data->error = -EIO;
302 }
303
304 return IRQ_HANDLED;
305}
306
307static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
921de864 308 struct mxs_mmc_host *host, unsigned long flags)
e4243f13
SG		 309{
310 struct dma_async_tx_descriptor *desc;
311 struct mmc_data *data = host->data;
312 struct scatterlist * sgl;
313 unsigned int sg_len;
314
315 if (data) {
316 /* data */
317 dma_map_sg(mmc_dev(host->mmc), data->sg,
318 data->sg_len, host->dma_dir);
319 sgl = data->sg;
320 sg_len = data->sg_len;
321 } else {
322 /* pio */
323 sgl = (struct scatterlist *) host->ssp_pio_words;
324 sg_len = SSP_PIO_NUM;
325 }
326
16052827 327 desc = dmaengine_prep_slave_sg(host->dmach,
921de864 328 sgl, sg_len, host->slave_dirn, flags);
e4243f13
SG		 329 if (desc) {
330 desc->callback = mxs_mmc_dma_irq_callback;
331 desc->callback_param = host;
332 } else {
333 if (data)
334 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
335 data->sg_len, host->dma_dir);
336 }
337
338 return desc;
339}
340
341static void mxs_mmc_bc(struct mxs_mmc_host *host)
342{
343 struct mmc_command *cmd = host->cmd;
344 struct dma_async_tx_descriptor *desc;
345 u32 ctrl0, cmd0, cmd1;
346
347 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
348 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
349 cmd1 = cmd->arg;
350
351 if (host->sdio_irq_en) {
352 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
353 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
354 }
355
356 host->ssp_pio_words[0] = ctrl0;
357 host->ssp_pio_words[1] = cmd0;
358 host->ssp_pio_words[2] = cmd1;
359 host->dma_dir = DMA_NONE;
a4e3e86d 360 host->slave_dirn = DMA_TRANS_NONE;
921de864 361 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
e4243f13
SG		 362 if (!desc)
363 goto out;
364
365 dmaengine_submit(desc);
d04525ed 366 dma_async_issue_pending(host->dmach);
e4243f13
SG		 367 return;
368
369out:
370 dev_warn(mmc_dev(host->mmc),
371 "%s: failed to prep dma\n", __func__);
372}
373
374static void mxs_mmc_ac(struct mxs_mmc_host *host)
375{
376 struct mmc_command *cmd = host->cmd;
377 struct dma_async_tx_descriptor *desc;
378 u32 ignore_crc, get_resp, long_resp;
379 u32 ctrl0, cmd0, cmd1;
380
381 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
382 0 : BM_SSP_CTRL0_IGNORE_CRC;
383 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
384 BM_SSP_CTRL0_GET_RESP : 0;
385 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
386 BM_SSP_CTRL0_LONG_RESP : 0;
387
388 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
389 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
390 cmd1 = cmd->arg;
391
392 if (host->sdio_irq_en) {
393 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
394 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
395 }
396
397 host->ssp_pio_words[0] = ctrl0;
398 host->ssp_pio_words[1] = cmd0;
399 host->ssp_pio_words[2] = cmd1;
400 host->dma_dir = DMA_NONE;
a4e3e86d 401 host->slave_dirn = DMA_TRANS_NONE;
921de864 402 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
e4243f13
SG		 403 if (!desc)
404 goto out;
405
406 dmaengine_submit(desc);
d04525ed 407 dma_async_issue_pending(host->dmach);
e4243f13
SG		 408 return;
409
410out:
411 dev_warn(mmc_dev(host->mmc),
412 "%s: failed to prep dma\n", __func__);
413}
414
415static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
416{
417 const unsigned int ssp_timeout_mul = 4096;
418 /*
419 * Calculate ticks in ms since ns are large numbers
420 * and might overflow
421 */
422 const unsigned int clock_per_ms = clock_rate / 1000;
423 const unsigned int ms = ns / 1000;
424 const unsigned int ticks = ms * clock_per_ms;
425 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
426
427 WARN_ON(ssp_ticks == 0);
428 return ssp_ticks;
429}
430
431static void mxs_mmc_adtc(struct mxs_mmc_host *host)
432{
433 struct mmc_command *cmd = host->cmd;
434 struct mmc_data *data = cmd->data;
435 struct dma_async_tx_descriptor *desc;
436 struct scatterlist *sgl = data->sg, *sg;
437 unsigned int sg_len = data->sg_len;
438 int i;
439
440 unsigned short dma_data_dir, timeout;
05f5799c 441 enum dma_transfer_direction slave_dirn;
e4243f13
SG		 442 unsigned int data_size = 0, log2_blksz;
443 unsigned int blocks = data->blocks;
444
445 u32 ignore_crc, get_resp, long_resp, read;
446 u32 ctrl0, cmd0, cmd1, val;
447
448 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
449 0 : BM_SSP_CTRL0_IGNORE_CRC;
450 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
451 BM_SSP_CTRL0_GET_RESP : 0;
452 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
453 BM_SSP_CTRL0_LONG_RESP : 0;
454
455 if (data->flags & MMC_DATA_WRITE) {
456 dma_data_dir = DMA_TO_DEVICE;
05f5799c 457 slave_dirn = DMA_MEM_TO_DEV;
e4243f13
SG		 458 read = 0;
459 } else {
460 dma_data_dir = DMA_FROM_DEVICE;
05f5799c 461 slave_dirn = DMA_DEV_TO_MEM;
e4243f13
SG		 462 read = BM_SSP_CTRL0_READ;
463 }
464
465 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
466 ignore_crc | get_resp | long_resp |
467 BM_SSP_CTRL0_DATA_XFER | read |
468 BM_SSP_CTRL0_WAIT_FOR_IRQ |
469 BM_SSP_CTRL0_ENABLE;
470
471 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
472
473 /* get logarithm to base 2 of block size for setting register */
474 log2_blksz = ilog2(data->blksz);
475
476 /*
477 * take special care of the case that data size from data->sg
478 * is not equal to blocks x blksz
479 */
480 for_each_sg(sgl, sg, sg_len, i)
481 data_size += sg->length;
482
483 if (data_size != data->blocks * data->blksz)
484 blocks = 1;
485
486 /* xfer count, block size and count need to be set differently */
487 if (ssp_is_old()) {
488 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
489 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
490 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
491 } else {
492 writel(data_size, host->base + HW_SSP_XFER_SIZE);
493 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
494 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
495 host->base + HW_SSP_BLOCK_SIZE);
496 }
497
498 if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
499 (cmd->opcode == SD_IO_RW_EXTENDED))
500 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
501
502 cmd1 = cmd->arg;
503
504 if (host->sdio_irq_en) {
505 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
506 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
507 }
508
509 /* set the timeout count */
510 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
511 val = readl(host->base + HW_SSP_TIMING);
512 val &= ~(BM_SSP_TIMING_TIMEOUT);
513 val |= BF_SSP(timeout, TIMING_TIMEOUT);
514 writel(val, host->base + HW_SSP_TIMING);
515
516 /* pio */
517 host->ssp_pio_words[0] = ctrl0;
518 host->ssp_pio_words[1] = cmd0;
519 host->ssp_pio_words[2] = cmd1;
520 host->dma_dir = DMA_NONE;
a4e3e86d 521 host->slave_dirn = DMA_TRANS_NONE;
e4243f13
SG		 522 desc = mxs_mmc_prep_dma(host, 0);
523 if (!desc)
524 goto out;
525
526 /* append data sg */
527 WARN_ON(host->data != NULL);
528 host->data = data;
529 host->dma_dir = dma_data_dir;
05f5799c 530 host->slave_dirn = slave_dirn;
921de864 531 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
e4243f13
SG		 532 if (!desc)
533 goto out;
534
535 dmaengine_submit(desc);
d04525ed 536 dma_async_issue_pending(host->dmach);
e4243f13
SG		 537 return;
538out:
539 dev_warn(mmc_dev(host->mmc),
540 "%s: failed to prep dma\n", __func__);
541}
542
543static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
544 struct mmc_command *cmd)
545{
546 host->cmd = cmd;
547
548 switch (mmc_cmd_type(cmd)) {
549 case MMC_CMD_BC:
550 mxs_mmc_bc(host);
551 break;
552 case MMC_CMD_BCR:
553 mxs_mmc_ac(host);
554 break;
555 case MMC_CMD_AC:
556 mxs_mmc_ac(host);
557 break;
558 case MMC_CMD_ADTC:
559 mxs_mmc_adtc(host);
560 break;
561 default:
562 dev_warn(mmc_dev(host->mmc),
563 "%s: unknown MMC command\n", __func__);
564 break;
565 }
566}
567
568static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
569{
570 struct mxs_mmc_host *host = mmc_priv(mmc);
571
572 WARN_ON(host->mrq != NULL);
573 host->mrq = mrq;
574 mxs_mmc_start_cmd(host, mrq->cmd);
575}
576
577static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
578{
d982dcdc
KB		 579 unsigned int ssp_clk, ssp_sck;
580 u32 clock_divide, clock_rate;
e4243f13
SG		 581 u32 val;
582
d982dcdc 583 ssp_clk = clk_get_rate(host->clk);
e4243f13 584
d982dcdc
KB		 585 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
586 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
587 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
588 if (clock_rate <= 255)
e4243f13
SG		 589 break;
590 }
591
d982dcdc 592 if (clock_divide > 254) {
e4243f13
SG		 593 dev_err(mmc_dev(host->mmc),
594 "%s: cannot set clock to %d\n", __func__, rate);
595 return;
596 }
597
d982dcdc 598 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
e4243f13
SG		 599
600 val = readl(host->base + HW_SSP_TIMING);
601 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
d982dcdc
KB		 602 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
603 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
e4243f13
SG		 604 writel(val, host->base + HW_SSP_TIMING);
605
d982dcdc 606 host->clk_rate = ssp_sck;
e4243f13
SG		 607
608 dev_dbg(mmc_dev(host->mmc),
d982dcdc
KB		 609 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
610 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
e4243f13
SG		 611}
612
613static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
614{
615 struct mxs_mmc_host *host = mmc_priv(mmc);
616
617 if (ios->bus_width == MMC_BUS_WIDTH_8)
618 host->bus_width = 2;
619 else if (ios->bus_width == MMC_BUS_WIDTH_4)
620 host->bus_width = 1;
621 else
622 host->bus_width = 0;
623
624 if (ios->clock)
625 mxs_mmc_set_clk_rate(host, ios->clock);
626}
627
628static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
629{
630 struct mxs_mmc_host *host = mmc_priv(mmc);
631 unsigned long flags;
632
633 spin_lock_irqsave(&host->lock, flags);
634
635 host->sdio_irq_en = enable;
636
637 if (enable) {
638 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
639 host->base + HW_SSP_CTRL0 + MXS_SET_ADDR);
640 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
641 host->base + HW_SSP_CTRL1 + MXS_SET_ADDR);
642
643 if (readl(host->base + HW_SSP_STATUS) & BM_SSP_STATUS_SDIO_IRQ)
644 mmc_signal_sdio_irq(host->mmc);
645
646 } else {
647 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
648 host->base + HW_SSP_CTRL0 + MXS_CLR_ADDR);
649 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
650 host->base + HW_SSP_CTRL1 + MXS_CLR_ADDR);
651 }
652
653 spin_unlock_irqrestore(&host->lock, flags);
654}
655
656static const struct mmc_host_ops mxs_mmc_ops = {
657 .request = mxs_mmc_request,
658 .get_ro = mxs_mmc_get_ro,
659 .get_cd = mxs_mmc_get_cd,
660 .set_ios = mxs_mmc_set_ios,
661 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
662};
663
664static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
665{
666 struct mxs_mmc_host *host = param;
667
668 if (!mxs_dma_is_apbh(chan))
669 return false;
670
671 if (chan->chan_id != host->dma_res->start)
672 return false;
673
674 chan->private = &host->dma_data;
675
676 return true;
677}
678
679static int mxs_mmc_probe(struct platform_device *pdev)
680{
681 struct mxs_mmc_host *host;
682 struct mmc_host *mmc;
683 struct resource *iores, *dmares, *r;
684 struct mxs_mmc_platform_data *pdata;
685 int ret = 0, irq_err, irq_dma;
686 dma_cap_mask_t mask;
687
688 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
689 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
690 irq_err = platform_get_irq(pdev, 0);
691 irq_dma = platform_get_irq(pdev, 1);
692 if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
693 return -EINVAL;
694
695 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
696 if (!r)
697 return -EBUSY;
698
699 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
700 if (!mmc) {
701 ret = -ENOMEM;
702 goto out_release_mem;
703 }
704
705 host = mmc_priv(mmc);
706 host->base = ioremap(r->start, resource_size(r));
707 if (!host->base) {
708 ret = -ENOMEM;
709 goto out_mmc_free;
710 }
711
712 /* only major verion does matter */
713 host->version = readl(host->base + HW_SSP_VERSION) >>
714 BP_SSP_VERSION_MAJOR;
715
716 host->mmc = mmc;
717 host->res = r;
718 host->dma_res = dmares;
719 host->irq = irq_err;
720 host->sdio_irq_en = 0;
721
722 host->clk = clk_get(&pdev->dev, NULL);
723 if (IS_ERR(host->clk)) {
724 ret = PTR_ERR(host->clk);
725 goto out_iounmap;
726 }
efdfc52c 727 clk_prepare_enable(host->clk);
e4243f13
SG		 728
729 mxs_mmc_reset(host);
730
731 dma_cap_zero(mask);
732 dma_cap_set(DMA_SLAVE, mask);
733 host->dma_data.chan_irq = irq_dma;
734 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
735 if (!host->dmach) {
736 dev_err(mmc_dev(host->mmc),
737 "%s: failed to request dma\n", __func__);
738 goto out_clk_put;
739 }
740
741 /* set mmc core parameters */
742 mmc->ops = &mxs_mmc_ops;
743 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
744 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
745
746 pdata = mmc_dev(host->mmc)->platform_data;
747 if (pdata) {
748 if (pdata->flags & SLOTF_8_BIT_CAPABLE)
749 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
750 if (pdata->flags & SLOTF_4_BIT_CAPABLE)
751 mmc->caps |= MMC_CAP_4_BIT_DATA;
752 }
753
754 mmc->f_min = 400000;
755 mmc->f_max = 288000000;
756 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
757
758 mmc->max_segs = 52;
759 mmc->max_blk_size = 1 << 0xf;
760 mmc->max_blk_count = (ssp_is_old()) ? 0xff : 0xffffff;
761 mmc->max_req_size = (ssp_is_old()) ? 0xffff : 0xffffffff;
762 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
763
764 platform_set_drvdata(pdev, mmc);
765
766 ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host);
767 if (ret)
768 goto out_free_dma;
769
770 spin_lock_init(&host->lock);
771
772 ret = mmc_add_host(mmc);
773 if (ret)
774 goto out_free_irq;
775
776 dev_info(mmc_dev(host->mmc), "initialized\n");
777
778 return 0;
779
780out_free_irq:
781 free_irq(host->irq, host);
782out_free_dma:
783 if (host->dmach)
784 dma_release_channel(host->dmach);
785out_clk_put:
efdfc52c 786 clk_disable_unprepare(host->clk);
e4243f13
SG		 787 clk_put(host->clk);
788out_iounmap:
789 iounmap(host->base);
790out_mmc_free:
791 mmc_free_host(mmc);
792out_release_mem:
793 release_mem_region(iores->start, resource_size(iores));
794 return ret;
795}
796
797static int mxs_mmc_remove(struct platform_device *pdev)
798{
799 struct mmc_host *mmc = platform_get_drvdata(pdev);
800 struct mxs_mmc_host *host = mmc_priv(mmc);
801 struct resource *res = host->res;
802
803 mmc_remove_host(mmc);
804
805 free_irq(host->irq, host);
806
807 platform_set_drvdata(pdev, NULL);
808
809 if (host->dmach)
810 dma_release_channel(host->dmach);
811
efdfc52c 812 clk_disable_unprepare(host->clk);
e4243f13
SG		 813 clk_put(host->clk);
814
815 iounmap(host->base);
816
817 mmc_free_host(mmc);
818
819 release_mem_region(res->start, resource_size(res));
820
821 return 0;
822}
823
824#ifdef CONFIG_PM
825static int mxs_mmc_suspend(struct device *dev)
826{
827 struct mmc_host *mmc = dev_get_drvdata(dev);
828 struct mxs_mmc_host *host = mmc_priv(mmc);
829 int ret = 0;
830
831 ret = mmc_suspend_host(mmc);
832
efdfc52c 833 clk_disable_unprepare(host->clk);
e4243f13
SG		 834
835 return ret;
836}
837
838static int mxs_mmc_resume(struct device *dev)
839{
840 struct mmc_host *mmc = dev_get_drvdata(dev);
841 struct mxs_mmc_host *host = mmc_priv(mmc);
842 int ret = 0;
843
efdfc52c 844 clk_prepare_enable(host->clk);
e4243f13
SG		 845
846 ret = mmc_resume_host(mmc);
847
848 return ret;
849}
850
851static const struct dev_pm_ops mxs_mmc_pm_ops = {
852 .suspend = mxs_mmc_suspend,
853 .resume = mxs_mmc_resume,
854};
855#endif
856
857static struct platform_driver mxs_mmc_driver = {
858 .probe = mxs_mmc_probe,
859 .remove = mxs_mmc_remove,
860 .driver = {
861 .name = DRIVER_NAME,
862 .owner = THIS_MODULE,
863#ifdef CONFIG_PM
864 .pm = &mxs_mmc_pm_ops,
865#endif
866 },
867};
868
d1f81a64 869module_platform_driver(mxs_mmc_driver);
e4243f13
SG		 870
871MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
872MODULE_AUTHOR("Freescale Semiconductor");
873MODULE_LICENSE("GPL");
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