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mmc: mxs-mmc: get rid of the use of cpu_is_xxx
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / mxs-mmc.c
CommitLineData
e4243f13
SG		 1/*
2 * Portions copyright (C) 2003 Russell King, PXA MMCI Driver
3 * Portions copyright (C) 2004-2005 Pierre Ossman, W83L51xD SD/MMC driver
4 *
5 * Copyright 2008 Embedded Alley Solutions, Inc.
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 */
22
23#include <linux/kernel.h>
24#include <linux/init.h>
25#include <linux/ioport.h>
26#include <linux/platform_device.h>
27#include <linux/delay.h>
28#include <linux/interrupt.h>
29#include <linux/dma-mapping.h>
30#include <linux/dmaengine.h>
31#include <linux/highmem.h>
32#include <linux/clk.h>
33#include <linux/err.h>
34#include <linux/completion.h>
35#include <linux/mmc/host.h>
36#include <linux/mmc/mmc.h>
37#include <linux/mmc/sdio.h>
38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
88b47679 40#include <linux/module.h>
39468604 41#include <linux/fsl/mxs-dma.h>
9c92cf24 42#include <linux/pinctrl/consumer.h>
70e60206 43#include <linux/stmp_device.h>
e4243f13 44
e4243f13
SG		 45#include <mach/mmc.h>
46
47#define DRIVER_NAME "mxs-mmc"
48
49/* card detect polling timeout */
50#define MXS_MMC_DETECT_TIMEOUT (HZ/2)
51
ef9b4d39 52#define ssp_is_old(host) ((host)->devid == IMX23_MMC)
e4243f13
SG		 53
54/* SSP registers */
55#define HW_SSP_CTRL0 0x000
56#define BM_SSP_CTRL0_RUN (1 << 29)
57#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
58#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
59#define BM_SSP_CTRL0_READ (1 << 25)
60#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
61#define BP_SSP_CTRL0_BUS_WIDTH (22)
62#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
63#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
64#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
65#define BM_SSP_CTRL0_GET_RESP (1 << 17)
66#define BM_SSP_CTRL0_ENABLE (1 << 16)
67#define BP_SSP_CTRL0_XFER_COUNT (0)
68#define BM_SSP_CTRL0_XFER_COUNT (0xffff)
69#define HW_SSP_CMD0 0x010
70#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
71#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
72#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
73#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
74#define BP_SSP_CMD0_BLOCK_SIZE (16)
75#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
76#define BP_SSP_CMD0_BLOCK_COUNT (8)
77#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
78#define BP_SSP_CMD0_CMD (0)
79#define BM_SSP_CMD0_CMD (0xff)
80#define HW_SSP_CMD1 0x020
81#define HW_SSP_XFER_SIZE 0x030
82#define HW_SSP_BLOCK_SIZE 0x040
83#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT (4)
84#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
85#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE (0)
86#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE (0xf)
e0bf141d 87#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
e4243f13
SG		 88#define BP_SSP_TIMING_TIMEOUT (16)
89#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
90#define BP_SSP_TIMING_CLOCK_DIVIDE (8)
91#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
92#define BP_SSP_TIMING_CLOCK_RATE (0)
93#define BM_SSP_TIMING_CLOCK_RATE (0xff)
e0bf141d 94#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
e4243f13
SG		 95#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
96#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
97#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
98#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
99#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
100#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
101#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
102#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
103#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
104#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
105#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
106#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
107#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
108#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
109#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
110#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
111#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
112#define BM_SSP_CTRL1_POLARITY (1 << 9)
113#define BP_SSP_CTRL1_WORD_LENGTH (4)
114#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
115#define BP_SSP_CTRL1_SSP_MODE (0)
116#define BM_SSP_CTRL1_SSP_MODE (0xf)
e0bf141d
SG		 117#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
118#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
119#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
120#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
121#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
e4243f13
SG		 122#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
123#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
e4243f13
SG		 124
125#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
126
127#define MXS_MMC_IRQ_BITS (BM_SSP_CTRL1_SDIO_IRQ | \
128 BM_SSP_CTRL1_RESP_ERR_IRQ | \
129 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ | \
130 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ | \
131 BM_SSP_CTRL1_DATA_CRC_IRQ | \
132 BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ | \
133 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ | \
134 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ)
135
136#define SSP_PIO_NUM 3
137
ef9b4d39
SG		 138enum mxs_mmc_id {
139 IMX23_MMC,
140 IMX28_MMC,
141};
142
e4243f13
SG		 143struct mxs_mmc_host {
144 struct mmc_host *mmc;
145 struct mmc_request *mrq;
146 struct mmc_command *cmd;
147 struct mmc_data *data;
148
149 void __iomem *base;
150 int irq;
151 struct resource *res;
152 struct resource *dma_res;
153 struct clk *clk;
154 unsigned int clk_rate;
155
156 struct dma_chan *dmach;
157 struct mxs_dma_data dma_data;
158 unsigned int dma_dir;
05f5799c 159 enum dma_transfer_direction slave_dirn;
e4243f13
SG		 160 u32 ssp_pio_words[SSP_PIO_NUM];
161
ef9b4d39 162 enum mxs_mmc_id devid;
e4243f13
SG		 163 unsigned char bus_width;
164 spinlock_t lock;
165 int sdio_irq_en;
166};
167
168static int mxs_mmc_get_ro(struct mmc_host *mmc)
169{
170 struct mxs_mmc_host *host = mmc_priv(mmc);
171 struct mxs_mmc_platform_data *pdata =
172 mmc_dev(host->mmc)->platform_data;
173
174 if (!pdata)
175 return -EFAULT;
176
177 if (!gpio_is_valid(pdata->wp_gpio))
178 return -EINVAL;
179
180 return gpio_get_value(pdata->wp_gpio);
181}
182
183static int mxs_mmc_get_cd(struct mmc_host *mmc)
184{
185 struct mxs_mmc_host *host = mmc_priv(mmc);
186
e0bf141d 187 return !(readl(host->base + HW_SSP_STATUS(host)) &
e4243f13
SG		 188 BM_SSP_STATUS_CARD_DETECT);
189}
190
191static void mxs_mmc_reset(struct mxs_mmc_host *host)
192{
193 u32 ctrl0, ctrl1;
194
70e60206 195 stmp_reset_block(host->base);
e4243f13
SG		 196
197 ctrl0 = BM_SSP_CTRL0_IGNORE_CRC;
198 ctrl1 = BF_SSP(0x3, CTRL1_SSP_MODE) |
199 BF_SSP(0x7, CTRL1_WORD_LENGTH) |
200 BM_SSP_CTRL1_DMA_ENABLE |
201 BM_SSP_CTRL1_POLARITY |
202 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN |
203 BM_SSP_CTRL1_DATA_CRC_IRQ_EN |
204 BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN |
205 BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN |
206 BM_SSP_CTRL1_RESP_ERR_IRQ_EN;
207
208 writel(BF_SSP(0xffff, TIMING_TIMEOUT) |
209 BF_SSP(2, TIMING_CLOCK_DIVIDE) |
210 BF_SSP(0, TIMING_CLOCK_RATE),
e0bf141d 211 host->base + HW_SSP_TIMING(host));
e4243f13
SG		 212
213 if (host->sdio_irq_en) {
214 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
215 ctrl1 |= BM_SSP_CTRL1_SDIO_IRQ_EN;
216 }
217
218 writel(ctrl0, host->base + HW_SSP_CTRL0);
e0bf141d 219 writel(ctrl1, host->base + HW_SSP_CTRL1(host));
e4243f13
SG		 220}
221
222static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
223 struct mmc_command *cmd);
224
225static void mxs_mmc_request_done(struct mxs_mmc_host *host)
226{
227 struct mmc_command *cmd = host->cmd;
228 struct mmc_data *data = host->data;
229 struct mmc_request *mrq = host->mrq;
230
231 if (mmc_resp_type(cmd) & MMC_RSP_PRESENT) {
232 if (mmc_resp_type(cmd) & MMC_RSP_136) {
e0bf141d
SG		 233 cmd->resp[3] = readl(host->base + HW_SSP_SDRESP0(host));
234 cmd->resp[2] = readl(host->base + HW_SSP_SDRESP1(host));
235 cmd->resp[1] = readl(host->base + HW_SSP_SDRESP2(host));
236 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP3(host));
e4243f13 237 } else {
e0bf141d 238 cmd->resp[0] = readl(host->base + HW_SSP_SDRESP0(host));
e4243f13
SG		 239 }
240 }
241
242 if (data) {
243 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
244 data->sg_len, host->dma_dir);
245 /*
246 * If there was an error on any block, we mark all
247 * data blocks as being in error.
248 */
249 if (!data->error)
250 data->bytes_xfered = data->blocks * data->blksz;
251 else
252 data->bytes_xfered = 0;
253
254 host->data = NULL;
255 if (mrq->stop) {
256 mxs_mmc_start_cmd(host, mrq->stop);
257 return;
258 }
259 }
260
261 host->mrq = NULL;
262 mmc_request_done(host->mmc, mrq);
263}
264
265static void mxs_mmc_dma_irq_callback(void *param)
266{
267 struct mxs_mmc_host *host = param;
268
269 mxs_mmc_request_done(host);
270}
271
272static irqreturn_t mxs_mmc_irq_handler(int irq, void *dev_id)
273{
274 struct mxs_mmc_host *host = dev_id;
275 struct mmc_command *cmd = host->cmd;
276 struct mmc_data *data = host->data;
277 u32 stat;
278
279 spin_lock(&host->lock);
280
e0bf141d 281 stat = readl(host->base + HW_SSP_CTRL1(host));
e4243f13 282 writel(stat & MXS_MMC_IRQ_BITS,
e0bf141d 283 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
e4243f13
SG		 284
285 if ((stat & BM_SSP_CTRL1_SDIO_IRQ) && (stat & BM_SSP_CTRL1_SDIO_IRQ_EN))
286 mmc_signal_sdio_irq(host->mmc);
287
288 spin_unlock(&host->lock);
289
290 if (stat & BM_SSP_CTRL1_RESP_TIMEOUT_IRQ)
291 cmd->error = -ETIMEDOUT;
292 else if (stat & BM_SSP_CTRL1_RESP_ERR_IRQ)
293 cmd->error = -EIO;
294
295 if (data) {
296 if (stat & (BM_SSP_CTRL1_DATA_TIMEOUT_IRQ |
297 BM_SSP_CTRL1_RECV_TIMEOUT_IRQ))
298 data->error = -ETIMEDOUT;
299 else if (stat & BM_SSP_CTRL1_DATA_CRC_IRQ)
300 data->error = -EILSEQ;
301 else if (stat & (BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ |
302 BM_SSP_CTRL1_FIFO_OVERRUN_IRQ))
303 data->error = -EIO;
304 }
305
306 return IRQ_HANDLED;
307}
308
309static struct dma_async_tx_descriptor *mxs_mmc_prep_dma(
921de864 310 struct mxs_mmc_host *host, unsigned long flags)
e4243f13
SG		 311{
312 struct dma_async_tx_descriptor *desc;
313 struct mmc_data *data = host->data;
314 struct scatterlist * sgl;
315 unsigned int sg_len;
316
317 if (data) {
318 /* data */
319 dma_map_sg(mmc_dev(host->mmc), data->sg,
320 data->sg_len, host->dma_dir);
321 sgl = data->sg;
322 sg_len = data->sg_len;
323 } else {
324 /* pio */
325 sgl = (struct scatterlist *) host->ssp_pio_words;
326 sg_len = SSP_PIO_NUM;
327 }
328
16052827 329 desc = dmaengine_prep_slave_sg(host->dmach,
921de864 330 sgl, sg_len, host->slave_dirn, flags);
e4243f13
SG		 331 if (desc) {
332 desc->callback = mxs_mmc_dma_irq_callback;
333 desc->callback_param = host;
334 } else {
335 if (data)
336 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
337 data->sg_len, host->dma_dir);
338 }
339
340 return desc;
341}
342
343static void mxs_mmc_bc(struct mxs_mmc_host *host)
344{
345 struct mmc_command *cmd = host->cmd;
346 struct dma_async_tx_descriptor *desc;
347 u32 ctrl0, cmd0, cmd1;
348
349 ctrl0 = BM_SSP_CTRL0_ENABLE | BM_SSP_CTRL0_IGNORE_CRC;
350 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD) | BM_SSP_CMD0_APPEND_8CYC;
351 cmd1 = cmd->arg;
352
353 if (host->sdio_irq_en) {
354 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
355 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
356 }
357
358 host->ssp_pio_words[0] = ctrl0;
359 host->ssp_pio_words[1] = cmd0;
360 host->ssp_pio_words[2] = cmd1;
361 host->dma_dir = DMA_NONE;
a4e3e86d 362 host->slave_dirn = DMA_TRANS_NONE;
921de864 363 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
e4243f13
SG		 364 if (!desc)
365 goto out;
366
367 dmaengine_submit(desc);
d04525ed 368 dma_async_issue_pending(host->dmach);
e4243f13
SG		 369 return;
370
371out:
372 dev_warn(mmc_dev(host->mmc),
373 "%s: failed to prep dma\n", __func__);
374}
375
376static void mxs_mmc_ac(struct mxs_mmc_host *host)
377{
378 struct mmc_command *cmd = host->cmd;
379 struct dma_async_tx_descriptor *desc;
380 u32 ignore_crc, get_resp, long_resp;
381 u32 ctrl0, cmd0, cmd1;
382
383 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
384 0 : BM_SSP_CTRL0_IGNORE_CRC;
385 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
386 BM_SSP_CTRL0_GET_RESP : 0;
387 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
388 BM_SSP_CTRL0_LONG_RESP : 0;
389
390 ctrl0 = BM_SSP_CTRL0_ENABLE | ignore_crc | get_resp | long_resp;
391 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
392 cmd1 = cmd->arg;
393
394 if (host->sdio_irq_en) {
395 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
396 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
397 }
398
399 host->ssp_pio_words[0] = ctrl0;
400 host->ssp_pio_words[1] = cmd0;
401 host->ssp_pio_words[2] = cmd1;
402 host->dma_dir = DMA_NONE;
a4e3e86d 403 host->slave_dirn = DMA_TRANS_NONE;
921de864 404 desc = mxs_mmc_prep_dma(host, DMA_CTRL_ACK);
e4243f13
SG		 405 if (!desc)
406 goto out;
407
408 dmaengine_submit(desc);
d04525ed 409 dma_async_issue_pending(host->dmach);
e4243f13
SG		 410 return;
411
412out:
413 dev_warn(mmc_dev(host->mmc),
414 "%s: failed to prep dma\n", __func__);
415}
416
417static unsigned short mxs_ns_to_ssp_ticks(unsigned clock_rate, unsigned ns)
418{
419 const unsigned int ssp_timeout_mul = 4096;
420 /*
421 * Calculate ticks in ms since ns are large numbers
422 * and might overflow
423 */
424 const unsigned int clock_per_ms = clock_rate / 1000;
425 const unsigned int ms = ns / 1000;
426 const unsigned int ticks = ms * clock_per_ms;
427 const unsigned int ssp_ticks = ticks / ssp_timeout_mul;
428
429 WARN_ON(ssp_ticks == 0);
430 return ssp_ticks;
431}
432
433static void mxs_mmc_adtc(struct mxs_mmc_host *host)
434{
435 struct mmc_command *cmd = host->cmd;
436 struct mmc_data *data = cmd->data;
437 struct dma_async_tx_descriptor *desc;
438 struct scatterlist *sgl = data->sg, *sg;
439 unsigned int sg_len = data->sg_len;
440 int i;
441
442 unsigned short dma_data_dir, timeout;
05f5799c 443 enum dma_transfer_direction slave_dirn;
e4243f13
SG		 444 unsigned int data_size = 0, log2_blksz;
445 unsigned int blocks = data->blocks;
446
447 u32 ignore_crc, get_resp, long_resp, read;
448 u32 ctrl0, cmd0, cmd1, val;
449
450 ignore_crc = (mmc_resp_type(cmd) & MMC_RSP_CRC) ?
451 0 : BM_SSP_CTRL0_IGNORE_CRC;
452 get_resp = (mmc_resp_type(cmd) & MMC_RSP_PRESENT) ?
453 BM_SSP_CTRL0_GET_RESP : 0;
454 long_resp = (mmc_resp_type(cmd) & MMC_RSP_136) ?
455 BM_SSP_CTRL0_LONG_RESP : 0;
456
457 if (data->flags & MMC_DATA_WRITE) {
458 dma_data_dir = DMA_TO_DEVICE;
05f5799c 459 slave_dirn = DMA_MEM_TO_DEV;
e4243f13
SG		 460 read = 0;
461 } else {
462 dma_data_dir = DMA_FROM_DEVICE;
05f5799c 463 slave_dirn = DMA_DEV_TO_MEM;
e4243f13
SG		 464 read = BM_SSP_CTRL0_READ;
465 }
466
467 ctrl0 = BF_SSP(host->bus_width, CTRL0_BUS_WIDTH) |
468 ignore_crc | get_resp | long_resp |
469 BM_SSP_CTRL0_DATA_XFER | read |
470 BM_SSP_CTRL0_WAIT_FOR_IRQ |
471 BM_SSP_CTRL0_ENABLE;
472
473 cmd0 = BF_SSP(cmd->opcode, CMD0_CMD);
474
475 /* get logarithm to base 2 of block size for setting register */
476 log2_blksz = ilog2(data->blksz);
477
478 /*
479 * take special care of the case that data size from data->sg
480 * is not equal to blocks x blksz
481 */
482 for_each_sg(sgl, sg, sg_len, i)
483 data_size += sg->length;
484
485 if (data_size != data->blocks * data->blksz)
486 blocks = 1;
487
488 /* xfer count, block size and count need to be set differently */
e0bf141d 489 if (ssp_is_old(host)) {
e4243f13
SG		 490 ctrl0 |= BF_SSP(data_size, CTRL0_XFER_COUNT);
491 cmd0 |= BF_SSP(log2_blksz, CMD0_BLOCK_SIZE) |
492 BF_SSP(blocks - 1, CMD0_BLOCK_COUNT);
493 } else {
494 writel(data_size, host->base + HW_SSP_XFER_SIZE);
495 writel(BF_SSP(log2_blksz, BLOCK_SIZE_BLOCK_SIZE) |
496 BF_SSP(blocks - 1, BLOCK_SIZE_BLOCK_COUNT),
497 host->base + HW_SSP_BLOCK_SIZE);
498 }
499
500 if ((cmd->opcode == MMC_STOP_TRANSMISSION) ||
501 (cmd->opcode == SD_IO_RW_EXTENDED))
502 cmd0 |= BM_SSP_CMD0_APPEND_8CYC;
503
504 cmd1 = cmd->arg;
505
506 if (host->sdio_irq_en) {
507 ctrl0 |= BM_SSP_CTRL0_SDIO_IRQ_CHECK;
508 cmd0 |= BM_SSP_CMD0_CONT_CLKING_EN | BM_SSP_CMD0_SLOW_CLKING_EN;
509 }
510
511 /* set the timeout count */
512 timeout = mxs_ns_to_ssp_ticks(host->clk_rate, data->timeout_ns);
e0bf141d 513 val = readl(host->base + HW_SSP_TIMING(host));
e4243f13
SG		 514 val &= ~(BM_SSP_TIMING_TIMEOUT);
515 val |= BF_SSP(timeout, TIMING_TIMEOUT);
e0bf141d 516 writel(val, host->base + HW_SSP_TIMING(host));
e4243f13
SG		 517
518 /* pio */
519 host->ssp_pio_words[0] = ctrl0;
520 host->ssp_pio_words[1] = cmd0;
521 host->ssp_pio_words[2] = cmd1;
522 host->dma_dir = DMA_NONE;
a4e3e86d 523 host->slave_dirn = DMA_TRANS_NONE;
e4243f13
SG		 524 desc = mxs_mmc_prep_dma(host, 0);
525 if (!desc)
526 goto out;
527
528 /* append data sg */
529 WARN_ON(host->data != NULL);
530 host->data = data;
531 host->dma_dir = dma_data_dir;
05f5799c 532 host->slave_dirn = slave_dirn;
921de864 533 desc = mxs_mmc_prep_dma(host, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
e4243f13
SG		 534 if (!desc)
535 goto out;
536
537 dmaengine_submit(desc);
d04525ed 538 dma_async_issue_pending(host->dmach);
e4243f13
SG		 539 return;
540out:
541 dev_warn(mmc_dev(host->mmc),
542 "%s: failed to prep dma\n", __func__);
543}
544
545static void mxs_mmc_start_cmd(struct mxs_mmc_host *host,
546 struct mmc_command *cmd)
547{
548 host->cmd = cmd;
549
550 switch (mmc_cmd_type(cmd)) {
551 case MMC_CMD_BC:
552 mxs_mmc_bc(host);
553 break;
554 case MMC_CMD_BCR:
555 mxs_mmc_ac(host);
556 break;
557 case MMC_CMD_AC:
558 mxs_mmc_ac(host);
559 break;
560 case MMC_CMD_ADTC:
561 mxs_mmc_adtc(host);
562 break;
563 default:
564 dev_warn(mmc_dev(host->mmc),
565 "%s: unknown MMC command\n", __func__);
566 break;
567 }
568}
569
570static void mxs_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
571{
572 struct mxs_mmc_host *host = mmc_priv(mmc);
573
574 WARN_ON(host->mrq != NULL);
575 host->mrq = mrq;
576 mxs_mmc_start_cmd(host, mrq->cmd);
577}
578
579static void mxs_mmc_set_clk_rate(struct mxs_mmc_host *host, unsigned int rate)
580{
d982dcdc
KB		 581 unsigned int ssp_clk, ssp_sck;
582 u32 clock_divide, clock_rate;
e4243f13
SG		 583 u32 val;
584
d982dcdc 585 ssp_clk = clk_get_rate(host->clk);
e4243f13 586
d982dcdc
KB		 587 for (clock_divide = 2; clock_divide <= 254; clock_divide += 2) {
588 clock_rate = DIV_ROUND_UP(ssp_clk, rate * clock_divide);
589 clock_rate = (clock_rate > 0) ? clock_rate - 1 : 0;
590 if (clock_rate <= 255)
e4243f13
SG		 591 break;
592 }
593
d982dcdc 594 if (clock_divide > 254) {
e4243f13
SG		 595 dev_err(mmc_dev(host->mmc),
596 "%s: cannot set clock to %d\n", __func__, rate);
597 return;
598 }
599
d982dcdc 600 ssp_sck = ssp_clk / clock_divide / (1 + clock_rate);
e4243f13 601
e0bf141d 602 val = readl(host->base + HW_SSP_TIMING(host));
e4243f13 603 val &= ~(BM_SSP_TIMING_CLOCK_DIVIDE | BM_SSP_TIMING_CLOCK_RATE);
d982dcdc
KB		 604 val |= BF_SSP(clock_divide, TIMING_CLOCK_DIVIDE);
605 val |= BF_SSP(clock_rate, TIMING_CLOCK_RATE);
e0bf141d 606 writel(val, host->base + HW_SSP_TIMING(host));
e4243f13 607
d982dcdc 608 host->clk_rate = ssp_sck;
e4243f13
SG		 609
610 dev_dbg(mmc_dev(host->mmc),
d982dcdc
KB		 611 "%s: clock_divide %d, clock_rate %d, ssp_clk %d, rate_actual %d, rate_requested %d\n",
612 __func__, clock_divide, clock_rate, ssp_clk, ssp_sck, rate);
e4243f13
SG		 613}
614
615static void mxs_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
616{
617 struct mxs_mmc_host *host = mmc_priv(mmc);
618
619 if (ios->bus_width == MMC_BUS_WIDTH_8)
620 host->bus_width = 2;
621 else if (ios->bus_width == MMC_BUS_WIDTH_4)
622 host->bus_width = 1;
623 else
624 host->bus_width = 0;
625
626 if (ios->clock)
627 mxs_mmc_set_clk_rate(host, ios->clock);
628}
629
630static void mxs_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
631{
632 struct mxs_mmc_host *host = mmc_priv(mmc);
633 unsigned long flags;
634
635 spin_lock_irqsave(&host->lock, flags);
636
637 host->sdio_irq_en = enable;
638
639 if (enable) {
640 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
70e60206 641 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_SET);
e4243f13 642 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
e0bf141d 643 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_SET);
e4243f13 644
e0bf141d
SG		 645 if (readl(host->base + HW_SSP_STATUS(host)) &
646 BM_SSP_STATUS_SDIO_IRQ)
e4243f13
SG		 647 mmc_signal_sdio_irq(host->mmc);
648
649 } else {
650 writel(BM_SSP_CTRL0_SDIO_IRQ_CHECK,
70e60206 651 host->base + HW_SSP_CTRL0 + STMP_OFFSET_REG_CLR);
e4243f13 652 writel(BM_SSP_CTRL1_SDIO_IRQ_EN,
e0bf141d 653 host->base + HW_SSP_CTRL1(host) + STMP_OFFSET_REG_CLR);
e4243f13
SG		 654 }
655
656 spin_unlock_irqrestore(&host->lock, flags);
657}
658
659static const struct mmc_host_ops mxs_mmc_ops = {
660 .request = mxs_mmc_request,
661 .get_ro = mxs_mmc_get_ro,
662 .get_cd = mxs_mmc_get_cd,
663 .set_ios = mxs_mmc_set_ios,
664 .enable_sdio_irq = mxs_mmc_enable_sdio_irq,
665};
666
667static bool mxs_mmc_dma_filter(struct dma_chan *chan, void *param)
668{
669 struct mxs_mmc_host *host = param;
670
671 if (!mxs_dma_is_apbh(chan))
672 return false;
673
674 if (chan->chan_id != host->dma_res->start)
675 return false;
676
677 chan->private = &host->dma_data;
678
679 return true;
680}
681
ef9b4d39
SG		 682static struct platform_device_id mxs_mmc_ids[] = {
683 {
684 .name = "imx23-mmc",
685 .driver_data = IMX23_MMC,
686 }, {
687 .name = "imx28-mmc",
688 .driver_data = IMX28_MMC,
689 }, {
690 /* sentinel */
691 }
692};
693MODULE_DEVICE_TABLE(platform, mxs_mmc_ids);
694
e4243f13
SG		 695static int mxs_mmc_probe(struct platform_device *pdev)
696{
697 struct mxs_mmc_host *host;
698 struct mmc_host *mmc;
699 struct resource *iores, *dmares, *r;
700 struct mxs_mmc_platform_data *pdata;
9c92cf24 701 struct pinctrl *pinctrl;
e4243f13
SG		 702 int ret = 0, irq_err, irq_dma;
703 dma_cap_mask_t mask;
704
705 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
706 dmares = platform_get_resource(pdev, IORESOURCE_DMA, 0);
707 irq_err = platform_get_irq(pdev, 0);
708 irq_dma = platform_get_irq(pdev, 1);
709 if (!iores || !dmares || irq_err < 0 || irq_dma < 0)
710 return -EINVAL;
711
712 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
713 if (!r)
714 return -EBUSY;
715
716 mmc = mmc_alloc_host(sizeof(struct mxs_mmc_host), &pdev->dev);
717 if (!mmc) {
718 ret = -ENOMEM;
719 goto out_release_mem;
720 }
721
722 host = mmc_priv(mmc);
723 host->base = ioremap(r->start, resource_size(r));
724 if (!host->base) {
725 ret = -ENOMEM;
726 goto out_mmc_free;
727 }
728
ef9b4d39 729 host->devid = pdev->id_entry->driver_data;
e4243f13
SG		 730 host->mmc = mmc;
731 host->res = r;
732 host->dma_res = dmares;
733 host->irq = irq_err;
734 host->sdio_irq_en = 0;
735
9c92cf24
SG		 736 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
737 if (IS_ERR(pinctrl)) {
738 ret = PTR_ERR(pinctrl);
739 goto out_iounmap;
740 }
741
e4243f13
SG		 742 host->clk = clk_get(&pdev->dev, NULL);
743 if (IS_ERR(host->clk)) {
744 ret = PTR_ERR(host->clk);
745 goto out_iounmap;
746 }
efdfc52c 747 clk_prepare_enable(host->clk);
e4243f13
SG		 748
749 mxs_mmc_reset(host);
750
751 dma_cap_zero(mask);
752 dma_cap_set(DMA_SLAVE, mask);
753 host->dma_data.chan_irq = irq_dma;
754 host->dmach = dma_request_channel(mask, mxs_mmc_dma_filter, host);
755 if (!host->dmach) {
756 dev_err(mmc_dev(host->mmc),
757 "%s: failed to request dma\n", __func__);
758 goto out_clk_put;
759 }
760
761 /* set mmc core parameters */
762 mmc->ops = &mxs_mmc_ops;
763 mmc->caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED |
764 MMC_CAP_SDIO_IRQ | MMC_CAP_NEEDS_POLL;
765
766 pdata = mmc_dev(host->mmc)->platform_data;
767 if (pdata) {
768 if (pdata->flags & SLOTF_8_BIT_CAPABLE)
769 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
770 if (pdata->flags & SLOTF_4_BIT_CAPABLE)
771 mmc->caps |= MMC_CAP_4_BIT_DATA;
772 }
773
774 mmc->f_min = 400000;
775 mmc->f_max = 288000000;
776 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
777
778 mmc->max_segs = 52;
779 mmc->max_blk_size = 1 << 0xf;
e0bf141d
SG		 780 mmc->max_blk_count = (ssp_is_old(host)) ? 0xff : 0xffffff;
781 mmc->max_req_size = (ssp_is_old(host)) ? 0xffff : 0xffffffff;
e4243f13
SG		 782 mmc->max_seg_size = dma_get_max_seg_size(host->dmach->device->dev);
783
784 platform_set_drvdata(pdev, mmc);
785
786 ret = request_irq(host->irq, mxs_mmc_irq_handler, 0, DRIVER_NAME, host);
787 if (ret)
788 goto out_free_dma;
789
790 spin_lock_init(&host->lock);
791
792 ret = mmc_add_host(mmc);
793 if (ret)
794 goto out_free_irq;
795
796 dev_info(mmc_dev(host->mmc), "initialized\n");
797
798 return 0;
799
800out_free_irq:
801 free_irq(host->irq, host);
802out_free_dma:
803 if (host->dmach)
804 dma_release_channel(host->dmach);
805out_clk_put:
efdfc52c 806 clk_disable_unprepare(host->clk);
e4243f13
SG		 807 clk_put(host->clk);
808out_iounmap:
809 iounmap(host->base);
810out_mmc_free:
811 mmc_free_host(mmc);
812out_release_mem:
813 release_mem_region(iores->start, resource_size(iores));
814 return ret;
815}
816
817static int mxs_mmc_remove(struct platform_device *pdev)
818{
819 struct mmc_host *mmc = platform_get_drvdata(pdev);
820 struct mxs_mmc_host *host = mmc_priv(mmc);
821 struct resource *res = host->res;
822
823 mmc_remove_host(mmc);
824
825 free_irq(host->irq, host);
826
827 platform_set_drvdata(pdev, NULL);
828
829 if (host->dmach)
830 dma_release_channel(host->dmach);
831
efdfc52c 832 clk_disable_unprepare(host->clk);
e4243f13
SG		 833 clk_put(host->clk);
834
835 iounmap(host->base);
836
837 mmc_free_host(mmc);
838
839 release_mem_region(res->start, resource_size(res));
840
841 return 0;
842}
843
844#ifdef CONFIG_PM
845static int mxs_mmc_suspend(struct device *dev)
846{
847 struct mmc_host *mmc = dev_get_drvdata(dev);
848 struct mxs_mmc_host *host = mmc_priv(mmc);
849 int ret = 0;
850
851 ret = mmc_suspend_host(mmc);
852
efdfc52c 853 clk_disable_unprepare(host->clk);
e4243f13
SG		 854
855 return ret;
856}
857
858static int mxs_mmc_resume(struct device *dev)
859{
860 struct mmc_host *mmc = dev_get_drvdata(dev);
861 struct mxs_mmc_host *host = mmc_priv(mmc);
862 int ret = 0;
863
efdfc52c 864 clk_prepare_enable(host->clk);
e4243f13
SG		 865
866 ret = mmc_resume_host(mmc);
867
868 return ret;
869}
870
871static const struct dev_pm_ops mxs_mmc_pm_ops = {
872 .suspend = mxs_mmc_suspend,
873 .resume = mxs_mmc_resume,
874};
875#endif
876
877static struct platform_driver mxs_mmc_driver = {
878 .probe = mxs_mmc_probe,
879 .remove = mxs_mmc_remove,
ef9b4d39 880 .id_table = mxs_mmc_ids,
e4243f13
SG		 881 .driver = {
882 .name = DRIVER_NAME,
883 .owner = THIS_MODULE,
884#ifdef CONFIG_PM
885 .pm = &mxs_mmc_pm_ops,
886#endif
887 },
888};
889
d1f81a64 890module_platform_driver(mxs_mmc_driver);
e4243f13
SG		 891
892MODULE_DESCRIPTION("FREESCALE MXS MMC peripheral");
893MODULE_AUTHOR("Freescale Semiconductor");
894MODULE_LICENSE("GPL");
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