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Commit | Line | Data |
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730c9b7e | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/omap.c |
730c9b7e CA |
3 | * |
4 | * Copyright (C) 2004 Nokia Corporation | |
d36b6910 | 5 | * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com> |
730c9b7e CA |
6 | * Misc hacks here and there by Tony Lindgren <tony@atomide.com> |
7 | * Other hacks (DMA, SD, etc) by David Brownell | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
730c9b7e CA |
14 | #include <linux/module.h> |
15 | #include <linux/moduleparam.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/ioport.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/interrupt.h> | |
3451c067 | 20 | #include <linux/dmaengine.h> |
730c9b7e CA |
21 | #include <linux/dma-mapping.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/timer.h> | |
9cb238c0 | 25 | #include <linux/of.h> |
3451c067 | 26 | #include <linux/omap-dma.h> |
730c9b7e | 27 | #include <linux/mmc/host.h> |
730c9b7e | 28 | #include <linux/mmc/card.h> |
b13d1f0f | 29 | #include <linux/mmc/mmc.h> |
730c9b7e | 30 | #include <linux/clk.h> |
45711f1a | 31 | #include <linux/scatterlist.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
68f39e74 | 33 | #include <linux/platform_data/mmc-omap.h> |
730c9b7e | 34 | |
730c9b7e | 35 | |
0551f4df | 36 | #define OMAP_MMC_REG_CMD 0x00 |
0e950fa6 MB |
37 | #define OMAP_MMC_REG_ARGL 0x01 |
38 | #define OMAP_MMC_REG_ARGH 0x02 | |
39 | #define OMAP_MMC_REG_CON 0x03 | |
40 | #define OMAP_MMC_REG_STAT 0x04 | |
41 | #define OMAP_MMC_REG_IE 0x05 | |
42 | #define OMAP_MMC_REG_CTO 0x06 | |
43 | #define OMAP_MMC_REG_DTO 0x07 | |
44 | #define OMAP_MMC_REG_DATA 0x08 | |
45 | #define OMAP_MMC_REG_BLEN 0x09 | |
46 | #define OMAP_MMC_REG_NBLK 0x0a | |
47 | #define OMAP_MMC_REG_BUF 0x0b | |
48 | #define OMAP_MMC_REG_SDIO 0x0d | |
49 | #define OMAP_MMC_REG_REV 0x0f | |
50 | #define OMAP_MMC_REG_RSP0 0x10 | |
51 | #define OMAP_MMC_REG_RSP1 0x11 | |
52 | #define OMAP_MMC_REG_RSP2 0x12 | |
53 | #define OMAP_MMC_REG_RSP3 0x13 | |
54 | #define OMAP_MMC_REG_RSP4 0x14 | |
55 | #define OMAP_MMC_REG_RSP5 0x15 | |
56 | #define OMAP_MMC_REG_RSP6 0x16 | |
57 | #define OMAP_MMC_REG_RSP7 0x17 | |
58 | #define OMAP_MMC_REG_IOSR 0x18 | |
59 | #define OMAP_MMC_REG_SYSC 0x19 | |
60 | #define OMAP_MMC_REG_SYSS 0x1a | |
0551f4df JY |
61 | |
62 | #define OMAP_MMC_STAT_CARD_ERR (1 << 14) | |
63 | #define OMAP_MMC_STAT_CARD_IRQ (1 << 13) | |
64 | #define OMAP_MMC_STAT_OCR_BUSY (1 << 12) | |
65 | #define OMAP_MMC_STAT_A_EMPTY (1 << 11) | |
66 | #define OMAP_MMC_STAT_A_FULL (1 << 10) | |
67 | #define OMAP_MMC_STAT_CMD_CRC (1 << 8) | |
68 | #define OMAP_MMC_STAT_CMD_TOUT (1 << 7) | |
69 | #define OMAP_MMC_STAT_DATA_CRC (1 << 6) | |
70 | #define OMAP_MMC_STAT_DATA_TOUT (1 << 5) | |
71 | #define OMAP_MMC_STAT_END_BUSY (1 << 4) | |
72 | #define OMAP_MMC_STAT_END_OF_DATA (1 << 3) | |
73 | #define OMAP_MMC_STAT_CARD_BUSY (1 << 2) | |
74 | #define OMAP_MMC_STAT_END_OF_CMD (1 << 0) | |
75 | ||
53db20d1 TL |
76 | #define mmc_omap7xx() (host->features & MMC_OMAP7XX) |
77 | #define mmc_omap15xx() (host->features & MMC_OMAP15XX) | |
78 | #define mmc_omap16xx() (host->features & MMC_OMAP16XX) | |
79 | #define MMC_OMAP1_MASK (MMC_OMAP7XX | MMC_OMAP15XX | MMC_OMAP16XX) | |
80 | #define mmc_omap1() (host->features & MMC_OMAP1_MASK) | |
81 | #define mmc_omap2() (!mmc_omap1()) | |
82 | ||
0e950fa6 MB |
83 | #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift) |
84 | #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg)) | |
85 | #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg)) | |
0551f4df JY |
86 | |
87 | /* | |
88 | * Command types | |
89 | */ | |
90 | #define OMAP_MMC_CMDTYPE_BC 0 | |
91 | #define OMAP_MMC_CMDTYPE_BCR 1 | |
92 | #define OMAP_MMC_CMDTYPE_AC 2 | |
93 | #define OMAP_MMC_CMDTYPE_ADTC 3 | |
94 | ||
730c9b7e | 95 | #define DRIVER_NAME "mmci-omap" |
730c9b7e CA |
96 | |
97 | /* Specifies how often in millisecs to poll for card status changes | |
98 | * when the cover switch is open */ | |
7584d276 | 99 | #define OMAP_MMC_COVER_POLL_DELAY 500 |
730c9b7e | 100 | |
abfbe5f7 JY |
101 | struct mmc_omap_host; |
102 | ||
103 | struct mmc_omap_slot { | |
104 | int id; | |
105 | unsigned int vdd; | |
106 | u16 saved_con; | |
107 | u16 bus_mode; | |
108 | unsigned int fclk_freq; | |
abfbe5f7 | 109 | |
7584d276 JL |
110 | struct tasklet_struct cover_tasklet; |
111 | struct timer_list cover_timer; | |
5a0f3f1f JY |
112 | unsigned cover_open; |
113 | ||
abfbe5f7 JY |
114 | struct mmc_request *mrq; |
115 | struct mmc_omap_host *host; | |
116 | struct mmc_host *mmc; | |
117 | struct omap_mmc_slot_data *pdata; | |
118 | }; | |
119 | ||
730c9b7e CA |
120 | struct mmc_omap_host { |
121 | int initialized; | |
730c9b7e CA |
122 | struct mmc_request * mrq; |
123 | struct mmc_command * cmd; | |
124 | struct mmc_data * data; | |
125 | struct mmc_host * mmc; | |
126 | struct device * dev; | |
127 | unsigned char id; /* 16xx chips have 2 MMC blocks */ | |
128 | struct clk * iclk; | |
129 | struct clk * fclk; | |
3451c067 RK |
130 | struct dma_chan *dma_rx; |
131 | u32 dma_rx_burst; | |
132 | struct dma_chan *dma_tx; | |
133 | u32 dma_tx_burst; | |
89783b1e JY |
134 | void __iomem *virt_base; |
135 | unsigned int phys_base; | |
730c9b7e CA |
136 | int irq; |
137 | unsigned char bus_mode; | |
0e950fa6 | 138 | unsigned int reg_shift; |
730c9b7e | 139 | |
0fb4723d JL |
140 | struct work_struct cmd_abort_work; |
141 | unsigned abort:1; | |
142 | struct timer_list cmd_abort_timer; | |
eb1860bc | 143 | |
0f602ec7 JL |
144 | struct work_struct slot_release_work; |
145 | struct mmc_omap_slot *next_slot; | |
146 | struct work_struct send_stop_work; | |
147 | struct mmc_data *stop_data; | |
148 | ||
730c9b7e CA |
149 | unsigned int sg_len; |
150 | int sg_idx; | |
151 | u16 * buffer; | |
152 | u32 buffer_bytes_left; | |
153 | u32 total_bytes_left; | |
154 | ||
53db20d1 | 155 | unsigned features; |
730c9b7e | 156 | unsigned brs_received:1, dma_done:1; |
730c9b7e | 157 | unsigned dma_in_use:1; |
3451c067 | 158 | spinlock_t dma_lock; |
730c9b7e | 159 | |
abfbe5f7 JY |
160 | struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS]; |
161 | struct mmc_omap_slot *current_slot; | |
162 | spinlock_t slot_lock; | |
163 | wait_queue_head_t slot_wq; | |
164 | int nr_slots; | |
165 | ||
0807a9b5 JL |
166 | struct timer_list clk_timer; |
167 | spinlock_t clk_lock; /* for changing enabled state */ | |
168 | unsigned int fclk_enabled:1; | |
b01a4f1c | 169 | struct workqueue_struct *mmc_omap_wq; |
0807a9b5 | 170 | |
abfbe5f7 | 171 | struct omap_mmc_platform_data *pdata; |
730c9b7e CA |
172 | }; |
173 | ||
0d9ee5b2 | 174 | |
7c8ad982 | 175 | static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot) |
0807a9b5 JL |
176 | { |
177 | unsigned long tick_ns; | |
178 | ||
179 | if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) { | |
03a16853 | 180 | tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq); |
0807a9b5 JL |
181 | ndelay(8 * tick_ns); |
182 | } | |
183 | } | |
184 | ||
7c8ad982 | 185 | static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable) |
0807a9b5 JL |
186 | { |
187 | unsigned long flags; | |
188 | ||
189 | spin_lock_irqsave(&host->clk_lock, flags); | |
190 | if (host->fclk_enabled != enable) { | |
191 | host->fclk_enabled = enable; | |
192 | if (enable) | |
193 | clk_enable(host->fclk); | |
194 | else | |
195 | clk_disable(host->fclk); | |
196 | } | |
197 | spin_unlock_irqrestore(&host->clk_lock, flags); | |
198 | } | |
199 | ||
abfbe5f7 JY |
200 | static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed) |
201 | { | |
202 | struct mmc_omap_host *host = slot->host; | |
203 | unsigned long flags; | |
204 | ||
205 | if (claimed) | |
206 | goto no_claim; | |
207 | spin_lock_irqsave(&host->slot_lock, flags); | |
208 | while (host->mmc != NULL) { | |
209 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
210 | wait_event(host->slot_wq, host->mmc == NULL); | |
211 | spin_lock_irqsave(&host->slot_lock, flags); | |
212 | } | |
213 | host->mmc = slot->mmc; | |
214 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
215 | no_claim: | |
0807a9b5 JL |
216 | del_timer(&host->clk_timer); |
217 | if (host->current_slot != slot || !claimed) | |
218 | mmc_omap_fclk_offdelay(host->current_slot); | |
219 | ||
abfbe5f7 | 220 | if (host->current_slot != slot) { |
0807a9b5 | 221 | OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00); |
abfbe5f7 JY |
222 | if (host->pdata->switch_slot != NULL) |
223 | host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id); | |
224 | host->current_slot = slot; | |
225 | } | |
226 | ||
0807a9b5 JL |
227 | if (claimed) { |
228 | mmc_omap_fclk_enable(host, 1); | |
229 | ||
230 | /* Doing the dummy read here seems to work around some bug | |
231 | * at least in OMAP24xx silicon where the command would not | |
232 | * start after writing the CMD register. Sigh. */ | |
233 | OMAP_MMC_READ(host, CON); | |
abfbe5f7 | 234 | |
0807a9b5 JL |
235 | OMAP_MMC_WRITE(host, CON, slot->saved_con); |
236 | } else | |
237 | mmc_omap_fclk_enable(host, 0); | |
abfbe5f7 JY |
238 | } |
239 | ||
240 | static void mmc_omap_start_request(struct mmc_omap_host *host, | |
241 | struct mmc_request *req); | |
242 | ||
0f602ec7 JL |
243 | static void mmc_omap_slot_release_work(struct work_struct *work) |
244 | { | |
245 | struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, | |
246 | slot_release_work); | |
247 | struct mmc_omap_slot *next_slot = host->next_slot; | |
248 | struct mmc_request *rq; | |
249 | ||
250 | host->next_slot = NULL; | |
251 | mmc_omap_select_slot(next_slot, 1); | |
252 | ||
253 | rq = next_slot->mrq; | |
254 | next_slot->mrq = NULL; | |
255 | mmc_omap_start_request(host, rq); | |
256 | } | |
257 | ||
0807a9b5 | 258 | static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled) |
abfbe5f7 JY |
259 | { |
260 | struct mmc_omap_host *host = slot->host; | |
261 | unsigned long flags; | |
262 | int i; | |
263 | ||
264 | BUG_ON(slot == NULL || host->mmc == NULL); | |
0807a9b5 JL |
265 | |
266 | if (clk_enabled) | |
267 | /* Keeps clock running for at least 8 cycles on valid freq */ | |
268 | mod_timer(&host->clk_timer, jiffies + HZ/10); | |
269 | else { | |
270 | del_timer(&host->clk_timer); | |
271 | mmc_omap_fclk_offdelay(slot); | |
272 | mmc_omap_fclk_enable(host, 0); | |
273 | } | |
abfbe5f7 JY |
274 | |
275 | spin_lock_irqsave(&host->slot_lock, flags); | |
276 | /* Check for any pending requests */ | |
277 | for (i = 0; i < host->nr_slots; i++) { | |
278 | struct mmc_omap_slot *new_slot; | |
abfbe5f7 JY |
279 | |
280 | if (host->slots[i] == NULL || host->slots[i]->mrq == NULL) | |
281 | continue; | |
282 | ||
0f602ec7 | 283 | BUG_ON(host->next_slot != NULL); |
abfbe5f7 JY |
284 | new_slot = host->slots[i]; |
285 | /* The current slot should not have a request in queue */ | |
286 | BUG_ON(new_slot == host->current_slot); | |
287 | ||
0f602ec7 | 288 | host->next_slot = new_slot; |
abfbe5f7 JY |
289 | host->mmc = new_slot->mmc; |
290 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
b01a4f1c | 291 | queue_work(host->mmc_omap_wq, &host->slot_release_work); |
abfbe5f7 JY |
292 | return; |
293 | } | |
294 | ||
295 | host->mmc = NULL; | |
296 | wake_up(&host->slot_wq); | |
297 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
298 | } | |
299 | ||
5a0f3f1f JY |
300 | static inline |
301 | int mmc_omap_cover_is_open(struct mmc_omap_slot *slot) | |
302 | { | |
8348f002 KP |
303 | if (slot->pdata->get_cover_state) |
304 | return slot->pdata->get_cover_state(mmc_dev(slot->mmc), | |
305 | slot->id); | |
306 | return 0; | |
5a0f3f1f JY |
307 | } |
308 | ||
309 | static ssize_t | |
310 | mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr, | |
311 | char *buf) | |
312 | { | |
313 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
314 | struct mmc_omap_slot *slot = mmc_priv(mmc); | |
315 | ||
316 | return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" : | |
317 | "closed"); | |
318 | } | |
319 | ||
320 | static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); | |
321 | ||
abfbe5f7 JY |
322 | static ssize_t |
323 | mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, | |
324 | char *buf) | |
325 | { | |
326 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
327 | struct mmc_omap_slot *slot = mmc_priv(mmc); | |
328 | ||
329 | return sprintf(buf, "%s\n", slot->pdata->name); | |
330 | } | |
331 | ||
332 | static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL); | |
333 | ||
730c9b7e CA |
334 | static void |
335 | mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd) | |
336 | { | |
337 | u32 cmdreg; | |
338 | u32 resptype; | |
339 | u32 cmdtype; | |
b13d1f0f | 340 | u16 irq_mask; |
730c9b7e CA |
341 | |
342 | host->cmd = cmd; | |
343 | ||
344 | resptype = 0; | |
345 | cmdtype = 0; | |
346 | ||
347 | /* Our hardware needs to know exact type */ | |
1b3b2631 CEA |
348 | switch (mmc_resp_type(cmd)) { |
349 | case MMC_RSP_NONE: | |
350 | break; | |
351 | case MMC_RSP_R1: | |
352 | case MMC_RSP_R1B: | |
6f949909 | 353 | /* resp 1, 1b, 6, 7 */ |
730c9b7e CA |
354 | resptype = 1; |
355 | break; | |
1b3b2631 | 356 | case MMC_RSP_R2: |
730c9b7e CA |
357 | resptype = 2; |
358 | break; | |
1b3b2631 | 359 | case MMC_RSP_R3: |
730c9b7e CA |
360 | resptype = 3; |
361 | break; | |
362 | default: | |
1b3b2631 | 363 | dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd)); |
730c9b7e CA |
364 | break; |
365 | } | |
366 | ||
367 | if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) { | |
368 | cmdtype = OMAP_MMC_CMDTYPE_ADTC; | |
369 | } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) { | |
370 | cmdtype = OMAP_MMC_CMDTYPE_BC; | |
371 | } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) { | |
372 | cmdtype = OMAP_MMC_CMDTYPE_BCR; | |
373 | } else { | |
374 | cmdtype = OMAP_MMC_CMDTYPE_AC; | |
375 | } | |
376 | ||
377 | cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12); | |
378 | ||
abfbe5f7 | 379 | if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN) |
730c9b7e CA |
380 | cmdreg |= 1 << 6; |
381 | ||
382 | if (cmd->flags & MMC_RSP_BUSY) | |
383 | cmdreg |= 1 << 11; | |
384 | ||
385 | if (host->data && !(host->data->flags & MMC_DATA_WRITE)) | |
386 | cmdreg |= 1 << 15; | |
387 | ||
0fb4723d | 388 | mod_timer(&host->cmd_abort_timer, jiffies + HZ/2); |
eb1860bc | 389 | |
3342ee8b JY |
390 | OMAP_MMC_WRITE(host, CTO, 200); |
391 | OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff); | |
392 | OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16); | |
b13d1f0f JN |
393 | irq_mask = OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL | |
394 | OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT | | |
395 | OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT | | |
396 | OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR | | |
397 | OMAP_MMC_STAT_END_OF_DATA; | |
398 | if (cmd->opcode == MMC_ERASE) | |
399 | irq_mask &= ~OMAP_MMC_STAT_DATA_TOUT; | |
400 | OMAP_MMC_WRITE(host, IE, irq_mask); | |
3342ee8b | 401 | OMAP_MMC_WRITE(host, CMD, cmdreg); |
730c9b7e CA |
402 | } |
403 | ||
a914ded2 JY |
404 | static void |
405 | mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data, | |
406 | int abort) | |
407 | { | |
408 | enum dma_data_direction dma_data_dir; | |
3451c067 RK |
409 | struct device *dev = mmc_dev(host->mmc); |
410 | struct dma_chan *c; | |
a914ded2 | 411 | |
3451c067 | 412 | if (data->flags & MMC_DATA_WRITE) { |
a914ded2 | 413 | dma_data_dir = DMA_TO_DEVICE; |
3451c067 RK |
414 | c = host->dma_tx; |
415 | } else { | |
a914ded2 | 416 | dma_data_dir = DMA_FROM_DEVICE; |
3451c067 RK |
417 | c = host->dma_rx; |
418 | } | |
419 | if (c) { | |
420 | if (data->error) { | |
421 | dmaengine_terminate_all(c); | |
422 | /* Claim nothing transferred on error... */ | |
423 | data->bytes_xfered = 0; | |
424 | } | |
425 | dev = c->device->dev; | |
426 | } | |
427 | dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir); | |
a914ded2 JY |
428 | } |
429 | ||
0f602ec7 JL |
430 | static void mmc_omap_send_stop_work(struct work_struct *work) |
431 | { | |
432 | struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, | |
433 | send_stop_work); | |
434 | struct mmc_omap_slot *slot = host->current_slot; | |
435 | struct mmc_data *data = host->stop_data; | |
436 | unsigned long tick_ns; | |
437 | ||
03a16853 | 438 | tick_ns = DIV_ROUND_UP(NSEC_PER_SEC, slot->fclk_freq); |
0f602ec7 JL |
439 | ndelay(8*tick_ns); |
440 | ||
441 | mmc_omap_start_command(host, data->stop); | |
442 | } | |
443 | ||
730c9b7e CA |
444 | static void |
445 | mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) | |
446 | { | |
a914ded2 JY |
447 | if (host->dma_in_use) |
448 | mmc_omap_release_dma(host, data, data->error); | |
449 | ||
730c9b7e CA |
450 | host->data = NULL; |
451 | host->sg_len = 0; | |
730c9b7e CA |
452 | |
453 | /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing | |
454 | * dozens of requests until the card finishes writing data. | |
455 | * It'd be cheaper to just wait till an EOFB interrupt arrives... | |
456 | */ | |
457 | ||
458 | if (!data->stop) { | |
a914ded2 JY |
459 | struct mmc_host *mmc; |
460 | ||
730c9b7e | 461 | host->mrq = NULL; |
a914ded2 | 462 | mmc = host->mmc; |
0807a9b5 | 463 | mmc_omap_release_slot(host->current_slot, 1); |
a914ded2 | 464 | mmc_request_done(mmc, data->mrq); |
730c9b7e CA |
465 | return; |
466 | } | |
467 | ||
0f602ec7 | 468 | host->stop_data = data; |
b01a4f1c | 469 | queue_work(host->mmc_omap_wq, &host->send_stop_work); |
730c9b7e CA |
470 | } |
471 | ||
eb1860bc | 472 | static void |
0fb4723d | 473 | mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops) |
eb1860bc JL |
474 | { |
475 | struct mmc_omap_slot *slot = host->current_slot; | |
476 | unsigned int restarts, passes, timeout; | |
477 | u16 stat = 0; | |
478 | ||
479 | /* Sending abort takes 80 clocks. Have some extra and round up */ | |
03a16853 | 480 | timeout = DIV_ROUND_UP(120 * USEC_PER_SEC, slot->fclk_freq); |
eb1860bc | 481 | restarts = 0; |
0fb4723d | 482 | while (restarts < maxloops) { |
eb1860bc JL |
483 | OMAP_MMC_WRITE(host, STAT, 0xFFFF); |
484 | OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7)); | |
485 | ||
486 | passes = 0; | |
487 | while (passes < timeout) { | |
488 | stat = OMAP_MMC_READ(host, STAT); | |
489 | if (stat & OMAP_MMC_STAT_END_OF_CMD) | |
490 | goto out; | |
491 | udelay(1); | |
492 | passes++; | |
493 | } | |
494 | ||
495 | restarts++; | |
496 | } | |
497 | out: | |
498 | OMAP_MMC_WRITE(host, STAT, stat); | |
499 | } | |
500 | ||
a914ded2 JY |
501 | static void |
502 | mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data) | |
503 | { | |
a914ded2 JY |
504 | if (host->dma_in_use) |
505 | mmc_omap_release_dma(host, data, 1); | |
506 | ||
507 | host->data = NULL; | |
508 | host->sg_len = 0; | |
509 | ||
0fb4723d | 510 | mmc_omap_send_abort(host, 10000); |
a914ded2 JY |
511 | } |
512 | ||
730c9b7e CA |
513 | static void |
514 | mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data) | |
515 | { | |
516 | unsigned long flags; | |
517 | int done; | |
518 | ||
519 | if (!host->dma_in_use) { | |
520 | mmc_omap_xfer_done(host, data); | |
521 | return; | |
522 | } | |
523 | done = 0; | |
524 | spin_lock_irqsave(&host->dma_lock, flags); | |
525 | if (host->dma_done) | |
526 | done = 1; | |
527 | else | |
528 | host->brs_received = 1; | |
529 | spin_unlock_irqrestore(&host->dma_lock, flags); | |
530 | if (done) | |
531 | mmc_omap_xfer_done(host, data); | |
532 | } | |
533 | ||
730c9b7e CA |
534 | static void |
535 | mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data) | |
536 | { | |
537 | unsigned long flags; | |
538 | int done; | |
539 | ||
540 | done = 0; | |
541 | spin_lock_irqsave(&host->dma_lock, flags); | |
542 | if (host->brs_received) | |
543 | done = 1; | |
544 | else | |
545 | host->dma_done = 1; | |
546 | spin_unlock_irqrestore(&host->dma_lock, flags); | |
547 | if (done) | |
548 | mmc_omap_xfer_done(host, data); | |
549 | } | |
550 | ||
551 | static void | |
552 | mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) | |
553 | { | |
554 | host->cmd = NULL; | |
555 | ||
0fb4723d | 556 | del_timer(&host->cmd_abort_timer); |
eb1860bc | 557 | |
730c9b7e CA |
558 | if (cmd->flags & MMC_RSP_PRESENT) { |
559 | if (cmd->flags & MMC_RSP_136) { | |
560 | /* response type 2 */ | |
561 | cmd->resp[3] = | |
3342ee8b JY |
562 | OMAP_MMC_READ(host, RSP0) | |
563 | (OMAP_MMC_READ(host, RSP1) << 16); | |
730c9b7e | 564 | cmd->resp[2] = |
3342ee8b JY |
565 | OMAP_MMC_READ(host, RSP2) | |
566 | (OMAP_MMC_READ(host, RSP3) << 16); | |
730c9b7e | 567 | cmd->resp[1] = |
3342ee8b JY |
568 | OMAP_MMC_READ(host, RSP4) | |
569 | (OMAP_MMC_READ(host, RSP5) << 16); | |
730c9b7e | 570 | cmd->resp[0] = |
3342ee8b JY |
571 | OMAP_MMC_READ(host, RSP6) | |
572 | (OMAP_MMC_READ(host, RSP7) << 16); | |
730c9b7e CA |
573 | } else { |
574 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
575 | cmd->resp[0] = | |
3342ee8b JY |
576 | OMAP_MMC_READ(host, RSP6) | |
577 | (OMAP_MMC_READ(host, RSP7) << 16); | |
730c9b7e CA |
578 | } |
579 | } | |
580 | ||
17b0429d | 581 | if (host->data == NULL || cmd->error) { |
a914ded2 JY |
582 | struct mmc_host *mmc; |
583 | ||
584 | if (host->data != NULL) | |
585 | mmc_omap_abort_xfer(host, host->data); | |
730c9b7e | 586 | host->mrq = NULL; |
a914ded2 | 587 | mmc = host->mmc; |
0807a9b5 | 588 | mmc_omap_release_slot(host->current_slot, 1); |
a914ded2 | 589 | mmc_request_done(mmc, cmd->mrq); |
730c9b7e CA |
590 | } |
591 | } | |
592 | ||
eb1860bc JL |
593 | /* |
594 | * Abort stuck command. Can occur when card is removed while it is being | |
595 | * read. | |
596 | */ | |
597 | static void mmc_omap_abort_command(struct work_struct *work) | |
598 | { | |
599 | struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, | |
0fb4723d JL |
600 | cmd_abort_work); |
601 | BUG_ON(!host->cmd); | |
eb1860bc JL |
602 | |
603 | dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n", | |
604 | host->cmd->opcode); | |
605 | ||
0fb4723d JL |
606 | if (host->cmd->error == 0) |
607 | host->cmd->error = -ETIMEDOUT; | |
eb1860bc | 608 | |
0fb4723d JL |
609 | if (host->data == NULL) { |
610 | struct mmc_command *cmd; | |
611 | struct mmc_host *mmc; | |
612 | ||
613 | cmd = host->cmd; | |
614 | host->cmd = NULL; | |
615 | mmc_omap_send_abort(host, 10000); | |
616 | ||
617 | host->mrq = NULL; | |
618 | mmc = host->mmc; | |
0807a9b5 | 619 | mmc_omap_release_slot(host->current_slot, 1); |
0fb4723d JL |
620 | mmc_request_done(mmc, cmd->mrq); |
621 | } else | |
622 | mmc_omap_cmd_done(host, host->cmd); | |
eb1860bc | 623 | |
0fb4723d JL |
624 | host->abort = 0; |
625 | enable_irq(host->irq); | |
eb1860bc JL |
626 | } |
627 | ||
628 | static void | |
629 | mmc_omap_cmd_timer(unsigned long data) | |
630 | { | |
631 | struct mmc_omap_host *host = (struct mmc_omap_host *) data; | |
0fb4723d | 632 | unsigned long flags; |
eb1860bc | 633 | |
0fb4723d JL |
634 | spin_lock_irqsave(&host->slot_lock, flags); |
635 | if (host->cmd != NULL && !host->abort) { | |
636 | OMAP_MMC_WRITE(host, IE, 0); | |
637 | disable_irq(host->irq); | |
638 | host->abort = 1; | |
b01a4f1c | 639 | queue_work(host->mmc_omap_wq, &host->cmd_abort_work); |
0fb4723d JL |
640 | } |
641 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
eb1860bc JL |
642 | } |
643 | ||
730c9b7e CA |
644 | /* PIO only */ |
645 | static void | |
646 | mmc_omap_sg_to_buf(struct mmc_omap_host *host) | |
647 | { | |
648 | struct scatterlist *sg; | |
649 | ||
650 | sg = host->data->sg + host->sg_idx; | |
651 | host->buffer_bytes_left = sg->length; | |
45711f1a | 652 | host->buffer = sg_virt(sg); |
730c9b7e CA |
653 | if (host->buffer_bytes_left > host->total_bytes_left) |
654 | host->buffer_bytes_left = host->total_bytes_left; | |
655 | } | |
656 | ||
0807a9b5 JL |
657 | static void |
658 | mmc_omap_clk_timer(unsigned long data) | |
659 | { | |
660 | struct mmc_omap_host *host = (struct mmc_omap_host *) data; | |
661 | ||
662 | mmc_omap_fclk_enable(host, 0); | |
663 | } | |
664 | ||
730c9b7e CA |
665 | /* PIO only */ |
666 | static void | |
667 | mmc_omap_xfer_data(struct mmc_omap_host *host, int write) | |
668 | { | |
75b53aee | 669 | int n, nwords; |
730c9b7e CA |
670 | |
671 | if (host->buffer_bytes_left == 0) { | |
672 | host->sg_idx++; | |
673 | BUG_ON(host->sg_idx == host->sg_len); | |
674 | mmc_omap_sg_to_buf(host); | |
675 | } | |
676 | n = 64; | |
677 | if (n > host->buffer_bytes_left) | |
678 | n = host->buffer_bytes_left; | |
75b53aee | 679 | |
03a16853 AL |
680 | /* Round up to handle odd number of bytes to transfer */ |
681 | nwords = DIV_ROUND_UP(n, 2); | |
75b53aee | 682 | |
730c9b7e CA |
683 | host->buffer_bytes_left -= n; |
684 | host->total_bytes_left -= n; | |
685 | host->data->bytes_xfered += n; | |
686 | ||
687 | if (write) { | |
75b53aee PW |
688 | __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), |
689 | host->buffer, nwords); | |
730c9b7e | 690 | } else { |
75b53aee PW |
691 | __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), |
692 | host->buffer, nwords); | |
730c9b7e | 693 | } |
75b53aee PW |
694 | |
695 | host->buffer += nwords; | |
730c9b7e CA |
696 | } |
697 | ||
75d569d3 V |
698 | #ifdef CONFIG_MMC_DEBUG |
699 | static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status) | |
730c9b7e CA |
700 | { |
701 | static const char *mmc_omap_status_bits[] = { | |
702 | "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO", | |
703 | "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR" | |
704 | }; | |
75d569d3 V |
705 | int i; |
706 | char res[64], *buf = res; | |
707 | ||
708 | buf += sprintf(buf, "MMC IRQ 0x%x:", status); | |
730c9b7e CA |
709 | |
710 | for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) | |
75d569d3 V |
711 | if (status & (1 << i)) |
712 | buf += sprintf(buf, " %s", mmc_omap_status_bits[i]); | |
713 | dev_vdbg(mmc_dev(host->mmc), "%s\n", res); | |
714 | } | |
715 | #else | |
716 | static void mmc_omap_report_irq(struct mmc_omap_host *host, u16 status) | |
717 | { | |
730c9b7e | 718 | } |
75d569d3 V |
719 | #endif |
720 | ||
730c9b7e | 721 | |
7d12e780 | 722 | static irqreturn_t mmc_omap_irq(int irq, void *dev_id) |
730c9b7e CA |
723 | { |
724 | struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id; | |
725 | u16 status; | |
726 | int end_command; | |
727 | int end_transfer; | |
2a50b888 | 728 | int transfer_error, cmd_error; |
730c9b7e CA |
729 | |
730 | if (host->cmd == NULL && host->data == NULL) { | |
3342ee8b | 731 | status = OMAP_MMC_READ(host, STAT); |
2a50b888 JY |
732 | dev_info(mmc_dev(host->slots[0]->mmc), |
733 | "Spurious IRQ 0x%04x\n", status); | |
730c9b7e | 734 | if (status != 0) { |
3342ee8b JY |
735 | OMAP_MMC_WRITE(host, STAT, status); |
736 | OMAP_MMC_WRITE(host, IE, 0); | |
730c9b7e CA |
737 | } |
738 | return IRQ_HANDLED; | |
739 | } | |
740 | ||
741 | end_command = 0; | |
742 | end_transfer = 0; | |
743 | transfer_error = 0; | |
2a50b888 | 744 | cmd_error = 0; |
730c9b7e | 745 | |
3342ee8b | 746 | while ((status = OMAP_MMC_READ(host, STAT)) != 0) { |
2a50b888 JY |
747 | int cmd; |
748 | ||
3342ee8b | 749 | OMAP_MMC_WRITE(host, STAT, status); |
2a50b888 JY |
750 | if (host->cmd != NULL) |
751 | cmd = host->cmd->opcode; | |
752 | else | |
753 | cmd = -1; | |
730c9b7e | 754 | dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ", |
2a50b888 | 755 | status, cmd); |
75d569d3 V |
756 | mmc_omap_report_irq(host, status); |
757 | ||
730c9b7e CA |
758 | if (host->total_bytes_left) { |
759 | if ((status & OMAP_MMC_STAT_A_FULL) || | |
760 | (status & OMAP_MMC_STAT_END_OF_DATA)) | |
761 | mmc_omap_xfer_data(host, 0); | |
762 | if (status & OMAP_MMC_STAT_A_EMPTY) | |
763 | mmc_omap_xfer_data(host, 1); | |
764 | } | |
765 | ||
2a50b888 | 766 | if (status & OMAP_MMC_STAT_END_OF_DATA) |
730c9b7e | 767 | end_transfer = 1; |
730c9b7e CA |
768 | |
769 | if (status & OMAP_MMC_STAT_DATA_TOUT) { | |
2a50b888 JY |
770 | dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n", |
771 | cmd); | |
730c9b7e | 772 | if (host->data) { |
17b0429d | 773 | host->data->error = -ETIMEDOUT; |
730c9b7e CA |
774 | transfer_error = 1; |
775 | } | |
776 | } | |
777 | ||
778 | if (status & OMAP_MMC_STAT_DATA_CRC) { | |
779 | if (host->data) { | |
17b0429d | 780 | host->data->error = -EILSEQ; |
730c9b7e CA |
781 | dev_dbg(mmc_dev(host->mmc), |
782 | "data CRC error, bytes left %d\n", | |
783 | host->total_bytes_left); | |
784 | transfer_error = 1; | |
785 | } else { | |
786 | dev_dbg(mmc_dev(host->mmc), "data CRC error\n"); | |
787 | } | |
788 | } | |
789 | ||
790 | if (status & OMAP_MMC_STAT_CMD_TOUT) { | |
791 | /* Timeouts are routine with some commands */ | |
792 | if (host->cmd) { | |
abfbe5f7 JY |
793 | struct mmc_omap_slot *slot = |
794 | host->current_slot; | |
2a50b888 JY |
795 | if (slot == NULL || |
796 | !mmc_omap_cover_is_open(slot)) | |
5a0f3f1f | 797 | dev_err(mmc_dev(host->mmc), |
2a50b888 JY |
798 | "command timeout (CMD%d)\n", |
799 | cmd); | |
17b0429d | 800 | host->cmd->error = -ETIMEDOUT; |
730c9b7e | 801 | end_command = 1; |
2a50b888 | 802 | cmd_error = 1; |
730c9b7e CA |
803 | } |
804 | } | |
805 | ||
806 | if (status & OMAP_MMC_STAT_CMD_CRC) { | |
807 | if (host->cmd) { | |
808 | dev_err(mmc_dev(host->mmc), | |
809 | "command CRC error (CMD%d, arg 0x%08x)\n", | |
2a50b888 | 810 | cmd, host->cmd->arg); |
17b0429d | 811 | host->cmd->error = -EILSEQ; |
730c9b7e | 812 | end_command = 1; |
2a50b888 | 813 | cmd_error = 1; |
730c9b7e CA |
814 | } else |
815 | dev_err(mmc_dev(host->mmc), | |
816 | "command CRC error without cmd?\n"); | |
817 | } | |
818 | ||
819 | if (status & OMAP_MMC_STAT_CARD_ERR) { | |
0107a4b3 RM |
820 | dev_dbg(mmc_dev(host->mmc), |
821 | "ignoring card status error (CMD%d)\n", | |
2a50b888 | 822 | cmd); |
0107a4b3 | 823 | end_command = 1; |
730c9b7e CA |
824 | } |
825 | ||
826 | /* | |
827 | * NOTE: On 1610 the END_OF_CMD may come too early when | |
2a50b888 | 828 | * starting a write |
730c9b7e CA |
829 | */ |
830 | if ((status & OMAP_MMC_STAT_END_OF_CMD) && | |
831 | (!(status & OMAP_MMC_STAT_A_EMPTY))) { | |
832 | end_command = 1; | |
833 | } | |
834 | } | |
835 | ||
0fb4723d JL |
836 | if (cmd_error && host->data) { |
837 | del_timer(&host->cmd_abort_timer); | |
838 | host->abort = 1; | |
839 | OMAP_MMC_WRITE(host, IE, 0); | |
e749c6f2 | 840 | disable_irq_nosync(host->irq); |
b01a4f1c | 841 | queue_work(host->mmc_omap_wq, &host->cmd_abort_work); |
0fb4723d JL |
842 | return IRQ_HANDLED; |
843 | } | |
844 | ||
f6947514 | 845 | if (end_command && host->cmd) |
730c9b7e | 846 | mmc_omap_cmd_done(host, host->cmd); |
2a50b888 JY |
847 | if (host->data != NULL) { |
848 | if (transfer_error) | |
849 | mmc_omap_xfer_done(host, host->data); | |
850 | else if (end_transfer) | |
851 | mmc_omap_end_of_data(host, host->data); | |
730c9b7e | 852 | } |
730c9b7e CA |
853 | |
854 | return IRQ_HANDLED; | |
855 | } | |
856 | ||
7584d276 | 857 | void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed) |
5a0f3f1f | 858 | { |
7584d276 | 859 | int cover_open; |
5a0f3f1f | 860 | struct mmc_omap_host *host = dev_get_drvdata(dev); |
7584d276 | 861 | struct mmc_omap_slot *slot = host->slots[num]; |
5a0f3f1f | 862 | |
7584d276 | 863 | BUG_ON(num >= host->nr_slots); |
5a0f3f1f JY |
864 | |
865 | /* Other subsystems can call in here before we're initialised. */ | |
7584d276 | 866 | if (host->nr_slots == 0 || !host->slots[num]) |
5a0f3f1f JY |
867 | return; |
868 | ||
7584d276 JL |
869 | cover_open = mmc_omap_cover_is_open(slot); |
870 | if (cover_open != slot->cover_open) { | |
871 | slot->cover_open = cover_open; | |
872 | sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch"); | |
873 | } | |
874 | ||
875 | tasklet_hi_schedule(&slot->cover_tasklet); | |
5a0f3f1f JY |
876 | } |
877 | ||
7584d276 | 878 | static void mmc_omap_cover_timer(unsigned long arg) |
5a0f3f1f JY |
879 | { |
880 | struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg; | |
7584d276 | 881 | tasklet_schedule(&slot->cover_tasklet); |
5a0f3f1f JY |
882 | } |
883 | ||
7584d276 | 884 | static void mmc_omap_cover_handler(unsigned long param) |
5a0f3f1f | 885 | { |
7584d276 JL |
886 | struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param; |
887 | int cover_open = mmc_omap_cover_is_open(slot); | |
5a0f3f1f | 888 | |
7584d276 JL |
889 | mmc_detect_change(slot->mmc, 0); |
890 | if (!cover_open) | |
891 | return; | |
892 | ||
893 | /* | |
894 | * If no card is inserted, we postpone polling until | |
895 | * the cover has been closed. | |
896 | */ | |
897 | if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card)) | |
898 | return; | |
899 | ||
900 | mod_timer(&slot->cover_timer, | |
901 | jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY)); | |
5a0f3f1f JY |
902 | } |
903 | ||
3451c067 RK |
904 | static void mmc_omap_dma_callback(void *priv) |
905 | { | |
906 | struct mmc_omap_host *host = priv; | |
907 | struct mmc_data *data = host->data; | |
908 | ||
909 | /* If we got to the end of DMA, assume everything went well */ | |
910 | data->bytes_xfered += data->blocks * data->blksz; | |
911 | ||
912 | mmc_omap_dma_done(host, data); | |
913 | } | |
914 | ||
730c9b7e CA |
915 | static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req) |
916 | { | |
917 | u16 reg; | |
918 | ||
3342ee8b | 919 | reg = OMAP_MMC_READ(host, SDIO); |
730c9b7e | 920 | reg &= ~(1 << 5); |
3342ee8b | 921 | OMAP_MMC_WRITE(host, SDIO, reg); |
730c9b7e | 922 | /* Set maximum timeout */ |
3342ee8b | 923 | OMAP_MMC_WRITE(host, CTO, 0xff); |
730c9b7e CA |
924 | } |
925 | ||
926 | static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) | |
927 | { | |
b8f9f0e9 | 928 | unsigned int timeout, cycle_ns; |
730c9b7e CA |
929 | u16 reg; |
930 | ||
b8f9f0e9 JY |
931 | cycle_ns = 1000000000 / host->current_slot->fclk_freq; |
932 | timeout = req->data->timeout_ns / cycle_ns; | |
933 | timeout += req->data->timeout_clks; | |
730c9b7e CA |
934 | |
935 | /* Check if we need to use timeout multiplier register */ | |
3342ee8b | 936 | reg = OMAP_MMC_READ(host, SDIO); |
730c9b7e CA |
937 | if (timeout > 0xffff) { |
938 | reg |= (1 << 5); | |
939 | timeout /= 1024; | |
940 | } else | |
941 | reg &= ~(1 << 5); | |
3342ee8b JY |
942 | OMAP_MMC_WRITE(host, SDIO, reg); |
943 | OMAP_MMC_WRITE(host, DTO, timeout); | |
730c9b7e CA |
944 | } |
945 | ||
946 | static void | |
947 | mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) | |
948 | { | |
949 | struct mmc_data *data = req->data; | |
a6c668fb | 950 | int i, use_dma = 1, block_size; |
8292adc6 | 951 | struct scatterlist *sg; |
730c9b7e CA |
952 | unsigned sg_len; |
953 | ||
954 | host->data = data; | |
955 | if (data == NULL) { | |
3342ee8b JY |
956 | OMAP_MMC_WRITE(host, BLEN, 0); |
957 | OMAP_MMC_WRITE(host, NBLK, 0); | |
958 | OMAP_MMC_WRITE(host, BUF, 0); | |
730c9b7e CA |
959 | host->dma_in_use = 0; |
960 | set_cmd_timeout(host, req); | |
961 | return; | |
962 | } | |
963 | ||
a3fd4a1b | 964 | block_size = data->blksz; |
730c9b7e | 965 | |
3342ee8b JY |
966 | OMAP_MMC_WRITE(host, NBLK, data->blocks - 1); |
967 | OMAP_MMC_WRITE(host, BLEN, block_size - 1); | |
730c9b7e CA |
968 | set_data_timeout(host, req); |
969 | ||
970 | /* cope with calling layer confusion; it issues "single | |
971 | * block" writes using multi-block scatterlists. | |
972 | */ | |
973 | sg_len = (data->blocks == 1) ? 1 : data->sg_len; | |
974 | ||
975 | /* Only do DMA for entire blocks */ | |
8292adc6 FF |
976 | for_each_sg(data->sg, sg, sg_len, i) { |
977 | if ((sg->length % block_size) != 0) { | |
a6c668fb JN |
978 | use_dma = 0; |
979 | break; | |
730c9b7e CA |
980 | } |
981 | } | |
982 | ||
983 | host->sg_idx = 0; | |
3451c067 RK |
984 | if (use_dma) { |
985 | enum dma_data_direction dma_data_dir; | |
986 | struct dma_async_tx_descriptor *tx; | |
987 | struct dma_chan *c; | |
988 | u32 burst, *bp; | |
989 | u16 buf; | |
990 | ||
991 | /* | |
992 | * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx | |
993 | * and 24xx. Use 16 or 32 word frames when the | |
994 | * blocksize is at least that large. Blocksize is | |
995 | * usually 512 bytes; but not for some SD reads. | |
996 | */ | |
53db20d1 | 997 | burst = mmc_omap15xx() ? 32 : 64; |
3451c067 RK |
998 | if (burst > data->blksz) |
999 | burst = data->blksz; | |
1000 | ||
1001 | burst >>= 1; | |
1002 | ||
1003 | if (data->flags & MMC_DATA_WRITE) { | |
1004 | c = host->dma_tx; | |
1005 | bp = &host->dma_tx_burst; | |
1006 | buf = 0x0f80 | (burst - 1) << 0; | |
1007 | dma_data_dir = DMA_TO_DEVICE; | |
1008 | } else { | |
1009 | c = host->dma_rx; | |
1010 | bp = &host->dma_rx_burst; | |
1011 | buf = 0x800f | (burst - 1) << 8; | |
1012 | dma_data_dir = DMA_FROM_DEVICE; | |
1013 | } | |
1014 | ||
1015 | if (!c) | |
1016 | goto use_pio; | |
1017 | ||
1018 | /* Only reconfigure if we have a different burst size */ | |
1019 | if (*bp != burst) { | |
1020 | struct dma_slave_config cfg; | |
1021 | ||
1022 | cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA); | |
1023 | cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA); | |
1024 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
1025 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; | |
1026 | cfg.src_maxburst = burst; | |
1027 | cfg.dst_maxburst = burst; | |
1028 | ||
1029 | if (dmaengine_slave_config(c, &cfg)) | |
1030 | goto use_pio; | |
1031 | ||
1032 | *bp = burst; | |
1033 | } | |
1034 | ||
1035 | host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len, | |
1036 | dma_data_dir); | |
1037 | if (host->sg_len == 0) | |
1038 | goto use_pio; | |
1039 | ||
1040 | tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len, | |
1041 | data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
1042 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1043 | if (!tx) | |
1044 | goto use_pio; | |
1045 | ||
1046 | OMAP_MMC_WRITE(host, BUF, buf); | |
1047 | ||
1048 | tx->callback = mmc_omap_dma_callback; | |
1049 | tx->callback_param = host; | |
1050 | dmaengine_submit(tx); | |
1051 | host->brs_received = 0; | |
1052 | host->dma_done = 0; | |
1053 | host->dma_in_use = 1; | |
1054 | return; | |
1055 | } | |
1056 | use_pio: | |
730c9b7e CA |
1057 | |
1058 | /* Revert to PIO? */ | |
4e078fbd RK |
1059 | OMAP_MMC_WRITE(host, BUF, 0x1f1f); |
1060 | host->total_bytes_left = data->blocks * block_size; | |
1061 | host->sg_len = sg_len; | |
1062 | mmc_omap_sg_to_buf(host); | |
1063 | host->dma_in_use = 0; | |
730c9b7e CA |
1064 | } |
1065 | ||
abfbe5f7 JY |
1066 | static void mmc_omap_start_request(struct mmc_omap_host *host, |
1067 | struct mmc_request *req) | |
730c9b7e | 1068 | { |
abfbe5f7 | 1069 | BUG_ON(host->mrq != NULL); |
730c9b7e CA |
1070 | |
1071 | host->mrq = req; | |
1072 | ||
1073 | /* only touch fifo AFTER the controller readies it */ | |
1074 | mmc_omap_prepare_data(host, req); | |
1075 | mmc_omap_start_command(host, req->cmd); | |
3451c067 RK |
1076 | if (host->dma_in_use) { |
1077 | struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ? | |
1078 | host->dma_tx : host->dma_rx; | |
1079 | ||
4e078fbd | 1080 | dma_async_issue_pending(c); |
3451c067 | 1081 | } |
abfbe5f7 JY |
1082 | } |
1083 | ||
1084 | static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req) | |
1085 | { | |
1086 | struct mmc_omap_slot *slot = mmc_priv(mmc); | |
1087 | struct mmc_omap_host *host = slot->host; | |
1088 | unsigned long flags; | |
1089 | ||
1090 | spin_lock_irqsave(&host->slot_lock, flags); | |
1091 | if (host->mmc != NULL) { | |
1092 | BUG_ON(slot->mrq != NULL); | |
1093 | slot->mrq = req; | |
1094 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
1095 | return; | |
1096 | } else | |
1097 | host->mmc = mmc; | |
1098 | spin_unlock_irqrestore(&host->slot_lock, flags); | |
1099 | mmc_omap_select_slot(slot, 1); | |
1100 | mmc_omap_start_request(host, req); | |
730c9b7e CA |
1101 | } |
1102 | ||
65b5b6e5 JY |
1103 | static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on, |
1104 | int vdd) | |
730c9b7e | 1105 | { |
65b5b6e5 | 1106 | struct mmc_omap_host *host; |
730c9b7e | 1107 | |
65b5b6e5 JY |
1108 | host = slot->host; |
1109 | ||
1110 | if (slot->pdata->set_power != NULL) | |
1111 | slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on, | |
1112 | vdd); | |
53db20d1 | 1113 | if (mmc_omap2()) { |
65b5b6e5 JY |
1114 | u16 w; |
1115 | ||
1116 | if (power_on) { | |
1117 | w = OMAP_MMC_READ(host, CON); | |
1118 | OMAP_MMC_WRITE(host, CON, w | (1 << 11)); | |
1119 | } else { | |
1120 | w = OMAP_MMC_READ(host, CON); | |
1121 | OMAP_MMC_WRITE(host, CON, w & ~(1 << 11)); | |
1122 | } | |
730c9b7e CA |
1123 | } |
1124 | } | |
1125 | ||
d3af5abe | 1126 | static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios) |
730c9b7e | 1127 | { |
abfbe5f7 JY |
1128 | struct mmc_omap_slot *slot = mmc_priv(mmc); |
1129 | struct mmc_omap_host *host = slot->host; | |
d3af5abe | 1130 | int func_clk_rate = clk_get_rate(host->fclk); |
730c9b7e | 1131 | int dsor; |
730c9b7e CA |
1132 | |
1133 | if (ios->clock == 0) | |
d3af5abe | 1134 | return 0; |
730c9b7e | 1135 | |
d3af5abe TL |
1136 | dsor = func_clk_rate / ios->clock; |
1137 | if (dsor < 1) | |
1138 | dsor = 1; | |
730c9b7e | 1139 | |
d3af5abe | 1140 | if (func_clk_rate / dsor > ios->clock) |
730c9b7e CA |
1141 | dsor++; |
1142 | ||
d3af5abe TL |
1143 | if (dsor > 250) |
1144 | dsor = 250; | |
d3af5abe | 1145 | |
abfbe5f7 JY |
1146 | slot->fclk_freq = func_clk_rate / dsor; |
1147 | ||
d3af5abe TL |
1148 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
1149 | dsor |= 1 << 15; | |
1150 | ||
1151 | return dsor; | |
1152 | } | |
1153 | ||
1154 | static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) | |
1155 | { | |
abfbe5f7 JY |
1156 | struct mmc_omap_slot *slot = mmc_priv(mmc); |
1157 | struct mmc_omap_host *host = slot->host; | |
1158 | int i, dsor; | |
0807a9b5 | 1159 | int clk_enabled; |
65b5b6e5 JY |
1160 | |
1161 | mmc_omap_select_slot(slot, 0); | |
1162 | ||
0807a9b5 JL |
1163 | dsor = mmc_omap_calc_divisor(mmc, ios); |
1164 | ||
65b5b6e5 JY |
1165 | if (ios->vdd != slot->vdd) |
1166 | slot->vdd = ios->vdd; | |
730c9b7e | 1167 | |
0807a9b5 | 1168 | clk_enabled = 0; |
730c9b7e CA |
1169 | switch (ios->power_mode) { |
1170 | case MMC_POWER_OFF: | |
65b5b6e5 | 1171 | mmc_omap_set_power(slot, 0, ios->vdd); |
730c9b7e CA |
1172 | break; |
1173 | case MMC_POWER_UP: | |
46a6730e | 1174 | /* Cannot touch dsor yet, just power up MMC */ |
65b5b6e5 JY |
1175 | mmc_omap_set_power(slot, 1, ios->vdd); |
1176 | goto exit; | |
46a6730e | 1177 | case MMC_POWER_ON: |
0807a9b5 JL |
1178 | mmc_omap_fclk_enable(host, 1); |
1179 | clk_enabled = 1; | |
c5cb431d | 1180 | dsor |= 1 << 11; |
730c9b7e CA |
1181 | break; |
1182 | } | |
1183 | ||
65b5b6e5 JY |
1184 | if (slot->bus_mode != ios->bus_mode) { |
1185 | if (slot->pdata->set_bus_mode != NULL) | |
1186 | slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id, | |
1187 | ios->bus_mode); | |
1188 | slot->bus_mode = ios->bus_mode; | |
1189 | } | |
730c9b7e CA |
1190 | |
1191 | /* On insanely high arm_per frequencies something sometimes | |
1192 | * goes somehow out of sync, and the POW bit is not being set, | |
1193 | * which results in the while loop below getting stuck. | |
1194 | * Writing to the CON register twice seems to do the trick. */ | |
1195 | for (i = 0; i < 2; i++) | |
3342ee8b | 1196 | OMAP_MMC_WRITE(host, CON, dsor); |
65b5b6e5 | 1197 | slot->saved_con = dsor; |
46a6730e | 1198 | if (ios->power_mode == MMC_POWER_ON) { |
9d7c6eee JL |
1199 | /* worst case at 400kHz, 80 cycles makes 200 microsecs */ |
1200 | int usecs = 250; | |
1201 | ||
730c9b7e | 1202 | /* Send clock cycles, poll completion */ |
3342ee8b JY |
1203 | OMAP_MMC_WRITE(host, IE, 0); |
1204 | OMAP_MMC_WRITE(host, STAT, 0xffff); | |
c5cb431d | 1205 | OMAP_MMC_WRITE(host, CMD, 1 << 7); |
9d7c6eee JL |
1206 | while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) { |
1207 | udelay(1); | |
1208 | usecs--; | |
1209 | } | |
3342ee8b | 1210 | OMAP_MMC_WRITE(host, STAT, 1); |
730c9b7e | 1211 | } |
65b5b6e5 JY |
1212 | |
1213 | exit: | |
0807a9b5 | 1214 | mmc_omap_release_slot(slot, clk_enabled); |
730c9b7e CA |
1215 | } |
1216 | ||
ab7aefd0 | 1217 | static const struct mmc_host_ops mmc_omap_ops = { |
730c9b7e CA |
1218 | .request = mmc_omap_request, |
1219 | .set_ios = mmc_omap_set_ios, | |
730c9b7e CA |
1220 | }; |
1221 | ||
c3be1efd | 1222 | static int mmc_omap_new_slot(struct mmc_omap_host *host, int id) |
730c9b7e | 1223 | { |
abfbe5f7 | 1224 | struct mmc_omap_slot *slot = NULL; |
730c9b7e | 1225 | struct mmc_host *mmc; |
abfbe5f7 JY |
1226 | int r; |
1227 | ||
1228 | mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev); | |
1229 | if (mmc == NULL) | |
1230 | return -ENOMEM; | |
1231 | ||
1232 | slot = mmc_priv(mmc); | |
1233 | slot->host = host; | |
1234 | slot->mmc = mmc; | |
1235 | slot->id = id; | |
1236 | slot->pdata = &host->pdata->slots[id]; | |
1237 | ||
1238 | host->slots[id] = slot; | |
1239 | ||
23af6039 | 1240 | mmc->caps = 0; |
90c62bf0 | 1241 | if (host->pdata->slots[id].wires >= 4) |
b13d1f0f | 1242 | mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_ERASE; |
abfbe5f7 JY |
1243 | |
1244 | mmc->ops = &mmc_omap_ops; | |
1245 | mmc->f_min = 400000; | |
1246 | ||
53db20d1 | 1247 | if (mmc_omap2()) |
abfbe5f7 JY |
1248 | mmc->f_max = 48000000; |
1249 | else | |
1250 | mmc->f_max = 24000000; | |
1251 | if (host->pdata->max_freq) | |
1252 | mmc->f_max = min(host->pdata->max_freq, mmc->f_max); | |
1253 | mmc->ocr_avail = slot->pdata->ocr_mask; | |
1254 | ||
1255 | /* Use scatterlist DMA to reduce per-transfer costs. | |
1256 | * NOTE max_seg_size assumption that small blocks aren't | |
1257 | * normally used (except e.g. for reading SD registers). | |
1258 | */ | |
a36274e0 | 1259 | mmc->max_segs = 32; |
abfbe5f7 JY |
1260 | mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */ |
1261 | mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */ | |
1262 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1263 | mmc->max_seg_size = mmc->max_req_size; | |
1264 | ||
0e5c93e0 JN |
1265 | if (slot->pdata->get_cover_state != NULL) { |
1266 | setup_timer(&slot->cover_timer, mmc_omap_cover_timer, | |
1267 | (unsigned long)slot); | |
1268 | tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler, | |
1269 | (unsigned long)slot); | |
1270 | } | |
1271 | ||
abfbe5f7 JY |
1272 | r = mmc_add_host(mmc); |
1273 | if (r < 0) | |
1274 | goto err_remove_host; | |
1275 | ||
1276 | if (slot->pdata->name != NULL) { | |
1277 | r = device_create_file(&mmc->class_dev, | |
1278 | &dev_attr_slot_name); | |
1279 | if (r < 0) | |
1280 | goto err_remove_host; | |
1281 | } | |
1282 | ||
5a0f3f1f JY |
1283 | if (slot->pdata->get_cover_state != NULL) { |
1284 | r = device_create_file(&mmc->class_dev, | |
1285 | &dev_attr_cover_switch); | |
1286 | if (r < 0) | |
1287 | goto err_remove_slot_name; | |
7584d276 | 1288 | tasklet_schedule(&slot->cover_tasklet); |
5a0f3f1f JY |
1289 | } |
1290 | ||
abfbe5f7 JY |
1291 | return 0; |
1292 | ||
5a0f3f1f JY |
1293 | err_remove_slot_name: |
1294 | if (slot->pdata->name != NULL) | |
1295 | device_remove_file(&mmc->class_dev, &dev_attr_slot_name); | |
abfbe5f7 JY |
1296 | err_remove_host: |
1297 | mmc_remove_host(mmc); | |
1298 | mmc_free_host(mmc); | |
1299 | return r; | |
1300 | } | |
1301 | ||
1302 | static void mmc_omap_remove_slot(struct mmc_omap_slot *slot) | |
1303 | { | |
1304 | struct mmc_host *mmc = slot->mmc; | |
1305 | ||
1306 | if (slot->pdata->name != NULL) | |
1307 | device_remove_file(&mmc->class_dev, &dev_attr_slot_name); | |
5a0f3f1f JY |
1308 | if (slot->pdata->get_cover_state != NULL) |
1309 | device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); | |
1310 | ||
7584d276 JL |
1311 | tasklet_kill(&slot->cover_tasklet); |
1312 | del_timer_sync(&slot->cover_timer); | |
b01a4f1c | 1313 | flush_workqueue(slot->host->mmc_omap_wq); |
abfbe5f7 JY |
1314 | |
1315 | mmc_remove_host(mmc); | |
1316 | mmc_free_host(mmc); | |
1317 | } | |
1318 | ||
c3be1efd | 1319 | static int mmc_omap_probe(struct platform_device *pdev) |
abfbe5f7 JY |
1320 | { |
1321 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; | |
730c9b7e | 1322 | struct mmc_omap_host *host = NULL; |
81ca7034 | 1323 | struct resource *res; |
3451c067 | 1324 | dma_cap_mask_t mask; |
31ee9181 | 1325 | unsigned sig = 0; |
abfbe5f7 | 1326 | int i, ret = 0; |
ce9c1a83 | 1327 | int irq; |
81ca7034 | 1328 | |
abfbe5f7 | 1329 | if (pdata == NULL) { |
81ca7034 JY |
1330 | dev_err(&pdev->dev, "platform data missing\n"); |
1331 | return -ENXIO; | |
1332 | } | |
abfbe5f7 JY |
1333 | if (pdata->nr_slots == 0) { |
1334 | dev_err(&pdev->dev, "no slots\n"); | |
9cb238c0 | 1335 | return -EPROBE_DEFER; |
abfbe5f7 | 1336 | } |
81ca7034 | 1337 | |
64ac16ec JN |
1338 | host = devm_kzalloc(&pdev->dev, sizeof(struct mmc_omap_host), |
1339 | GFP_KERNEL); | |
1340 | if (host == NULL) | |
1341 | return -ENOMEM; | |
1342 | ||
ce9c1a83 | 1343 | irq = platform_get_irq(pdev, 0); |
64ac16ec | 1344 | if (irq < 0) |
ce9c1a83 | 1345 | return -ENXIO; |
730c9b7e | 1346 | |
64ac16ec JN |
1347 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1348 | host->virt_base = devm_ioremap_resource(&pdev->dev, res); | |
1349 | if (IS_ERR(host->virt_base)) | |
1350 | return PTR_ERR(host->virt_base); | |
730c9b7e | 1351 | |
0f602ec7 JL |
1352 | INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work); |
1353 | INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work); | |
1354 | ||
0fb4723d JL |
1355 | INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command); |
1356 | setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer, | |
1357 | (unsigned long) host); | |
eb1860bc | 1358 | |
0807a9b5 JL |
1359 | spin_lock_init(&host->clk_lock); |
1360 | setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host); | |
1361 | ||
730c9b7e | 1362 | spin_lock_init(&host->dma_lock); |
abfbe5f7 JY |
1363 | spin_lock_init(&host->slot_lock); |
1364 | init_waitqueue_head(&host->slot_wq); | |
1365 | ||
abfbe5f7 | 1366 | host->pdata = pdata; |
53db20d1 | 1367 | host->features = host->pdata->slots[0].features; |
abfbe5f7 JY |
1368 | host->dev = &pdev->dev; |
1369 | platform_set_drvdata(pdev, host); | |
1370 | ||
730c9b7e | 1371 | host->id = pdev->id; |
ce9c1a83 | 1372 | host->irq = irq; |
2ca5dc6f | 1373 | host->phys_base = res->start; |
d4a36645 | 1374 | host->iclk = clk_get(&pdev->dev, "ick"); |
64ac16ec JN |
1375 | if (IS_ERR(host->iclk)) |
1376 | return PTR_ERR(host->iclk); | |
d4a36645 | 1377 | clk_enable(host->iclk); |
730c9b7e | 1378 | |
5c9e02b1 | 1379 | host->fclk = clk_get(&pdev->dev, "fck"); |
730c9b7e CA |
1380 | if (IS_ERR(host->fclk)) { |
1381 | ret = PTR_ERR(host->fclk); | |
81ca7034 | 1382 | goto err_free_iclk; |
730c9b7e CA |
1383 | } |
1384 | ||
3451c067 RK |
1385 | dma_cap_zero(mask); |
1386 | dma_cap_set(DMA_SLAVE, mask); | |
1387 | ||
1388 | host->dma_tx_burst = -1; | |
1389 | host->dma_rx_burst = -1; | |
1390 | ||
31ee9181 TL |
1391 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); |
1392 | if (res) | |
1393 | sig = res->start; | |
1394 | host->dma_tx = dma_request_slave_channel_compat(mask, | |
1395 | omap_dma_filter_fn, &sig, &pdev->dev, "tx"); | |
3451c067 RK |
1396 | if (!host->dma_tx) |
1397 | dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n", | |
1398 | sig); | |
31ee9181 TL |
1399 | |
1400 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); | |
1401 | if (res) | |
1402 | sig = res->start; | |
1403 | host->dma_rx = dma_request_slave_channel_compat(mask, | |
1404 | omap_dma_filter_fn, &sig, &pdev->dev, "rx"); | |
3451c067 RK |
1405 | if (!host->dma_rx) |
1406 | dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n", | |
1407 | sig); | |
3451c067 | 1408 | |
abfbe5f7 JY |
1409 | ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); |
1410 | if (ret) | |
3451c067 | 1411 | goto err_free_dma; |
42431acb | 1412 | |
abfbe5f7 JY |
1413 | if (pdata->init != NULL) { |
1414 | ret = pdata->init(&pdev->dev); | |
1415 | if (ret < 0) | |
1416 | goto err_free_irq; | |
1417 | } | |
730c9b7e | 1418 | |
abfbe5f7 | 1419 | host->nr_slots = pdata->nr_slots; |
53db20d1 | 1420 | host->reg_shift = (mmc_omap7xx() ? 1 : 2); |
3caf4140 TL |
1421 | |
1422 | host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0); | |
1423 | if (!host->mmc_omap_wq) | |
1424 | goto err_plat_cleanup; | |
1425 | ||
abfbe5f7 JY |
1426 | for (i = 0; i < pdata->nr_slots; i++) { |
1427 | ret = mmc_omap_new_slot(host, i); | |
1428 | if (ret < 0) { | |
1429 | while (--i >= 0) | |
1430 | mmc_omap_remove_slot(host->slots[i]); | |
730c9b7e | 1431 | |
3caf4140 | 1432 | goto err_destroy_wq; |
730c9b7e | 1433 | } |
730c9b7e CA |
1434 | } |
1435 | ||
730c9b7e CA |
1436 | return 0; |
1437 | ||
3caf4140 TL |
1438 | err_destroy_wq: |
1439 | destroy_workqueue(host->mmc_omap_wq); | |
abfbe5f7 JY |
1440 | err_plat_cleanup: |
1441 | if (pdata->cleanup) | |
1442 | pdata->cleanup(&pdev->dev); | |
1443 | err_free_irq: | |
1444 | free_irq(host->irq, host); | |
3451c067 RK |
1445 | err_free_dma: |
1446 | if (host->dma_tx) | |
1447 | dma_release_channel(host->dma_tx); | |
1448 | if (host->dma_rx) | |
1449 | dma_release_channel(host->dma_rx); | |
81ca7034 JY |
1450 | clk_put(host->fclk); |
1451 | err_free_iclk: | |
e799acb2 LM |
1452 | clk_disable(host->iclk); |
1453 | clk_put(host->iclk); | |
730c9b7e CA |
1454 | return ret; |
1455 | } | |
1456 | ||
6e0ee714 | 1457 | static int mmc_omap_remove(struct platform_device *pdev) |
730c9b7e CA |
1458 | { |
1459 | struct mmc_omap_host *host = platform_get_drvdata(pdev); | |
abfbe5f7 | 1460 | int i; |
730c9b7e | 1461 | |
81ca7034 JY |
1462 | BUG_ON(host == NULL); |
1463 | ||
abfbe5f7 JY |
1464 | for (i = 0; i < host->nr_slots; i++) |
1465 | mmc_omap_remove_slot(host->slots[i]); | |
1466 | ||
1467 | if (host->pdata->cleanup) | |
1468 | host->pdata->cleanup(&pdev->dev); | |
81ca7034 | 1469 | |
d4a36645 | 1470 | mmc_omap_fclk_enable(host, 0); |
49c1d9da | 1471 | free_irq(host->irq, host); |
d4a36645 RK |
1472 | clk_put(host->fclk); |
1473 | clk_disable(host->iclk); | |
1474 | clk_put(host->iclk); | |
730c9b7e | 1475 | |
3451c067 RK |
1476 | if (host->dma_tx) |
1477 | dma_release_channel(host->dma_tx); | |
1478 | if (host->dma_rx) | |
1479 | dma_release_channel(host->dma_rx); | |
1480 | ||
b01a4f1c | 1481 | destroy_workqueue(host->mmc_omap_wq); |
81ca7034 | 1482 | |
730c9b7e CA |
1483 | return 0; |
1484 | } | |
1485 | ||
9cb238c0 TL |
1486 | #if IS_BUILTIN(CONFIG_OF) |
1487 | static const struct of_device_id mmc_omap_match[] = { | |
1488 | { .compatible = "ti,omap2420-mmc", }, | |
1489 | { }, | |
1490 | }; | |
1491 | #endif | |
1492 | ||
730c9b7e | 1493 | static struct platform_driver mmc_omap_driver = { |
b6e0703b | 1494 | .probe = mmc_omap_probe, |
0433c143 | 1495 | .remove = mmc_omap_remove, |
730c9b7e CA |
1496 | .driver = { |
1497 | .name = DRIVER_NAME, | |
9cb238c0 | 1498 | .of_match_table = of_match_ptr(mmc_omap_match), |
730c9b7e CA |
1499 | }, |
1500 | }; | |
1501 | ||
680f1b5b | 1502 | module_platform_driver(mmc_omap_driver); |
730c9b7e CA |
1503 | MODULE_DESCRIPTION("OMAP Multimedia Card driver"); |
1504 | MODULE_LICENSE("GPL"); | |
bc65c724 | 1505 | MODULE_ALIAS("platform:" DRIVER_NAME); |
d36b6910 | 1506 | MODULE_AUTHOR("Juha Yrjölä"); |