]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/mmc/host/omap_hsmmc.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
mmc: omap_hsmmc: Fix Oops in case of data errors
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712 21#include <linux/debugfs.h>
c5c98927 22#include <linux/dmaengine.h>
d900f712 23#include <linux/seq_file.h>
a45c6cb8
MC		 24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
a45c6cb8
MC		 28#include <linux/timer.h>
29#include <linux/clk.h>
46856a68
RN		 30#include <linux/of.h>
31#include <linux/of_gpio.h>
32#include <linux/of_device.h>
3451c067 33#include <linux/omap-dma.h>
a45c6cb8 34#include <linux/mmc/host.h>
13189e78 35#include <linux/mmc/core.h>
93caf8e6 36#include <linux/mmc/mmc.h>
a45c6cb8 37#include <linux/io.h>
db0fefc5
AH		 38#include <linux/gpio.h>
39#include <linux/regulator/consumer.h>
46b76035 40#include <linux/pinctrl/consumer.h>
fa4aa2d4 41#include <linux/pm_runtime.h>
a45c6cb8 42#include <mach/hardware.h>
ce491cf8
TL		 43#include <plat/mmc.h>
44#include <plat/cpu.h>
a45c6cb8
MC		 45
46/* OMAP HSMMC Host Controller Registers */
11dd62a7 47#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 48#define OMAP_HSMMC_CON 0x002C
49#define OMAP_HSMMC_BLK 0x0104
50#define OMAP_HSMMC_ARG 0x0108
51#define OMAP_HSMMC_CMD 0x010C
52#define OMAP_HSMMC_RSP10 0x0110
53#define OMAP_HSMMC_RSP32 0x0114
54#define OMAP_HSMMC_RSP54 0x0118
55#define OMAP_HSMMC_RSP76 0x011C
56#define OMAP_HSMMC_DATA 0x0120
57#define OMAP_HSMMC_HCTL 0x0128
58#define OMAP_HSMMC_SYSCTL 0x012C
59#define OMAP_HSMMC_STAT 0x0130
60#define OMAP_HSMMC_IE 0x0134
61#define OMAP_HSMMC_ISE 0x0138
62#define OMAP_HSMMC_CAPA 0x0140
63
64#define VS18 (1 << 26)
65#define VS30 (1 << 25)
66#define SDVS18 (0x5 << 9)
67#define SDVS30 (0x6 << 9)
eb250826 68#define SDVS33 (0x7 << 9)
1b331e69 69#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 70#define SDVSCLR 0xFFFFF1FF
71#define SDVSDET 0x00000400
72#define AUTOIDLE 0x1
73#define SDBP (1 << 8)
74#define DTO 0xe
75#define ICE 0x1
76#define ICS 0x2
77#define CEN (1 << 2)
78#define CLKD_MASK 0x0000FFC0
79#define CLKD_SHIFT 6
80#define DTO_MASK 0x000F0000
81#define DTO_SHIFT 16
82#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 83#define BWR_ENABLE (1 << 4)
84#define BRR_ENABLE (1 << 5)
93caf8e6 85#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 86#define INIT_STREAM (1 << 1)
87#define DP_SELECT (1 << 21)
88#define DDIR (1 << 4)
89#define DMA_EN 0x1
90#define MSBS (1 << 5)
91#define BCE (1 << 1)
92#define FOUR_BIT (1 << 1)
03b5d924 93#define DDR (1 << 19)
73153010 94#define DW8 (1 << 5)
a45c6cb8
MC		 95#define CC 0x1
96#define TC 0x02
97#define OD 0x1
98#define ERR (1 << 15)
99#define CMD_TIMEOUT (1 << 16)
100#define DATA_TIMEOUT (1 << 20)
101#define CMD_CRC (1 << 17)
102#define DATA_CRC (1 << 21)
103#define CARD_ERR (1 << 28)
104#define STAT_CLEAR 0xFFFFFFFF
105#define INIT_STREAM_CMD 0x00000000
106#define DUAL_VOLT_OCR_BIT 7
107#define SRC (1 << 25)
108#define SRD (1 << 26)
11dd62a7
DK		 109#define SOFTRESET (1 << 1)
110#define RESETDONE (1 << 0)
a45c6cb8 111
fa4aa2d4 112#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8 113#define MMC_TIMEOUT_MS 20
6b206efe
AS		 114#define OMAP_MMC_MIN_CLOCK 400000
115#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 116#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 117
118/*
119 * One controller can have multiple slots, like on some omap boards using
120 * omap.c controller driver. Luckily this is not currently done on any known
121 * omap_hsmmc.c device.
122 */
123#define mmc_slot(host) (host->pdata->slots[host->slot_id])
124
125/*
126 * MMC Host controller read/write API's
127 */
128#define OMAP_HSMMC_READ(base, reg) \
129 __raw_readl((base) + OMAP_HSMMC_##reg)
130
131#define OMAP_HSMMC_WRITE(base, reg, val) \
132 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
133
9782aff8
PF		 134struct omap_hsmmc_next {
135 unsigned int dma_len;
136 s32 cookie;
137};
138
70a3341a 139struct omap_hsmmc_host {
a45c6cb8
MC		 140 struct device *dev;
141 struct mmc_host *mmc;
142 struct mmc_request *mrq;
143 struct mmc_command *cmd;
144 struct mmc_data *data;
145 struct clk *fclk;
a45c6cb8 146 struct clk *dbclk;
db0fefc5
AH		 147 /*
148 * vcc == configured supply
149 * vcc_aux == optional
150 * - MMC1, supply for DAT4..DAT7
151 * - MMC2/MMC2, external level shifter voltage supply, for
152 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
153 */
154 struct regulator *vcc;
155 struct regulator *vcc_aux;
a45c6cb8
MC		 156 void __iomem *base;
157 resource_size_t mapbase;
4dffd7a2 158 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 159 unsigned int dma_len;
0ccd76d4 160 unsigned int dma_sg_idx;
a45c6cb8 161 unsigned char bus_mode;
a3621465 162 unsigned char power_mode;
a45c6cb8
MC		 163 int suspended;
164 int irq;
a45c6cb8 165 int use_dma, dma_ch;
c5c98927
RK		 166 struct dma_chan *tx_chan;
167 struct dma_chan *rx_chan;
a45c6cb8 168 int slot_id;
4a694dc9 169 int response_busy;
11dd62a7 170 int context_loss;
b62f6228
AH		 171 int protect_card;
172 int reqs_blocked;
db0fefc5 173 int use_reg;
b417577d 174 int req_in_progress;
9782aff8 175 struct omap_hsmmc_next next_data;
11dd62a7 176
a45c6cb8
MC		 177 struct omap_mmc_platform_data *pdata;
178};
179
db0fefc5
AH		 180static int omap_hsmmc_card_detect(struct device *dev, int slot)
181{
9ea28ecb
B		 182 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
183 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 184
185 /* NOTE: assumes card detect signal is active-low */
186 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
187}
188
189static int omap_hsmmc_get_wp(struct device *dev, int slot)
190{
9ea28ecb
B		 191 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
192 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 193
194 /* NOTE: assumes write protect signal is active-high */
195 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
196}
197
198static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
199{
9ea28ecb
B		 200 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
201 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 202
203 /* NOTE: assumes card detect signal is active-low */
204 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
205}
206
207#ifdef CONFIG_PM
208
209static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
210{
9ea28ecb
B		 211 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
212 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 213
214 disable_irq(mmc->slots[0].card_detect_irq);
215 return 0;
216}
217
218static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
219{
9ea28ecb
B		 220 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
221 struct omap_mmc_platform_data *mmc = host->pdata;
db0fefc5
AH		 222
223 enable_irq(mmc->slots[0].card_detect_irq);
224 return 0;
225}
226
227#else
228
229#define omap_hsmmc_suspend_cdirq NULL
230#define omap_hsmmc_resume_cdirq NULL
231
232#endif
233
b702b106
AH		 234#ifdef CONFIG_REGULATOR
235
69b07ece 236static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 237 int vdd)
238{
239 struct omap_hsmmc_host *host =
240 platform_get_drvdata(to_platform_device(dev));
241 int ret = 0;
242
243 /*
244 * If we don't see a Vcc regulator, assume it's a fixed
245 * voltage always-on regulator.
246 */
247 if (!host->vcc)
248 return 0;
1f84b71b
RN		 249 /*
250 * With DT, never turn OFF the regulator. This is because
251 * the pbias cell programming support is still missing when
252 * booting with Device tree
253 */
4d048f91 254 if (dev->of_node && !vdd)
1f84b71b 255 return 0;
db0fefc5
AH		 256
257 if (mmc_slot(host).before_set_reg)
258 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
259
260 /*
261 * Assume Vcc regulator is used only to power the card ... OMAP
262 * VDDS is used to power the pins, optionally with a transceiver to
263 * support cards using voltages other than VDDS (1.8V nominal). When a
264 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
265 *
266 * In some cases this regulator won't support enable/disable;
267 * e.g. it's a fixed rail for a WLAN chip.
268 *
269 * In other cases vcc_aux switches interface power. Example, for
270 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
271 * chips/cards need an interface voltage rail too.
272 */
273 if (power_on) {
99fc5131 274 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 275 /* Enable interface voltage rail, if needed */
276 if (ret == 0 && host->vcc_aux) {
277 ret = regulator_enable(host->vcc_aux);
278 if (ret < 0)
99fc5131
LW		 279 ret = mmc_regulator_set_ocr(host->mmc,
280 host->vcc, 0);
db0fefc5
AH		 281 }
282 } else {
99fc5131 283 /* Shut down the rail */
6da20c89
AH		 284 if (host->vcc_aux)
285 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 286 if (!ret) {
287 /* Then proceed to shut down the local regulator */
288 ret = mmc_regulator_set_ocr(host->mmc,
289 host->vcc, 0);
290 }
db0fefc5
AH		 291 }
292
293 if (mmc_slot(host).after_set_reg)
294 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
295
296 return ret;
297}
298
db0fefc5
AH		 299static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
300{
301 struct regulator *reg;
64be9782 302 int ocr_value = 0;
db0fefc5 303
db0fefc5
AH		 304 reg = regulator_get(host->dev, "vmmc");
305 if (IS_ERR(reg)) {
306 dev_dbg(host->dev, "vmmc regulator missing\n");
1fdc90fb 307 return PTR_ERR(reg);
db0fefc5 308 } else {
1fdc90fb 309 mmc_slot(host).set_power = omap_hsmmc_set_power;
db0fefc5 310 host->vcc = reg;
64be9782 311 ocr_value = mmc_regulator_get_ocrmask(reg);
312 if (!mmc_slot(host).ocr_mask) {
313 mmc_slot(host).ocr_mask = ocr_value;
314 } else {
315 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
2cecdf00 316 dev_err(host->dev, "ocrmask %x is not supported\n",
e3f1adb6 317 mmc_slot(host).ocr_mask);
64be9782 318 mmc_slot(host).ocr_mask = 0;
319 return -EINVAL;
320 }
321 }
db0fefc5
AH		 322
323 /* Allow an aux regulator */
324 reg = regulator_get(host->dev, "vmmc_aux");
325 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
326
b1c1df7a
B		 327 /* For eMMC do not power off when not in sleep state */
328 if (mmc_slot(host).no_regulator_off_init)
329 return 0;
db0fefc5
AH		 330 /*
331 * UGLY HACK: workaround regulator framework bugs.
332 * When the bootloader leaves a supply active, it's
333 * initialized with zero usecount ... and we can't
334 * disable it without first enabling it. Until the
335 * framework is fixed, we need a workaround like this
336 * (which is safe for MMC, but not in general).
337 */
e840ce13
AH		 338 if (regulator_is_enabled(host->vcc) > 0 ||
339 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
340 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
341
342 mmc_slot(host).set_power(host->dev, host->slot_id,
343 1, vdd);
344 mmc_slot(host).set_power(host->dev, host->slot_id,
345 0, 0);
db0fefc5
AH		 346 }
347 }
348
349 return 0;
db0fefc5
AH		 350}
351
352static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
353{
354 regulator_put(host->vcc);
355 regulator_put(host->vcc_aux);
356 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 357}
358
b702b106
AH		 359static inline int omap_hsmmc_have_reg(void)
360{
361 return 1;
362}
363
364#else
365
366static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
367{
368 return -EINVAL;
369}
370
371static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
372{
373}
374
375static inline int omap_hsmmc_have_reg(void)
376{
377 return 0;
378}
379
380#endif
381
382static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
383{
384 int ret;
385
386 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 387 if (pdata->slots[0].cover)
388 pdata->slots[0].get_cover_state =
389 omap_hsmmc_get_cover_state;
390 else
391 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
392 pdata->slots[0].card_detect_irq =
393 gpio_to_irq(pdata->slots[0].switch_pin);
394 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
395 if (ret)
396 return ret;
397 ret = gpio_direction_input(pdata->slots[0].switch_pin);
398 if (ret)
399 goto err_free_sp;
400 } else
401 pdata->slots[0].switch_pin = -EINVAL;
402
403 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
404 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
405 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
406 if (ret)
407 goto err_free_cd;
408 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
409 if (ret)
410 goto err_free_wp;
411 } else
412 pdata->slots[0].gpio_wp = -EINVAL;
413
414 return 0;
415
416err_free_wp:
417 gpio_free(pdata->slots[0].gpio_wp);
418err_free_cd:
419 if (gpio_is_valid(pdata->slots[0].switch_pin))
420err_free_sp:
421 gpio_free(pdata->slots[0].switch_pin);
422 return ret;
423}
424
425static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
426{
427 if (gpio_is_valid(pdata->slots[0].gpio_wp))
428 gpio_free(pdata->slots[0].gpio_wp);
429 if (gpio_is_valid(pdata->slots[0].switch_pin))
430 gpio_free(pdata->slots[0].switch_pin);
431}
432
e0c7f99b
AS		 433/*
434 * Start clock to the card
435 */
436static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
437{
438 OMAP_HSMMC_WRITE(host->base, SYSCTL,
439 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
440}
441
a45c6cb8
MC		 442/*
443 * Stop clock to the card
444 */
70a3341a 445static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 446{
447 OMAP_HSMMC_WRITE(host->base, SYSCTL,
448 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
449 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
7122bbb0 450 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
a45c6cb8
MC		 451}
452
93caf8e6
AH		 453static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
454 struct mmc_command *cmd)
b417577d
AH		 455{
456 unsigned int irq_mask;
457
458 if (host->use_dma)
459 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
460 else
461 irq_mask = INT_EN_MASK;
462
93caf8e6
AH		 463 /* Disable timeout for erases */
464 if (cmd->opcode == MMC_ERASE)
465 irq_mask &= ~DTO_ENABLE;
466
b417577d
AH		 467 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
468 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
469 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
470}
471
472static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
473{
474 OMAP_HSMMC_WRITE(host->base, ISE, 0);
475 OMAP_HSMMC_WRITE(host->base, IE, 0);
476 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
477}
478
ac330f44 479/* Calculate divisor for the given clock frequency */
d83b6e03 480static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 481{
482 u16 dsor = 0;
483
484 if (ios->clock) {
d83b6e03 485 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ac330f44
AS		 486 if (dsor > 250)
487 dsor = 250;
488 }
489
490 return dsor;
491}
492
5934df2f
AS		 493static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
494{
495 struct mmc_ios *ios = &host->mmc->ios;
496 unsigned long regval;
497 unsigned long timeout;
498
8986d31b 499 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
5934df2f
AS		 500
501 omap_hsmmc_stop_clock(host);
502
503 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
504 regval = regval & ~(CLKD_MASK | DTO_MASK);
d83b6e03 505 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
5934df2f
AS		 506 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
507 OMAP_HSMMC_WRITE(host->base, SYSCTL,
508 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
509
510 /* Wait till the ICS bit is set */
511 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
512 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
513 && time_before(jiffies, timeout))
514 cpu_relax();
515
516 omap_hsmmc_start_clock(host);
517}
518
3796fb8a
AS		 519static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
520{
521 struct mmc_ios *ios = &host->mmc->ios;
522 u32 con;
523
524 con = OMAP_HSMMC_READ(host->base, CON);
03b5d924
B		 525 if (ios->timing == MMC_TIMING_UHS_DDR50)
526 con |= DDR; /* configure in DDR mode */
527 else
528 con &= ~DDR;
3796fb8a
AS		 529 switch (ios->bus_width) {
530 case MMC_BUS_WIDTH_8:
531 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
532 break;
533 case MMC_BUS_WIDTH_4:
534 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
535 OMAP_HSMMC_WRITE(host->base, HCTL,
536 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
537 break;
538 case MMC_BUS_WIDTH_1:
539 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
540 OMAP_HSMMC_WRITE(host->base, HCTL,
541 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
542 break;
543 }
544}
545
546static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
547{
548 struct mmc_ios *ios = &host->mmc->ios;
549 u32 con;
550
551 con = OMAP_HSMMC_READ(host->base, CON);
552 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
553 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
554 else
555 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
556}
557
11dd62a7
DK		 558#ifdef CONFIG_PM
559
560/*
561 * Restore the MMC host context, if it was lost as result of a
562 * power state change.
563 */
70a3341a 564static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 565{
566 struct mmc_ios *ios = &host->mmc->ios;
567 struct omap_mmc_platform_data *pdata = host->pdata;
568 int context_loss = 0;
3796fb8a 569 u32 hctl, capa;
11dd62a7
DK		 570 unsigned long timeout;
571
572 if (pdata->get_context_loss_count) {
573 context_loss = pdata->get_context_loss_count(host->dev);
574 if (context_loss < 0)
575 return 1;
576 }
577
578 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
579 context_loss == host->context_loss ? "not " : "");
580 if (host->context_loss == context_loss)
581 return 1;
582
6c31b215
V		 583 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE)
584 return 1;
11dd62a7 585
c2200efb 586 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 587 if (host->power_mode != MMC_POWER_OFF &&
588 (1 << ios->vdd) <= MMC_VDD_23_24)
589 hctl = SDVS18;
590 else
591 hctl = SDVS30;
592 capa = VS30 | VS18;
593 } else {
594 hctl = SDVS18;
595 capa = VS18;
596 }
597
598 OMAP_HSMMC_WRITE(host->base, HCTL,
599 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
600
601 OMAP_HSMMC_WRITE(host->base, CAPA,
602 OMAP_HSMMC_READ(host->base, CAPA) | capa);
603
604 OMAP_HSMMC_WRITE(host->base, HCTL,
605 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
606
607 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
608 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
609 && time_before(jiffies, timeout))
610 ;
611
b417577d 612 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 613
614 /* Do not initialize card-specific things if the power is off */
615 if (host->power_mode == MMC_POWER_OFF)
616 goto out;
617
3796fb8a 618 omap_hsmmc_set_bus_width(host);
11dd62a7 619
5934df2f 620 omap_hsmmc_set_clock(host);
11dd62a7 621
3796fb8a
AS		 622 omap_hsmmc_set_bus_mode(host);
623
11dd62a7
DK		 624out:
625 host->context_loss = context_loss;
626
627 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
628 return 0;
629}
630
631/*
632 * Save the MMC host context (store the number of power state changes so far).
633 */
70a3341a 634static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 635{
636 struct omap_mmc_platform_data *pdata = host->pdata;
637 int context_loss;
638
639 if (pdata->get_context_loss_count) {
640 context_loss = pdata->get_context_loss_count(host->dev);
641 if (context_loss < 0)
642 return;
643 host->context_loss = context_loss;
644 }
645}
646
647#else
648
70a3341a 649static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 650{
651 return 0;
652}
653
70a3341a 654static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 655{
656}
657
658#endif
659
a45c6cb8
MC		 660/*
661 * Send init stream sequence to card
662 * before sending IDLE command
663 */
70a3341a 664static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 665{
666 int reg = 0;
667 unsigned long timeout;
668
b62f6228
AH		 669 if (host->protect_card)
670 return;
671
a45c6cb8 672 disable_irq(host->irq);
b417577d
AH		 673
674 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 675 OMAP_HSMMC_WRITE(host->base, CON,
676 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
677 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
678
679 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
680 while ((reg != CC) && time_before(jiffies, timeout))
681 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
682
683 OMAP_HSMMC_WRITE(host->base, CON,
684 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 685
686 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
687 OMAP_HSMMC_READ(host->base, STAT);
688
a45c6cb8
MC		 689 enable_irq(host->irq);
690}
691
692static inline
70a3341a 693int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 694{
695 int r = 1;
696
191d1f1d
DK		 697 if (mmc_slot(host).get_cover_state)
698 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 699 return r;
700}
701
702static ssize_t
70a3341a 703omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 704 char *buf)
705{
706 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 707 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 708
70a3341a
DK		 709 return sprintf(buf, "%s\n",
710 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 711}
712
70a3341a 713static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 714
715static ssize_t
70a3341a 716omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 717 char *buf)
718{
719 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 720 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 721
191d1f1d 722 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 723}
724
70a3341a 725static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 726
727/*
728 * Configure the response type and send the cmd.
729 */
730static void
70a3341a 731omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 732 struct mmc_data *data)
733{
734 int cmdreg = 0, resptype = 0, cmdtype = 0;
735
8986d31b 736 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
a45c6cb8
MC		 737 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
738 host->cmd = cmd;
739
93caf8e6 740 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 741
4a694dc9 742 host->response_busy = 0;
a45c6cb8
MC		 743 if (cmd->flags & MMC_RSP_PRESENT) {
744 if (cmd->flags & MMC_RSP_136)
745 resptype = 1;
4a694dc9
AH		 746 else if (cmd->flags & MMC_RSP_BUSY) {
747 resptype = 3;
748 host->response_busy = 1;
749 } else
a45c6cb8
MC		 750 resptype = 2;
751 }
752
753 /*
754 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
755 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
756 * a val of 0x3, rest 0x0.
757 */
758 if (cmd == host->mrq->stop)
759 cmdtype = 0x3;
760
761 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
762
763 if (data) {
764 cmdreg |= DP_SELECT | MSBS | BCE;
765 if (data->flags & MMC_DATA_READ)
766 cmdreg |= DDIR;
767 else
768 cmdreg &= ~(DDIR);
769 }
770
771 if (host->use_dma)
772 cmdreg |= DMA_EN;
773
b417577d 774 host->req_in_progress = 1;
4dffd7a2 775
a45c6cb8
MC		 776 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
777 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
778}
779
0ccd76d4 780static int
70a3341a 781omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 782{
783 if (data->flags & MMC_DATA_WRITE)
784 return DMA_TO_DEVICE;
785 else
786 return DMA_FROM_DEVICE;
787}
788
c5c98927
RK		 789static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
790 struct mmc_data *data)
791{
792 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
793}
794
b417577d
AH		 795static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
796{
797 int dma_ch;
31463b14 798 unsigned long flags;
b417577d 799
31463b14 800 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 801 host->req_in_progress = 0;
802 dma_ch = host->dma_ch;
31463b14 803 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 804
805 omap_hsmmc_disable_irq(host);
806 /* Do not complete the request if DMA is still in progress */
807 if (mrq->data && host->use_dma && dma_ch != -1)
808 return;
809 host->mrq = NULL;
810 mmc_request_done(host->mmc, mrq);
811}
812
a45c6cb8
MC		 813/*
814 * Notify the transfer complete to MMC core
815 */
816static void
70a3341a 817omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 818{
4a694dc9
AH		 819 if (!data) {
820 struct mmc_request *mrq = host->mrq;
821
23050103
AH		 822 /* TC before CC from CMD6 - don't know why, but it happens */
823 if (host->cmd && host->cmd->opcode == 6 &&
824 host->response_busy) {
825 host->response_busy = 0;
826 return;
827 }
828
b417577d 829 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 830 return;
831 }
832
a45c6cb8
MC		 833 host->data = NULL;
834
a45c6cb8
MC		 835 if (!data->error)
836 data->bytes_xfered += data->blocks * (data->blksz);
837 else
838 data->bytes_xfered = 0;
839
fe852273 840 if (!data->stop) {
b417577d 841 omap_hsmmc_request_done(host, data->mrq);
fe852273 842 return;
a45c6cb8 843 }
fe852273 844 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 845}
846
847/*
848 * Notify the core about command completion
849 */
850static void
70a3341a 851omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 852{
853 host->cmd = NULL;
854
855 if (cmd->flags & MMC_RSP_PRESENT) {
856 if (cmd->flags & MMC_RSP_136) {
857 /* response type 2 */
858 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
859 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
860 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
861 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
862 } else {
863 /* response types 1, 1b, 3, 4, 5, 6 */
864 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
865 }
866 }
b417577d
AH		 867 if ((host->data == NULL && !host->response_busy) || cmd->error)
868 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 869}
870
871/*
872 * DMA clean up for command errors
873 */
70a3341a 874static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 875{
b417577d 876 int dma_ch;
31463b14 877 unsigned long flags;
b417577d 878
82788ff5 879 host->data->error = errno;
a45c6cb8 880
31463b14 881 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 882 dma_ch = host->dma_ch;
883 host->dma_ch = -1;
31463b14 884 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 885
886 if (host->use_dma && dma_ch != -1) {
c5c98927
RK		 887 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
888
889 dmaengine_terminate_all(chan);
890 dma_unmap_sg(chan->device->dev,
891 host->data->sg, host->data->sg_len,
70a3341a 892 omap_hsmmc_get_dma_dir(host, host->data));
c5c98927 893
053bf34f 894 host->data->host_cookie = 0;
a45c6cb8
MC		 895 }
896 host->data = NULL;
a45c6cb8
MC		 897}
898
899/*
900 * Readable error output
901 */
902#ifdef CONFIG_MMC_DEBUG
699b958b 903static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 904{
905 /* --- means reserved bit without definition at documentation */
70a3341a 906 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 907 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
908 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
909 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
910 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 911 };
912 char res[256];
913 char *buf = res;
914 int len, i;
915
916 len = sprintf(buf, "MMC IRQ 0x%x :", status);
917 buf += len;
918
70a3341a 919 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 920 if (status & (1 << i)) {
70a3341a 921 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 922 buf += len;
923 }
924
8986d31b 925 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
a45c6cb8 926}
699b958b
AH		 927#else
928static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
929 u32 status)
930{
931}
a45c6cb8
MC		 932#endif /* CONFIG_MMC_DEBUG */
933
3ebf74b1
JP		 934/*
935 * MMC controller internal state machines reset
936 *
937 * Used to reset command or data internal state machines, using respectively
938 * SRC or SRD bit of SYSCTL register
939 * Can be called from interrupt context
940 */
70a3341a
DK		 941static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
942 unsigned long bit)
3ebf74b1
JP		 943{
944 unsigned long i = 0;
945 unsigned long limit = (loops_per_jiffy *
946 msecs_to_jiffies(MMC_TIMEOUT_MS));
947
948 OMAP_HSMMC_WRITE(host->base, SYSCTL,
949 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
950
07ad64b6
MC		 951 /*
952 * OMAP4 ES2 and greater has an updated reset logic.
953 * Monitor a 0->1 transition first
954 */
955 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 956 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 957 && (i++ < limit))
958 cpu_relax();
959 }
960 i = 0;
961
3ebf74b1
JP		 962 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
963 (i++ < limit))
964 cpu_relax();
965
966 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
967 dev_err(mmc_dev(host->mmc),
968 "Timeout waiting on controller reset in %s\n",
969 __func__);
970}
a45c6cb8 971
25e1897b
B		 972static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
973 int err, int end_cmd)
ae4bf788
V		 974{
975 omap_hsmmc_reset_controller_fsm(host, SRC);
25e1897b
B		 976 if (end_cmd) {
977 if (host->cmd)
978 host->cmd->error = err;
979 }
ae4bf788
V		 980
981 if (host->data) {
982 omap_hsmmc_reset_controller_fsm(host, SRD);
983 omap_hsmmc_dma_cleanup(host, err);
984 }
985
986}
987
b417577d 988static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 989{
a45c6cb8 990 struct mmc_data *data;
b417577d
AH		 991 int end_cmd = 0, end_trans = 0;
992
a45c6cb8 993 data = host->data;
8986d31b 994 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
a45c6cb8
MC		 995
996 if (status & ERR) {
699b958b 997 omap_hsmmc_dbg_report_irq(host, status);
25e1897b
B		 998
999 if (status & (CMD_TIMEOUT | CMD_CRC))
1000 end_cmd = 1;
ae4bf788 1001 if (status & (CMD_TIMEOUT | DATA_TIMEOUT))
25e1897b 1002 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
ae4bf788 1003 else if (status & (CMD_CRC | DATA_CRC))
25e1897b 1004 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
ae4bf788 1005
ae4bf788 1006 if (host->data || host->response_busy) {
25e1897b 1007 end_trans = !end_cmd;
ae4bf788 1008 host->response_busy = 0;
a45c6cb8
MC		 1009 }
1010 }
1011
a8fe29d8 1012 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1013 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1014 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1015 omap_hsmmc_xfer_done(host, data);
b417577d 1016}
a45c6cb8 1017
b417577d
AH		 1018/*
1019 * MMC controller IRQ handler
1020 */
1021static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1022{
1023 struct omap_hsmmc_host *host = dev_id;
1024 int status;
1025
1026 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1027 while (status & INT_EN_MASK && host->req_in_progress) {
b417577d 1028 omap_hsmmc_do_irq(host, status);
1f6b9fa4 1029
b417577d 1030 /* Flush posted write */
1f6b9fa4 1031 OMAP_HSMMC_WRITE(host->base, STAT, status);
b417577d 1032 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1033 }
4dffd7a2 1034
a45c6cb8
MC		 1035 return IRQ_HANDLED;
1036}
1037
70a3341a 1038static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1039{
1040 unsigned long i;
1041
1042 OMAP_HSMMC_WRITE(host->base, HCTL,
1043 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1044 for (i = 0; i < loops_per_jiffy; i++) {
1045 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1046 break;
1047 cpu_relax();
1048 }
1049}
1050
a45c6cb8 1051/*
eb250826
DB		 1052 * Switch MMC interface voltage ... only relevant for MMC1.
1053 *
1054 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1055 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1056 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1057 */
70a3341a 1058static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1059{
1060 u32 reg_val = 0;
1061 int ret;
1062
1063 /* Disable the clocks */
fa4aa2d4 1064 pm_runtime_put_sync(host->dev);
cd03d9a8 1065 if (host->dbclk)
94c18149 1066 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1067
1068 /* Turn the power off */
1069 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1070
1071 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1072 if (!ret)
1073 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1074 vdd);
fa4aa2d4 1075 pm_runtime_get_sync(host->dev);
cd03d9a8 1076 if (host->dbclk)
94c18149 1077 clk_prepare_enable(host->dbclk);
2bec0893 1078
a45c6cb8
MC		 1079 if (ret != 0)
1080 goto err;
1081
a45c6cb8
MC		 1082 OMAP_HSMMC_WRITE(host->base, HCTL,
1083 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1084 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1085
a45c6cb8
MC		 1086 /*
1087 * If a MMC dual voltage card is detected, the set_ios fn calls
1088 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1089 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1090 *
eb250826
DB		 1091 * Cope with a bit of slop in the range ... per data sheets:
1092 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1093 * but recommended values are 1.71V to 1.89V
1094 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1095 * but recommended values are 2.7V to 3.3V
1096 *
1097 * Board setup code shouldn't permit anything very out-of-range.
1098 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1099 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1100 */
eb250826 1101 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1102 reg_val |= SDVS18;
eb250826
DB		 1103 else
1104 reg_val |= SDVS30;
a45c6cb8
MC		 1105
1106 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1107 set_sd_bus_power(host);
a45c6cb8
MC		 1108
1109 return 0;
1110err:
1111 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1112 return ret;
1113}
1114
b62f6228
AH		 1115/* Protect the card while the cover is open */
1116static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1117{
1118 if (!mmc_slot(host).get_cover_state)
1119 return;
1120
1121 host->reqs_blocked = 0;
1122 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1123 if (host->protect_card) {
2cecdf00 1124 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1125 "card is now accessible\n",
1126 mmc_hostname(host->mmc));
1127 host->protect_card = 0;
1128 }
1129 } else {
1130 if (!host->protect_card) {
2cecdf00 1131 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1132 "card is now inaccessible\n",
1133 mmc_hostname(host->mmc));
1134 host->protect_card = 1;
1135 }
1136 }
1137}
1138
a45c6cb8 1139/*
7efab4f3 1140 * irq handler to notify the core about card insertion/removal
a45c6cb8 1141 */
7efab4f3 1142static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
a45c6cb8 1143{
7efab4f3 1144 struct omap_hsmmc_host *host = dev_id;
249d0fa9 1145 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1146 int carddetect;
1147
1148 if (host->suspended)
7efab4f3 1149 return IRQ_HANDLED;
a6b2240d
AH		 1150
1151 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1152
191d1f1d 1153 if (slot->card_detect)
db0fefc5 1154 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1155 else {
1156 omap_hsmmc_protect_card(host);
a6b2240d 1157 carddetect = -ENOSYS;
b62f6228 1158 }
a45c6cb8 1159
cdeebadd 1160 if (carddetect)
a45c6cb8 1161 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1162 else
a45c6cb8 1163 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1164 return IRQ_HANDLED;
1165}
1166
c5c98927 1167static void omap_hsmmc_dma_callback(void *param)
a45c6cb8 1168{
c5c98927
RK		 1169 struct omap_hsmmc_host *host = param;
1170 struct dma_chan *chan;
770d7432 1171 struct mmc_data *data;
c5c98927 1172 int req_in_progress;
a45c6cb8 1173
c5c98927 1174 spin_lock_irq(&host->irq_lock);
b417577d 1175 if (host->dma_ch < 0) {
c5c98927 1176 spin_unlock_irq(&host->irq_lock);
a45c6cb8 1177 return;
b417577d 1178 }
a45c6cb8 1179
770d7432 1180 data = host->mrq->data;
c5c98927 1181 chan = omap_hsmmc_get_dma_chan(host, data);
9782aff8 1182 if (!data->host_cookie)
c5c98927
RK		 1183 dma_unmap_sg(chan->device->dev,
1184 data->sg, data->sg_len,
9782aff8 1185 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1186
1187 req_in_progress = host->req_in_progress;
a45c6cb8 1188 host->dma_ch = -1;
c5c98927 1189 spin_unlock_irq(&host->irq_lock);
b417577d
AH		 1190
1191 /* If DMA has finished after TC, complete the request */
1192 if (!req_in_progress) {
1193 struct mmc_request *mrq = host->mrq;
1194
1195 host->mrq = NULL;
1196 mmc_request_done(host->mmc, mrq);
1197 }
a45c6cb8
MC		 1198}
1199
9782aff8
PF		 1200static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1201 struct mmc_data *data,
c5c98927 1202 struct omap_hsmmc_next *next,
26b88520 1203 struct dma_chan *chan)
9782aff8
PF		 1204{
1205 int dma_len;
1206
1207 if (!next && data->host_cookie &&
1208 data->host_cookie != host->next_data.cookie) {
2cecdf00 1209 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1210 " host->next_data.cookie %d\n",
1211 __func__, data->host_cookie, host->next_data.cookie);
1212 data->host_cookie = 0;
1213 }
1214
1215 /* Check if next job is already prepared */
1216 if (next ||
1217 (!next && data->host_cookie != host->next_data.cookie)) {
26b88520 1218 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
9782aff8
PF		 1219 omap_hsmmc_get_dma_dir(host, data));
1220
1221 } else {
1222 dma_len = host->next_data.dma_len;
1223 host->next_data.dma_len = 0;
1224 }
1225
1226
1227 if (dma_len == 0)
1228 return -EINVAL;
1229
1230 if (next) {
1231 next->dma_len = dma_len;
1232 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1233 } else
1234 host->dma_len = dma_len;
1235
1236 return 0;
1237}
1238
a45c6cb8
MC		 1239/*
1240 * Routine to configure and start DMA for the MMC card
1241 */
70a3341a
DK		 1242static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1243 struct mmc_request *req)
a45c6cb8 1244{
26b88520
RK		 1245 struct dma_slave_config cfg;
1246 struct dma_async_tx_descriptor *tx;
1247 int ret = 0, i;
a45c6cb8 1248 struct mmc_data *data = req->data;
c5c98927 1249 struct dma_chan *chan;
a45c6cb8 1250
0ccd76d4 1251 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1252 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1253 struct scatterlist *sgl;
1254
1255 sgl = data->sg + i;
1256 if (sgl->length % data->blksz)
1257 return -EINVAL;
1258 }
1259 if ((data->blksz % 4) != 0)
1260 /* REVISIT: The MMC buffer increments only when MSB is written.
1261 * Return error for blksz which is non multiple of four.
1262 */
1263 return -EINVAL;
1264
b417577d 1265 BUG_ON(host->dma_ch != -1);
a45c6cb8 1266
c5c98927 1267 chan = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1268
26b88520
RK		 1269 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1270 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1271 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1272 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1273 cfg.src_maxburst = data->blksz / 4;
1274 cfg.dst_maxburst = data->blksz / 4;
c5c98927 1275
26b88520
RK		 1276 ret = dmaengine_slave_config(chan, &cfg);
1277 if (ret)
a45c6cb8 1278 return ret;
c5c98927 1279
26b88520 1280 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
9782aff8
PF		 1281 if (ret)
1282 return ret;
a45c6cb8 1283
26b88520
RK		 1284 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1285 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1286 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1287 if (!tx) {
1288 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1289 /* FIXME: cleanup */
1290 return -1;
1291 }
a45c6cb8 1292
26b88520
RK		 1293 tx->callback = omap_hsmmc_dma_callback;
1294 tx->callback_param = host;
a45c6cb8 1295
26b88520
RK		 1296 /* Does not fail */
1297 dmaengine_submit(tx);
c5c98927 1298
26b88520 1299 host->dma_ch = 1;
c5c98927 1300
26b88520 1301 dma_async_issue_pending(chan);
a45c6cb8 1302
a45c6cb8
MC		 1303 return 0;
1304}
1305
70a3341a 1306static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1307 unsigned int timeout_ns,
1308 unsigned int timeout_clks)
a45c6cb8
MC		 1309{
1310 unsigned int timeout, cycle_ns;
1311 uint32_t reg, clkd, dto = 0;
1312
1313 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1314 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1315 if (clkd == 0)
1316 clkd = 1;
1317
1318 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1319 timeout = timeout_ns / cycle_ns;
1320 timeout += timeout_clks;
a45c6cb8
MC		 1321 if (timeout) {
1322 while ((timeout & 0x80000000) == 0) {
1323 dto += 1;
1324 timeout <<= 1;
1325 }
1326 dto = 31 - dto;
1327 timeout <<= 1;
1328 if (timeout && dto)
1329 dto += 1;
1330 if (dto >= 13)
1331 dto -= 13;
1332 else
1333 dto = 0;
1334 if (dto > 14)
1335 dto = 14;
1336 }
1337
1338 reg &= ~DTO_MASK;
1339 reg |= dto << DTO_SHIFT;
1340 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1341}
1342
1343/*
1344 * Configure block length for MMC/SD cards and initiate the transfer.
1345 */
1346static int
70a3341a 1347omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1348{
1349 int ret;
1350 host->data = req->data;
1351
1352 if (req->data == NULL) {
a45c6cb8 1353 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1354 /*
1355 * Set an arbitrary 100ms data timeout for commands with
1356 * busy signal.
1357 */
1358 if (req->cmd->flags & MMC_RSP_BUSY)
1359 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1360 return 0;
1361 }
1362
1363 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1364 | (req->data->blocks << 16));
e2bf08d6 1365 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1366
a45c6cb8 1367 if (host->use_dma) {
70a3341a 1368 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1369 if (ret != 0) {
1370 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1371 return ret;
1372 }
1373 }
1374 return 0;
1375}
1376
9782aff8
PF		 1377static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1378 int err)
1379{
1380 struct omap_hsmmc_host *host = mmc_priv(mmc);
1381 struct mmc_data *data = mrq->data;
1382
26b88520 1383 if (host->use_dma && data->host_cookie) {
c5c98927 1384 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1385
26b88520
RK		 1386 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1387 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1388 data->host_cookie = 0;
1389 }
1390}
1391
1392static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1393 bool is_first_req)
1394{
1395 struct omap_hsmmc_host *host = mmc_priv(mmc);
1396
1397 if (mrq->data->host_cookie) {
1398 mrq->data->host_cookie = 0;
1399 return ;
1400 }
1401
c5c98927
RK		 1402 if (host->use_dma) {
1403 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
c5c98927 1404
9782aff8 1405 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
26b88520 1406 &host->next_data, c))
9782aff8 1407 mrq->data->host_cookie = 0;
c5c98927 1408 }
9782aff8
PF		 1409}
1410
a45c6cb8
MC		 1411/*
1412 * Request function. for read/write operation
1413 */
70a3341a 1414static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1415{
70a3341a 1416 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1417 int err;
a45c6cb8 1418
b417577d
AH		 1419 BUG_ON(host->req_in_progress);
1420 BUG_ON(host->dma_ch != -1);
1421 if (host->protect_card) {
1422 if (host->reqs_blocked < 3) {
1423 /*
1424 * Ensure the controller is left in a consistent
1425 * state by resetting the command and data state
1426 * machines.
1427 */
1428 omap_hsmmc_reset_controller_fsm(host, SRD);
1429 omap_hsmmc_reset_controller_fsm(host, SRC);
1430 host->reqs_blocked += 1;
1431 }
1432 req->cmd->error = -EBADF;
1433 if (req->data)
1434 req->data->error = -EBADF;
1435 req->cmd->retries = 0;
1436 mmc_request_done(mmc, req);
1437 return;
1438 } else if (host->reqs_blocked)
1439 host->reqs_blocked = 0;
a45c6cb8
MC		 1440 WARN_ON(host->mrq != NULL);
1441 host->mrq = req;
70a3341a 1442 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1443 if (err) {
1444 req->cmd->error = err;
1445 if (req->data)
1446 req->data->error = err;
1447 host->mrq = NULL;
1448 mmc_request_done(mmc, req);
1449 return;
1450 }
1451
70a3341a 1452 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1453}
1454
a45c6cb8 1455/* Routine to configure clock values. Exposed API to core */
70a3341a 1456static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1457{
70a3341a 1458 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1459 int do_send_init_stream = 0;
a45c6cb8 1460
fa4aa2d4 1461 pm_runtime_get_sync(host->dev);
5e2ea617 1462
a3621465
AH		 1463 if (ios->power_mode != host->power_mode) {
1464 switch (ios->power_mode) {
1465 case MMC_POWER_OFF:
1466 mmc_slot(host).set_power(host->dev, host->slot_id,
1467 0, 0);
1468 break;
1469 case MMC_POWER_UP:
1470 mmc_slot(host).set_power(host->dev, host->slot_id,
1471 1, ios->vdd);
1472 break;
1473 case MMC_POWER_ON:
1474 do_send_init_stream = 1;
1475 break;
1476 }
1477 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1478 }
1479
dd498eff
DK		 1480 /* FIXME: set registers based only on changes to ios */
1481
3796fb8a 1482 omap_hsmmc_set_bus_width(host);
a45c6cb8 1483
4621d5f8 1484 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1485 /* Only MMC1 can interface at 3V without some flavor
1486 * of external transceiver; but they all handle 1.8V.
1487 */
a45c6cb8 1488 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1f84b71b
RN		 1489 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1490 /*
1491 * With pbias cell programming missing, this
1492 * can't be allowed when booting with device
1493 * tree.
1494 */
4d048f91 1495 !host->dev->of_node) {
a45c6cb8
MC		 1496 /*
1497 * The mmc_select_voltage fn of the core does
1498 * not seem to set the power_mode to
1499 * MMC_POWER_UP upon recalculating the voltage.
1500 * vdd 1.8v.
1501 */
70a3341a
DK		 1502 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1503 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1504 "Switch operation failed\n");
1505 }
1506 }
1507
5934df2f 1508 omap_hsmmc_set_clock(host);
a45c6cb8 1509
a3621465 1510 if (do_send_init_stream)
a45c6cb8
MC		 1511 send_init_stream(host);
1512
3796fb8a 1513 omap_hsmmc_set_bus_mode(host);
5e2ea617 1514
fa4aa2d4 1515 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1516}
1517
1518static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1519{
70a3341a 1520 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1521
191d1f1d 1522 if (!mmc_slot(host).card_detect)
a45c6cb8 1523 return -ENOSYS;
db0fefc5 1524 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1525}
1526
1527static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1528{
70a3341a 1529 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1530
191d1f1d 1531 if (!mmc_slot(host).get_ro)
a45c6cb8 1532 return -ENOSYS;
191d1f1d 1533 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1534}
1535
4816858c
GI		 1536static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1537{
1538 struct omap_hsmmc_host *host = mmc_priv(mmc);
1539
1540 if (mmc_slot(host).init_card)
1541 mmc_slot(host).init_card(card);
1542}
1543
70a3341a 1544static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1545{
1546 u32 hctl, capa, value;
1547
1548 /* Only MMC1 supports 3.0V */
4621d5f8 1549 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1550 hctl = SDVS30;
1551 capa = VS30 | VS18;
1552 } else {
1553 hctl = SDVS18;
1554 capa = VS18;
1555 }
1556
1557 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1558 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1559
1560 value = OMAP_HSMMC_READ(host->base, CAPA);
1561 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1562
1b331e69 1563 /* Set SD bus power bit */
e13bb300 1564 set_sd_bus_power(host);
1b331e69
KK		 1565}
1566
70a3341a 1567static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1568{
70a3341a 1569 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1570
fa4aa2d4
B		 1571 pm_runtime_get_sync(host->dev);
1572
dd498eff
DK		 1573 return 0;
1574}
1575
907d2e7c 1576static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
dd498eff 1577{
70a3341a 1578 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1579
fa4aa2d4
B		 1580 pm_runtime_mark_last_busy(host->dev);
1581 pm_runtime_put_autosuspend(host->dev);
1582
dd498eff
DK		 1583 return 0;
1584}
1585
70a3341a
DK		 1586static const struct mmc_host_ops omap_hsmmc_ops = {
1587 .enable = omap_hsmmc_enable_fclk,
1588 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1589 .post_req = omap_hsmmc_post_req,
1590 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1591 .request = omap_hsmmc_request,
1592 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1593 .get_cd = omap_hsmmc_get_cd,
1594 .get_ro = omap_hsmmc_get_ro,
4816858c 1595 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1596 /* NYET -- enable_sdio_irq */
1597};
1598
d900f712
DK		 1599#ifdef CONFIG_DEBUG_FS
1600
70a3341a 1601static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1602{
1603 struct mmc_host *mmc = s->private;
70a3341a 1604 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1605 int context_loss = 0;
1606
70a3341a
DK		 1607 if (host->pdata->get_context_loss_count)
1608 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1609
907d2e7c
AH		 1610 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1611 mmc->index, host->context_loss, context_loss);
5e2ea617 1612
7a8c2cef 1613 if (host->suspended) {
dd498eff
DK		 1614 seq_printf(s, "host suspended, can't read registers\n");
1615 return 0;
1616 }
1617
fa4aa2d4 1618 pm_runtime_get_sync(host->dev);
d900f712 1619
d900f712
DK		 1620 seq_printf(s, "CON:\t\t0x%08x\n",
1621 OMAP_HSMMC_READ(host->base, CON));
1622 seq_printf(s, "HCTL:\t\t0x%08x\n",
1623 OMAP_HSMMC_READ(host->base, HCTL));
1624 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1625 OMAP_HSMMC_READ(host->base, SYSCTL));
1626 seq_printf(s, "IE:\t\t0x%08x\n",
1627 OMAP_HSMMC_READ(host->base, IE));
1628 seq_printf(s, "ISE:\t\t0x%08x\n",
1629 OMAP_HSMMC_READ(host->base, ISE));
1630 seq_printf(s, "CAPA:\t\t0x%08x\n",
1631 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1632
fa4aa2d4
B		 1633 pm_runtime_mark_last_busy(host->dev);
1634 pm_runtime_put_autosuspend(host->dev);
dd498eff 1635
d900f712
DK		 1636 return 0;
1637}
1638
70a3341a 1639static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1640{
70a3341a 1641 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1642}
1643
1644static const struct file_operations mmc_regs_fops = {
70a3341a 1645 .open = omap_hsmmc_regs_open,
d900f712
DK		 1646 .read = seq_read,
1647 .llseek = seq_lseek,
1648 .release = single_release,
1649};
1650
70a3341a 1651static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1652{
1653 if (mmc->debugfs_root)
1654 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1655 mmc, &mmc_regs_fops);
1656}
1657
1658#else
1659
70a3341a 1660static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1661{
1662}
1663
1664#endif
1665
46856a68
RN		 1666#ifdef CONFIG_OF
1667static u16 omap4_reg_offset = 0x100;
1668
1669static const struct of_device_id omap_mmc_of_match[] = {
1670 {
1671 .compatible = "ti,omap2-hsmmc",
1672 },
1673 {
1674 .compatible = "ti,omap3-hsmmc",
1675 },
1676 {
1677 .compatible = "ti,omap4-hsmmc",
1678 .data = &omap4_reg_offset,
1679 },
1680 {},
b6d085f6 1681};
46856a68
RN		 1682MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1683
1684static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1685{
1686 struct omap_mmc_platform_data *pdata;
1687 struct device_node *np = dev->of_node;
d8714e87 1688 u32 bus_width, max_freq;
46856a68
RN		 1689
1690 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1691 if (!pdata)
1692 return NULL; /* out of memory */
1693
1694 if (of_find_property(np, "ti,dual-volt", NULL))
1695 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1696
1697 /* This driver only supports 1 slot */
1698 pdata->nr_slots = 1;
1699 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1700 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1701
1702 if (of_find_property(np, "ti,non-removable", NULL)) {
1703 pdata->slots[0].nonremovable = true;
1704 pdata->slots[0].no_regulator_off_init = true;
1705 }
7f217794 1706 of_property_read_u32(np, "bus-width", &bus_width);
46856a68
RN		 1707 if (bus_width == 4)
1708 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1709 else if (bus_width == 8)
1710 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1711
1712 if (of_find_property(np, "ti,needs-special-reset", NULL))
1713 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1714
d8714e87
DM		 1715 if (!of_property_read_u32(np, "max-frequency", &max_freq))
1716 pdata->max_freq = max_freq;
1717
46856a68
RN		 1718 return pdata;
1719}
1720#else
1721static inline struct omap_mmc_platform_data
1722 *of_get_hsmmc_pdata(struct device *dev)
1723{
1724 return NULL;
1725}
1726#endif
1727
efa25fd3 1728static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1729{
1730 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1731 struct mmc_host *mmc;
70a3341a 1732 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1733 struct resource *res;
db0fefc5 1734 int ret, irq;
46856a68 1735 const struct of_device_id *match;
26b88520
RK		 1736 dma_cap_mask_t mask;
1737 unsigned tx_req, rx_req;
46b76035 1738 struct pinctrl *pinctrl;
46856a68
RN		 1739
1740 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1741 if (match) {
1742 pdata = of_get_hsmmc_pdata(&pdev->dev);
1743 if (match->data) {
efc9b736 1744 const u16 *offsetp = match->data;
46856a68
RN		 1745 pdata->reg_offset = *offsetp;
1746 }
1747 }
a45c6cb8
MC		 1748
1749 if (pdata == NULL) {
1750 dev_err(&pdev->dev, "Platform Data is missing\n");
1751 return -ENXIO;
1752 }
1753
1754 if (pdata->nr_slots == 0) {
1755 dev_err(&pdev->dev, "No Slots\n");
1756 return -ENXIO;
1757 }
1758
1759 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1760 irq = platform_get_irq(pdev, 0);
1761 if (res == NULL || irq < 0)
1762 return -ENXIO;
1763
984b203a 1764 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1765 if (res == NULL)
1766 return -EBUSY;
1767
db0fefc5
AH		 1768 ret = omap_hsmmc_gpio_init(pdata);
1769 if (ret)
1770 goto err;
1771
70a3341a 1772 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1773 if (!mmc) {
1774 ret = -ENOMEM;
db0fefc5 1775 goto err_alloc;
a45c6cb8
MC		 1776 }
1777
1778 host = mmc_priv(mmc);
1779 host->mmc = mmc;
1780 host->pdata = pdata;
1781 host->dev = &pdev->dev;
1782 host->use_dma = 1;
a45c6cb8
MC		 1783 host->dma_ch = -1;
1784 host->irq = irq;
a45c6cb8 1785 host->slot_id = 0;
fc307df8 1786 host->mapbase = res->start + pdata->reg_offset;
a45c6cb8 1787 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1788 host->power_mode = MMC_POWER_OFF;
9782aff8 1789 host->next_data.cookie = 1;
a45c6cb8
MC		 1790
1791 platform_set_drvdata(pdev, host);
a45c6cb8 1792
7a8c2cef 1793 mmc->ops = &omap_hsmmc_ops;
dd498eff 1794
e0eb2424
AH		 1795 /*
1796 * If regulator_disable can only put vcc_aux to sleep then there is
1797 * no off state.
1798 */
1799 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1800 mmc_slot(host).no_off = 1;
1801
d418ed87
DM		 1802 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1803
1804 if (pdata->max_freq > 0)
1805 mmc->f_max = pdata->max_freq;
1806 else
1807 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1808
4dffd7a2 1809 spin_lock_init(&host->irq_lock);
a45c6cb8 1810
6f7607cc 1811 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1812 if (IS_ERR(host->fclk)) {
1813 ret = PTR_ERR(host->fclk);
1814 host->fclk = NULL;
a45c6cb8
MC		 1815 goto err1;
1816 }
1817
9b68256c
PW		 1818 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1819 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1820 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1821 }
dd498eff 1822
fa4aa2d4
B		 1823 pm_runtime_enable(host->dev);
1824 pm_runtime_get_sync(host->dev);
1825 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1826 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1827
92a3aebf
B		 1828 omap_hsmmc_context_save(host);
1829
cd03d9a8
RN		 1830 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1831 /*
1832 * MMC can still work without debounce clock.
1833 */
1834 if (IS_ERR(host->dbclk)) {
cd03d9a8 1835 host->dbclk = NULL;
94c18149 1836 } else if (clk_prepare_enable(host->dbclk) != 0) {
cd03d9a8
RN		 1837 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
1838 clk_put(host->dbclk);
1839 host->dbclk = NULL;
2bec0893 1840 }
a45c6cb8 1841
0ccd76d4
JY		 1842 /* Since we do only SG emulation, we can have as many segs
1843 * as we want. */
a36274e0 1844 mmc->max_segs = 1024;
0ccd76d4 1845
a45c6cb8
MC		 1846 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1847 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1848 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1849 mmc->max_seg_size = mmc->max_req_size;
1850
13189e78 1851 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1852 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1853
3a63833e
SG		 1854 mmc->caps |= mmc_slot(host).caps;
1855 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1856 mmc->caps |= MMC_CAP_4_BIT_DATA;
1857
191d1f1d 1858 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1859 mmc->caps |= MMC_CAP_NONREMOVABLE;
1860
6fdc75de
EP		 1861 mmc->pm_caps = mmc_slot(host).pm_caps;
1862
70a3341a 1863 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1864
b7bf773b
B		 1865 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1866 if (!res) {
1867 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
9c17d08c 1868 ret = -ENXIO;
b7bf773b
B		 1869 goto err_irq;
1870 }
26b88520 1871 tx_req = res->start;
b7bf773b
B		 1872
1873 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1874 if (!res) {
1875 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
9c17d08c 1876 ret = -ENXIO;
f3e2f1dd
GI		 1877 goto err_irq;
1878 }
26b88520 1879 rx_req = res->start;
a45c6cb8 1880
26b88520
RK		 1881 dma_cap_zero(mask);
1882 dma_cap_set(DMA_SLAVE, mask);
1883
1884 host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
1885 if (!host->rx_chan) {
1886 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
04e8c7bc 1887 ret = -ENXIO;
26b88520
RK		 1888 goto err_irq;
1889 }
1890
1891 host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
1892 if (!host->tx_chan) {
1893 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
04e8c7bc 1894 ret = -ENXIO;
26b88520 1895 goto err_irq;
c5c98927 1896 }
a45c6cb8
MC		 1897
1898 /* Request IRQ for MMC operations */
d9618e9f 1899 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 1900 mmc_hostname(mmc), host);
1901 if (ret) {
1902 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1903 goto err_irq;
1904 }
1905
1906 if (pdata->init != NULL) {
1907 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 1908 dev_dbg(mmc_dev(host->mmc),
1909 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 1910 goto err_irq_cd_init;
1911 }
1912 }
db0fefc5 1913
b702b106 1914 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 1915 ret = omap_hsmmc_reg_get(host);
1916 if (ret)
1917 goto err_reg;
1918 host->use_reg = 1;
1919 }
1920
b583f26d 1921 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1922
1923 /* Request IRQ for card detect */
e1a55f5e 1924 if ((mmc_slot(host).card_detect_irq)) {
7efab4f3
N		 1925 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1926 NULL,
1927 omap_hsmmc_detect,
db35f83e 1928 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
7efab4f3 1929 mmc_hostname(mmc), host);
a45c6cb8
MC		 1930 if (ret) {
1931 dev_dbg(mmc_dev(host->mmc),
1932 "Unable to grab MMC CD IRQ\n");
1933 goto err_irq_cd;
1934 }
72f2e2c7 1935 pdata->suspend = omap_hsmmc_suspend_cdirq;
1936 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 1937 }
1938
b417577d 1939 omap_hsmmc_disable_irq(host);
a45c6cb8 1940
46b76035
DM		 1941 pinctrl = devm_pinctrl_get_select_default(&pdev->dev);
1942 if (IS_ERR(pinctrl))
1943 dev_warn(&pdev->dev,
1944 "pins are not configured from the driver\n");
1945
b62f6228
AH		 1946 omap_hsmmc_protect_card(host);
1947
a45c6cb8
MC		 1948 mmc_add_host(mmc);
1949
191d1f1d 1950 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 1951 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1952 if (ret < 0)
1953 goto err_slot_name;
1954 }
191d1f1d 1955 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 1956 ret = device_create_file(&mmc->class_dev,
1957 &dev_attr_cover_switch);
1958 if (ret < 0)
db0fefc5 1959 goto err_slot_name;
a45c6cb8
MC		 1960 }
1961
70a3341a 1962 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 1963 pm_runtime_mark_last_busy(host->dev);
1964 pm_runtime_put_autosuspend(host->dev);
d900f712 1965
a45c6cb8
MC		 1966 return 0;
1967
a45c6cb8
MC		 1968err_slot_name:
1969 mmc_remove_host(mmc);
a45c6cb8 1970 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 1971err_irq_cd:
1972 if (host->use_reg)
1973 omap_hsmmc_reg_put(host);
1974err_reg:
1975 if (host->pdata->cleanup)
1976 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 1977err_irq_cd_init:
1978 free_irq(host->irq, host);
1979err_irq:
c5c98927
RK		 1980 if (host->tx_chan)
1981 dma_release_channel(host->tx_chan);
1982 if (host->rx_chan)
1983 dma_release_channel(host->rx_chan);
d59d77ed 1984 pm_runtime_put_sync(host->dev);
37f6190d 1985 pm_runtime_disable(host->dev);
a45c6cb8 1986 clk_put(host->fclk);
cd03d9a8 1987 if (host->dbclk) {
94c18149 1988 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1989 clk_put(host->dbclk);
1990 }
a45c6cb8
MC		 1991err1:
1992 iounmap(host->base);
db0fefc5
AH		 1993 platform_set_drvdata(pdev, NULL);
1994 mmc_free_host(mmc);
1995err_alloc:
1996 omap_hsmmc_gpio_free(pdata);
a45c6cb8 1997err:
48b332f9
RK		 1998 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1999 if (res)
2000 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2001 return ret;
2002}
2003
efa25fd3 2004static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2005{
70a3341a 2006 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2007 struct resource *res;
2008
927ce944
FB		 2009 pm_runtime_get_sync(host->dev);
2010 mmc_remove_host(host->mmc);
2011 if (host->use_reg)
2012 omap_hsmmc_reg_put(host);
2013 if (host->pdata->cleanup)
2014 host->pdata->cleanup(&pdev->dev);
2015 free_irq(host->irq, host);
2016 if (mmc_slot(host).card_detect_irq)
2017 free_irq(mmc_slot(host).card_detect_irq, host);
a45c6cb8 2018
c5c98927
RK		 2019 if (host->tx_chan)
2020 dma_release_channel(host->tx_chan);
2021 if (host->rx_chan)
2022 dma_release_channel(host->rx_chan);
2023
927ce944
FB		 2024 pm_runtime_put_sync(host->dev);
2025 pm_runtime_disable(host->dev);
2026 clk_put(host->fclk);
cd03d9a8 2027 if (host->dbclk) {
94c18149 2028 clk_disable_unprepare(host->dbclk);
927ce944 2029 clk_put(host->dbclk);
a45c6cb8
MC		 2030 }
2031
9ea28ecb 2032 omap_hsmmc_gpio_free(host->pdata);
927ce944 2033 iounmap(host->base);
9d1f0286 2034 mmc_free_host(host->mmc);
927ce944 2035
a45c6cb8
MC		 2036 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2037 if (res)
984b203a 2038 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2039 platform_set_drvdata(pdev, NULL);
2040
2041 return 0;
2042}
2043
2044#ifdef CONFIG_PM
a791daa1 2045static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2046{
2047 int ret = 0;
927ce944 2048 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2049
927ce944 2050 if (!host)
a45c6cb8
MC		 2051 return 0;
2052
927ce944
FB		 2053 if (host && host->suspended)
2054 return 0;
fa4aa2d4 2055
927ce944
FB		 2056 pm_runtime_get_sync(host->dev);
2057 host->suspended = 1;
2058 if (host->pdata->suspend) {
2059 ret = host->pdata->suspend(dev, host->slot_id);
31f9d463 2060 if (ret) {
927ce944
FB		 2061 dev_dbg(dev, "Unable to handle MMC board"
2062 " level suspend\n");
a6b2240d 2063 host->suspended = 0;
927ce944 2064 return ret;
a6b2240d 2065 }
927ce944
FB		 2066 }
2067 ret = mmc_suspend_host(host->mmc);
31f9d463 2068
927ce944
FB		 2069 if (ret) {
2070 host->suspended = 0;
2071 if (host->pdata->resume) {
c4c8eeb4 2072 if (host->pdata->resume(dev, host->slot_id))
927ce944 2073 dev_dbg(dev, "Unmask interrupt failed\n");
31f9d463 2074 }
927ce944
FB		 2075 goto err;
2076 }
31f9d463 2077
927ce944
FB		 2078 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2079 omap_hsmmc_disable_irq(host);
2080 OMAP_HSMMC_WRITE(host->base, HCTL,
2081 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2082 }
927ce944 2083
cd03d9a8 2084 if (host->dbclk)
94c18149 2085 clk_disable_unprepare(host->dbclk);
31f9d463
EP		 2086err:
2087 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2088 return ret;
2089}
2090
2091/* Routine to resume the MMC device */
a791daa1 2092static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2093{
2094 int ret = 0;
927ce944
FB		 2095 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2096
2097 if (!host)
2098 return 0;
a45c6cb8
MC		 2099
2100 if (host && !host->suspended)
2101 return 0;
2102
927ce944 2103 pm_runtime_get_sync(host->dev);
11dd62a7 2104
cd03d9a8 2105 if (host->dbclk)
94c18149 2106 clk_prepare_enable(host->dbclk);
2bec0893 2107
927ce944
FB		 2108 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2109 omap_hsmmc_conf_bus_power(host);
1b331e69 2110
927ce944
FB		 2111 if (host->pdata->resume) {
2112 ret = host->pdata->resume(dev, host->slot_id);
2113 if (ret)
2114 dev_dbg(dev, "Unmask interrupt failed\n");
2115 }
a45c6cb8 2116
927ce944 2117 omap_hsmmc_protect_card(host);
b62f6228 2118
927ce944
FB		 2119 /* Notify the core to resume the host */
2120 ret = mmc_resume_host(host->mmc);
2121 if (ret == 0)
2122 host->suspended = 0;
fa4aa2d4 2123
927ce944
FB		 2124 pm_runtime_mark_last_busy(host->dev);
2125 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2126
2127 return ret;
2128
a45c6cb8
MC		 2129}
2130
2131#else
70a3341a
DK		 2132#define omap_hsmmc_suspend NULL
2133#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2134#endif
2135
fa4aa2d4
B		 2136static int omap_hsmmc_runtime_suspend(struct device *dev)
2137{
2138 struct omap_hsmmc_host *host;
2139
2140 host = platform_get_drvdata(to_platform_device(dev));
2141 omap_hsmmc_context_save(host);
927ce944 2142 dev_dbg(dev, "disabled\n");
fa4aa2d4
B		 2143
2144 return 0;
2145}
2146
2147static int omap_hsmmc_runtime_resume(struct device *dev)
2148{
2149 struct omap_hsmmc_host *host;
2150
2151 host = platform_get_drvdata(to_platform_device(dev));
2152 omap_hsmmc_context_restore(host);
927ce944 2153 dev_dbg(dev, "enabled\n");
fa4aa2d4
B		 2154
2155 return 0;
2156}
2157
a791daa1 2158static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2159 .suspend = omap_hsmmc_suspend,
2160 .resume = omap_hsmmc_resume,
fa4aa2d4
B		 2161 .runtime_suspend = omap_hsmmc_runtime_suspend,
2162 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2163};
2164
2165static struct platform_driver omap_hsmmc_driver = {
efa25fd3
FB		 2166 .probe = omap_hsmmc_probe,
2167 .remove = __devexit_p(omap_hsmmc_remove),
a45c6cb8
MC		 2168 .driver = {
2169 .name = DRIVER_NAME,
2170 .owner = THIS_MODULE,
a791daa1 2171 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2172 .of_match_table = of_match_ptr(omap_mmc_of_match),
a45c6cb8
MC		 2173 },
2174};
2175
b796450b 2176module_platform_driver(omap_hsmmc_driver);
a45c6cb8
MC		 2177MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2178MODULE_LICENSE("GPL");
2179MODULE_ALIAS("platform:" DRIVER_NAME);
2180MODULE_AUTHOR("Texas Instruments Inc");
Ubuntu Artful kernel mirror