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Commit | Line | Data |
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a45c6cb8 MC |
1 | /* |
2 | * drivers/mmc/host/omap_hsmmc.c | |
3 | * | |
4 | * Driver for OMAP2430/3430 MMC controller. | |
5 | * | |
6 | * Copyright (C) 2007 Texas Instruments. | |
7 | * | |
8 | * Authors: | |
9 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
10 | * Madhusudhan <madhu.cr@ti.com> | |
11 | * Mohit Jalori <mjalori@ti.com> | |
12 | * | |
13 | * This file is licensed under the terms of the GNU General Public License | |
14 | * version 2. This program is licensed "as is" without any warranty of any | |
15 | * kind, whether express or implied. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
d900f712 DK |
20 | #include <linux/debugfs.h> |
21 | #include <linux/seq_file.h> | |
a45c6cb8 MC |
22 | #include <linux/interrupt.h> |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/workqueue.h> | |
27 | #include <linux/timer.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/mmc/host.h> | |
13189e78 | 30 | #include <linux/mmc/core.h> |
a45c6cb8 MC |
31 | #include <linux/io.h> |
32 | #include <linux/semaphore.h> | |
db0fefc5 AH |
33 | #include <linux/gpio.h> |
34 | #include <linux/regulator/consumer.h> | |
ce491cf8 | 35 | #include <plat/dma.h> |
a45c6cb8 | 36 | #include <mach/hardware.h> |
ce491cf8 TL |
37 | #include <plat/board.h> |
38 | #include <plat/mmc.h> | |
39 | #include <plat/cpu.h> | |
a45c6cb8 MC |
40 | |
41 | /* OMAP HSMMC Host Controller Registers */ | |
42 | #define OMAP_HSMMC_SYSCONFIG 0x0010 | |
11dd62a7 | 43 | #define OMAP_HSMMC_SYSSTATUS 0x0014 |
a45c6cb8 MC |
44 | #define OMAP_HSMMC_CON 0x002C |
45 | #define OMAP_HSMMC_BLK 0x0104 | |
46 | #define OMAP_HSMMC_ARG 0x0108 | |
47 | #define OMAP_HSMMC_CMD 0x010C | |
48 | #define OMAP_HSMMC_RSP10 0x0110 | |
49 | #define OMAP_HSMMC_RSP32 0x0114 | |
50 | #define OMAP_HSMMC_RSP54 0x0118 | |
51 | #define OMAP_HSMMC_RSP76 0x011C | |
52 | #define OMAP_HSMMC_DATA 0x0120 | |
53 | #define OMAP_HSMMC_HCTL 0x0128 | |
54 | #define OMAP_HSMMC_SYSCTL 0x012C | |
55 | #define OMAP_HSMMC_STAT 0x0130 | |
56 | #define OMAP_HSMMC_IE 0x0134 | |
57 | #define OMAP_HSMMC_ISE 0x0138 | |
58 | #define OMAP_HSMMC_CAPA 0x0140 | |
59 | ||
60 | #define VS18 (1 << 26) | |
61 | #define VS30 (1 << 25) | |
62 | #define SDVS18 (0x5 << 9) | |
63 | #define SDVS30 (0x6 << 9) | |
eb250826 | 64 | #define SDVS33 (0x7 << 9) |
1b331e69 | 65 | #define SDVS_MASK 0x00000E00 |
a45c6cb8 MC |
66 | #define SDVSCLR 0xFFFFF1FF |
67 | #define SDVSDET 0x00000400 | |
68 | #define AUTOIDLE 0x1 | |
69 | #define SDBP (1 << 8) | |
70 | #define DTO 0xe | |
71 | #define ICE 0x1 | |
72 | #define ICS 0x2 | |
73 | #define CEN (1 << 2) | |
74 | #define CLKD_MASK 0x0000FFC0 | |
75 | #define CLKD_SHIFT 6 | |
76 | #define DTO_MASK 0x000F0000 | |
77 | #define DTO_SHIFT 16 | |
78 | #define INT_EN_MASK 0x307F0033 | |
ccdfe3a6 AG |
79 | #define BWR_ENABLE (1 << 4) |
80 | #define BRR_ENABLE (1 << 5) | |
a45c6cb8 MC |
81 | #define INIT_STREAM (1 << 1) |
82 | #define DP_SELECT (1 << 21) | |
83 | #define DDIR (1 << 4) | |
84 | #define DMA_EN 0x1 | |
85 | #define MSBS (1 << 5) | |
86 | #define BCE (1 << 1) | |
87 | #define FOUR_BIT (1 << 1) | |
73153010 | 88 | #define DW8 (1 << 5) |
a45c6cb8 MC |
89 | #define CC 0x1 |
90 | #define TC 0x02 | |
91 | #define OD 0x1 | |
92 | #define ERR (1 << 15) | |
93 | #define CMD_TIMEOUT (1 << 16) | |
94 | #define DATA_TIMEOUT (1 << 20) | |
95 | #define CMD_CRC (1 << 17) | |
96 | #define DATA_CRC (1 << 21) | |
97 | #define CARD_ERR (1 << 28) | |
98 | #define STAT_CLEAR 0xFFFFFFFF | |
99 | #define INIT_STREAM_CMD 0x00000000 | |
100 | #define DUAL_VOLT_OCR_BIT 7 | |
101 | #define SRC (1 << 25) | |
102 | #define SRD (1 << 26) | |
11dd62a7 DK |
103 | #define SOFTRESET (1 << 1) |
104 | #define RESETDONE (1 << 0) | |
a45c6cb8 MC |
105 | |
106 | /* | |
107 | * FIXME: Most likely all the data using these _DEVID defines should come | |
108 | * from the platform_data, or implemented in controller and slot specific | |
109 | * functions. | |
110 | */ | |
111 | #define OMAP_MMC1_DEVID 0 | |
112 | #define OMAP_MMC2_DEVID 1 | |
f3e2f1dd | 113 | #define OMAP_MMC3_DEVID 2 |
82cf818d | 114 | #define OMAP_MMC4_DEVID 3 |
115 | #define OMAP_MMC5_DEVID 4 | |
a45c6cb8 | 116 | |
a45c6cb8 MC |
117 | #define MMC_TIMEOUT_MS 20 |
118 | #define OMAP_MMC_MASTER_CLOCK 96000000 | |
119 | #define DRIVER_NAME "mmci-omap-hs" | |
120 | ||
dd498eff DK |
121 | /* Timeouts for entering power saving states on inactivity, msec */ |
122 | #define OMAP_MMC_DISABLED_TIMEOUT 100 | |
13189e78 JL |
123 | #define OMAP_MMC_SLEEP_TIMEOUT 1000 |
124 | #define OMAP_MMC_OFF_TIMEOUT 8000 | |
dd498eff | 125 | |
a45c6cb8 MC |
126 | /* |
127 | * One controller can have multiple slots, like on some omap boards using | |
128 | * omap.c controller driver. Luckily this is not currently done on any known | |
129 | * omap_hsmmc.c device. | |
130 | */ | |
131 | #define mmc_slot(host) (host->pdata->slots[host->slot_id]) | |
132 | ||
133 | /* | |
134 | * MMC Host controller read/write API's | |
135 | */ | |
136 | #define OMAP_HSMMC_READ(base, reg) \ | |
137 | __raw_readl((base) + OMAP_HSMMC_##reg) | |
138 | ||
139 | #define OMAP_HSMMC_WRITE(base, reg, val) \ | |
140 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) | |
141 | ||
70a3341a | 142 | struct omap_hsmmc_host { |
a45c6cb8 MC |
143 | struct device *dev; |
144 | struct mmc_host *mmc; | |
145 | struct mmc_request *mrq; | |
146 | struct mmc_command *cmd; | |
147 | struct mmc_data *data; | |
148 | struct clk *fclk; | |
149 | struct clk *iclk; | |
150 | struct clk *dbclk; | |
db0fefc5 AH |
151 | /* |
152 | * vcc == configured supply | |
153 | * vcc_aux == optional | |
154 | * - MMC1, supply for DAT4..DAT7 | |
155 | * - MMC2/MMC2, external level shifter voltage supply, for | |
156 | * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) | |
157 | */ | |
158 | struct regulator *vcc; | |
159 | struct regulator *vcc_aux; | |
a45c6cb8 MC |
160 | struct semaphore sem; |
161 | struct work_struct mmc_carddetect_work; | |
162 | void __iomem *base; | |
163 | resource_size_t mapbase; | |
4dffd7a2 AH |
164 | spinlock_t irq_lock; /* Prevent races with irq handler */ |
165 | unsigned long flags; | |
a45c6cb8 MC |
166 | unsigned int id; |
167 | unsigned int dma_len; | |
0ccd76d4 | 168 | unsigned int dma_sg_idx; |
a45c6cb8 | 169 | unsigned char bus_mode; |
a3621465 | 170 | unsigned char power_mode; |
a45c6cb8 MC |
171 | u32 *buffer; |
172 | u32 bytesleft; | |
173 | int suspended; | |
174 | int irq; | |
a45c6cb8 | 175 | int use_dma, dma_ch; |
f3e2f1dd | 176 | int dma_line_tx, dma_line_rx; |
a45c6cb8 | 177 | int slot_id; |
2bec0893 | 178 | int got_dbclk; |
4a694dc9 | 179 | int response_busy; |
11dd62a7 | 180 | int context_loss; |
dd498eff | 181 | int dpm_state; |
623821f7 | 182 | int vdd; |
b62f6228 AH |
183 | int protect_card; |
184 | int reqs_blocked; | |
db0fefc5 | 185 | int use_reg; |
11dd62a7 | 186 | |
a45c6cb8 MC |
187 | struct omap_mmc_platform_data *pdata; |
188 | }; | |
189 | ||
db0fefc5 AH |
190 | static int omap_hsmmc_card_detect(struct device *dev, int slot) |
191 | { | |
192 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
193 | ||
194 | /* NOTE: assumes card detect signal is active-low */ | |
195 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
196 | } | |
197 | ||
198 | static int omap_hsmmc_get_wp(struct device *dev, int slot) | |
199 | { | |
200 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
201 | ||
202 | /* NOTE: assumes write protect signal is active-high */ | |
203 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | |
204 | } | |
205 | ||
206 | static int omap_hsmmc_get_cover_state(struct device *dev, int slot) | |
207 | { | |
208 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
209 | ||
210 | /* NOTE: assumes card detect signal is active-low */ | |
211 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
212 | } | |
213 | ||
214 | #ifdef CONFIG_PM | |
215 | ||
216 | static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) | |
217 | { | |
218 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
219 | ||
220 | disable_irq(mmc->slots[0].card_detect_irq); | |
221 | return 0; | |
222 | } | |
223 | ||
224 | static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) | |
225 | { | |
226 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
227 | ||
228 | enable_irq(mmc->slots[0].card_detect_irq); | |
229 | return 0; | |
230 | } | |
231 | ||
232 | #else | |
233 | ||
234 | #define omap_hsmmc_suspend_cdirq NULL | |
235 | #define omap_hsmmc_resume_cdirq NULL | |
236 | ||
237 | #endif | |
238 | ||
b702b106 AH |
239 | #ifdef CONFIG_REGULATOR |
240 | ||
db0fefc5 AH |
241 | static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, |
242 | int vdd) | |
243 | { | |
244 | struct omap_hsmmc_host *host = | |
245 | platform_get_drvdata(to_platform_device(dev)); | |
246 | int ret; | |
247 | ||
248 | if (mmc_slot(host).before_set_reg) | |
249 | mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); | |
250 | ||
251 | if (power_on) | |
252 | ret = mmc_regulator_set_ocr(host->vcc, vdd); | |
253 | else | |
254 | ret = mmc_regulator_set_ocr(host->vcc, 0); | |
255 | ||
256 | if (mmc_slot(host).after_set_reg) | |
257 | mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); | |
258 | ||
259 | return ret; | |
260 | } | |
261 | ||
262 | static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, | |
263 | int vdd) | |
264 | { | |
265 | struct omap_hsmmc_host *host = | |
266 | platform_get_drvdata(to_platform_device(dev)); | |
267 | int ret = 0; | |
268 | ||
269 | /* | |
270 | * If we don't see a Vcc regulator, assume it's a fixed | |
271 | * voltage always-on regulator. | |
272 | */ | |
273 | if (!host->vcc) | |
274 | return 0; | |
275 | ||
276 | if (mmc_slot(host).before_set_reg) | |
277 | mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); | |
278 | ||
279 | /* | |
280 | * Assume Vcc regulator is used only to power the card ... OMAP | |
281 | * VDDS is used to power the pins, optionally with a transceiver to | |
282 | * support cards using voltages other than VDDS (1.8V nominal). When a | |
283 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. | |
284 | * | |
285 | * In some cases this regulator won't support enable/disable; | |
286 | * e.g. it's a fixed rail for a WLAN chip. | |
287 | * | |
288 | * In other cases vcc_aux switches interface power. Example, for | |
289 | * eMMC cards it represents VccQ. Sometimes transceivers or SDIO | |
290 | * chips/cards need an interface voltage rail too. | |
291 | */ | |
292 | if (power_on) { | |
293 | ret = mmc_regulator_set_ocr(host->vcc, vdd); | |
294 | /* Enable interface voltage rail, if needed */ | |
295 | if (ret == 0 && host->vcc_aux) { | |
296 | ret = regulator_enable(host->vcc_aux); | |
297 | if (ret < 0) | |
298 | ret = mmc_regulator_set_ocr(host->vcc, 0); | |
299 | } | |
300 | } else { | |
6da20c89 AH |
301 | if (host->vcc_aux) |
302 | ret = regulator_disable(host->vcc_aux); | |
db0fefc5 AH |
303 | if (ret == 0) |
304 | ret = mmc_regulator_set_ocr(host->vcc, 0); | |
305 | } | |
306 | ||
307 | if (mmc_slot(host).after_set_reg) | |
308 | mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); | |
309 | ||
310 | return ret; | |
311 | } | |
312 | ||
313 | static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, | |
314 | int vdd, int cardsleep) | |
315 | { | |
316 | struct omap_hsmmc_host *host = | |
317 | platform_get_drvdata(to_platform_device(dev)); | |
318 | int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; | |
319 | ||
320 | return regulator_set_mode(host->vcc, mode); | |
321 | } | |
322 | ||
323 | static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, | |
324 | int vdd, int cardsleep) | |
325 | { | |
326 | struct omap_hsmmc_host *host = | |
327 | platform_get_drvdata(to_platform_device(dev)); | |
328 | int err, mode; | |
329 | ||
330 | /* | |
331 | * If we don't see a Vcc regulator, assume it's a fixed | |
332 | * voltage always-on regulator. | |
333 | */ | |
334 | if (!host->vcc) | |
335 | return 0; | |
336 | ||
337 | mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; | |
338 | ||
339 | if (!host->vcc_aux) | |
340 | return regulator_set_mode(host->vcc, mode); | |
341 | ||
342 | if (cardsleep) { | |
343 | /* VCC can be turned off if card is asleep */ | |
344 | if (sleep) | |
345 | err = mmc_regulator_set_ocr(host->vcc, 0); | |
346 | else | |
347 | err = mmc_regulator_set_ocr(host->vcc, vdd); | |
348 | } else | |
349 | err = regulator_set_mode(host->vcc, mode); | |
350 | if (err) | |
351 | return err; | |
e0eb2424 AH |
352 | |
353 | if (!mmc_slot(host).vcc_aux_disable_is_sleep) | |
354 | return regulator_set_mode(host->vcc_aux, mode); | |
355 | ||
356 | if (sleep) | |
357 | return regulator_disable(host->vcc_aux); | |
358 | else | |
359 | return regulator_enable(host->vcc_aux); | |
db0fefc5 AH |
360 | } |
361 | ||
db0fefc5 AH |
362 | static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) |
363 | { | |
364 | struct regulator *reg; | |
365 | int ret = 0; | |
366 | ||
367 | switch (host->id) { | |
368 | case OMAP_MMC1_DEVID: | |
369 | /* On-chip level shifting via PBIAS0/PBIAS1 */ | |
370 | mmc_slot(host).set_power = omap_hsmmc_1_set_power; | |
371 | mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; | |
372 | break; | |
373 | case OMAP_MMC2_DEVID: | |
374 | case OMAP_MMC3_DEVID: | |
375 | /* Off-chip level shifting, or none */ | |
376 | mmc_slot(host).set_power = omap_hsmmc_23_set_power; | |
377 | mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; | |
378 | break; | |
379 | default: | |
380 | pr_err("MMC%d configuration not supported!\n", host->id); | |
381 | return -EINVAL; | |
382 | } | |
383 | ||
384 | reg = regulator_get(host->dev, "vmmc"); | |
385 | if (IS_ERR(reg)) { | |
386 | dev_dbg(host->dev, "vmmc regulator missing\n"); | |
387 | /* | |
388 | * HACK: until fixed.c regulator is usable, | |
389 | * we don't require a main regulator | |
390 | * for MMC2 or MMC3 | |
391 | */ | |
392 | if (host->id == OMAP_MMC1_DEVID) { | |
393 | ret = PTR_ERR(reg); | |
394 | goto err; | |
395 | } | |
396 | } else { | |
397 | host->vcc = reg; | |
398 | mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg); | |
399 | ||
400 | /* Allow an aux regulator */ | |
401 | reg = regulator_get(host->dev, "vmmc_aux"); | |
402 | host->vcc_aux = IS_ERR(reg) ? NULL : reg; | |
403 | ||
404 | /* | |
405 | * UGLY HACK: workaround regulator framework bugs. | |
406 | * When the bootloader leaves a supply active, it's | |
407 | * initialized with zero usecount ... and we can't | |
408 | * disable it without first enabling it. Until the | |
409 | * framework is fixed, we need a workaround like this | |
410 | * (which is safe for MMC, but not in general). | |
411 | */ | |
412 | if (regulator_is_enabled(host->vcc) > 0) { | |
413 | regulator_enable(host->vcc); | |
414 | regulator_disable(host->vcc); | |
415 | } | |
416 | if (host->vcc_aux) { | |
417 | if (regulator_is_enabled(reg) > 0) { | |
418 | regulator_enable(reg); | |
419 | regulator_disable(reg); | |
420 | } | |
421 | } | |
422 | } | |
423 | ||
424 | return 0; | |
425 | ||
426 | err: | |
427 | mmc_slot(host).set_power = NULL; | |
428 | mmc_slot(host).set_sleep = NULL; | |
429 | return ret; | |
430 | } | |
431 | ||
432 | static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) | |
433 | { | |
434 | regulator_put(host->vcc); | |
435 | regulator_put(host->vcc_aux); | |
436 | mmc_slot(host).set_power = NULL; | |
437 | mmc_slot(host).set_sleep = NULL; | |
438 | } | |
439 | ||
b702b106 AH |
440 | static inline int omap_hsmmc_have_reg(void) |
441 | { | |
442 | return 1; | |
443 | } | |
444 | ||
445 | #else | |
446 | ||
447 | static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) | |
448 | { | |
449 | return -EINVAL; | |
450 | } | |
451 | ||
452 | static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) | |
453 | { | |
454 | } | |
455 | ||
456 | static inline int omap_hsmmc_have_reg(void) | |
457 | { | |
458 | return 0; | |
459 | } | |
460 | ||
461 | #endif | |
462 | ||
463 | static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) | |
464 | { | |
465 | int ret; | |
466 | ||
467 | if (gpio_is_valid(pdata->slots[0].switch_pin)) { | |
468 | pdata->suspend = omap_hsmmc_suspend_cdirq; | |
469 | pdata->resume = omap_hsmmc_resume_cdirq; | |
470 | if (pdata->slots[0].cover) | |
471 | pdata->slots[0].get_cover_state = | |
472 | omap_hsmmc_get_cover_state; | |
473 | else | |
474 | pdata->slots[0].card_detect = omap_hsmmc_card_detect; | |
475 | pdata->slots[0].card_detect_irq = | |
476 | gpio_to_irq(pdata->slots[0].switch_pin); | |
477 | ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); | |
478 | if (ret) | |
479 | return ret; | |
480 | ret = gpio_direction_input(pdata->slots[0].switch_pin); | |
481 | if (ret) | |
482 | goto err_free_sp; | |
483 | } else | |
484 | pdata->slots[0].switch_pin = -EINVAL; | |
485 | ||
486 | if (gpio_is_valid(pdata->slots[0].gpio_wp)) { | |
487 | pdata->slots[0].get_ro = omap_hsmmc_get_wp; | |
488 | ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); | |
489 | if (ret) | |
490 | goto err_free_cd; | |
491 | ret = gpio_direction_input(pdata->slots[0].gpio_wp); | |
492 | if (ret) | |
493 | goto err_free_wp; | |
494 | } else | |
495 | pdata->slots[0].gpio_wp = -EINVAL; | |
496 | ||
497 | return 0; | |
498 | ||
499 | err_free_wp: | |
500 | gpio_free(pdata->slots[0].gpio_wp); | |
501 | err_free_cd: | |
502 | if (gpio_is_valid(pdata->slots[0].switch_pin)) | |
503 | err_free_sp: | |
504 | gpio_free(pdata->slots[0].switch_pin); | |
505 | return ret; | |
506 | } | |
507 | ||
508 | static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) | |
509 | { | |
510 | if (gpio_is_valid(pdata->slots[0].gpio_wp)) | |
511 | gpio_free(pdata->slots[0].gpio_wp); | |
512 | if (gpio_is_valid(pdata->slots[0].switch_pin)) | |
513 | gpio_free(pdata->slots[0].switch_pin); | |
514 | } | |
515 | ||
a45c6cb8 MC |
516 | /* |
517 | * Stop clock to the card | |
518 | */ | |
70a3341a | 519 | static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
520 | { |
521 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
522 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
523 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) | |
524 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); | |
525 | } | |
526 | ||
11dd62a7 DK |
527 | #ifdef CONFIG_PM |
528 | ||
529 | /* | |
530 | * Restore the MMC host context, if it was lost as result of a | |
531 | * power state change. | |
532 | */ | |
70a3341a | 533 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
534 | { |
535 | struct mmc_ios *ios = &host->mmc->ios; | |
536 | struct omap_mmc_platform_data *pdata = host->pdata; | |
537 | int context_loss = 0; | |
538 | u32 hctl, capa, con; | |
539 | u16 dsor = 0; | |
540 | unsigned long timeout; | |
541 | ||
542 | if (pdata->get_context_loss_count) { | |
543 | context_loss = pdata->get_context_loss_count(host->dev); | |
544 | if (context_loss < 0) | |
545 | return 1; | |
546 | } | |
547 | ||
548 | dev_dbg(mmc_dev(host->mmc), "context was %slost\n", | |
549 | context_loss == host->context_loss ? "not " : ""); | |
550 | if (host->context_loss == context_loss) | |
551 | return 1; | |
552 | ||
553 | /* Wait for hardware reset */ | |
554 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
555 | while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE | |
556 | && time_before(jiffies, timeout)) | |
557 | ; | |
558 | ||
559 | /* Do software reset */ | |
560 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); | |
561 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
562 | while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE | |
563 | && time_before(jiffies, timeout)) | |
564 | ; | |
565 | ||
566 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, | |
567 | OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); | |
568 | ||
569 | if (host->id == OMAP_MMC1_DEVID) { | |
570 | if (host->power_mode != MMC_POWER_OFF && | |
571 | (1 << ios->vdd) <= MMC_VDD_23_24) | |
572 | hctl = SDVS18; | |
573 | else | |
574 | hctl = SDVS30; | |
575 | capa = VS30 | VS18; | |
576 | } else { | |
577 | hctl = SDVS18; | |
578 | capa = VS18; | |
579 | } | |
580 | ||
581 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
582 | OMAP_HSMMC_READ(host->base, HCTL) | hctl); | |
583 | ||
584 | OMAP_HSMMC_WRITE(host->base, CAPA, | |
585 | OMAP_HSMMC_READ(host->base, CAPA) | capa); | |
586 | ||
587 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
588 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
589 | ||
590 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
591 | while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP | |
592 | && time_before(jiffies, timeout)) | |
593 | ; | |
594 | ||
595 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
596 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
597 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
598 | ||
599 | /* Do not initialize card-specific things if the power is off */ | |
600 | if (host->power_mode == MMC_POWER_OFF) | |
601 | goto out; | |
602 | ||
603 | con = OMAP_HSMMC_READ(host->base, CON); | |
604 | switch (ios->bus_width) { | |
605 | case MMC_BUS_WIDTH_8: | |
606 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
607 | break; | |
608 | case MMC_BUS_WIDTH_4: | |
609 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
610 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
611 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
612 | break; | |
613 | case MMC_BUS_WIDTH_1: | |
614 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
615 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
616 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
617 | break; | |
618 | } | |
619 | ||
620 | if (ios->clock) { | |
621 | dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; | |
622 | if (dsor < 1) | |
623 | dsor = 1; | |
624 | ||
625 | if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) | |
626 | dsor++; | |
627 | ||
628 | if (dsor > 250) | |
629 | dsor = 250; | |
630 | } | |
631 | ||
632 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
633 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
634 | OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); | |
635 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
636 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
637 | ||
638 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
639 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS | |
640 | && time_before(jiffies, timeout)) | |
641 | ; | |
642 | ||
643 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
644 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
645 | ||
646 | con = OMAP_HSMMC_READ(host->base, CON); | |
647 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
648 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); | |
649 | else | |
650 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
651 | out: | |
652 | host->context_loss = context_loss; | |
653 | ||
654 | dev_dbg(mmc_dev(host->mmc), "context is restored\n"); | |
655 | return 0; | |
656 | } | |
657 | ||
658 | /* | |
659 | * Save the MMC host context (store the number of power state changes so far). | |
660 | */ | |
70a3341a | 661 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
662 | { |
663 | struct omap_mmc_platform_data *pdata = host->pdata; | |
664 | int context_loss; | |
665 | ||
666 | if (pdata->get_context_loss_count) { | |
667 | context_loss = pdata->get_context_loss_count(host->dev); | |
668 | if (context_loss < 0) | |
669 | return; | |
670 | host->context_loss = context_loss; | |
671 | } | |
672 | } | |
673 | ||
674 | #else | |
675 | ||
70a3341a | 676 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
677 | { |
678 | return 0; | |
679 | } | |
680 | ||
70a3341a | 681 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
682 | { |
683 | } | |
684 | ||
685 | #endif | |
686 | ||
a45c6cb8 MC |
687 | /* |
688 | * Send init stream sequence to card | |
689 | * before sending IDLE command | |
690 | */ | |
70a3341a | 691 | static void send_init_stream(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
692 | { |
693 | int reg = 0; | |
694 | unsigned long timeout; | |
695 | ||
b62f6228 AH |
696 | if (host->protect_card) |
697 | return; | |
698 | ||
a45c6cb8 MC |
699 | disable_irq(host->irq); |
700 | OMAP_HSMMC_WRITE(host->base, CON, | |
701 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); | |
702 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); | |
703 | ||
704 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
705 | while ((reg != CC) && time_before(jiffies, timeout)) | |
706 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC; | |
707 | ||
708 | OMAP_HSMMC_WRITE(host->base, CON, | |
709 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); | |
c653a6d4 AH |
710 | |
711 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
712 | OMAP_HSMMC_READ(host->base, STAT); | |
713 | ||
a45c6cb8 MC |
714 | enable_irq(host->irq); |
715 | } | |
716 | ||
717 | static inline | |
70a3341a | 718 | int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
719 | { |
720 | int r = 1; | |
721 | ||
191d1f1d DK |
722 | if (mmc_slot(host).get_cover_state) |
723 | r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); | |
a45c6cb8 MC |
724 | return r; |
725 | } | |
726 | ||
727 | static ssize_t | |
70a3341a | 728 | omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
729 | char *buf) |
730 | { | |
731 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 732 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 733 | |
70a3341a DK |
734 | return sprintf(buf, "%s\n", |
735 | omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); | |
a45c6cb8 MC |
736 | } |
737 | ||
70a3341a | 738 | static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); |
a45c6cb8 MC |
739 | |
740 | static ssize_t | |
70a3341a | 741 | omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
742 | char *buf) |
743 | { | |
744 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 745 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 746 | |
191d1f1d | 747 | return sprintf(buf, "%s\n", mmc_slot(host).name); |
a45c6cb8 MC |
748 | } |
749 | ||
70a3341a | 750 | static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); |
a45c6cb8 MC |
751 | |
752 | /* | |
753 | * Configure the response type and send the cmd. | |
754 | */ | |
755 | static void | |
70a3341a | 756 | omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, |
a45c6cb8 MC |
757 | struct mmc_data *data) |
758 | { | |
759 | int cmdreg = 0, resptype = 0, cmdtype = 0; | |
760 | ||
761 | dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", | |
762 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); | |
763 | host->cmd = cmd; | |
764 | ||
765 | /* | |
766 | * Clear status bits and enable interrupts | |
767 | */ | |
768 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
769 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
ccdfe3a6 AG |
770 | |
771 | if (host->use_dma) | |
772 | OMAP_HSMMC_WRITE(host->base, IE, | |
773 | INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE)); | |
774 | else | |
775 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
a45c6cb8 | 776 | |
4a694dc9 | 777 | host->response_busy = 0; |
a45c6cb8 MC |
778 | if (cmd->flags & MMC_RSP_PRESENT) { |
779 | if (cmd->flags & MMC_RSP_136) | |
780 | resptype = 1; | |
4a694dc9 AH |
781 | else if (cmd->flags & MMC_RSP_BUSY) { |
782 | resptype = 3; | |
783 | host->response_busy = 1; | |
784 | } else | |
a45c6cb8 MC |
785 | resptype = 2; |
786 | } | |
787 | ||
788 | /* | |
789 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on | |
790 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need | |
791 | * a val of 0x3, rest 0x0. | |
792 | */ | |
793 | if (cmd == host->mrq->stop) | |
794 | cmdtype = 0x3; | |
795 | ||
796 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); | |
797 | ||
798 | if (data) { | |
799 | cmdreg |= DP_SELECT | MSBS | BCE; | |
800 | if (data->flags & MMC_DATA_READ) | |
801 | cmdreg |= DDIR; | |
802 | else | |
803 | cmdreg &= ~(DDIR); | |
804 | } | |
805 | ||
806 | if (host->use_dma) | |
807 | cmdreg |= DMA_EN; | |
808 | ||
4dffd7a2 AH |
809 | /* |
810 | * In an interrupt context (i.e. STOP command), the spinlock is unlocked | |
811 | * by the interrupt handler, otherwise (i.e. for a new request) it is | |
812 | * unlocked here. | |
813 | */ | |
814 | if (!in_interrupt()) | |
815 | spin_unlock_irqrestore(&host->irq_lock, host->flags); | |
816 | ||
a45c6cb8 MC |
817 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); |
818 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); | |
819 | } | |
820 | ||
0ccd76d4 | 821 | static int |
70a3341a | 822 | omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) |
0ccd76d4 JY |
823 | { |
824 | if (data->flags & MMC_DATA_WRITE) | |
825 | return DMA_TO_DEVICE; | |
826 | else | |
827 | return DMA_FROM_DEVICE; | |
828 | } | |
829 | ||
a45c6cb8 MC |
830 | /* |
831 | * Notify the transfer complete to MMC core | |
832 | */ | |
833 | static void | |
70a3341a | 834 | omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) |
a45c6cb8 | 835 | { |
4a694dc9 AH |
836 | if (!data) { |
837 | struct mmc_request *mrq = host->mrq; | |
838 | ||
23050103 AH |
839 | /* TC before CC from CMD6 - don't know why, but it happens */ |
840 | if (host->cmd && host->cmd->opcode == 6 && | |
841 | host->response_busy) { | |
842 | host->response_busy = 0; | |
843 | return; | |
844 | } | |
845 | ||
4a694dc9 | 846 | host->mrq = NULL; |
4a694dc9 AH |
847 | mmc_request_done(host->mmc, mrq); |
848 | return; | |
849 | } | |
850 | ||
a45c6cb8 MC |
851 | host->data = NULL; |
852 | ||
853 | if (host->use_dma && host->dma_ch != -1) | |
854 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, | |
70a3341a | 855 | omap_hsmmc_get_dma_dir(host, data)); |
a45c6cb8 MC |
856 | |
857 | if (!data->error) | |
858 | data->bytes_xfered += data->blocks * (data->blksz); | |
859 | else | |
860 | data->bytes_xfered = 0; | |
861 | ||
862 | if (!data->stop) { | |
863 | host->mrq = NULL; | |
864 | mmc_request_done(host->mmc, data->mrq); | |
865 | return; | |
866 | } | |
70a3341a | 867 | omap_hsmmc_start_command(host, data->stop, NULL); |
a45c6cb8 MC |
868 | } |
869 | ||
870 | /* | |
871 | * Notify the core about command completion | |
872 | */ | |
873 | static void | |
70a3341a | 874 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) |
a45c6cb8 MC |
875 | { |
876 | host->cmd = NULL; | |
877 | ||
878 | if (cmd->flags & MMC_RSP_PRESENT) { | |
879 | if (cmd->flags & MMC_RSP_136) { | |
880 | /* response type 2 */ | |
881 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); | |
882 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); | |
883 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); | |
884 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); | |
885 | } else { | |
886 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
887 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); | |
888 | } | |
889 | } | |
4a694dc9 | 890 | if ((host->data == NULL && !host->response_busy) || cmd->error) { |
a45c6cb8 MC |
891 | host->mrq = NULL; |
892 | mmc_request_done(host->mmc, cmd->mrq); | |
893 | } | |
894 | } | |
895 | ||
896 | /* | |
897 | * DMA clean up for command errors | |
898 | */ | |
70a3341a | 899 | static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) |
a45c6cb8 | 900 | { |
82788ff5 | 901 | host->data->error = errno; |
a45c6cb8 MC |
902 | |
903 | if (host->use_dma && host->dma_ch != -1) { | |
904 | dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, | |
70a3341a | 905 | omap_hsmmc_get_dma_dir(host, host->data)); |
a45c6cb8 MC |
906 | omap_free_dma(host->dma_ch); |
907 | host->dma_ch = -1; | |
908 | up(&host->sem); | |
909 | } | |
910 | host->data = NULL; | |
a45c6cb8 MC |
911 | } |
912 | ||
913 | /* | |
914 | * Readable error output | |
915 | */ | |
916 | #ifdef CONFIG_MMC_DEBUG | |
70a3341a | 917 | static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status) |
a45c6cb8 MC |
918 | { |
919 | /* --- means reserved bit without definition at documentation */ | |
70a3341a | 920 | static const char *omap_hsmmc_status_bits[] = { |
a45c6cb8 MC |
921 | "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", |
922 | "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", | |
923 | "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", | |
924 | "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" | |
925 | }; | |
926 | char res[256]; | |
927 | char *buf = res; | |
928 | int len, i; | |
929 | ||
930 | len = sprintf(buf, "MMC IRQ 0x%x :", status); | |
931 | buf += len; | |
932 | ||
70a3341a | 933 | for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) |
a45c6cb8 | 934 | if (status & (1 << i)) { |
70a3341a | 935 | len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); |
a45c6cb8 MC |
936 | buf += len; |
937 | } | |
938 | ||
939 | dev_dbg(mmc_dev(host->mmc), "%s\n", res); | |
940 | } | |
941 | #endif /* CONFIG_MMC_DEBUG */ | |
942 | ||
3ebf74b1 JP |
943 | /* |
944 | * MMC controller internal state machines reset | |
945 | * | |
946 | * Used to reset command or data internal state machines, using respectively | |
947 | * SRC or SRD bit of SYSCTL register | |
948 | * Can be called from interrupt context | |
949 | */ | |
70a3341a DK |
950 | static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, |
951 | unsigned long bit) | |
3ebf74b1 JP |
952 | { |
953 | unsigned long i = 0; | |
954 | unsigned long limit = (loops_per_jiffy * | |
955 | msecs_to_jiffies(MMC_TIMEOUT_MS)); | |
956 | ||
957 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
958 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); | |
959 | ||
960 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && | |
961 | (i++ < limit)) | |
962 | cpu_relax(); | |
963 | ||
964 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) | |
965 | dev_err(mmc_dev(host->mmc), | |
966 | "Timeout waiting on controller reset in %s\n", | |
967 | __func__); | |
968 | } | |
a45c6cb8 MC |
969 | |
970 | /* | |
971 | * MMC controller IRQ handler | |
972 | */ | |
70a3341a | 973 | static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) |
a45c6cb8 | 974 | { |
70a3341a | 975 | struct omap_hsmmc_host *host = dev_id; |
a45c6cb8 MC |
976 | struct mmc_data *data; |
977 | int end_cmd = 0, end_trans = 0, status; | |
978 | ||
4dffd7a2 AH |
979 | spin_lock(&host->irq_lock); |
980 | ||
4a694dc9 | 981 | if (host->mrq == NULL) { |
a45c6cb8 MC |
982 | OMAP_HSMMC_WRITE(host->base, STAT, |
983 | OMAP_HSMMC_READ(host->base, STAT)); | |
00adadc1 KH |
984 | /* Flush posted write */ |
985 | OMAP_HSMMC_READ(host->base, STAT); | |
4dffd7a2 | 986 | spin_unlock(&host->irq_lock); |
a45c6cb8 MC |
987 | return IRQ_HANDLED; |
988 | } | |
989 | ||
990 | data = host->data; | |
991 | status = OMAP_HSMMC_READ(host->base, STAT); | |
992 | dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); | |
993 | ||
994 | if (status & ERR) { | |
995 | #ifdef CONFIG_MMC_DEBUG | |
70a3341a | 996 | omap_hsmmc_report_irq(host, status); |
a45c6cb8 MC |
997 | #endif |
998 | if ((status & CMD_TIMEOUT) || | |
999 | (status & CMD_CRC)) { | |
1000 | if (host->cmd) { | |
1001 | if (status & CMD_TIMEOUT) { | |
70a3341a DK |
1002 | omap_hsmmc_reset_controller_fsm(host, |
1003 | SRC); | |
a45c6cb8 MC |
1004 | host->cmd->error = -ETIMEDOUT; |
1005 | } else { | |
1006 | host->cmd->error = -EILSEQ; | |
1007 | } | |
1008 | end_cmd = 1; | |
1009 | } | |
4a694dc9 AH |
1010 | if (host->data || host->response_busy) { |
1011 | if (host->data) | |
70a3341a DK |
1012 | omap_hsmmc_dma_cleanup(host, |
1013 | -ETIMEDOUT); | |
4a694dc9 | 1014 | host->response_busy = 0; |
70a3341a | 1015 | omap_hsmmc_reset_controller_fsm(host, SRD); |
c232f457 | 1016 | } |
a45c6cb8 MC |
1017 | } |
1018 | if ((status & DATA_TIMEOUT) || | |
1019 | (status & DATA_CRC)) { | |
4a694dc9 AH |
1020 | if (host->data || host->response_busy) { |
1021 | int err = (status & DATA_TIMEOUT) ? | |
1022 | -ETIMEDOUT : -EILSEQ; | |
1023 | ||
1024 | if (host->data) | |
70a3341a | 1025 | omap_hsmmc_dma_cleanup(host, err); |
a45c6cb8 | 1026 | else |
4a694dc9 AH |
1027 | host->mrq->cmd->error = err; |
1028 | host->response_busy = 0; | |
70a3341a | 1029 | omap_hsmmc_reset_controller_fsm(host, SRD); |
a45c6cb8 MC |
1030 | end_trans = 1; |
1031 | } | |
1032 | } | |
1033 | if (status & CARD_ERR) { | |
1034 | dev_dbg(mmc_dev(host->mmc), | |
1035 | "Ignoring card err CMD%d\n", host->cmd->opcode); | |
1036 | if (host->cmd) | |
1037 | end_cmd = 1; | |
1038 | if (host->data) | |
1039 | end_trans = 1; | |
1040 | } | |
1041 | } | |
1042 | ||
1043 | OMAP_HSMMC_WRITE(host->base, STAT, status); | |
00adadc1 KH |
1044 | /* Flush posted write */ |
1045 | OMAP_HSMMC_READ(host->base, STAT); | |
a45c6cb8 | 1046 | |
a8fe29d8 | 1047 | if (end_cmd || ((status & CC) && host->cmd)) |
70a3341a | 1048 | omap_hsmmc_cmd_done(host, host->cmd); |
0a40e647 | 1049 | if ((end_trans || (status & TC)) && host->mrq) |
70a3341a | 1050 | omap_hsmmc_xfer_done(host, data); |
a45c6cb8 | 1051 | |
4dffd7a2 AH |
1052 | spin_unlock(&host->irq_lock); |
1053 | ||
a45c6cb8 MC |
1054 | return IRQ_HANDLED; |
1055 | } | |
1056 | ||
70a3341a | 1057 | static void set_sd_bus_power(struct omap_hsmmc_host *host) |
e13bb300 AH |
1058 | { |
1059 | unsigned long i; | |
1060 | ||
1061 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
1062 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
1063 | for (i = 0; i < loops_per_jiffy; i++) { | |
1064 | if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) | |
1065 | break; | |
1066 | cpu_relax(); | |
1067 | } | |
1068 | } | |
1069 | ||
a45c6cb8 | 1070 | /* |
eb250826 DB |
1071 | * Switch MMC interface voltage ... only relevant for MMC1. |
1072 | * | |
1073 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. | |
1074 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. | |
1075 | * Some chips, like eMMC ones, use internal transceivers. | |
a45c6cb8 | 1076 | */ |
70a3341a | 1077 | static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) |
a45c6cb8 MC |
1078 | { |
1079 | u32 reg_val = 0; | |
1080 | int ret; | |
1081 | ||
1082 | /* Disable the clocks */ | |
1083 | clk_disable(host->fclk); | |
1084 | clk_disable(host->iclk); | |
2bec0893 AH |
1085 | if (host->got_dbclk) |
1086 | clk_disable(host->dbclk); | |
a45c6cb8 MC |
1087 | |
1088 | /* Turn the power off */ | |
1089 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); | |
a45c6cb8 MC |
1090 | |
1091 | /* Turn the power ON with given VDD 1.8 or 3.0v */ | |
2bec0893 AH |
1092 | if (!ret) |
1093 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, | |
1094 | vdd); | |
1095 | clk_enable(host->iclk); | |
1096 | clk_enable(host->fclk); | |
1097 | if (host->got_dbclk) | |
1098 | clk_enable(host->dbclk); | |
1099 | ||
a45c6cb8 MC |
1100 | if (ret != 0) |
1101 | goto err; | |
1102 | ||
a45c6cb8 MC |
1103 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1104 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); | |
1105 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); | |
eb250826 | 1106 | |
a45c6cb8 MC |
1107 | /* |
1108 | * If a MMC dual voltage card is detected, the set_ios fn calls | |
1109 | * this fn with VDD bit set for 1.8V. Upon card removal from the | |
70a3341a | 1110 | * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. |
a45c6cb8 | 1111 | * |
eb250826 DB |
1112 | * Cope with a bit of slop in the range ... per data sheets: |
1113 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, | |
1114 | * but recommended values are 1.71V to 1.89V | |
1115 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, | |
1116 | * but recommended values are 2.7V to 3.3V | |
1117 | * | |
1118 | * Board setup code shouldn't permit anything very out-of-range. | |
1119 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the | |
1120 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. | |
a45c6cb8 | 1121 | */ |
eb250826 | 1122 | if ((1 << vdd) <= MMC_VDD_23_24) |
a45c6cb8 | 1123 | reg_val |= SDVS18; |
eb250826 DB |
1124 | else |
1125 | reg_val |= SDVS30; | |
a45c6cb8 MC |
1126 | |
1127 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); | |
e13bb300 | 1128 | set_sd_bus_power(host); |
a45c6cb8 MC |
1129 | |
1130 | return 0; | |
1131 | err: | |
1132 | dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); | |
1133 | return ret; | |
1134 | } | |
1135 | ||
b62f6228 AH |
1136 | /* Protect the card while the cover is open */ |
1137 | static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) | |
1138 | { | |
1139 | if (!mmc_slot(host).get_cover_state) | |
1140 | return; | |
1141 | ||
1142 | host->reqs_blocked = 0; | |
1143 | if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { | |
1144 | if (host->protect_card) { | |
1145 | printk(KERN_INFO "%s: cover is closed, " | |
1146 | "card is now accessible\n", | |
1147 | mmc_hostname(host->mmc)); | |
1148 | host->protect_card = 0; | |
1149 | } | |
1150 | } else { | |
1151 | if (!host->protect_card) { | |
1152 | printk(KERN_INFO "%s: cover is open, " | |
1153 | "card is now inaccessible\n", | |
1154 | mmc_hostname(host->mmc)); | |
1155 | host->protect_card = 1; | |
1156 | } | |
1157 | } | |
1158 | } | |
1159 | ||
a45c6cb8 MC |
1160 | /* |
1161 | * Work Item to notify the core about card insertion/removal | |
1162 | */ | |
70a3341a | 1163 | static void omap_hsmmc_detect(struct work_struct *work) |
a45c6cb8 | 1164 | { |
70a3341a DK |
1165 | struct omap_hsmmc_host *host = |
1166 | container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); | |
249d0fa9 | 1167 | struct omap_mmc_slot_data *slot = &mmc_slot(host); |
a6b2240d AH |
1168 | int carddetect; |
1169 | ||
1170 | if (host->suspended) | |
1171 | return; | |
1172 | ||
1173 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); | |
249d0fa9 | 1174 | |
191d1f1d | 1175 | if (slot->card_detect) |
db0fefc5 | 1176 | carddetect = slot->card_detect(host->dev, host->slot_id); |
b62f6228 AH |
1177 | else { |
1178 | omap_hsmmc_protect_card(host); | |
a6b2240d | 1179 | carddetect = -ENOSYS; |
b62f6228 | 1180 | } |
a45c6cb8 | 1181 | |
a6b2240d | 1182 | if (carddetect) { |
a45c6cb8 MC |
1183 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); |
1184 | } else { | |
5e2ea617 | 1185 | mmc_host_enable(host->mmc); |
70a3341a | 1186 | omap_hsmmc_reset_controller_fsm(host, SRD); |
5e2ea617 | 1187 | mmc_host_lazy_disable(host->mmc); |
70a3341a | 1188 | |
a45c6cb8 MC |
1189 | mmc_detect_change(host->mmc, (HZ * 50) / 1000); |
1190 | } | |
1191 | } | |
1192 | ||
1193 | /* | |
1194 | * ISR for handling card insertion and removal | |
1195 | */ | |
70a3341a | 1196 | static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) |
a45c6cb8 | 1197 | { |
70a3341a | 1198 | struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; |
a45c6cb8 | 1199 | |
a6b2240d AH |
1200 | if (host->suspended) |
1201 | return IRQ_HANDLED; | |
a45c6cb8 MC |
1202 | schedule_work(&host->mmc_carddetect_work); |
1203 | ||
1204 | return IRQ_HANDLED; | |
1205 | } | |
1206 | ||
70a3341a | 1207 | static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, |
0ccd76d4 JY |
1208 | struct mmc_data *data) |
1209 | { | |
1210 | int sync_dev; | |
1211 | ||
f3e2f1dd GI |
1212 | if (data->flags & MMC_DATA_WRITE) |
1213 | sync_dev = host->dma_line_tx; | |
1214 | else | |
1215 | sync_dev = host->dma_line_rx; | |
0ccd76d4 JY |
1216 | return sync_dev; |
1217 | } | |
1218 | ||
70a3341a | 1219 | static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, |
0ccd76d4 JY |
1220 | struct mmc_data *data, |
1221 | struct scatterlist *sgl) | |
1222 | { | |
1223 | int blksz, nblk, dma_ch; | |
1224 | ||
1225 | dma_ch = host->dma_ch; | |
1226 | if (data->flags & MMC_DATA_WRITE) { | |
1227 | omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
1228 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); | |
1229 | omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, | |
1230 | sg_dma_address(sgl), 0, 0); | |
1231 | } else { | |
1232 | omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
191d1f1d | 1233 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); |
0ccd76d4 JY |
1234 | omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, |
1235 | sg_dma_address(sgl), 0, 0); | |
1236 | } | |
1237 | ||
1238 | blksz = host->data->blksz; | |
1239 | nblk = sg_dma_len(sgl) / blksz; | |
1240 | ||
1241 | omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, | |
1242 | blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, | |
70a3341a | 1243 | omap_hsmmc_get_dma_sync_dev(host, data), |
0ccd76d4 JY |
1244 | !(data->flags & MMC_DATA_WRITE)); |
1245 | ||
1246 | omap_start_dma(dma_ch); | |
1247 | } | |
1248 | ||
a45c6cb8 MC |
1249 | /* |
1250 | * DMA call back function | |
1251 | */ | |
70a3341a | 1252 | static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data) |
a45c6cb8 | 1253 | { |
70a3341a | 1254 | struct omap_hsmmc_host *host = data; |
a45c6cb8 MC |
1255 | |
1256 | if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ) | |
1257 | dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n"); | |
1258 | ||
1259 | if (host->dma_ch < 0) | |
1260 | return; | |
1261 | ||
0ccd76d4 JY |
1262 | host->dma_sg_idx++; |
1263 | if (host->dma_sg_idx < host->dma_len) { | |
1264 | /* Fire up the next transfer. */ | |
70a3341a | 1265 | omap_hsmmc_config_dma_params(host, host->data, |
0ccd76d4 JY |
1266 | host->data->sg + host->dma_sg_idx); |
1267 | return; | |
1268 | } | |
1269 | ||
a45c6cb8 MC |
1270 | omap_free_dma(host->dma_ch); |
1271 | host->dma_ch = -1; | |
1272 | /* | |
1273 | * DMA Callback: run in interrupt context. | |
85b84322 | 1274 | * mutex_unlock will throw a kernel warning if used. |
a45c6cb8 MC |
1275 | */ |
1276 | up(&host->sem); | |
1277 | } | |
1278 | ||
a45c6cb8 MC |
1279 | /* |
1280 | * Routine to configure and start DMA for the MMC card | |
1281 | */ | |
70a3341a DK |
1282 | static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, |
1283 | struct mmc_request *req) | |
a45c6cb8 | 1284 | { |
0ccd76d4 | 1285 | int dma_ch = 0, ret = 0, err = 1, i; |
a45c6cb8 MC |
1286 | struct mmc_data *data = req->data; |
1287 | ||
0ccd76d4 | 1288 | /* Sanity check: all the SG entries must be aligned by block size. */ |
a3f406f8 | 1289 | for (i = 0; i < data->sg_len; i++) { |
0ccd76d4 JY |
1290 | struct scatterlist *sgl; |
1291 | ||
1292 | sgl = data->sg + i; | |
1293 | if (sgl->length % data->blksz) | |
1294 | return -EINVAL; | |
1295 | } | |
1296 | if ((data->blksz % 4) != 0) | |
1297 | /* REVISIT: The MMC buffer increments only when MSB is written. | |
1298 | * Return error for blksz which is non multiple of four. | |
1299 | */ | |
1300 | return -EINVAL; | |
1301 | ||
a45c6cb8 MC |
1302 | /* |
1303 | * If for some reason the DMA transfer is still active, | |
1304 | * we wait for timeout period and free the dma | |
1305 | */ | |
1306 | if (host->dma_ch != -1) { | |
1307 | set_current_state(TASK_UNINTERRUPTIBLE); | |
1308 | schedule_timeout(100); | |
1309 | if (down_trylock(&host->sem)) { | |
1310 | omap_free_dma(host->dma_ch); | |
1311 | host->dma_ch = -1; | |
1312 | up(&host->sem); | |
1313 | return err; | |
1314 | } | |
1315 | } else { | |
1316 | if (down_trylock(&host->sem)) | |
1317 | return err; | |
1318 | } | |
1319 | ||
70a3341a DK |
1320 | ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), |
1321 | "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); | |
a45c6cb8 | 1322 | if (ret != 0) { |
0ccd76d4 | 1323 | dev_err(mmc_dev(host->mmc), |
a45c6cb8 MC |
1324 | "%s: omap_request_dma() failed with %d\n", |
1325 | mmc_hostname(host->mmc), ret); | |
1326 | return ret; | |
1327 | } | |
1328 | ||
1329 | host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
70a3341a | 1330 | data->sg_len, omap_hsmmc_get_dma_dir(host, data)); |
a45c6cb8 | 1331 | host->dma_ch = dma_ch; |
0ccd76d4 | 1332 | host->dma_sg_idx = 0; |
a45c6cb8 | 1333 | |
70a3341a | 1334 | omap_hsmmc_config_dma_params(host, data, data->sg); |
a45c6cb8 | 1335 | |
a45c6cb8 MC |
1336 | return 0; |
1337 | } | |
1338 | ||
70a3341a | 1339 | static void set_data_timeout(struct omap_hsmmc_host *host, |
e2bf08d6 AH |
1340 | unsigned int timeout_ns, |
1341 | unsigned int timeout_clks) | |
a45c6cb8 MC |
1342 | { |
1343 | unsigned int timeout, cycle_ns; | |
1344 | uint32_t reg, clkd, dto = 0; | |
1345 | ||
1346 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); | |
1347 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; | |
1348 | if (clkd == 0) | |
1349 | clkd = 1; | |
1350 | ||
1351 | cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); | |
e2bf08d6 AH |
1352 | timeout = timeout_ns / cycle_ns; |
1353 | timeout += timeout_clks; | |
a45c6cb8 MC |
1354 | if (timeout) { |
1355 | while ((timeout & 0x80000000) == 0) { | |
1356 | dto += 1; | |
1357 | timeout <<= 1; | |
1358 | } | |
1359 | dto = 31 - dto; | |
1360 | timeout <<= 1; | |
1361 | if (timeout && dto) | |
1362 | dto += 1; | |
1363 | if (dto >= 13) | |
1364 | dto -= 13; | |
1365 | else | |
1366 | dto = 0; | |
1367 | if (dto > 14) | |
1368 | dto = 14; | |
1369 | } | |
1370 | ||
1371 | reg &= ~DTO_MASK; | |
1372 | reg |= dto << DTO_SHIFT; | |
1373 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); | |
1374 | } | |
1375 | ||
1376 | /* | |
1377 | * Configure block length for MMC/SD cards and initiate the transfer. | |
1378 | */ | |
1379 | static int | |
70a3341a | 1380 | omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) |
a45c6cb8 MC |
1381 | { |
1382 | int ret; | |
1383 | host->data = req->data; | |
1384 | ||
1385 | if (req->data == NULL) { | |
a45c6cb8 | 1386 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
e2bf08d6 AH |
1387 | /* |
1388 | * Set an arbitrary 100ms data timeout for commands with | |
1389 | * busy signal. | |
1390 | */ | |
1391 | if (req->cmd->flags & MMC_RSP_BUSY) | |
1392 | set_data_timeout(host, 100000000U, 0); | |
a45c6cb8 MC |
1393 | return 0; |
1394 | } | |
1395 | ||
1396 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) | |
1397 | | (req->data->blocks << 16)); | |
e2bf08d6 | 1398 | set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); |
a45c6cb8 | 1399 | |
a45c6cb8 | 1400 | if (host->use_dma) { |
70a3341a | 1401 | ret = omap_hsmmc_start_dma_transfer(host, req); |
a45c6cb8 MC |
1402 | if (ret != 0) { |
1403 | dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); | |
1404 | return ret; | |
1405 | } | |
1406 | } | |
1407 | return 0; | |
1408 | } | |
1409 | ||
1410 | /* | |
1411 | * Request function. for read/write operation | |
1412 | */ | |
70a3341a | 1413 | static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) |
a45c6cb8 | 1414 | { |
70a3341a | 1415 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3f406f8 | 1416 | int err; |
a45c6cb8 | 1417 | |
4dffd7a2 AH |
1418 | /* |
1419 | * Prevent races with the interrupt handler because of unexpected | |
1420 | * interrupts, but not if we are already in interrupt context i.e. | |
1421 | * retries. | |
1422 | */ | |
b62f6228 | 1423 | if (!in_interrupt()) { |
4dffd7a2 | 1424 | spin_lock_irqsave(&host->irq_lock, host->flags); |
b62f6228 AH |
1425 | /* |
1426 | * Protect the card from I/O if there is a possibility | |
1427 | * it can be removed. | |
1428 | */ | |
1429 | if (host->protect_card) { | |
1430 | if (host->reqs_blocked < 3) { | |
1431 | /* | |
1432 | * Ensure the controller is left in a consistent | |
1433 | * state by resetting the command and data state | |
1434 | * machines. | |
1435 | */ | |
1436 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
1437 | omap_hsmmc_reset_controller_fsm(host, SRC); | |
1438 | host->reqs_blocked += 1; | |
1439 | } | |
1440 | req->cmd->error = -EBADF; | |
1441 | if (req->data) | |
1442 | req->data->error = -EBADF; | |
1443 | spin_unlock_irqrestore(&host->irq_lock, host->flags); | |
1444 | mmc_request_done(mmc, req); | |
1445 | return; | |
1446 | } else if (host->reqs_blocked) | |
1447 | host->reqs_blocked = 0; | |
1448 | } | |
a45c6cb8 MC |
1449 | WARN_ON(host->mrq != NULL); |
1450 | host->mrq = req; | |
70a3341a | 1451 | err = omap_hsmmc_prepare_data(host, req); |
a3f406f8 JL |
1452 | if (err) { |
1453 | req->cmd->error = err; | |
1454 | if (req->data) | |
1455 | req->data->error = err; | |
1456 | host->mrq = NULL; | |
4dffd7a2 AH |
1457 | if (!in_interrupt()) |
1458 | spin_unlock_irqrestore(&host->irq_lock, host->flags); | |
a3f406f8 JL |
1459 | mmc_request_done(mmc, req); |
1460 | return; | |
1461 | } | |
1462 | ||
70a3341a | 1463 | omap_hsmmc_start_command(host, req->cmd, req->data); |
a45c6cb8 MC |
1464 | } |
1465 | ||
a45c6cb8 | 1466 | /* Routine to configure clock values. Exposed API to core */ |
70a3341a | 1467 | static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
a45c6cb8 | 1468 | { |
70a3341a | 1469 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 MC |
1470 | u16 dsor = 0; |
1471 | unsigned long regval; | |
1472 | unsigned long timeout; | |
73153010 | 1473 | u32 con; |
a3621465 | 1474 | int do_send_init_stream = 0; |
a45c6cb8 | 1475 | |
5e2ea617 AH |
1476 | mmc_host_enable(host->mmc); |
1477 | ||
a3621465 AH |
1478 | if (ios->power_mode != host->power_mode) { |
1479 | switch (ios->power_mode) { | |
1480 | case MMC_POWER_OFF: | |
1481 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1482 | 0, 0); | |
623821f7 | 1483 | host->vdd = 0; |
a3621465 AH |
1484 | break; |
1485 | case MMC_POWER_UP: | |
1486 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1487 | 1, ios->vdd); | |
623821f7 | 1488 | host->vdd = ios->vdd; |
a3621465 AH |
1489 | break; |
1490 | case MMC_POWER_ON: | |
1491 | do_send_init_stream = 1; | |
1492 | break; | |
1493 | } | |
1494 | host->power_mode = ios->power_mode; | |
a45c6cb8 MC |
1495 | } |
1496 | ||
dd498eff DK |
1497 | /* FIXME: set registers based only on changes to ios */ |
1498 | ||
73153010 | 1499 | con = OMAP_HSMMC_READ(host->base, CON); |
a45c6cb8 | 1500 | switch (mmc->ios.bus_width) { |
73153010 JL |
1501 | case MMC_BUS_WIDTH_8: |
1502 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
1503 | break; | |
a45c6cb8 | 1504 | case MMC_BUS_WIDTH_4: |
73153010 | 1505 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); |
a45c6cb8 MC |
1506 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1507 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
1508 | break; | |
1509 | case MMC_BUS_WIDTH_1: | |
73153010 | 1510 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); |
a45c6cb8 MC |
1511 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1512 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
1513 | break; | |
1514 | } | |
1515 | ||
1516 | if (host->id == OMAP_MMC1_DEVID) { | |
eb250826 DB |
1517 | /* Only MMC1 can interface at 3V without some flavor |
1518 | * of external transceiver; but they all handle 1.8V. | |
1519 | */ | |
a45c6cb8 MC |
1520 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
1521 | (ios->vdd == DUAL_VOLT_OCR_BIT)) { | |
1522 | /* | |
1523 | * The mmc_select_voltage fn of the core does | |
1524 | * not seem to set the power_mode to | |
1525 | * MMC_POWER_UP upon recalculating the voltage. | |
1526 | * vdd 1.8v. | |
1527 | */ | |
70a3341a DK |
1528 | if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) |
1529 | dev_dbg(mmc_dev(host->mmc), | |
a45c6cb8 MC |
1530 | "Switch operation failed\n"); |
1531 | } | |
1532 | } | |
1533 | ||
1534 | if (ios->clock) { | |
1535 | dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; | |
1536 | if (dsor < 1) | |
1537 | dsor = 1; | |
1538 | ||
1539 | if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) | |
1540 | dsor++; | |
1541 | ||
1542 | if (dsor > 250) | |
1543 | dsor = 250; | |
1544 | } | |
70a3341a | 1545 | omap_hsmmc_stop_clock(host); |
a45c6cb8 MC |
1546 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); |
1547 | regval = regval & ~(CLKD_MASK); | |
1548 | regval = regval | (dsor << 6) | (DTO << 16); | |
1549 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); | |
1550 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
1551 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
1552 | ||
1553 | /* Wait till the ICS bit is set */ | |
1554 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
11dd62a7 | 1555 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS |
a45c6cb8 MC |
1556 | && time_before(jiffies, timeout)) |
1557 | msleep(1); | |
1558 | ||
1559 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
1560 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
1561 | ||
a3621465 | 1562 | if (do_send_init_stream) |
a45c6cb8 MC |
1563 | send_init_stream(host); |
1564 | ||
abb28e73 | 1565 | con = OMAP_HSMMC_READ(host->base, CON); |
a45c6cb8 | 1566 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) |
abb28e73 DK |
1567 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); |
1568 | else | |
1569 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
5e2ea617 | 1570 | |
dd498eff DK |
1571 | if (host->power_mode == MMC_POWER_OFF) |
1572 | mmc_host_disable(host->mmc); | |
1573 | else | |
1574 | mmc_host_lazy_disable(host->mmc); | |
a45c6cb8 MC |
1575 | } |
1576 | ||
1577 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) | |
1578 | { | |
70a3341a | 1579 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1580 | |
191d1f1d | 1581 | if (!mmc_slot(host).card_detect) |
a45c6cb8 | 1582 | return -ENOSYS; |
db0fefc5 | 1583 | return mmc_slot(host).card_detect(host->dev, host->slot_id); |
a45c6cb8 MC |
1584 | } |
1585 | ||
1586 | static int omap_hsmmc_get_ro(struct mmc_host *mmc) | |
1587 | { | |
70a3341a | 1588 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1589 | |
191d1f1d | 1590 | if (!mmc_slot(host).get_ro) |
a45c6cb8 | 1591 | return -ENOSYS; |
191d1f1d | 1592 | return mmc_slot(host).get_ro(host->dev, 0); |
a45c6cb8 MC |
1593 | } |
1594 | ||
70a3341a | 1595 | static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) |
1b331e69 KK |
1596 | { |
1597 | u32 hctl, capa, value; | |
1598 | ||
1599 | /* Only MMC1 supports 3.0V */ | |
1600 | if (host->id == OMAP_MMC1_DEVID) { | |
1601 | hctl = SDVS30; | |
1602 | capa = VS30 | VS18; | |
1603 | } else { | |
1604 | hctl = SDVS18; | |
1605 | capa = VS18; | |
1606 | } | |
1607 | ||
1608 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; | |
1609 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); | |
1610 | ||
1611 | value = OMAP_HSMMC_READ(host->base, CAPA); | |
1612 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); | |
1613 | ||
1614 | /* Set the controller to AUTO IDLE mode */ | |
1615 | value = OMAP_HSMMC_READ(host->base, SYSCONFIG); | |
1616 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); | |
1617 | ||
1618 | /* Set SD bus power bit */ | |
e13bb300 | 1619 | set_sd_bus_power(host); |
1b331e69 KK |
1620 | } |
1621 | ||
dd498eff DK |
1622 | /* |
1623 | * Dynamic power saving handling, FSM: | |
13189e78 JL |
1624 | * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF |
1625 | * ^___________| | | | |
1626 | * |______________________|______________________| | |
dd498eff DK |
1627 | * |
1628 | * ENABLED: mmc host is fully functional | |
1629 | * DISABLED: fclk is off | |
13189e78 JL |
1630 | * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep |
1631 | * REGSLEEP: fclk is off, voltage regulator is asleep | |
1632 | * OFF: fclk is off, voltage regulator is off | |
dd498eff DK |
1633 | * |
1634 | * Transition handlers return the timeout for the next state transition | |
1635 | * or negative error. | |
1636 | */ | |
1637 | ||
13189e78 | 1638 | enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF}; |
dd498eff DK |
1639 | |
1640 | /* Handler for [ENABLED -> DISABLED] transition */ | |
70a3341a | 1641 | static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host) |
dd498eff | 1642 | { |
70a3341a | 1643 | omap_hsmmc_context_save(host); |
dd498eff DK |
1644 | clk_disable(host->fclk); |
1645 | host->dpm_state = DISABLED; | |
1646 | ||
1647 | dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n"); | |
1648 | ||
1649 | if (host->power_mode == MMC_POWER_OFF) | |
1650 | return 0; | |
1651 | ||
4380eea2 | 1652 | return OMAP_MMC_SLEEP_TIMEOUT; |
dd498eff DK |
1653 | } |
1654 | ||
13189e78 | 1655 | /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */ |
70a3341a | 1656 | static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host) |
dd498eff | 1657 | { |
13189e78 | 1658 | int err, new_state; |
dd498eff DK |
1659 | |
1660 | if (!mmc_try_claim_host(host->mmc)) | |
1661 | return 0; | |
1662 | ||
1663 | clk_enable(host->fclk); | |
70a3341a | 1664 | omap_hsmmc_context_restore(host); |
13189e78 JL |
1665 | if (mmc_card_can_sleep(host->mmc)) { |
1666 | err = mmc_card_sleep(host->mmc); | |
1667 | if (err < 0) { | |
1668 | clk_disable(host->fclk); | |
1669 | mmc_release_host(host->mmc); | |
1670 | return err; | |
1671 | } | |
1672 | new_state = CARDSLEEP; | |
70a3341a | 1673 | } else { |
13189e78 | 1674 | new_state = REGSLEEP; |
70a3341a | 1675 | } |
13189e78 JL |
1676 | if (mmc_slot(host).set_sleep) |
1677 | mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0, | |
1678 | new_state == CARDSLEEP); | |
1679 | /* FIXME: turn off bus power and perhaps interrupts too */ | |
1680 | clk_disable(host->fclk); | |
1681 | host->dpm_state = new_state; | |
1682 | ||
1683 | mmc_release_host(host->mmc); | |
1684 | ||
1685 | dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n", | |
1686 | host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); | |
dd498eff | 1687 | |
1df58db8 AH |
1688 | if (mmc_slot(host).no_off) |
1689 | return 0; | |
1690 | ||
dd498eff DK |
1691 | if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || |
1692 | mmc_slot(host).card_detect || | |
1693 | (mmc_slot(host).get_cover_state && | |
13189e78 | 1694 | mmc_slot(host).get_cover_state(host->dev, host->slot_id))) |
4380eea2 | 1695 | return OMAP_MMC_OFF_TIMEOUT; |
13189e78 JL |
1696 | |
1697 | return 0; | |
1698 | } | |
1699 | ||
1700 | /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */ | |
70a3341a | 1701 | static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host) |
13189e78 JL |
1702 | { |
1703 | if (!mmc_try_claim_host(host->mmc)) | |
1704 | return 0; | |
1705 | ||
1df58db8 AH |
1706 | if (mmc_slot(host).no_off) |
1707 | return 0; | |
1708 | ||
13189e78 JL |
1709 | if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) || |
1710 | mmc_slot(host).card_detect || | |
1711 | (mmc_slot(host).get_cover_state && | |
1712 | mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) { | |
1713 | mmc_release_host(host->mmc); | |
1714 | return 0; | |
623821f7 | 1715 | } |
dd498eff | 1716 | |
13189e78 JL |
1717 | mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); |
1718 | host->vdd = 0; | |
1719 | host->power_mode = MMC_POWER_OFF; | |
dd498eff | 1720 | |
13189e78 JL |
1721 | dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n", |
1722 | host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); | |
dd498eff | 1723 | |
13189e78 | 1724 | host->dpm_state = OFF; |
dd498eff DK |
1725 | |
1726 | mmc_release_host(host->mmc); | |
1727 | ||
1728 | return 0; | |
1729 | } | |
1730 | ||
1731 | /* Handler for [DISABLED -> ENABLED] transition */ | |
70a3341a | 1732 | static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host) |
dd498eff DK |
1733 | { |
1734 | int err; | |
1735 | ||
1736 | err = clk_enable(host->fclk); | |
1737 | if (err < 0) | |
1738 | return err; | |
1739 | ||
70a3341a | 1740 | omap_hsmmc_context_restore(host); |
dd498eff DK |
1741 | host->dpm_state = ENABLED; |
1742 | ||
1743 | dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n"); | |
1744 | ||
1745 | return 0; | |
1746 | } | |
1747 | ||
13189e78 | 1748 | /* Handler for [SLEEP -> ENABLED] transition */ |
70a3341a | 1749 | static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host) |
dd498eff | 1750 | { |
13189e78 JL |
1751 | if (!mmc_try_claim_host(host->mmc)) |
1752 | return 0; | |
dd498eff | 1753 | |
13189e78 | 1754 | clk_enable(host->fclk); |
70a3341a | 1755 | omap_hsmmc_context_restore(host); |
13189e78 JL |
1756 | if (mmc_slot(host).set_sleep) |
1757 | mmc_slot(host).set_sleep(host->dev, host->slot_id, 0, | |
1758 | host->vdd, host->dpm_state == CARDSLEEP); | |
1759 | if (mmc_card_can_sleep(host->mmc)) | |
1760 | mmc_card_awake(host->mmc); | |
1761 | ||
1762 | dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n", | |
1763 | host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); | |
dd498eff DK |
1764 | |
1765 | host->dpm_state = ENABLED; | |
1766 | ||
13189e78 | 1767 | mmc_release_host(host->mmc); |
dd498eff DK |
1768 | |
1769 | return 0; | |
1770 | } | |
1771 | ||
13189e78 | 1772 | /* Handler for [OFF -> ENABLED] transition */ |
70a3341a | 1773 | static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host) |
623821f7 | 1774 | { |
623821f7 | 1775 | clk_enable(host->fclk); |
623821f7 | 1776 | |
70a3341a DK |
1777 | omap_hsmmc_context_restore(host); |
1778 | omap_hsmmc_conf_bus_power(host); | |
13189e78 | 1779 | mmc_power_restore_host(host->mmc); |
623821f7 AH |
1780 | |
1781 | host->dpm_state = ENABLED; | |
1782 | ||
13189e78 JL |
1783 | dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n"); |
1784 | ||
623821f7 AH |
1785 | return 0; |
1786 | } | |
1787 | ||
dd498eff DK |
1788 | /* |
1789 | * Bring MMC host to ENABLED from any other PM state. | |
1790 | */ | |
70a3341a | 1791 | static int omap_hsmmc_enable(struct mmc_host *mmc) |
dd498eff | 1792 | { |
70a3341a | 1793 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff DK |
1794 | |
1795 | switch (host->dpm_state) { | |
1796 | case DISABLED: | |
70a3341a | 1797 | return omap_hsmmc_disabled_to_enabled(host); |
13189e78 | 1798 | case CARDSLEEP: |
623821f7 | 1799 | case REGSLEEP: |
70a3341a | 1800 | return omap_hsmmc_sleep_to_enabled(host); |
dd498eff | 1801 | case OFF: |
70a3341a | 1802 | return omap_hsmmc_off_to_enabled(host); |
dd498eff DK |
1803 | default: |
1804 | dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); | |
1805 | return -EINVAL; | |
1806 | } | |
1807 | } | |
1808 | ||
1809 | /* | |
1810 | * Bring MMC host in PM state (one level deeper). | |
1811 | */ | |
70a3341a | 1812 | static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy) |
dd498eff | 1813 | { |
70a3341a | 1814 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff DK |
1815 | |
1816 | switch (host->dpm_state) { | |
1817 | case ENABLED: { | |
1818 | int delay; | |
1819 | ||
70a3341a | 1820 | delay = omap_hsmmc_enabled_to_disabled(host); |
dd498eff DK |
1821 | if (lazy || delay < 0) |
1822 | return delay; | |
1823 | return 0; | |
1824 | } | |
1825 | case DISABLED: | |
70a3341a | 1826 | return omap_hsmmc_disabled_to_sleep(host); |
13189e78 JL |
1827 | case CARDSLEEP: |
1828 | case REGSLEEP: | |
70a3341a | 1829 | return omap_hsmmc_sleep_to_off(host); |
dd498eff DK |
1830 | default: |
1831 | dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); | |
1832 | return -EINVAL; | |
1833 | } | |
1834 | } | |
1835 | ||
70a3341a | 1836 | static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) |
dd498eff | 1837 | { |
70a3341a | 1838 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff DK |
1839 | int err; |
1840 | ||
1841 | err = clk_enable(host->fclk); | |
1842 | if (err) | |
1843 | return err; | |
1844 | dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n"); | |
70a3341a | 1845 | omap_hsmmc_context_restore(host); |
dd498eff DK |
1846 | return 0; |
1847 | } | |
1848 | ||
70a3341a | 1849 | static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) |
dd498eff | 1850 | { |
70a3341a | 1851 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1852 | |
70a3341a | 1853 | omap_hsmmc_context_save(host); |
dd498eff DK |
1854 | clk_disable(host->fclk); |
1855 | dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n"); | |
1856 | return 0; | |
1857 | } | |
1858 | ||
70a3341a DK |
1859 | static const struct mmc_host_ops omap_hsmmc_ops = { |
1860 | .enable = omap_hsmmc_enable_fclk, | |
1861 | .disable = omap_hsmmc_disable_fclk, | |
1862 | .request = omap_hsmmc_request, | |
1863 | .set_ios = omap_hsmmc_set_ios, | |
dd498eff DK |
1864 | .get_cd = omap_hsmmc_get_cd, |
1865 | .get_ro = omap_hsmmc_get_ro, | |
1866 | /* NYET -- enable_sdio_irq */ | |
1867 | }; | |
1868 | ||
70a3341a DK |
1869 | static const struct mmc_host_ops omap_hsmmc_ps_ops = { |
1870 | .enable = omap_hsmmc_enable, | |
1871 | .disable = omap_hsmmc_disable, | |
1872 | .request = omap_hsmmc_request, | |
1873 | .set_ios = omap_hsmmc_set_ios, | |
a45c6cb8 MC |
1874 | .get_cd = omap_hsmmc_get_cd, |
1875 | .get_ro = omap_hsmmc_get_ro, | |
1876 | /* NYET -- enable_sdio_irq */ | |
1877 | }; | |
1878 | ||
d900f712 DK |
1879 | #ifdef CONFIG_DEBUG_FS |
1880 | ||
70a3341a | 1881 | static int omap_hsmmc_regs_show(struct seq_file *s, void *data) |
d900f712 DK |
1882 | { |
1883 | struct mmc_host *mmc = s->private; | |
70a3341a | 1884 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
11dd62a7 DK |
1885 | int context_loss = 0; |
1886 | ||
70a3341a DK |
1887 | if (host->pdata->get_context_loss_count) |
1888 | context_loss = host->pdata->get_context_loss_count(host->dev); | |
d900f712 | 1889 | |
5e2ea617 AH |
1890 | seq_printf(s, "mmc%d:\n" |
1891 | " enabled:\t%d\n" | |
dd498eff | 1892 | " dpm_state:\t%d\n" |
5e2ea617 | 1893 | " nesting_cnt:\t%d\n" |
11dd62a7 | 1894 | " ctx_loss:\t%d:%d\n" |
5e2ea617 | 1895 | "\nregs:\n", |
dd498eff DK |
1896 | mmc->index, mmc->enabled ? 1 : 0, |
1897 | host->dpm_state, mmc->nesting_cnt, | |
11dd62a7 | 1898 | host->context_loss, context_loss); |
5e2ea617 | 1899 | |
13189e78 | 1900 | if (host->suspended || host->dpm_state == OFF) { |
dd498eff DK |
1901 | seq_printf(s, "host suspended, can't read registers\n"); |
1902 | return 0; | |
1903 | } | |
1904 | ||
5e2ea617 AH |
1905 | if (clk_enable(host->fclk) != 0) { |
1906 | seq_printf(s, "can't read the regs\n"); | |
dd498eff | 1907 | return 0; |
5e2ea617 | 1908 | } |
d900f712 DK |
1909 | |
1910 | seq_printf(s, "SYSCONFIG:\t0x%08x\n", | |
1911 | OMAP_HSMMC_READ(host->base, SYSCONFIG)); | |
1912 | seq_printf(s, "CON:\t\t0x%08x\n", | |
1913 | OMAP_HSMMC_READ(host->base, CON)); | |
1914 | seq_printf(s, "HCTL:\t\t0x%08x\n", | |
1915 | OMAP_HSMMC_READ(host->base, HCTL)); | |
1916 | seq_printf(s, "SYSCTL:\t\t0x%08x\n", | |
1917 | OMAP_HSMMC_READ(host->base, SYSCTL)); | |
1918 | seq_printf(s, "IE:\t\t0x%08x\n", | |
1919 | OMAP_HSMMC_READ(host->base, IE)); | |
1920 | seq_printf(s, "ISE:\t\t0x%08x\n", | |
1921 | OMAP_HSMMC_READ(host->base, ISE)); | |
1922 | seq_printf(s, "CAPA:\t\t0x%08x\n", | |
1923 | OMAP_HSMMC_READ(host->base, CAPA)); | |
5e2ea617 AH |
1924 | |
1925 | clk_disable(host->fclk); | |
dd498eff | 1926 | |
d900f712 DK |
1927 | return 0; |
1928 | } | |
1929 | ||
70a3341a | 1930 | static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) |
d900f712 | 1931 | { |
70a3341a | 1932 | return single_open(file, omap_hsmmc_regs_show, inode->i_private); |
d900f712 DK |
1933 | } |
1934 | ||
1935 | static const struct file_operations mmc_regs_fops = { | |
70a3341a | 1936 | .open = omap_hsmmc_regs_open, |
d900f712 DK |
1937 | .read = seq_read, |
1938 | .llseek = seq_lseek, | |
1939 | .release = single_release, | |
1940 | }; | |
1941 | ||
70a3341a | 1942 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1943 | { |
1944 | if (mmc->debugfs_root) | |
1945 | debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, | |
1946 | mmc, &mmc_regs_fops); | |
1947 | } | |
1948 | ||
1949 | #else | |
1950 | ||
70a3341a | 1951 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1952 | { |
1953 | } | |
1954 | ||
1955 | #endif | |
1956 | ||
70a3341a | 1957 | static int __init omap_hsmmc_probe(struct platform_device *pdev) |
a45c6cb8 MC |
1958 | { |
1959 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; | |
1960 | struct mmc_host *mmc; | |
70a3341a | 1961 | struct omap_hsmmc_host *host = NULL; |
a45c6cb8 | 1962 | struct resource *res; |
db0fefc5 | 1963 | int ret, irq; |
a45c6cb8 MC |
1964 | |
1965 | if (pdata == NULL) { | |
1966 | dev_err(&pdev->dev, "Platform Data is missing\n"); | |
1967 | return -ENXIO; | |
1968 | } | |
1969 | ||
1970 | if (pdata->nr_slots == 0) { | |
1971 | dev_err(&pdev->dev, "No Slots\n"); | |
1972 | return -ENXIO; | |
1973 | } | |
1974 | ||
1975 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1976 | irq = platform_get_irq(pdev, 0); | |
1977 | if (res == NULL || irq < 0) | |
1978 | return -ENXIO; | |
1979 | ||
1980 | res = request_mem_region(res->start, res->end - res->start + 1, | |
1981 | pdev->name); | |
1982 | if (res == NULL) | |
1983 | return -EBUSY; | |
1984 | ||
db0fefc5 AH |
1985 | ret = omap_hsmmc_gpio_init(pdata); |
1986 | if (ret) | |
1987 | goto err; | |
1988 | ||
70a3341a | 1989 | mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); |
a45c6cb8 MC |
1990 | if (!mmc) { |
1991 | ret = -ENOMEM; | |
db0fefc5 | 1992 | goto err_alloc; |
a45c6cb8 MC |
1993 | } |
1994 | ||
1995 | host = mmc_priv(mmc); | |
1996 | host->mmc = mmc; | |
1997 | host->pdata = pdata; | |
1998 | host->dev = &pdev->dev; | |
1999 | host->use_dma = 1; | |
2000 | host->dev->dma_mask = &pdata->dma_mask; | |
2001 | host->dma_ch = -1; | |
2002 | host->irq = irq; | |
2003 | host->id = pdev->id; | |
2004 | host->slot_id = 0; | |
2005 | host->mapbase = res->start; | |
2006 | host->base = ioremap(host->mapbase, SZ_4K); | |
6da20c89 | 2007 | host->power_mode = MMC_POWER_OFF; |
a45c6cb8 MC |
2008 | |
2009 | platform_set_drvdata(pdev, host); | |
70a3341a | 2010 | INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); |
a45c6cb8 | 2011 | |
191d1f1d | 2012 | if (mmc_slot(host).power_saving) |
70a3341a | 2013 | mmc->ops = &omap_hsmmc_ps_ops; |
dd498eff | 2014 | else |
70a3341a | 2015 | mmc->ops = &omap_hsmmc_ops; |
dd498eff | 2016 | |
e0eb2424 AH |
2017 | /* |
2018 | * If regulator_disable can only put vcc_aux to sleep then there is | |
2019 | * no off state. | |
2020 | */ | |
2021 | if (mmc_slot(host).vcc_aux_disable_is_sleep) | |
2022 | mmc_slot(host).no_off = 1; | |
2023 | ||
a45c6cb8 MC |
2024 | mmc->f_min = 400000; |
2025 | mmc->f_max = 52000000; | |
2026 | ||
2027 | sema_init(&host->sem, 1); | |
4dffd7a2 | 2028 | spin_lock_init(&host->irq_lock); |
a45c6cb8 | 2029 | |
6f7607cc | 2030 | host->iclk = clk_get(&pdev->dev, "ick"); |
a45c6cb8 MC |
2031 | if (IS_ERR(host->iclk)) { |
2032 | ret = PTR_ERR(host->iclk); | |
2033 | host->iclk = NULL; | |
2034 | goto err1; | |
2035 | } | |
6f7607cc | 2036 | host->fclk = clk_get(&pdev->dev, "fck"); |
a45c6cb8 MC |
2037 | if (IS_ERR(host->fclk)) { |
2038 | ret = PTR_ERR(host->fclk); | |
2039 | host->fclk = NULL; | |
2040 | clk_put(host->iclk); | |
2041 | goto err1; | |
2042 | } | |
2043 | ||
70a3341a | 2044 | omap_hsmmc_context_save(host); |
11dd62a7 | 2045 | |
5e2ea617 | 2046 | mmc->caps |= MMC_CAP_DISABLE; |
dd498eff DK |
2047 | mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT); |
2048 | /* we start off in DISABLED state */ | |
2049 | host->dpm_state = DISABLED; | |
2050 | ||
5e2ea617 | 2051 | if (mmc_host_enable(host->mmc) != 0) { |
a45c6cb8 MC |
2052 | clk_put(host->iclk); |
2053 | clk_put(host->fclk); | |
2054 | goto err1; | |
2055 | } | |
2056 | ||
2057 | if (clk_enable(host->iclk) != 0) { | |
5e2ea617 | 2058 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
2059 | clk_put(host->iclk); |
2060 | clk_put(host->fclk); | |
2061 | goto err1; | |
2062 | } | |
2063 | ||
2bec0893 AH |
2064 | if (cpu_is_omap2430()) { |
2065 | host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); | |
2066 | /* | |
2067 | * MMC can still work without debounce clock. | |
2068 | */ | |
2069 | if (IS_ERR(host->dbclk)) | |
2070 | dev_warn(mmc_dev(host->mmc), | |
2071 | "Failed to get debounce clock\n"); | |
a45c6cb8 | 2072 | else |
2bec0893 AH |
2073 | host->got_dbclk = 1; |
2074 | ||
2075 | if (host->got_dbclk) | |
2076 | if (clk_enable(host->dbclk) != 0) | |
2077 | dev_dbg(mmc_dev(host->mmc), "Enabling debounce" | |
2078 | " clk failed\n"); | |
2079 | } | |
a45c6cb8 | 2080 | |
0ccd76d4 JY |
2081 | /* Since we do only SG emulation, we can have as many segs |
2082 | * as we want. */ | |
2083 | mmc->max_phys_segs = 1024; | |
2084 | mmc->max_hw_segs = 1024; | |
2085 | ||
a45c6cb8 MC |
2086 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
2087 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ | |
2088 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
2089 | mmc->max_seg_size = mmc->max_req_size; | |
2090 | ||
13189e78 JL |
2091 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
2092 | MMC_CAP_WAIT_WHILE_BUSY; | |
a45c6cb8 | 2093 | |
191d1f1d | 2094 | if (mmc_slot(host).wires >= 8) |
73153010 | 2095 | mmc->caps |= MMC_CAP_8_BIT_DATA; |
191d1f1d | 2096 | else if (mmc_slot(host).wires >= 4) |
a45c6cb8 MC |
2097 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
2098 | ||
191d1f1d | 2099 | if (mmc_slot(host).nonremovable) |
23d99bb9 AH |
2100 | mmc->caps |= MMC_CAP_NONREMOVABLE; |
2101 | ||
70a3341a | 2102 | omap_hsmmc_conf_bus_power(host); |
a45c6cb8 | 2103 | |
f3e2f1dd GI |
2104 | /* Select DMA lines */ |
2105 | switch (host->id) { | |
2106 | case OMAP_MMC1_DEVID: | |
2107 | host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; | |
2108 | host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; | |
2109 | break; | |
2110 | case OMAP_MMC2_DEVID: | |
2111 | host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; | |
2112 | host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; | |
2113 | break; | |
2114 | case OMAP_MMC3_DEVID: | |
2115 | host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; | |
2116 | host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; | |
2117 | break; | |
82cf818d | 2118 | case OMAP_MMC4_DEVID: |
2119 | host->dma_line_tx = OMAP44XX_DMA_MMC4_TX; | |
2120 | host->dma_line_rx = OMAP44XX_DMA_MMC4_RX; | |
2121 | break; | |
2122 | case OMAP_MMC5_DEVID: | |
2123 | host->dma_line_tx = OMAP44XX_DMA_MMC5_TX; | |
2124 | host->dma_line_rx = OMAP44XX_DMA_MMC5_RX; | |
2125 | break; | |
f3e2f1dd GI |
2126 | default: |
2127 | dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); | |
2128 | goto err_irq; | |
2129 | } | |
a45c6cb8 MC |
2130 | |
2131 | /* Request IRQ for MMC operations */ | |
70a3341a | 2132 | ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED, |
a45c6cb8 MC |
2133 | mmc_hostname(mmc), host); |
2134 | if (ret) { | |
2135 | dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); | |
2136 | goto err_irq; | |
2137 | } | |
2138 | ||
2139 | if (pdata->init != NULL) { | |
2140 | if (pdata->init(&pdev->dev) != 0) { | |
70a3341a DK |
2141 | dev_dbg(mmc_dev(host->mmc), |
2142 | "Unable to configure MMC IRQs\n"); | |
a45c6cb8 MC |
2143 | goto err_irq_cd_init; |
2144 | } | |
2145 | } | |
db0fefc5 | 2146 | |
b702b106 | 2147 | if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { |
db0fefc5 AH |
2148 | ret = omap_hsmmc_reg_get(host); |
2149 | if (ret) | |
2150 | goto err_reg; | |
2151 | host->use_reg = 1; | |
2152 | } | |
2153 | ||
b583f26d | 2154 | mmc->ocr_avail = mmc_slot(host).ocr_mask; |
a45c6cb8 MC |
2155 | |
2156 | /* Request IRQ for card detect */ | |
e1a55f5e | 2157 | if ((mmc_slot(host).card_detect_irq)) { |
a45c6cb8 | 2158 | ret = request_irq(mmc_slot(host).card_detect_irq, |
70a3341a | 2159 | omap_hsmmc_cd_handler, |
a45c6cb8 MC |
2160 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
2161 | | IRQF_DISABLED, | |
2162 | mmc_hostname(mmc), host); | |
2163 | if (ret) { | |
2164 | dev_dbg(mmc_dev(host->mmc), | |
2165 | "Unable to grab MMC CD IRQ\n"); | |
2166 | goto err_irq_cd; | |
2167 | } | |
2168 | } | |
2169 | ||
2170 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
2171 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
2172 | ||
5e2ea617 AH |
2173 | mmc_host_lazy_disable(host->mmc); |
2174 | ||
b62f6228 AH |
2175 | omap_hsmmc_protect_card(host); |
2176 | ||
a45c6cb8 MC |
2177 | mmc_add_host(mmc); |
2178 | ||
191d1f1d | 2179 | if (mmc_slot(host).name != NULL) { |
a45c6cb8 MC |
2180 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); |
2181 | if (ret < 0) | |
2182 | goto err_slot_name; | |
2183 | } | |
191d1f1d | 2184 | if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { |
a45c6cb8 MC |
2185 | ret = device_create_file(&mmc->class_dev, |
2186 | &dev_attr_cover_switch); | |
2187 | if (ret < 0) | |
db0fefc5 | 2188 | goto err_slot_name; |
a45c6cb8 MC |
2189 | } |
2190 | ||
70a3341a | 2191 | omap_hsmmc_debugfs(mmc); |
d900f712 | 2192 | |
a45c6cb8 MC |
2193 | return 0; |
2194 | ||
a45c6cb8 MC |
2195 | err_slot_name: |
2196 | mmc_remove_host(mmc); | |
a45c6cb8 | 2197 | free_irq(mmc_slot(host).card_detect_irq, host); |
db0fefc5 AH |
2198 | err_irq_cd: |
2199 | if (host->use_reg) | |
2200 | omap_hsmmc_reg_put(host); | |
2201 | err_reg: | |
2202 | if (host->pdata->cleanup) | |
2203 | host->pdata->cleanup(&pdev->dev); | |
a45c6cb8 MC |
2204 | err_irq_cd_init: |
2205 | free_irq(host->irq, host); | |
2206 | err_irq: | |
5e2ea617 | 2207 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
2208 | clk_disable(host->iclk); |
2209 | clk_put(host->fclk); | |
2210 | clk_put(host->iclk); | |
2bec0893 | 2211 | if (host->got_dbclk) { |
a45c6cb8 MC |
2212 | clk_disable(host->dbclk); |
2213 | clk_put(host->dbclk); | |
2214 | } | |
a45c6cb8 MC |
2215 | err1: |
2216 | iounmap(host->base); | |
db0fefc5 AH |
2217 | platform_set_drvdata(pdev, NULL); |
2218 | mmc_free_host(mmc); | |
2219 | err_alloc: | |
2220 | omap_hsmmc_gpio_free(pdata); | |
a45c6cb8 | 2221 | err: |
a45c6cb8 | 2222 | release_mem_region(res->start, res->end - res->start + 1); |
a45c6cb8 MC |
2223 | return ret; |
2224 | } | |
2225 | ||
70a3341a | 2226 | static int omap_hsmmc_remove(struct platform_device *pdev) |
a45c6cb8 | 2227 | { |
70a3341a | 2228 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
2229 | struct resource *res; |
2230 | ||
2231 | if (host) { | |
5e2ea617 | 2232 | mmc_host_enable(host->mmc); |
a45c6cb8 | 2233 | mmc_remove_host(host->mmc); |
db0fefc5 AH |
2234 | if (host->use_reg) |
2235 | omap_hsmmc_reg_put(host); | |
a45c6cb8 MC |
2236 | if (host->pdata->cleanup) |
2237 | host->pdata->cleanup(&pdev->dev); | |
2238 | free_irq(host->irq, host); | |
2239 | if (mmc_slot(host).card_detect_irq) | |
2240 | free_irq(mmc_slot(host).card_detect_irq, host); | |
2241 | flush_scheduled_work(); | |
2242 | ||
5e2ea617 | 2243 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
2244 | clk_disable(host->iclk); |
2245 | clk_put(host->fclk); | |
2246 | clk_put(host->iclk); | |
2bec0893 | 2247 | if (host->got_dbclk) { |
a45c6cb8 MC |
2248 | clk_disable(host->dbclk); |
2249 | clk_put(host->dbclk); | |
2250 | } | |
2251 | ||
2252 | mmc_free_host(host->mmc); | |
2253 | iounmap(host->base); | |
db0fefc5 | 2254 | omap_hsmmc_gpio_free(pdev->dev.platform_data); |
a45c6cb8 MC |
2255 | } |
2256 | ||
2257 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2258 | if (res) | |
2259 | release_mem_region(res->start, res->end - res->start + 1); | |
2260 | platform_set_drvdata(pdev, NULL); | |
2261 | ||
2262 | return 0; | |
2263 | } | |
2264 | ||
2265 | #ifdef CONFIG_PM | |
70a3341a | 2266 | static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state) |
a45c6cb8 MC |
2267 | { |
2268 | int ret = 0; | |
70a3341a | 2269 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
2270 | |
2271 | if (host && host->suspended) | |
2272 | return 0; | |
2273 | ||
2274 | if (host) { | |
a6b2240d AH |
2275 | host->suspended = 1; |
2276 | if (host->pdata->suspend) { | |
2277 | ret = host->pdata->suspend(&pdev->dev, | |
2278 | host->slot_id); | |
2279 | if (ret) { | |
2280 | dev_dbg(mmc_dev(host->mmc), | |
2281 | "Unable to handle MMC board" | |
2282 | " level suspend\n"); | |
2283 | host->suspended = 0; | |
2284 | return ret; | |
2285 | } | |
2286 | } | |
2287 | cancel_work_sync(&host->mmc_carddetect_work); | |
5e2ea617 | 2288 | mmc_host_enable(host->mmc); |
a45c6cb8 MC |
2289 | ret = mmc_suspend_host(host->mmc, state); |
2290 | if (ret == 0) { | |
a45c6cb8 MC |
2291 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
2292 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
2293 | ||
a45c6cb8 | 2294 | |
0683af48 | 2295 | OMAP_HSMMC_WRITE(host->base, HCTL, |
191d1f1d | 2296 | OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); |
5e2ea617 | 2297 | mmc_host_disable(host->mmc); |
a45c6cb8 | 2298 | clk_disable(host->iclk); |
2bec0893 AH |
2299 | if (host->got_dbclk) |
2300 | clk_disable(host->dbclk); | |
a6b2240d AH |
2301 | } else { |
2302 | host->suspended = 0; | |
2303 | if (host->pdata->resume) { | |
2304 | ret = host->pdata->resume(&pdev->dev, | |
2305 | host->slot_id); | |
2306 | if (ret) | |
2307 | dev_dbg(mmc_dev(host->mmc), | |
2308 | "Unmask interrupt failed\n"); | |
2309 | } | |
5e2ea617 | 2310 | mmc_host_disable(host->mmc); |
a6b2240d | 2311 | } |
a45c6cb8 MC |
2312 | |
2313 | } | |
2314 | return ret; | |
2315 | } | |
2316 | ||
2317 | /* Routine to resume the MMC device */ | |
70a3341a | 2318 | static int omap_hsmmc_resume(struct platform_device *pdev) |
a45c6cb8 MC |
2319 | { |
2320 | int ret = 0; | |
70a3341a | 2321 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
2322 | |
2323 | if (host && !host->suspended) | |
2324 | return 0; | |
2325 | ||
2326 | if (host) { | |
a45c6cb8 | 2327 | ret = clk_enable(host->iclk); |
11dd62a7 | 2328 | if (ret) |
a45c6cb8 | 2329 | goto clk_en_err; |
a45c6cb8 | 2330 | |
11dd62a7 DK |
2331 | if (mmc_host_enable(host->mmc) != 0) { |
2332 | clk_disable(host->iclk); | |
2333 | goto clk_en_err; | |
2334 | } | |
2335 | ||
2bec0893 AH |
2336 | if (host->got_dbclk) |
2337 | clk_enable(host->dbclk); | |
2338 | ||
70a3341a | 2339 | omap_hsmmc_conf_bus_power(host); |
1b331e69 | 2340 | |
a45c6cb8 MC |
2341 | if (host->pdata->resume) { |
2342 | ret = host->pdata->resume(&pdev->dev, host->slot_id); | |
2343 | if (ret) | |
2344 | dev_dbg(mmc_dev(host->mmc), | |
2345 | "Unmask interrupt failed\n"); | |
2346 | } | |
2347 | ||
b62f6228 AH |
2348 | omap_hsmmc_protect_card(host); |
2349 | ||
a45c6cb8 MC |
2350 | /* Notify the core to resume the host */ |
2351 | ret = mmc_resume_host(host->mmc); | |
2352 | if (ret == 0) | |
2353 | host->suspended = 0; | |
70a3341a | 2354 | |
5e2ea617 | 2355 | mmc_host_lazy_disable(host->mmc); |
a45c6cb8 MC |
2356 | } |
2357 | ||
2358 | return ret; | |
2359 | ||
2360 | clk_en_err: | |
2361 | dev_dbg(mmc_dev(host->mmc), | |
2362 | "Failed to enable MMC clocks during resume\n"); | |
2363 | return ret; | |
2364 | } | |
2365 | ||
2366 | #else | |
70a3341a DK |
2367 | #define omap_hsmmc_suspend NULL |
2368 | #define omap_hsmmc_resume NULL | |
a45c6cb8 MC |
2369 | #endif |
2370 | ||
70a3341a DK |
2371 | static struct platform_driver omap_hsmmc_driver = { |
2372 | .remove = omap_hsmmc_remove, | |
2373 | .suspend = omap_hsmmc_suspend, | |
2374 | .resume = omap_hsmmc_resume, | |
a45c6cb8 MC |
2375 | .driver = { |
2376 | .name = DRIVER_NAME, | |
2377 | .owner = THIS_MODULE, | |
2378 | }, | |
2379 | }; | |
2380 | ||
70a3341a | 2381 | static int __init omap_hsmmc_init(void) |
a45c6cb8 MC |
2382 | { |
2383 | /* Register the MMC driver */ | |
8753298a | 2384 | return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe); |
a45c6cb8 MC |
2385 | } |
2386 | ||
70a3341a | 2387 | static void __exit omap_hsmmc_cleanup(void) |
a45c6cb8 MC |
2388 | { |
2389 | /* Unregister MMC driver */ | |
70a3341a | 2390 | platform_driver_unregister(&omap_hsmmc_driver); |
a45c6cb8 MC |
2391 | } |
2392 | ||
70a3341a DK |
2393 | module_init(omap_hsmmc_init); |
2394 | module_exit(omap_hsmmc_cleanup); | |
a45c6cb8 MC |
2395 | |
2396 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); | |
2397 | MODULE_LICENSE("GPL"); | |
2398 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2399 | MODULE_AUTHOR("Texas Instruments Inc"); |