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Commit | Line | Data |
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a45c6cb8 MC |
1 | /* |
2 | * drivers/mmc/host/omap_hsmmc.c | |
3 | * | |
4 | * Driver for OMAP2430/3430 MMC controller. | |
5 | * | |
6 | * Copyright (C) 2007 Texas Instruments. | |
7 | * | |
8 | * Authors: | |
9 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
10 | * Madhusudhan <madhu.cr@ti.com> | |
11 | * Mohit Jalori <mjalori@ti.com> | |
12 | * | |
13 | * This file is licensed under the terms of the GNU General Public License | |
14 | * version 2. This program is licensed "as is" without any warranty of any | |
15 | * kind, whether express or implied. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
ac330f44 | 20 | #include <linux/kernel.h> |
d900f712 DK |
21 | #include <linux/debugfs.h> |
22 | #include <linux/seq_file.h> | |
a45c6cb8 MC |
23 | #include <linux/interrupt.h> |
24 | #include <linux/delay.h> | |
25 | #include <linux/dma-mapping.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/workqueue.h> | |
28 | #include <linux/timer.h> | |
29 | #include <linux/clk.h> | |
30 | #include <linux/mmc/host.h> | |
13189e78 | 31 | #include <linux/mmc/core.h> |
93caf8e6 | 32 | #include <linux/mmc/mmc.h> |
a45c6cb8 MC |
33 | #include <linux/io.h> |
34 | #include <linux/semaphore.h> | |
db0fefc5 AH |
35 | #include <linux/gpio.h> |
36 | #include <linux/regulator/consumer.h> | |
fa4aa2d4 | 37 | #include <linux/pm_runtime.h> |
ce491cf8 | 38 | #include <plat/dma.h> |
a45c6cb8 | 39 | #include <mach/hardware.h> |
ce491cf8 TL |
40 | #include <plat/board.h> |
41 | #include <plat/mmc.h> | |
42 | #include <plat/cpu.h> | |
a45c6cb8 MC |
43 | |
44 | /* OMAP HSMMC Host Controller Registers */ | |
45 | #define OMAP_HSMMC_SYSCONFIG 0x0010 | |
11dd62a7 | 46 | #define OMAP_HSMMC_SYSSTATUS 0x0014 |
a45c6cb8 MC |
47 | #define OMAP_HSMMC_CON 0x002C |
48 | #define OMAP_HSMMC_BLK 0x0104 | |
49 | #define OMAP_HSMMC_ARG 0x0108 | |
50 | #define OMAP_HSMMC_CMD 0x010C | |
51 | #define OMAP_HSMMC_RSP10 0x0110 | |
52 | #define OMAP_HSMMC_RSP32 0x0114 | |
53 | #define OMAP_HSMMC_RSP54 0x0118 | |
54 | #define OMAP_HSMMC_RSP76 0x011C | |
55 | #define OMAP_HSMMC_DATA 0x0120 | |
56 | #define OMAP_HSMMC_HCTL 0x0128 | |
57 | #define OMAP_HSMMC_SYSCTL 0x012C | |
58 | #define OMAP_HSMMC_STAT 0x0130 | |
59 | #define OMAP_HSMMC_IE 0x0134 | |
60 | #define OMAP_HSMMC_ISE 0x0138 | |
61 | #define OMAP_HSMMC_CAPA 0x0140 | |
62 | ||
63 | #define VS18 (1 << 26) | |
64 | #define VS30 (1 << 25) | |
65 | #define SDVS18 (0x5 << 9) | |
66 | #define SDVS30 (0x6 << 9) | |
eb250826 | 67 | #define SDVS33 (0x7 << 9) |
1b331e69 | 68 | #define SDVS_MASK 0x00000E00 |
a45c6cb8 MC |
69 | #define SDVSCLR 0xFFFFF1FF |
70 | #define SDVSDET 0x00000400 | |
71 | #define AUTOIDLE 0x1 | |
72 | #define SDBP (1 << 8) | |
73 | #define DTO 0xe | |
74 | #define ICE 0x1 | |
75 | #define ICS 0x2 | |
76 | #define CEN (1 << 2) | |
77 | #define CLKD_MASK 0x0000FFC0 | |
78 | #define CLKD_SHIFT 6 | |
79 | #define DTO_MASK 0x000F0000 | |
80 | #define DTO_SHIFT 16 | |
81 | #define INT_EN_MASK 0x307F0033 | |
ccdfe3a6 AG |
82 | #define BWR_ENABLE (1 << 4) |
83 | #define BRR_ENABLE (1 << 5) | |
93caf8e6 | 84 | #define DTO_ENABLE (1 << 20) |
a45c6cb8 MC |
85 | #define INIT_STREAM (1 << 1) |
86 | #define DP_SELECT (1 << 21) | |
87 | #define DDIR (1 << 4) | |
88 | #define DMA_EN 0x1 | |
89 | #define MSBS (1 << 5) | |
90 | #define BCE (1 << 1) | |
91 | #define FOUR_BIT (1 << 1) | |
73153010 | 92 | #define DW8 (1 << 5) |
a45c6cb8 MC |
93 | #define CC 0x1 |
94 | #define TC 0x02 | |
95 | #define OD 0x1 | |
96 | #define ERR (1 << 15) | |
97 | #define CMD_TIMEOUT (1 << 16) | |
98 | #define DATA_TIMEOUT (1 << 20) | |
99 | #define CMD_CRC (1 << 17) | |
100 | #define DATA_CRC (1 << 21) | |
101 | #define CARD_ERR (1 << 28) | |
102 | #define STAT_CLEAR 0xFFFFFFFF | |
103 | #define INIT_STREAM_CMD 0x00000000 | |
104 | #define DUAL_VOLT_OCR_BIT 7 | |
105 | #define SRC (1 << 25) | |
106 | #define SRD (1 << 26) | |
11dd62a7 DK |
107 | #define SOFTRESET (1 << 1) |
108 | #define RESETDONE (1 << 0) | |
a45c6cb8 MC |
109 | |
110 | /* | |
111 | * FIXME: Most likely all the data using these _DEVID defines should come | |
112 | * from the platform_data, or implemented in controller and slot specific | |
113 | * functions. | |
114 | */ | |
115 | #define OMAP_MMC1_DEVID 0 | |
116 | #define OMAP_MMC2_DEVID 1 | |
f3e2f1dd | 117 | #define OMAP_MMC3_DEVID 2 |
82cf818d | 118 | #define OMAP_MMC4_DEVID 3 |
119 | #define OMAP_MMC5_DEVID 4 | |
a45c6cb8 | 120 | |
fa4aa2d4 | 121 | #define MMC_AUTOSUSPEND_DELAY 100 |
a45c6cb8 MC |
122 | #define MMC_TIMEOUT_MS 20 |
123 | #define OMAP_MMC_MASTER_CLOCK 96000000 | |
6b206efe AS |
124 | #define OMAP_MMC_MIN_CLOCK 400000 |
125 | #define OMAP_MMC_MAX_CLOCK 52000000 | |
0005ae73 | 126 | #define DRIVER_NAME "omap_hsmmc" |
a45c6cb8 MC |
127 | |
128 | /* | |
129 | * One controller can have multiple slots, like on some omap boards using | |
130 | * omap.c controller driver. Luckily this is not currently done on any known | |
131 | * omap_hsmmc.c device. | |
132 | */ | |
133 | #define mmc_slot(host) (host->pdata->slots[host->slot_id]) | |
134 | ||
135 | /* | |
136 | * MMC Host controller read/write API's | |
137 | */ | |
138 | #define OMAP_HSMMC_READ(base, reg) \ | |
139 | __raw_readl((base) + OMAP_HSMMC_##reg) | |
140 | ||
141 | #define OMAP_HSMMC_WRITE(base, reg, val) \ | |
142 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) | |
143 | ||
9782aff8 PF |
144 | struct omap_hsmmc_next { |
145 | unsigned int dma_len; | |
146 | s32 cookie; | |
147 | }; | |
148 | ||
70a3341a | 149 | struct omap_hsmmc_host { |
a45c6cb8 MC |
150 | struct device *dev; |
151 | struct mmc_host *mmc; | |
152 | struct mmc_request *mrq; | |
153 | struct mmc_command *cmd; | |
154 | struct mmc_data *data; | |
155 | struct clk *fclk; | |
a45c6cb8 | 156 | struct clk *dbclk; |
db0fefc5 AH |
157 | /* |
158 | * vcc == configured supply | |
159 | * vcc_aux == optional | |
160 | * - MMC1, supply for DAT4..DAT7 | |
161 | * - MMC2/MMC2, external level shifter voltage supply, for | |
162 | * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) | |
163 | */ | |
164 | struct regulator *vcc; | |
165 | struct regulator *vcc_aux; | |
a45c6cb8 MC |
166 | struct work_struct mmc_carddetect_work; |
167 | void __iomem *base; | |
168 | resource_size_t mapbase; | |
4dffd7a2 | 169 | spinlock_t irq_lock; /* Prevent races with irq handler */ |
a45c6cb8 MC |
170 | unsigned int id; |
171 | unsigned int dma_len; | |
0ccd76d4 | 172 | unsigned int dma_sg_idx; |
a45c6cb8 | 173 | unsigned char bus_mode; |
a3621465 | 174 | unsigned char power_mode; |
a45c6cb8 MC |
175 | u32 *buffer; |
176 | u32 bytesleft; | |
177 | int suspended; | |
178 | int irq; | |
a45c6cb8 | 179 | int use_dma, dma_ch; |
f3e2f1dd | 180 | int dma_line_tx, dma_line_rx; |
a45c6cb8 | 181 | int slot_id; |
2bec0893 | 182 | int got_dbclk; |
4a694dc9 | 183 | int response_busy; |
11dd62a7 | 184 | int context_loss; |
dd498eff | 185 | int dpm_state; |
623821f7 | 186 | int vdd; |
b62f6228 AH |
187 | int protect_card; |
188 | int reqs_blocked; | |
db0fefc5 | 189 | int use_reg; |
b417577d | 190 | int req_in_progress; |
9782aff8 | 191 | struct omap_hsmmc_next next_data; |
11dd62a7 | 192 | |
a45c6cb8 MC |
193 | struct omap_mmc_platform_data *pdata; |
194 | }; | |
195 | ||
db0fefc5 AH |
196 | static int omap_hsmmc_card_detect(struct device *dev, int slot) |
197 | { | |
198 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
199 | ||
200 | /* NOTE: assumes card detect signal is active-low */ | |
201 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
202 | } | |
203 | ||
204 | static int omap_hsmmc_get_wp(struct device *dev, int slot) | |
205 | { | |
206 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
207 | ||
208 | /* NOTE: assumes write protect signal is active-high */ | |
209 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | |
210 | } | |
211 | ||
212 | static int omap_hsmmc_get_cover_state(struct device *dev, int slot) | |
213 | { | |
214 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
215 | ||
216 | /* NOTE: assumes card detect signal is active-low */ | |
217 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
218 | } | |
219 | ||
220 | #ifdef CONFIG_PM | |
221 | ||
222 | static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) | |
223 | { | |
224 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
225 | ||
226 | disable_irq(mmc->slots[0].card_detect_irq); | |
227 | return 0; | |
228 | } | |
229 | ||
230 | static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) | |
231 | { | |
232 | struct omap_mmc_platform_data *mmc = dev->platform_data; | |
233 | ||
234 | enable_irq(mmc->slots[0].card_detect_irq); | |
235 | return 0; | |
236 | } | |
237 | ||
238 | #else | |
239 | ||
240 | #define omap_hsmmc_suspend_cdirq NULL | |
241 | #define omap_hsmmc_resume_cdirq NULL | |
242 | ||
243 | #endif | |
244 | ||
b702b106 AH |
245 | #ifdef CONFIG_REGULATOR |
246 | ||
db0fefc5 AH |
247 | static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, |
248 | int vdd) | |
249 | { | |
250 | struct omap_hsmmc_host *host = | |
251 | platform_get_drvdata(to_platform_device(dev)); | |
252 | int ret; | |
253 | ||
254 | if (mmc_slot(host).before_set_reg) | |
255 | mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); | |
256 | ||
257 | if (power_on) | |
99fc5131 | 258 | ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); |
db0fefc5 | 259 | else |
99fc5131 | 260 | ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); |
db0fefc5 AH |
261 | |
262 | if (mmc_slot(host).after_set_reg) | |
263 | mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); | |
264 | ||
265 | return ret; | |
266 | } | |
267 | ||
7715db5a | 268 | static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on, |
db0fefc5 AH |
269 | int vdd) |
270 | { | |
271 | struct omap_hsmmc_host *host = | |
272 | platform_get_drvdata(to_platform_device(dev)); | |
273 | int ret = 0; | |
274 | ||
275 | /* | |
276 | * If we don't see a Vcc regulator, assume it's a fixed | |
277 | * voltage always-on regulator. | |
278 | */ | |
279 | if (!host->vcc) | |
280 | return 0; | |
281 | ||
282 | if (mmc_slot(host).before_set_reg) | |
283 | mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); | |
284 | ||
285 | /* | |
286 | * Assume Vcc regulator is used only to power the card ... OMAP | |
287 | * VDDS is used to power the pins, optionally with a transceiver to | |
288 | * support cards using voltages other than VDDS (1.8V nominal). When a | |
289 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. | |
290 | * | |
291 | * In some cases this regulator won't support enable/disable; | |
292 | * e.g. it's a fixed rail for a WLAN chip. | |
293 | * | |
294 | * In other cases vcc_aux switches interface power. Example, for | |
295 | * eMMC cards it represents VccQ. Sometimes transceivers or SDIO | |
296 | * chips/cards need an interface voltage rail too. | |
297 | */ | |
298 | if (power_on) { | |
99fc5131 | 299 | ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); |
db0fefc5 AH |
300 | /* Enable interface voltage rail, if needed */ |
301 | if (ret == 0 && host->vcc_aux) { | |
302 | ret = regulator_enable(host->vcc_aux); | |
303 | if (ret < 0) | |
99fc5131 LW |
304 | ret = mmc_regulator_set_ocr(host->mmc, |
305 | host->vcc, 0); | |
db0fefc5 AH |
306 | } |
307 | } else { | |
99fc5131 | 308 | /* Shut down the rail */ |
6da20c89 AH |
309 | if (host->vcc_aux) |
310 | ret = regulator_disable(host->vcc_aux); | |
99fc5131 LW |
311 | if (!ret) { |
312 | /* Then proceed to shut down the local regulator */ | |
313 | ret = mmc_regulator_set_ocr(host->mmc, | |
314 | host->vcc, 0); | |
315 | } | |
db0fefc5 AH |
316 | } |
317 | ||
318 | if (mmc_slot(host).after_set_reg) | |
319 | mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); | |
320 | ||
321 | return ret; | |
322 | } | |
323 | ||
7715db5a KK |
324 | static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on, |
325 | int vdd) | |
326 | { | |
327 | return 0; | |
328 | } | |
329 | ||
db0fefc5 AH |
330 | static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, |
331 | int vdd, int cardsleep) | |
332 | { | |
333 | struct omap_hsmmc_host *host = | |
334 | platform_get_drvdata(to_platform_device(dev)); | |
335 | int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; | |
336 | ||
337 | return regulator_set_mode(host->vcc, mode); | |
338 | } | |
339 | ||
7715db5a | 340 | static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep, |
db0fefc5 AH |
341 | int vdd, int cardsleep) |
342 | { | |
343 | struct omap_hsmmc_host *host = | |
344 | platform_get_drvdata(to_platform_device(dev)); | |
345 | int err, mode; | |
346 | ||
347 | /* | |
348 | * If we don't see a Vcc regulator, assume it's a fixed | |
349 | * voltage always-on regulator. | |
350 | */ | |
351 | if (!host->vcc) | |
352 | return 0; | |
353 | ||
354 | mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; | |
355 | ||
356 | if (!host->vcc_aux) | |
357 | return regulator_set_mode(host->vcc, mode); | |
358 | ||
359 | if (cardsleep) { | |
360 | /* VCC can be turned off if card is asleep */ | |
361 | if (sleep) | |
99fc5131 | 362 | err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); |
db0fefc5 | 363 | else |
99fc5131 | 364 | err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); |
db0fefc5 AH |
365 | } else |
366 | err = regulator_set_mode(host->vcc, mode); | |
367 | if (err) | |
368 | return err; | |
e0eb2424 AH |
369 | |
370 | if (!mmc_slot(host).vcc_aux_disable_is_sleep) | |
371 | return regulator_set_mode(host->vcc_aux, mode); | |
372 | ||
373 | if (sleep) | |
374 | return regulator_disable(host->vcc_aux); | |
375 | else | |
376 | return regulator_enable(host->vcc_aux); | |
db0fefc5 AH |
377 | } |
378 | ||
7715db5a KK |
379 | static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep, |
380 | int vdd, int cardsleep) | |
381 | { | |
382 | return 0; | |
383 | } | |
384 | ||
db0fefc5 AH |
385 | static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) |
386 | { | |
387 | struct regulator *reg; | |
388 | int ret = 0; | |
64be9782 | 389 | int ocr_value = 0; |
db0fefc5 AH |
390 | |
391 | switch (host->id) { | |
392 | case OMAP_MMC1_DEVID: | |
393 | /* On-chip level shifting via PBIAS0/PBIAS1 */ | |
394 | mmc_slot(host).set_power = omap_hsmmc_1_set_power; | |
395 | mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; | |
396 | break; | |
397 | case OMAP_MMC2_DEVID: | |
398 | case OMAP_MMC3_DEVID: | |
7715db5a | 399 | case OMAP_MMC5_DEVID: |
db0fefc5 | 400 | /* Off-chip level shifting, or none */ |
7715db5a KK |
401 | mmc_slot(host).set_power = omap_hsmmc_235_set_power; |
402 | mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep; | |
db0fefc5 | 403 | break; |
7715db5a KK |
404 | case OMAP_MMC4_DEVID: |
405 | mmc_slot(host).set_power = omap_hsmmc_4_set_power; | |
406 | mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep; | |
db0fefc5 AH |
407 | default: |
408 | pr_err("MMC%d configuration not supported!\n", host->id); | |
409 | return -EINVAL; | |
410 | } | |
411 | ||
412 | reg = regulator_get(host->dev, "vmmc"); | |
413 | if (IS_ERR(reg)) { | |
414 | dev_dbg(host->dev, "vmmc regulator missing\n"); | |
415 | /* | |
416 | * HACK: until fixed.c regulator is usable, | |
417 | * we don't require a main regulator | |
418 | * for MMC2 or MMC3 | |
419 | */ | |
420 | if (host->id == OMAP_MMC1_DEVID) { | |
421 | ret = PTR_ERR(reg); | |
422 | goto err; | |
423 | } | |
424 | } else { | |
425 | host->vcc = reg; | |
64be9782 | 426 | ocr_value = mmc_regulator_get_ocrmask(reg); |
427 | if (!mmc_slot(host).ocr_mask) { | |
428 | mmc_slot(host).ocr_mask = ocr_value; | |
429 | } else { | |
430 | if (!(mmc_slot(host).ocr_mask & ocr_value)) { | |
431 | pr_err("MMC%d ocrmask %x is not supported\n", | |
432 | host->id, mmc_slot(host).ocr_mask); | |
433 | mmc_slot(host).ocr_mask = 0; | |
434 | return -EINVAL; | |
435 | } | |
436 | } | |
db0fefc5 AH |
437 | |
438 | /* Allow an aux regulator */ | |
439 | reg = regulator_get(host->dev, "vmmc_aux"); | |
440 | host->vcc_aux = IS_ERR(reg) ? NULL : reg; | |
441 | ||
b1c1df7a B |
442 | /* For eMMC do not power off when not in sleep state */ |
443 | if (mmc_slot(host).no_regulator_off_init) | |
444 | return 0; | |
db0fefc5 AH |
445 | /* |
446 | * UGLY HACK: workaround regulator framework bugs. | |
447 | * When the bootloader leaves a supply active, it's | |
448 | * initialized with zero usecount ... and we can't | |
449 | * disable it without first enabling it. Until the | |
450 | * framework is fixed, we need a workaround like this | |
451 | * (which is safe for MMC, but not in general). | |
452 | */ | |
e840ce13 AH |
453 | if (regulator_is_enabled(host->vcc) > 0 || |
454 | (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { | |
455 | int vdd = ffs(mmc_slot(host).ocr_mask) - 1; | |
456 | ||
457 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
458 | 1, vdd); | |
459 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
460 | 0, 0); | |
db0fefc5 AH |
461 | } |
462 | } | |
463 | ||
464 | return 0; | |
465 | ||
466 | err: | |
467 | mmc_slot(host).set_power = NULL; | |
468 | mmc_slot(host).set_sleep = NULL; | |
469 | return ret; | |
470 | } | |
471 | ||
472 | static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) | |
473 | { | |
474 | regulator_put(host->vcc); | |
475 | regulator_put(host->vcc_aux); | |
476 | mmc_slot(host).set_power = NULL; | |
477 | mmc_slot(host).set_sleep = NULL; | |
478 | } | |
479 | ||
b702b106 AH |
480 | static inline int omap_hsmmc_have_reg(void) |
481 | { | |
482 | return 1; | |
483 | } | |
484 | ||
485 | #else | |
486 | ||
487 | static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) | |
488 | { | |
489 | return -EINVAL; | |
490 | } | |
491 | ||
492 | static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) | |
493 | { | |
494 | } | |
495 | ||
496 | static inline int omap_hsmmc_have_reg(void) | |
497 | { | |
498 | return 0; | |
499 | } | |
500 | ||
501 | #endif | |
502 | ||
503 | static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) | |
504 | { | |
505 | int ret; | |
506 | ||
507 | if (gpio_is_valid(pdata->slots[0].switch_pin)) { | |
b702b106 AH |
508 | if (pdata->slots[0].cover) |
509 | pdata->slots[0].get_cover_state = | |
510 | omap_hsmmc_get_cover_state; | |
511 | else | |
512 | pdata->slots[0].card_detect = omap_hsmmc_card_detect; | |
513 | pdata->slots[0].card_detect_irq = | |
514 | gpio_to_irq(pdata->slots[0].switch_pin); | |
515 | ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); | |
516 | if (ret) | |
517 | return ret; | |
518 | ret = gpio_direction_input(pdata->slots[0].switch_pin); | |
519 | if (ret) | |
520 | goto err_free_sp; | |
521 | } else | |
522 | pdata->slots[0].switch_pin = -EINVAL; | |
523 | ||
524 | if (gpio_is_valid(pdata->slots[0].gpio_wp)) { | |
525 | pdata->slots[0].get_ro = omap_hsmmc_get_wp; | |
526 | ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); | |
527 | if (ret) | |
528 | goto err_free_cd; | |
529 | ret = gpio_direction_input(pdata->slots[0].gpio_wp); | |
530 | if (ret) | |
531 | goto err_free_wp; | |
532 | } else | |
533 | pdata->slots[0].gpio_wp = -EINVAL; | |
534 | ||
535 | return 0; | |
536 | ||
537 | err_free_wp: | |
538 | gpio_free(pdata->slots[0].gpio_wp); | |
539 | err_free_cd: | |
540 | if (gpio_is_valid(pdata->slots[0].switch_pin)) | |
541 | err_free_sp: | |
542 | gpio_free(pdata->slots[0].switch_pin); | |
543 | return ret; | |
544 | } | |
545 | ||
546 | static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) | |
547 | { | |
548 | if (gpio_is_valid(pdata->slots[0].gpio_wp)) | |
549 | gpio_free(pdata->slots[0].gpio_wp); | |
550 | if (gpio_is_valid(pdata->slots[0].switch_pin)) | |
551 | gpio_free(pdata->slots[0].switch_pin); | |
552 | } | |
553 | ||
e0c7f99b AS |
554 | /* |
555 | * Start clock to the card | |
556 | */ | |
557 | static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) | |
558 | { | |
559 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
560 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
561 | } | |
562 | ||
a45c6cb8 MC |
563 | /* |
564 | * Stop clock to the card | |
565 | */ | |
70a3341a | 566 | static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
567 | { |
568 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
569 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
570 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) | |
571 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); | |
572 | } | |
573 | ||
93caf8e6 AH |
574 | static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, |
575 | struct mmc_command *cmd) | |
b417577d AH |
576 | { |
577 | unsigned int irq_mask; | |
578 | ||
579 | if (host->use_dma) | |
580 | irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); | |
581 | else | |
582 | irq_mask = INT_EN_MASK; | |
583 | ||
93caf8e6 AH |
584 | /* Disable timeout for erases */ |
585 | if (cmd->opcode == MMC_ERASE) | |
586 | irq_mask &= ~DTO_ENABLE; | |
587 | ||
b417577d AH |
588 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
589 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); | |
590 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); | |
591 | } | |
592 | ||
593 | static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) | |
594 | { | |
595 | OMAP_HSMMC_WRITE(host->base, ISE, 0); | |
596 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
597 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
598 | } | |
599 | ||
ac330f44 AS |
600 | /* Calculate divisor for the given clock frequency */ |
601 | static u16 calc_divisor(struct mmc_ios *ios) | |
602 | { | |
603 | u16 dsor = 0; | |
604 | ||
605 | if (ios->clock) { | |
606 | dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock); | |
607 | if (dsor > 250) | |
608 | dsor = 250; | |
609 | } | |
610 | ||
611 | return dsor; | |
612 | } | |
613 | ||
5934df2f AS |
614 | static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) |
615 | { | |
616 | struct mmc_ios *ios = &host->mmc->ios; | |
617 | unsigned long regval; | |
618 | unsigned long timeout; | |
619 | ||
620 | dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); | |
621 | ||
622 | omap_hsmmc_stop_clock(host); | |
623 | ||
624 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); | |
625 | regval = regval & ~(CLKD_MASK | DTO_MASK); | |
626 | regval = regval | (calc_divisor(ios) << 6) | (DTO << 16); | |
627 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); | |
628 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
629 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
630 | ||
631 | /* Wait till the ICS bit is set */ | |
632 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
633 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS | |
634 | && time_before(jiffies, timeout)) | |
635 | cpu_relax(); | |
636 | ||
637 | omap_hsmmc_start_clock(host); | |
638 | } | |
639 | ||
3796fb8a AS |
640 | static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) |
641 | { | |
642 | struct mmc_ios *ios = &host->mmc->ios; | |
643 | u32 con; | |
644 | ||
645 | con = OMAP_HSMMC_READ(host->base, CON); | |
646 | switch (ios->bus_width) { | |
647 | case MMC_BUS_WIDTH_8: | |
648 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
649 | break; | |
650 | case MMC_BUS_WIDTH_4: | |
651 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
652 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
653 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
654 | break; | |
655 | case MMC_BUS_WIDTH_1: | |
656 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
657 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
658 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
659 | break; | |
660 | } | |
661 | } | |
662 | ||
663 | static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) | |
664 | { | |
665 | struct mmc_ios *ios = &host->mmc->ios; | |
666 | u32 con; | |
667 | ||
668 | con = OMAP_HSMMC_READ(host->base, CON); | |
669 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
670 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); | |
671 | else | |
672 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
673 | } | |
674 | ||
11dd62a7 DK |
675 | #ifdef CONFIG_PM |
676 | ||
677 | /* | |
678 | * Restore the MMC host context, if it was lost as result of a | |
679 | * power state change. | |
680 | */ | |
70a3341a | 681 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
682 | { |
683 | struct mmc_ios *ios = &host->mmc->ios; | |
684 | struct omap_mmc_platform_data *pdata = host->pdata; | |
685 | int context_loss = 0; | |
3796fb8a | 686 | u32 hctl, capa; |
11dd62a7 DK |
687 | unsigned long timeout; |
688 | ||
689 | if (pdata->get_context_loss_count) { | |
690 | context_loss = pdata->get_context_loss_count(host->dev); | |
691 | if (context_loss < 0) | |
692 | return 1; | |
693 | } | |
694 | ||
695 | dev_dbg(mmc_dev(host->mmc), "context was %slost\n", | |
696 | context_loss == host->context_loss ? "not " : ""); | |
697 | if (host->context_loss == context_loss) | |
698 | return 1; | |
699 | ||
700 | /* Wait for hardware reset */ | |
701 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
702 | while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE | |
703 | && time_before(jiffies, timeout)) | |
704 | ; | |
705 | ||
706 | /* Do software reset */ | |
707 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); | |
708 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
709 | while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE | |
710 | && time_before(jiffies, timeout)) | |
711 | ; | |
712 | ||
713 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, | |
714 | OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); | |
715 | ||
716 | if (host->id == OMAP_MMC1_DEVID) { | |
717 | if (host->power_mode != MMC_POWER_OFF && | |
718 | (1 << ios->vdd) <= MMC_VDD_23_24) | |
719 | hctl = SDVS18; | |
720 | else | |
721 | hctl = SDVS30; | |
722 | capa = VS30 | VS18; | |
723 | } else { | |
724 | hctl = SDVS18; | |
725 | capa = VS18; | |
726 | } | |
727 | ||
728 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
729 | OMAP_HSMMC_READ(host->base, HCTL) | hctl); | |
730 | ||
731 | OMAP_HSMMC_WRITE(host->base, CAPA, | |
732 | OMAP_HSMMC_READ(host->base, CAPA) | capa); | |
733 | ||
734 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
735 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
736 | ||
737 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
738 | while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP | |
739 | && time_before(jiffies, timeout)) | |
740 | ; | |
741 | ||
b417577d | 742 | omap_hsmmc_disable_irq(host); |
11dd62a7 DK |
743 | |
744 | /* Do not initialize card-specific things if the power is off */ | |
745 | if (host->power_mode == MMC_POWER_OFF) | |
746 | goto out; | |
747 | ||
3796fb8a | 748 | omap_hsmmc_set_bus_width(host); |
11dd62a7 | 749 | |
5934df2f | 750 | omap_hsmmc_set_clock(host); |
11dd62a7 | 751 | |
3796fb8a AS |
752 | omap_hsmmc_set_bus_mode(host); |
753 | ||
11dd62a7 DK |
754 | out: |
755 | host->context_loss = context_loss; | |
756 | ||
757 | dev_dbg(mmc_dev(host->mmc), "context is restored\n"); | |
758 | return 0; | |
759 | } | |
760 | ||
761 | /* | |
762 | * Save the MMC host context (store the number of power state changes so far). | |
763 | */ | |
70a3341a | 764 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
765 | { |
766 | struct omap_mmc_platform_data *pdata = host->pdata; | |
767 | int context_loss; | |
768 | ||
769 | if (pdata->get_context_loss_count) { | |
770 | context_loss = pdata->get_context_loss_count(host->dev); | |
771 | if (context_loss < 0) | |
772 | return; | |
773 | host->context_loss = context_loss; | |
774 | } | |
775 | } | |
776 | ||
777 | #else | |
778 | ||
70a3341a | 779 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
780 | { |
781 | return 0; | |
782 | } | |
783 | ||
70a3341a | 784 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
785 | { |
786 | } | |
787 | ||
788 | #endif | |
789 | ||
a45c6cb8 MC |
790 | /* |
791 | * Send init stream sequence to card | |
792 | * before sending IDLE command | |
793 | */ | |
70a3341a | 794 | static void send_init_stream(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
795 | { |
796 | int reg = 0; | |
797 | unsigned long timeout; | |
798 | ||
b62f6228 AH |
799 | if (host->protect_card) |
800 | return; | |
801 | ||
a45c6cb8 | 802 | disable_irq(host->irq); |
b417577d AH |
803 | |
804 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
a45c6cb8 MC |
805 | OMAP_HSMMC_WRITE(host->base, CON, |
806 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); | |
807 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); | |
808 | ||
809 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
810 | while ((reg != CC) && time_before(jiffies, timeout)) | |
811 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC; | |
812 | ||
813 | OMAP_HSMMC_WRITE(host->base, CON, | |
814 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); | |
c653a6d4 AH |
815 | |
816 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
817 | OMAP_HSMMC_READ(host->base, STAT); | |
818 | ||
a45c6cb8 MC |
819 | enable_irq(host->irq); |
820 | } | |
821 | ||
822 | static inline | |
70a3341a | 823 | int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
824 | { |
825 | int r = 1; | |
826 | ||
191d1f1d DK |
827 | if (mmc_slot(host).get_cover_state) |
828 | r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); | |
a45c6cb8 MC |
829 | return r; |
830 | } | |
831 | ||
832 | static ssize_t | |
70a3341a | 833 | omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
834 | char *buf) |
835 | { | |
836 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 837 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 838 | |
70a3341a DK |
839 | return sprintf(buf, "%s\n", |
840 | omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); | |
a45c6cb8 MC |
841 | } |
842 | ||
70a3341a | 843 | static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); |
a45c6cb8 MC |
844 | |
845 | static ssize_t | |
70a3341a | 846 | omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
847 | char *buf) |
848 | { | |
849 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 850 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 851 | |
191d1f1d | 852 | return sprintf(buf, "%s\n", mmc_slot(host).name); |
a45c6cb8 MC |
853 | } |
854 | ||
70a3341a | 855 | static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); |
a45c6cb8 MC |
856 | |
857 | /* | |
858 | * Configure the response type and send the cmd. | |
859 | */ | |
860 | static void | |
70a3341a | 861 | omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, |
a45c6cb8 MC |
862 | struct mmc_data *data) |
863 | { | |
864 | int cmdreg = 0, resptype = 0, cmdtype = 0; | |
865 | ||
866 | dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", | |
867 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); | |
868 | host->cmd = cmd; | |
869 | ||
93caf8e6 | 870 | omap_hsmmc_enable_irq(host, cmd); |
a45c6cb8 | 871 | |
4a694dc9 | 872 | host->response_busy = 0; |
a45c6cb8 MC |
873 | if (cmd->flags & MMC_RSP_PRESENT) { |
874 | if (cmd->flags & MMC_RSP_136) | |
875 | resptype = 1; | |
4a694dc9 AH |
876 | else if (cmd->flags & MMC_RSP_BUSY) { |
877 | resptype = 3; | |
878 | host->response_busy = 1; | |
879 | } else | |
a45c6cb8 MC |
880 | resptype = 2; |
881 | } | |
882 | ||
883 | /* | |
884 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on | |
885 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need | |
886 | * a val of 0x3, rest 0x0. | |
887 | */ | |
888 | if (cmd == host->mrq->stop) | |
889 | cmdtype = 0x3; | |
890 | ||
891 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); | |
892 | ||
893 | if (data) { | |
894 | cmdreg |= DP_SELECT | MSBS | BCE; | |
895 | if (data->flags & MMC_DATA_READ) | |
896 | cmdreg |= DDIR; | |
897 | else | |
898 | cmdreg &= ~(DDIR); | |
899 | } | |
900 | ||
901 | if (host->use_dma) | |
902 | cmdreg |= DMA_EN; | |
903 | ||
b417577d | 904 | host->req_in_progress = 1; |
4dffd7a2 | 905 | |
a45c6cb8 MC |
906 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); |
907 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); | |
908 | } | |
909 | ||
0ccd76d4 | 910 | static int |
70a3341a | 911 | omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) |
0ccd76d4 JY |
912 | { |
913 | if (data->flags & MMC_DATA_WRITE) | |
914 | return DMA_TO_DEVICE; | |
915 | else | |
916 | return DMA_FROM_DEVICE; | |
917 | } | |
918 | ||
b417577d AH |
919 | static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) |
920 | { | |
921 | int dma_ch; | |
922 | ||
923 | spin_lock(&host->irq_lock); | |
924 | host->req_in_progress = 0; | |
925 | dma_ch = host->dma_ch; | |
926 | spin_unlock(&host->irq_lock); | |
927 | ||
928 | omap_hsmmc_disable_irq(host); | |
929 | /* Do not complete the request if DMA is still in progress */ | |
930 | if (mrq->data && host->use_dma && dma_ch != -1) | |
931 | return; | |
932 | host->mrq = NULL; | |
933 | mmc_request_done(host->mmc, mrq); | |
934 | } | |
935 | ||
a45c6cb8 MC |
936 | /* |
937 | * Notify the transfer complete to MMC core | |
938 | */ | |
939 | static void | |
70a3341a | 940 | omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) |
a45c6cb8 | 941 | { |
4a694dc9 AH |
942 | if (!data) { |
943 | struct mmc_request *mrq = host->mrq; | |
944 | ||
23050103 AH |
945 | /* TC before CC from CMD6 - don't know why, but it happens */ |
946 | if (host->cmd && host->cmd->opcode == 6 && | |
947 | host->response_busy) { | |
948 | host->response_busy = 0; | |
949 | return; | |
950 | } | |
951 | ||
b417577d | 952 | omap_hsmmc_request_done(host, mrq); |
4a694dc9 AH |
953 | return; |
954 | } | |
955 | ||
a45c6cb8 MC |
956 | host->data = NULL; |
957 | ||
a45c6cb8 MC |
958 | if (!data->error) |
959 | data->bytes_xfered += data->blocks * (data->blksz); | |
960 | else | |
961 | data->bytes_xfered = 0; | |
962 | ||
963 | if (!data->stop) { | |
b417577d | 964 | omap_hsmmc_request_done(host, data->mrq); |
a45c6cb8 MC |
965 | return; |
966 | } | |
70a3341a | 967 | omap_hsmmc_start_command(host, data->stop, NULL); |
a45c6cb8 MC |
968 | } |
969 | ||
970 | /* | |
971 | * Notify the core about command completion | |
972 | */ | |
973 | static void | |
70a3341a | 974 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) |
a45c6cb8 MC |
975 | { |
976 | host->cmd = NULL; | |
977 | ||
978 | if (cmd->flags & MMC_RSP_PRESENT) { | |
979 | if (cmd->flags & MMC_RSP_136) { | |
980 | /* response type 2 */ | |
981 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); | |
982 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); | |
983 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); | |
984 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); | |
985 | } else { | |
986 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
987 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); | |
988 | } | |
989 | } | |
b417577d AH |
990 | if ((host->data == NULL && !host->response_busy) || cmd->error) |
991 | omap_hsmmc_request_done(host, cmd->mrq); | |
a45c6cb8 MC |
992 | } |
993 | ||
994 | /* | |
995 | * DMA clean up for command errors | |
996 | */ | |
70a3341a | 997 | static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) |
a45c6cb8 | 998 | { |
b417577d AH |
999 | int dma_ch; |
1000 | ||
82788ff5 | 1001 | host->data->error = errno; |
a45c6cb8 | 1002 | |
b417577d AH |
1003 | spin_lock(&host->irq_lock); |
1004 | dma_ch = host->dma_ch; | |
1005 | host->dma_ch = -1; | |
1006 | spin_unlock(&host->irq_lock); | |
1007 | ||
1008 | if (host->use_dma && dma_ch != -1) { | |
a9120c33 PF |
1009 | dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, |
1010 | host->data->sg_len, | |
70a3341a | 1011 | omap_hsmmc_get_dma_dir(host, host->data)); |
b417577d | 1012 | omap_free_dma(dma_ch); |
a45c6cb8 MC |
1013 | } |
1014 | host->data = NULL; | |
a45c6cb8 MC |
1015 | } |
1016 | ||
1017 | /* | |
1018 | * Readable error output | |
1019 | */ | |
1020 | #ifdef CONFIG_MMC_DEBUG | |
699b958b | 1021 | static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) |
a45c6cb8 MC |
1022 | { |
1023 | /* --- means reserved bit without definition at documentation */ | |
70a3341a | 1024 | static const char *omap_hsmmc_status_bits[] = { |
699b958b AH |
1025 | "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , |
1026 | "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", | |
1027 | "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , | |
1028 | "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" | |
a45c6cb8 MC |
1029 | }; |
1030 | char res[256]; | |
1031 | char *buf = res; | |
1032 | int len, i; | |
1033 | ||
1034 | len = sprintf(buf, "MMC IRQ 0x%x :", status); | |
1035 | buf += len; | |
1036 | ||
70a3341a | 1037 | for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) |
a45c6cb8 | 1038 | if (status & (1 << i)) { |
70a3341a | 1039 | len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); |
a45c6cb8 MC |
1040 | buf += len; |
1041 | } | |
1042 | ||
1043 | dev_dbg(mmc_dev(host->mmc), "%s\n", res); | |
1044 | } | |
699b958b AH |
1045 | #else |
1046 | static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, | |
1047 | u32 status) | |
1048 | { | |
1049 | } | |
a45c6cb8 MC |
1050 | #endif /* CONFIG_MMC_DEBUG */ |
1051 | ||
3ebf74b1 JP |
1052 | /* |
1053 | * MMC controller internal state machines reset | |
1054 | * | |
1055 | * Used to reset command or data internal state machines, using respectively | |
1056 | * SRC or SRD bit of SYSCTL register | |
1057 | * Can be called from interrupt context | |
1058 | */ | |
70a3341a DK |
1059 | static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, |
1060 | unsigned long bit) | |
3ebf74b1 JP |
1061 | { |
1062 | unsigned long i = 0; | |
1063 | unsigned long limit = (loops_per_jiffy * | |
1064 | msecs_to_jiffies(MMC_TIMEOUT_MS)); | |
1065 | ||
1066 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
1067 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); | |
1068 | ||
07ad64b6 MC |
1069 | /* |
1070 | * OMAP4 ES2 and greater has an updated reset logic. | |
1071 | * Monitor a 0->1 transition first | |
1072 | */ | |
1073 | if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { | |
b432b4b3 | 1074 | while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) |
07ad64b6 MC |
1075 | && (i++ < limit)) |
1076 | cpu_relax(); | |
1077 | } | |
1078 | i = 0; | |
1079 | ||
3ebf74b1 JP |
1080 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && |
1081 | (i++ < limit)) | |
1082 | cpu_relax(); | |
1083 | ||
1084 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) | |
1085 | dev_err(mmc_dev(host->mmc), | |
1086 | "Timeout waiting on controller reset in %s\n", | |
1087 | __func__); | |
1088 | } | |
a45c6cb8 | 1089 | |
b417577d | 1090 | static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) |
a45c6cb8 | 1091 | { |
a45c6cb8 | 1092 | struct mmc_data *data; |
b417577d AH |
1093 | int end_cmd = 0, end_trans = 0; |
1094 | ||
1095 | if (!host->req_in_progress) { | |
1096 | do { | |
1097 | OMAP_HSMMC_WRITE(host->base, STAT, status); | |
1098 | /* Flush posted write */ | |
1099 | status = OMAP_HSMMC_READ(host->base, STAT); | |
1100 | } while (status & INT_EN_MASK); | |
1101 | return; | |
a45c6cb8 MC |
1102 | } |
1103 | ||
1104 | data = host->data; | |
a45c6cb8 MC |
1105 | dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); |
1106 | ||
1107 | if (status & ERR) { | |
699b958b | 1108 | omap_hsmmc_dbg_report_irq(host, status); |
a45c6cb8 MC |
1109 | if ((status & CMD_TIMEOUT) || |
1110 | (status & CMD_CRC)) { | |
1111 | if (host->cmd) { | |
1112 | if (status & CMD_TIMEOUT) { | |
70a3341a DK |
1113 | omap_hsmmc_reset_controller_fsm(host, |
1114 | SRC); | |
a45c6cb8 MC |
1115 | host->cmd->error = -ETIMEDOUT; |
1116 | } else { | |
1117 | host->cmd->error = -EILSEQ; | |
1118 | } | |
1119 | end_cmd = 1; | |
1120 | } | |
4a694dc9 AH |
1121 | if (host->data || host->response_busy) { |
1122 | if (host->data) | |
70a3341a DK |
1123 | omap_hsmmc_dma_cleanup(host, |
1124 | -ETIMEDOUT); | |
4a694dc9 | 1125 | host->response_busy = 0; |
70a3341a | 1126 | omap_hsmmc_reset_controller_fsm(host, SRD); |
c232f457 | 1127 | } |
a45c6cb8 MC |
1128 | } |
1129 | if ((status & DATA_TIMEOUT) || | |
1130 | (status & DATA_CRC)) { | |
4a694dc9 AH |
1131 | if (host->data || host->response_busy) { |
1132 | int err = (status & DATA_TIMEOUT) ? | |
1133 | -ETIMEDOUT : -EILSEQ; | |
1134 | ||
1135 | if (host->data) | |
70a3341a | 1136 | omap_hsmmc_dma_cleanup(host, err); |
a45c6cb8 | 1137 | else |
4a694dc9 AH |
1138 | host->mrq->cmd->error = err; |
1139 | host->response_busy = 0; | |
70a3341a | 1140 | omap_hsmmc_reset_controller_fsm(host, SRD); |
a45c6cb8 MC |
1141 | end_trans = 1; |
1142 | } | |
1143 | } | |
1144 | if (status & CARD_ERR) { | |
1145 | dev_dbg(mmc_dev(host->mmc), | |
1146 | "Ignoring card err CMD%d\n", host->cmd->opcode); | |
1147 | if (host->cmd) | |
1148 | end_cmd = 1; | |
1149 | if (host->data) | |
1150 | end_trans = 1; | |
1151 | } | |
1152 | } | |
1153 | ||
1154 | OMAP_HSMMC_WRITE(host->base, STAT, status); | |
1155 | ||
a8fe29d8 | 1156 | if (end_cmd || ((status & CC) && host->cmd)) |
70a3341a | 1157 | omap_hsmmc_cmd_done(host, host->cmd); |
0a40e647 | 1158 | if ((end_trans || (status & TC)) && host->mrq) |
70a3341a | 1159 | omap_hsmmc_xfer_done(host, data); |
b417577d | 1160 | } |
a45c6cb8 | 1161 | |
b417577d AH |
1162 | /* |
1163 | * MMC controller IRQ handler | |
1164 | */ | |
1165 | static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) | |
1166 | { | |
1167 | struct omap_hsmmc_host *host = dev_id; | |
1168 | int status; | |
1169 | ||
1170 | status = OMAP_HSMMC_READ(host->base, STAT); | |
1171 | do { | |
1172 | omap_hsmmc_do_irq(host, status); | |
1173 | /* Flush posted write */ | |
1174 | status = OMAP_HSMMC_READ(host->base, STAT); | |
1175 | } while (status & INT_EN_MASK); | |
4dffd7a2 | 1176 | |
a45c6cb8 MC |
1177 | return IRQ_HANDLED; |
1178 | } | |
1179 | ||
70a3341a | 1180 | static void set_sd_bus_power(struct omap_hsmmc_host *host) |
e13bb300 AH |
1181 | { |
1182 | unsigned long i; | |
1183 | ||
1184 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
1185 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
1186 | for (i = 0; i < loops_per_jiffy; i++) { | |
1187 | if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) | |
1188 | break; | |
1189 | cpu_relax(); | |
1190 | } | |
1191 | } | |
1192 | ||
a45c6cb8 | 1193 | /* |
eb250826 DB |
1194 | * Switch MMC interface voltage ... only relevant for MMC1. |
1195 | * | |
1196 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. | |
1197 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. | |
1198 | * Some chips, like eMMC ones, use internal transceivers. | |
a45c6cb8 | 1199 | */ |
70a3341a | 1200 | static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) |
a45c6cb8 MC |
1201 | { |
1202 | u32 reg_val = 0; | |
1203 | int ret; | |
1204 | ||
1205 | /* Disable the clocks */ | |
fa4aa2d4 | 1206 | pm_runtime_put_sync(host->dev); |
2bec0893 AH |
1207 | if (host->got_dbclk) |
1208 | clk_disable(host->dbclk); | |
a45c6cb8 MC |
1209 | |
1210 | /* Turn the power off */ | |
1211 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); | |
a45c6cb8 MC |
1212 | |
1213 | /* Turn the power ON with given VDD 1.8 or 3.0v */ | |
2bec0893 AH |
1214 | if (!ret) |
1215 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, | |
1216 | vdd); | |
fa4aa2d4 | 1217 | pm_runtime_get_sync(host->dev); |
2bec0893 AH |
1218 | if (host->got_dbclk) |
1219 | clk_enable(host->dbclk); | |
1220 | ||
a45c6cb8 MC |
1221 | if (ret != 0) |
1222 | goto err; | |
1223 | ||
a45c6cb8 MC |
1224 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1225 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); | |
1226 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); | |
eb250826 | 1227 | |
a45c6cb8 MC |
1228 | /* |
1229 | * If a MMC dual voltage card is detected, the set_ios fn calls | |
1230 | * this fn with VDD bit set for 1.8V. Upon card removal from the | |
70a3341a | 1231 | * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. |
a45c6cb8 | 1232 | * |
eb250826 DB |
1233 | * Cope with a bit of slop in the range ... per data sheets: |
1234 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, | |
1235 | * but recommended values are 1.71V to 1.89V | |
1236 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, | |
1237 | * but recommended values are 2.7V to 3.3V | |
1238 | * | |
1239 | * Board setup code shouldn't permit anything very out-of-range. | |
1240 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the | |
1241 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. | |
a45c6cb8 | 1242 | */ |
eb250826 | 1243 | if ((1 << vdd) <= MMC_VDD_23_24) |
a45c6cb8 | 1244 | reg_val |= SDVS18; |
eb250826 DB |
1245 | else |
1246 | reg_val |= SDVS30; | |
a45c6cb8 MC |
1247 | |
1248 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); | |
e13bb300 | 1249 | set_sd_bus_power(host); |
a45c6cb8 MC |
1250 | |
1251 | return 0; | |
1252 | err: | |
1253 | dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); | |
1254 | return ret; | |
1255 | } | |
1256 | ||
b62f6228 AH |
1257 | /* Protect the card while the cover is open */ |
1258 | static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) | |
1259 | { | |
1260 | if (!mmc_slot(host).get_cover_state) | |
1261 | return; | |
1262 | ||
1263 | host->reqs_blocked = 0; | |
1264 | if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { | |
1265 | if (host->protect_card) { | |
a3c76eb9 | 1266 | pr_info("%s: cover is closed, " |
b62f6228 AH |
1267 | "card is now accessible\n", |
1268 | mmc_hostname(host->mmc)); | |
1269 | host->protect_card = 0; | |
1270 | } | |
1271 | } else { | |
1272 | if (!host->protect_card) { | |
3f8ddb03 | 1273 | pr_info("%s: cover is open, " |
b62f6228 AH |
1274 | "card is now inaccessible\n", |
1275 | mmc_hostname(host->mmc)); | |
1276 | host->protect_card = 1; | |
1277 | } | |
1278 | } | |
1279 | } | |
1280 | ||
a45c6cb8 MC |
1281 | /* |
1282 | * Work Item to notify the core about card insertion/removal | |
1283 | */ | |
70a3341a | 1284 | static void omap_hsmmc_detect(struct work_struct *work) |
a45c6cb8 | 1285 | { |
70a3341a DK |
1286 | struct omap_hsmmc_host *host = |
1287 | container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); | |
249d0fa9 | 1288 | struct omap_mmc_slot_data *slot = &mmc_slot(host); |
a6b2240d AH |
1289 | int carddetect; |
1290 | ||
1291 | if (host->suspended) | |
1292 | return; | |
1293 | ||
1294 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); | |
249d0fa9 | 1295 | |
191d1f1d | 1296 | if (slot->card_detect) |
db0fefc5 | 1297 | carddetect = slot->card_detect(host->dev, host->slot_id); |
b62f6228 AH |
1298 | else { |
1299 | omap_hsmmc_protect_card(host); | |
a6b2240d | 1300 | carddetect = -ENOSYS; |
b62f6228 | 1301 | } |
a45c6cb8 | 1302 | |
cdeebadd | 1303 | if (carddetect) |
a45c6cb8 | 1304 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); |
cdeebadd | 1305 | else |
a45c6cb8 | 1306 | mmc_detect_change(host->mmc, (HZ * 50) / 1000); |
a45c6cb8 MC |
1307 | } |
1308 | ||
1309 | /* | |
1310 | * ISR for handling card insertion and removal | |
1311 | */ | |
70a3341a | 1312 | static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) |
a45c6cb8 | 1313 | { |
70a3341a | 1314 | struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; |
a45c6cb8 | 1315 | |
a6b2240d AH |
1316 | if (host->suspended) |
1317 | return IRQ_HANDLED; | |
a45c6cb8 MC |
1318 | schedule_work(&host->mmc_carddetect_work); |
1319 | ||
1320 | return IRQ_HANDLED; | |
1321 | } | |
1322 | ||
70a3341a | 1323 | static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, |
0ccd76d4 JY |
1324 | struct mmc_data *data) |
1325 | { | |
1326 | int sync_dev; | |
1327 | ||
f3e2f1dd GI |
1328 | if (data->flags & MMC_DATA_WRITE) |
1329 | sync_dev = host->dma_line_tx; | |
1330 | else | |
1331 | sync_dev = host->dma_line_rx; | |
0ccd76d4 JY |
1332 | return sync_dev; |
1333 | } | |
1334 | ||
70a3341a | 1335 | static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, |
0ccd76d4 JY |
1336 | struct mmc_data *data, |
1337 | struct scatterlist *sgl) | |
1338 | { | |
1339 | int blksz, nblk, dma_ch; | |
1340 | ||
1341 | dma_ch = host->dma_ch; | |
1342 | if (data->flags & MMC_DATA_WRITE) { | |
1343 | omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
1344 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); | |
1345 | omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, | |
1346 | sg_dma_address(sgl), 0, 0); | |
1347 | } else { | |
1348 | omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
191d1f1d | 1349 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); |
0ccd76d4 JY |
1350 | omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, |
1351 | sg_dma_address(sgl), 0, 0); | |
1352 | } | |
1353 | ||
1354 | blksz = host->data->blksz; | |
1355 | nblk = sg_dma_len(sgl) / blksz; | |
1356 | ||
1357 | omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, | |
1358 | blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, | |
70a3341a | 1359 | omap_hsmmc_get_dma_sync_dev(host, data), |
0ccd76d4 JY |
1360 | !(data->flags & MMC_DATA_WRITE)); |
1361 | ||
1362 | omap_start_dma(dma_ch); | |
1363 | } | |
1364 | ||
a45c6cb8 MC |
1365 | /* |
1366 | * DMA call back function | |
1367 | */ | |
b417577d | 1368 | static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) |
a45c6cb8 | 1369 | { |
b417577d | 1370 | struct omap_hsmmc_host *host = cb_data; |
770d7432 | 1371 | struct mmc_data *data; |
b417577d | 1372 | int dma_ch, req_in_progress; |
a45c6cb8 | 1373 | |
f3584e5e V |
1374 | if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { |
1375 | dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n", | |
1376 | ch_status); | |
1377 | return; | |
1378 | } | |
a45c6cb8 | 1379 | |
b417577d AH |
1380 | spin_lock(&host->irq_lock); |
1381 | if (host->dma_ch < 0) { | |
1382 | spin_unlock(&host->irq_lock); | |
a45c6cb8 | 1383 | return; |
b417577d | 1384 | } |
a45c6cb8 | 1385 | |
770d7432 | 1386 | data = host->mrq->data; |
0ccd76d4 JY |
1387 | host->dma_sg_idx++; |
1388 | if (host->dma_sg_idx < host->dma_len) { | |
1389 | /* Fire up the next transfer. */ | |
b417577d AH |
1390 | omap_hsmmc_config_dma_params(host, data, |
1391 | data->sg + host->dma_sg_idx); | |
1392 | spin_unlock(&host->irq_lock); | |
0ccd76d4 JY |
1393 | return; |
1394 | } | |
1395 | ||
9782aff8 PF |
1396 | if (!data->host_cookie) |
1397 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
1398 | omap_hsmmc_get_dma_dir(host, data)); | |
b417577d AH |
1399 | |
1400 | req_in_progress = host->req_in_progress; | |
1401 | dma_ch = host->dma_ch; | |
a45c6cb8 | 1402 | host->dma_ch = -1; |
b417577d AH |
1403 | spin_unlock(&host->irq_lock); |
1404 | ||
1405 | omap_free_dma(dma_ch); | |
1406 | ||
1407 | /* If DMA has finished after TC, complete the request */ | |
1408 | if (!req_in_progress) { | |
1409 | struct mmc_request *mrq = host->mrq; | |
1410 | ||
1411 | host->mrq = NULL; | |
1412 | mmc_request_done(host->mmc, mrq); | |
1413 | } | |
a45c6cb8 MC |
1414 | } |
1415 | ||
9782aff8 PF |
1416 | static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, |
1417 | struct mmc_data *data, | |
1418 | struct omap_hsmmc_next *next) | |
1419 | { | |
1420 | int dma_len; | |
1421 | ||
1422 | if (!next && data->host_cookie && | |
1423 | data->host_cookie != host->next_data.cookie) { | |
a3c76eb9 | 1424 | pr_warning("[%s] invalid cookie: data->host_cookie %d" |
9782aff8 PF |
1425 | " host->next_data.cookie %d\n", |
1426 | __func__, data->host_cookie, host->next_data.cookie); | |
1427 | data->host_cookie = 0; | |
1428 | } | |
1429 | ||
1430 | /* Check if next job is already prepared */ | |
1431 | if (next || | |
1432 | (!next && data->host_cookie != host->next_data.cookie)) { | |
1433 | dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
1434 | data->sg_len, | |
1435 | omap_hsmmc_get_dma_dir(host, data)); | |
1436 | ||
1437 | } else { | |
1438 | dma_len = host->next_data.dma_len; | |
1439 | host->next_data.dma_len = 0; | |
1440 | } | |
1441 | ||
1442 | ||
1443 | if (dma_len == 0) | |
1444 | return -EINVAL; | |
1445 | ||
1446 | if (next) { | |
1447 | next->dma_len = dma_len; | |
1448 | data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; | |
1449 | } else | |
1450 | host->dma_len = dma_len; | |
1451 | ||
1452 | return 0; | |
1453 | } | |
1454 | ||
a45c6cb8 MC |
1455 | /* |
1456 | * Routine to configure and start DMA for the MMC card | |
1457 | */ | |
70a3341a DK |
1458 | static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, |
1459 | struct mmc_request *req) | |
a45c6cb8 | 1460 | { |
b417577d | 1461 | int dma_ch = 0, ret = 0, i; |
a45c6cb8 MC |
1462 | struct mmc_data *data = req->data; |
1463 | ||
0ccd76d4 | 1464 | /* Sanity check: all the SG entries must be aligned by block size. */ |
a3f406f8 | 1465 | for (i = 0; i < data->sg_len; i++) { |
0ccd76d4 JY |
1466 | struct scatterlist *sgl; |
1467 | ||
1468 | sgl = data->sg + i; | |
1469 | if (sgl->length % data->blksz) | |
1470 | return -EINVAL; | |
1471 | } | |
1472 | if ((data->blksz % 4) != 0) | |
1473 | /* REVISIT: The MMC buffer increments only when MSB is written. | |
1474 | * Return error for blksz which is non multiple of four. | |
1475 | */ | |
1476 | return -EINVAL; | |
1477 | ||
b417577d | 1478 | BUG_ON(host->dma_ch != -1); |
a45c6cb8 | 1479 | |
70a3341a DK |
1480 | ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), |
1481 | "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); | |
a45c6cb8 | 1482 | if (ret != 0) { |
0ccd76d4 | 1483 | dev_err(mmc_dev(host->mmc), |
a45c6cb8 MC |
1484 | "%s: omap_request_dma() failed with %d\n", |
1485 | mmc_hostname(host->mmc), ret); | |
1486 | return ret; | |
1487 | } | |
9782aff8 PF |
1488 | ret = omap_hsmmc_pre_dma_transfer(host, data, NULL); |
1489 | if (ret) | |
1490 | return ret; | |
a45c6cb8 | 1491 | |
a45c6cb8 | 1492 | host->dma_ch = dma_ch; |
0ccd76d4 | 1493 | host->dma_sg_idx = 0; |
a45c6cb8 | 1494 | |
70a3341a | 1495 | omap_hsmmc_config_dma_params(host, data, data->sg); |
a45c6cb8 | 1496 | |
a45c6cb8 MC |
1497 | return 0; |
1498 | } | |
1499 | ||
70a3341a | 1500 | static void set_data_timeout(struct omap_hsmmc_host *host, |
e2bf08d6 AH |
1501 | unsigned int timeout_ns, |
1502 | unsigned int timeout_clks) | |
a45c6cb8 MC |
1503 | { |
1504 | unsigned int timeout, cycle_ns; | |
1505 | uint32_t reg, clkd, dto = 0; | |
1506 | ||
1507 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); | |
1508 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; | |
1509 | if (clkd == 0) | |
1510 | clkd = 1; | |
1511 | ||
1512 | cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); | |
e2bf08d6 AH |
1513 | timeout = timeout_ns / cycle_ns; |
1514 | timeout += timeout_clks; | |
a45c6cb8 MC |
1515 | if (timeout) { |
1516 | while ((timeout & 0x80000000) == 0) { | |
1517 | dto += 1; | |
1518 | timeout <<= 1; | |
1519 | } | |
1520 | dto = 31 - dto; | |
1521 | timeout <<= 1; | |
1522 | if (timeout && dto) | |
1523 | dto += 1; | |
1524 | if (dto >= 13) | |
1525 | dto -= 13; | |
1526 | else | |
1527 | dto = 0; | |
1528 | if (dto > 14) | |
1529 | dto = 14; | |
1530 | } | |
1531 | ||
1532 | reg &= ~DTO_MASK; | |
1533 | reg |= dto << DTO_SHIFT; | |
1534 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); | |
1535 | } | |
1536 | ||
1537 | /* | |
1538 | * Configure block length for MMC/SD cards and initiate the transfer. | |
1539 | */ | |
1540 | static int | |
70a3341a | 1541 | omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) |
a45c6cb8 MC |
1542 | { |
1543 | int ret; | |
1544 | host->data = req->data; | |
1545 | ||
1546 | if (req->data == NULL) { | |
a45c6cb8 | 1547 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
e2bf08d6 AH |
1548 | /* |
1549 | * Set an arbitrary 100ms data timeout for commands with | |
1550 | * busy signal. | |
1551 | */ | |
1552 | if (req->cmd->flags & MMC_RSP_BUSY) | |
1553 | set_data_timeout(host, 100000000U, 0); | |
a45c6cb8 MC |
1554 | return 0; |
1555 | } | |
1556 | ||
1557 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) | |
1558 | | (req->data->blocks << 16)); | |
e2bf08d6 | 1559 | set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); |
a45c6cb8 | 1560 | |
a45c6cb8 | 1561 | if (host->use_dma) { |
70a3341a | 1562 | ret = omap_hsmmc_start_dma_transfer(host, req); |
a45c6cb8 MC |
1563 | if (ret != 0) { |
1564 | dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); | |
1565 | return ret; | |
1566 | } | |
1567 | } | |
1568 | return 0; | |
1569 | } | |
1570 | ||
9782aff8 PF |
1571 | static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
1572 | int err) | |
1573 | { | |
1574 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1575 | struct mmc_data *data = mrq->data; | |
1576 | ||
1577 | if (host->use_dma) { | |
1578 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
1579 | omap_hsmmc_get_dma_dir(host, data)); | |
1580 | data->host_cookie = 0; | |
1581 | } | |
1582 | } | |
1583 | ||
1584 | static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, | |
1585 | bool is_first_req) | |
1586 | { | |
1587 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1588 | ||
1589 | if (mrq->data->host_cookie) { | |
1590 | mrq->data->host_cookie = 0; | |
1591 | return ; | |
1592 | } | |
1593 | ||
1594 | if (host->use_dma) | |
1595 | if (omap_hsmmc_pre_dma_transfer(host, mrq->data, | |
1596 | &host->next_data)) | |
1597 | mrq->data->host_cookie = 0; | |
1598 | } | |
1599 | ||
a45c6cb8 MC |
1600 | /* |
1601 | * Request function. for read/write operation | |
1602 | */ | |
70a3341a | 1603 | static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) |
a45c6cb8 | 1604 | { |
70a3341a | 1605 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3f406f8 | 1606 | int err; |
a45c6cb8 | 1607 | |
b417577d AH |
1608 | BUG_ON(host->req_in_progress); |
1609 | BUG_ON(host->dma_ch != -1); | |
1610 | if (host->protect_card) { | |
1611 | if (host->reqs_blocked < 3) { | |
1612 | /* | |
1613 | * Ensure the controller is left in a consistent | |
1614 | * state by resetting the command and data state | |
1615 | * machines. | |
1616 | */ | |
1617 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
1618 | omap_hsmmc_reset_controller_fsm(host, SRC); | |
1619 | host->reqs_blocked += 1; | |
1620 | } | |
1621 | req->cmd->error = -EBADF; | |
1622 | if (req->data) | |
1623 | req->data->error = -EBADF; | |
1624 | req->cmd->retries = 0; | |
1625 | mmc_request_done(mmc, req); | |
1626 | return; | |
1627 | } else if (host->reqs_blocked) | |
1628 | host->reqs_blocked = 0; | |
a45c6cb8 MC |
1629 | WARN_ON(host->mrq != NULL); |
1630 | host->mrq = req; | |
70a3341a | 1631 | err = omap_hsmmc_prepare_data(host, req); |
a3f406f8 JL |
1632 | if (err) { |
1633 | req->cmd->error = err; | |
1634 | if (req->data) | |
1635 | req->data->error = err; | |
1636 | host->mrq = NULL; | |
1637 | mmc_request_done(mmc, req); | |
1638 | return; | |
1639 | } | |
1640 | ||
70a3341a | 1641 | omap_hsmmc_start_command(host, req->cmd, req->data); |
a45c6cb8 MC |
1642 | } |
1643 | ||
a45c6cb8 | 1644 | /* Routine to configure clock values. Exposed API to core */ |
70a3341a | 1645 | static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
a45c6cb8 | 1646 | { |
70a3341a | 1647 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3621465 | 1648 | int do_send_init_stream = 0; |
a45c6cb8 | 1649 | |
fa4aa2d4 | 1650 | pm_runtime_get_sync(host->dev); |
5e2ea617 | 1651 | |
a3621465 AH |
1652 | if (ios->power_mode != host->power_mode) { |
1653 | switch (ios->power_mode) { | |
1654 | case MMC_POWER_OFF: | |
1655 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1656 | 0, 0); | |
623821f7 | 1657 | host->vdd = 0; |
a3621465 AH |
1658 | break; |
1659 | case MMC_POWER_UP: | |
1660 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1661 | 1, ios->vdd); | |
623821f7 | 1662 | host->vdd = ios->vdd; |
a3621465 AH |
1663 | break; |
1664 | case MMC_POWER_ON: | |
1665 | do_send_init_stream = 1; | |
1666 | break; | |
1667 | } | |
1668 | host->power_mode = ios->power_mode; | |
a45c6cb8 MC |
1669 | } |
1670 | ||
dd498eff DK |
1671 | /* FIXME: set registers based only on changes to ios */ |
1672 | ||
3796fb8a | 1673 | omap_hsmmc_set_bus_width(host); |
a45c6cb8 | 1674 | |
4621d5f8 | 1675 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
eb250826 DB |
1676 | /* Only MMC1 can interface at 3V without some flavor |
1677 | * of external transceiver; but they all handle 1.8V. | |
1678 | */ | |
a45c6cb8 MC |
1679 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
1680 | (ios->vdd == DUAL_VOLT_OCR_BIT)) { | |
1681 | /* | |
1682 | * The mmc_select_voltage fn of the core does | |
1683 | * not seem to set the power_mode to | |
1684 | * MMC_POWER_UP upon recalculating the voltage. | |
1685 | * vdd 1.8v. | |
1686 | */ | |
70a3341a DK |
1687 | if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) |
1688 | dev_dbg(mmc_dev(host->mmc), | |
a45c6cb8 MC |
1689 | "Switch operation failed\n"); |
1690 | } | |
1691 | } | |
1692 | ||
5934df2f | 1693 | omap_hsmmc_set_clock(host); |
a45c6cb8 | 1694 | |
a3621465 | 1695 | if (do_send_init_stream) |
a45c6cb8 MC |
1696 | send_init_stream(host); |
1697 | ||
3796fb8a | 1698 | omap_hsmmc_set_bus_mode(host); |
5e2ea617 | 1699 | |
fa4aa2d4 | 1700 | pm_runtime_put_autosuspend(host->dev); |
a45c6cb8 MC |
1701 | } |
1702 | ||
1703 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) | |
1704 | { | |
70a3341a | 1705 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1706 | |
191d1f1d | 1707 | if (!mmc_slot(host).card_detect) |
a45c6cb8 | 1708 | return -ENOSYS; |
db0fefc5 | 1709 | return mmc_slot(host).card_detect(host->dev, host->slot_id); |
a45c6cb8 MC |
1710 | } |
1711 | ||
1712 | static int omap_hsmmc_get_ro(struct mmc_host *mmc) | |
1713 | { | |
70a3341a | 1714 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1715 | |
191d1f1d | 1716 | if (!mmc_slot(host).get_ro) |
a45c6cb8 | 1717 | return -ENOSYS; |
191d1f1d | 1718 | return mmc_slot(host).get_ro(host->dev, 0); |
a45c6cb8 MC |
1719 | } |
1720 | ||
4816858c GI |
1721 | static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) |
1722 | { | |
1723 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1724 | ||
1725 | if (mmc_slot(host).init_card) | |
1726 | mmc_slot(host).init_card(card); | |
1727 | } | |
1728 | ||
70a3341a | 1729 | static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) |
1b331e69 KK |
1730 | { |
1731 | u32 hctl, capa, value; | |
1732 | ||
1733 | /* Only MMC1 supports 3.0V */ | |
4621d5f8 | 1734 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
1b331e69 KK |
1735 | hctl = SDVS30; |
1736 | capa = VS30 | VS18; | |
1737 | } else { | |
1738 | hctl = SDVS18; | |
1739 | capa = VS18; | |
1740 | } | |
1741 | ||
1742 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; | |
1743 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); | |
1744 | ||
1745 | value = OMAP_HSMMC_READ(host->base, CAPA); | |
1746 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); | |
1747 | ||
1748 | /* Set the controller to AUTO IDLE mode */ | |
1749 | value = OMAP_HSMMC_READ(host->base, SYSCONFIG); | |
1750 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); | |
1751 | ||
1752 | /* Set SD bus power bit */ | |
e13bb300 | 1753 | set_sd_bus_power(host); |
1b331e69 KK |
1754 | } |
1755 | ||
70a3341a | 1756 | static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) |
dd498eff | 1757 | { |
70a3341a | 1758 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1759 | |
fa4aa2d4 B |
1760 | pm_runtime_get_sync(host->dev); |
1761 | ||
dd498eff DK |
1762 | return 0; |
1763 | } | |
1764 | ||
70a3341a | 1765 | static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) |
dd498eff | 1766 | { |
70a3341a | 1767 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1768 | |
fa4aa2d4 B |
1769 | pm_runtime_mark_last_busy(host->dev); |
1770 | pm_runtime_put_autosuspend(host->dev); | |
1771 | ||
dd498eff DK |
1772 | return 0; |
1773 | } | |
1774 | ||
70a3341a DK |
1775 | static const struct mmc_host_ops omap_hsmmc_ops = { |
1776 | .enable = omap_hsmmc_enable_fclk, | |
1777 | .disable = omap_hsmmc_disable_fclk, | |
9782aff8 PF |
1778 | .post_req = omap_hsmmc_post_req, |
1779 | .pre_req = omap_hsmmc_pre_req, | |
70a3341a DK |
1780 | .request = omap_hsmmc_request, |
1781 | .set_ios = omap_hsmmc_set_ios, | |
dd498eff DK |
1782 | .get_cd = omap_hsmmc_get_cd, |
1783 | .get_ro = omap_hsmmc_get_ro, | |
4816858c | 1784 | .init_card = omap_hsmmc_init_card, |
dd498eff DK |
1785 | /* NYET -- enable_sdio_irq */ |
1786 | }; | |
1787 | ||
d900f712 DK |
1788 | #ifdef CONFIG_DEBUG_FS |
1789 | ||
70a3341a | 1790 | static int omap_hsmmc_regs_show(struct seq_file *s, void *data) |
d900f712 DK |
1791 | { |
1792 | struct mmc_host *mmc = s->private; | |
70a3341a | 1793 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
11dd62a7 DK |
1794 | int context_loss = 0; |
1795 | ||
70a3341a DK |
1796 | if (host->pdata->get_context_loss_count) |
1797 | context_loss = host->pdata->get_context_loss_count(host->dev); | |
d900f712 | 1798 | |
5e2ea617 AH |
1799 | seq_printf(s, "mmc%d:\n" |
1800 | " enabled:\t%d\n" | |
dd498eff | 1801 | " dpm_state:\t%d\n" |
5e2ea617 | 1802 | " nesting_cnt:\t%d\n" |
11dd62a7 | 1803 | " ctx_loss:\t%d:%d\n" |
5e2ea617 | 1804 | "\nregs:\n", |
dd498eff DK |
1805 | mmc->index, mmc->enabled ? 1 : 0, |
1806 | host->dpm_state, mmc->nesting_cnt, | |
11dd62a7 | 1807 | host->context_loss, context_loss); |
5e2ea617 | 1808 | |
7a8c2cef | 1809 | if (host->suspended) { |
dd498eff DK |
1810 | seq_printf(s, "host suspended, can't read registers\n"); |
1811 | return 0; | |
1812 | } | |
1813 | ||
fa4aa2d4 | 1814 | pm_runtime_get_sync(host->dev); |
d900f712 DK |
1815 | |
1816 | seq_printf(s, "SYSCONFIG:\t0x%08x\n", | |
1817 | OMAP_HSMMC_READ(host->base, SYSCONFIG)); | |
1818 | seq_printf(s, "CON:\t\t0x%08x\n", | |
1819 | OMAP_HSMMC_READ(host->base, CON)); | |
1820 | seq_printf(s, "HCTL:\t\t0x%08x\n", | |
1821 | OMAP_HSMMC_READ(host->base, HCTL)); | |
1822 | seq_printf(s, "SYSCTL:\t\t0x%08x\n", | |
1823 | OMAP_HSMMC_READ(host->base, SYSCTL)); | |
1824 | seq_printf(s, "IE:\t\t0x%08x\n", | |
1825 | OMAP_HSMMC_READ(host->base, IE)); | |
1826 | seq_printf(s, "ISE:\t\t0x%08x\n", | |
1827 | OMAP_HSMMC_READ(host->base, ISE)); | |
1828 | seq_printf(s, "CAPA:\t\t0x%08x\n", | |
1829 | OMAP_HSMMC_READ(host->base, CAPA)); | |
5e2ea617 | 1830 | |
fa4aa2d4 B |
1831 | pm_runtime_mark_last_busy(host->dev); |
1832 | pm_runtime_put_autosuspend(host->dev); | |
dd498eff | 1833 | |
d900f712 DK |
1834 | return 0; |
1835 | } | |
1836 | ||
70a3341a | 1837 | static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) |
d900f712 | 1838 | { |
70a3341a | 1839 | return single_open(file, omap_hsmmc_regs_show, inode->i_private); |
d900f712 DK |
1840 | } |
1841 | ||
1842 | static const struct file_operations mmc_regs_fops = { | |
70a3341a | 1843 | .open = omap_hsmmc_regs_open, |
d900f712 DK |
1844 | .read = seq_read, |
1845 | .llseek = seq_lseek, | |
1846 | .release = single_release, | |
1847 | }; | |
1848 | ||
70a3341a | 1849 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1850 | { |
1851 | if (mmc->debugfs_root) | |
1852 | debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, | |
1853 | mmc, &mmc_regs_fops); | |
1854 | } | |
1855 | ||
1856 | #else | |
1857 | ||
70a3341a | 1858 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1859 | { |
1860 | } | |
1861 | ||
1862 | #endif | |
1863 | ||
70a3341a | 1864 | static int __init omap_hsmmc_probe(struct platform_device *pdev) |
a45c6cb8 MC |
1865 | { |
1866 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; | |
1867 | struct mmc_host *mmc; | |
70a3341a | 1868 | struct omap_hsmmc_host *host = NULL; |
a45c6cb8 | 1869 | struct resource *res; |
db0fefc5 | 1870 | int ret, irq; |
a45c6cb8 MC |
1871 | |
1872 | if (pdata == NULL) { | |
1873 | dev_err(&pdev->dev, "Platform Data is missing\n"); | |
1874 | return -ENXIO; | |
1875 | } | |
1876 | ||
1877 | if (pdata->nr_slots == 0) { | |
1878 | dev_err(&pdev->dev, "No Slots\n"); | |
1879 | return -ENXIO; | |
1880 | } | |
1881 | ||
1882 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1883 | irq = platform_get_irq(pdev, 0); | |
1884 | if (res == NULL || irq < 0) | |
1885 | return -ENXIO; | |
1886 | ||
91a0b089 | 1887 | res->start += pdata->reg_offset; |
1888 | res->end += pdata->reg_offset; | |
984b203a | 1889 | res = request_mem_region(res->start, resource_size(res), pdev->name); |
a45c6cb8 MC |
1890 | if (res == NULL) |
1891 | return -EBUSY; | |
1892 | ||
db0fefc5 AH |
1893 | ret = omap_hsmmc_gpio_init(pdata); |
1894 | if (ret) | |
1895 | goto err; | |
1896 | ||
70a3341a | 1897 | mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); |
a45c6cb8 MC |
1898 | if (!mmc) { |
1899 | ret = -ENOMEM; | |
db0fefc5 | 1900 | goto err_alloc; |
a45c6cb8 MC |
1901 | } |
1902 | ||
1903 | host = mmc_priv(mmc); | |
1904 | host->mmc = mmc; | |
1905 | host->pdata = pdata; | |
1906 | host->dev = &pdev->dev; | |
1907 | host->use_dma = 1; | |
1908 | host->dev->dma_mask = &pdata->dma_mask; | |
1909 | host->dma_ch = -1; | |
1910 | host->irq = irq; | |
1911 | host->id = pdev->id; | |
1912 | host->slot_id = 0; | |
1913 | host->mapbase = res->start; | |
1914 | host->base = ioremap(host->mapbase, SZ_4K); | |
6da20c89 | 1915 | host->power_mode = MMC_POWER_OFF; |
9782aff8 | 1916 | host->next_data.cookie = 1; |
a45c6cb8 MC |
1917 | |
1918 | platform_set_drvdata(pdev, host); | |
70a3341a | 1919 | INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); |
a45c6cb8 | 1920 | |
7a8c2cef | 1921 | mmc->ops = &omap_hsmmc_ops; |
dd498eff | 1922 | |
e0eb2424 AH |
1923 | /* |
1924 | * If regulator_disable can only put vcc_aux to sleep then there is | |
1925 | * no off state. | |
1926 | */ | |
1927 | if (mmc_slot(host).vcc_aux_disable_is_sleep) | |
1928 | mmc_slot(host).no_off = 1; | |
1929 | ||
6b206efe AS |
1930 | mmc->f_min = OMAP_MMC_MIN_CLOCK; |
1931 | mmc->f_max = OMAP_MMC_MAX_CLOCK; | |
a45c6cb8 | 1932 | |
4dffd7a2 | 1933 | spin_lock_init(&host->irq_lock); |
a45c6cb8 | 1934 | |
6f7607cc | 1935 | host->fclk = clk_get(&pdev->dev, "fck"); |
a45c6cb8 MC |
1936 | if (IS_ERR(host->fclk)) { |
1937 | ret = PTR_ERR(host->fclk); | |
1938 | host->fclk = NULL; | |
a45c6cb8 MC |
1939 | goto err1; |
1940 | } | |
1941 | ||
70a3341a | 1942 | omap_hsmmc_context_save(host); |
11dd62a7 | 1943 | |
5e2ea617 | 1944 | mmc->caps |= MMC_CAP_DISABLE; |
9b68256c PW |
1945 | if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { |
1946 | dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); | |
1947 | mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; | |
1948 | } | |
dd498eff | 1949 | |
fa4aa2d4 B |
1950 | pm_runtime_enable(host->dev); |
1951 | pm_runtime_get_sync(host->dev); | |
1952 | pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); | |
1953 | pm_runtime_use_autosuspend(host->dev); | |
a45c6cb8 | 1954 | |
2bec0893 AH |
1955 | if (cpu_is_omap2430()) { |
1956 | host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); | |
1957 | /* | |
1958 | * MMC can still work without debounce clock. | |
1959 | */ | |
1960 | if (IS_ERR(host->dbclk)) | |
1961 | dev_warn(mmc_dev(host->mmc), | |
1962 | "Failed to get debounce clock\n"); | |
a45c6cb8 | 1963 | else |
2bec0893 AH |
1964 | host->got_dbclk = 1; |
1965 | ||
1966 | if (host->got_dbclk) | |
1967 | if (clk_enable(host->dbclk) != 0) | |
1968 | dev_dbg(mmc_dev(host->mmc), "Enabling debounce" | |
1969 | " clk failed\n"); | |
1970 | } | |
a45c6cb8 | 1971 | |
0ccd76d4 JY |
1972 | /* Since we do only SG emulation, we can have as many segs |
1973 | * as we want. */ | |
a36274e0 | 1974 | mmc->max_segs = 1024; |
0ccd76d4 | 1975 | |
a45c6cb8 MC |
1976 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
1977 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ | |
1978 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1979 | mmc->max_seg_size = mmc->max_req_size; | |
1980 | ||
13189e78 | 1981 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
93caf8e6 | 1982 | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; |
a45c6cb8 | 1983 | |
3a63833e SG |
1984 | mmc->caps |= mmc_slot(host).caps; |
1985 | if (mmc->caps & MMC_CAP_8_BIT_DATA) | |
a45c6cb8 MC |
1986 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
1987 | ||
191d1f1d | 1988 | if (mmc_slot(host).nonremovable) |
23d99bb9 AH |
1989 | mmc->caps |= MMC_CAP_NONREMOVABLE; |
1990 | ||
70a3341a | 1991 | omap_hsmmc_conf_bus_power(host); |
a45c6cb8 | 1992 | |
f3e2f1dd GI |
1993 | /* Select DMA lines */ |
1994 | switch (host->id) { | |
1995 | case OMAP_MMC1_DEVID: | |
1996 | host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; | |
1997 | host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; | |
1998 | break; | |
1999 | case OMAP_MMC2_DEVID: | |
2000 | host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; | |
2001 | host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; | |
2002 | break; | |
2003 | case OMAP_MMC3_DEVID: | |
2004 | host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; | |
2005 | host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; | |
2006 | break; | |
82cf818d | 2007 | case OMAP_MMC4_DEVID: |
2008 | host->dma_line_tx = OMAP44XX_DMA_MMC4_TX; | |
2009 | host->dma_line_rx = OMAP44XX_DMA_MMC4_RX; | |
2010 | break; | |
2011 | case OMAP_MMC5_DEVID: | |
2012 | host->dma_line_tx = OMAP44XX_DMA_MMC5_TX; | |
2013 | host->dma_line_rx = OMAP44XX_DMA_MMC5_RX; | |
2014 | break; | |
f3e2f1dd GI |
2015 | default: |
2016 | dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); | |
2017 | goto err_irq; | |
2018 | } | |
a45c6cb8 MC |
2019 | |
2020 | /* Request IRQ for MMC operations */ | |
d9618e9f | 2021 | ret = request_irq(host->irq, omap_hsmmc_irq, 0, |
a45c6cb8 MC |
2022 | mmc_hostname(mmc), host); |
2023 | if (ret) { | |
2024 | dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); | |
2025 | goto err_irq; | |
2026 | } | |
2027 | ||
2028 | if (pdata->init != NULL) { | |
2029 | if (pdata->init(&pdev->dev) != 0) { | |
70a3341a DK |
2030 | dev_dbg(mmc_dev(host->mmc), |
2031 | "Unable to configure MMC IRQs\n"); | |
a45c6cb8 MC |
2032 | goto err_irq_cd_init; |
2033 | } | |
2034 | } | |
db0fefc5 | 2035 | |
b702b106 | 2036 | if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { |
db0fefc5 AH |
2037 | ret = omap_hsmmc_reg_get(host); |
2038 | if (ret) | |
2039 | goto err_reg; | |
2040 | host->use_reg = 1; | |
2041 | } | |
2042 | ||
b583f26d | 2043 | mmc->ocr_avail = mmc_slot(host).ocr_mask; |
a45c6cb8 MC |
2044 | |
2045 | /* Request IRQ for card detect */ | |
e1a55f5e | 2046 | if ((mmc_slot(host).card_detect_irq)) { |
a45c6cb8 | 2047 | ret = request_irq(mmc_slot(host).card_detect_irq, |
70a3341a | 2048 | omap_hsmmc_cd_handler, |
d9618e9f | 2049 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
a45c6cb8 MC |
2050 | mmc_hostname(mmc), host); |
2051 | if (ret) { | |
2052 | dev_dbg(mmc_dev(host->mmc), | |
2053 | "Unable to grab MMC CD IRQ\n"); | |
2054 | goto err_irq_cd; | |
2055 | } | |
72f2e2c7 | 2056 | pdata->suspend = omap_hsmmc_suspend_cdirq; |
2057 | pdata->resume = omap_hsmmc_resume_cdirq; | |
a45c6cb8 MC |
2058 | } |
2059 | ||
b417577d | 2060 | omap_hsmmc_disable_irq(host); |
a45c6cb8 | 2061 | |
b62f6228 AH |
2062 | omap_hsmmc_protect_card(host); |
2063 | ||
a45c6cb8 MC |
2064 | mmc_add_host(mmc); |
2065 | ||
191d1f1d | 2066 | if (mmc_slot(host).name != NULL) { |
a45c6cb8 MC |
2067 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); |
2068 | if (ret < 0) | |
2069 | goto err_slot_name; | |
2070 | } | |
191d1f1d | 2071 | if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { |
a45c6cb8 MC |
2072 | ret = device_create_file(&mmc->class_dev, |
2073 | &dev_attr_cover_switch); | |
2074 | if (ret < 0) | |
db0fefc5 | 2075 | goto err_slot_name; |
a45c6cb8 MC |
2076 | } |
2077 | ||
70a3341a | 2078 | omap_hsmmc_debugfs(mmc); |
fa4aa2d4 B |
2079 | pm_runtime_mark_last_busy(host->dev); |
2080 | pm_runtime_put_autosuspend(host->dev); | |
d900f712 | 2081 | |
a45c6cb8 MC |
2082 | return 0; |
2083 | ||
a45c6cb8 MC |
2084 | err_slot_name: |
2085 | mmc_remove_host(mmc); | |
a45c6cb8 | 2086 | free_irq(mmc_slot(host).card_detect_irq, host); |
db0fefc5 AH |
2087 | err_irq_cd: |
2088 | if (host->use_reg) | |
2089 | omap_hsmmc_reg_put(host); | |
2090 | err_reg: | |
2091 | if (host->pdata->cleanup) | |
2092 | host->pdata->cleanup(&pdev->dev); | |
a45c6cb8 MC |
2093 | err_irq_cd_init: |
2094 | free_irq(host->irq, host); | |
2095 | err_irq: | |
fa4aa2d4 B |
2096 | pm_runtime_mark_last_busy(host->dev); |
2097 | pm_runtime_put_autosuspend(host->dev); | |
a45c6cb8 | 2098 | clk_put(host->fclk); |
2bec0893 | 2099 | if (host->got_dbclk) { |
a45c6cb8 MC |
2100 | clk_disable(host->dbclk); |
2101 | clk_put(host->dbclk); | |
2102 | } | |
a45c6cb8 MC |
2103 | err1: |
2104 | iounmap(host->base); | |
db0fefc5 AH |
2105 | platform_set_drvdata(pdev, NULL); |
2106 | mmc_free_host(mmc); | |
2107 | err_alloc: | |
2108 | omap_hsmmc_gpio_free(pdata); | |
a45c6cb8 | 2109 | err: |
984b203a | 2110 | release_mem_region(res->start, resource_size(res)); |
a45c6cb8 MC |
2111 | return ret; |
2112 | } | |
2113 | ||
70a3341a | 2114 | static int omap_hsmmc_remove(struct platform_device *pdev) |
a45c6cb8 | 2115 | { |
70a3341a | 2116 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
2117 | struct resource *res; |
2118 | ||
2119 | if (host) { | |
fa4aa2d4 | 2120 | pm_runtime_get_sync(host->dev); |
a45c6cb8 | 2121 | mmc_remove_host(host->mmc); |
db0fefc5 AH |
2122 | if (host->use_reg) |
2123 | omap_hsmmc_reg_put(host); | |
a45c6cb8 MC |
2124 | if (host->pdata->cleanup) |
2125 | host->pdata->cleanup(&pdev->dev); | |
2126 | free_irq(host->irq, host); | |
2127 | if (mmc_slot(host).card_detect_irq) | |
2128 | free_irq(mmc_slot(host).card_detect_irq, host); | |
0d9ee5b2 | 2129 | flush_work_sync(&host->mmc_carddetect_work); |
a45c6cb8 | 2130 | |
fa4aa2d4 B |
2131 | pm_runtime_put_sync(host->dev); |
2132 | pm_runtime_disable(host->dev); | |
a45c6cb8 | 2133 | clk_put(host->fclk); |
2bec0893 | 2134 | if (host->got_dbclk) { |
a45c6cb8 MC |
2135 | clk_disable(host->dbclk); |
2136 | clk_put(host->dbclk); | |
2137 | } | |
2138 | ||
2139 | mmc_free_host(host->mmc); | |
2140 | iounmap(host->base); | |
db0fefc5 | 2141 | omap_hsmmc_gpio_free(pdev->dev.platform_data); |
a45c6cb8 MC |
2142 | } |
2143 | ||
2144 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2145 | if (res) | |
984b203a | 2146 | release_mem_region(res->start, resource_size(res)); |
a45c6cb8 MC |
2147 | platform_set_drvdata(pdev, NULL); |
2148 | ||
2149 | return 0; | |
2150 | } | |
2151 | ||
2152 | #ifdef CONFIG_PM | |
a791daa1 | 2153 | static int omap_hsmmc_suspend(struct device *dev) |
a45c6cb8 MC |
2154 | { |
2155 | int ret = 0; | |
a791daa1 | 2156 | struct platform_device *pdev = to_platform_device(dev); |
70a3341a | 2157 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
2158 | |
2159 | if (host && host->suspended) | |
2160 | return 0; | |
2161 | ||
2162 | if (host) { | |
fa4aa2d4 | 2163 | pm_runtime_get_sync(host->dev); |
a6b2240d AH |
2164 | host->suspended = 1; |
2165 | if (host->pdata->suspend) { | |
2166 | ret = host->pdata->suspend(&pdev->dev, | |
2167 | host->slot_id); | |
2168 | if (ret) { | |
2169 | dev_dbg(mmc_dev(host->mmc), | |
2170 | "Unable to handle MMC board" | |
2171 | " level suspend\n"); | |
2172 | host->suspended = 0; | |
2173 | return ret; | |
2174 | } | |
2175 | } | |
2176 | cancel_work_sync(&host->mmc_carddetect_work); | |
1a13f8fa | 2177 | ret = mmc_suspend_host(host->mmc); |
fa4aa2d4 | 2178 | |
a45c6cb8 | 2179 | if (ret == 0) { |
b417577d | 2180 | omap_hsmmc_disable_irq(host); |
0683af48 | 2181 | OMAP_HSMMC_WRITE(host->base, HCTL, |
191d1f1d | 2182 | OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); |
2bec0893 AH |
2183 | if (host->got_dbclk) |
2184 | clk_disable(host->dbclk); | |
a6b2240d AH |
2185 | } else { |
2186 | host->suspended = 0; | |
2187 | if (host->pdata->resume) { | |
2188 | ret = host->pdata->resume(&pdev->dev, | |
2189 | host->slot_id); | |
2190 | if (ret) | |
2191 | dev_dbg(mmc_dev(host->mmc), | |
2192 | "Unmask interrupt failed\n"); | |
2193 | } | |
a6b2240d | 2194 | } |
fa4aa2d4 | 2195 | pm_runtime_put_sync(host->dev); |
a45c6cb8 MC |
2196 | } |
2197 | return ret; | |
2198 | } | |
2199 | ||
2200 | /* Routine to resume the MMC device */ | |
a791daa1 | 2201 | static int omap_hsmmc_resume(struct device *dev) |
a45c6cb8 MC |
2202 | { |
2203 | int ret = 0; | |
a791daa1 | 2204 | struct platform_device *pdev = to_platform_device(dev); |
70a3341a | 2205 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
2206 | |
2207 | if (host && !host->suspended) | |
2208 | return 0; | |
2209 | ||
2210 | if (host) { | |
fa4aa2d4 | 2211 | pm_runtime_get_sync(host->dev); |
11dd62a7 | 2212 | |
2bec0893 AH |
2213 | if (host->got_dbclk) |
2214 | clk_enable(host->dbclk); | |
2215 | ||
70a3341a | 2216 | omap_hsmmc_conf_bus_power(host); |
1b331e69 | 2217 | |
a45c6cb8 MC |
2218 | if (host->pdata->resume) { |
2219 | ret = host->pdata->resume(&pdev->dev, host->slot_id); | |
2220 | if (ret) | |
2221 | dev_dbg(mmc_dev(host->mmc), | |
2222 | "Unmask interrupt failed\n"); | |
2223 | } | |
2224 | ||
b62f6228 AH |
2225 | omap_hsmmc_protect_card(host); |
2226 | ||
a45c6cb8 MC |
2227 | /* Notify the core to resume the host */ |
2228 | ret = mmc_resume_host(host->mmc); | |
2229 | if (ret == 0) | |
2230 | host->suspended = 0; | |
fa4aa2d4 B |
2231 | |
2232 | pm_runtime_mark_last_busy(host->dev); | |
2233 | pm_runtime_put_autosuspend(host->dev); | |
a45c6cb8 MC |
2234 | } |
2235 | ||
2236 | return ret; | |
2237 | ||
a45c6cb8 MC |
2238 | } |
2239 | ||
2240 | #else | |
70a3341a DK |
2241 | #define omap_hsmmc_suspend NULL |
2242 | #define omap_hsmmc_resume NULL | |
a45c6cb8 MC |
2243 | #endif |
2244 | ||
fa4aa2d4 B |
2245 | static int omap_hsmmc_runtime_suspend(struct device *dev) |
2246 | { | |
2247 | struct omap_hsmmc_host *host; | |
2248 | ||
2249 | host = platform_get_drvdata(to_platform_device(dev)); | |
2250 | omap_hsmmc_context_save(host); | |
2251 | dev_dbg(mmc_dev(host->mmc), "disabled\n"); | |
2252 | ||
2253 | return 0; | |
2254 | } | |
2255 | ||
2256 | static int omap_hsmmc_runtime_resume(struct device *dev) | |
2257 | { | |
2258 | struct omap_hsmmc_host *host; | |
2259 | ||
2260 | host = platform_get_drvdata(to_platform_device(dev)); | |
2261 | omap_hsmmc_context_restore(host); | |
2262 | dev_dbg(mmc_dev(host->mmc), "enabled\n"); | |
2263 | ||
2264 | return 0; | |
2265 | } | |
2266 | ||
a791daa1 | 2267 | static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { |
70a3341a DK |
2268 | .suspend = omap_hsmmc_suspend, |
2269 | .resume = omap_hsmmc_resume, | |
fa4aa2d4 B |
2270 | .runtime_suspend = omap_hsmmc_runtime_suspend, |
2271 | .runtime_resume = omap_hsmmc_runtime_resume, | |
a791daa1 KH |
2272 | }; |
2273 | ||
2274 | static struct platform_driver omap_hsmmc_driver = { | |
2275 | .remove = omap_hsmmc_remove, | |
a45c6cb8 MC |
2276 | .driver = { |
2277 | .name = DRIVER_NAME, | |
2278 | .owner = THIS_MODULE, | |
a791daa1 | 2279 | .pm = &omap_hsmmc_dev_pm_ops, |
a45c6cb8 MC |
2280 | }, |
2281 | }; | |
2282 | ||
70a3341a | 2283 | static int __init omap_hsmmc_init(void) |
a45c6cb8 MC |
2284 | { |
2285 | /* Register the MMC driver */ | |
8753298a | 2286 | return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe); |
a45c6cb8 MC |
2287 | } |
2288 | ||
70a3341a | 2289 | static void __exit omap_hsmmc_cleanup(void) |
a45c6cb8 MC |
2290 | { |
2291 | /* Unregister MMC driver */ | |
70a3341a | 2292 | platform_driver_unregister(&omap_hsmmc_driver); |
a45c6cb8 MC |
2293 | } |
2294 | ||
70a3341a DK |
2295 | module_init(omap_hsmmc_init); |
2296 | module_exit(omap_hsmmc_cleanup); | |
a45c6cb8 MC |
2297 | |
2298 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); | |
2299 | MODULE_LICENSE("GPL"); | |
2300 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2301 | MODULE_AUTHOR("Texas Instruments Inc"); |