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[mirror_ubuntu-zesty-kernel.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712 21#include <linux/debugfs.h>
c5c98927 22#include <linux/dmaengine.h>
d900f712 23#include <linux/seq_file.h>
031cd037 24#include <linux/sizes.h>
a45c6cb8
MC		 25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
a45c6cb8
MC		 29#include <linux/timer.h>
30#include <linux/clk.h>
46856a68 31#include <linux/of.h>
2cd3a2a5 32#include <linux/of_irq.h>
46856a68
RN		 33#include <linux/of_gpio.h>
34#include <linux/of_device.h>
a45c6cb8 35#include <linux/mmc/host.h>
13189e78 36#include <linux/mmc/core.h>
93caf8e6 37#include <linux/mmc/mmc.h>
41afa314 38#include <linux/mmc/slot-gpio.h>
a45c6cb8 39#include <linux/io.h>
2cd3a2a5 40#include <linux/irq.h>
db0fefc5
AH		 41#include <linux/gpio.h>
42#include <linux/regulator/consumer.h>
46b76035 43#include <linux/pinctrl/consumer.h>
fa4aa2d4 44#include <linux/pm_runtime.h>
5b83b223 45#include <linux/pm_wakeirq.h>
55143438 46#include <linux/platform_data/hsmmc-omap.h>
a45c6cb8
MC		 47
48/* OMAP HSMMC Host Controller Registers */
11dd62a7 49#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8 50#define OMAP_HSMMC_CON 0x002C
a2e77152 51#define OMAP_HSMMC_SDMASA 0x0100
a45c6cb8
MC		 52#define OMAP_HSMMC_BLK 0x0104
53#define OMAP_HSMMC_ARG 0x0108
54#define OMAP_HSMMC_CMD 0x010C
55#define OMAP_HSMMC_RSP10 0x0110
56#define OMAP_HSMMC_RSP32 0x0114
57#define OMAP_HSMMC_RSP54 0x0118
58#define OMAP_HSMMC_RSP76 0x011C
59#define OMAP_HSMMC_DATA 0x0120
bb0635f0 60#define OMAP_HSMMC_PSTATE 0x0124
a45c6cb8
MC		 61#define OMAP_HSMMC_HCTL 0x0128
62#define OMAP_HSMMC_SYSCTL 0x012C
63#define OMAP_HSMMC_STAT 0x0130
64#define OMAP_HSMMC_IE 0x0134
65#define OMAP_HSMMC_ISE 0x0138
a2e77152 66#define OMAP_HSMMC_AC12 0x013C
a45c6cb8
MC		 67#define OMAP_HSMMC_CAPA 0x0140
68
69#define VS18 (1 << 26)
70#define VS30 (1 << 25)
cd587096 71#define HSS (1 << 21)
a45c6cb8
MC		 72#define SDVS18 (0x5 << 9)
73#define SDVS30 (0x6 << 9)
eb250826 74#define SDVS33 (0x7 << 9)
1b331e69 75#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 76#define SDVSCLR 0xFFFFF1FF
77#define SDVSDET 0x00000400
78#define AUTOIDLE 0x1
79#define SDBP (1 << 8)
80#define DTO 0xe
81#define ICE 0x1
82#define ICS 0x2
83#define CEN (1 << 2)
ed164182 84#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
a45c6cb8
MC		 85#define CLKD_MASK 0x0000FFC0
86#define CLKD_SHIFT 6
87#define DTO_MASK 0x000F0000
88#define DTO_SHIFT 16
a45c6cb8 89#define INIT_STREAM (1 << 1)
a2e77152 90#define ACEN_ACMD23 (2 << 2)
a45c6cb8
MC		 91#define DP_SELECT (1 << 21)
92#define DDIR (1 << 4)
a7e96879 93#define DMAE 0x1
a45c6cb8
MC		 94#define MSBS (1 << 5)
95#define BCE (1 << 1)
96#define FOUR_BIT (1 << 1)
cd587096 97#define HSPE (1 << 2)
5a52b08b 98#define IWE (1 << 24)
03b5d924 99#define DDR (1 << 19)
5a52b08b
B		 100#define CLKEXTFREE (1 << 16)
101#define CTPL (1 << 11)
73153010 102#define DW8 (1 << 5)
a45c6cb8 103#define OD 0x1
a45c6cb8
MC		 104#define STAT_CLEAR 0xFFFFFFFF
105#define INIT_STREAM_CMD 0x00000000
106#define DUAL_VOLT_OCR_BIT 7
107#define SRC (1 << 25)
108#define SRD (1 << 26)
11dd62a7 109#define SOFTRESET (1 << 1)
a45c6cb8 110
f945901f
AF		 111/* PSTATE */
112#define DLEV_DAT(x) (1 << (20 + (x)))
113
a7e96879
V		 114/* Interrupt masks for IE and ISE register */
115#define CC_EN (1 << 0)
116#define TC_EN (1 << 1)
117#define BWR_EN (1 << 4)
118#define BRR_EN (1 << 5)
2cd3a2a5 119#define CIRQ_EN (1 << 8)
a7e96879
V		 120#define ERR_EN (1 << 15)
121#define CTO_EN (1 << 16)
122#define CCRC_EN (1 << 17)
123#define CEB_EN (1 << 18)
124#define CIE_EN (1 << 19)
125#define DTO_EN (1 << 20)
126#define DCRC_EN (1 << 21)
127#define DEB_EN (1 << 22)
a2e77152 128#define ACE_EN (1 << 24)
a7e96879
V		 129#define CERR_EN (1 << 28)
130#define BADA_EN (1 << 29)
131
a2e77152 132#define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
a7e96879
V		 133 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
134 BRR_EN | BWR_EN | TC_EN | CC_EN)
135
a2e77152
B		 136#define CNI (1 << 7)
137#define ACIE (1 << 4)
138#define ACEB (1 << 3)
139#define ACCE (1 << 2)
140#define ACTO (1 << 1)
141#define ACNE (1 << 0)
142
fa4aa2d4 143#define MMC_AUTOSUSPEND_DELAY 100
1e881786
JM		 144#define MMC_TIMEOUT_MS 20 /* 20 mSec */
145#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
6b206efe
AS		 146#define OMAP_MMC_MIN_CLOCK 400000
147#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 148#define DRIVER_NAME "omap_hsmmc"
a45c6cb8 149
e99448ff
B		 150#define VDD_1V8 1800000 /* 180000 uV */
151#define VDD_3V0 3000000 /* 300000 uV */
152#define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
153
a45c6cb8
MC		 154/*
155 * One controller can have multiple slots, like on some omap boards using
156 * omap.c controller driver. Luckily this is not currently done on any known
157 * omap_hsmmc.c device.
158 */
326119c9 159#define mmc_pdata(host) host->pdata
a45c6cb8
MC		 160
161/*
162 * MMC Host controller read/write API's
163 */
164#define OMAP_HSMMC_READ(base, reg) \
165 __raw_readl((base) + OMAP_HSMMC_##reg)
166
167#define OMAP_HSMMC_WRITE(base, reg, val) \
168 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
169
9782aff8
PF		 170struct omap_hsmmc_next {
171 unsigned int dma_len;
172 s32 cookie;
173};
174
70a3341a 175struct omap_hsmmc_host {
a45c6cb8
MC		 176 struct device *dev;
177 struct mmc_host *mmc;
178 struct mmc_request *mrq;
179 struct mmc_command *cmd;
180 struct mmc_data *data;
181 struct clk *fclk;
a45c6cb8 182 struct clk *dbclk;
e99448ff 183 struct regulator *pbias;
bb2726b5 184 bool pbias_enabled;
a45c6cb8 185 void __iomem *base;
3f77f702 186 int vqmmc_enabled;
a45c6cb8 187 resource_size_t mapbase;
4dffd7a2 188 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 189 unsigned int dma_len;
0ccd76d4 190 unsigned int dma_sg_idx;
a45c6cb8 191 unsigned char bus_mode;
a3621465 192 unsigned char power_mode;
a45c6cb8 193 int suspended;
0a82e06e
TL		 194 u32 con;
195 u32 hctl;
196 u32 sysctl;
197 u32 capa;
a45c6cb8 198 int irq;
2cd3a2a5 199 int wake_irq;
a45c6cb8 200 int use_dma, dma_ch;
c5c98927
RK		 201 struct dma_chan *tx_chan;
202 struct dma_chan *rx_chan;
4a694dc9 203 int response_busy;
11dd62a7 204 int context_loss;
b62f6228
AH		 205 int protect_card;
206 int reqs_blocked;
b417577d 207 int req_in_progress;
6e3076c2 208 unsigned long clk_rate;
a2e77152 209 unsigned int flags;
2cd3a2a5
AF		 210#define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
211#define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
9782aff8 212 struct omap_hsmmc_next next_data;
55143438 213 struct omap_hsmmc_platform_data *pdata;
b5cd43f0 214
b5cd43f0
AF		 215 /* return MMC cover switch state, can be NULL if not supported.
216 *
217 * possible return values:
218 * 0 - closed
219 * 1 - open
220 */
80412ca8 221 int (*get_cover_state)(struct device *dev);
b5cd43f0 222
80412ca8 223 int (*card_detect)(struct device *dev);
a45c6cb8
MC		 224};
225
59445b10
NM		 226struct omap_mmc_of_data {
227 u32 reg_offset;
228 u8 controller_flags;
229};
230
bf129e1c
B		 231static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
232
80412ca8 233static int omap_hsmmc_card_detect(struct device *dev)
db0fefc5 234{
9ea28ecb 235 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
db0fefc5 236
41afa314 237 return mmc_gpio_get_cd(host->mmc);
db0fefc5
AH		 238}
239
80412ca8 240static int omap_hsmmc_get_cover_state(struct device *dev)
db0fefc5 241{
9ea28ecb 242 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
db0fefc5 243
41afa314 244 return mmc_gpio_get_cd(host->mmc);
db0fefc5
AH		 245}
246
1d17f30b 247static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
2a17f844
KVA		 248{
249 int ret;
3f77f702 250 struct omap_hsmmc_host *host = mmc_priv(mmc);
1d17f30b 251 struct mmc_ios *ios = &mmc->ios;
2a17f844
KVA		 252
253 if (mmc->supply.vmmc) {
1d17f30b 254 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
2a17f844
KVA		 255 if (ret)
256 return ret;
257 }
258
259 /* Enable interface voltage rail, if needed */
3f77f702 260 if (mmc->supply.vqmmc && !host->vqmmc_enabled) {
2a17f844
KVA		 261 ret = regulator_enable(mmc->supply.vqmmc);
262 if (ret) {
263 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
264 goto err_vqmmc;
265 }
3f77f702 266 host->vqmmc_enabled = 1;
2a17f844
KVA		 267 }
268
269 return 0;
270
271err_vqmmc:
272 if (mmc->supply.vmmc)
273 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
274
275 return ret;
276}
277
278static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
279{
280 int ret;
281 int status;
3f77f702 282 struct omap_hsmmc_host *host = mmc_priv(mmc);
2a17f844 283
3f77f702 284 if (mmc->supply.vqmmc && host->vqmmc_enabled) {
2a17f844
KVA		 285 ret = regulator_disable(mmc->supply.vqmmc);
286 if (ret) {
287 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
288 return ret;
289 }
3f77f702 290 host->vqmmc_enabled = 0;
2a17f844
KVA		 291 }
292
293 if (mmc->supply.vmmc) {
294 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
295 if (ret)
296 goto err_set_ocr;
297 }
298
299 return 0;
300
301err_set_ocr:
302 if (mmc->supply.vqmmc) {
303 status = regulator_enable(mmc->supply.vqmmc);
304 if (status)
305 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
306 }
307
308 return ret;
309}
310
ec85c95e
KVA		 311static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on,
312 int vdd)
313{
314 int ret;
315
316 if (!host->pbias)
317 return 0;
318
319 if (power_on) {
320 if (vdd <= VDD_165_195)
321 ret = regulator_set_voltage(host->pbias, VDD_1V8,
322 VDD_1V8);
323 else
324 ret = regulator_set_voltage(host->pbias, VDD_3V0,
325 VDD_3V0);
326 if (ret < 0) {
327 dev_err(host->dev, "pbias set voltage fail\n");
328 return ret;
329 }
330
bb2726b5 331 if (host->pbias_enabled == 0) {
ec85c95e
KVA		 332 ret = regulator_enable(host->pbias);
333 if (ret) {
334 dev_err(host->dev, "pbias reg enable fail\n");
335 return ret;
336 }
bb2726b5 337 host->pbias_enabled = 1;
ec85c95e
KVA		 338 }
339 } else {
bb2726b5 340 if (host->pbias_enabled == 1) {
ec85c95e
KVA		 341 ret = regulator_disable(host->pbias);
342 if (ret) {
343 dev_err(host->dev, "pbias reg disable fail\n");
344 return ret;
345 }
bb2726b5 346 host->pbias_enabled = 0;
ec85c95e
KVA		 347 }
348 }
349
350 return 0;
351}
352
1ca4d359
AF		 353static int omap_hsmmc_set_power(struct omap_hsmmc_host *host, int power_on,
354 int vdd)
db0fefc5 355{
aa9a6801 356 struct mmc_host *mmc = host->mmc;
db0fefc5
AH		 357 int ret = 0;
358
f7f0f035 359 if (mmc_pdata(host)->set_power)
1ca4d359 360 return mmc_pdata(host)->set_power(host->dev, power_on, vdd);
f7f0f035 361
db0fefc5
AH		 362 /*
363 * If we don't see a Vcc regulator, assume it's a fixed
364 * voltage always-on regulator.
365 */
aa9a6801 366 if (!mmc->supply.vmmc)
db0fefc5
AH		 367 return 0;
368
326119c9 369 if (mmc_pdata(host)->before_set_reg)
1ca4d359 370 mmc_pdata(host)->before_set_reg(host->dev, power_on, vdd);
db0fefc5 371
ec85c95e
KVA		 372 ret = omap_hsmmc_set_pbias(host, false, 0);
373 if (ret)
374 return ret;
e99448ff 375
db0fefc5
AH		 376 /*
377 * Assume Vcc regulator is used only to power the card ... OMAP
378 * VDDS is used to power the pins, optionally with a transceiver to
379 * support cards using voltages other than VDDS (1.8V nominal). When a
380 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
381 *
382 * In some cases this regulator won't support enable/disable;
383 * e.g. it's a fixed rail for a WLAN chip.
384 *
385 * In other cases vcc_aux switches interface power. Example, for
386 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
387 * chips/cards need an interface voltage rail too.
388 */
389 if (power_on) {
1d17f30b 390 ret = omap_hsmmc_enable_supply(mmc);
2a17f844
KVA		 391 if (ret)
392 return ret;
97fe7e5a
KVA		 393
394 ret = omap_hsmmc_set_pbias(host, true, vdd);
395 if (ret)
396 goto err_set_voltage;
db0fefc5 397 } else {
2a17f844
KVA		 398 ret = omap_hsmmc_disable_supply(mmc);
399 if (ret)
400 return ret;
db0fefc5
AH		 401 }
402
326119c9 403 if (mmc_pdata(host)->after_set_reg)
1ca4d359 404 mmc_pdata(host)->after_set_reg(host->dev, power_on, vdd);
db0fefc5 405
229f3292
KVA		 406 return 0;
407
408err_set_voltage:
2a17f844 409 omap_hsmmc_disable_supply(mmc);
229f3292 410
db0fefc5
AH		 411 return ret;
412}
413
c8518efa
KVA		 414static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
415{
416 int ret;
417
418 if (!reg)
419 return 0;
420
421 if (regulator_is_enabled(reg)) {
422 ret = regulator_enable(reg);
423 if (ret)
424 return ret;
425
426 ret = regulator_disable(reg);
427 if (ret)
428 return ret;
429 }
430
431 return 0;
432}
433
434static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
435{
436 struct mmc_host *mmc = host->mmc;
437 int ret;
438
439 /*
440 * disable regulators enabled during boot and get the usecount
441 * right so that regulators can be enabled/disabled by checking
442 * the return value of regulator_is_enabled
443 */
444 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
445 if (ret) {
446 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
447 return ret;
448 }
449
450 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
451 if (ret) {
452 dev_err(host->dev,
453 "fail to disable boot enabled vmmc_aux reg\n");
454 return ret;
455 }
456
457 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
458 if (ret) {
459 dev_err(host->dev,
460 "failed to disable boot enabled pbias reg\n");
461 return ret;
462 }
463
464 return 0;
465}
466
db0fefc5
AH		 467static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
468{
64be9782 469 int ocr_value = 0;
7d607f91 470 int ret;
aa9a6801 471 struct mmc_host *mmc = host->mmc;
db0fefc5 472
f7f0f035
AF		 473 if (mmc_pdata(host)->set_power)
474 return 0;
475
aa9a6801
KVA		 476 mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc");
477 if (IS_ERR(mmc->supply.vmmc)) {
478 ret = PTR_ERR(mmc->supply.vmmc);
123e20b1 479 if ((ret != -ENODEV) && host->dev->of_node)
7d607f91 480 return ret;
7d607f91 481 dev_dbg(host->dev, "unable to get vmmc regulator %ld\n",
aa9a6801
KVA		 482 PTR_ERR(mmc->supply.vmmc));
483 mmc->supply.vmmc = NULL;
db0fefc5 484 } else {
aa9a6801 485 ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc);
b49069fc 486 if (ocr_value > 0)
326119c9 487 mmc_pdata(host)->ocr_mask = ocr_value;
987fd49b 488 }
db0fefc5 489
987fd49b 490 /* Allow an aux regulator */
aa9a6801
KVA		 491 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux");
492 if (IS_ERR(mmc->supply.vqmmc)) {
493 ret = PTR_ERR(mmc->supply.vqmmc);
123e20b1 494 if ((ret != -ENODEV) && host->dev->of_node)
6a9b2ff0 495 return ret;
6a9b2ff0 496 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
aa9a6801
KVA		 497 PTR_ERR(mmc->supply.vqmmc));
498 mmc->supply.vqmmc = NULL;
6a9b2ff0 499 }
987fd49b 500
c299dc39
KVA		 501 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
502 if (IS_ERR(host->pbias)) {
503 ret = PTR_ERR(host->pbias);
9143757b
KVA		 504 if ((ret != -ENODEV) && host->dev->of_node) {
505 dev_err(host->dev,
506 "SD card detect fail? enable CONFIG_REGULATOR_PBIAS\n");
6a9b2ff0 507 return ret;
9143757b 508 }
6a9b2ff0 509 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
c299dc39
KVA		 510 PTR_ERR(host->pbias));
511 host->pbias = NULL;
6a9b2ff0 512 }
e99448ff 513
987fd49b 514 /* For eMMC do not power off when not in sleep state */
326119c9 515 if (mmc_pdata(host)->no_regulator_off_init)
987fd49b 516 return 0;
987fd49b 517
c8518efa
KVA		 518 ret = omap_hsmmc_disable_boot_regulators(host);
519 if (ret)
520 return ret;
db0fefc5
AH		 521
522 return 0;
db0fefc5
AH		 523}
524
cde592cb 525static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
41afa314
N		 526
527static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
528 struct omap_hsmmc_host *host,
1e363e3b 529 struct omap_hsmmc_platform_data *pdata)
b702b106
AH		 530{
531 int ret;
532
b7a5646f
AF		 533 if (gpio_is_valid(pdata->gpio_cod)) {
534 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
b702b106
AH		 535 if (ret)
536 return ret;
cde592cb
AF		 537
538 host->get_cover_state = omap_hsmmc_get_cover_state;
539 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
b7a5646f
AF		 540 } else if (gpio_is_valid(pdata->gpio_cd)) {
541 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
cde592cb
AF		 542 if (ret)
543 return ret;
544
545 host->card_detect = omap_hsmmc_card_detect;
326119c9 546 }
b702b106 547
326119c9 548 if (gpio_is_valid(pdata->gpio_wp)) {
41afa314 549 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
b702b106 550 if (ret)
41afa314 551 return ret;
326119c9 552 }
b702b106
AH		 553
554 return 0;
b702b106
AH		 555}
556
e0c7f99b
AS		 557/*
558 * Start clock to the card
559 */
560static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
561{
562 OMAP_HSMMC_WRITE(host->base, SYSCTL,
563 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
564}
565
a45c6cb8
MC		 566/*
567 * Stop clock to the card
568 */
70a3341a 569static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 570{
571 OMAP_HSMMC_WRITE(host->base, SYSCTL,
572 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
573 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
7122bbb0 574 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
a45c6cb8
MC		 575}
576
93caf8e6
AH		 577static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
578 struct mmc_command *cmd)
b417577d 579{
2cd3a2a5
AF		 580 u32 irq_mask = INT_EN_MASK;
581 unsigned long flags;
b417577d
AH		 582
583 if (host->use_dma)
2cd3a2a5 584 irq_mask &= ~(BRR_EN | BWR_EN);
b417577d 585
93caf8e6
AH		 586 /* Disable timeout for erases */
587 if (cmd->opcode == MMC_ERASE)
a7e96879 588 irq_mask &= ~DTO_EN;
93caf8e6 589
2cd3a2a5 590 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 591 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
592 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
2cd3a2a5
AF		 593
594 /* latch pending CIRQ, but don't signal MMC core */
595 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
596 irq_mask |= CIRQ_EN;
b417577d 597 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
2cd3a2a5 598 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 599}
600
601static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
602{
2cd3a2a5
AF		 603 u32 irq_mask = 0;
604 unsigned long flags;
605
606 spin_lock_irqsave(&host->irq_lock, flags);
607 /* no transfer running but need to keep cirq if enabled */
608 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
609 irq_mask |= CIRQ_EN;
610 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
611 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
b417577d 612 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2cd3a2a5 613 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 614}
615
ac330f44 616/* Calculate divisor for the given clock frequency */
d83b6e03 617static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 618{
619 u16 dsor = 0;
620
621 if (ios->clock) {
d83b6e03 622 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ed164182
B		 623 if (dsor > CLKD_MAX)
624 dsor = CLKD_MAX;
ac330f44
AS		 625 }
626
627 return dsor;
628}
629
5934df2f
AS		 630static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
631{
632 struct mmc_ios *ios = &host->mmc->ios;
633 unsigned long regval;
634 unsigned long timeout;
cd587096 635 unsigned long clkdiv;
5934df2f 636
8986d31b 637 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
5934df2f
AS		 638
639 omap_hsmmc_stop_clock(host);
640
641 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
642 regval = regval & ~(CLKD_MASK | DTO_MASK);
cd587096
HG		 643 clkdiv = calc_divisor(host, ios);
644 regval = regval | (clkdiv << 6) | (DTO << 16);
5934df2f
AS		 645 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
646 OMAP_HSMMC_WRITE(host->base, SYSCTL,
647 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
648
649 /* Wait till the ICS bit is set */
650 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
651 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
652 && time_before(jiffies, timeout))
653 cpu_relax();
654
cd587096
HG		 655 /*
656 * Enable High-Speed Support
657 * Pre-Requisites
658 * - Controller should support High-Speed-Enable Bit
659 * - Controller should not be using DDR Mode
660 * - Controller should advertise that it supports High Speed
661 * in capabilities register
662 * - MMC/SD clock coming out of controller > 25MHz
663 */
326119c9 664 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
5438ad95 665 (ios->timing != MMC_TIMING_MMC_DDR52) &&
903101a8 666 (ios->timing != MMC_TIMING_UHS_DDR50) &&
cd587096
HG		 667 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
668 regval = OMAP_HSMMC_READ(host->base, HCTL);
669 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
670 regval |= HSPE;
671 else
672 regval &= ~HSPE;
673
674 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
675 }
676
5934df2f
AS		 677 omap_hsmmc_start_clock(host);
678}
679
3796fb8a
AS		 680static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
681{
682 struct mmc_ios *ios = &host->mmc->ios;
683 u32 con;
684
685 con = OMAP_HSMMC_READ(host->base, CON);
903101a8
UH		 686 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
687 ios->timing == MMC_TIMING_UHS_DDR50)
03b5d924
B		 688 con |= DDR; /* configure in DDR mode */
689 else
690 con &= ~DDR;
3796fb8a
AS		 691 switch (ios->bus_width) {
692 case MMC_BUS_WIDTH_8:
693 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
694 break;
695 case MMC_BUS_WIDTH_4:
696 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
697 OMAP_HSMMC_WRITE(host->base, HCTL,
698 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
699 break;
700 case MMC_BUS_WIDTH_1:
701 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
702 OMAP_HSMMC_WRITE(host->base, HCTL,
703 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
704 break;
705 }
706}
707
708static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
709{
710 struct mmc_ios *ios = &host->mmc->ios;
711 u32 con;
712
713 con = OMAP_HSMMC_READ(host->base, CON);
714 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
715 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
716 else
717 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
718}
719
11dd62a7
DK		 720#ifdef CONFIG_PM
721
722/*
723 * Restore the MMC host context, if it was lost as result of a
724 * power state change.
725 */
70a3341a 726static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 727{
728 struct mmc_ios *ios = &host->mmc->ios;
3796fb8a 729 u32 hctl, capa;
11dd62a7
DK		 730 unsigned long timeout;
731
0a82e06e
TL		 732 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
733 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
734 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
735 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
736 return 0;
737
738 host->context_loss++;
739
c2200efb 740 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 741 if (host->power_mode != MMC_POWER_OFF &&
742 (1 << ios->vdd) <= MMC_VDD_23_24)
743 hctl = SDVS18;
744 else
745 hctl = SDVS30;
746 capa = VS30 | VS18;
747 } else {
748 hctl = SDVS18;
749 capa = VS18;
750 }
751
5a52b08b
B		 752 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
753 hctl |= IWE;
754
11dd62a7
DK		 755 OMAP_HSMMC_WRITE(host->base, HCTL,
756 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
757
758 OMAP_HSMMC_WRITE(host->base, CAPA,
759 OMAP_HSMMC_READ(host->base, CAPA) | capa);
760
761 OMAP_HSMMC_WRITE(host->base, HCTL,
762 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
763
764 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
765 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
766 && time_before(jiffies, timeout))
767 ;
768
2cd3a2a5
AF		 769 OMAP_HSMMC_WRITE(host->base, ISE, 0);
770 OMAP_HSMMC_WRITE(host->base, IE, 0);
771 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
11dd62a7
DK		 772
773 /* Do not initialize card-specific things if the power is off */
774 if (host->power_mode == MMC_POWER_OFF)
775 goto out;
776
3796fb8a 777 omap_hsmmc_set_bus_width(host);
11dd62a7 778
5934df2f 779 omap_hsmmc_set_clock(host);
11dd62a7 780
3796fb8a
AS		 781 omap_hsmmc_set_bus_mode(host);
782
11dd62a7 783out:
0a82e06e
TL		 784 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
785 host->context_loss);
11dd62a7
DK		 786 return 0;
787}
788
789/*
790 * Save the MMC host context (store the number of power state changes so far).
791 */
70a3341a 792static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7 793{
0a82e06e
TL		 794 host->con = OMAP_HSMMC_READ(host->base, CON);
795 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
796 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
797 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
11dd62a7
DK		 798}
799
800#else
801
70a3341a 802static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 803{
804 return 0;
805}
806
70a3341a 807static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 808{
809}
810
811#endif
812
a45c6cb8
MC		 813/*
814 * Send init stream sequence to card
815 * before sending IDLE command
816 */
70a3341a 817static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 818{
819 int reg = 0;
820 unsigned long timeout;
821
b62f6228
AH		 822 if (host->protect_card)
823 return;
824
a45c6cb8 825 disable_irq(host->irq);
b417577d
AH		 826
827 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 828 OMAP_HSMMC_WRITE(host->base, CON,
829 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
830 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
831
832 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
a7e96879
V		 833 while ((reg != CC_EN) && time_before(jiffies, timeout))
834 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
a45c6cb8
MC		 835
836 OMAP_HSMMC_WRITE(host->base, CON,
837 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 838
839 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
840 OMAP_HSMMC_READ(host->base, STAT);
841
a45c6cb8
MC		 842 enable_irq(host->irq);
843}
844
845static inline
70a3341a 846int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 847{
848 int r = 1;
849
b5cd43f0 850 if (host->get_cover_state)
80412ca8 851 r = host->get_cover_state(host->dev);
a45c6cb8
MC		 852 return r;
853}
854
855static ssize_t
70a3341a 856omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 857 char *buf)
858{
859 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 860 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 861
70a3341a
DK		 862 return sprintf(buf, "%s\n",
863 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 864}
865
70a3341a 866static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 867
868static ssize_t
70a3341a 869omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 870 char *buf)
871{
872 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 873 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 874
326119c9 875 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
a45c6cb8
MC		 876}
877
70a3341a 878static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 879
880/*
881 * Configure the response type and send the cmd.
882 */
883static void
70a3341a 884omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 885 struct mmc_data *data)
886{
887 int cmdreg = 0, resptype = 0, cmdtype = 0;
888
8986d31b 889 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
a45c6cb8
MC		 890 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
891 host->cmd = cmd;
892
93caf8e6 893 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 894
4a694dc9 895 host->response_busy = 0;
a45c6cb8
MC		 896 if (cmd->flags & MMC_RSP_PRESENT) {
897 if (cmd->flags & MMC_RSP_136)
898 resptype = 1;
4a694dc9
AH		 899 else if (cmd->flags & MMC_RSP_BUSY) {
900 resptype = 3;
901 host->response_busy = 1;
902 } else
a45c6cb8
MC		 903 resptype = 2;
904 }
905
906 /*
907 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
908 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
909 * a val of 0x3, rest 0x0.
910 */
911 if (cmd == host->mrq->stop)
912 cmdtype = 0x3;
913
914 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
915
a2e77152
B		 916 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
917 host->mrq->sbc) {
918 cmdreg |= ACEN_ACMD23;
919 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
920 }
a45c6cb8
MC		 921 if (data) {
922 cmdreg |= DP_SELECT | MSBS | BCE;
923 if (data->flags & MMC_DATA_READ)
924 cmdreg |= DDIR;
925 else
926 cmdreg &= ~(DDIR);
927 }
928
929 if (host->use_dma)
a7e96879 930 cmdreg |= DMAE;
a45c6cb8 931
b417577d 932 host->req_in_progress = 1;
4dffd7a2 933
a45c6cb8
MC		 934 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
935 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
936}
937
0ccd76d4 938static int
70a3341a 939omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 940{
941 if (data->flags & MMC_DATA_WRITE)
942 return DMA_TO_DEVICE;
943 else
944 return DMA_FROM_DEVICE;
945}
946
c5c98927
RK		 947static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
948 struct mmc_data *data)
949{
950 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
951}
952
b417577d
AH		 953static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
954{
955 int dma_ch;
31463b14 956 unsigned long flags;
b417577d 957
31463b14 958 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 959 host->req_in_progress = 0;
960 dma_ch = host->dma_ch;
31463b14 961 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 962
963 omap_hsmmc_disable_irq(host);
964 /* Do not complete the request if DMA is still in progress */
965 if (mrq->data && host->use_dma && dma_ch != -1)
966 return;
967 host->mrq = NULL;
968 mmc_request_done(host->mmc, mrq);
969}
970
a45c6cb8
MC		 971/*
972 * Notify the transfer complete to MMC core
973 */
974static void
70a3341a 975omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 976{
4a694dc9
AH		 977 if (!data) {
978 struct mmc_request *mrq = host->mrq;
979
23050103
AH		 980 /* TC before CC from CMD6 - don't know why, but it happens */
981 if (host->cmd && host->cmd->opcode == 6 &&
982 host->response_busy) {
983 host->response_busy = 0;
984 return;
985 }
986
b417577d 987 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 988 return;
989 }
990
a45c6cb8
MC		 991 host->data = NULL;
992
a45c6cb8
MC		 993 if (!data->error)
994 data->bytes_xfered += data->blocks * (data->blksz);
995 else
996 data->bytes_xfered = 0;
997
bf129e1c
B		 998 if (data->stop && (data->error || !host->mrq->sbc))
999 omap_hsmmc_start_command(host, data->stop, NULL);
1000 else
b417577d 1001 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 1002}
1003
1004/*
1005 * Notify the core about command completion
1006 */
1007static void
70a3341a 1008omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8 1009{
bf129e1c 1010 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
a2e77152 1011 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
2177fa94 1012 host->cmd = NULL;
bf129e1c
B		 1013 omap_hsmmc_start_dma_transfer(host);
1014 omap_hsmmc_start_command(host, host->mrq->cmd,
1015 host->mrq->data);
1016 return;
1017 }
1018
2177fa94
B		 1019 host->cmd = NULL;
1020
a45c6cb8
MC		 1021 if (cmd->flags & MMC_RSP_PRESENT) {
1022 if (cmd->flags & MMC_RSP_136) {
1023 /* response type 2 */
1024 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1025 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1026 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1027 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1028 } else {
1029 /* response types 1, 1b, 3, 4, 5, 6 */
1030 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1031 }
1032 }
b417577d 1033 if ((host->data == NULL && !host->response_busy) || cmd->error)
d4b2c375 1034 omap_hsmmc_request_done(host, host->mrq);
a45c6cb8
MC		 1035}
1036
1037/*
1038 * DMA clean up for command errors
1039 */
70a3341a 1040static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 1041{
b417577d 1042 int dma_ch;
31463b14 1043 unsigned long flags;
b417577d 1044
82788ff5 1045 host->data->error = errno;
a45c6cb8 1046
31463b14 1047 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 1048 dma_ch = host->dma_ch;
1049 host->dma_ch = -1;
31463b14 1050 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 1051
1052 if (host->use_dma && dma_ch != -1) {
c5c98927
RK		 1053 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1054
1055 dmaengine_terminate_all(chan);
1056 dma_unmap_sg(chan->device->dev,
1057 host->data->sg, host->data->sg_len,
70a3341a 1058 omap_hsmmc_get_dma_dir(host, host->data));
c5c98927 1059
053bf34f 1060 host->data->host_cookie = 0;
a45c6cb8
MC		 1061 }
1062 host->data = NULL;
a45c6cb8
MC		 1063}
1064
1065/*
1066 * Readable error output
1067 */
1068#ifdef CONFIG_MMC_DEBUG
699b958b 1069static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 1070{
1071 /* --- means reserved bit without definition at documentation */
70a3341a 1072 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 1073 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1074 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1075 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1076 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 1077 };
1078 char res[256];
1079 char *buf = res;
1080 int len, i;
1081
1082 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1083 buf += len;
1084
70a3341a 1085 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 1086 if (status & (1 << i)) {
70a3341a 1087 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 1088 buf += len;
1089 }
1090
8986d31b 1091 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
a45c6cb8 1092}
699b958b
AH		 1093#else
1094static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1095 u32 status)
1096{
1097}
a45c6cb8
MC		 1098#endif /* CONFIG_MMC_DEBUG */
1099
3ebf74b1
JP		 1100/*
1101 * MMC controller internal state machines reset
1102 *
1103 * Used to reset command or data internal state machines, using respectively
1104 * SRC or SRD bit of SYSCTL register
1105 * Can be called from interrupt context
1106 */
70a3341a
DK		 1107static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1108 unsigned long bit)
3ebf74b1
JP		 1109{
1110 unsigned long i = 0;
1e881786 1111 unsigned long limit = MMC_TIMEOUT_US;
3ebf74b1
JP		 1112
1113 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1114 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1115
07ad64b6
MC		 1116 /*
1117 * OMAP4 ES2 and greater has an updated reset logic.
1118 * Monitor a 0->1 transition first
1119 */
326119c9 1120 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1121 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6 1122 && (i++ < limit))
1e881786 1123 udelay(1);
07ad64b6
MC		 1124 }
1125 i = 0;
1126
3ebf74b1
JP		 1127 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1128 (i++ < limit))
1e881786 1129 udelay(1);
3ebf74b1
JP		 1130
1131 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1132 dev_err(mmc_dev(host->mmc),
1133 "Timeout waiting on controller reset in %s\n",
1134 __func__);
1135}
a45c6cb8 1136
25e1897b
B		 1137static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1138 int err, int end_cmd)
ae4bf788 1139{
25e1897b 1140 if (end_cmd) {
94d4f272 1141 omap_hsmmc_reset_controller_fsm(host, SRC);
25e1897b
B		 1142 if (host->cmd)
1143 host->cmd->error = err;
1144 }
ae4bf788
V		 1145
1146 if (host->data) {
1147 omap_hsmmc_reset_controller_fsm(host, SRD);
1148 omap_hsmmc_dma_cleanup(host, err);
dc7745bd
B		 1149 } else if (host->mrq && host->mrq->cmd)
1150 host->mrq->cmd->error = err;
ae4bf788
V		 1151}
1152
b417577d 1153static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1154{
a45c6cb8 1155 struct mmc_data *data;
b417577d 1156 int end_cmd = 0, end_trans = 0;
a2e77152 1157 int error = 0;
b417577d 1158
a45c6cb8 1159 data = host->data;
8986d31b 1160 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
a45c6cb8 1161
a7e96879 1162 if (status & ERR_EN) {
699b958b 1163 omap_hsmmc_dbg_report_irq(host, status);
25e1897b 1164
a7e96879 1165 if (status & (CTO_EN | CCRC_EN))
25e1897b 1166 end_cmd = 1;
408806f7
KVA		 1167 if (host->data || host->response_busy) {
1168 end_trans = !end_cmd;
1169 host->response_busy = 0;
1170 }
a7e96879 1171 if (status & (CTO_EN | DTO_EN))
25e1897b 1172 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
5027cd1e
V		 1173 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1174 BADA_EN))
25e1897b 1175 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
ae4bf788 1176
a2e77152
B		 1177 if (status & ACE_EN) {
1178 u32 ac12;
1179 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1180 if (!(ac12 & ACNE) && host->mrq->sbc) {
1181 end_cmd = 1;
1182 if (ac12 & ACTO)
1183 error = -ETIMEDOUT;
1184 else if (ac12 & (ACCE | ACEB | ACIE))
1185 error = -EILSEQ;
1186 host->mrq->sbc->error = error;
1187 hsmmc_command_incomplete(host, error, end_cmd);
1188 }
1189 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1190 }
a45c6cb8
MC		 1191 }
1192
7472bab2 1193 OMAP_HSMMC_WRITE(host->base, STAT, status);
a7e96879 1194 if (end_cmd || ((status & CC_EN) && host->cmd))
70a3341a 1195 omap_hsmmc_cmd_done(host, host->cmd);
a7e96879 1196 if ((end_trans || (status & TC_EN)) && host->mrq)
70a3341a 1197 omap_hsmmc_xfer_done(host, data);
b417577d 1198}
a45c6cb8 1199
b417577d
AH		 1200/*
1201 * MMC controller IRQ handler
1202 */
1203static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1204{
1205 struct omap_hsmmc_host *host = dev_id;
1206 int status;
1207
1208 status = OMAP_HSMMC_READ(host->base, STAT);
2cd3a2a5
AF		 1209 while (status & (INT_EN_MASK | CIRQ_EN)) {
1210 if (host->req_in_progress)
1211 omap_hsmmc_do_irq(host, status);
1212
1213 if (status & CIRQ_EN)
1214 mmc_signal_sdio_irq(host->mmc);
1f6b9fa4 1215
b417577d
AH		 1216 /* Flush posted write */
1217 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1218 }
4dffd7a2 1219
a45c6cb8
MC		 1220 return IRQ_HANDLED;
1221}
1222
70a3341a 1223static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1224{
1225 unsigned long i;
1226
1227 OMAP_HSMMC_WRITE(host->base, HCTL,
1228 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1229 for (i = 0; i < loops_per_jiffy; i++) {
1230 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1231 break;
1232 cpu_relax();
1233 }
1234}
1235
a45c6cb8 1236/*
eb250826
DB		 1237 * Switch MMC interface voltage ... only relevant for MMC1.
1238 *
1239 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1240 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1241 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1242 */
70a3341a 1243static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1244{
1245 u32 reg_val = 0;
1246 int ret;
1247
1248 /* Disable the clocks */
cd03d9a8 1249 if (host->dbclk)
94c18149 1250 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1251
1252 /* Turn the power off */
1ca4d359 1253 ret = omap_hsmmc_set_power(host, 0, 0);
a45c6cb8
MC		 1254
1255 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893 1256 if (!ret)
1ca4d359 1257 ret = omap_hsmmc_set_power(host, 1, vdd);
cd03d9a8 1258 if (host->dbclk)
94c18149 1259 clk_prepare_enable(host->dbclk);
2bec0893 1260
a45c6cb8
MC		 1261 if (ret != 0)
1262 goto err;
1263
a45c6cb8
MC		 1264 OMAP_HSMMC_WRITE(host->base, HCTL,
1265 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1266 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1267
a45c6cb8
MC		 1268 /*
1269 * If a MMC dual voltage card is detected, the set_ios fn calls
1270 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1271 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1272 *
eb250826
DB		 1273 * Cope with a bit of slop in the range ... per data sheets:
1274 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1275 * but recommended values are 1.71V to 1.89V
1276 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1277 * but recommended values are 2.7V to 3.3V
1278 *
1279 * Board setup code shouldn't permit anything very out-of-range.
1280 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1281 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1282 */
eb250826 1283 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1284 reg_val |= SDVS18;
eb250826
DB		 1285 else
1286 reg_val |= SDVS30;
a45c6cb8
MC		 1287
1288 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1289 set_sd_bus_power(host);
a45c6cb8
MC		 1290
1291 return 0;
1292err:
b1e056ae 1293 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
a45c6cb8
MC		 1294 return ret;
1295}
1296
b62f6228
AH		 1297/* Protect the card while the cover is open */
1298static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1299{
b5cd43f0 1300 if (!host->get_cover_state)
b62f6228
AH		 1301 return;
1302
1303 host->reqs_blocked = 0;
80412ca8 1304 if (host->get_cover_state(host->dev)) {
b62f6228 1305 if (host->protect_card) {
2cecdf00 1306 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1307 "card is now accessible\n",
1308 mmc_hostname(host->mmc));
1309 host->protect_card = 0;
1310 }
1311 } else {
1312 if (!host->protect_card) {
2cecdf00 1313 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1314 "card is now inaccessible\n",
1315 mmc_hostname(host->mmc));
1316 host->protect_card = 1;
1317 }
1318 }
1319}
1320
a45c6cb8 1321/*
cde592cb 1322 * irq handler when (cell-phone) cover is mounted/removed
a45c6cb8 1323 */
cde592cb 1324static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
a45c6cb8 1325{
7efab4f3 1326 struct omap_hsmmc_host *host = dev_id;
a6b2240d 1327
a6b2240d 1328 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1329
11227d12
AF		 1330 omap_hsmmc_protect_card(host);
1331 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cde592cb
AF		 1332 return IRQ_HANDLED;
1333}
1334
c5c98927 1335static void omap_hsmmc_dma_callback(void *param)
a45c6cb8 1336{
c5c98927
RK		 1337 struct omap_hsmmc_host *host = param;
1338 struct dma_chan *chan;
770d7432 1339 struct mmc_data *data;
c5c98927 1340 int req_in_progress;
a45c6cb8 1341
c5c98927 1342 spin_lock_irq(&host->irq_lock);
b417577d 1343 if (host->dma_ch < 0) {
c5c98927 1344 spin_unlock_irq(&host->irq_lock);
a45c6cb8 1345 return;
b417577d 1346 }
a45c6cb8 1347
770d7432 1348 data = host->mrq->data;
c5c98927 1349 chan = omap_hsmmc_get_dma_chan(host, data);
9782aff8 1350 if (!data->host_cookie)
c5c98927
RK		 1351 dma_unmap_sg(chan->device->dev,
1352 data->sg, data->sg_len,
9782aff8 1353 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1354
1355 req_in_progress = host->req_in_progress;
a45c6cb8 1356 host->dma_ch = -1;
c5c98927 1357 spin_unlock_irq(&host->irq_lock);
b417577d
AH		 1358
1359 /* If DMA has finished after TC, complete the request */
1360 if (!req_in_progress) {
1361 struct mmc_request *mrq = host->mrq;
1362
1363 host->mrq = NULL;
1364 mmc_request_done(host->mmc, mrq);
1365 }
a45c6cb8
MC		 1366}
1367
9782aff8
PF		 1368static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1369 struct mmc_data *data,
c5c98927 1370 struct omap_hsmmc_next *next,
26b88520 1371 struct dma_chan *chan)
9782aff8
PF		 1372{
1373 int dma_len;
1374
1375 if (!next && data->host_cookie &&
1376 data->host_cookie != host->next_data.cookie) {
2cecdf00 1377 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1378 " host->next_data.cookie %d\n",
1379 __func__, data->host_cookie, host->next_data.cookie);
1380 data->host_cookie = 0;
1381 }
1382
1383 /* Check if next job is already prepared */
b38313d6 1384 if (next || data->host_cookie != host->next_data.cookie) {
26b88520 1385 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
9782aff8
PF		 1386 omap_hsmmc_get_dma_dir(host, data));
1387
1388 } else {
1389 dma_len = host->next_data.dma_len;
1390 host->next_data.dma_len = 0;
1391 }
1392
1393
1394 if (dma_len == 0)
1395 return -EINVAL;
1396
1397 if (next) {
1398 next->dma_len = dma_len;
1399 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1400 } else
1401 host->dma_len = dma_len;
1402
1403 return 0;
1404}
1405
a45c6cb8
MC		 1406/*
1407 * Routine to configure and start DMA for the MMC card
1408 */
9d025334 1409static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
70a3341a 1410 struct mmc_request *req)
a45c6cb8 1411{
26b88520
RK		 1412 struct dma_async_tx_descriptor *tx;
1413 int ret = 0, i;
a45c6cb8 1414 struct mmc_data *data = req->data;
c5c98927 1415 struct dma_chan *chan;
e5789608
PU		 1416 struct dma_slave_config cfg = {
1417 .src_addr = host->mapbase + OMAP_HSMMC_DATA,
1418 .dst_addr = host->mapbase + OMAP_HSMMC_DATA,
1419 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1420 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
1421 .src_maxburst = data->blksz / 4,
1422 .dst_maxburst = data->blksz / 4,
1423 };
a45c6cb8 1424
0ccd76d4 1425 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1426 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1427 struct scatterlist *sgl;
1428
1429 sgl = data->sg + i;
1430 if (sgl->length % data->blksz)
1431 return -EINVAL;
1432 }
1433 if ((data->blksz % 4) != 0)
1434 /* REVISIT: The MMC buffer increments only when MSB is written.
1435 * Return error for blksz which is non multiple of four.
1436 */
1437 return -EINVAL;
1438
b417577d 1439 BUG_ON(host->dma_ch != -1);
a45c6cb8 1440
c5c98927 1441 chan = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1442
26b88520
RK		 1443 ret = dmaengine_slave_config(chan, &cfg);
1444 if (ret)
a45c6cb8 1445 return ret;
c5c98927 1446
26b88520 1447 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
9782aff8
PF		 1448 if (ret)
1449 return ret;
a45c6cb8 1450
26b88520
RK		 1451 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1452 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1453 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1454 if (!tx) {
1455 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1456 /* FIXME: cleanup */
1457 return -1;
1458 }
a45c6cb8 1459
26b88520
RK		 1460 tx->callback = omap_hsmmc_dma_callback;
1461 tx->callback_param = host;
a45c6cb8 1462
26b88520
RK		 1463 /* Does not fail */
1464 dmaengine_submit(tx);
c5c98927 1465
26b88520 1466 host->dma_ch = 1;
c5c98927 1467
a45c6cb8
MC		 1468 return 0;
1469}
1470
70a3341a 1471static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1472 unsigned int timeout_ns,
1473 unsigned int timeout_clks)
a45c6cb8
MC		 1474{
1475 unsigned int timeout, cycle_ns;
1476 uint32_t reg, clkd, dto = 0;
1477
1478 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1479 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1480 if (clkd == 0)
1481 clkd = 1;
1482
6e3076c2 1483 cycle_ns = 1000000000 / (host->clk_rate / clkd);
e2bf08d6
AH		 1484 timeout = timeout_ns / cycle_ns;
1485 timeout += timeout_clks;
a45c6cb8
MC		 1486 if (timeout) {
1487 while ((timeout & 0x80000000) == 0) {
1488 dto += 1;
1489 timeout <<= 1;
1490 }
1491 dto = 31 - dto;
1492 timeout <<= 1;
1493 if (timeout && dto)
1494 dto += 1;
1495 if (dto >= 13)
1496 dto -= 13;
1497 else
1498 dto = 0;
1499 if (dto > 14)
1500 dto = 14;
1501 }
1502
1503 reg &= ~DTO_MASK;
1504 reg |= dto << DTO_SHIFT;
1505 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1506}
1507
9d025334
B		 1508static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1509{
1510 struct mmc_request *req = host->mrq;
1511 struct dma_chan *chan;
1512
1513 if (!req->data)
1514 return;
1515 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1516 | (req->data->blocks << 16));
1517 set_data_timeout(host, req->data->timeout_ns,
1518 req->data->timeout_clks);
1519 chan = omap_hsmmc_get_dma_chan(host, req->data);
1520 dma_async_issue_pending(chan);
1521}
1522
a45c6cb8
MC		 1523/*
1524 * Configure block length for MMC/SD cards and initiate the transfer.
1525 */
1526static int
70a3341a 1527omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1528{
1529 int ret;
1530 host->data = req->data;
1531
1532 if (req->data == NULL) {
a45c6cb8 1533 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1534 /*
1535 * Set an arbitrary 100ms data timeout for commands with
1536 * busy signal.
1537 */
1538 if (req->cmd->flags & MMC_RSP_BUSY)
1539 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1540 return 0;
1541 }
1542
a45c6cb8 1543 if (host->use_dma) {
9d025334 1544 ret = omap_hsmmc_setup_dma_transfer(host, req);
a45c6cb8 1545 if (ret != 0) {
b1e056ae 1546 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
a45c6cb8
MC		 1547 return ret;
1548 }
1549 }
1550 return 0;
1551}
1552
9782aff8
PF		 1553static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1554 int err)
1555{
1556 struct omap_hsmmc_host *host = mmc_priv(mmc);
1557 struct mmc_data *data = mrq->data;
1558
26b88520 1559 if (host->use_dma && data->host_cookie) {
c5c98927 1560 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1561
26b88520
RK		 1562 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1563 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1564 data->host_cookie = 0;
1565 }
1566}
1567
1568static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1569 bool is_first_req)
1570{
1571 struct omap_hsmmc_host *host = mmc_priv(mmc);
1572
1573 if (mrq->data->host_cookie) {
1574 mrq->data->host_cookie = 0;
1575 return ;
1576 }
1577
c5c98927
RK		 1578 if (host->use_dma) {
1579 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
c5c98927 1580
9782aff8 1581 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
26b88520 1582 &host->next_data, c))
9782aff8 1583 mrq->data->host_cookie = 0;
c5c98927 1584 }
9782aff8
PF		 1585}
1586
a45c6cb8
MC		 1587/*
1588 * Request function. for read/write operation
1589 */
70a3341a 1590static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1591{
70a3341a 1592 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1593 int err;
a45c6cb8 1594
b417577d
AH		 1595 BUG_ON(host->req_in_progress);
1596 BUG_ON(host->dma_ch != -1);
1597 if (host->protect_card) {
1598 if (host->reqs_blocked < 3) {
1599 /*
1600 * Ensure the controller is left in a consistent
1601 * state by resetting the command and data state
1602 * machines.
1603 */
1604 omap_hsmmc_reset_controller_fsm(host, SRD);
1605 omap_hsmmc_reset_controller_fsm(host, SRC);
1606 host->reqs_blocked += 1;
1607 }
1608 req->cmd->error = -EBADF;
1609 if (req->data)
1610 req->data->error = -EBADF;
1611 req->cmd->retries = 0;
1612 mmc_request_done(mmc, req);
1613 return;
1614 } else if (host->reqs_blocked)
1615 host->reqs_blocked = 0;
a45c6cb8
MC		 1616 WARN_ON(host->mrq != NULL);
1617 host->mrq = req;
6e3076c2 1618 host->clk_rate = clk_get_rate(host->fclk);
70a3341a 1619 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1620 if (err) {
1621 req->cmd->error = err;
1622 if (req->data)
1623 req->data->error = err;
1624 host->mrq = NULL;
1625 mmc_request_done(mmc, req);
1626 return;
1627 }
a2e77152 1628 if (req->sbc && !(host->flags & AUTO_CMD23)) {
bf129e1c
B		 1629 omap_hsmmc_start_command(host, req->sbc, NULL);
1630 return;
1631 }
a3f406f8 1632
9d025334 1633 omap_hsmmc_start_dma_transfer(host);
70a3341a 1634 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1635}
1636
a45c6cb8 1637/* Routine to configure clock values. Exposed API to core */
70a3341a 1638static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1639{
70a3341a 1640 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1641 int do_send_init_stream = 0;
a45c6cb8 1642
a3621465
AH		 1643 if (ios->power_mode != host->power_mode) {
1644 switch (ios->power_mode) {
1645 case MMC_POWER_OFF:
1ca4d359 1646 omap_hsmmc_set_power(host, 0, 0);
a3621465
AH		 1647 break;
1648 case MMC_POWER_UP:
1ca4d359 1649 omap_hsmmc_set_power(host, 1, ios->vdd);
a3621465
AH		 1650 break;
1651 case MMC_POWER_ON:
1652 do_send_init_stream = 1;
1653 break;
1654 }
1655 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1656 }
1657
dd498eff
DK		 1658 /* FIXME: set registers based only on changes to ios */
1659
3796fb8a 1660 omap_hsmmc_set_bus_width(host);
a45c6cb8 1661
4621d5f8 1662 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1663 /* Only MMC1 can interface at 3V without some flavor
1664 * of external transceiver; but they all handle 1.8V.
1665 */
a45c6cb8 1666 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
2cf171cb 1667 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
a45c6cb8
MC		 1668 /*
1669 * The mmc_select_voltage fn of the core does
1670 * not seem to set the power_mode to
1671 * MMC_POWER_UP upon recalculating the voltage.
1672 * vdd 1.8v.
1673 */
70a3341a
DK		 1674 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1675 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1676 "Switch operation failed\n");
1677 }
1678 }
1679
5934df2f 1680 omap_hsmmc_set_clock(host);
a45c6cb8 1681
a3621465 1682 if (do_send_init_stream)
a45c6cb8
MC		 1683 send_init_stream(host);
1684
3796fb8a 1685 omap_hsmmc_set_bus_mode(host);
a45c6cb8
MC		 1686}
1687
1688static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1689{
70a3341a 1690 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1691
b5cd43f0 1692 if (!host->card_detect)
a45c6cb8 1693 return -ENOSYS;
80412ca8 1694 return host->card_detect(host->dev);
a45c6cb8
MC		 1695}
1696
4816858c
GI		 1697static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1698{
1699 struct omap_hsmmc_host *host = mmc_priv(mmc);
1700
326119c9
AF		 1701 if (mmc_pdata(host)->init_card)
1702 mmc_pdata(host)->init_card(card);
4816858c
GI		 1703}
1704
2cd3a2a5
AF		 1705static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1706{
1707 struct omap_hsmmc_host *host = mmc_priv(mmc);
5a52b08b 1708 u32 irq_mask, con;
2cd3a2a5
AF		 1709 unsigned long flags;
1710
1711 spin_lock_irqsave(&host->irq_lock, flags);
1712
5a52b08b 1713 con = OMAP_HSMMC_READ(host->base, CON);
2cd3a2a5
AF		 1714 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1715 if (enable) {
1716 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1717 irq_mask |= CIRQ_EN;
5a52b08b 1718 con |= CTPL | CLKEXTFREE;
2cd3a2a5
AF		 1719 } else {
1720 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1721 irq_mask &= ~CIRQ_EN;
5a52b08b 1722 con &= ~(CTPL | CLKEXTFREE);
2cd3a2a5 1723 }
5a52b08b 1724 OMAP_HSMMC_WRITE(host->base, CON, con);
2cd3a2a5
AF		 1725 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1726
1727 /*
1728 * if enable, piggy back detection on current request
1729 * but always disable immediately
1730 */
1731 if (!host->req_in_progress || !enable)
1732 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1733
1734 /* flush posted write */
1735 OMAP_HSMMC_READ(host->base, IE);
1736
1737 spin_unlock_irqrestore(&host->irq_lock, flags);
1738}
1739
1740static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1741{
2cd3a2a5
AF		 1742 int ret;
1743
1744 /*
1745 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1746 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1747 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1748 * with functional clock disabled.
1749 */
1750 if (!host->dev->of_node || !host->wake_irq)
1751 return -ENODEV;
1752
5b83b223 1753 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
2cd3a2a5
AF		 1754 if (ret) {
1755 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1756 goto err;
1757 }
1758
1759 /*
1760 * Some omaps don't have wake-up path from deeper idle states
1761 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1762 */
1763 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
455e5cd6
AF		 1764 struct pinctrl *p = devm_pinctrl_get(host->dev);
1765 if (!p) {
1766 ret = -ENODEV;
1767 goto err_free_irq;
1768 }
1769 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1770 dev_info(host->dev, "missing default pinctrl state\n");
1771 devm_pinctrl_put(p);
1772 ret = -EINVAL;
1773 goto err_free_irq;
1774 }
1775
1776 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1777 dev_info(host->dev, "missing idle pinctrl state\n");
1778 devm_pinctrl_put(p);
1779 ret = -EINVAL;
1780 goto err_free_irq;
1781 }
1782 devm_pinctrl_put(p);
2cd3a2a5
AF		 1783 }
1784
5a52b08b
B		 1785 OMAP_HSMMC_WRITE(host->base, HCTL,
1786 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
2cd3a2a5
AF		 1787 return 0;
1788
455e5cd6 1789err_free_irq:
5b83b223 1790 dev_pm_clear_wake_irq(host->dev);
2cd3a2a5
AF		 1791err:
1792 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1793 host->wake_irq = 0;
1794 return ret;
1795}
1796
70a3341a 1797static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1798{
1799 u32 hctl, capa, value;
1800
1801 /* Only MMC1 supports 3.0V */
4621d5f8 1802 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1803 hctl = SDVS30;
1804 capa = VS30 | VS18;
1805 } else {
1806 hctl = SDVS18;
1807 capa = VS18;
1808 }
1809
1810 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1811 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1812
1813 value = OMAP_HSMMC_READ(host->base, CAPA);
1814 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1815
1b331e69 1816 /* Set SD bus power bit */
e13bb300 1817 set_sd_bus_power(host);
1b331e69
KK		 1818}
1819
afd8c29d
KM		 1820static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1821 unsigned int direction, int blk_size)
1822{
1823 /* This controller can't do multiblock reads due to hw bugs */
1824 if (direction == MMC_DATA_READ)
1825 return 1;
1826
1827 return blk_size;
1828}
1829
1830static struct mmc_host_ops omap_hsmmc_ops = {
9782aff8
PF		 1831 .post_req = omap_hsmmc_post_req,
1832 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1833 .request = omap_hsmmc_request,
1834 .set_ios = omap_hsmmc_set_ios,
dd498eff 1835 .get_cd = omap_hsmmc_get_cd,
a49d8353 1836 .get_ro = mmc_gpio_get_ro,
4816858c 1837 .init_card = omap_hsmmc_init_card,
2cd3a2a5 1838 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
dd498eff
DK		 1839};
1840
d900f712
DK		 1841#ifdef CONFIG_DEBUG_FS
1842
70a3341a 1843static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1844{
1845 struct mmc_host *mmc = s->private;
70a3341a 1846 struct omap_hsmmc_host *host = mmc_priv(mmc);
d900f712 1847
bb0635f0
AF		 1848 seq_printf(s, "mmc%d:\n", mmc->index);
1849 seq_printf(s, "sdio irq mode\t%s\n",
1850 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
5e2ea617 1851
bb0635f0
AF		 1852 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1853 seq_printf(s, "sdio irq \t%s\n",
1854 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1855 : "disabled");
1856 }
1857 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
d900f712 1858
bb0635f0
AF		 1859 pm_runtime_get_sync(host->dev);
1860 seq_puts(s, "\nregs:\n");
d900f712
DK		 1861 seq_printf(s, "CON:\t\t0x%08x\n",
1862 OMAP_HSMMC_READ(host->base, CON));
bb0635f0
AF		 1863 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1864 OMAP_HSMMC_READ(host->base, PSTATE));
d900f712
DK		 1865 seq_printf(s, "HCTL:\t\t0x%08x\n",
1866 OMAP_HSMMC_READ(host->base, HCTL));
1867 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1868 OMAP_HSMMC_READ(host->base, SYSCTL));
1869 seq_printf(s, "IE:\t\t0x%08x\n",
1870 OMAP_HSMMC_READ(host->base, IE));
1871 seq_printf(s, "ISE:\t\t0x%08x\n",
1872 OMAP_HSMMC_READ(host->base, ISE));
1873 seq_printf(s, "CAPA:\t\t0x%08x\n",
1874 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1875
fa4aa2d4
B		 1876 pm_runtime_mark_last_busy(host->dev);
1877 pm_runtime_put_autosuspend(host->dev);
dd498eff 1878
d900f712
DK		 1879 return 0;
1880}
1881
70a3341a 1882static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1883{
70a3341a 1884 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1885}
1886
1887static const struct file_operations mmc_regs_fops = {
70a3341a 1888 .open = omap_hsmmc_regs_open,
d900f712
DK		 1889 .read = seq_read,
1890 .llseek = seq_lseek,
1891 .release = single_release,
1892};
1893
70a3341a 1894static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1895{
1896 if (mmc->debugfs_root)
1897 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1898 mmc, &mmc_regs_fops);
1899}
1900
1901#else
1902
70a3341a 1903static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1904{
1905}
1906
1907#endif
1908
46856a68 1909#ifdef CONFIG_OF
59445b10
NM		 1910static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1911 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1912 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1913};
1914
1915static const struct omap_mmc_of_data omap4_mmc_of_data = {
1916 .reg_offset = 0x100,
1917};
2cd3a2a5
AF		 1918static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1919 .reg_offset = 0x100,
1920 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1921};
46856a68
RN		 1922
1923static const struct of_device_id omap_mmc_of_match[] = {
1924 {
1925 .compatible = "ti,omap2-hsmmc",
1926 },
59445b10
NM		 1927 {
1928 .compatible = "ti,omap3-pre-es3-hsmmc",
1929 .data = &omap3_pre_es3_mmc_of_data,
1930 },
46856a68
RN		 1931 {
1932 .compatible = "ti,omap3-hsmmc",
1933 },
1934 {
1935 .compatible = "ti,omap4-hsmmc",
59445b10 1936 .data = &omap4_mmc_of_data,
46856a68 1937 },
2cd3a2a5
AF		 1938 {
1939 .compatible = "ti,am33xx-hsmmc",
1940 .data = &am33xx_mmc_of_data,
1941 },
46856a68 1942 {},
b6d085f6 1943};
46856a68
RN		 1944MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1945
55143438 1946static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
46856a68 1947{
db863d89 1948 struct omap_hsmmc_platform_data *pdata, *legacy;
46856a68 1949 struct device_node *np = dev->of_node;
46856a68
RN		 1950
1951 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1952 if (!pdata)
19df45bc 1953 return ERR_PTR(-ENOMEM); /* out of memory */
46856a68 1954
db863d89
TL		 1955 legacy = dev_get_platdata(dev);
1956 if (legacy && legacy->name)
1957 pdata->name = legacy->name;
1958
46856a68
RN		 1959 if (of_find_property(np, "ti,dual-volt", NULL))
1960 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1961
b7a5646f
AF		 1962 pdata->gpio_cd = -EINVAL;
1963 pdata->gpio_cod = -EINVAL;
fdb9de12 1964 pdata->gpio_wp = -EINVAL;
46856a68
RN		 1965
1966 if (of_find_property(np, "ti,non-removable", NULL)) {
326119c9
AF		 1967 pdata->nonremovable = true;
1968 pdata->no_regulator_off_init = true;
46856a68 1969 }
46856a68
RN		 1970
1971 if (of_find_property(np, "ti,needs-special-reset", NULL))
326119c9 1972 pdata->features |= HSMMC_HAS_UPDATED_RESET;
46856a68 1973
cd587096 1974 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
326119c9 1975 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
cd587096 1976
46856a68
RN		 1977 return pdata;
1978}
1979#else
55143438 1980static inline struct omap_hsmmc_platform_data
46856a68
RN		 1981 *of_get_hsmmc_pdata(struct device *dev)
1982{
19df45bc 1983 return ERR_PTR(-EINVAL);
46856a68
RN		 1984}
1985#endif
1986
c3be1efd 1987static int omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8 1988{
55143438 1989 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
a45c6cb8 1990 struct mmc_host *mmc;
70a3341a 1991 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1992 struct resource *res;
db0fefc5 1993 int ret, irq;
46856a68 1994 const struct of_device_id *match;
59445b10 1995 const struct omap_mmc_of_data *data;
77fae219 1996 void __iomem *base;
46856a68
RN		 1997
1998 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1999 if (match) {
2000 pdata = of_get_hsmmc_pdata(&pdev->dev);
dc642c28
JL		 2001
2002 if (IS_ERR(pdata))
2003 return PTR_ERR(pdata);
2004
46856a68 2005 if (match->data) {
59445b10
NM		 2006 data = match->data;
2007 pdata->reg_offset = data->reg_offset;
2008 pdata->controller_flags |= data->controller_flags;
46856a68
RN		 2009 }
2010 }
a45c6cb8
MC		 2011
2012 if (pdata == NULL) {
2013 dev_err(&pdev->dev, "Platform Data is missing\n");
2014 return -ENXIO;
2015 }
2016
a45c6cb8
MC		 2017 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2018 irq = platform_get_irq(pdev, 0);
2019 if (res == NULL || irq < 0)
2020 return -ENXIO;
2021
77fae219
B		 2022 base = devm_ioremap_resource(&pdev->dev, res);
2023 if (IS_ERR(base))
2024 return PTR_ERR(base);
a45c6cb8 2025
70a3341a 2026 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 2027 if (!mmc) {
2028 ret = -ENOMEM;
1e363e3b 2029 goto err;
a45c6cb8
MC		 2030 }
2031
fdb9de12
N		 2032 ret = mmc_of_parse(mmc);
2033 if (ret)
2034 goto err1;
2035
a45c6cb8
MC		 2036 host = mmc_priv(mmc);
2037 host->mmc = mmc;
2038 host->pdata = pdata;
2039 host->dev = &pdev->dev;
2040 host->use_dma = 1;
a45c6cb8
MC		 2041 host->dma_ch = -1;
2042 host->irq = irq;
fc307df8 2043 host->mapbase = res->start + pdata->reg_offset;
77fae219 2044 host->base = base + pdata->reg_offset;
6da20c89 2045 host->power_mode = MMC_POWER_OFF;
9782aff8 2046 host->next_data.cookie = 1;
bb2726b5 2047 host->pbias_enabled = 0;
3f77f702 2048 host->vqmmc_enabled = 0;
a45c6cb8 2049
41afa314 2050 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
1e363e3b
AF		 2051 if (ret)
2052 goto err_gpio;
2053
a45c6cb8 2054 platform_set_drvdata(pdev, host);
a45c6cb8 2055
2cd3a2a5
AF		 2056 if (pdev->dev.of_node)
2057 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2058
7a8c2cef 2059 mmc->ops = &omap_hsmmc_ops;
dd498eff 2060
d418ed87
DM		 2061 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2062
2063 if (pdata->max_freq > 0)
2064 mmc->f_max = pdata->max_freq;
fdb9de12 2065 else if (mmc->f_max == 0)
d418ed87 2066 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 2067
4dffd7a2 2068 spin_lock_init(&host->irq_lock);
a45c6cb8 2069
9618195e 2070 host->fclk = devm_clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 2071 if (IS_ERR(host->fclk)) {
2072 ret = PTR_ERR(host->fclk);
2073 host->fclk = NULL;
a45c6cb8
MC		 2074 goto err1;
2075 }
2076
9b68256c
PW		 2077 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2078 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
afd8c29d 2079 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
9b68256c 2080 }
dd498eff 2081
5b83b223 2082 device_init_wakeup(&pdev->dev, true);
fa4aa2d4
B		 2083 pm_runtime_enable(host->dev);
2084 pm_runtime_get_sync(host->dev);
2085 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2086 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 2087
92a3aebf
B		 2088 omap_hsmmc_context_save(host);
2089
9618195e 2090 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
cd03d9a8
RN		 2091 /*
2092 * MMC can still work without debounce clock.
2093 */
2094 if (IS_ERR(host->dbclk)) {
cd03d9a8 2095 host->dbclk = NULL;
94c18149 2096 } else if (clk_prepare_enable(host->dbclk) != 0) {
cd03d9a8 2097 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
cd03d9a8 2098 host->dbclk = NULL;
2bec0893 2099 }
a45c6cb8 2100
0ccd76d4
JY		 2101 /* Since we do only SG emulation, we can have as many segs
2102 * as we want. */
a36274e0 2103 mmc->max_segs = 1024;
0ccd76d4 2104
a45c6cb8
MC		 2105 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2106 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2107 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2108 mmc->max_seg_size = mmc->max_req_size;
2109
13189e78 2110 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 2111 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 2112
326119c9 2113 mmc->caps |= mmc_pdata(host)->caps;
3a63833e 2114 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 2115 mmc->caps |= MMC_CAP_4_BIT_DATA;
2116
326119c9 2117 if (mmc_pdata(host)->nonremovable)
23d99bb9
AH		 2118 mmc->caps |= MMC_CAP_NONREMOVABLE;
2119
fdb9de12 2120 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
6fdc75de 2121
70a3341a 2122 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2123
81eef6ca
PU		 2124 host->rx_chan = dma_request_chan(&pdev->dev, "rx");
2125 if (IS_ERR(host->rx_chan)) {
2126 dev_err(mmc_dev(host->mmc), "RX DMA channel request failed\n");
2127 ret = PTR_ERR(host->rx_chan);
26b88520
RK		 2128 goto err_irq;
2129 }
2130
81eef6ca
PU		 2131 host->tx_chan = dma_request_chan(&pdev->dev, "tx");
2132 if (IS_ERR(host->tx_chan)) {
2133 dev_err(mmc_dev(host->mmc), "TX DMA channel request failed\n");
2134 ret = PTR_ERR(host->tx_chan);
26b88520 2135 goto err_irq;
c5c98927 2136 }
a45c6cb8
MC		 2137
2138 /* Request IRQ for MMC operations */
e1538ed7 2139 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 2140 mmc_hostname(mmc), host);
2141 if (ret) {
b1e056ae 2142 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
a45c6cb8
MC		 2143 goto err_irq;
2144 }
2145
987e05c9
KVA		 2146 ret = omap_hsmmc_reg_get(host);
2147 if (ret)
2148 goto err_irq;
db0fefc5 2149
326119c9 2150 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
a45c6cb8 2151
b417577d 2152 omap_hsmmc_disable_irq(host);
a45c6cb8 2153
2cd3a2a5
AF		 2154 /*
2155 * For now, only support SDIO interrupt if we have a separate
2156 * wake-up interrupt configured from device tree. This is because
2157 * the wake-up interrupt is needed for idle state and some
2158 * platforms need special quirks. And we don't want to add new
2159 * legacy mux platform init code callbacks any longer as we
2160 * are moving to DT based booting anyways.
2161 */
2162 ret = omap_hsmmc_configure_wake_irq(host);
2163 if (!ret)
2164 mmc->caps |= MMC_CAP_SDIO_IRQ;
2165
b62f6228
AH		 2166 omap_hsmmc_protect_card(host);
2167
a45c6cb8
MC		 2168 mmc_add_host(mmc);
2169
326119c9 2170 if (mmc_pdata(host)->name != NULL) {
a45c6cb8
MC		 2171 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2172 if (ret < 0)
2173 goto err_slot_name;
2174 }
cde592cb 2175 if (host->get_cover_state) {
a45c6cb8 2176 ret = device_create_file(&mmc->class_dev,
cde592cb 2177 &dev_attr_cover_switch);
a45c6cb8 2178 if (ret < 0)
db0fefc5 2179 goto err_slot_name;
a45c6cb8
MC		 2180 }
2181
70a3341a 2182 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 2183 pm_runtime_mark_last_busy(host->dev);
2184 pm_runtime_put_autosuspend(host->dev);
d900f712 2185
a45c6cb8
MC		 2186 return 0;
2187
a45c6cb8
MC		 2188err_slot_name:
2189 mmc_remove_host(mmc);
a45c6cb8 2190err_irq:
5b83b223 2191 device_init_wakeup(&pdev->dev, false);
81eef6ca 2192 if (!IS_ERR_OR_NULL(host->tx_chan))
c5c98927 2193 dma_release_channel(host->tx_chan);
81eef6ca 2194 if (!IS_ERR_OR_NULL(host->rx_chan))
c5c98927 2195 dma_release_channel(host->rx_chan);
814a3c0c 2196 pm_runtime_dont_use_autosuspend(host->dev);
d59d77ed 2197 pm_runtime_put_sync(host->dev);
37f6190d 2198 pm_runtime_disable(host->dev);
9618195e 2199 if (host->dbclk)
94c18149 2200 clk_disable_unprepare(host->dbclk);
a45c6cb8 2201err1:
1e363e3b 2202err_gpio:
db0fefc5 2203 mmc_free_host(mmc);
a45c6cb8 2204err:
a45c6cb8
MC		 2205 return ret;
2206}
2207
6e0ee714 2208static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2209{
70a3341a 2210 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8 2211
927ce944
FB		 2212 pm_runtime_get_sync(host->dev);
2213 mmc_remove_host(host->mmc);
a45c6cb8 2214
dc28562b
PU		 2215 dma_release_channel(host->tx_chan);
2216 dma_release_channel(host->rx_chan);
c5c98927 2217
814a3c0c 2218 pm_runtime_dont_use_autosuspend(host->dev);
927ce944
FB		 2219 pm_runtime_put_sync(host->dev);
2220 pm_runtime_disable(host->dev);
5b83b223 2221 device_init_wakeup(&pdev->dev, false);
9618195e 2222 if (host->dbclk)
94c18149 2223 clk_disable_unprepare(host->dbclk);
a45c6cb8 2224
9d1f0286 2225 mmc_free_host(host->mmc);
927ce944 2226
a45c6cb8
MC		 2227 return 0;
2228}
2229
3d3bbfbd 2230#ifdef CONFIG_PM_SLEEP
a791daa1 2231static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8 2232{
927ce944 2233 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2234
927ce944 2235 if (!host)
a45c6cb8
MC		 2236 return 0;
2237
927ce944 2238 pm_runtime_get_sync(host->dev);
31f9d463 2239
927ce944 2240 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2cd3a2a5
AF		 2241 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2242 OMAP_HSMMC_WRITE(host->base, IE, 0);
2243 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
927ce944
FB		 2244 OMAP_HSMMC_WRITE(host->base, HCTL,
2245 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2246 }
927ce944 2247
cd03d9a8 2248 if (host->dbclk)
94c18149 2249 clk_disable_unprepare(host->dbclk);
3932afd5 2250
31f9d463 2251 pm_runtime_put_sync(host->dev);
3932afd5 2252 return 0;
a45c6cb8
MC		 2253}
2254
2255/* Routine to resume the MMC device */
a791daa1 2256static int omap_hsmmc_resume(struct device *dev)
a45c6cb8 2257{
927ce944
FB		 2258 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2259
2260 if (!host)
2261 return 0;
a45c6cb8 2262
927ce944 2263 pm_runtime_get_sync(host->dev);
11dd62a7 2264
cd03d9a8 2265 if (host->dbclk)
94c18149 2266 clk_prepare_enable(host->dbclk);
2bec0893 2267
927ce944
FB		 2268 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2269 omap_hsmmc_conf_bus_power(host);
1b331e69 2270
927ce944 2271 omap_hsmmc_protect_card(host);
927ce944
FB		 2272 pm_runtime_mark_last_busy(host->dev);
2273 pm_runtime_put_autosuspend(host->dev);
3932afd5 2274 return 0;
a45c6cb8 2275}
a45c6cb8
MC		 2276#endif
2277
fa4aa2d4
B		 2278static int omap_hsmmc_runtime_suspend(struct device *dev)
2279{
2280 struct omap_hsmmc_host *host;
2cd3a2a5 2281 unsigned long flags;
f945901f 2282 int ret = 0;
fa4aa2d4
B		 2283
2284 host = platform_get_drvdata(to_platform_device(dev));
2285 omap_hsmmc_context_save(host);
927ce944 2286 dev_dbg(dev, "disabled\n");
fa4aa2d4 2287
2cd3a2a5
AF		 2288 spin_lock_irqsave(&host->irq_lock, flags);
2289 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2290 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2291 /* disable sdio irq handling to prevent race */
2292 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2293 OMAP_HSMMC_WRITE(host->base, IE, 0);
f945901f
AF		 2294
2295 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2296 /*
2297 * dat1 line low, pending sdio irq
2298 * race condition: possible irq handler running on
2299 * multi-core, abort
2300 */
2301 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2302 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2303 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2304 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2305 pm_runtime_mark_last_busy(dev);
2306 ret = -EBUSY;
2307 goto abort;
2308 }
2cd3a2a5 2309
97978a44 2310 pinctrl_pm_select_idle_state(dev);
97978a44
AF		 2311 } else {
2312 pinctrl_pm_select_idle_state(dev);
2cd3a2a5 2313 }
97978a44 2314
f945901f 2315abort:
2cd3a2a5 2316 spin_unlock_irqrestore(&host->irq_lock, flags);
f945901f 2317 return ret;
fa4aa2d4
B		 2318}
2319
2320static int omap_hsmmc_runtime_resume(struct device *dev)
2321{
2322 struct omap_hsmmc_host *host;
2cd3a2a5 2323 unsigned long flags;
fa4aa2d4
B		 2324
2325 host = platform_get_drvdata(to_platform_device(dev));
2326 omap_hsmmc_context_restore(host);
927ce944 2327 dev_dbg(dev, "enabled\n");
fa4aa2d4 2328
2cd3a2a5
AF		 2329 spin_lock_irqsave(&host->irq_lock, flags);
2330 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2331 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2cd3a2a5 2332
97978a44
AF		 2333 pinctrl_pm_select_default_state(host->dev);
2334
2335 /* irq lost, if pinmux incorrect */
2cd3a2a5
AF		 2336 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2337 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2338 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
97978a44
AF		 2339 } else {
2340 pinctrl_pm_select_default_state(host->dev);
2cd3a2a5
AF		 2341 }
2342 spin_unlock_irqrestore(&host->irq_lock, flags);
fa4aa2d4
B		 2343 return 0;
2344}
2345
a791daa1 2346static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
3d3bbfbd 2347 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
fa4aa2d4
B		 2348 .runtime_suspend = omap_hsmmc_runtime_suspend,
2349 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2350};
2351
2352static struct platform_driver omap_hsmmc_driver = {
efa25fd3 2353 .probe = omap_hsmmc_probe,
0433c143 2354 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2355 .driver = {
2356 .name = DRIVER_NAME,
a791daa1 2357 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2358 .of_match_table = of_match_ptr(omap_mmc_of_match),
a45c6cb8
MC		 2359 },
2360};
2361
b796450b 2362module_platform_driver(omap_hsmmc_driver);
a45c6cb8
MC		 2363MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2364MODULE_LICENSE("GPL");
2365MODULE_ALIAS("platform:" DRIVER_NAME);
2366MODULE_AUTHOR("Texas Instruments Inc");
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