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Commit | Line | Data |
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a45c6cb8 MC |
1 | /* |
2 | * drivers/mmc/host/omap_hsmmc.c | |
3 | * | |
4 | * Driver for OMAP2430/3430 MMC controller. | |
5 | * | |
6 | * Copyright (C) 2007 Texas Instruments. | |
7 | * | |
8 | * Authors: | |
9 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
10 | * Madhusudhan <madhu.cr@ti.com> | |
11 | * Mohit Jalori <mjalori@ti.com> | |
12 | * | |
13 | * This file is licensed under the terms of the GNU General Public License | |
14 | * version 2. This program is licensed "as is" without any warranty of any | |
15 | * kind, whether express or implied. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
d900f712 DK |
20 | #include <linux/debugfs.h> |
21 | #include <linux/seq_file.h> | |
a45c6cb8 MC |
22 | #include <linux/interrupt.h> |
23 | #include <linux/delay.h> | |
24 | #include <linux/dma-mapping.h> | |
25 | #include <linux/platform_device.h> | |
26 | #include <linux/workqueue.h> | |
27 | #include <linux/timer.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/mmc/host.h> | |
13189e78 | 30 | #include <linux/mmc/core.h> |
a45c6cb8 MC |
31 | #include <linux/io.h> |
32 | #include <linux/semaphore.h> | |
33 | #include <mach/dma.h> | |
34 | #include <mach/hardware.h> | |
35 | #include <mach/board.h> | |
36 | #include <mach/mmc.h> | |
37 | #include <mach/cpu.h> | |
38 | ||
39 | /* OMAP HSMMC Host Controller Registers */ | |
40 | #define OMAP_HSMMC_SYSCONFIG 0x0010 | |
11dd62a7 | 41 | #define OMAP_HSMMC_SYSSTATUS 0x0014 |
a45c6cb8 MC |
42 | #define OMAP_HSMMC_CON 0x002C |
43 | #define OMAP_HSMMC_BLK 0x0104 | |
44 | #define OMAP_HSMMC_ARG 0x0108 | |
45 | #define OMAP_HSMMC_CMD 0x010C | |
46 | #define OMAP_HSMMC_RSP10 0x0110 | |
47 | #define OMAP_HSMMC_RSP32 0x0114 | |
48 | #define OMAP_HSMMC_RSP54 0x0118 | |
49 | #define OMAP_HSMMC_RSP76 0x011C | |
50 | #define OMAP_HSMMC_DATA 0x0120 | |
51 | #define OMAP_HSMMC_HCTL 0x0128 | |
52 | #define OMAP_HSMMC_SYSCTL 0x012C | |
53 | #define OMAP_HSMMC_STAT 0x0130 | |
54 | #define OMAP_HSMMC_IE 0x0134 | |
55 | #define OMAP_HSMMC_ISE 0x0138 | |
56 | #define OMAP_HSMMC_CAPA 0x0140 | |
57 | ||
58 | #define VS18 (1 << 26) | |
59 | #define VS30 (1 << 25) | |
60 | #define SDVS18 (0x5 << 9) | |
61 | #define SDVS30 (0x6 << 9) | |
eb250826 | 62 | #define SDVS33 (0x7 << 9) |
1b331e69 | 63 | #define SDVS_MASK 0x00000E00 |
a45c6cb8 MC |
64 | #define SDVSCLR 0xFFFFF1FF |
65 | #define SDVSDET 0x00000400 | |
66 | #define AUTOIDLE 0x1 | |
67 | #define SDBP (1 << 8) | |
68 | #define DTO 0xe | |
69 | #define ICE 0x1 | |
70 | #define ICS 0x2 | |
71 | #define CEN (1 << 2) | |
72 | #define CLKD_MASK 0x0000FFC0 | |
73 | #define CLKD_SHIFT 6 | |
74 | #define DTO_MASK 0x000F0000 | |
75 | #define DTO_SHIFT 16 | |
76 | #define INT_EN_MASK 0x307F0033 | |
ccdfe3a6 AG |
77 | #define BWR_ENABLE (1 << 4) |
78 | #define BRR_ENABLE (1 << 5) | |
a45c6cb8 MC |
79 | #define INIT_STREAM (1 << 1) |
80 | #define DP_SELECT (1 << 21) | |
81 | #define DDIR (1 << 4) | |
82 | #define DMA_EN 0x1 | |
83 | #define MSBS (1 << 5) | |
84 | #define BCE (1 << 1) | |
85 | #define FOUR_BIT (1 << 1) | |
73153010 | 86 | #define DW8 (1 << 5) |
a45c6cb8 MC |
87 | #define CC 0x1 |
88 | #define TC 0x02 | |
89 | #define OD 0x1 | |
90 | #define ERR (1 << 15) | |
91 | #define CMD_TIMEOUT (1 << 16) | |
92 | #define DATA_TIMEOUT (1 << 20) | |
93 | #define CMD_CRC (1 << 17) | |
94 | #define DATA_CRC (1 << 21) | |
95 | #define CARD_ERR (1 << 28) | |
96 | #define STAT_CLEAR 0xFFFFFFFF | |
97 | #define INIT_STREAM_CMD 0x00000000 | |
98 | #define DUAL_VOLT_OCR_BIT 7 | |
99 | #define SRC (1 << 25) | |
100 | #define SRD (1 << 26) | |
11dd62a7 DK |
101 | #define SOFTRESET (1 << 1) |
102 | #define RESETDONE (1 << 0) | |
a45c6cb8 MC |
103 | |
104 | /* | |
105 | * FIXME: Most likely all the data using these _DEVID defines should come | |
106 | * from the platform_data, or implemented in controller and slot specific | |
107 | * functions. | |
108 | */ | |
109 | #define OMAP_MMC1_DEVID 0 | |
110 | #define OMAP_MMC2_DEVID 1 | |
f3e2f1dd | 111 | #define OMAP_MMC3_DEVID 2 |
a45c6cb8 | 112 | |
a45c6cb8 MC |
113 | #define MMC_TIMEOUT_MS 20 |
114 | #define OMAP_MMC_MASTER_CLOCK 96000000 | |
115 | #define DRIVER_NAME "mmci-omap-hs" | |
116 | ||
dd498eff DK |
117 | /* Timeouts for entering power saving states on inactivity, msec */ |
118 | #define OMAP_MMC_DISABLED_TIMEOUT 100 | |
13189e78 JL |
119 | #define OMAP_MMC_SLEEP_TIMEOUT 1000 |
120 | #define OMAP_MMC_OFF_TIMEOUT 8000 | |
dd498eff | 121 | |
a45c6cb8 MC |
122 | /* |
123 | * One controller can have multiple slots, like on some omap boards using | |
124 | * omap.c controller driver. Luckily this is not currently done on any known | |
125 | * omap_hsmmc.c device. | |
126 | */ | |
127 | #define mmc_slot(host) (host->pdata->slots[host->slot_id]) | |
128 | ||
129 | /* | |
130 | * MMC Host controller read/write API's | |
131 | */ | |
132 | #define OMAP_HSMMC_READ(base, reg) \ | |
133 | __raw_readl((base) + OMAP_HSMMC_##reg) | |
134 | ||
135 | #define OMAP_HSMMC_WRITE(base, reg, val) \ | |
136 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) | |
137 | ||
70a3341a | 138 | struct omap_hsmmc_host { |
a45c6cb8 MC |
139 | struct device *dev; |
140 | struct mmc_host *mmc; | |
141 | struct mmc_request *mrq; | |
142 | struct mmc_command *cmd; | |
143 | struct mmc_data *data; | |
144 | struct clk *fclk; | |
145 | struct clk *iclk; | |
146 | struct clk *dbclk; | |
147 | struct semaphore sem; | |
148 | struct work_struct mmc_carddetect_work; | |
149 | void __iomem *base; | |
150 | resource_size_t mapbase; | |
4dffd7a2 AH |
151 | spinlock_t irq_lock; /* Prevent races with irq handler */ |
152 | unsigned long flags; | |
a45c6cb8 MC |
153 | unsigned int id; |
154 | unsigned int dma_len; | |
0ccd76d4 | 155 | unsigned int dma_sg_idx; |
a45c6cb8 | 156 | unsigned char bus_mode; |
a3621465 | 157 | unsigned char power_mode; |
a45c6cb8 MC |
158 | u32 *buffer; |
159 | u32 bytesleft; | |
160 | int suspended; | |
161 | int irq; | |
a45c6cb8 | 162 | int use_dma, dma_ch; |
f3e2f1dd | 163 | int dma_line_tx, dma_line_rx; |
a45c6cb8 MC |
164 | int slot_id; |
165 | int dbclk_enabled; | |
4a694dc9 | 166 | int response_busy; |
11dd62a7 | 167 | int context_loss; |
dd498eff | 168 | int dpm_state; |
623821f7 | 169 | int vdd; |
11dd62a7 | 170 | |
a45c6cb8 MC |
171 | struct omap_mmc_platform_data *pdata; |
172 | }; | |
173 | ||
174 | /* | |
175 | * Stop clock to the card | |
176 | */ | |
70a3341a | 177 | static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
178 | { |
179 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
180 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
181 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) | |
182 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); | |
183 | } | |
184 | ||
11dd62a7 DK |
185 | #ifdef CONFIG_PM |
186 | ||
187 | /* | |
188 | * Restore the MMC host context, if it was lost as result of a | |
189 | * power state change. | |
190 | */ | |
70a3341a | 191 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
192 | { |
193 | struct mmc_ios *ios = &host->mmc->ios; | |
194 | struct omap_mmc_platform_data *pdata = host->pdata; | |
195 | int context_loss = 0; | |
196 | u32 hctl, capa, con; | |
197 | u16 dsor = 0; | |
198 | unsigned long timeout; | |
199 | ||
200 | if (pdata->get_context_loss_count) { | |
201 | context_loss = pdata->get_context_loss_count(host->dev); | |
202 | if (context_loss < 0) | |
203 | return 1; | |
204 | } | |
205 | ||
206 | dev_dbg(mmc_dev(host->mmc), "context was %slost\n", | |
207 | context_loss == host->context_loss ? "not " : ""); | |
208 | if (host->context_loss == context_loss) | |
209 | return 1; | |
210 | ||
211 | /* Wait for hardware reset */ | |
212 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
213 | while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE | |
214 | && time_before(jiffies, timeout)) | |
215 | ; | |
216 | ||
217 | /* Do software reset */ | |
218 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); | |
219 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
220 | while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE | |
221 | && time_before(jiffies, timeout)) | |
222 | ; | |
223 | ||
224 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, | |
225 | OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); | |
226 | ||
227 | if (host->id == OMAP_MMC1_DEVID) { | |
228 | if (host->power_mode != MMC_POWER_OFF && | |
229 | (1 << ios->vdd) <= MMC_VDD_23_24) | |
230 | hctl = SDVS18; | |
231 | else | |
232 | hctl = SDVS30; | |
233 | capa = VS30 | VS18; | |
234 | } else { | |
235 | hctl = SDVS18; | |
236 | capa = VS18; | |
237 | } | |
238 | ||
239 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
240 | OMAP_HSMMC_READ(host->base, HCTL) | hctl); | |
241 | ||
242 | OMAP_HSMMC_WRITE(host->base, CAPA, | |
243 | OMAP_HSMMC_READ(host->base, CAPA) | capa); | |
244 | ||
245 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
246 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
247 | ||
248 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
249 | while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP | |
250 | && time_before(jiffies, timeout)) | |
251 | ; | |
252 | ||
253 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
254 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
255 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
256 | ||
257 | /* Do not initialize card-specific things if the power is off */ | |
258 | if (host->power_mode == MMC_POWER_OFF) | |
259 | goto out; | |
260 | ||
261 | con = OMAP_HSMMC_READ(host->base, CON); | |
262 | switch (ios->bus_width) { | |
263 | case MMC_BUS_WIDTH_8: | |
264 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
265 | break; | |
266 | case MMC_BUS_WIDTH_4: | |
267 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
268 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
269 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
270 | break; | |
271 | case MMC_BUS_WIDTH_1: | |
272 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
273 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
274 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
275 | break; | |
276 | } | |
277 | ||
278 | if (ios->clock) { | |
279 | dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; | |
280 | if (dsor < 1) | |
281 | dsor = 1; | |
282 | ||
283 | if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) | |
284 | dsor++; | |
285 | ||
286 | if (dsor > 250) | |
287 | dsor = 250; | |
288 | } | |
289 | ||
290 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
291 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
292 | OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); | |
293 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
294 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
295 | ||
296 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
297 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS | |
298 | && time_before(jiffies, timeout)) | |
299 | ; | |
300 | ||
301 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
302 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
303 | ||
304 | con = OMAP_HSMMC_READ(host->base, CON); | |
305 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
306 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); | |
307 | else | |
308 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
309 | out: | |
310 | host->context_loss = context_loss; | |
311 | ||
312 | dev_dbg(mmc_dev(host->mmc), "context is restored\n"); | |
313 | return 0; | |
314 | } | |
315 | ||
316 | /* | |
317 | * Save the MMC host context (store the number of power state changes so far). | |
318 | */ | |
70a3341a | 319 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
320 | { |
321 | struct omap_mmc_platform_data *pdata = host->pdata; | |
322 | int context_loss; | |
323 | ||
324 | if (pdata->get_context_loss_count) { | |
325 | context_loss = pdata->get_context_loss_count(host->dev); | |
326 | if (context_loss < 0) | |
327 | return; | |
328 | host->context_loss = context_loss; | |
329 | } | |
330 | } | |
331 | ||
332 | #else | |
333 | ||
70a3341a | 334 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
335 | { |
336 | return 0; | |
337 | } | |
338 | ||
70a3341a | 339 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
340 | { |
341 | } | |
342 | ||
343 | #endif | |
344 | ||
a45c6cb8 MC |
345 | /* |
346 | * Send init stream sequence to card | |
347 | * before sending IDLE command | |
348 | */ | |
70a3341a | 349 | static void send_init_stream(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
350 | { |
351 | int reg = 0; | |
352 | unsigned long timeout; | |
353 | ||
354 | disable_irq(host->irq); | |
355 | OMAP_HSMMC_WRITE(host->base, CON, | |
356 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); | |
357 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); | |
358 | ||
359 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
360 | while ((reg != CC) && time_before(jiffies, timeout)) | |
361 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC; | |
362 | ||
363 | OMAP_HSMMC_WRITE(host->base, CON, | |
364 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); | |
c653a6d4 AH |
365 | |
366 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
367 | OMAP_HSMMC_READ(host->base, STAT); | |
368 | ||
a45c6cb8 MC |
369 | enable_irq(host->irq); |
370 | } | |
371 | ||
372 | static inline | |
70a3341a | 373 | int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
374 | { |
375 | int r = 1; | |
376 | ||
191d1f1d DK |
377 | if (mmc_slot(host).get_cover_state) |
378 | r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); | |
a45c6cb8 MC |
379 | return r; |
380 | } | |
381 | ||
382 | static ssize_t | |
70a3341a | 383 | omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
384 | char *buf) |
385 | { | |
386 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 387 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 388 | |
70a3341a DK |
389 | return sprintf(buf, "%s\n", |
390 | omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); | |
a45c6cb8 MC |
391 | } |
392 | ||
70a3341a | 393 | static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); |
a45c6cb8 MC |
394 | |
395 | static ssize_t | |
70a3341a | 396 | omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
397 | char *buf) |
398 | { | |
399 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 400 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 401 | |
191d1f1d | 402 | return sprintf(buf, "%s\n", mmc_slot(host).name); |
a45c6cb8 MC |
403 | } |
404 | ||
70a3341a | 405 | static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); |
a45c6cb8 MC |
406 | |
407 | /* | |
408 | * Configure the response type and send the cmd. | |
409 | */ | |
410 | static void | |
70a3341a | 411 | omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, |
a45c6cb8 MC |
412 | struct mmc_data *data) |
413 | { | |
414 | int cmdreg = 0, resptype = 0, cmdtype = 0; | |
415 | ||
416 | dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", | |
417 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); | |
418 | host->cmd = cmd; | |
419 | ||
420 | /* | |
421 | * Clear status bits and enable interrupts | |
422 | */ | |
423 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
424 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
ccdfe3a6 AG |
425 | |
426 | if (host->use_dma) | |
427 | OMAP_HSMMC_WRITE(host->base, IE, | |
428 | INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE)); | |
429 | else | |
430 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
a45c6cb8 | 431 | |
4a694dc9 | 432 | host->response_busy = 0; |
a45c6cb8 MC |
433 | if (cmd->flags & MMC_RSP_PRESENT) { |
434 | if (cmd->flags & MMC_RSP_136) | |
435 | resptype = 1; | |
4a694dc9 AH |
436 | else if (cmd->flags & MMC_RSP_BUSY) { |
437 | resptype = 3; | |
438 | host->response_busy = 1; | |
439 | } else | |
a45c6cb8 MC |
440 | resptype = 2; |
441 | } | |
442 | ||
443 | /* | |
444 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on | |
445 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need | |
446 | * a val of 0x3, rest 0x0. | |
447 | */ | |
448 | if (cmd == host->mrq->stop) | |
449 | cmdtype = 0x3; | |
450 | ||
451 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); | |
452 | ||
453 | if (data) { | |
454 | cmdreg |= DP_SELECT | MSBS | BCE; | |
455 | if (data->flags & MMC_DATA_READ) | |
456 | cmdreg |= DDIR; | |
457 | else | |
458 | cmdreg &= ~(DDIR); | |
459 | } | |
460 | ||
461 | if (host->use_dma) | |
462 | cmdreg |= DMA_EN; | |
463 | ||
4dffd7a2 AH |
464 | /* |
465 | * In an interrupt context (i.e. STOP command), the spinlock is unlocked | |
466 | * by the interrupt handler, otherwise (i.e. for a new request) it is | |
467 | * unlocked here. | |
468 | */ | |
469 | if (!in_interrupt()) | |
470 | spin_unlock_irqrestore(&host->irq_lock, host->flags); | |
471 | ||
a45c6cb8 MC |
472 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); |
473 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); | |
474 | } | |
475 | ||
0ccd76d4 | 476 | static int |
70a3341a | 477 | omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) |
0ccd76d4 JY |
478 | { |
479 | if (data->flags & MMC_DATA_WRITE) | |
480 | return DMA_TO_DEVICE; | |
481 | else | |
482 | return DMA_FROM_DEVICE; | |
483 | } | |
484 | ||
a45c6cb8 MC |
485 | /* |
486 | * Notify the transfer complete to MMC core | |
487 | */ | |
488 | static void | |
70a3341a | 489 | omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) |
a45c6cb8 | 490 | { |
4a694dc9 AH |
491 | if (!data) { |
492 | struct mmc_request *mrq = host->mrq; | |
493 | ||
23050103 AH |
494 | /* TC before CC from CMD6 - don't know why, but it happens */ |
495 | if (host->cmd && host->cmd->opcode == 6 && | |
496 | host->response_busy) { | |
497 | host->response_busy = 0; | |
498 | return; | |
499 | } | |
500 | ||
4a694dc9 | 501 | host->mrq = NULL; |
4a694dc9 AH |
502 | mmc_request_done(host->mmc, mrq); |
503 | return; | |
504 | } | |
505 | ||
a45c6cb8 MC |
506 | host->data = NULL; |
507 | ||
508 | if (host->use_dma && host->dma_ch != -1) | |
509 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, | |
70a3341a | 510 | omap_hsmmc_get_dma_dir(host, data)); |
a45c6cb8 MC |
511 | |
512 | if (!data->error) | |
513 | data->bytes_xfered += data->blocks * (data->blksz); | |
514 | else | |
515 | data->bytes_xfered = 0; | |
516 | ||
517 | if (!data->stop) { | |
518 | host->mrq = NULL; | |
519 | mmc_request_done(host->mmc, data->mrq); | |
520 | return; | |
521 | } | |
70a3341a | 522 | omap_hsmmc_start_command(host, data->stop, NULL); |
a45c6cb8 MC |
523 | } |
524 | ||
525 | /* | |
526 | * Notify the core about command completion | |
527 | */ | |
528 | static void | |
70a3341a | 529 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) |
a45c6cb8 MC |
530 | { |
531 | host->cmd = NULL; | |
532 | ||
533 | if (cmd->flags & MMC_RSP_PRESENT) { | |
534 | if (cmd->flags & MMC_RSP_136) { | |
535 | /* response type 2 */ | |
536 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); | |
537 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); | |
538 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); | |
539 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); | |
540 | } else { | |
541 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
542 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); | |
543 | } | |
544 | } | |
4a694dc9 | 545 | if ((host->data == NULL && !host->response_busy) || cmd->error) { |
a45c6cb8 MC |
546 | host->mrq = NULL; |
547 | mmc_request_done(host->mmc, cmd->mrq); | |
548 | } | |
549 | } | |
550 | ||
551 | /* | |
552 | * DMA clean up for command errors | |
553 | */ | |
70a3341a | 554 | static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) |
a45c6cb8 | 555 | { |
82788ff5 | 556 | host->data->error = errno; |
a45c6cb8 MC |
557 | |
558 | if (host->use_dma && host->dma_ch != -1) { | |
559 | dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, | |
70a3341a | 560 | omap_hsmmc_get_dma_dir(host, host->data)); |
a45c6cb8 MC |
561 | omap_free_dma(host->dma_ch); |
562 | host->dma_ch = -1; | |
563 | up(&host->sem); | |
564 | } | |
565 | host->data = NULL; | |
a45c6cb8 MC |
566 | } |
567 | ||
568 | /* | |
569 | * Readable error output | |
570 | */ | |
571 | #ifdef CONFIG_MMC_DEBUG | |
70a3341a | 572 | static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status) |
a45c6cb8 MC |
573 | { |
574 | /* --- means reserved bit without definition at documentation */ | |
70a3341a | 575 | static const char *omap_hsmmc_status_bits[] = { |
a45c6cb8 MC |
576 | "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", |
577 | "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", | |
578 | "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", | |
579 | "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" | |
580 | }; | |
581 | char res[256]; | |
582 | char *buf = res; | |
583 | int len, i; | |
584 | ||
585 | len = sprintf(buf, "MMC IRQ 0x%x :", status); | |
586 | buf += len; | |
587 | ||
70a3341a | 588 | for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) |
a45c6cb8 | 589 | if (status & (1 << i)) { |
70a3341a | 590 | len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); |
a45c6cb8 MC |
591 | buf += len; |
592 | } | |
593 | ||
594 | dev_dbg(mmc_dev(host->mmc), "%s\n", res); | |
595 | } | |
596 | #endif /* CONFIG_MMC_DEBUG */ | |
597 | ||
3ebf74b1 JP |
598 | /* |
599 | * MMC controller internal state machines reset | |
600 | * | |
601 | * Used to reset command or data internal state machines, using respectively | |
602 | * SRC or SRD bit of SYSCTL register | |
603 | * Can be called from interrupt context | |
604 | */ | |
70a3341a DK |
605 | static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, |
606 | unsigned long bit) | |
3ebf74b1 JP |
607 | { |
608 | unsigned long i = 0; | |
609 | unsigned long limit = (loops_per_jiffy * | |
610 | msecs_to_jiffies(MMC_TIMEOUT_MS)); | |
611 | ||
612 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
613 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); | |
614 | ||
615 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && | |
616 | (i++ < limit)) | |
617 | cpu_relax(); | |
618 | ||
619 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) | |
620 | dev_err(mmc_dev(host->mmc), | |
621 | "Timeout waiting on controller reset in %s\n", | |
622 | __func__); | |
623 | } | |
a45c6cb8 MC |
624 | |
625 | /* | |
626 | * MMC controller IRQ handler | |
627 | */ | |
70a3341a | 628 | static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) |
a45c6cb8 | 629 | { |
70a3341a | 630 | struct omap_hsmmc_host *host = dev_id; |
a45c6cb8 MC |
631 | struct mmc_data *data; |
632 | int end_cmd = 0, end_trans = 0, status; | |
633 | ||
4dffd7a2 AH |
634 | spin_lock(&host->irq_lock); |
635 | ||
4a694dc9 | 636 | if (host->mrq == NULL) { |
a45c6cb8 MC |
637 | OMAP_HSMMC_WRITE(host->base, STAT, |
638 | OMAP_HSMMC_READ(host->base, STAT)); | |
00adadc1 KH |
639 | /* Flush posted write */ |
640 | OMAP_HSMMC_READ(host->base, STAT); | |
4dffd7a2 | 641 | spin_unlock(&host->irq_lock); |
a45c6cb8 MC |
642 | return IRQ_HANDLED; |
643 | } | |
644 | ||
645 | data = host->data; | |
646 | status = OMAP_HSMMC_READ(host->base, STAT); | |
647 | dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); | |
648 | ||
649 | if (status & ERR) { | |
650 | #ifdef CONFIG_MMC_DEBUG | |
70a3341a | 651 | omap_hsmmc_report_irq(host, status); |
a45c6cb8 MC |
652 | #endif |
653 | if ((status & CMD_TIMEOUT) || | |
654 | (status & CMD_CRC)) { | |
655 | if (host->cmd) { | |
656 | if (status & CMD_TIMEOUT) { | |
70a3341a DK |
657 | omap_hsmmc_reset_controller_fsm(host, |
658 | SRC); | |
a45c6cb8 MC |
659 | host->cmd->error = -ETIMEDOUT; |
660 | } else { | |
661 | host->cmd->error = -EILSEQ; | |
662 | } | |
663 | end_cmd = 1; | |
664 | } | |
4a694dc9 AH |
665 | if (host->data || host->response_busy) { |
666 | if (host->data) | |
70a3341a DK |
667 | omap_hsmmc_dma_cleanup(host, |
668 | -ETIMEDOUT); | |
4a694dc9 | 669 | host->response_busy = 0; |
70a3341a | 670 | omap_hsmmc_reset_controller_fsm(host, SRD); |
c232f457 | 671 | } |
a45c6cb8 MC |
672 | } |
673 | if ((status & DATA_TIMEOUT) || | |
674 | (status & DATA_CRC)) { | |
4a694dc9 AH |
675 | if (host->data || host->response_busy) { |
676 | int err = (status & DATA_TIMEOUT) ? | |
677 | -ETIMEDOUT : -EILSEQ; | |
678 | ||
679 | if (host->data) | |
70a3341a | 680 | omap_hsmmc_dma_cleanup(host, err); |
a45c6cb8 | 681 | else |
4a694dc9 AH |
682 | host->mrq->cmd->error = err; |
683 | host->response_busy = 0; | |
70a3341a | 684 | omap_hsmmc_reset_controller_fsm(host, SRD); |
a45c6cb8 MC |
685 | end_trans = 1; |
686 | } | |
687 | } | |
688 | if (status & CARD_ERR) { | |
689 | dev_dbg(mmc_dev(host->mmc), | |
690 | "Ignoring card err CMD%d\n", host->cmd->opcode); | |
691 | if (host->cmd) | |
692 | end_cmd = 1; | |
693 | if (host->data) | |
694 | end_trans = 1; | |
695 | } | |
696 | } | |
697 | ||
698 | OMAP_HSMMC_WRITE(host->base, STAT, status); | |
00adadc1 KH |
699 | /* Flush posted write */ |
700 | OMAP_HSMMC_READ(host->base, STAT); | |
a45c6cb8 | 701 | |
a8fe29d8 | 702 | if (end_cmd || ((status & CC) && host->cmd)) |
70a3341a | 703 | omap_hsmmc_cmd_done(host, host->cmd); |
0a40e647 | 704 | if ((end_trans || (status & TC)) && host->mrq) |
70a3341a | 705 | omap_hsmmc_xfer_done(host, data); |
a45c6cb8 | 706 | |
4dffd7a2 AH |
707 | spin_unlock(&host->irq_lock); |
708 | ||
a45c6cb8 MC |
709 | return IRQ_HANDLED; |
710 | } | |
711 | ||
70a3341a | 712 | static void set_sd_bus_power(struct omap_hsmmc_host *host) |
e13bb300 AH |
713 | { |
714 | unsigned long i; | |
715 | ||
716 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
717 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
718 | for (i = 0; i < loops_per_jiffy; i++) { | |
719 | if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) | |
720 | break; | |
721 | cpu_relax(); | |
722 | } | |
723 | } | |
724 | ||
a45c6cb8 | 725 | /* |
eb250826 DB |
726 | * Switch MMC interface voltage ... only relevant for MMC1. |
727 | * | |
728 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. | |
729 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. | |
730 | * Some chips, like eMMC ones, use internal transceivers. | |
a45c6cb8 | 731 | */ |
70a3341a | 732 | static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) |
a45c6cb8 MC |
733 | { |
734 | u32 reg_val = 0; | |
735 | int ret; | |
736 | ||
737 | /* Disable the clocks */ | |
738 | clk_disable(host->fclk); | |
739 | clk_disable(host->iclk); | |
740 | clk_disable(host->dbclk); | |
741 | ||
742 | /* Turn the power off */ | |
743 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); | |
744 | if (ret != 0) | |
745 | goto err; | |
746 | ||
747 | /* Turn the power ON with given VDD 1.8 or 3.0v */ | |
748 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); | |
749 | if (ret != 0) | |
750 | goto err; | |
751 | ||
752 | clk_enable(host->fclk); | |
753 | clk_enable(host->iclk); | |
754 | clk_enable(host->dbclk); | |
755 | ||
756 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
757 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); | |
758 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); | |
eb250826 | 759 | |
a45c6cb8 MC |
760 | /* |
761 | * If a MMC dual voltage card is detected, the set_ios fn calls | |
762 | * this fn with VDD bit set for 1.8V. Upon card removal from the | |
70a3341a | 763 | * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. |
a45c6cb8 | 764 | * |
eb250826 DB |
765 | * Cope with a bit of slop in the range ... per data sheets: |
766 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, | |
767 | * but recommended values are 1.71V to 1.89V | |
768 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, | |
769 | * but recommended values are 2.7V to 3.3V | |
770 | * | |
771 | * Board setup code shouldn't permit anything very out-of-range. | |
772 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the | |
773 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. | |
a45c6cb8 | 774 | */ |
eb250826 | 775 | if ((1 << vdd) <= MMC_VDD_23_24) |
a45c6cb8 | 776 | reg_val |= SDVS18; |
eb250826 DB |
777 | else |
778 | reg_val |= SDVS30; | |
a45c6cb8 MC |
779 | |
780 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); | |
e13bb300 | 781 | set_sd_bus_power(host); |
a45c6cb8 MC |
782 | |
783 | return 0; | |
784 | err: | |
785 | dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); | |
786 | return ret; | |
787 | } | |
788 | ||
789 | /* | |
790 | * Work Item to notify the core about card insertion/removal | |
791 | */ | |
70a3341a | 792 | static void omap_hsmmc_detect(struct work_struct *work) |
a45c6cb8 | 793 | { |
70a3341a DK |
794 | struct omap_hsmmc_host *host = |
795 | container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); | |
249d0fa9 | 796 | struct omap_mmc_slot_data *slot = &mmc_slot(host); |
a6b2240d AH |
797 | int carddetect; |
798 | ||
799 | if (host->suspended) | |
800 | return; | |
801 | ||
802 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); | |
249d0fa9 | 803 | |
191d1f1d | 804 | if (slot->card_detect) |
a6b2240d | 805 | carddetect = slot->card_detect(slot->card_detect_irq); |
e1a55f5e | 806 | else |
a6b2240d | 807 | carddetect = -ENOSYS; |
a45c6cb8 | 808 | |
a6b2240d | 809 | if (carddetect) { |
a45c6cb8 MC |
810 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); |
811 | } else { | |
5e2ea617 | 812 | mmc_host_enable(host->mmc); |
70a3341a | 813 | omap_hsmmc_reset_controller_fsm(host, SRD); |
5e2ea617 | 814 | mmc_host_lazy_disable(host->mmc); |
70a3341a | 815 | |
a45c6cb8 MC |
816 | mmc_detect_change(host->mmc, (HZ * 50) / 1000); |
817 | } | |
818 | } | |
819 | ||
820 | /* | |
821 | * ISR for handling card insertion and removal | |
822 | */ | |
70a3341a | 823 | static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) |
a45c6cb8 | 824 | { |
70a3341a | 825 | struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; |
a45c6cb8 | 826 | |
a6b2240d AH |
827 | if (host->suspended) |
828 | return IRQ_HANDLED; | |
a45c6cb8 MC |
829 | schedule_work(&host->mmc_carddetect_work); |
830 | ||
831 | return IRQ_HANDLED; | |
832 | } | |
833 | ||
70a3341a | 834 | static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, |
0ccd76d4 JY |
835 | struct mmc_data *data) |
836 | { | |
837 | int sync_dev; | |
838 | ||
f3e2f1dd GI |
839 | if (data->flags & MMC_DATA_WRITE) |
840 | sync_dev = host->dma_line_tx; | |
841 | else | |
842 | sync_dev = host->dma_line_rx; | |
0ccd76d4 JY |
843 | return sync_dev; |
844 | } | |
845 | ||
70a3341a | 846 | static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, |
0ccd76d4 JY |
847 | struct mmc_data *data, |
848 | struct scatterlist *sgl) | |
849 | { | |
850 | int blksz, nblk, dma_ch; | |
851 | ||
852 | dma_ch = host->dma_ch; | |
853 | if (data->flags & MMC_DATA_WRITE) { | |
854 | omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
855 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); | |
856 | omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, | |
857 | sg_dma_address(sgl), 0, 0); | |
858 | } else { | |
859 | omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, | |
191d1f1d | 860 | (host->mapbase + OMAP_HSMMC_DATA), 0, 0); |
0ccd76d4 JY |
861 | omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, |
862 | sg_dma_address(sgl), 0, 0); | |
863 | } | |
864 | ||
865 | blksz = host->data->blksz; | |
866 | nblk = sg_dma_len(sgl) / blksz; | |
867 | ||
868 | omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, | |
869 | blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, | |
70a3341a | 870 | omap_hsmmc_get_dma_sync_dev(host, data), |
0ccd76d4 JY |
871 | !(data->flags & MMC_DATA_WRITE)); |
872 | ||
873 | omap_start_dma(dma_ch); | |
874 | } | |
875 | ||
a45c6cb8 MC |
876 | /* |
877 | * DMA call back function | |
878 | */ | |
70a3341a | 879 | static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data) |
a45c6cb8 | 880 | { |
70a3341a | 881 | struct omap_hsmmc_host *host = data; |
a45c6cb8 MC |
882 | |
883 | if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ) | |
884 | dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n"); | |
885 | ||
886 | if (host->dma_ch < 0) | |
887 | return; | |
888 | ||
0ccd76d4 JY |
889 | host->dma_sg_idx++; |
890 | if (host->dma_sg_idx < host->dma_len) { | |
891 | /* Fire up the next transfer. */ | |
70a3341a | 892 | omap_hsmmc_config_dma_params(host, host->data, |
0ccd76d4 JY |
893 | host->data->sg + host->dma_sg_idx); |
894 | return; | |
895 | } | |
896 | ||
a45c6cb8 MC |
897 | omap_free_dma(host->dma_ch); |
898 | host->dma_ch = -1; | |
899 | /* | |
900 | * DMA Callback: run in interrupt context. | |
85b84322 | 901 | * mutex_unlock will throw a kernel warning if used. |
a45c6cb8 MC |
902 | */ |
903 | up(&host->sem); | |
904 | } | |
905 | ||
a45c6cb8 MC |
906 | /* |
907 | * Routine to configure and start DMA for the MMC card | |
908 | */ | |
70a3341a DK |
909 | static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, |
910 | struct mmc_request *req) | |
a45c6cb8 | 911 | { |
0ccd76d4 | 912 | int dma_ch = 0, ret = 0, err = 1, i; |
a45c6cb8 MC |
913 | struct mmc_data *data = req->data; |
914 | ||
0ccd76d4 | 915 | /* Sanity check: all the SG entries must be aligned by block size. */ |
a3f406f8 | 916 | for (i = 0; i < data->sg_len; i++) { |
0ccd76d4 JY |
917 | struct scatterlist *sgl; |
918 | ||
919 | sgl = data->sg + i; | |
920 | if (sgl->length % data->blksz) | |
921 | return -EINVAL; | |
922 | } | |
923 | if ((data->blksz % 4) != 0) | |
924 | /* REVISIT: The MMC buffer increments only when MSB is written. | |
925 | * Return error for blksz which is non multiple of four. | |
926 | */ | |
927 | return -EINVAL; | |
928 | ||
a45c6cb8 MC |
929 | /* |
930 | * If for some reason the DMA transfer is still active, | |
931 | * we wait for timeout period and free the dma | |
932 | */ | |
933 | if (host->dma_ch != -1) { | |
934 | set_current_state(TASK_UNINTERRUPTIBLE); | |
935 | schedule_timeout(100); | |
936 | if (down_trylock(&host->sem)) { | |
937 | omap_free_dma(host->dma_ch); | |
938 | host->dma_ch = -1; | |
939 | up(&host->sem); | |
940 | return err; | |
941 | } | |
942 | } else { | |
943 | if (down_trylock(&host->sem)) | |
944 | return err; | |
945 | } | |
946 | ||
70a3341a DK |
947 | ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), |
948 | "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); | |
a45c6cb8 | 949 | if (ret != 0) { |
0ccd76d4 | 950 | dev_err(mmc_dev(host->mmc), |
a45c6cb8 MC |
951 | "%s: omap_request_dma() failed with %d\n", |
952 | mmc_hostname(host->mmc), ret); | |
953 | return ret; | |
954 | } | |
955 | ||
956 | host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, | |
70a3341a | 957 | data->sg_len, omap_hsmmc_get_dma_dir(host, data)); |
a45c6cb8 | 958 | host->dma_ch = dma_ch; |
0ccd76d4 | 959 | host->dma_sg_idx = 0; |
a45c6cb8 | 960 | |
70a3341a | 961 | omap_hsmmc_config_dma_params(host, data, data->sg); |
a45c6cb8 | 962 | |
a45c6cb8 MC |
963 | return 0; |
964 | } | |
965 | ||
70a3341a | 966 | static void set_data_timeout(struct omap_hsmmc_host *host, |
a45c6cb8 MC |
967 | struct mmc_request *req) |
968 | { | |
969 | unsigned int timeout, cycle_ns; | |
970 | uint32_t reg, clkd, dto = 0; | |
971 | ||
972 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); | |
973 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; | |
974 | if (clkd == 0) | |
975 | clkd = 1; | |
976 | ||
977 | cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); | |
978 | timeout = req->data->timeout_ns / cycle_ns; | |
979 | timeout += req->data->timeout_clks; | |
980 | if (timeout) { | |
981 | while ((timeout & 0x80000000) == 0) { | |
982 | dto += 1; | |
983 | timeout <<= 1; | |
984 | } | |
985 | dto = 31 - dto; | |
986 | timeout <<= 1; | |
987 | if (timeout && dto) | |
988 | dto += 1; | |
989 | if (dto >= 13) | |
990 | dto -= 13; | |
991 | else | |
992 | dto = 0; | |
993 | if (dto > 14) | |
994 | dto = 14; | |
995 | } | |
996 | ||
997 | reg &= ~DTO_MASK; | |
998 | reg |= dto << DTO_SHIFT; | |
999 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); | |
1000 | } | |
1001 | ||
1002 | /* | |
1003 | * Configure block length for MMC/SD cards and initiate the transfer. | |
1004 | */ | |
1005 | static int | |
70a3341a | 1006 | omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) |
a45c6cb8 MC |
1007 | { |
1008 | int ret; | |
1009 | host->data = req->data; | |
1010 | ||
1011 | if (req->data == NULL) { | |
a45c6cb8 MC |
1012 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
1013 | return 0; | |
1014 | } | |
1015 | ||
1016 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) | |
1017 | | (req->data->blocks << 16)); | |
1018 | set_data_timeout(host, req); | |
1019 | ||
a45c6cb8 | 1020 | if (host->use_dma) { |
70a3341a | 1021 | ret = omap_hsmmc_start_dma_transfer(host, req); |
a45c6cb8 MC |
1022 | if (ret != 0) { |
1023 | dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); | |
1024 | return ret; | |
1025 | } | |
1026 | } | |
1027 | return 0; | |
1028 | } | |
1029 | ||
1030 | /* | |
1031 | * Request function. for read/write operation | |
1032 | */ | |
70a3341a | 1033 | static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) |
a45c6cb8 | 1034 | { |
70a3341a | 1035 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3f406f8 | 1036 | int err; |
a45c6cb8 | 1037 | |
4dffd7a2 AH |
1038 | /* |
1039 | * Prevent races with the interrupt handler because of unexpected | |
1040 | * interrupts, but not if we are already in interrupt context i.e. | |
1041 | * retries. | |
1042 | */ | |
1043 | if (!in_interrupt()) | |
1044 | spin_lock_irqsave(&host->irq_lock, host->flags); | |
a45c6cb8 MC |
1045 | WARN_ON(host->mrq != NULL); |
1046 | host->mrq = req; | |
70a3341a | 1047 | err = omap_hsmmc_prepare_data(host, req); |
a3f406f8 JL |
1048 | if (err) { |
1049 | req->cmd->error = err; | |
1050 | if (req->data) | |
1051 | req->data->error = err; | |
1052 | host->mrq = NULL; | |
4dffd7a2 AH |
1053 | if (!in_interrupt()) |
1054 | spin_unlock_irqrestore(&host->irq_lock, host->flags); | |
a3f406f8 JL |
1055 | mmc_request_done(mmc, req); |
1056 | return; | |
1057 | } | |
1058 | ||
70a3341a | 1059 | omap_hsmmc_start_command(host, req->cmd, req->data); |
a45c6cb8 MC |
1060 | } |
1061 | ||
a45c6cb8 | 1062 | /* Routine to configure clock values. Exposed API to core */ |
70a3341a | 1063 | static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
a45c6cb8 | 1064 | { |
70a3341a | 1065 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 MC |
1066 | u16 dsor = 0; |
1067 | unsigned long regval; | |
1068 | unsigned long timeout; | |
73153010 | 1069 | u32 con; |
a3621465 | 1070 | int do_send_init_stream = 0; |
a45c6cb8 | 1071 | |
5e2ea617 AH |
1072 | mmc_host_enable(host->mmc); |
1073 | ||
a3621465 AH |
1074 | if (ios->power_mode != host->power_mode) { |
1075 | switch (ios->power_mode) { | |
1076 | case MMC_POWER_OFF: | |
1077 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1078 | 0, 0); | |
623821f7 | 1079 | host->vdd = 0; |
a3621465 AH |
1080 | break; |
1081 | case MMC_POWER_UP: | |
1082 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1083 | 1, ios->vdd); | |
623821f7 | 1084 | host->vdd = ios->vdd; |
a3621465 AH |
1085 | break; |
1086 | case MMC_POWER_ON: | |
1087 | do_send_init_stream = 1; | |
1088 | break; | |
1089 | } | |
1090 | host->power_mode = ios->power_mode; | |
a45c6cb8 MC |
1091 | } |
1092 | ||
dd498eff DK |
1093 | /* FIXME: set registers based only on changes to ios */ |
1094 | ||
73153010 | 1095 | con = OMAP_HSMMC_READ(host->base, CON); |
a45c6cb8 | 1096 | switch (mmc->ios.bus_width) { |
73153010 JL |
1097 | case MMC_BUS_WIDTH_8: |
1098 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
1099 | break; | |
a45c6cb8 | 1100 | case MMC_BUS_WIDTH_4: |
73153010 | 1101 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); |
a45c6cb8 MC |
1102 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1103 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
1104 | break; | |
1105 | case MMC_BUS_WIDTH_1: | |
73153010 | 1106 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); |
a45c6cb8 MC |
1107 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1108 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
1109 | break; | |
1110 | } | |
1111 | ||
1112 | if (host->id == OMAP_MMC1_DEVID) { | |
eb250826 DB |
1113 | /* Only MMC1 can interface at 3V without some flavor |
1114 | * of external transceiver; but they all handle 1.8V. | |
1115 | */ | |
a45c6cb8 MC |
1116 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
1117 | (ios->vdd == DUAL_VOLT_OCR_BIT)) { | |
1118 | /* | |
1119 | * The mmc_select_voltage fn of the core does | |
1120 | * not seem to set the power_mode to | |
1121 | * MMC_POWER_UP upon recalculating the voltage. | |
1122 | * vdd 1.8v. | |
1123 | */ | |
70a3341a DK |
1124 | if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) |
1125 | dev_dbg(mmc_dev(host->mmc), | |
a45c6cb8 MC |
1126 | "Switch operation failed\n"); |
1127 | } | |
1128 | } | |
1129 | ||
1130 | if (ios->clock) { | |
1131 | dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; | |
1132 | if (dsor < 1) | |
1133 | dsor = 1; | |
1134 | ||
1135 | if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) | |
1136 | dsor++; | |
1137 | ||
1138 | if (dsor > 250) | |
1139 | dsor = 250; | |
1140 | } | |
70a3341a | 1141 | omap_hsmmc_stop_clock(host); |
a45c6cb8 MC |
1142 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); |
1143 | regval = regval & ~(CLKD_MASK); | |
1144 | regval = regval | (dsor << 6) | (DTO << 16); | |
1145 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); | |
1146 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
1147 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
1148 | ||
1149 | /* Wait till the ICS bit is set */ | |
1150 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
11dd62a7 | 1151 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS |
a45c6cb8 MC |
1152 | && time_before(jiffies, timeout)) |
1153 | msleep(1); | |
1154 | ||
1155 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
1156 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
1157 | ||
a3621465 | 1158 | if (do_send_init_stream) |
a45c6cb8 MC |
1159 | send_init_stream(host); |
1160 | ||
abb28e73 | 1161 | con = OMAP_HSMMC_READ(host->base, CON); |
a45c6cb8 | 1162 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) |
abb28e73 DK |
1163 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); |
1164 | else | |
1165 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
5e2ea617 | 1166 | |
dd498eff DK |
1167 | if (host->power_mode == MMC_POWER_OFF) |
1168 | mmc_host_disable(host->mmc); | |
1169 | else | |
1170 | mmc_host_lazy_disable(host->mmc); | |
a45c6cb8 MC |
1171 | } |
1172 | ||
1173 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) | |
1174 | { | |
70a3341a | 1175 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1176 | |
191d1f1d | 1177 | if (!mmc_slot(host).card_detect) |
a45c6cb8 | 1178 | return -ENOSYS; |
191d1f1d | 1179 | return mmc_slot(host).card_detect(mmc_slot(host).card_detect_irq); |
a45c6cb8 MC |
1180 | } |
1181 | ||
1182 | static int omap_hsmmc_get_ro(struct mmc_host *mmc) | |
1183 | { | |
70a3341a | 1184 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1185 | |
191d1f1d | 1186 | if (!mmc_slot(host).get_ro) |
a45c6cb8 | 1187 | return -ENOSYS; |
191d1f1d | 1188 | return mmc_slot(host).get_ro(host->dev, 0); |
a45c6cb8 MC |
1189 | } |
1190 | ||
70a3341a | 1191 | static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) |
1b331e69 KK |
1192 | { |
1193 | u32 hctl, capa, value; | |
1194 | ||
1195 | /* Only MMC1 supports 3.0V */ | |
1196 | if (host->id == OMAP_MMC1_DEVID) { | |
1197 | hctl = SDVS30; | |
1198 | capa = VS30 | VS18; | |
1199 | } else { | |
1200 | hctl = SDVS18; | |
1201 | capa = VS18; | |
1202 | } | |
1203 | ||
1204 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; | |
1205 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); | |
1206 | ||
1207 | value = OMAP_HSMMC_READ(host->base, CAPA); | |
1208 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); | |
1209 | ||
1210 | /* Set the controller to AUTO IDLE mode */ | |
1211 | value = OMAP_HSMMC_READ(host->base, SYSCONFIG); | |
1212 | OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); | |
1213 | ||
1214 | /* Set SD bus power bit */ | |
e13bb300 | 1215 | set_sd_bus_power(host); |
1b331e69 KK |
1216 | } |
1217 | ||
dd498eff DK |
1218 | /* |
1219 | * Dynamic power saving handling, FSM: | |
13189e78 JL |
1220 | * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF |
1221 | * ^___________| | | | |
1222 | * |______________________|______________________| | |
dd498eff DK |
1223 | * |
1224 | * ENABLED: mmc host is fully functional | |
1225 | * DISABLED: fclk is off | |
13189e78 JL |
1226 | * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep |
1227 | * REGSLEEP: fclk is off, voltage regulator is asleep | |
1228 | * OFF: fclk is off, voltage regulator is off | |
dd498eff DK |
1229 | * |
1230 | * Transition handlers return the timeout for the next state transition | |
1231 | * or negative error. | |
1232 | */ | |
1233 | ||
13189e78 | 1234 | enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF}; |
dd498eff DK |
1235 | |
1236 | /* Handler for [ENABLED -> DISABLED] transition */ | |
70a3341a | 1237 | static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host) |
dd498eff | 1238 | { |
70a3341a | 1239 | omap_hsmmc_context_save(host); |
dd498eff DK |
1240 | clk_disable(host->fclk); |
1241 | host->dpm_state = DISABLED; | |
1242 | ||
1243 | dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n"); | |
1244 | ||
1245 | if (host->power_mode == MMC_POWER_OFF) | |
1246 | return 0; | |
1247 | ||
13189e78 | 1248 | return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT); |
dd498eff DK |
1249 | } |
1250 | ||
13189e78 | 1251 | /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */ |
70a3341a | 1252 | static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host) |
dd498eff | 1253 | { |
13189e78 | 1254 | int err, new_state; |
dd498eff DK |
1255 | |
1256 | if (!mmc_try_claim_host(host->mmc)) | |
1257 | return 0; | |
1258 | ||
1259 | clk_enable(host->fclk); | |
70a3341a | 1260 | omap_hsmmc_context_restore(host); |
13189e78 JL |
1261 | if (mmc_card_can_sleep(host->mmc)) { |
1262 | err = mmc_card_sleep(host->mmc); | |
1263 | if (err < 0) { | |
1264 | clk_disable(host->fclk); | |
1265 | mmc_release_host(host->mmc); | |
1266 | return err; | |
1267 | } | |
1268 | new_state = CARDSLEEP; | |
70a3341a | 1269 | } else { |
13189e78 | 1270 | new_state = REGSLEEP; |
70a3341a | 1271 | } |
13189e78 JL |
1272 | if (mmc_slot(host).set_sleep) |
1273 | mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0, | |
1274 | new_state == CARDSLEEP); | |
1275 | /* FIXME: turn off bus power and perhaps interrupts too */ | |
1276 | clk_disable(host->fclk); | |
1277 | host->dpm_state = new_state; | |
1278 | ||
1279 | mmc_release_host(host->mmc); | |
1280 | ||
1281 | dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n", | |
1282 | host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); | |
dd498eff DK |
1283 | |
1284 | if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || | |
1285 | mmc_slot(host).card_detect || | |
1286 | (mmc_slot(host).get_cover_state && | |
13189e78 JL |
1287 | mmc_slot(host).get_cover_state(host->dev, host->slot_id))) |
1288 | return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT); | |
1289 | ||
1290 | return 0; | |
1291 | } | |
1292 | ||
1293 | /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */ | |
70a3341a | 1294 | static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host) |
13189e78 JL |
1295 | { |
1296 | if (!mmc_try_claim_host(host->mmc)) | |
1297 | return 0; | |
1298 | ||
1299 | if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) || | |
1300 | mmc_slot(host).card_detect || | |
1301 | (mmc_slot(host).get_cover_state && | |
1302 | mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) { | |
1303 | mmc_release_host(host->mmc); | |
1304 | return 0; | |
623821f7 | 1305 | } |
dd498eff | 1306 | |
13189e78 JL |
1307 | mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); |
1308 | host->vdd = 0; | |
1309 | host->power_mode = MMC_POWER_OFF; | |
dd498eff | 1310 | |
13189e78 JL |
1311 | dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n", |
1312 | host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); | |
dd498eff | 1313 | |
13189e78 | 1314 | host->dpm_state = OFF; |
dd498eff DK |
1315 | |
1316 | mmc_release_host(host->mmc); | |
1317 | ||
1318 | return 0; | |
1319 | } | |
1320 | ||
1321 | /* Handler for [DISABLED -> ENABLED] transition */ | |
70a3341a | 1322 | static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host) |
dd498eff DK |
1323 | { |
1324 | int err; | |
1325 | ||
1326 | err = clk_enable(host->fclk); | |
1327 | if (err < 0) | |
1328 | return err; | |
1329 | ||
70a3341a | 1330 | omap_hsmmc_context_restore(host); |
dd498eff DK |
1331 | host->dpm_state = ENABLED; |
1332 | ||
1333 | dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n"); | |
1334 | ||
1335 | return 0; | |
1336 | } | |
1337 | ||
13189e78 | 1338 | /* Handler for [SLEEP -> ENABLED] transition */ |
70a3341a | 1339 | static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host) |
dd498eff | 1340 | { |
13189e78 JL |
1341 | if (!mmc_try_claim_host(host->mmc)) |
1342 | return 0; | |
dd498eff | 1343 | |
13189e78 | 1344 | clk_enable(host->fclk); |
70a3341a | 1345 | omap_hsmmc_context_restore(host); |
13189e78 JL |
1346 | if (mmc_slot(host).set_sleep) |
1347 | mmc_slot(host).set_sleep(host->dev, host->slot_id, 0, | |
1348 | host->vdd, host->dpm_state == CARDSLEEP); | |
1349 | if (mmc_card_can_sleep(host->mmc)) | |
1350 | mmc_card_awake(host->mmc); | |
1351 | ||
1352 | dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n", | |
1353 | host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); | |
dd498eff DK |
1354 | |
1355 | host->dpm_state = ENABLED; | |
1356 | ||
13189e78 | 1357 | mmc_release_host(host->mmc); |
dd498eff DK |
1358 | |
1359 | return 0; | |
1360 | } | |
1361 | ||
13189e78 | 1362 | /* Handler for [OFF -> ENABLED] transition */ |
70a3341a | 1363 | static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host) |
623821f7 | 1364 | { |
623821f7 | 1365 | clk_enable(host->fclk); |
623821f7 | 1366 | |
70a3341a DK |
1367 | omap_hsmmc_context_restore(host); |
1368 | omap_hsmmc_conf_bus_power(host); | |
13189e78 | 1369 | mmc_power_restore_host(host->mmc); |
623821f7 AH |
1370 | |
1371 | host->dpm_state = ENABLED; | |
1372 | ||
13189e78 JL |
1373 | dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n"); |
1374 | ||
623821f7 AH |
1375 | return 0; |
1376 | } | |
1377 | ||
dd498eff DK |
1378 | /* |
1379 | * Bring MMC host to ENABLED from any other PM state. | |
1380 | */ | |
70a3341a | 1381 | static int omap_hsmmc_enable(struct mmc_host *mmc) |
dd498eff | 1382 | { |
70a3341a | 1383 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff DK |
1384 | |
1385 | switch (host->dpm_state) { | |
1386 | case DISABLED: | |
70a3341a | 1387 | return omap_hsmmc_disabled_to_enabled(host); |
13189e78 | 1388 | case CARDSLEEP: |
623821f7 | 1389 | case REGSLEEP: |
70a3341a | 1390 | return omap_hsmmc_sleep_to_enabled(host); |
dd498eff | 1391 | case OFF: |
70a3341a | 1392 | return omap_hsmmc_off_to_enabled(host); |
dd498eff DK |
1393 | default: |
1394 | dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); | |
1395 | return -EINVAL; | |
1396 | } | |
1397 | } | |
1398 | ||
1399 | /* | |
1400 | * Bring MMC host in PM state (one level deeper). | |
1401 | */ | |
70a3341a | 1402 | static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy) |
dd498eff | 1403 | { |
70a3341a | 1404 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff DK |
1405 | |
1406 | switch (host->dpm_state) { | |
1407 | case ENABLED: { | |
1408 | int delay; | |
1409 | ||
70a3341a | 1410 | delay = omap_hsmmc_enabled_to_disabled(host); |
dd498eff DK |
1411 | if (lazy || delay < 0) |
1412 | return delay; | |
1413 | return 0; | |
1414 | } | |
1415 | case DISABLED: | |
70a3341a | 1416 | return omap_hsmmc_disabled_to_sleep(host); |
13189e78 JL |
1417 | case CARDSLEEP: |
1418 | case REGSLEEP: | |
70a3341a | 1419 | return omap_hsmmc_sleep_to_off(host); |
dd498eff DK |
1420 | default: |
1421 | dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); | |
1422 | return -EINVAL; | |
1423 | } | |
1424 | } | |
1425 | ||
70a3341a | 1426 | static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) |
dd498eff | 1427 | { |
70a3341a | 1428 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff DK |
1429 | int err; |
1430 | ||
1431 | err = clk_enable(host->fclk); | |
1432 | if (err) | |
1433 | return err; | |
1434 | dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n"); | |
70a3341a | 1435 | omap_hsmmc_context_restore(host); |
dd498eff DK |
1436 | return 0; |
1437 | } | |
1438 | ||
70a3341a | 1439 | static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) |
dd498eff | 1440 | { |
70a3341a | 1441 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1442 | |
70a3341a | 1443 | omap_hsmmc_context_save(host); |
dd498eff DK |
1444 | clk_disable(host->fclk); |
1445 | dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n"); | |
1446 | return 0; | |
1447 | } | |
1448 | ||
70a3341a DK |
1449 | static const struct mmc_host_ops omap_hsmmc_ops = { |
1450 | .enable = omap_hsmmc_enable_fclk, | |
1451 | .disable = omap_hsmmc_disable_fclk, | |
1452 | .request = omap_hsmmc_request, | |
1453 | .set_ios = omap_hsmmc_set_ios, | |
dd498eff DK |
1454 | .get_cd = omap_hsmmc_get_cd, |
1455 | .get_ro = omap_hsmmc_get_ro, | |
1456 | /* NYET -- enable_sdio_irq */ | |
1457 | }; | |
1458 | ||
70a3341a DK |
1459 | static const struct mmc_host_ops omap_hsmmc_ps_ops = { |
1460 | .enable = omap_hsmmc_enable, | |
1461 | .disable = omap_hsmmc_disable, | |
1462 | .request = omap_hsmmc_request, | |
1463 | .set_ios = omap_hsmmc_set_ios, | |
a45c6cb8 MC |
1464 | .get_cd = omap_hsmmc_get_cd, |
1465 | .get_ro = omap_hsmmc_get_ro, | |
1466 | /* NYET -- enable_sdio_irq */ | |
1467 | }; | |
1468 | ||
d900f712 DK |
1469 | #ifdef CONFIG_DEBUG_FS |
1470 | ||
70a3341a | 1471 | static int omap_hsmmc_regs_show(struct seq_file *s, void *data) |
d900f712 DK |
1472 | { |
1473 | struct mmc_host *mmc = s->private; | |
70a3341a | 1474 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
11dd62a7 DK |
1475 | int context_loss = 0; |
1476 | ||
70a3341a DK |
1477 | if (host->pdata->get_context_loss_count) |
1478 | context_loss = host->pdata->get_context_loss_count(host->dev); | |
d900f712 | 1479 | |
5e2ea617 AH |
1480 | seq_printf(s, "mmc%d:\n" |
1481 | " enabled:\t%d\n" | |
dd498eff | 1482 | " dpm_state:\t%d\n" |
5e2ea617 | 1483 | " nesting_cnt:\t%d\n" |
11dd62a7 | 1484 | " ctx_loss:\t%d:%d\n" |
5e2ea617 | 1485 | "\nregs:\n", |
dd498eff DK |
1486 | mmc->index, mmc->enabled ? 1 : 0, |
1487 | host->dpm_state, mmc->nesting_cnt, | |
11dd62a7 | 1488 | host->context_loss, context_loss); |
5e2ea617 | 1489 | |
13189e78 | 1490 | if (host->suspended || host->dpm_state == OFF) { |
dd498eff DK |
1491 | seq_printf(s, "host suspended, can't read registers\n"); |
1492 | return 0; | |
1493 | } | |
1494 | ||
5e2ea617 AH |
1495 | if (clk_enable(host->fclk) != 0) { |
1496 | seq_printf(s, "can't read the regs\n"); | |
dd498eff | 1497 | return 0; |
5e2ea617 | 1498 | } |
d900f712 DK |
1499 | |
1500 | seq_printf(s, "SYSCONFIG:\t0x%08x\n", | |
1501 | OMAP_HSMMC_READ(host->base, SYSCONFIG)); | |
1502 | seq_printf(s, "CON:\t\t0x%08x\n", | |
1503 | OMAP_HSMMC_READ(host->base, CON)); | |
1504 | seq_printf(s, "HCTL:\t\t0x%08x\n", | |
1505 | OMAP_HSMMC_READ(host->base, HCTL)); | |
1506 | seq_printf(s, "SYSCTL:\t\t0x%08x\n", | |
1507 | OMAP_HSMMC_READ(host->base, SYSCTL)); | |
1508 | seq_printf(s, "IE:\t\t0x%08x\n", | |
1509 | OMAP_HSMMC_READ(host->base, IE)); | |
1510 | seq_printf(s, "ISE:\t\t0x%08x\n", | |
1511 | OMAP_HSMMC_READ(host->base, ISE)); | |
1512 | seq_printf(s, "CAPA:\t\t0x%08x\n", | |
1513 | OMAP_HSMMC_READ(host->base, CAPA)); | |
5e2ea617 AH |
1514 | |
1515 | clk_disable(host->fclk); | |
dd498eff | 1516 | |
d900f712 DK |
1517 | return 0; |
1518 | } | |
1519 | ||
70a3341a | 1520 | static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) |
d900f712 | 1521 | { |
70a3341a | 1522 | return single_open(file, omap_hsmmc_regs_show, inode->i_private); |
d900f712 DK |
1523 | } |
1524 | ||
1525 | static const struct file_operations mmc_regs_fops = { | |
70a3341a | 1526 | .open = omap_hsmmc_regs_open, |
d900f712 DK |
1527 | .read = seq_read, |
1528 | .llseek = seq_lseek, | |
1529 | .release = single_release, | |
1530 | }; | |
1531 | ||
70a3341a | 1532 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1533 | { |
1534 | if (mmc->debugfs_root) | |
1535 | debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, | |
1536 | mmc, &mmc_regs_fops); | |
1537 | } | |
1538 | ||
1539 | #else | |
1540 | ||
70a3341a | 1541 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1542 | { |
1543 | } | |
1544 | ||
1545 | #endif | |
1546 | ||
70a3341a | 1547 | static int __init omap_hsmmc_probe(struct platform_device *pdev) |
a45c6cb8 MC |
1548 | { |
1549 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; | |
1550 | struct mmc_host *mmc; | |
70a3341a | 1551 | struct omap_hsmmc_host *host = NULL; |
a45c6cb8 MC |
1552 | struct resource *res; |
1553 | int ret = 0, irq; | |
a45c6cb8 MC |
1554 | |
1555 | if (pdata == NULL) { | |
1556 | dev_err(&pdev->dev, "Platform Data is missing\n"); | |
1557 | return -ENXIO; | |
1558 | } | |
1559 | ||
1560 | if (pdata->nr_slots == 0) { | |
1561 | dev_err(&pdev->dev, "No Slots\n"); | |
1562 | return -ENXIO; | |
1563 | } | |
1564 | ||
1565 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1566 | irq = platform_get_irq(pdev, 0); | |
1567 | if (res == NULL || irq < 0) | |
1568 | return -ENXIO; | |
1569 | ||
1570 | res = request_mem_region(res->start, res->end - res->start + 1, | |
1571 | pdev->name); | |
1572 | if (res == NULL) | |
1573 | return -EBUSY; | |
1574 | ||
70a3341a | 1575 | mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); |
a45c6cb8 MC |
1576 | if (!mmc) { |
1577 | ret = -ENOMEM; | |
1578 | goto err; | |
1579 | } | |
1580 | ||
1581 | host = mmc_priv(mmc); | |
1582 | host->mmc = mmc; | |
1583 | host->pdata = pdata; | |
1584 | host->dev = &pdev->dev; | |
1585 | host->use_dma = 1; | |
1586 | host->dev->dma_mask = &pdata->dma_mask; | |
1587 | host->dma_ch = -1; | |
1588 | host->irq = irq; | |
1589 | host->id = pdev->id; | |
1590 | host->slot_id = 0; | |
1591 | host->mapbase = res->start; | |
1592 | host->base = ioremap(host->mapbase, SZ_4K); | |
a3621465 | 1593 | host->power_mode = -1; |
a45c6cb8 MC |
1594 | |
1595 | platform_set_drvdata(pdev, host); | |
70a3341a | 1596 | INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); |
a45c6cb8 | 1597 | |
191d1f1d | 1598 | if (mmc_slot(host).power_saving) |
70a3341a | 1599 | mmc->ops = &omap_hsmmc_ps_ops; |
dd498eff | 1600 | else |
70a3341a | 1601 | mmc->ops = &omap_hsmmc_ops; |
dd498eff | 1602 | |
a45c6cb8 MC |
1603 | mmc->f_min = 400000; |
1604 | mmc->f_max = 52000000; | |
1605 | ||
1606 | sema_init(&host->sem, 1); | |
4dffd7a2 | 1607 | spin_lock_init(&host->irq_lock); |
a45c6cb8 | 1608 | |
6f7607cc | 1609 | host->iclk = clk_get(&pdev->dev, "ick"); |
a45c6cb8 MC |
1610 | if (IS_ERR(host->iclk)) { |
1611 | ret = PTR_ERR(host->iclk); | |
1612 | host->iclk = NULL; | |
1613 | goto err1; | |
1614 | } | |
6f7607cc | 1615 | host->fclk = clk_get(&pdev->dev, "fck"); |
a45c6cb8 MC |
1616 | if (IS_ERR(host->fclk)) { |
1617 | ret = PTR_ERR(host->fclk); | |
1618 | host->fclk = NULL; | |
1619 | clk_put(host->iclk); | |
1620 | goto err1; | |
1621 | } | |
1622 | ||
70a3341a | 1623 | omap_hsmmc_context_save(host); |
11dd62a7 | 1624 | |
5e2ea617 | 1625 | mmc->caps |= MMC_CAP_DISABLE; |
dd498eff DK |
1626 | mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT); |
1627 | /* we start off in DISABLED state */ | |
1628 | host->dpm_state = DISABLED; | |
1629 | ||
5e2ea617 | 1630 | if (mmc_host_enable(host->mmc) != 0) { |
a45c6cb8 MC |
1631 | clk_put(host->iclk); |
1632 | clk_put(host->fclk); | |
1633 | goto err1; | |
1634 | } | |
1635 | ||
1636 | if (clk_enable(host->iclk) != 0) { | |
5e2ea617 | 1637 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
1638 | clk_put(host->iclk); |
1639 | clk_put(host->fclk); | |
1640 | goto err1; | |
1641 | } | |
1642 | ||
1643 | host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); | |
1644 | /* | |
1645 | * MMC can still work without debounce clock. | |
1646 | */ | |
1647 | if (IS_ERR(host->dbclk)) | |
1648 | dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n"); | |
1649 | else | |
1650 | if (clk_enable(host->dbclk) != 0) | |
1651 | dev_dbg(mmc_dev(host->mmc), "Enabling debounce" | |
1652 | " clk failed\n"); | |
1653 | else | |
1654 | host->dbclk_enabled = 1; | |
1655 | ||
0ccd76d4 JY |
1656 | /* Since we do only SG emulation, we can have as many segs |
1657 | * as we want. */ | |
1658 | mmc->max_phys_segs = 1024; | |
1659 | mmc->max_hw_segs = 1024; | |
1660 | ||
a45c6cb8 MC |
1661 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
1662 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ | |
1663 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1664 | mmc->max_seg_size = mmc->max_req_size; | |
1665 | ||
13189e78 JL |
1666 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
1667 | MMC_CAP_WAIT_WHILE_BUSY; | |
a45c6cb8 | 1668 | |
191d1f1d | 1669 | if (mmc_slot(host).wires >= 8) |
73153010 | 1670 | mmc->caps |= MMC_CAP_8_BIT_DATA; |
191d1f1d | 1671 | else if (mmc_slot(host).wires >= 4) |
a45c6cb8 MC |
1672 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
1673 | ||
191d1f1d | 1674 | if (mmc_slot(host).nonremovable) |
23d99bb9 AH |
1675 | mmc->caps |= MMC_CAP_NONREMOVABLE; |
1676 | ||
70a3341a | 1677 | omap_hsmmc_conf_bus_power(host); |
a45c6cb8 | 1678 | |
f3e2f1dd GI |
1679 | /* Select DMA lines */ |
1680 | switch (host->id) { | |
1681 | case OMAP_MMC1_DEVID: | |
1682 | host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; | |
1683 | host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; | |
1684 | break; | |
1685 | case OMAP_MMC2_DEVID: | |
1686 | host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; | |
1687 | host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; | |
1688 | break; | |
1689 | case OMAP_MMC3_DEVID: | |
1690 | host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; | |
1691 | host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; | |
1692 | break; | |
1693 | default: | |
1694 | dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); | |
1695 | goto err_irq; | |
1696 | } | |
a45c6cb8 MC |
1697 | |
1698 | /* Request IRQ for MMC operations */ | |
70a3341a | 1699 | ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED, |
a45c6cb8 MC |
1700 | mmc_hostname(mmc), host); |
1701 | if (ret) { | |
1702 | dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); | |
1703 | goto err_irq; | |
1704 | } | |
1705 | ||
b583f26d | 1706 | /* initialize power supplies, gpios, etc */ |
a45c6cb8 MC |
1707 | if (pdata->init != NULL) { |
1708 | if (pdata->init(&pdev->dev) != 0) { | |
70a3341a DK |
1709 | dev_dbg(mmc_dev(host->mmc), |
1710 | "Unable to configure MMC IRQs\n"); | |
a45c6cb8 MC |
1711 | goto err_irq_cd_init; |
1712 | } | |
1713 | } | |
b583f26d | 1714 | mmc->ocr_avail = mmc_slot(host).ocr_mask; |
a45c6cb8 MC |
1715 | |
1716 | /* Request IRQ for card detect */ | |
e1a55f5e | 1717 | if ((mmc_slot(host).card_detect_irq)) { |
a45c6cb8 | 1718 | ret = request_irq(mmc_slot(host).card_detect_irq, |
70a3341a | 1719 | omap_hsmmc_cd_handler, |
a45c6cb8 MC |
1720 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
1721 | | IRQF_DISABLED, | |
1722 | mmc_hostname(mmc), host); | |
1723 | if (ret) { | |
1724 | dev_dbg(mmc_dev(host->mmc), | |
1725 | "Unable to grab MMC CD IRQ\n"); | |
1726 | goto err_irq_cd; | |
1727 | } | |
1728 | } | |
1729 | ||
1730 | OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK); | |
1731 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
1732 | ||
5e2ea617 AH |
1733 | mmc_host_lazy_disable(host->mmc); |
1734 | ||
a45c6cb8 MC |
1735 | mmc_add_host(mmc); |
1736 | ||
191d1f1d | 1737 | if (mmc_slot(host).name != NULL) { |
a45c6cb8 MC |
1738 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); |
1739 | if (ret < 0) | |
1740 | goto err_slot_name; | |
1741 | } | |
191d1f1d | 1742 | if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { |
a45c6cb8 MC |
1743 | ret = device_create_file(&mmc->class_dev, |
1744 | &dev_attr_cover_switch); | |
1745 | if (ret < 0) | |
1746 | goto err_cover_switch; | |
1747 | } | |
1748 | ||
70a3341a | 1749 | omap_hsmmc_debugfs(mmc); |
d900f712 | 1750 | |
a45c6cb8 MC |
1751 | return 0; |
1752 | ||
1753 | err_cover_switch: | |
1754 | device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); | |
1755 | err_slot_name: | |
1756 | mmc_remove_host(mmc); | |
1757 | err_irq_cd: | |
1758 | free_irq(mmc_slot(host).card_detect_irq, host); | |
1759 | err_irq_cd_init: | |
1760 | free_irq(host->irq, host); | |
1761 | err_irq: | |
5e2ea617 | 1762 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
1763 | clk_disable(host->iclk); |
1764 | clk_put(host->fclk); | |
1765 | clk_put(host->iclk); | |
1766 | if (host->dbclk_enabled) { | |
1767 | clk_disable(host->dbclk); | |
1768 | clk_put(host->dbclk); | |
1769 | } | |
1770 | ||
1771 | err1: | |
1772 | iounmap(host->base); | |
1773 | err: | |
1774 | dev_dbg(mmc_dev(host->mmc), "Probe Failed\n"); | |
1775 | release_mem_region(res->start, res->end - res->start + 1); | |
1776 | if (host) | |
1777 | mmc_free_host(mmc); | |
1778 | return ret; | |
1779 | } | |
1780 | ||
70a3341a | 1781 | static int omap_hsmmc_remove(struct platform_device *pdev) |
a45c6cb8 | 1782 | { |
70a3341a | 1783 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
1784 | struct resource *res; |
1785 | ||
1786 | if (host) { | |
5e2ea617 | 1787 | mmc_host_enable(host->mmc); |
a45c6cb8 MC |
1788 | mmc_remove_host(host->mmc); |
1789 | if (host->pdata->cleanup) | |
1790 | host->pdata->cleanup(&pdev->dev); | |
1791 | free_irq(host->irq, host); | |
1792 | if (mmc_slot(host).card_detect_irq) | |
1793 | free_irq(mmc_slot(host).card_detect_irq, host); | |
1794 | flush_scheduled_work(); | |
1795 | ||
5e2ea617 | 1796 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
1797 | clk_disable(host->iclk); |
1798 | clk_put(host->fclk); | |
1799 | clk_put(host->iclk); | |
1800 | if (host->dbclk_enabled) { | |
1801 | clk_disable(host->dbclk); | |
1802 | clk_put(host->dbclk); | |
1803 | } | |
1804 | ||
1805 | mmc_free_host(host->mmc); | |
1806 | iounmap(host->base); | |
1807 | } | |
1808 | ||
1809 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1810 | if (res) | |
1811 | release_mem_region(res->start, res->end - res->start + 1); | |
1812 | platform_set_drvdata(pdev, NULL); | |
1813 | ||
1814 | return 0; | |
1815 | } | |
1816 | ||
1817 | #ifdef CONFIG_PM | |
70a3341a | 1818 | static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state) |
a45c6cb8 MC |
1819 | { |
1820 | int ret = 0; | |
70a3341a | 1821 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
1822 | |
1823 | if (host && host->suspended) | |
1824 | return 0; | |
1825 | ||
1826 | if (host) { | |
a6b2240d AH |
1827 | host->suspended = 1; |
1828 | if (host->pdata->suspend) { | |
1829 | ret = host->pdata->suspend(&pdev->dev, | |
1830 | host->slot_id); | |
1831 | if (ret) { | |
1832 | dev_dbg(mmc_dev(host->mmc), | |
1833 | "Unable to handle MMC board" | |
1834 | " level suspend\n"); | |
1835 | host->suspended = 0; | |
1836 | return ret; | |
1837 | } | |
1838 | } | |
1839 | cancel_work_sync(&host->mmc_carddetect_work); | |
5e2ea617 | 1840 | mmc_host_enable(host->mmc); |
a45c6cb8 MC |
1841 | ret = mmc_suspend_host(host->mmc, state); |
1842 | if (ret == 0) { | |
a45c6cb8 MC |
1843 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
1844 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
1845 | ||
a45c6cb8 | 1846 | |
0683af48 | 1847 | OMAP_HSMMC_WRITE(host->base, HCTL, |
191d1f1d | 1848 | OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); |
5e2ea617 | 1849 | mmc_host_disable(host->mmc); |
a45c6cb8 MC |
1850 | clk_disable(host->iclk); |
1851 | clk_disable(host->dbclk); | |
a6b2240d AH |
1852 | } else { |
1853 | host->suspended = 0; | |
1854 | if (host->pdata->resume) { | |
1855 | ret = host->pdata->resume(&pdev->dev, | |
1856 | host->slot_id); | |
1857 | if (ret) | |
1858 | dev_dbg(mmc_dev(host->mmc), | |
1859 | "Unmask interrupt failed\n"); | |
1860 | } | |
5e2ea617 | 1861 | mmc_host_disable(host->mmc); |
a6b2240d | 1862 | } |
a45c6cb8 MC |
1863 | |
1864 | } | |
1865 | return ret; | |
1866 | } | |
1867 | ||
1868 | /* Routine to resume the MMC device */ | |
70a3341a | 1869 | static int omap_hsmmc_resume(struct platform_device *pdev) |
a45c6cb8 MC |
1870 | { |
1871 | int ret = 0; | |
70a3341a | 1872 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
1873 | |
1874 | if (host && !host->suspended) | |
1875 | return 0; | |
1876 | ||
1877 | if (host) { | |
a45c6cb8 | 1878 | ret = clk_enable(host->iclk); |
11dd62a7 | 1879 | if (ret) |
a45c6cb8 | 1880 | goto clk_en_err; |
a45c6cb8 MC |
1881 | |
1882 | if (clk_enable(host->dbclk) != 0) | |
1883 | dev_dbg(mmc_dev(host->mmc), | |
1884 | "Enabling debounce clk failed\n"); | |
1885 | ||
11dd62a7 DK |
1886 | if (mmc_host_enable(host->mmc) != 0) { |
1887 | clk_disable(host->iclk); | |
1888 | goto clk_en_err; | |
1889 | } | |
1890 | ||
70a3341a | 1891 | omap_hsmmc_conf_bus_power(host); |
1b331e69 | 1892 | |
a45c6cb8 MC |
1893 | if (host->pdata->resume) { |
1894 | ret = host->pdata->resume(&pdev->dev, host->slot_id); | |
1895 | if (ret) | |
1896 | dev_dbg(mmc_dev(host->mmc), | |
1897 | "Unmask interrupt failed\n"); | |
1898 | } | |
1899 | ||
1900 | /* Notify the core to resume the host */ | |
1901 | ret = mmc_resume_host(host->mmc); | |
1902 | if (ret == 0) | |
1903 | host->suspended = 0; | |
70a3341a | 1904 | |
5e2ea617 | 1905 | mmc_host_lazy_disable(host->mmc); |
a45c6cb8 MC |
1906 | } |
1907 | ||
1908 | return ret; | |
1909 | ||
1910 | clk_en_err: | |
1911 | dev_dbg(mmc_dev(host->mmc), | |
1912 | "Failed to enable MMC clocks during resume\n"); | |
1913 | return ret; | |
1914 | } | |
1915 | ||
1916 | #else | |
70a3341a DK |
1917 | #define omap_hsmmc_suspend NULL |
1918 | #define omap_hsmmc_resume NULL | |
a45c6cb8 MC |
1919 | #endif |
1920 | ||
70a3341a DK |
1921 | static struct platform_driver omap_hsmmc_driver = { |
1922 | .remove = omap_hsmmc_remove, | |
1923 | .suspend = omap_hsmmc_suspend, | |
1924 | .resume = omap_hsmmc_resume, | |
a45c6cb8 MC |
1925 | .driver = { |
1926 | .name = DRIVER_NAME, | |
1927 | .owner = THIS_MODULE, | |
1928 | }, | |
1929 | }; | |
1930 | ||
70a3341a | 1931 | static int __init omap_hsmmc_init(void) |
a45c6cb8 MC |
1932 | { |
1933 | /* Register the MMC driver */ | |
70a3341a | 1934 | return platform_driver_register(&omap_hsmmc_driver); |
a45c6cb8 MC |
1935 | } |
1936 | ||
70a3341a | 1937 | static void __exit omap_hsmmc_cleanup(void) |
a45c6cb8 MC |
1938 | { |
1939 | /* Unregister MMC driver */ | |
70a3341a | 1940 | platform_driver_unregister(&omap_hsmmc_driver); |
a45c6cb8 MC |
1941 | } |
1942 | ||
70a3341a DK |
1943 | module_init(omap_hsmmc_init); |
1944 | module_exit(omap_hsmmc_cleanup); | |
a45c6cb8 MC |
1945 | |
1946 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); | |
1947 | MODULE_LICENSE("GPL"); | |
1948 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
1949 | MODULE_AUTHOR("Texas Instruments Inc"); |