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mmc: omap_hsmmc: Remove lazy_disable
[mirror_ubuntu-zesty-kernel.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
93caf8e6 31#include <linux/mmc/mmc.h>
a45c6cb8
MC		 32#include <linux/io.h>
33#include <linux/semaphore.h>
db0fefc5
AH		 34#include <linux/gpio.h>
35#include <linux/regulator/consumer.h>
ce491cf8 36#include <plat/dma.h>
a45c6cb8 37#include <mach/hardware.h>
ce491cf8
TL		 38#include <plat/board.h>
39#include <plat/mmc.h>
40#include <plat/cpu.h>
a45c6cb8
MC		 41
42/* OMAP HSMMC Host Controller Registers */
43#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 44#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 45#define OMAP_HSMMC_CON 0x002C
46#define OMAP_HSMMC_BLK 0x0104
47#define OMAP_HSMMC_ARG 0x0108
48#define OMAP_HSMMC_CMD 0x010C
49#define OMAP_HSMMC_RSP10 0x0110
50#define OMAP_HSMMC_RSP32 0x0114
51#define OMAP_HSMMC_RSP54 0x0118
52#define OMAP_HSMMC_RSP76 0x011C
53#define OMAP_HSMMC_DATA 0x0120
54#define OMAP_HSMMC_HCTL 0x0128
55#define OMAP_HSMMC_SYSCTL 0x012C
56#define OMAP_HSMMC_STAT 0x0130
57#define OMAP_HSMMC_IE 0x0134
58#define OMAP_HSMMC_ISE 0x0138
59#define OMAP_HSMMC_CAPA 0x0140
60
61#define VS18 (1 << 26)
62#define VS30 (1 << 25)
63#define SDVS18 (0x5 << 9)
64#define SDVS30 (0x6 << 9)
eb250826 65#define SDVS33 (0x7 << 9)
1b331e69 66#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 67#define SDVSCLR 0xFFFFF1FF
68#define SDVSDET 0x00000400
69#define AUTOIDLE 0x1
70#define SDBP (1 << 8)
71#define DTO 0xe
72#define ICE 0x1
73#define ICS 0x2
74#define CEN (1 << 2)
75#define CLKD_MASK 0x0000FFC0
76#define CLKD_SHIFT 6
77#define DTO_MASK 0x000F0000
78#define DTO_SHIFT 16
79#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 80#define BWR_ENABLE (1 << 4)
81#define BRR_ENABLE (1 << 5)
93caf8e6 82#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 83#define INIT_STREAM (1 << 1)
84#define DP_SELECT (1 << 21)
85#define DDIR (1 << 4)
86#define DMA_EN 0x1
87#define MSBS (1 << 5)
88#define BCE (1 << 1)
89#define FOUR_BIT (1 << 1)
73153010 90#define DW8 (1 << 5)
a45c6cb8
MC		 91#define CC 0x1
92#define TC 0x02
93#define OD 0x1
94#define ERR (1 << 15)
95#define CMD_TIMEOUT (1 << 16)
96#define DATA_TIMEOUT (1 << 20)
97#define CMD_CRC (1 << 17)
98#define DATA_CRC (1 << 21)
99#define CARD_ERR (1 << 28)
100#define STAT_CLEAR 0xFFFFFFFF
101#define INIT_STREAM_CMD 0x00000000
102#define DUAL_VOLT_OCR_BIT 7
103#define SRC (1 << 25)
104#define SRD (1 << 26)
11dd62a7
DK		 105#define SOFTRESET (1 << 1)
106#define RESETDONE (1 << 0)
a45c6cb8
MC		 107
108/*
109 * FIXME: Most likely all the data using these _DEVID defines should come
110 * from the platform_data, or implemented in controller and slot specific
111 * functions.
112 */
113#define OMAP_MMC1_DEVID 0
114#define OMAP_MMC2_DEVID 1
f3e2f1dd 115#define OMAP_MMC3_DEVID 2
82cf818d 116#define OMAP_MMC4_DEVID 3
117#define OMAP_MMC5_DEVID 4
a45c6cb8 118
a45c6cb8
MC		 119#define MMC_TIMEOUT_MS 20
120#define OMAP_MMC_MASTER_CLOCK 96000000
0005ae73 121#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 122
123/*
124 * One controller can have multiple slots, like on some omap boards using
125 * omap.c controller driver. Luckily this is not currently done on any known
126 * omap_hsmmc.c device.
127 */
128#define mmc_slot(host) (host->pdata->slots[host->slot_id])
129
130/*
131 * MMC Host controller read/write API's
132 */
133#define OMAP_HSMMC_READ(base, reg) \
134 __raw_readl((base) + OMAP_HSMMC_##reg)
135
136#define OMAP_HSMMC_WRITE(base, reg, val) \
137 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
138
9782aff8
PF		 139struct omap_hsmmc_next {
140 unsigned int dma_len;
141 s32 cookie;
142};
143
70a3341a 144struct omap_hsmmc_host {
a45c6cb8
MC		 145 struct device *dev;
146 struct mmc_host *mmc;
147 struct mmc_request *mrq;
148 struct mmc_command *cmd;
149 struct mmc_data *data;
150 struct clk *fclk;
151 struct clk *iclk;
152 struct clk *dbclk;
db0fefc5
AH		 153 /*
154 * vcc == configured supply
155 * vcc_aux == optional
156 * - MMC1, supply for DAT4..DAT7
157 * - MMC2/MMC2, external level shifter voltage supply, for
158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
159 */
160 struct regulator *vcc;
161 struct regulator *vcc_aux;
a45c6cb8
MC		 162 struct work_struct mmc_carddetect_work;
163 void __iomem *base;
164 resource_size_t mapbase;
4dffd7a2 165 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 166 unsigned int id;
167 unsigned int dma_len;
0ccd76d4 168 unsigned int dma_sg_idx;
a45c6cb8 169 unsigned char bus_mode;
a3621465 170 unsigned char power_mode;
a45c6cb8
MC		 171 u32 *buffer;
172 u32 bytesleft;
173 int suspended;
174 int irq;
a45c6cb8 175 int use_dma, dma_ch;
f3e2f1dd 176 int dma_line_tx, dma_line_rx;
a45c6cb8 177 int slot_id;
2bec0893 178 int got_dbclk;
4a694dc9 179 int response_busy;
11dd62a7 180 int context_loss;
dd498eff 181 int dpm_state;
623821f7 182 int vdd;
b62f6228
AH		 183 int protect_card;
184 int reqs_blocked;
db0fefc5 185 int use_reg;
b417577d 186 int req_in_progress;
9782aff8 187 struct omap_hsmmc_next next_data;
11dd62a7 188
a45c6cb8
MC		 189 struct omap_mmc_platform_data *pdata;
190};
191
db0fefc5
AH		 192static int omap_hsmmc_card_detect(struct device *dev, int slot)
193{
194 struct omap_mmc_platform_data *mmc = dev->platform_data;
195
196 /* NOTE: assumes card detect signal is active-low */
197 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
198}
199
200static int omap_hsmmc_get_wp(struct device *dev, int slot)
201{
202 struct omap_mmc_platform_data *mmc = dev->platform_data;
203
204 /* NOTE: assumes write protect signal is active-high */
205 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
206}
207
208static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
209{
210 struct omap_mmc_platform_data *mmc = dev->platform_data;
211
212 /* NOTE: assumes card detect signal is active-low */
213 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
214}
215
216#ifdef CONFIG_PM
217
218static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
219{
220 struct omap_mmc_platform_data *mmc = dev->platform_data;
221
222 disable_irq(mmc->slots[0].card_detect_irq);
223 return 0;
224}
225
226static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
227{
228 struct omap_mmc_platform_data *mmc = dev->platform_data;
229
230 enable_irq(mmc->slots[0].card_detect_irq);
231 return 0;
232}
233
234#else
235
236#define omap_hsmmc_suspend_cdirq NULL
237#define omap_hsmmc_resume_cdirq NULL
238
239#endif
240
b702b106
AH		 241#ifdef CONFIG_REGULATOR
242
db0fefc5
AH		 243static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
244 int vdd)
245{
246 struct omap_hsmmc_host *host =
247 platform_get_drvdata(to_platform_device(dev));
248 int ret;
249
250 if (mmc_slot(host).before_set_reg)
251 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
252
253 if (power_on)
99fc5131 254 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5 255 else
99fc5131 256 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5
AH		 257
258 if (mmc_slot(host).after_set_reg)
259 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
260
261 return ret;
262}
263
7715db5a 264static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 265 int vdd)
266{
267 struct omap_hsmmc_host *host =
268 platform_get_drvdata(to_platform_device(dev));
269 int ret = 0;
270
271 /*
272 * If we don't see a Vcc regulator, assume it's a fixed
273 * voltage always-on regulator.
274 */
275 if (!host->vcc)
276 return 0;
277
278 if (mmc_slot(host).before_set_reg)
279 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
280
281 /*
282 * Assume Vcc regulator is used only to power the card ... OMAP
283 * VDDS is used to power the pins, optionally with a transceiver to
284 * support cards using voltages other than VDDS (1.8V nominal). When a
285 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
286 *
287 * In some cases this regulator won't support enable/disable;
288 * e.g. it's a fixed rail for a WLAN chip.
289 *
290 * In other cases vcc_aux switches interface power. Example, for
291 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
292 * chips/cards need an interface voltage rail too.
293 */
294 if (power_on) {
99fc5131 295 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 296 /* Enable interface voltage rail, if needed */
297 if (ret == 0 && host->vcc_aux) {
298 ret = regulator_enable(host->vcc_aux);
299 if (ret < 0)
99fc5131
LW		 300 ret = mmc_regulator_set_ocr(host->mmc,
301 host->vcc, 0);
db0fefc5
AH		 302 }
303 } else {
99fc5131 304 /* Shut down the rail */
6da20c89
AH		 305 if (host->vcc_aux)
306 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 307 if (!ret) {
308 /* Then proceed to shut down the local regulator */
309 ret = mmc_regulator_set_ocr(host->mmc,
310 host->vcc, 0);
311 }
db0fefc5
AH		 312 }
313
314 if (mmc_slot(host).after_set_reg)
315 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
316
317 return ret;
318}
319
7715db5a
KK		 320static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
321 int vdd)
322{
323 return 0;
324}
325
db0fefc5
AH		 326static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
327 int vdd, int cardsleep)
328{
329 struct omap_hsmmc_host *host =
330 platform_get_drvdata(to_platform_device(dev));
331 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
332
333 return regulator_set_mode(host->vcc, mode);
334}
335
7715db5a 336static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
db0fefc5
AH		 337 int vdd, int cardsleep)
338{
339 struct omap_hsmmc_host *host =
340 platform_get_drvdata(to_platform_device(dev));
341 int err, mode;
342
343 /*
344 * If we don't see a Vcc regulator, assume it's a fixed
345 * voltage always-on regulator.
346 */
347 if (!host->vcc)
348 return 0;
349
350 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
351
352 if (!host->vcc_aux)
353 return regulator_set_mode(host->vcc, mode);
354
355 if (cardsleep) {
356 /* VCC can be turned off if card is asleep */
357 if (sleep)
99fc5131 358 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5 359 else
99fc5131 360 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 361 } else
362 err = regulator_set_mode(host->vcc, mode);
363 if (err)
364 return err;
e0eb2424
AH		 365
366 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
367 return regulator_set_mode(host->vcc_aux, mode);
368
369 if (sleep)
370 return regulator_disable(host->vcc_aux);
371 else
372 return regulator_enable(host->vcc_aux);
db0fefc5
AH		 373}
374
7715db5a
KK		 375static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
376 int vdd, int cardsleep)
377{
378 return 0;
379}
380
db0fefc5
AH		 381static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
382{
383 struct regulator *reg;
384 int ret = 0;
64be9782 385 int ocr_value = 0;
db0fefc5
AH		 386
387 switch (host->id) {
388 case OMAP_MMC1_DEVID:
389 /* On-chip level shifting via PBIAS0/PBIAS1 */
390 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
391 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
392 break;
393 case OMAP_MMC2_DEVID:
394 case OMAP_MMC3_DEVID:
7715db5a 395 case OMAP_MMC5_DEVID:
db0fefc5 396 /* Off-chip level shifting, or none */
7715db5a
KK		 397 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
398 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
db0fefc5 399 break;
7715db5a
KK		 400 case OMAP_MMC4_DEVID:
401 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
402 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
db0fefc5
AH		 403 default:
404 pr_err("MMC%d configuration not supported!\n", host->id);
405 return -EINVAL;
406 }
407
408 reg = regulator_get(host->dev, "vmmc");
409 if (IS_ERR(reg)) {
410 dev_dbg(host->dev, "vmmc regulator missing\n");
411 /*
412 * HACK: until fixed.c regulator is usable,
413 * we don't require a main regulator
414 * for MMC2 or MMC3
415 */
416 if (host->id == OMAP_MMC1_DEVID) {
417 ret = PTR_ERR(reg);
418 goto err;
419 }
420 } else {
421 host->vcc = reg;
64be9782 422 ocr_value = mmc_regulator_get_ocrmask(reg);
423 if (!mmc_slot(host).ocr_mask) {
424 mmc_slot(host).ocr_mask = ocr_value;
425 } else {
426 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
427 pr_err("MMC%d ocrmask %x is not supported\n",
428 host->id, mmc_slot(host).ocr_mask);
429 mmc_slot(host).ocr_mask = 0;
430 return -EINVAL;
431 }
432 }
db0fefc5
AH		 433
434 /* Allow an aux regulator */
435 reg = regulator_get(host->dev, "vmmc_aux");
436 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
437
b1c1df7a
B		 438 /* For eMMC do not power off when not in sleep state */
439 if (mmc_slot(host).no_regulator_off_init)
440 return 0;
db0fefc5
AH		 441 /*
442 * UGLY HACK: workaround regulator framework bugs.
443 * When the bootloader leaves a supply active, it's
444 * initialized with zero usecount ... and we can't
445 * disable it without first enabling it. Until the
446 * framework is fixed, we need a workaround like this
447 * (which is safe for MMC, but not in general).
448 */
449 if (regulator_is_enabled(host->vcc) > 0) {
450 regulator_enable(host->vcc);
451 regulator_disable(host->vcc);
452 }
453 if (host->vcc_aux) {
454 if (regulator_is_enabled(reg) > 0) {
455 regulator_enable(reg);
456 regulator_disable(reg);
457 }
458 }
459 }
460
461 return 0;
462
463err:
464 mmc_slot(host).set_power = NULL;
465 mmc_slot(host).set_sleep = NULL;
466 return ret;
467}
468
469static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
470{
471 regulator_put(host->vcc);
472 regulator_put(host->vcc_aux);
473 mmc_slot(host).set_power = NULL;
474 mmc_slot(host).set_sleep = NULL;
475}
476
b702b106
AH		 477static inline int omap_hsmmc_have_reg(void)
478{
479 return 1;
480}
481
482#else
483
484static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
485{
486 return -EINVAL;
487}
488
489static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
490{
491}
492
493static inline int omap_hsmmc_have_reg(void)
494{
495 return 0;
496}
497
498#endif
499
500static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
501{
502 int ret;
503
504 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 505 if (pdata->slots[0].cover)
506 pdata->slots[0].get_cover_state =
507 omap_hsmmc_get_cover_state;
508 else
509 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
510 pdata->slots[0].card_detect_irq =
511 gpio_to_irq(pdata->slots[0].switch_pin);
512 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
513 if (ret)
514 return ret;
515 ret = gpio_direction_input(pdata->slots[0].switch_pin);
516 if (ret)
517 goto err_free_sp;
518 } else
519 pdata->slots[0].switch_pin = -EINVAL;
520
521 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
522 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
523 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
524 if (ret)
525 goto err_free_cd;
526 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
527 if (ret)
528 goto err_free_wp;
529 } else
530 pdata->slots[0].gpio_wp = -EINVAL;
531
532 return 0;
533
534err_free_wp:
535 gpio_free(pdata->slots[0].gpio_wp);
536err_free_cd:
537 if (gpio_is_valid(pdata->slots[0].switch_pin))
538err_free_sp:
539 gpio_free(pdata->slots[0].switch_pin);
540 return ret;
541}
542
543static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
544{
545 if (gpio_is_valid(pdata->slots[0].gpio_wp))
546 gpio_free(pdata->slots[0].gpio_wp);
547 if (gpio_is_valid(pdata->slots[0].switch_pin))
548 gpio_free(pdata->slots[0].switch_pin);
549}
550
a45c6cb8
MC		 551/*
552 * Stop clock to the card
553 */
70a3341a 554static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 555{
556 OMAP_HSMMC_WRITE(host->base, SYSCTL,
557 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
558 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
559 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
560}
561
93caf8e6
AH		 562static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
563 struct mmc_command *cmd)
b417577d
AH		 564{
565 unsigned int irq_mask;
566
567 if (host->use_dma)
568 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
569 else
570 irq_mask = INT_EN_MASK;
571
93caf8e6
AH		 572 /* Disable timeout for erases */
573 if (cmd->opcode == MMC_ERASE)
574 irq_mask &= ~DTO_ENABLE;
575
b417577d
AH		 576 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
577 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
578 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
579}
580
581static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
582{
583 OMAP_HSMMC_WRITE(host->base, ISE, 0);
584 OMAP_HSMMC_WRITE(host->base, IE, 0);
585 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
586}
587
11dd62a7
DK		 588#ifdef CONFIG_PM
589
590/*
591 * Restore the MMC host context, if it was lost as result of a
592 * power state change.
593 */
70a3341a 594static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 595{
596 struct mmc_ios *ios = &host->mmc->ios;
597 struct omap_mmc_platform_data *pdata = host->pdata;
598 int context_loss = 0;
599 u32 hctl, capa, con;
600 u16 dsor = 0;
601 unsigned long timeout;
602
603 if (pdata->get_context_loss_count) {
604 context_loss = pdata->get_context_loss_count(host->dev);
605 if (context_loss < 0)
606 return 1;
607 }
608
609 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
610 context_loss == host->context_loss ? "not " : "");
611 if (host->context_loss == context_loss)
612 return 1;
613
614 /* Wait for hardware reset */
615 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
616 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
617 && time_before(jiffies, timeout))
618 ;
619
620 /* Do software reset */
621 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
622 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
623 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
624 && time_before(jiffies, timeout))
625 ;
626
627 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
628 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
629
630 if (host->id == OMAP_MMC1_DEVID) {
631 if (host->power_mode != MMC_POWER_OFF &&
632 (1 << ios->vdd) <= MMC_VDD_23_24)
633 hctl = SDVS18;
634 else
635 hctl = SDVS30;
636 capa = VS30 | VS18;
637 } else {
638 hctl = SDVS18;
639 capa = VS18;
640 }
641
642 OMAP_HSMMC_WRITE(host->base, HCTL,
643 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
644
645 OMAP_HSMMC_WRITE(host->base, CAPA,
646 OMAP_HSMMC_READ(host->base, CAPA) | capa);
647
648 OMAP_HSMMC_WRITE(host->base, HCTL,
649 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
650
651 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
652 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
653 && time_before(jiffies, timeout))
654 ;
655
b417577d 656 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 657
658 /* Do not initialize card-specific things if the power is off */
659 if (host->power_mode == MMC_POWER_OFF)
660 goto out;
661
662 con = OMAP_HSMMC_READ(host->base, CON);
663 switch (ios->bus_width) {
664 case MMC_BUS_WIDTH_8:
665 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
666 break;
667 case MMC_BUS_WIDTH_4:
668 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
669 OMAP_HSMMC_WRITE(host->base, HCTL,
670 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
671 break;
672 case MMC_BUS_WIDTH_1:
673 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
674 OMAP_HSMMC_WRITE(host->base, HCTL,
675 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
676 break;
677 }
678
679 if (ios->clock) {
680 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
681 if (dsor < 1)
682 dsor = 1;
683
684 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
685 dsor++;
686
687 if (dsor > 250)
688 dsor = 250;
689 }
690
691 OMAP_HSMMC_WRITE(host->base, SYSCTL,
692 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
693 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
694 OMAP_HSMMC_WRITE(host->base, SYSCTL,
695 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
696
697 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
698 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
699 && time_before(jiffies, timeout))
700 ;
701
702 OMAP_HSMMC_WRITE(host->base, SYSCTL,
703 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
704
705 con = OMAP_HSMMC_READ(host->base, CON);
706 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
707 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
708 else
709 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
710out:
711 host->context_loss = context_loss;
712
713 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
714 return 0;
715}
716
717/*
718 * Save the MMC host context (store the number of power state changes so far).
719 */
70a3341a 720static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 721{
722 struct omap_mmc_platform_data *pdata = host->pdata;
723 int context_loss;
724
725 if (pdata->get_context_loss_count) {
726 context_loss = pdata->get_context_loss_count(host->dev);
727 if (context_loss < 0)
728 return;
729 host->context_loss = context_loss;
730 }
731}
732
733#else
734
70a3341a 735static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 736{
737 return 0;
738}
739
70a3341a 740static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 741{
742}
743
744#endif
745
a45c6cb8
MC		 746/*
747 * Send init stream sequence to card
748 * before sending IDLE command
749 */
70a3341a 750static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 751{
752 int reg = 0;
753 unsigned long timeout;
754
b62f6228
AH		 755 if (host->protect_card)
756 return;
757
a45c6cb8 758 disable_irq(host->irq);
b417577d
AH		 759
760 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 761 OMAP_HSMMC_WRITE(host->base, CON,
762 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
763 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
764
765 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
766 while ((reg != CC) && time_before(jiffies, timeout))
767 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
768
769 OMAP_HSMMC_WRITE(host->base, CON,
770 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 771
772 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
773 OMAP_HSMMC_READ(host->base, STAT);
774
a45c6cb8
MC		 775 enable_irq(host->irq);
776}
777
778static inline
70a3341a 779int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 780{
781 int r = 1;
782
191d1f1d
DK		 783 if (mmc_slot(host).get_cover_state)
784 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 785 return r;
786}
787
788static ssize_t
70a3341a 789omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 790 char *buf)
791{
792 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 793 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 794
70a3341a
DK		 795 return sprintf(buf, "%s\n",
796 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 797}
798
70a3341a 799static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 800
801static ssize_t
70a3341a 802omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 803 char *buf)
804{
805 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 806 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 807
191d1f1d 808 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 809}
810
70a3341a 811static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 812
813/*
814 * Configure the response type and send the cmd.
815 */
816static void
70a3341a 817omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 818 struct mmc_data *data)
819{
820 int cmdreg = 0, resptype = 0, cmdtype = 0;
821
822 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
823 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
824 host->cmd = cmd;
825
93caf8e6 826 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 827
4a694dc9 828 host->response_busy = 0;
a45c6cb8
MC		 829 if (cmd->flags & MMC_RSP_PRESENT) {
830 if (cmd->flags & MMC_RSP_136)
831 resptype = 1;
4a694dc9
AH		 832 else if (cmd->flags & MMC_RSP_BUSY) {
833 resptype = 3;
834 host->response_busy = 1;
835 } else
a45c6cb8
MC		 836 resptype = 2;
837 }
838
839 /*
840 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
841 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
842 * a val of 0x3, rest 0x0.
843 */
844 if (cmd == host->mrq->stop)
845 cmdtype = 0x3;
846
847 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
848
849 if (data) {
850 cmdreg |= DP_SELECT | MSBS | BCE;
851 if (data->flags & MMC_DATA_READ)
852 cmdreg |= DDIR;
853 else
854 cmdreg &= ~(DDIR);
855 }
856
857 if (host->use_dma)
858 cmdreg |= DMA_EN;
859
b417577d 860 host->req_in_progress = 1;
4dffd7a2 861
a45c6cb8
MC		 862 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
863 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
864}
865
0ccd76d4 866static int
70a3341a 867omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 868{
869 if (data->flags & MMC_DATA_WRITE)
870 return DMA_TO_DEVICE;
871 else
872 return DMA_FROM_DEVICE;
873}
874
b417577d
AH		 875static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
876{
877 int dma_ch;
878
879 spin_lock(&host->irq_lock);
880 host->req_in_progress = 0;
881 dma_ch = host->dma_ch;
882 spin_unlock(&host->irq_lock);
883
884 omap_hsmmc_disable_irq(host);
885 /* Do not complete the request if DMA is still in progress */
886 if (mrq->data && host->use_dma && dma_ch != -1)
887 return;
888 host->mrq = NULL;
889 mmc_request_done(host->mmc, mrq);
890}
891
a45c6cb8
MC		 892/*
893 * Notify the transfer complete to MMC core
894 */
895static void
70a3341a 896omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 897{
4a694dc9
AH		 898 if (!data) {
899 struct mmc_request *mrq = host->mrq;
900
23050103
AH		 901 /* TC before CC from CMD6 - don't know why, but it happens */
902 if (host->cmd && host->cmd->opcode == 6 &&
903 host->response_busy) {
904 host->response_busy = 0;
905 return;
906 }
907
b417577d 908 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 909 return;
910 }
911
a45c6cb8
MC		 912 host->data = NULL;
913
a45c6cb8
MC		 914 if (!data->error)
915 data->bytes_xfered += data->blocks * (data->blksz);
916 else
917 data->bytes_xfered = 0;
918
919 if (!data->stop) {
b417577d 920 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 921 return;
922 }
70a3341a 923 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 924}
925
926/*
927 * Notify the core about command completion
928 */
929static void
70a3341a 930omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 931{
932 host->cmd = NULL;
933
934 if (cmd->flags & MMC_RSP_PRESENT) {
935 if (cmd->flags & MMC_RSP_136) {
936 /* response type 2 */
937 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
938 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
939 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
940 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
941 } else {
942 /* response types 1, 1b, 3, 4, 5, 6 */
943 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
944 }
945 }
b417577d
AH		 946 if ((host->data == NULL && !host->response_busy) || cmd->error)
947 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 948}
949
950/*
951 * DMA clean up for command errors
952 */
70a3341a 953static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 954{
b417577d
AH		 955 int dma_ch;
956
82788ff5 957 host->data->error = errno;
a45c6cb8 958
b417577d
AH		 959 spin_lock(&host->irq_lock);
960 dma_ch = host->dma_ch;
961 host->dma_ch = -1;
962 spin_unlock(&host->irq_lock);
963
964 if (host->use_dma && dma_ch != -1) {
a9120c33
PF		 965 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
966 host->data->sg_len,
70a3341a 967 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 968 omap_free_dma(dma_ch);
a45c6cb8
MC		 969 }
970 host->data = NULL;
a45c6cb8
MC		 971}
972
973/*
974 * Readable error output
975 */
976#ifdef CONFIG_MMC_DEBUG
70a3341a 977static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 978{
979 /* --- means reserved bit without definition at documentation */
70a3341a 980 static const char *omap_hsmmc_status_bits[] = {
a45c6cb8
MC		 981 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
982 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
983 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
984 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
985 };
986 char res[256];
987 char *buf = res;
988 int len, i;
989
990 len = sprintf(buf, "MMC IRQ 0x%x :", status);
991 buf += len;
992
70a3341a 993 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 994 if (status & (1 << i)) {
70a3341a 995 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 996 buf += len;
997 }
998
999 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1000}
1001#endif /* CONFIG_MMC_DEBUG */
1002
3ebf74b1
JP		 1003/*
1004 * MMC controller internal state machines reset
1005 *
1006 * Used to reset command or data internal state machines, using respectively
1007 * SRC or SRD bit of SYSCTL register
1008 * Can be called from interrupt context
1009 */
70a3341a
DK		 1010static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1011 unsigned long bit)
3ebf74b1
JP		 1012{
1013 unsigned long i = 0;
1014 unsigned long limit = (loops_per_jiffy *
1015 msecs_to_jiffies(MMC_TIMEOUT_MS));
1016
1017 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1018 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1019
07ad64b6
MC		 1020 /*
1021 * OMAP4 ES2 and greater has an updated reset logic.
1022 * Monitor a 0->1 transition first
1023 */
1024 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1025 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 1026 && (i++ < limit))
1027 cpu_relax();
1028 }
1029 i = 0;
1030
3ebf74b1
JP		 1031 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1032 (i++ < limit))
1033 cpu_relax();
1034
1035 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1036 dev_err(mmc_dev(host->mmc),
1037 "Timeout waiting on controller reset in %s\n",
1038 __func__);
1039}
a45c6cb8 1040
b417577d 1041static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1042{
a45c6cb8 1043 struct mmc_data *data;
b417577d
AH		 1044 int end_cmd = 0, end_trans = 0;
1045
1046 if (!host->req_in_progress) {
1047 do {
1048 OMAP_HSMMC_WRITE(host->base, STAT, status);
1049 /* Flush posted write */
1050 status = OMAP_HSMMC_READ(host->base, STAT);
1051 } while (status & INT_EN_MASK);
1052 return;
a45c6cb8
MC		 1053 }
1054
1055 data = host->data;
a45c6cb8
MC		 1056 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1057
1058 if (status & ERR) {
1059#ifdef CONFIG_MMC_DEBUG
70a3341a 1060 omap_hsmmc_report_irq(host, status);
a45c6cb8
MC		 1061#endif
1062 if ((status & CMD_TIMEOUT) ||
1063 (status & CMD_CRC)) {
1064 if (host->cmd) {
1065 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1066 omap_hsmmc_reset_controller_fsm(host,
1067 SRC);
a45c6cb8
MC		 1068 host->cmd->error = -ETIMEDOUT;
1069 } else {
1070 host->cmd->error = -EILSEQ;
1071 }
1072 end_cmd = 1;
1073 }
4a694dc9
AH		 1074 if (host->data || host->response_busy) {
1075 if (host->data)
70a3341a
DK		 1076 omap_hsmmc_dma_cleanup(host,
1077 -ETIMEDOUT);
4a694dc9 1078 host->response_busy = 0;
70a3341a 1079 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1080 }
a45c6cb8
MC		 1081 }
1082 if ((status & DATA_TIMEOUT) ||
1083 (status & DATA_CRC)) {
4a694dc9
AH		 1084 if (host->data || host->response_busy) {
1085 int err = (status & DATA_TIMEOUT) ?
1086 -ETIMEDOUT : -EILSEQ;
1087
1088 if (host->data)
70a3341a 1089 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1090 else
4a694dc9
AH		 1091 host->mrq->cmd->error = err;
1092 host->response_busy = 0;
70a3341a 1093 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1094 end_trans = 1;
1095 }
1096 }
1097 if (status & CARD_ERR) {
1098 dev_dbg(mmc_dev(host->mmc),
1099 "Ignoring card err CMD%d\n", host->cmd->opcode);
1100 if (host->cmd)
1101 end_cmd = 1;
1102 if (host->data)
1103 end_trans = 1;
1104 }
1105 }
1106
1107 OMAP_HSMMC_WRITE(host->base, STAT, status);
1108
a8fe29d8 1109 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1110 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1111 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1112 omap_hsmmc_xfer_done(host, data);
b417577d 1113}
a45c6cb8 1114
b417577d
AH		 1115/*
1116 * MMC controller IRQ handler
1117 */
1118static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1119{
1120 struct omap_hsmmc_host *host = dev_id;
1121 int status;
1122
1123 status = OMAP_HSMMC_READ(host->base, STAT);
1124 do {
1125 omap_hsmmc_do_irq(host, status);
1126 /* Flush posted write */
1127 status = OMAP_HSMMC_READ(host->base, STAT);
1128 } while (status & INT_EN_MASK);
4dffd7a2 1129
a45c6cb8
MC		 1130 return IRQ_HANDLED;
1131}
1132
70a3341a 1133static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1134{
1135 unsigned long i;
1136
1137 OMAP_HSMMC_WRITE(host->base, HCTL,
1138 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1139 for (i = 0; i < loops_per_jiffy; i++) {
1140 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1141 break;
1142 cpu_relax();
1143 }
1144}
1145
a45c6cb8 1146/*
eb250826
DB		 1147 * Switch MMC interface voltage ... only relevant for MMC1.
1148 *
1149 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1150 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1151 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1152 */
70a3341a 1153static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1154{
1155 u32 reg_val = 0;
1156 int ret;
1157
1158 /* Disable the clocks */
1159 clk_disable(host->fclk);
1160 clk_disable(host->iclk);
2bec0893
AH		 1161 if (host->got_dbclk)
1162 clk_disable(host->dbclk);
a45c6cb8
MC		 1163
1164 /* Turn the power off */
1165 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1166
1167 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1168 if (!ret)
1169 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1170 vdd);
1171 clk_enable(host->iclk);
1172 clk_enable(host->fclk);
1173 if (host->got_dbclk)
1174 clk_enable(host->dbclk);
1175
a45c6cb8
MC		 1176 if (ret != 0)
1177 goto err;
1178
a45c6cb8
MC		 1179 OMAP_HSMMC_WRITE(host->base, HCTL,
1180 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1181 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1182
a45c6cb8
MC		 1183 /*
1184 * If a MMC dual voltage card is detected, the set_ios fn calls
1185 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1186 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1187 *
eb250826
DB		 1188 * Cope with a bit of slop in the range ... per data sheets:
1189 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1190 * but recommended values are 1.71V to 1.89V
1191 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1192 * but recommended values are 2.7V to 3.3V
1193 *
1194 * Board setup code shouldn't permit anything very out-of-range.
1195 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1196 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1197 */
eb250826 1198 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1199 reg_val |= SDVS18;
eb250826
DB		 1200 else
1201 reg_val |= SDVS30;
a45c6cb8
MC		 1202
1203 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1204 set_sd_bus_power(host);
a45c6cb8
MC		 1205
1206 return 0;
1207err:
1208 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1209 return ret;
1210}
1211
b62f6228
AH		 1212/* Protect the card while the cover is open */
1213static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1214{
1215 if (!mmc_slot(host).get_cover_state)
1216 return;
1217
1218 host->reqs_blocked = 0;
1219 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1220 if (host->protect_card) {
1221 printk(KERN_INFO "%s: cover is closed, "
1222 "card is now accessible\n",
1223 mmc_hostname(host->mmc));
1224 host->protect_card = 0;
1225 }
1226 } else {
1227 if (!host->protect_card) {
1228 printk(KERN_INFO "%s: cover is open, "
1229 "card is now inaccessible\n",
1230 mmc_hostname(host->mmc));
1231 host->protect_card = 1;
1232 }
1233 }
1234}
1235
a45c6cb8
MC		 1236/*
1237 * Work Item to notify the core about card insertion/removal
1238 */
70a3341a 1239static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1240{
70a3341a
DK		 1241 struct omap_hsmmc_host *host =
1242 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1243 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1244 int carddetect;
1245
1246 if (host->suspended)
1247 return;
1248
1249 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1250
191d1f1d 1251 if (slot->card_detect)
db0fefc5 1252 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1253 else {
1254 omap_hsmmc_protect_card(host);
a6b2240d 1255 carddetect = -ENOSYS;
b62f6228 1256 }
a45c6cb8 1257
cdeebadd 1258 if (carddetect)
a45c6cb8 1259 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1260 else
a45c6cb8 1261 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1262}
1263
1264/*
1265 * ISR for handling card insertion and removal
1266 */
70a3341a 1267static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1268{
70a3341a 1269 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1270
a6b2240d
AH		 1271 if (host->suspended)
1272 return IRQ_HANDLED;
a45c6cb8
MC		 1273 schedule_work(&host->mmc_carddetect_work);
1274
1275 return IRQ_HANDLED;
1276}
1277
70a3341a 1278static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1279 struct mmc_data *data)
1280{
1281 int sync_dev;
1282
f3e2f1dd
GI		 1283 if (data->flags & MMC_DATA_WRITE)
1284 sync_dev = host->dma_line_tx;
1285 else
1286 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1287 return sync_dev;
1288}
1289
70a3341a 1290static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1291 struct mmc_data *data,
1292 struct scatterlist *sgl)
1293{
1294 int blksz, nblk, dma_ch;
1295
1296 dma_ch = host->dma_ch;
1297 if (data->flags & MMC_DATA_WRITE) {
1298 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1299 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1300 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1301 sg_dma_address(sgl), 0, 0);
1302 } else {
1303 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1304 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1305 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1306 sg_dma_address(sgl), 0, 0);
1307 }
1308
1309 blksz = host->data->blksz;
1310 nblk = sg_dma_len(sgl) / blksz;
1311
1312 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1313 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1314 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1315 !(data->flags & MMC_DATA_WRITE));
1316
1317 omap_start_dma(dma_ch);
1318}
1319
a45c6cb8
MC		 1320/*
1321 * DMA call back function
1322 */
b417577d 1323static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1324{
b417577d
AH		 1325 struct omap_hsmmc_host *host = cb_data;
1326 struct mmc_data *data = host->mrq->data;
1327 int dma_ch, req_in_progress;
a45c6cb8 1328
f3584e5e
V		 1329 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1330 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1331 ch_status);
1332 return;
1333 }
a45c6cb8 1334
b417577d
AH		 1335 spin_lock(&host->irq_lock);
1336 if (host->dma_ch < 0) {
1337 spin_unlock(&host->irq_lock);
a45c6cb8 1338 return;
b417577d 1339 }
a45c6cb8 1340
0ccd76d4
JY		 1341 host->dma_sg_idx++;
1342 if (host->dma_sg_idx < host->dma_len) {
1343 /* Fire up the next transfer. */
b417577d
AH		 1344 omap_hsmmc_config_dma_params(host, data,
1345 data->sg + host->dma_sg_idx);
1346 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1347 return;
1348 }
1349
9782aff8
PF		 1350 if (!data->host_cookie)
1351 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1352 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1353
1354 req_in_progress = host->req_in_progress;
1355 dma_ch = host->dma_ch;
a45c6cb8 1356 host->dma_ch = -1;
b417577d
AH		 1357 spin_unlock(&host->irq_lock);
1358
1359 omap_free_dma(dma_ch);
1360
1361 /* If DMA has finished after TC, complete the request */
1362 if (!req_in_progress) {
1363 struct mmc_request *mrq = host->mrq;
1364
1365 host->mrq = NULL;
1366 mmc_request_done(host->mmc, mrq);
1367 }
a45c6cb8
MC		 1368}
1369
9782aff8
PF		 1370static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1371 struct mmc_data *data,
1372 struct omap_hsmmc_next *next)
1373{
1374 int dma_len;
1375
1376 if (!next && data->host_cookie &&
1377 data->host_cookie != host->next_data.cookie) {
1378 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1379 " host->next_data.cookie %d\n",
1380 __func__, data->host_cookie, host->next_data.cookie);
1381 data->host_cookie = 0;
1382 }
1383
1384 /* Check if next job is already prepared */
1385 if (next ||
1386 (!next && data->host_cookie != host->next_data.cookie)) {
1387 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1388 data->sg_len,
1389 omap_hsmmc_get_dma_dir(host, data));
1390
1391 } else {
1392 dma_len = host->next_data.dma_len;
1393 host->next_data.dma_len = 0;
1394 }
1395
1396
1397 if (dma_len == 0)
1398 return -EINVAL;
1399
1400 if (next) {
1401 next->dma_len = dma_len;
1402 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1403 } else
1404 host->dma_len = dma_len;
1405
1406 return 0;
1407}
1408
a45c6cb8
MC		 1409/*
1410 * Routine to configure and start DMA for the MMC card
1411 */
70a3341a
DK		 1412static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1413 struct mmc_request *req)
a45c6cb8 1414{
b417577d 1415 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1416 struct mmc_data *data = req->data;
1417
0ccd76d4 1418 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1419 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1420 struct scatterlist *sgl;
1421
1422 sgl = data->sg + i;
1423 if (sgl->length % data->blksz)
1424 return -EINVAL;
1425 }
1426 if ((data->blksz % 4) != 0)
1427 /* REVISIT: The MMC buffer increments only when MSB is written.
1428 * Return error for blksz which is non multiple of four.
1429 */
1430 return -EINVAL;
1431
b417577d 1432 BUG_ON(host->dma_ch != -1);
a45c6cb8 1433
70a3341a
DK		 1434 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1435 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1436 if (ret != 0) {
0ccd76d4 1437 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1438 "%s: omap_request_dma() failed with %d\n",
1439 mmc_hostname(host->mmc), ret);
1440 return ret;
1441 }
9782aff8
PF		 1442 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1443 if (ret)
1444 return ret;
a45c6cb8 1445
a45c6cb8 1446 host->dma_ch = dma_ch;
0ccd76d4 1447 host->dma_sg_idx = 0;
a45c6cb8 1448
70a3341a 1449 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1450
a45c6cb8
MC		 1451 return 0;
1452}
1453
70a3341a 1454static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1455 unsigned int timeout_ns,
1456 unsigned int timeout_clks)
a45c6cb8
MC		 1457{
1458 unsigned int timeout, cycle_ns;
1459 uint32_t reg, clkd, dto = 0;
1460
1461 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1462 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1463 if (clkd == 0)
1464 clkd = 1;
1465
1466 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1467 timeout = timeout_ns / cycle_ns;
1468 timeout += timeout_clks;
a45c6cb8
MC		 1469 if (timeout) {
1470 while ((timeout & 0x80000000) == 0) {
1471 dto += 1;
1472 timeout <<= 1;
1473 }
1474 dto = 31 - dto;
1475 timeout <<= 1;
1476 if (timeout && dto)
1477 dto += 1;
1478 if (dto >= 13)
1479 dto -= 13;
1480 else
1481 dto = 0;
1482 if (dto > 14)
1483 dto = 14;
1484 }
1485
1486 reg &= ~DTO_MASK;
1487 reg |= dto << DTO_SHIFT;
1488 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1489}
1490
1491/*
1492 * Configure block length for MMC/SD cards and initiate the transfer.
1493 */
1494static int
70a3341a 1495omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1496{
1497 int ret;
1498 host->data = req->data;
1499
1500 if (req->data == NULL) {
a45c6cb8 1501 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1502 /*
1503 * Set an arbitrary 100ms data timeout for commands with
1504 * busy signal.
1505 */
1506 if (req->cmd->flags & MMC_RSP_BUSY)
1507 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1508 return 0;
1509 }
1510
1511 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1512 | (req->data->blocks << 16));
e2bf08d6 1513 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1514
a45c6cb8 1515 if (host->use_dma) {
70a3341a 1516 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1517 if (ret != 0) {
1518 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1519 return ret;
1520 }
1521 }
1522 return 0;
1523}
1524
9782aff8
PF		 1525static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1526 int err)
1527{
1528 struct omap_hsmmc_host *host = mmc_priv(mmc);
1529 struct mmc_data *data = mrq->data;
1530
1531 if (host->use_dma) {
1532 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1533 omap_hsmmc_get_dma_dir(host, data));
1534 data->host_cookie = 0;
1535 }
1536}
1537
1538static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1539 bool is_first_req)
1540{
1541 struct omap_hsmmc_host *host = mmc_priv(mmc);
1542
1543 if (mrq->data->host_cookie) {
1544 mrq->data->host_cookie = 0;
1545 return ;
1546 }
1547
1548 if (host->use_dma)
1549 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1550 &host->next_data))
1551 mrq->data->host_cookie = 0;
1552}
1553
a45c6cb8
MC		 1554/*
1555 * Request function. for read/write operation
1556 */
70a3341a 1557static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1558{
70a3341a 1559 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1560 int err;
a45c6cb8 1561
b417577d
AH		 1562 BUG_ON(host->req_in_progress);
1563 BUG_ON(host->dma_ch != -1);
1564 if (host->protect_card) {
1565 if (host->reqs_blocked < 3) {
1566 /*
1567 * Ensure the controller is left in a consistent
1568 * state by resetting the command and data state
1569 * machines.
1570 */
1571 omap_hsmmc_reset_controller_fsm(host, SRD);
1572 omap_hsmmc_reset_controller_fsm(host, SRC);
1573 host->reqs_blocked += 1;
1574 }
1575 req->cmd->error = -EBADF;
1576 if (req->data)
1577 req->data->error = -EBADF;
1578 req->cmd->retries = 0;
1579 mmc_request_done(mmc, req);
1580 return;
1581 } else if (host->reqs_blocked)
1582 host->reqs_blocked = 0;
a45c6cb8
MC		 1583 WARN_ON(host->mrq != NULL);
1584 host->mrq = req;
70a3341a 1585 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1586 if (err) {
1587 req->cmd->error = err;
1588 if (req->data)
1589 req->data->error = err;
1590 host->mrq = NULL;
1591 mmc_request_done(mmc, req);
1592 return;
1593 }
1594
70a3341a 1595 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1596}
1597
a45c6cb8 1598/* Routine to configure clock values. Exposed API to core */
70a3341a 1599static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1600{
70a3341a 1601 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8
MC		 1602 u16 dsor = 0;
1603 unsigned long regval;
1604 unsigned long timeout;
73153010 1605 u32 con;
a3621465 1606 int do_send_init_stream = 0;
a45c6cb8 1607
5e2ea617
AH		 1608 mmc_host_enable(host->mmc);
1609
a3621465
AH		 1610 if (ios->power_mode != host->power_mode) {
1611 switch (ios->power_mode) {
1612 case MMC_POWER_OFF:
1613 mmc_slot(host).set_power(host->dev, host->slot_id,
1614 0, 0);
623821f7 1615 host->vdd = 0;
a3621465
AH		 1616 break;
1617 case MMC_POWER_UP:
1618 mmc_slot(host).set_power(host->dev, host->slot_id,
1619 1, ios->vdd);
623821f7 1620 host->vdd = ios->vdd;
a3621465
AH		 1621 break;
1622 case MMC_POWER_ON:
1623 do_send_init_stream = 1;
1624 break;
1625 }
1626 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1627 }
1628
dd498eff
DK		 1629 /* FIXME: set registers based only on changes to ios */
1630
73153010 1631 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1632 switch (mmc->ios.bus_width) {
73153010
JL		 1633 case MMC_BUS_WIDTH_8:
1634 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1635 break;
a45c6cb8 1636 case MMC_BUS_WIDTH_4:
73153010 1637 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1638 OMAP_HSMMC_WRITE(host->base, HCTL,
1639 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1640 break;
1641 case MMC_BUS_WIDTH_1:
73153010 1642 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1643 OMAP_HSMMC_WRITE(host->base, HCTL,
1644 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1645 break;
1646 }
1647
4621d5f8 1648 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1649 /* Only MMC1 can interface at 3V without some flavor
1650 * of external transceiver; but they all handle 1.8V.
1651 */
a45c6cb8
MC		 1652 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1653 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1654 /*
1655 * The mmc_select_voltage fn of the core does
1656 * not seem to set the power_mode to
1657 * MMC_POWER_UP upon recalculating the voltage.
1658 * vdd 1.8v.
1659 */
70a3341a
DK		 1660 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1661 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1662 "Switch operation failed\n");
1663 }
1664 }
1665
1666 if (ios->clock) {
1667 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1668 if (dsor < 1)
1669 dsor = 1;
1670
1671 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1672 dsor++;
1673
1674 if (dsor > 250)
1675 dsor = 250;
1676 }
70a3341a 1677 omap_hsmmc_stop_clock(host);
a45c6cb8
MC		 1678 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1679 regval = regval & ~(CLKD_MASK);
1680 regval = regval | (dsor << 6) | (DTO << 16);
1681 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1682 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1683 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1684
1685 /* Wait till the ICS bit is set */
1686 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1687 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1688 && time_before(jiffies, timeout))
1689 msleep(1);
1690
1691 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1692 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1693
a3621465 1694 if (do_send_init_stream)
a45c6cb8
MC		 1695 send_init_stream(host);
1696
abb28e73 1697 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1698 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1699 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1700 else
1701 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1702
dd498eff
DK		 1703 if (host->power_mode == MMC_POWER_OFF)
1704 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1705}
1706
1707static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1708{
70a3341a 1709 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1710
191d1f1d 1711 if (!mmc_slot(host).card_detect)
a45c6cb8 1712 return -ENOSYS;
db0fefc5 1713 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1714}
1715
1716static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1717{
70a3341a 1718 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1719
191d1f1d 1720 if (!mmc_slot(host).get_ro)
a45c6cb8 1721 return -ENOSYS;
191d1f1d 1722 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1723}
1724
4816858c
GI		 1725static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1726{
1727 struct omap_hsmmc_host *host = mmc_priv(mmc);
1728
1729 if (mmc_slot(host).init_card)
1730 mmc_slot(host).init_card(card);
1731}
1732
70a3341a 1733static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1734{
1735 u32 hctl, capa, value;
1736
1737 /* Only MMC1 supports 3.0V */
4621d5f8 1738 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1739 hctl = SDVS30;
1740 capa = VS30 | VS18;
1741 } else {
1742 hctl = SDVS18;
1743 capa = VS18;
1744 }
1745
1746 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1747 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1748
1749 value = OMAP_HSMMC_READ(host->base, CAPA);
1750 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1751
1752 /* Set the controller to AUTO IDLE mode */
1753 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1754 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1755
1756 /* Set SD bus power bit */
e13bb300 1757 set_sd_bus_power(host);
1b331e69
KK		 1758}
1759
70a3341a 1760static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1761{
70a3341a 1762 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1763 int err;
1764
1765 err = clk_enable(host->fclk);
1766 if (err)
1767 return err;
1768 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
70a3341a 1769 omap_hsmmc_context_restore(host);
dd498eff
DK		 1770 return 0;
1771}
1772
70a3341a 1773static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1774{
70a3341a 1775 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1776
70a3341a 1777 omap_hsmmc_context_save(host);
dd498eff
DK		 1778 clk_disable(host->fclk);
1779 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1780 return 0;
1781}
1782
70a3341a
DK		 1783static const struct mmc_host_ops omap_hsmmc_ops = {
1784 .enable = omap_hsmmc_enable_fclk,
1785 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1786 .post_req = omap_hsmmc_post_req,
1787 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1788 .request = omap_hsmmc_request,
1789 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1790 .get_cd = omap_hsmmc_get_cd,
1791 .get_ro = omap_hsmmc_get_ro,
4816858c 1792 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1793 /* NYET -- enable_sdio_irq */
1794};
1795
d900f712
DK		 1796#ifdef CONFIG_DEBUG_FS
1797
70a3341a 1798static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1799{
1800 struct mmc_host *mmc = s->private;
70a3341a 1801 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1802 int context_loss = 0;
1803
70a3341a
DK		 1804 if (host->pdata->get_context_loss_count)
1805 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1806
5e2ea617
AH		 1807 seq_printf(s, "mmc%d:\n"
1808 " enabled:\t%d\n"
dd498eff 1809 " dpm_state:\t%d\n"
5e2ea617 1810 " nesting_cnt:\t%d\n"
11dd62a7 1811 " ctx_loss:\t%d:%d\n"
5e2ea617 1812 "\nregs:\n",
dd498eff
DK		 1813 mmc->index, mmc->enabled ? 1 : 0,
1814 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1815 host->context_loss, context_loss);
5e2ea617 1816
7a8c2cef 1817 if (host->suspended) {
dd498eff
DK		 1818 seq_printf(s, "host suspended, can't read registers\n");
1819 return 0;
1820 }
1821
5e2ea617
AH		 1822 if (clk_enable(host->fclk) != 0) {
1823 seq_printf(s, "can't read the regs\n");
dd498eff 1824 return 0;
5e2ea617 1825 }
d900f712
DK		 1826
1827 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1828 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1829 seq_printf(s, "CON:\t\t0x%08x\n",
1830 OMAP_HSMMC_READ(host->base, CON));
1831 seq_printf(s, "HCTL:\t\t0x%08x\n",
1832 OMAP_HSMMC_READ(host->base, HCTL));
1833 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1834 OMAP_HSMMC_READ(host->base, SYSCTL));
1835 seq_printf(s, "IE:\t\t0x%08x\n",
1836 OMAP_HSMMC_READ(host->base, IE));
1837 seq_printf(s, "ISE:\t\t0x%08x\n",
1838 OMAP_HSMMC_READ(host->base, ISE));
1839 seq_printf(s, "CAPA:\t\t0x%08x\n",
1840 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1841
1842 clk_disable(host->fclk);
dd498eff 1843
d900f712
DK		 1844 return 0;
1845}
1846
70a3341a 1847static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1848{
70a3341a 1849 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1850}
1851
1852static const struct file_operations mmc_regs_fops = {
70a3341a 1853 .open = omap_hsmmc_regs_open,
d900f712
DK		 1854 .read = seq_read,
1855 .llseek = seq_lseek,
1856 .release = single_release,
1857};
1858
70a3341a 1859static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1860{
1861 if (mmc->debugfs_root)
1862 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1863 mmc, &mmc_regs_fops);
1864}
1865
1866#else
1867
70a3341a 1868static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1869{
1870}
1871
1872#endif
1873
70a3341a 1874static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1875{
1876 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1877 struct mmc_host *mmc;
70a3341a 1878 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1879 struct resource *res;
db0fefc5 1880 int ret, irq;
a45c6cb8
MC		 1881
1882 if (pdata == NULL) {
1883 dev_err(&pdev->dev, "Platform Data is missing\n");
1884 return -ENXIO;
1885 }
1886
1887 if (pdata->nr_slots == 0) {
1888 dev_err(&pdev->dev, "No Slots\n");
1889 return -ENXIO;
1890 }
1891
1892 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1893 irq = platform_get_irq(pdev, 0);
1894 if (res == NULL || irq < 0)
1895 return -ENXIO;
1896
91a0b089 1897 res->start += pdata->reg_offset;
1898 res->end += pdata->reg_offset;
984b203a 1899 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1900 if (res == NULL)
1901 return -EBUSY;
1902
db0fefc5
AH		 1903 ret = omap_hsmmc_gpio_init(pdata);
1904 if (ret)
1905 goto err;
1906
70a3341a 1907 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1908 if (!mmc) {
1909 ret = -ENOMEM;
db0fefc5 1910 goto err_alloc;
a45c6cb8
MC		 1911 }
1912
1913 host = mmc_priv(mmc);
1914 host->mmc = mmc;
1915 host->pdata = pdata;
1916 host->dev = &pdev->dev;
1917 host->use_dma = 1;
1918 host->dev->dma_mask = &pdata->dma_mask;
1919 host->dma_ch = -1;
1920 host->irq = irq;
1921 host->id = pdev->id;
1922 host->slot_id = 0;
1923 host->mapbase = res->start;
1924 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1925 host->power_mode = MMC_POWER_OFF;
9782aff8 1926 host->next_data.cookie = 1;
a45c6cb8
MC		 1927
1928 platform_set_drvdata(pdev, host);
70a3341a 1929 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 1930
7a8c2cef 1931 mmc->ops = &omap_hsmmc_ops;
dd498eff 1932
e0eb2424
AH		 1933 /*
1934 * If regulator_disable can only put vcc_aux to sleep then there is
1935 * no off state.
1936 */
1937 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1938 mmc_slot(host).no_off = 1;
1939
a45c6cb8
MC		 1940 mmc->f_min = 400000;
1941 mmc->f_max = 52000000;
1942
4dffd7a2 1943 spin_lock_init(&host->irq_lock);
a45c6cb8 1944
6f7607cc 1945 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 1946 if (IS_ERR(host->iclk)) {
1947 ret = PTR_ERR(host->iclk);
1948 host->iclk = NULL;
1949 goto err1;
1950 }
6f7607cc 1951 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1952 if (IS_ERR(host->fclk)) {
1953 ret = PTR_ERR(host->fclk);
1954 host->fclk = NULL;
1955 clk_put(host->iclk);
1956 goto err1;
1957 }
1958
70a3341a 1959 omap_hsmmc_context_save(host);
11dd62a7 1960
5e2ea617 1961 mmc->caps |= MMC_CAP_DISABLE;
dd498eff 1962
a05dcdb9 1963 if (clk_enable(host->iclk) != 0) {
a45c6cb8
MC		 1964 clk_put(host->iclk);
1965 clk_put(host->fclk);
1966 goto err1;
1967 }
1968
a05dcdb9
PW		 1969 if (mmc_host_enable(host->mmc) != 0) {
1970 clk_disable(host->iclk);
a45c6cb8
MC		 1971 clk_put(host->iclk);
1972 clk_put(host->fclk);
1973 goto err1;
1974 }
1975
2bec0893
AH		 1976 if (cpu_is_omap2430()) {
1977 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1978 /*
1979 * MMC can still work without debounce clock.
1980 */
1981 if (IS_ERR(host->dbclk))
1982 dev_warn(mmc_dev(host->mmc),
1983 "Failed to get debounce clock\n");
a45c6cb8 1984 else
2bec0893
AH		 1985 host->got_dbclk = 1;
1986
1987 if (host->got_dbclk)
1988 if (clk_enable(host->dbclk) != 0)
1989 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1990 " clk failed\n");
1991 }
a45c6cb8 1992
0ccd76d4
JY		 1993 /* Since we do only SG emulation, we can have as many segs
1994 * as we want. */
a36274e0 1995 mmc->max_segs = 1024;
0ccd76d4 1996
a45c6cb8
MC		 1997 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1998 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1999 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2000 mmc->max_seg_size = mmc->max_req_size;
2001
13189e78 2002 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 2003 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 2004
3a63833e
SG		 2005 mmc->caps |= mmc_slot(host).caps;
2006 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 2007 mmc->caps |= MMC_CAP_4_BIT_DATA;
2008
191d1f1d 2009 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 2010 mmc->caps |= MMC_CAP_NONREMOVABLE;
2011
70a3341a 2012 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2013
f3e2f1dd
GI		 2014 /* Select DMA lines */
2015 switch (host->id) {
2016 case OMAP_MMC1_DEVID:
2017 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2018 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2019 break;
2020 case OMAP_MMC2_DEVID:
2021 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2022 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2023 break;
2024 case OMAP_MMC3_DEVID:
2025 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2026 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2027 break;
82cf818d 2028 case OMAP_MMC4_DEVID:
2029 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2030 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2031 break;
2032 case OMAP_MMC5_DEVID:
2033 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2034 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2035 break;
f3e2f1dd
GI		 2036 default:
2037 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2038 goto err_irq;
2039 }
a45c6cb8
MC		 2040
2041 /* Request IRQ for MMC operations */
70a3341a 2042 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
a45c6cb8
MC		 2043 mmc_hostname(mmc), host);
2044 if (ret) {
2045 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2046 goto err_irq;
2047 }
2048
2049 if (pdata->init != NULL) {
2050 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2051 dev_dbg(mmc_dev(host->mmc),
2052 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2053 goto err_irq_cd_init;
2054 }
2055 }
db0fefc5 2056
b702b106 2057 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 2058 ret = omap_hsmmc_reg_get(host);
2059 if (ret)
2060 goto err_reg;
2061 host->use_reg = 1;
2062 }
2063
b583f26d 2064 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2065
2066 /* Request IRQ for card detect */
e1a55f5e 2067 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2068 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2069 omap_hsmmc_cd_handler,
a45c6cb8
MC		 2070 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2071 | IRQF_DISABLED,
2072 mmc_hostname(mmc), host);
2073 if (ret) {
2074 dev_dbg(mmc_dev(host->mmc),
2075 "Unable to grab MMC CD IRQ\n");
2076 goto err_irq_cd;
2077 }
72f2e2c7 2078 pdata->suspend = omap_hsmmc_suspend_cdirq;
2079 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 2080 }
2081
b417577d 2082 omap_hsmmc_disable_irq(host);
a45c6cb8 2083
b62f6228
AH		 2084 omap_hsmmc_protect_card(host);
2085
a45c6cb8
MC		 2086 mmc_add_host(mmc);
2087
191d1f1d 2088 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2089 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2090 if (ret < 0)
2091 goto err_slot_name;
2092 }
191d1f1d 2093 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2094 ret = device_create_file(&mmc->class_dev,
2095 &dev_attr_cover_switch);
2096 if (ret < 0)
db0fefc5 2097 goto err_slot_name;
a45c6cb8
MC		 2098 }
2099
70a3341a 2100 omap_hsmmc_debugfs(mmc);
d900f712 2101
a45c6cb8
MC		 2102 return 0;
2103
a45c6cb8
MC		 2104err_slot_name:
2105 mmc_remove_host(mmc);
a45c6cb8 2106 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2107err_irq_cd:
2108 if (host->use_reg)
2109 omap_hsmmc_reg_put(host);
2110err_reg:
2111 if (host->pdata->cleanup)
2112 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2113err_irq_cd_init:
2114 free_irq(host->irq, host);
2115err_irq:
5e2ea617 2116 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2117 clk_disable(host->iclk);
2118 clk_put(host->fclk);
2119 clk_put(host->iclk);
2bec0893 2120 if (host->got_dbclk) {
a45c6cb8
MC		 2121 clk_disable(host->dbclk);
2122 clk_put(host->dbclk);
2123 }
a45c6cb8
MC		 2124err1:
2125 iounmap(host->base);
db0fefc5
AH		 2126 platform_set_drvdata(pdev, NULL);
2127 mmc_free_host(mmc);
2128err_alloc:
2129 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2130err:
984b203a 2131 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2132 return ret;
2133}
2134
70a3341a 2135static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2136{
70a3341a 2137 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2138 struct resource *res;
2139
2140 if (host) {
5e2ea617 2141 mmc_host_enable(host->mmc);
a45c6cb8 2142 mmc_remove_host(host->mmc);
db0fefc5
AH		 2143 if (host->use_reg)
2144 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2145 if (host->pdata->cleanup)
2146 host->pdata->cleanup(&pdev->dev);
2147 free_irq(host->irq, host);
2148 if (mmc_slot(host).card_detect_irq)
2149 free_irq(mmc_slot(host).card_detect_irq, host);
0d9ee5b2 2150 flush_work_sync(&host->mmc_carddetect_work);
a45c6cb8 2151
5e2ea617 2152 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2153 clk_disable(host->iclk);
2154 clk_put(host->fclk);
2155 clk_put(host->iclk);
2bec0893 2156 if (host->got_dbclk) {
a45c6cb8
MC		 2157 clk_disable(host->dbclk);
2158 clk_put(host->dbclk);
2159 }
2160
2161 mmc_free_host(host->mmc);
2162 iounmap(host->base);
db0fefc5 2163 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2164 }
2165
2166 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2167 if (res)
984b203a 2168 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2169 platform_set_drvdata(pdev, NULL);
2170
2171 return 0;
2172}
2173
2174#ifdef CONFIG_PM
a791daa1 2175static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2176{
2177 int ret = 0;
a791daa1 2178 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2179 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2180
2181 if (host && host->suspended)
2182 return 0;
2183
2184 if (host) {
a6b2240d
AH		 2185 host->suspended = 1;
2186 if (host->pdata->suspend) {
2187 ret = host->pdata->suspend(&pdev->dev,
2188 host->slot_id);
2189 if (ret) {
2190 dev_dbg(mmc_dev(host->mmc),
2191 "Unable to handle MMC board"
2192 " level suspend\n");
2193 host->suspended = 0;
2194 return ret;
2195 }
2196 }
2197 cancel_work_sync(&host->mmc_carddetect_work);
1a13f8fa 2198 ret = mmc_suspend_host(host->mmc);
e7cb756f 2199 mmc_host_enable(host->mmc);
a45c6cb8 2200 if (ret == 0) {
b417577d 2201 omap_hsmmc_disable_irq(host);
0683af48 2202 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2203 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 2204 mmc_host_disable(host->mmc);
a45c6cb8 2205 clk_disable(host->iclk);
2bec0893
AH		 2206 if (host->got_dbclk)
2207 clk_disable(host->dbclk);
a6b2240d
AH		 2208 } else {
2209 host->suspended = 0;
2210 if (host->pdata->resume) {
2211 ret = host->pdata->resume(&pdev->dev,
2212 host->slot_id);
2213 if (ret)
2214 dev_dbg(mmc_dev(host->mmc),
2215 "Unmask interrupt failed\n");
2216 }
5e2ea617 2217 mmc_host_disable(host->mmc);
a6b2240d 2218 }
a45c6cb8
MC		 2219
2220 }
2221 return ret;
2222}
2223
2224/* Routine to resume the MMC device */
a791daa1 2225static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2226{
2227 int ret = 0;
a791daa1 2228 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2229 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2230
2231 if (host && !host->suspended)
2232 return 0;
2233
2234 if (host) {
a45c6cb8 2235 ret = clk_enable(host->iclk);
11dd62a7 2236 if (ret)
a45c6cb8 2237 goto clk_en_err;
a45c6cb8 2238
11dd62a7
DK		 2239 if (mmc_host_enable(host->mmc) != 0) {
2240 clk_disable(host->iclk);
2241 goto clk_en_err;
2242 }
2243
2bec0893
AH		 2244 if (host->got_dbclk)
2245 clk_enable(host->dbclk);
2246
70a3341a 2247 omap_hsmmc_conf_bus_power(host);
1b331e69 2248
a45c6cb8
MC		 2249 if (host->pdata->resume) {
2250 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2251 if (ret)
2252 dev_dbg(mmc_dev(host->mmc),
2253 "Unmask interrupt failed\n");
2254 }
2255
b62f6228
AH		 2256 omap_hsmmc_protect_card(host);
2257
a45c6cb8
MC		 2258 /* Notify the core to resume the host */
2259 ret = mmc_resume_host(host->mmc);
2260 if (ret == 0)
2261 host->suspended = 0;
2262 }
2263
2264 return ret;
2265
2266clk_en_err:
2267 dev_dbg(mmc_dev(host->mmc),
2268 "Failed to enable MMC clocks during resume\n");
2269 return ret;
2270}
2271
2272#else
70a3341a
DK		 2273#define omap_hsmmc_suspend NULL
2274#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2275#endif
2276
a791daa1 2277static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2278 .suspend = omap_hsmmc_suspend,
2279 .resume = omap_hsmmc_resume,
a791daa1
KH		 2280};
2281
2282static struct platform_driver omap_hsmmc_driver = {
2283 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2284 .driver = {
2285 .name = DRIVER_NAME,
2286 .owner = THIS_MODULE,
a791daa1 2287 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2288 },
2289};
2290
70a3341a 2291static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2292{
2293 /* Register the MMC driver */
8753298a 2294 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2295}
2296
70a3341a 2297static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2298{
2299 /* Unregister MMC driver */
70a3341a 2300 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2301}
2302
70a3341a
DK		 2303module_init(omap_hsmmc_init);
2304module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2305
2306MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2307MODULE_LICENSE("GPL");
2308MODULE_ALIAS("platform:" DRIVER_NAME);
2309MODULE_AUTHOR("Texas Instruments Inc");
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