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Commit | Line | Data |
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a45c6cb8 MC |
1 | /* |
2 | * drivers/mmc/host/omap_hsmmc.c | |
3 | * | |
4 | * Driver for OMAP2430/3430 MMC controller. | |
5 | * | |
6 | * Copyright (C) 2007 Texas Instruments. | |
7 | * | |
8 | * Authors: | |
9 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
10 | * Madhusudhan <madhu.cr@ti.com> | |
11 | * Mohit Jalori <mjalori@ti.com> | |
12 | * | |
13 | * This file is licensed under the terms of the GNU General Public License | |
14 | * version 2. This program is licensed "as is" without any warranty of any | |
15 | * kind, whether express or implied. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
ac330f44 | 20 | #include <linux/kernel.h> |
d900f712 | 21 | #include <linux/debugfs.h> |
c5c98927 | 22 | #include <linux/dmaengine.h> |
d900f712 | 23 | #include <linux/seq_file.h> |
031cd037 | 24 | #include <linux/sizes.h> |
a45c6cb8 MC |
25 | #include <linux/interrupt.h> |
26 | #include <linux/delay.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/platform_device.h> | |
a45c6cb8 MC |
29 | #include <linux/timer.h> |
30 | #include <linux/clk.h> | |
46856a68 | 31 | #include <linux/of.h> |
2cd3a2a5 | 32 | #include <linux/of_irq.h> |
46856a68 RN |
33 | #include <linux/of_gpio.h> |
34 | #include <linux/of_device.h> | |
ee526d51 | 35 | #include <linux/omap-dmaengine.h> |
a45c6cb8 | 36 | #include <linux/mmc/host.h> |
13189e78 | 37 | #include <linux/mmc/core.h> |
93caf8e6 | 38 | #include <linux/mmc/mmc.h> |
a45c6cb8 | 39 | #include <linux/io.h> |
2cd3a2a5 | 40 | #include <linux/irq.h> |
db0fefc5 AH |
41 | #include <linux/gpio.h> |
42 | #include <linux/regulator/consumer.h> | |
46b76035 | 43 | #include <linux/pinctrl/consumer.h> |
fa4aa2d4 | 44 | #include <linux/pm_runtime.h> |
68f39e74 | 45 | #include <linux/platform_data/mmc-omap.h> |
a45c6cb8 MC |
46 | |
47 | /* OMAP HSMMC Host Controller Registers */ | |
11dd62a7 | 48 | #define OMAP_HSMMC_SYSSTATUS 0x0014 |
a45c6cb8 | 49 | #define OMAP_HSMMC_CON 0x002C |
a2e77152 | 50 | #define OMAP_HSMMC_SDMASA 0x0100 |
a45c6cb8 MC |
51 | #define OMAP_HSMMC_BLK 0x0104 |
52 | #define OMAP_HSMMC_ARG 0x0108 | |
53 | #define OMAP_HSMMC_CMD 0x010C | |
54 | #define OMAP_HSMMC_RSP10 0x0110 | |
55 | #define OMAP_HSMMC_RSP32 0x0114 | |
56 | #define OMAP_HSMMC_RSP54 0x0118 | |
57 | #define OMAP_HSMMC_RSP76 0x011C | |
58 | #define OMAP_HSMMC_DATA 0x0120 | |
bb0635f0 | 59 | #define OMAP_HSMMC_PSTATE 0x0124 |
a45c6cb8 MC |
60 | #define OMAP_HSMMC_HCTL 0x0128 |
61 | #define OMAP_HSMMC_SYSCTL 0x012C | |
62 | #define OMAP_HSMMC_STAT 0x0130 | |
63 | #define OMAP_HSMMC_IE 0x0134 | |
64 | #define OMAP_HSMMC_ISE 0x0138 | |
a2e77152 | 65 | #define OMAP_HSMMC_AC12 0x013C |
a45c6cb8 MC |
66 | #define OMAP_HSMMC_CAPA 0x0140 |
67 | ||
68 | #define VS18 (1 << 26) | |
69 | #define VS30 (1 << 25) | |
cd587096 | 70 | #define HSS (1 << 21) |
a45c6cb8 MC |
71 | #define SDVS18 (0x5 << 9) |
72 | #define SDVS30 (0x6 << 9) | |
eb250826 | 73 | #define SDVS33 (0x7 << 9) |
1b331e69 | 74 | #define SDVS_MASK 0x00000E00 |
a45c6cb8 MC |
75 | #define SDVSCLR 0xFFFFF1FF |
76 | #define SDVSDET 0x00000400 | |
77 | #define AUTOIDLE 0x1 | |
78 | #define SDBP (1 << 8) | |
79 | #define DTO 0xe | |
80 | #define ICE 0x1 | |
81 | #define ICS 0x2 | |
82 | #define CEN (1 << 2) | |
ed164182 | 83 | #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ |
a45c6cb8 MC |
84 | #define CLKD_MASK 0x0000FFC0 |
85 | #define CLKD_SHIFT 6 | |
86 | #define DTO_MASK 0x000F0000 | |
87 | #define DTO_SHIFT 16 | |
a45c6cb8 | 88 | #define INIT_STREAM (1 << 1) |
a2e77152 | 89 | #define ACEN_ACMD23 (2 << 2) |
a45c6cb8 MC |
90 | #define DP_SELECT (1 << 21) |
91 | #define DDIR (1 << 4) | |
a7e96879 | 92 | #define DMAE 0x1 |
a45c6cb8 MC |
93 | #define MSBS (1 << 5) |
94 | #define BCE (1 << 1) | |
95 | #define FOUR_BIT (1 << 1) | |
cd587096 | 96 | #define HSPE (1 << 2) |
5a52b08b | 97 | #define IWE (1 << 24) |
03b5d924 | 98 | #define DDR (1 << 19) |
5a52b08b B |
99 | #define CLKEXTFREE (1 << 16) |
100 | #define CTPL (1 << 11) | |
73153010 | 101 | #define DW8 (1 << 5) |
a45c6cb8 | 102 | #define OD 0x1 |
a45c6cb8 MC |
103 | #define STAT_CLEAR 0xFFFFFFFF |
104 | #define INIT_STREAM_CMD 0x00000000 | |
105 | #define DUAL_VOLT_OCR_BIT 7 | |
106 | #define SRC (1 << 25) | |
107 | #define SRD (1 << 26) | |
11dd62a7 | 108 | #define SOFTRESET (1 << 1) |
a45c6cb8 | 109 | |
f945901f AF |
110 | /* PSTATE */ |
111 | #define DLEV_DAT(x) (1 << (20 + (x))) | |
112 | ||
a7e96879 V |
113 | /* Interrupt masks for IE and ISE register */ |
114 | #define CC_EN (1 << 0) | |
115 | #define TC_EN (1 << 1) | |
116 | #define BWR_EN (1 << 4) | |
117 | #define BRR_EN (1 << 5) | |
2cd3a2a5 | 118 | #define CIRQ_EN (1 << 8) |
a7e96879 V |
119 | #define ERR_EN (1 << 15) |
120 | #define CTO_EN (1 << 16) | |
121 | #define CCRC_EN (1 << 17) | |
122 | #define CEB_EN (1 << 18) | |
123 | #define CIE_EN (1 << 19) | |
124 | #define DTO_EN (1 << 20) | |
125 | #define DCRC_EN (1 << 21) | |
126 | #define DEB_EN (1 << 22) | |
a2e77152 | 127 | #define ACE_EN (1 << 24) |
a7e96879 V |
128 | #define CERR_EN (1 << 28) |
129 | #define BADA_EN (1 << 29) | |
130 | ||
a2e77152 | 131 | #define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\ |
a7e96879 V |
132 | DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ |
133 | BRR_EN | BWR_EN | TC_EN | CC_EN) | |
134 | ||
a2e77152 B |
135 | #define CNI (1 << 7) |
136 | #define ACIE (1 << 4) | |
137 | #define ACEB (1 << 3) | |
138 | #define ACCE (1 << 2) | |
139 | #define ACTO (1 << 1) | |
140 | #define ACNE (1 << 0) | |
141 | ||
fa4aa2d4 | 142 | #define MMC_AUTOSUSPEND_DELAY 100 |
1e881786 JM |
143 | #define MMC_TIMEOUT_MS 20 /* 20 mSec */ |
144 | #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ | |
6b206efe AS |
145 | #define OMAP_MMC_MIN_CLOCK 400000 |
146 | #define OMAP_MMC_MAX_CLOCK 52000000 | |
0005ae73 | 147 | #define DRIVER_NAME "omap_hsmmc" |
a45c6cb8 | 148 | |
e99448ff B |
149 | #define VDD_1V8 1800000 /* 180000 uV */ |
150 | #define VDD_3V0 3000000 /* 300000 uV */ | |
151 | #define VDD_165_195 (ffs(MMC_VDD_165_195) - 1) | |
152 | ||
a45c6cb8 MC |
153 | /* |
154 | * One controller can have multiple slots, like on some omap boards using | |
155 | * omap.c controller driver. Luckily this is not currently done on any known | |
156 | * omap_hsmmc.c device. | |
157 | */ | |
158 | #define mmc_slot(host) (host->pdata->slots[host->slot_id]) | |
159 | ||
160 | /* | |
161 | * MMC Host controller read/write API's | |
162 | */ | |
163 | #define OMAP_HSMMC_READ(base, reg) \ | |
164 | __raw_readl((base) + OMAP_HSMMC_##reg) | |
165 | ||
166 | #define OMAP_HSMMC_WRITE(base, reg, val) \ | |
167 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) | |
168 | ||
9782aff8 PF |
169 | struct omap_hsmmc_next { |
170 | unsigned int dma_len; | |
171 | s32 cookie; | |
172 | }; | |
173 | ||
70a3341a | 174 | struct omap_hsmmc_host { |
a45c6cb8 MC |
175 | struct device *dev; |
176 | struct mmc_host *mmc; | |
177 | struct mmc_request *mrq; | |
178 | struct mmc_command *cmd; | |
179 | struct mmc_data *data; | |
180 | struct clk *fclk; | |
a45c6cb8 | 181 | struct clk *dbclk; |
db0fefc5 AH |
182 | /* |
183 | * vcc == configured supply | |
184 | * vcc_aux == optional | |
185 | * - MMC1, supply for DAT4..DAT7 | |
186 | * - MMC2/MMC2, external level shifter voltage supply, for | |
187 | * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) | |
188 | */ | |
189 | struct regulator *vcc; | |
190 | struct regulator *vcc_aux; | |
e99448ff B |
191 | struct regulator *pbias; |
192 | bool pbias_enabled; | |
a45c6cb8 MC |
193 | void __iomem *base; |
194 | resource_size_t mapbase; | |
4dffd7a2 | 195 | spinlock_t irq_lock; /* Prevent races with irq handler */ |
a45c6cb8 | 196 | unsigned int dma_len; |
0ccd76d4 | 197 | unsigned int dma_sg_idx; |
a45c6cb8 | 198 | unsigned char bus_mode; |
a3621465 | 199 | unsigned char power_mode; |
a45c6cb8 | 200 | int suspended; |
0a82e06e TL |
201 | u32 con; |
202 | u32 hctl; | |
203 | u32 sysctl; | |
204 | u32 capa; | |
a45c6cb8 | 205 | int irq; |
2cd3a2a5 | 206 | int wake_irq; |
a45c6cb8 | 207 | int use_dma, dma_ch; |
c5c98927 RK |
208 | struct dma_chan *tx_chan; |
209 | struct dma_chan *rx_chan; | |
a45c6cb8 | 210 | int slot_id; |
4a694dc9 | 211 | int response_busy; |
11dd62a7 | 212 | int context_loss; |
b62f6228 AH |
213 | int protect_card; |
214 | int reqs_blocked; | |
db0fefc5 | 215 | int use_reg; |
b417577d | 216 | int req_in_progress; |
6e3076c2 | 217 | unsigned long clk_rate; |
a2e77152 | 218 | unsigned int flags; |
2cd3a2a5 AF |
219 | #define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */ |
220 | #define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */ | |
221 | #define HSMMC_WAKE_IRQ_ENABLED (1 << 2) | |
9782aff8 | 222 | struct omap_hsmmc_next next_data; |
a45c6cb8 MC |
223 | struct omap_mmc_platform_data *pdata; |
224 | }; | |
225 | ||
59445b10 NM |
226 | struct omap_mmc_of_data { |
227 | u32 reg_offset; | |
228 | u8 controller_flags; | |
229 | }; | |
230 | ||
bf129e1c B |
231 | static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host); |
232 | ||
db0fefc5 AH |
233 | static int omap_hsmmc_card_detect(struct device *dev, int slot) |
234 | { | |
9ea28ecb B |
235 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
236 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
237 | |
238 | /* NOTE: assumes card detect signal is active-low */ | |
239 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
240 | } | |
241 | ||
242 | static int omap_hsmmc_get_wp(struct device *dev, int slot) | |
243 | { | |
9ea28ecb B |
244 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
245 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
246 | |
247 | /* NOTE: assumes write protect signal is active-high */ | |
248 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | |
249 | } | |
250 | ||
251 | static int omap_hsmmc_get_cover_state(struct device *dev, int slot) | |
252 | { | |
9ea28ecb B |
253 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
254 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
255 | |
256 | /* NOTE: assumes card detect signal is active-low */ | |
257 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
258 | } | |
259 | ||
260 | #ifdef CONFIG_PM | |
261 | ||
262 | static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) | |
263 | { | |
9ea28ecb B |
264 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
265 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
266 | |
267 | disable_irq(mmc->slots[0].card_detect_irq); | |
268 | return 0; | |
269 | } | |
270 | ||
271 | static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) | |
272 | { | |
9ea28ecb B |
273 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
274 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
275 | |
276 | enable_irq(mmc->slots[0].card_detect_irq); | |
277 | return 0; | |
278 | } | |
279 | ||
280 | #else | |
281 | ||
282 | #define omap_hsmmc_suspend_cdirq NULL | |
283 | #define omap_hsmmc_resume_cdirq NULL | |
284 | ||
285 | #endif | |
286 | ||
b702b106 AH |
287 | #ifdef CONFIG_REGULATOR |
288 | ||
69b07ece | 289 | static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, |
db0fefc5 AH |
290 | int vdd) |
291 | { | |
292 | struct omap_hsmmc_host *host = | |
293 | platform_get_drvdata(to_platform_device(dev)); | |
294 | int ret = 0; | |
295 | ||
296 | /* | |
297 | * If we don't see a Vcc regulator, assume it's a fixed | |
298 | * voltage always-on regulator. | |
299 | */ | |
300 | if (!host->vcc) | |
301 | return 0; | |
302 | ||
303 | if (mmc_slot(host).before_set_reg) | |
304 | mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); | |
305 | ||
e99448ff B |
306 | if (host->pbias) { |
307 | if (host->pbias_enabled == 1) { | |
308 | ret = regulator_disable(host->pbias); | |
309 | if (!ret) | |
310 | host->pbias_enabled = 0; | |
311 | } | |
312 | regulator_set_voltage(host->pbias, VDD_3V0, VDD_3V0); | |
313 | } | |
314 | ||
db0fefc5 AH |
315 | /* |
316 | * Assume Vcc regulator is used only to power the card ... OMAP | |
317 | * VDDS is used to power the pins, optionally with a transceiver to | |
318 | * support cards using voltages other than VDDS (1.8V nominal). When a | |
319 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. | |
320 | * | |
321 | * In some cases this regulator won't support enable/disable; | |
322 | * e.g. it's a fixed rail for a WLAN chip. | |
323 | * | |
324 | * In other cases vcc_aux switches interface power. Example, for | |
325 | * eMMC cards it represents VccQ. Sometimes transceivers or SDIO | |
326 | * chips/cards need an interface voltage rail too. | |
327 | */ | |
328 | if (power_on) { | |
987fd49b B |
329 | if (host->vcc) |
330 | ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); | |
db0fefc5 AH |
331 | /* Enable interface voltage rail, if needed */ |
332 | if (ret == 0 && host->vcc_aux) { | |
333 | ret = regulator_enable(host->vcc_aux); | |
987fd49b | 334 | if (ret < 0 && host->vcc) |
99fc5131 LW |
335 | ret = mmc_regulator_set_ocr(host->mmc, |
336 | host->vcc, 0); | |
db0fefc5 AH |
337 | } |
338 | } else { | |
99fc5131 | 339 | /* Shut down the rail */ |
6da20c89 AH |
340 | if (host->vcc_aux) |
341 | ret = regulator_disable(host->vcc_aux); | |
987fd49b | 342 | if (host->vcc) { |
99fc5131 LW |
343 | /* Then proceed to shut down the local regulator */ |
344 | ret = mmc_regulator_set_ocr(host->mmc, | |
345 | host->vcc, 0); | |
346 | } | |
db0fefc5 AH |
347 | } |
348 | ||
e99448ff B |
349 | if (host->pbias) { |
350 | if (vdd <= VDD_165_195) | |
351 | ret = regulator_set_voltage(host->pbias, VDD_1V8, | |
352 | VDD_1V8); | |
353 | else | |
354 | ret = regulator_set_voltage(host->pbias, VDD_3V0, | |
355 | VDD_3V0); | |
356 | if (ret < 0) | |
357 | goto error_set_power; | |
358 | ||
359 | if (host->pbias_enabled == 0) { | |
360 | ret = regulator_enable(host->pbias); | |
361 | if (!ret) | |
362 | host->pbias_enabled = 1; | |
363 | } | |
364 | } | |
365 | ||
db0fefc5 AH |
366 | if (mmc_slot(host).after_set_reg) |
367 | mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); | |
368 | ||
e99448ff | 369 | error_set_power: |
db0fefc5 AH |
370 | return ret; |
371 | } | |
372 | ||
db0fefc5 AH |
373 | static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) |
374 | { | |
375 | struct regulator *reg; | |
64be9782 | 376 | int ocr_value = 0; |
db0fefc5 | 377 | |
f2ddc1da | 378 | reg = devm_regulator_get(host->dev, "vmmc"); |
db0fefc5 | 379 | if (IS_ERR(reg)) { |
987fd49b B |
380 | dev_err(host->dev, "unable to get vmmc regulator %ld\n", |
381 | PTR_ERR(reg)); | |
1fdc90fb | 382 | return PTR_ERR(reg); |
db0fefc5 AH |
383 | } else { |
384 | host->vcc = reg; | |
64be9782 | 385 | ocr_value = mmc_regulator_get_ocrmask(reg); |
386 | if (!mmc_slot(host).ocr_mask) { | |
387 | mmc_slot(host).ocr_mask = ocr_value; | |
388 | } else { | |
389 | if (!(mmc_slot(host).ocr_mask & ocr_value)) { | |
2cecdf00 | 390 | dev_err(host->dev, "ocrmask %x is not supported\n", |
e3f1adb6 | 391 | mmc_slot(host).ocr_mask); |
64be9782 | 392 | mmc_slot(host).ocr_mask = 0; |
393 | return -EINVAL; | |
394 | } | |
395 | } | |
987fd49b B |
396 | } |
397 | mmc_slot(host).set_power = omap_hsmmc_set_power; | |
db0fefc5 | 398 | |
987fd49b B |
399 | /* Allow an aux regulator */ |
400 | reg = devm_regulator_get_optional(host->dev, "vmmc_aux"); | |
401 | host->vcc_aux = IS_ERR(reg) ? NULL : reg; | |
402 | ||
e99448ff B |
403 | reg = devm_regulator_get_optional(host->dev, "pbias"); |
404 | host->pbias = IS_ERR(reg) ? NULL : reg; | |
405 | ||
987fd49b B |
406 | /* For eMMC do not power off when not in sleep state */ |
407 | if (mmc_slot(host).no_regulator_off_init) | |
408 | return 0; | |
409 | /* | |
410 | * To disable boot_on regulator, enable regulator | |
411 | * to increase usecount and then disable it. | |
412 | */ | |
413 | if ((host->vcc && regulator_is_enabled(host->vcc) > 0) || | |
414 | (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { | |
415 | int vdd = ffs(mmc_slot(host).ocr_mask) - 1; | |
416 | ||
417 | mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd); | |
418 | mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); | |
db0fefc5 AH |
419 | } |
420 | ||
421 | return 0; | |
db0fefc5 AH |
422 | } |
423 | ||
424 | static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) | |
425 | { | |
db0fefc5 | 426 | mmc_slot(host).set_power = NULL; |
db0fefc5 AH |
427 | } |
428 | ||
b702b106 AH |
429 | static inline int omap_hsmmc_have_reg(void) |
430 | { | |
431 | return 1; | |
432 | } | |
433 | ||
434 | #else | |
435 | ||
436 | static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) | |
437 | { | |
438 | return -EINVAL; | |
439 | } | |
440 | ||
441 | static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) | |
442 | { | |
443 | } | |
444 | ||
445 | static inline int omap_hsmmc_have_reg(void) | |
446 | { | |
447 | return 0; | |
448 | } | |
449 | ||
450 | #endif | |
451 | ||
452 | static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) | |
453 | { | |
454 | int ret; | |
455 | ||
456 | if (gpio_is_valid(pdata->slots[0].switch_pin)) { | |
b702b106 AH |
457 | if (pdata->slots[0].cover) |
458 | pdata->slots[0].get_cover_state = | |
459 | omap_hsmmc_get_cover_state; | |
460 | else | |
461 | pdata->slots[0].card_detect = omap_hsmmc_card_detect; | |
462 | pdata->slots[0].card_detect_irq = | |
463 | gpio_to_irq(pdata->slots[0].switch_pin); | |
464 | ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); | |
465 | if (ret) | |
466 | return ret; | |
467 | ret = gpio_direction_input(pdata->slots[0].switch_pin); | |
468 | if (ret) | |
469 | goto err_free_sp; | |
470 | } else | |
471 | pdata->slots[0].switch_pin = -EINVAL; | |
472 | ||
473 | if (gpio_is_valid(pdata->slots[0].gpio_wp)) { | |
474 | pdata->slots[0].get_ro = omap_hsmmc_get_wp; | |
475 | ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); | |
476 | if (ret) | |
477 | goto err_free_cd; | |
478 | ret = gpio_direction_input(pdata->slots[0].gpio_wp); | |
479 | if (ret) | |
480 | goto err_free_wp; | |
481 | } else | |
482 | pdata->slots[0].gpio_wp = -EINVAL; | |
483 | ||
484 | return 0; | |
485 | ||
486 | err_free_wp: | |
487 | gpio_free(pdata->slots[0].gpio_wp); | |
488 | err_free_cd: | |
489 | if (gpio_is_valid(pdata->slots[0].switch_pin)) | |
490 | err_free_sp: | |
491 | gpio_free(pdata->slots[0].switch_pin); | |
492 | return ret; | |
493 | } | |
494 | ||
495 | static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) | |
496 | { | |
497 | if (gpio_is_valid(pdata->slots[0].gpio_wp)) | |
498 | gpio_free(pdata->slots[0].gpio_wp); | |
499 | if (gpio_is_valid(pdata->slots[0].switch_pin)) | |
500 | gpio_free(pdata->slots[0].switch_pin); | |
501 | } | |
502 | ||
e0c7f99b AS |
503 | /* |
504 | * Start clock to the card | |
505 | */ | |
506 | static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) | |
507 | { | |
508 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
509 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
510 | } | |
511 | ||
a45c6cb8 MC |
512 | /* |
513 | * Stop clock to the card | |
514 | */ | |
70a3341a | 515 | static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
516 | { |
517 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
518 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
519 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) | |
7122bbb0 | 520 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); |
a45c6cb8 MC |
521 | } |
522 | ||
93caf8e6 AH |
523 | static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, |
524 | struct mmc_command *cmd) | |
b417577d | 525 | { |
2cd3a2a5 AF |
526 | u32 irq_mask = INT_EN_MASK; |
527 | unsigned long flags; | |
b417577d AH |
528 | |
529 | if (host->use_dma) | |
2cd3a2a5 | 530 | irq_mask &= ~(BRR_EN | BWR_EN); |
b417577d | 531 | |
93caf8e6 AH |
532 | /* Disable timeout for erases */ |
533 | if (cmd->opcode == MMC_ERASE) | |
a7e96879 | 534 | irq_mask &= ~DTO_EN; |
93caf8e6 | 535 | |
2cd3a2a5 | 536 | spin_lock_irqsave(&host->irq_lock, flags); |
b417577d AH |
537 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
538 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); | |
2cd3a2a5 AF |
539 | |
540 | /* latch pending CIRQ, but don't signal MMC core */ | |
541 | if (host->flags & HSMMC_SDIO_IRQ_ENABLED) | |
542 | irq_mask |= CIRQ_EN; | |
b417577d | 543 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); |
2cd3a2a5 | 544 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
545 | } |
546 | ||
547 | static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) | |
548 | { | |
2cd3a2a5 AF |
549 | u32 irq_mask = 0; |
550 | unsigned long flags; | |
551 | ||
552 | spin_lock_irqsave(&host->irq_lock, flags); | |
553 | /* no transfer running but need to keep cirq if enabled */ | |
554 | if (host->flags & HSMMC_SDIO_IRQ_ENABLED) | |
555 | irq_mask |= CIRQ_EN; | |
556 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); | |
557 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); | |
b417577d | 558 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
2cd3a2a5 | 559 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
560 | } |
561 | ||
ac330f44 | 562 | /* Calculate divisor for the given clock frequency */ |
d83b6e03 | 563 | static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) |
ac330f44 AS |
564 | { |
565 | u16 dsor = 0; | |
566 | ||
567 | if (ios->clock) { | |
d83b6e03 | 568 | dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); |
ed164182 B |
569 | if (dsor > CLKD_MAX) |
570 | dsor = CLKD_MAX; | |
ac330f44 AS |
571 | } |
572 | ||
573 | return dsor; | |
574 | } | |
575 | ||
5934df2f AS |
576 | static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) |
577 | { | |
578 | struct mmc_ios *ios = &host->mmc->ios; | |
579 | unsigned long regval; | |
580 | unsigned long timeout; | |
cd587096 | 581 | unsigned long clkdiv; |
5934df2f | 582 | |
8986d31b | 583 | dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); |
5934df2f AS |
584 | |
585 | omap_hsmmc_stop_clock(host); | |
586 | ||
587 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); | |
588 | regval = regval & ~(CLKD_MASK | DTO_MASK); | |
cd587096 HG |
589 | clkdiv = calc_divisor(host, ios); |
590 | regval = regval | (clkdiv << 6) | (DTO << 16); | |
5934df2f AS |
591 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); |
592 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
593 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
594 | ||
595 | /* Wait till the ICS bit is set */ | |
596 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
597 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS | |
598 | && time_before(jiffies, timeout)) | |
599 | cpu_relax(); | |
600 | ||
cd587096 HG |
601 | /* |
602 | * Enable High-Speed Support | |
603 | * Pre-Requisites | |
604 | * - Controller should support High-Speed-Enable Bit | |
605 | * - Controller should not be using DDR Mode | |
606 | * - Controller should advertise that it supports High Speed | |
607 | * in capabilities register | |
608 | * - MMC/SD clock coming out of controller > 25MHz | |
609 | */ | |
610 | if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && | |
5438ad95 | 611 | (ios->timing != MMC_TIMING_MMC_DDR52) && |
cd587096 HG |
612 | ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { |
613 | regval = OMAP_HSMMC_READ(host->base, HCTL); | |
614 | if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) | |
615 | regval |= HSPE; | |
616 | else | |
617 | regval &= ~HSPE; | |
618 | ||
619 | OMAP_HSMMC_WRITE(host->base, HCTL, regval); | |
620 | } | |
621 | ||
5934df2f AS |
622 | omap_hsmmc_start_clock(host); |
623 | } | |
624 | ||
3796fb8a AS |
625 | static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) |
626 | { | |
627 | struct mmc_ios *ios = &host->mmc->ios; | |
628 | u32 con; | |
629 | ||
630 | con = OMAP_HSMMC_READ(host->base, CON); | |
5438ad95 | 631 | if (ios->timing == MMC_TIMING_MMC_DDR52) |
03b5d924 B |
632 | con |= DDR; /* configure in DDR mode */ |
633 | else | |
634 | con &= ~DDR; | |
3796fb8a AS |
635 | switch (ios->bus_width) { |
636 | case MMC_BUS_WIDTH_8: | |
637 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
638 | break; | |
639 | case MMC_BUS_WIDTH_4: | |
640 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
641 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
642 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
643 | break; | |
644 | case MMC_BUS_WIDTH_1: | |
645 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
646 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
647 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
648 | break; | |
649 | } | |
650 | } | |
651 | ||
652 | static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) | |
653 | { | |
654 | struct mmc_ios *ios = &host->mmc->ios; | |
655 | u32 con; | |
656 | ||
657 | con = OMAP_HSMMC_READ(host->base, CON); | |
658 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
659 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); | |
660 | else | |
661 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
662 | } | |
663 | ||
11dd62a7 DK |
664 | #ifdef CONFIG_PM |
665 | ||
666 | /* | |
667 | * Restore the MMC host context, if it was lost as result of a | |
668 | * power state change. | |
669 | */ | |
70a3341a | 670 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
671 | { |
672 | struct mmc_ios *ios = &host->mmc->ios; | |
3796fb8a | 673 | u32 hctl, capa; |
11dd62a7 DK |
674 | unsigned long timeout; |
675 | ||
0a82e06e TL |
676 | if (host->con == OMAP_HSMMC_READ(host->base, CON) && |
677 | host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && | |
678 | host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && | |
679 | host->capa == OMAP_HSMMC_READ(host->base, CAPA)) | |
680 | return 0; | |
681 | ||
682 | host->context_loss++; | |
683 | ||
c2200efb | 684 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
11dd62a7 DK |
685 | if (host->power_mode != MMC_POWER_OFF && |
686 | (1 << ios->vdd) <= MMC_VDD_23_24) | |
687 | hctl = SDVS18; | |
688 | else | |
689 | hctl = SDVS30; | |
690 | capa = VS30 | VS18; | |
691 | } else { | |
692 | hctl = SDVS18; | |
693 | capa = VS18; | |
694 | } | |
695 | ||
5a52b08b B |
696 | if (host->mmc->caps & MMC_CAP_SDIO_IRQ) |
697 | hctl |= IWE; | |
698 | ||
11dd62a7 DK |
699 | OMAP_HSMMC_WRITE(host->base, HCTL, |
700 | OMAP_HSMMC_READ(host->base, HCTL) | hctl); | |
701 | ||
702 | OMAP_HSMMC_WRITE(host->base, CAPA, | |
703 | OMAP_HSMMC_READ(host->base, CAPA) | capa); | |
704 | ||
705 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
706 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
707 | ||
708 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
709 | while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP | |
710 | && time_before(jiffies, timeout)) | |
711 | ; | |
712 | ||
2cd3a2a5 AF |
713 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
714 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
715 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
11dd62a7 DK |
716 | |
717 | /* Do not initialize card-specific things if the power is off */ | |
718 | if (host->power_mode == MMC_POWER_OFF) | |
719 | goto out; | |
720 | ||
3796fb8a | 721 | omap_hsmmc_set_bus_width(host); |
11dd62a7 | 722 | |
5934df2f | 723 | omap_hsmmc_set_clock(host); |
11dd62a7 | 724 | |
3796fb8a AS |
725 | omap_hsmmc_set_bus_mode(host); |
726 | ||
11dd62a7 | 727 | out: |
0a82e06e TL |
728 | dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", |
729 | host->context_loss); | |
11dd62a7 DK |
730 | return 0; |
731 | } | |
732 | ||
733 | /* | |
734 | * Save the MMC host context (store the number of power state changes so far). | |
735 | */ | |
70a3341a | 736 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 | 737 | { |
0a82e06e TL |
738 | host->con = OMAP_HSMMC_READ(host->base, CON); |
739 | host->hctl = OMAP_HSMMC_READ(host->base, HCTL); | |
740 | host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); | |
741 | host->capa = OMAP_HSMMC_READ(host->base, CAPA); | |
11dd62a7 DK |
742 | } |
743 | ||
744 | #else | |
745 | ||
70a3341a | 746 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
747 | { |
748 | return 0; | |
749 | } | |
750 | ||
70a3341a | 751 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
752 | { |
753 | } | |
754 | ||
755 | #endif | |
756 | ||
a45c6cb8 MC |
757 | /* |
758 | * Send init stream sequence to card | |
759 | * before sending IDLE command | |
760 | */ | |
70a3341a | 761 | static void send_init_stream(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
762 | { |
763 | int reg = 0; | |
764 | unsigned long timeout; | |
765 | ||
b62f6228 AH |
766 | if (host->protect_card) |
767 | return; | |
768 | ||
a45c6cb8 | 769 | disable_irq(host->irq); |
b417577d AH |
770 | |
771 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
a45c6cb8 MC |
772 | OMAP_HSMMC_WRITE(host->base, CON, |
773 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); | |
774 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); | |
775 | ||
776 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
a7e96879 V |
777 | while ((reg != CC_EN) && time_before(jiffies, timeout)) |
778 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; | |
a45c6cb8 MC |
779 | |
780 | OMAP_HSMMC_WRITE(host->base, CON, | |
781 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); | |
c653a6d4 AH |
782 | |
783 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
784 | OMAP_HSMMC_READ(host->base, STAT); | |
785 | ||
a45c6cb8 MC |
786 | enable_irq(host->irq); |
787 | } | |
788 | ||
789 | static inline | |
70a3341a | 790 | int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
791 | { |
792 | int r = 1; | |
793 | ||
191d1f1d DK |
794 | if (mmc_slot(host).get_cover_state) |
795 | r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); | |
a45c6cb8 MC |
796 | return r; |
797 | } | |
798 | ||
799 | static ssize_t | |
70a3341a | 800 | omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
801 | char *buf) |
802 | { | |
803 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 804 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 805 | |
70a3341a DK |
806 | return sprintf(buf, "%s\n", |
807 | omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); | |
a45c6cb8 MC |
808 | } |
809 | ||
70a3341a | 810 | static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); |
a45c6cb8 MC |
811 | |
812 | static ssize_t | |
70a3341a | 813 | omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
814 | char *buf) |
815 | { | |
816 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 817 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 818 | |
191d1f1d | 819 | return sprintf(buf, "%s\n", mmc_slot(host).name); |
a45c6cb8 MC |
820 | } |
821 | ||
70a3341a | 822 | static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); |
a45c6cb8 MC |
823 | |
824 | /* | |
825 | * Configure the response type and send the cmd. | |
826 | */ | |
827 | static void | |
70a3341a | 828 | omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, |
a45c6cb8 MC |
829 | struct mmc_data *data) |
830 | { | |
831 | int cmdreg = 0, resptype = 0, cmdtype = 0; | |
832 | ||
8986d31b | 833 | dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", |
a45c6cb8 MC |
834 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); |
835 | host->cmd = cmd; | |
836 | ||
93caf8e6 | 837 | omap_hsmmc_enable_irq(host, cmd); |
a45c6cb8 | 838 | |
4a694dc9 | 839 | host->response_busy = 0; |
a45c6cb8 MC |
840 | if (cmd->flags & MMC_RSP_PRESENT) { |
841 | if (cmd->flags & MMC_RSP_136) | |
842 | resptype = 1; | |
4a694dc9 AH |
843 | else if (cmd->flags & MMC_RSP_BUSY) { |
844 | resptype = 3; | |
845 | host->response_busy = 1; | |
846 | } else | |
a45c6cb8 MC |
847 | resptype = 2; |
848 | } | |
849 | ||
850 | /* | |
851 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on | |
852 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need | |
853 | * a val of 0x3, rest 0x0. | |
854 | */ | |
855 | if (cmd == host->mrq->stop) | |
856 | cmdtype = 0x3; | |
857 | ||
858 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); | |
859 | ||
a2e77152 B |
860 | if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) && |
861 | host->mrq->sbc) { | |
862 | cmdreg |= ACEN_ACMD23; | |
863 | OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg); | |
864 | } | |
a45c6cb8 MC |
865 | if (data) { |
866 | cmdreg |= DP_SELECT | MSBS | BCE; | |
867 | if (data->flags & MMC_DATA_READ) | |
868 | cmdreg |= DDIR; | |
869 | else | |
870 | cmdreg &= ~(DDIR); | |
871 | } | |
872 | ||
873 | if (host->use_dma) | |
a7e96879 | 874 | cmdreg |= DMAE; |
a45c6cb8 | 875 | |
b417577d | 876 | host->req_in_progress = 1; |
4dffd7a2 | 877 | |
a45c6cb8 MC |
878 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); |
879 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); | |
880 | } | |
881 | ||
0ccd76d4 | 882 | static int |
70a3341a | 883 | omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) |
0ccd76d4 JY |
884 | { |
885 | if (data->flags & MMC_DATA_WRITE) | |
886 | return DMA_TO_DEVICE; | |
887 | else | |
888 | return DMA_FROM_DEVICE; | |
889 | } | |
890 | ||
c5c98927 RK |
891 | static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, |
892 | struct mmc_data *data) | |
893 | { | |
894 | return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; | |
895 | } | |
896 | ||
b417577d AH |
897 | static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) |
898 | { | |
899 | int dma_ch; | |
31463b14 | 900 | unsigned long flags; |
b417577d | 901 | |
31463b14 | 902 | spin_lock_irqsave(&host->irq_lock, flags); |
b417577d AH |
903 | host->req_in_progress = 0; |
904 | dma_ch = host->dma_ch; | |
31463b14 | 905 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
906 | |
907 | omap_hsmmc_disable_irq(host); | |
908 | /* Do not complete the request if DMA is still in progress */ | |
909 | if (mrq->data && host->use_dma && dma_ch != -1) | |
910 | return; | |
911 | host->mrq = NULL; | |
912 | mmc_request_done(host->mmc, mrq); | |
913 | } | |
914 | ||
a45c6cb8 MC |
915 | /* |
916 | * Notify the transfer complete to MMC core | |
917 | */ | |
918 | static void | |
70a3341a | 919 | omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) |
a45c6cb8 | 920 | { |
4a694dc9 AH |
921 | if (!data) { |
922 | struct mmc_request *mrq = host->mrq; | |
923 | ||
23050103 AH |
924 | /* TC before CC from CMD6 - don't know why, but it happens */ |
925 | if (host->cmd && host->cmd->opcode == 6 && | |
926 | host->response_busy) { | |
927 | host->response_busy = 0; | |
928 | return; | |
929 | } | |
930 | ||
b417577d | 931 | omap_hsmmc_request_done(host, mrq); |
4a694dc9 AH |
932 | return; |
933 | } | |
934 | ||
a45c6cb8 MC |
935 | host->data = NULL; |
936 | ||
a45c6cb8 MC |
937 | if (!data->error) |
938 | data->bytes_xfered += data->blocks * (data->blksz); | |
939 | else | |
940 | data->bytes_xfered = 0; | |
941 | ||
bf129e1c B |
942 | if (data->stop && (data->error || !host->mrq->sbc)) |
943 | omap_hsmmc_start_command(host, data->stop, NULL); | |
944 | else | |
b417577d | 945 | omap_hsmmc_request_done(host, data->mrq); |
a45c6cb8 MC |
946 | } |
947 | ||
948 | /* | |
949 | * Notify the core about command completion | |
950 | */ | |
951 | static void | |
70a3341a | 952 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) |
a45c6cb8 | 953 | { |
bf129e1c | 954 | if (host->mrq->sbc && (host->cmd == host->mrq->sbc) && |
a2e77152 | 955 | !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) { |
2177fa94 | 956 | host->cmd = NULL; |
bf129e1c B |
957 | omap_hsmmc_start_dma_transfer(host); |
958 | omap_hsmmc_start_command(host, host->mrq->cmd, | |
959 | host->mrq->data); | |
960 | return; | |
961 | } | |
962 | ||
2177fa94 B |
963 | host->cmd = NULL; |
964 | ||
a45c6cb8 MC |
965 | if (cmd->flags & MMC_RSP_PRESENT) { |
966 | if (cmd->flags & MMC_RSP_136) { | |
967 | /* response type 2 */ | |
968 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); | |
969 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); | |
970 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); | |
971 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); | |
972 | } else { | |
973 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
974 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); | |
975 | } | |
976 | } | |
b417577d | 977 | if ((host->data == NULL && !host->response_busy) || cmd->error) |
d4b2c375 | 978 | omap_hsmmc_request_done(host, host->mrq); |
a45c6cb8 MC |
979 | } |
980 | ||
981 | /* | |
982 | * DMA clean up for command errors | |
983 | */ | |
70a3341a | 984 | static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) |
a45c6cb8 | 985 | { |
b417577d | 986 | int dma_ch; |
31463b14 | 987 | unsigned long flags; |
b417577d | 988 | |
82788ff5 | 989 | host->data->error = errno; |
a45c6cb8 | 990 | |
31463b14 | 991 | spin_lock_irqsave(&host->irq_lock, flags); |
b417577d AH |
992 | dma_ch = host->dma_ch; |
993 | host->dma_ch = -1; | |
31463b14 | 994 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
995 | |
996 | if (host->use_dma && dma_ch != -1) { | |
c5c98927 RK |
997 | struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); |
998 | ||
999 | dmaengine_terminate_all(chan); | |
1000 | dma_unmap_sg(chan->device->dev, | |
1001 | host->data->sg, host->data->sg_len, | |
70a3341a | 1002 | omap_hsmmc_get_dma_dir(host, host->data)); |
c5c98927 | 1003 | |
053bf34f | 1004 | host->data->host_cookie = 0; |
a45c6cb8 MC |
1005 | } |
1006 | host->data = NULL; | |
a45c6cb8 MC |
1007 | } |
1008 | ||
1009 | /* | |
1010 | * Readable error output | |
1011 | */ | |
1012 | #ifdef CONFIG_MMC_DEBUG | |
699b958b | 1013 | static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) |
a45c6cb8 MC |
1014 | { |
1015 | /* --- means reserved bit without definition at documentation */ | |
70a3341a | 1016 | static const char *omap_hsmmc_status_bits[] = { |
699b958b AH |
1017 | "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , |
1018 | "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", | |
1019 | "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , | |
1020 | "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" | |
a45c6cb8 MC |
1021 | }; |
1022 | char res[256]; | |
1023 | char *buf = res; | |
1024 | int len, i; | |
1025 | ||
1026 | len = sprintf(buf, "MMC IRQ 0x%x :", status); | |
1027 | buf += len; | |
1028 | ||
70a3341a | 1029 | for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) |
a45c6cb8 | 1030 | if (status & (1 << i)) { |
70a3341a | 1031 | len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); |
a45c6cb8 MC |
1032 | buf += len; |
1033 | } | |
1034 | ||
8986d31b | 1035 | dev_vdbg(mmc_dev(host->mmc), "%s\n", res); |
a45c6cb8 | 1036 | } |
699b958b AH |
1037 | #else |
1038 | static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, | |
1039 | u32 status) | |
1040 | { | |
1041 | } | |
a45c6cb8 MC |
1042 | #endif /* CONFIG_MMC_DEBUG */ |
1043 | ||
3ebf74b1 JP |
1044 | /* |
1045 | * MMC controller internal state machines reset | |
1046 | * | |
1047 | * Used to reset command or data internal state machines, using respectively | |
1048 | * SRC or SRD bit of SYSCTL register | |
1049 | * Can be called from interrupt context | |
1050 | */ | |
70a3341a DK |
1051 | static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, |
1052 | unsigned long bit) | |
3ebf74b1 JP |
1053 | { |
1054 | unsigned long i = 0; | |
1e881786 | 1055 | unsigned long limit = MMC_TIMEOUT_US; |
3ebf74b1 JP |
1056 | |
1057 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
1058 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); | |
1059 | ||
07ad64b6 MC |
1060 | /* |
1061 | * OMAP4 ES2 and greater has an updated reset logic. | |
1062 | * Monitor a 0->1 transition first | |
1063 | */ | |
1064 | if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { | |
b432b4b3 | 1065 | while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) |
07ad64b6 | 1066 | && (i++ < limit)) |
1e881786 | 1067 | udelay(1); |
07ad64b6 MC |
1068 | } |
1069 | i = 0; | |
1070 | ||
3ebf74b1 JP |
1071 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && |
1072 | (i++ < limit)) | |
1e881786 | 1073 | udelay(1); |
3ebf74b1 JP |
1074 | |
1075 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) | |
1076 | dev_err(mmc_dev(host->mmc), | |
1077 | "Timeout waiting on controller reset in %s\n", | |
1078 | __func__); | |
1079 | } | |
a45c6cb8 | 1080 | |
25e1897b B |
1081 | static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, |
1082 | int err, int end_cmd) | |
ae4bf788 | 1083 | { |
25e1897b | 1084 | if (end_cmd) { |
94d4f272 | 1085 | omap_hsmmc_reset_controller_fsm(host, SRC); |
25e1897b B |
1086 | if (host->cmd) |
1087 | host->cmd->error = err; | |
1088 | } | |
ae4bf788 V |
1089 | |
1090 | if (host->data) { | |
1091 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
1092 | omap_hsmmc_dma_cleanup(host, err); | |
dc7745bd B |
1093 | } else if (host->mrq && host->mrq->cmd) |
1094 | host->mrq->cmd->error = err; | |
ae4bf788 V |
1095 | } |
1096 | ||
b417577d | 1097 | static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) |
a45c6cb8 | 1098 | { |
a45c6cb8 | 1099 | struct mmc_data *data; |
b417577d | 1100 | int end_cmd = 0, end_trans = 0; |
a2e77152 | 1101 | int error = 0; |
b417577d | 1102 | |
a45c6cb8 | 1103 | data = host->data; |
8986d31b | 1104 | dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); |
a45c6cb8 | 1105 | |
a7e96879 | 1106 | if (status & ERR_EN) { |
699b958b | 1107 | omap_hsmmc_dbg_report_irq(host, status); |
25e1897b | 1108 | |
a7e96879 | 1109 | if (status & (CTO_EN | CCRC_EN)) |
25e1897b | 1110 | end_cmd = 1; |
a7e96879 | 1111 | if (status & (CTO_EN | DTO_EN)) |
25e1897b | 1112 | hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); |
a7e96879 | 1113 | else if (status & (CCRC_EN | DCRC_EN)) |
25e1897b | 1114 | hsmmc_command_incomplete(host, -EILSEQ, end_cmd); |
ae4bf788 | 1115 | |
a2e77152 B |
1116 | if (status & ACE_EN) { |
1117 | u32 ac12; | |
1118 | ac12 = OMAP_HSMMC_READ(host->base, AC12); | |
1119 | if (!(ac12 & ACNE) && host->mrq->sbc) { | |
1120 | end_cmd = 1; | |
1121 | if (ac12 & ACTO) | |
1122 | error = -ETIMEDOUT; | |
1123 | else if (ac12 & (ACCE | ACEB | ACIE)) | |
1124 | error = -EILSEQ; | |
1125 | host->mrq->sbc->error = error; | |
1126 | hsmmc_command_incomplete(host, error, end_cmd); | |
1127 | } | |
1128 | dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12); | |
1129 | } | |
ae4bf788 | 1130 | if (host->data || host->response_busy) { |
25e1897b | 1131 | end_trans = !end_cmd; |
ae4bf788 | 1132 | host->response_busy = 0; |
a45c6cb8 MC |
1133 | } |
1134 | } | |
1135 | ||
7472bab2 | 1136 | OMAP_HSMMC_WRITE(host->base, STAT, status); |
a7e96879 | 1137 | if (end_cmd || ((status & CC_EN) && host->cmd)) |
70a3341a | 1138 | omap_hsmmc_cmd_done(host, host->cmd); |
a7e96879 | 1139 | if ((end_trans || (status & TC_EN)) && host->mrq) |
70a3341a | 1140 | omap_hsmmc_xfer_done(host, data); |
b417577d | 1141 | } |
a45c6cb8 | 1142 | |
b417577d AH |
1143 | /* |
1144 | * MMC controller IRQ handler | |
1145 | */ | |
1146 | static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) | |
1147 | { | |
1148 | struct omap_hsmmc_host *host = dev_id; | |
1149 | int status; | |
1150 | ||
1151 | status = OMAP_HSMMC_READ(host->base, STAT); | |
2cd3a2a5 AF |
1152 | while (status & (INT_EN_MASK | CIRQ_EN)) { |
1153 | if (host->req_in_progress) | |
1154 | omap_hsmmc_do_irq(host, status); | |
1155 | ||
1156 | if (status & CIRQ_EN) | |
1157 | mmc_signal_sdio_irq(host->mmc); | |
1f6b9fa4 | 1158 | |
b417577d AH |
1159 | /* Flush posted write */ |
1160 | status = OMAP_HSMMC_READ(host->base, STAT); | |
1f6b9fa4 | 1161 | } |
4dffd7a2 | 1162 | |
a45c6cb8 MC |
1163 | return IRQ_HANDLED; |
1164 | } | |
1165 | ||
2cd3a2a5 AF |
1166 | static irqreturn_t omap_hsmmc_wake_irq(int irq, void *dev_id) |
1167 | { | |
1168 | struct omap_hsmmc_host *host = dev_id; | |
1169 | ||
1170 | /* cirq is level triggered, disable to avoid infinite loop */ | |
1171 | spin_lock(&host->irq_lock); | |
1172 | if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { | |
1173 | disable_irq_nosync(host->wake_irq); | |
1174 | host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; | |
1175 | } | |
1176 | spin_unlock(&host->irq_lock); | |
1177 | pm_request_resume(host->dev); /* no use counter */ | |
1178 | ||
1179 | return IRQ_HANDLED; | |
1180 | } | |
1181 | ||
70a3341a | 1182 | static void set_sd_bus_power(struct omap_hsmmc_host *host) |
e13bb300 AH |
1183 | { |
1184 | unsigned long i; | |
1185 | ||
1186 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
1187 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
1188 | for (i = 0; i < loops_per_jiffy; i++) { | |
1189 | if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) | |
1190 | break; | |
1191 | cpu_relax(); | |
1192 | } | |
1193 | } | |
1194 | ||
a45c6cb8 | 1195 | /* |
eb250826 DB |
1196 | * Switch MMC interface voltage ... only relevant for MMC1. |
1197 | * | |
1198 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. | |
1199 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. | |
1200 | * Some chips, like eMMC ones, use internal transceivers. | |
a45c6cb8 | 1201 | */ |
70a3341a | 1202 | static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) |
a45c6cb8 MC |
1203 | { |
1204 | u32 reg_val = 0; | |
1205 | int ret; | |
1206 | ||
1207 | /* Disable the clocks */ | |
fa4aa2d4 | 1208 | pm_runtime_put_sync(host->dev); |
cd03d9a8 | 1209 | if (host->dbclk) |
94c18149 | 1210 | clk_disable_unprepare(host->dbclk); |
a45c6cb8 MC |
1211 | |
1212 | /* Turn the power off */ | |
1213 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); | |
a45c6cb8 MC |
1214 | |
1215 | /* Turn the power ON with given VDD 1.8 or 3.0v */ | |
2bec0893 AH |
1216 | if (!ret) |
1217 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, | |
1218 | vdd); | |
fa4aa2d4 | 1219 | pm_runtime_get_sync(host->dev); |
cd03d9a8 | 1220 | if (host->dbclk) |
94c18149 | 1221 | clk_prepare_enable(host->dbclk); |
2bec0893 | 1222 | |
a45c6cb8 MC |
1223 | if (ret != 0) |
1224 | goto err; | |
1225 | ||
a45c6cb8 MC |
1226 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1227 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); | |
1228 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); | |
eb250826 | 1229 | |
a45c6cb8 MC |
1230 | /* |
1231 | * If a MMC dual voltage card is detected, the set_ios fn calls | |
1232 | * this fn with VDD bit set for 1.8V. Upon card removal from the | |
70a3341a | 1233 | * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. |
a45c6cb8 | 1234 | * |
eb250826 DB |
1235 | * Cope with a bit of slop in the range ... per data sheets: |
1236 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, | |
1237 | * but recommended values are 1.71V to 1.89V | |
1238 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, | |
1239 | * but recommended values are 2.7V to 3.3V | |
1240 | * | |
1241 | * Board setup code shouldn't permit anything very out-of-range. | |
1242 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the | |
1243 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. | |
a45c6cb8 | 1244 | */ |
eb250826 | 1245 | if ((1 << vdd) <= MMC_VDD_23_24) |
a45c6cb8 | 1246 | reg_val |= SDVS18; |
eb250826 DB |
1247 | else |
1248 | reg_val |= SDVS30; | |
a45c6cb8 MC |
1249 | |
1250 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); | |
e13bb300 | 1251 | set_sd_bus_power(host); |
a45c6cb8 MC |
1252 | |
1253 | return 0; | |
1254 | err: | |
b1e056ae | 1255 | dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); |
a45c6cb8 MC |
1256 | return ret; |
1257 | } | |
1258 | ||
b62f6228 AH |
1259 | /* Protect the card while the cover is open */ |
1260 | static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) | |
1261 | { | |
1262 | if (!mmc_slot(host).get_cover_state) | |
1263 | return; | |
1264 | ||
1265 | host->reqs_blocked = 0; | |
1266 | if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { | |
1267 | if (host->protect_card) { | |
2cecdf00 | 1268 | dev_info(host->dev, "%s: cover is closed, " |
b62f6228 AH |
1269 | "card is now accessible\n", |
1270 | mmc_hostname(host->mmc)); | |
1271 | host->protect_card = 0; | |
1272 | } | |
1273 | } else { | |
1274 | if (!host->protect_card) { | |
2cecdf00 | 1275 | dev_info(host->dev, "%s: cover is open, " |
b62f6228 AH |
1276 | "card is now inaccessible\n", |
1277 | mmc_hostname(host->mmc)); | |
1278 | host->protect_card = 1; | |
1279 | } | |
1280 | } | |
1281 | } | |
1282 | ||
a45c6cb8 | 1283 | /* |
7efab4f3 | 1284 | * irq handler to notify the core about card insertion/removal |
a45c6cb8 | 1285 | */ |
7efab4f3 | 1286 | static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) |
a45c6cb8 | 1287 | { |
7efab4f3 | 1288 | struct omap_hsmmc_host *host = dev_id; |
249d0fa9 | 1289 | struct omap_mmc_slot_data *slot = &mmc_slot(host); |
a6b2240d AH |
1290 | int carddetect; |
1291 | ||
a6b2240d | 1292 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); |
249d0fa9 | 1293 | |
191d1f1d | 1294 | if (slot->card_detect) |
db0fefc5 | 1295 | carddetect = slot->card_detect(host->dev, host->slot_id); |
b62f6228 AH |
1296 | else { |
1297 | omap_hsmmc_protect_card(host); | |
a6b2240d | 1298 | carddetect = -ENOSYS; |
b62f6228 | 1299 | } |
a45c6cb8 | 1300 | |
cdeebadd | 1301 | if (carddetect) |
a45c6cb8 | 1302 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); |
cdeebadd | 1303 | else |
a45c6cb8 | 1304 | mmc_detect_change(host->mmc, (HZ * 50) / 1000); |
a45c6cb8 MC |
1305 | return IRQ_HANDLED; |
1306 | } | |
1307 | ||
c5c98927 | 1308 | static void omap_hsmmc_dma_callback(void *param) |
a45c6cb8 | 1309 | { |
c5c98927 RK |
1310 | struct omap_hsmmc_host *host = param; |
1311 | struct dma_chan *chan; | |
770d7432 | 1312 | struct mmc_data *data; |
c5c98927 | 1313 | int req_in_progress; |
a45c6cb8 | 1314 | |
c5c98927 | 1315 | spin_lock_irq(&host->irq_lock); |
b417577d | 1316 | if (host->dma_ch < 0) { |
c5c98927 | 1317 | spin_unlock_irq(&host->irq_lock); |
a45c6cb8 | 1318 | return; |
b417577d | 1319 | } |
a45c6cb8 | 1320 | |
770d7432 | 1321 | data = host->mrq->data; |
c5c98927 | 1322 | chan = omap_hsmmc_get_dma_chan(host, data); |
9782aff8 | 1323 | if (!data->host_cookie) |
c5c98927 RK |
1324 | dma_unmap_sg(chan->device->dev, |
1325 | data->sg, data->sg_len, | |
9782aff8 | 1326 | omap_hsmmc_get_dma_dir(host, data)); |
b417577d AH |
1327 | |
1328 | req_in_progress = host->req_in_progress; | |
a45c6cb8 | 1329 | host->dma_ch = -1; |
c5c98927 | 1330 | spin_unlock_irq(&host->irq_lock); |
b417577d AH |
1331 | |
1332 | /* If DMA has finished after TC, complete the request */ | |
1333 | if (!req_in_progress) { | |
1334 | struct mmc_request *mrq = host->mrq; | |
1335 | ||
1336 | host->mrq = NULL; | |
1337 | mmc_request_done(host->mmc, mrq); | |
1338 | } | |
a45c6cb8 MC |
1339 | } |
1340 | ||
9782aff8 PF |
1341 | static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, |
1342 | struct mmc_data *data, | |
c5c98927 | 1343 | struct omap_hsmmc_next *next, |
26b88520 | 1344 | struct dma_chan *chan) |
9782aff8 PF |
1345 | { |
1346 | int dma_len; | |
1347 | ||
1348 | if (!next && data->host_cookie && | |
1349 | data->host_cookie != host->next_data.cookie) { | |
2cecdf00 | 1350 | dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" |
9782aff8 PF |
1351 | " host->next_data.cookie %d\n", |
1352 | __func__, data->host_cookie, host->next_data.cookie); | |
1353 | data->host_cookie = 0; | |
1354 | } | |
1355 | ||
1356 | /* Check if next job is already prepared */ | |
b38313d6 | 1357 | if (next || data->host_cookie != host->next_data.cookie) { |
26b88520 | 1358 | dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, |
9782aff8 PF |
1359 | omap_hsmmc_get_dma_dir(host, data)); |
1360 | ||
1361 | } else { | |
1362 | dma_len = host->next_data.dma_len; | |
1363 | host->next_data.dma_len = 0; | |
1364 | } | |
1365 | ||
1366 | ||
1367 | if (dma_len == 0) | |
1368 | return -EINVAL; | |
1369 | ||
1370 | if (next) { | |
1371 | next->dma_len = dma_len; | |
1372 | data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; | |
1373 | } else | |
1374 | host->dma_len = dma_len; | |
1375 | ||
1376 | return 0; | |
1377 | } | |
1378 | ||
a45c6cb8 MC |
1379 | /* |
1380 | * Routine to configure and start DMA for the MMC card | |
1381 | */ | |
9d025334 | 1382 | static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host, |
70a3341a | 1383 | struct mmc_request *req) |
a45c6cb8 | 1384 | { |
26b88520 RK |
1385 | struct dma_slave_config cfg; |
1386 | struct dma_async_tx_descriptor *tx; | |
1387 | int ret = 0, i; | |
a45c6cb8 | 1388 | struct mmc_data *data = req->data; |
c5c98927 | 1389 | struct dma_chan *chan; |
a45c6cb8 | 1390 | |
0ccd76d4 | 1391 | /* Sanity check: all the SG entries must be aligned by block size. */ |
a3f406f8 | 1392 | for (i = 0; i < data->sg_len; i++) { |
0ccd76d4 JY |
1393 | struct scatterlist *sgl; |
1394 | ||
1395 | sgl = data->sg + i; | |
1396 | if (sgl->length % data->blksz) | |
1397 | return -EINVAL; | |
1398 | } | |
1399 | if ((data->blksz % 4) != 0) | |
1400 | /* REVISIT: The MMC buffer increments only when MSB is written. | |
1401 | * Return error for blksz which is non multiple of four. | |
1402 | */ | |
1403 | return -EINVAL; | |
1404 | ||
b417577d | 1405 | BUG_ON(host->dma_ch != -1); |
a45c6cb8 | 1406 | |
c5c98927 | 1407 | chan = omap_hsmmc_get_dma_chan(host, data); |
c5c98927 | 1408 | |
26b88520 RK |
1409 | cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; |
1410 | cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; | |
1411 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1412 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1413 | cfg.src_maxburst = data->blksz / 4; | |
1414 | cfg.dst_maxburst = data->blksz / 4; | |
c5c98927 | 1415 | |
26b88520 RK |
1416 | ret = dmaengine_slave_config(chan, &cfg); |
1417 | if (ret) | |
a45c6cb8 | 1418 | return ret; |
c5c98927 | 1419 | |
26b88520 | 1420 | ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); |
9782aff8 PF |
1421 | if (ret) |
1422 | return ret; | |
a45c6cb8 | 1423 | |
26b88520 RK |
1424 | tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, |
1425 | data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
1426 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1427 | if (!tx) { | |
1428 | dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); | |
1429 | /* FIXME: cleanup */ | |
1430 | return -1; | |
1431 | } | |
a45c6cb8 | 1432 | |
26b88520 RK |
1433 | tx->callback = omap_hsmmc_dma_callback; |
1434 | tx->callback_param = host; | |
a45c6cb8 | 1435 | |
26b88520 RK |
1436 | /* Does not fail */ |
1437 | dmaengine_submit(tx); | |
c5c98927 | 1438 | |
26b88520 | 1439 | host->dma_ch = 1; |
c5c98927 | 1440 | |
a45c6cb8 MC |
1441 | return 0; |
1442 | } | |
1443 | ||
70a3341a | 1444 | static void set_data_timeout(struct omap_hsmmc_host *host, |
e2bf08d6 AH |
1445 | unsigned int timeout_ns, |
1446 | unsigned int timeout_clks) | |
a45c6cb8 MC |
1447 | { |
1448 | unsigned int timeout, cycle_ns; | |
1449 | uint32_t reg, clkd, dto = 0; | |
1450 | ||
1451 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); | |
1452 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; | |
1453 | if (clkd == 0) | |
1454 | clkd = 1; | |
1455 | ||
6e3076c2 | 1456 | cycle_ns = 1000000000 / (host->clk_rate / clkd); |
e2bf08d6 AH |
1457 | timeout = timeout_ns / cycle_ns; |
1458 | timeout += timeout_clks; | |
a45c6cb8 MC |
1459 | if (timeout) { |
1460 | while ((timeout & 0x80000000) == 0) { | |
1461 | dto += 1; | |
1462 | timeout <<= 1; | |
1463 | } | |
1464 | dto = 31 - dto; | |
1465 | timeout <<= 1; | |
1466 | if (timeout && dto) | |
1467 | dto += 1; | |
1468 | if (dto >= 13) | |
1469 | dto -= 13; | |
1470 | else | |
1471 | dto = 0; | |
1472 | if (dto > 14) | |
1473 | dto = 14; | |
1474 | } | |
1475 | ||
1476 | reg &= ~DTO_MASK; | |
1477 | reg |= dto << DTO_SHIFT; | |
1478 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); | |
1479 | } | |
1480 | ||
9d025334 B |
1481 | static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host) |
1482 | { | |
1483 | struct mmc_request *req = host->mrq; | |
1484 | struct dma_chan *chan; | |
1485 | ||
1486 | if (!req->data) | |
1487 | return; | |
1488 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) | |
1489 | | (req->data->blocks << 16)); | |
1490 | set_data_timeout(host, req->data->timeout_ns, | |
1491 | req->data->timeout_clks); | |
1492 | chan = omap_hsmmc_get_dma_chan(host, req->data); | |
1493 | dma_async_issue_pending(chan); | |
1494 | } | |
1495 | ||
a45c6cb8 MC |
1496 | /* |
1497 | * Configure block length for MMC/SD cards and initiate the transfer. | |
1498 | */ | |
1499 | static int | |
70a3341a | 1500 | omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) |
a45c6cb8 MC |
1501 | { |
1502 | int ret; | |
1503 | host->data = req->data; | |
1504 | ||
1505 | if (req->data == NULL) { | |
a45c6cb8 | 1506 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
e2bf08d6 AH |
1507 | /* |
1508 | * Set an arbitrary 100ms data timeout for commands with | |
1509 | * busy signal. | |
1510 | */ | |
1511 | if (req->cmd->flags & MMC_RSP_BUSY) | |
1512 | set_data_timeout(host, 100000000U, 0); | |
a45c6cb8 MC |
1513 | return 0; |
1514 | } | |
1515 | ||
a45c6cb8 | 1516 | if (host->use_dma) { |
9d025334 | 1517 | ret = omap_hsmmc_setup_dma_transfer(host, req); |
a45c6cb8 | 1518 | if (ret != 0) { |
b1e056ae | 1519 | dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); |
a45c6cb8 MC |
1520 | return ret; |
1521 | } | |
1522 | } | |
1523 | return 0; | |
1524 | } | |
1525 | ||
9782aff8 PF |
1526 | static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
1527 | int err) | |
1528 | { | |
1529 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1530 | struct mmc_data *data = mrq->data; | |
1531 | ||
26b88520 | 1532 | if (host->use_dma && data->host_cookie) { |
c5c98927 | 1533 | struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); |
c5c98927 | 1534 | |
26b88520 RK |
1535 | dma_unmap_sg(c->device->dev, data->sg, data->sg_len, |
1536 | omap_hsmmc_get_dma_dir(host, data)); | |
9782aff8 PF |
1537 | data->host_cookie = 0; |
1538 | } | |
1539 | } | |
1540 | ||
1541 | static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, | |
1542 | bool is_first_req) | |
1543 | { | |
1544 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1545 | ||
1546 | if (mrq->data->host_cookie) { | |
1547 | mrq->data->host_cookie = 0; | |
1548 | return ; | |
1549 | } | |
1550 | ||
c5c98927 RK |
1551 | if (host->use_dma) { |
1552 | struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); | |
c5c98927 | 1553 | |
9782aff8 | 1554 | if (omap_hsmmc_pre_dma_transfer(host, mrq->data, |
26b88520 | 1555 | &host->next_data, c)) |
9782aff8 | 1556 | mrq->data->host_cookie = 0; |
c5c98927 | 1557 | } |
9782aff8 PF |
1558 | } |
1559 | ||
a45c6cb8 MC |
1560 | /* |
1561 | * Request function. for read/write operation | |
1562 | */ | |
70a3341a | 1563 | static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) |
a45c6cb8 | 1564 | { |
70a3341a | 1565 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3f406f8 | 1566 | int err; |
a45c6cb8 | 1567 | |
b417577d AH |
1568 | BUG_ON(host->req_in_progress); |
1569 | BUG_ON(host->dma_ch != -1); | |
1570 | if (host->protect_card) { | |
1571 | if (host->reqs_blocked < 3) { | |
1572 | /* | |
1573 | * Ensure the controller is left in a consistent | |
1574 | * state by resetting the command and data state | |
1575 | * machines. | |
1576 | */ | |
1577 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
1578 | omap_hsmmc_reset_controller_fsm(host, SRC); | |
1579 | host->reqs_blocked += 1; | |
1580 | } | |
1581 | req->cmd->error = -EBADF; | |
1582 | if (req->data) | |
1583 | req->data->error = -EBADF; | |
1584 | req->cmd->retries = 0; | |
1585 | mmc_request_done(mmc, req); | |
1586 | return; | |
1587 | } else if (host->reqs_blocked) | |
1588 | host->reqs_blocked = 0; | |
a45c6cb8 MC |
1589 | WARN_ON(host->mrq != NULL); |
1590 | host->mrq = req; | |
6e3076c2 | 1591 | host->clk_rate = clk_get_rate(host->fclk); |
70a3341a | 1592 | err = omap_hsmmc_prepare_data(host, req); |
a3f406f8 JL |
1593 | if (err) { |
1594 | req->cmd->error = err; | |
1595 | if (req->data) | |
1596 | req->data->error = err; | |
1597 | host->mrq = NULL; | |
1598 | mmc_request_done(mmc, req); | |
1599 | return; | |
1600 | } | |
a2e77152 | 1601 | if (req->sbc && !(host->flags & AUTO_CMD23)) { |
bf129e1c B |
1602 | omap_hsmmc_start_command(host, req->sbc, NULL); |
1603 | return; | |
1604 | } | |
a3f406f8 | 1605 | |
9d025334 | 1606 | omap_hsmmc_start_dma_transfer(host); |
70a3341a | 1607 | omap_hsmmc_start_command(host, req->cmd, req->data); |
a45c6cb8 MC |
1608 | } |
1609 | ||
a45c6cb8 | 1610 | /* Routine to configure clock values. Exposed API to core */ |
70a3341a | 1611 | static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
a45c6cb8 | 1612 | { |
70a3341a | 1613 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3621465 | 1614 | int do_send_init_stream = 0; |
a45c6cb8 | 1615 | |
fa4aa2d4 | 1616 | pm_runtime_get_sync(host->dev); |
5e2ea617 | 1617 | |
a3621465 AH |
1618 | if (ios->power_mode != host->power_mode) { |
1619 | switch (ios->power_mode) { | |
1620 | case MMC_POWER_OFF: | |
1621 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1622 | 0, 0); | |
1623 | break; | |
1624 | case MMC_POWER_UP: | |
1625 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1626 | 1, ios->vdd); | |
1627 | break; | |
1628 | case MMC_POWER_ON: | |
1629 | do_send_init_stream = 1; | |
1630 | break; | |
1631 | } | |
1632 | host->power_mode = ios->power_mode; | |
a45c6cb8 MC |
1633 | } |
1634 | ||
dd498eff DK |
1635 | /* FIXME: set registers based only on changes to ios */ |
1636 | ||
3796fb8a | 1637 | omap_hsmmc_set_bus_width(host); |
a45c6cb8 | 1638 | |
4621d5f8 | 1639 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
eb250826 DB |
1640 | /* Only MMC1 can interface at 3V without some flavor |
1641 | * of external transceiver; but they all handle 1.8V. | |
1642 | */ | |
a45c6cb8 | 1643 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
2cf171cb | 1644 | (ios->vdd == DUAL_VOLT_OCR_BIT)) { |
a45c6cb8 MC |
1645 | /* |
1646 | * The mmc_select_voltage fn of the core does | |
1647 | * not seem to set the power_mode to | |
1648 | * MMC_POWER_UP upon recalculating the voltage. | |
1649 | * vdd 1.8v. | |
1650 | */ | |
70a3341a DK |
1651 | if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) |
1652 | dev_dbg(mmc_dev(host->mmc), | |
a45c6cb8 MC |
1653 | "Switch operation failed\n"); |
1654 | } | |
1655 | } | |
1656 | ||
5934df2f | 1657 | omap_hsmmc_set_clock(host); |
a45c6cb8 | 1658 | |
a3621465 | 1659 | if (do_send_init_stream) |
a45c6cb8 MC |
1660 | send_init_stream(host); |
1661 | ||
3796fb8a | 1662 | omap_hsmmc_set_bus_mode(host); |
5e2ea617 | 1663 | |
fa4aa2d4 | 1664 | pm_runtime_put_autosuspend(host->dev); |
a45c6cb8 MC |
1665 | } |
1666 | ||
1667 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) | |
1668 | { | |
70a3341a | 1669 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1670 | |
191d1f1d | 1671 | if (!mmc_slot(host).card_detect) |
a45c6cb8 | 1672 | return -ENOSYS; |
db0fefc5 | 1673 | return mmc_slot(host).card_detect(host->dev, host->slot_id); |
a45c6cb8 MC |
1674 | } |
1675 | ||
1676 | static int omap_hsmmc_get_ro(struct mmc_host *mmc) | |
1677 | { | |
70a3341a | 1678 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1679 | |
191d1f1d | 1680 | if (!mmc_slot(host).get_ro) |
a45c6cb8 | 1681 | return -ENOSYS; |
191d1f1d | 1682 | return mmc_slot(host).get_ro(host->dev, 0); |
a45c6cb8 MC |
1683 | } |
1684 | ||
4816858c GI |
1685 | static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) |
1686 | { | |
1687 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1688 | ||
1689 | if (mmc_slot(host).init_card) | |
1690 | mmc_slot(host).init_card(card); | |
1691 | } | |
1692 | ||
2cd3a2a5 AF |
1693 | static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable) |
1694 | { | |
1695 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
5a52b08b | 1696 | u32 irq_mask, con; |
2cd3a2a5 AF |
1697 | unsigned long flags; |
1698 | ||
1699 | spin_lock_irqsave(&host->irq_lock, flags); | |
1700 | ||
5a52b08b | 1701 | con = OMAP_HSMMC_READ(host->base, CON); |
2cd3a2a5 AF |
1702 | irq_mask = OMAP_HSMMC_READ(host->base, ISE); |
1703 | if (enable) { | |
1704 | host->flags |= HSMMC_SDIO_IRQ_ENABLED; | |
1705 | irq_mask |= CIRQ_EN; | |
5a52b08b | 1706 | con |= CTPL | CLKEXTFREE; |
2cd3a2a5 AF |
1707 | } else { |
1708 | host->flags &= ~HSMMC_SDIO_IRQ_ENABLED; | |
1709 | irq_mask &= ~CIRQ_EN; | |
5a52b08b | 1710 | con &= ~(CTPL | CLKEXTFREE); |
2cd3a2a5 | 1711 | } |
5a52b08b | 1712 | OMAP_HSMMC_WRITE(host->base, CON, con); |
2cd3a2a5 AF |
1713 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); |
1714 | ||
1715 | /* | |
1716 | * if enable, piggy back detection on current request | |
1717 | * but always disable immediately | |
1718 | */ | |
1719 | if (!host->req_in_progress || !enable) | |
1720 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); | |
1721 | ||
1722 | /* flush posted write */ | |
1723 | OMAP_HSMMC_READ(host->base, IE); | |
1724 | ||
1725 | spin_unlock_irqrestore(&host->irq_lock, flags); | |
1726 | } | |
1727 | ||
1728 | static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host) | |
1729 | { | |
1730 | struct mmc_host *mmc = host->mmc; | |
1731 | int ret; | |
1732 | ||
1733 | /* | |
1734 | * For omaps with wake-up path, wakeirq will be irq from pinctrl and | |
1735 | * for other omaps, wakeirq will be from GPIO (dat line remuxed to | |
1736 | * gpio). wakeirq is needed to detect sdio irq in runtime suspend state | |
1737 | * with functional clock disabled. | |
1738 | */ | |
1739 | if (!host->dev->of_node || !host->wake_irq) | |
1740 | return -ENODEV; | |
1741 | ||
1742 | /* Prevent auto-enabling of IRQ */ | |
1743 | irq_set_status_flags(host->wake_irq, IRQ_NOAUTOEN); | |
1744 | ret = devm_request_irq(host->dev, host->wake_irq, omap_hsmmc_wake_irq, | |
1745 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, | |
1746 | mmc_hostname(mmc), host); | |
1747 | if (ret) { | |
1748 | dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n"); | |
1749 | goto err; | |
1750 | } | |
1751 | ||
1752 | /* | |
1753 | * Some omaps don't have wake-up path from deeper idle states | |
1754 | * and need to remux SDIO DAT1 to GPIO for wake-up from idle. | |
1755 | */ | |
1756 | if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) { | |
1757 | ret = -ENODEV; | |
1758 | devm_free_irq(host->dev, host->wake_irq, host); | |
1759 | goto err; | |
1760 | } | |
1761 | ||
5a52b08b B |
1762 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1763 | OMAP_HSMMC_READ(host->base, HCTL) | IWE); | |
2cd3a2a5 AF |
1764 | return 0; |
1765 | ||
1766 | err: | |
1767 | dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n"); | |
1768 | host->wake_irq = 0; | |
1769 | return ret; | |
1770 | } | |
1771 | ||
70a3341a | 1772 | static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) |
1b331e69 KK |
1773 | { |
1774 | u32 hctl, capa, value; | |
1775 | ||
1776 | /* Only MMC1 supports 3.0V */ | |
4621d5f8 | 1777 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
1b331e69 KK |
1778 | hctl = SDVS30; |
1779 | capa = VS30 | VS18; | |
1780 | } else { | |
1781 | hctl = SDVS18; | |
1782 | capa = VS18; | |
1783 | } | |
1784 | ||
1785 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; | |
1786 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); | |
1787 | ||
1788 | value = OMAP_HSMMC_READ(host->base, CAPA); | |
1789 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); | |
1790 | ||
1b331e69 | 1791 | /* Set SD bus power bit */ |
e13bb300 | 1792 | set_sd_bus_power(host); |
1b331e69 KK |
1793 | } |
1794 | ||
70a3341a | 1795 | static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) |
dd498eff | 1796 | { |
70a3341a | 1797 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1798 | |
fa4aa2d4 B |
1799 | pm_runtime_get_sync(host->dev); |
1800 | ||
dd498eff DK |
1801 | return 0; |
1802 | } | |
1803 | ||
907d2e7c | 1804 | static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) |
dd498eff | 1805 | { |
70a3341a | 1806 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1807 | |
fa4aa2d4 B |
1808 | pm_runtime_mark_last_busy(host->dev); |
1809 | pm_runtime_put_autosuspend(host->dev); | |
1810 | ||
dd498eff DK |
1811 | return 0; |
1812 | } | |
1813 | ||
70a3341a DK |
1814 | static const struct mmc_host_ops omap_hsmmc_ops = { |
1815 | .enable = omap_hsmmc_enable_fclk, | |
1816 | .disable = omap_hsmmc_disable_fclk, | |
9782aff8 PF |
1817 | .post_req = omap_hsmmc_post_req, |
1818 | .pre_req = omap_hsmmc_pre_req, | |
70a3341a DK |
1819 | .request = omap_hsmmc_request, |
1820 | .set_ios = omap_hsmmc_set_ios, | |
dd498eff DK |
1821 | .get_cd = omap_hsmmc_get_cd, |
1822 | .get_ro = omap_hsmmc_get_ro, | |
4816858c | 1823 | .init_card = omap_hsmmc_init_card, |
2cd3a2a5 | 1824 | .enable_sdio_irq = omap_hsmmc_enable_sdio_irq, |
dd498eff DK |
1825 | }; |
1826 | ||
d900f712 DK |
1827 | #ifdef CONFIG_DEBUG_FS |
1828 | ||
70a3341a | 1829 | static int omap_hsmmc_regs_show(struct seq_file *s, void *data) |
d900f712 DK |
1830 | { |
1831 | struct mmc_host *mmc = s->private; | |
70a3341a | 1832 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
d900f712 | 1833 | |
bb0635f0 AF |
1834 | seq_printf(s, "mmc%d:\n", mmc->index); |
1835 | seq_printf(s, "sdio irq mode\t%s\n", | |
1836 | (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling"); | |
5e2ea617 | 1837 | |
bb0635f0 AF |
1838 | if (mmc->caps & MMC_CAP_SDIO_IRQ) { |
1839 | seq_printf(s, "sdio irq \t%s\n", | |
1840 | (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled" | |
1841 | : "disabled"); | |
1842 | } | |
1843 | seq_printf(s, "ctx_loss:\t%d\n", host->context_loss); | |
d900f712 | 1844 | |
bb0635f0 AF |
1845 | pm_runtime_get_sync(host->dev); |
1846 | seq_puts(s, "\nregs:\n"); | |
d900f712 DK |
1847 | seq_printf(s, "CON:\t\t0x%08x\n", |
1848 | OMAP_HSMMC_READ(host->base, CON)); | |
bb0635f0 AF |
1849 | seq_printf(s, "PSTATE:\t\t0x%08x\n", |
1850 | OMAP_HSMMC_READ(host->base, PSTATE)); | |
d900f712 DK |
1851 | seq_printf(s, "HCTL:\t\t0x%08x\n", |
1852 | OMAP_HSMMC_READ(host->base, HCTL)); | |
1853 | seq_printf(s, "SYSCTL:\t\t0x%08x\n", | |
1854 | OMAP_HSMMC_READ(host->base, SYSCTL)); | |
1855 | seq_printf(s, "IE:\t\t0x%08x\n", | |
1856 | OMAP_HSMMC_READ(host->base, IE)); | |
1857 | seq_printf(s, "ISE:\t\t0x%08x\n", | |
1858 | OMAP_HSMMC_READ(host->base, ISE)); | |
1859 | seq_printf(s, "CAPA:\t\t0x%08x\n", | |
1860 | OMAP_HSMMC_READ(host->base, CAPA)); | |
5e2ea617 | 1861 | |
fa4aa2d4 B |
1862 | pm_runtime_mark_last_busy(host->dev); |
1863 | pm_runtime_put_autosuspend(host->dev); | |
dd498eff | 1864 | |
d900f712 DK |
1865 | return 0; |
1866 | } | |
1867 | ||
70a3341a | 1868 | static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) |
d900f712 | 1869 | { |
70a3341a | 1870 | return single_open(file, omap_hsmmc_regs_show, inode->i_private); |
d900f712 DK |
1871 | } |
1872 | ||
1873 | static const struct file_operations mmc_regs_fops = { | |
70a3341a | 1874 | .open = omap_hsmmc_regs_open, |
d900f712 DK |
1875 | .read = seq_read, |
1876 | .llseek = seq_lseek, | |
1877 | .release = single_release, | |
1878 | }; | |
1879 | ||
70a3341a | 1880 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1881 | { |
1882 | if (mmc->debugfs_root) | |
1883 | debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, | |
1884 | mmc, &mmc_regs_fops); | |
1885 | } | |
1886 | ||
1887 | #else | |
1888 | ||
70a3341a | 1889 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1890 | { |
1891 | } | |
1892 | ||
1893 | #endif | |
1894 | ||
46856a68 | 1895 | #ifdef CONFIG_OF |
59445b10 NM |
1896 | static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = { |
1897 | /* See 35xx errata 2.1.1.128 in SPRZ278F */ | |
1898 | .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ, | |
1899 | }; | |
1900 | ||
1901 | static const struct omap_mmc_of_data omap4_mmc_of_data = { | |
1902 | .reg_offset = 0x100, | |
1903 | }; | |
2cd3a2a5 AF |
1904 | static const struct omap_mmc_of_data am33xx_mmc_of_data = { |
1905 | .reg_offset = 0x100, | |
1906 | .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING, | |
1907 | }; | |
46856a68 RN |
1908 | |
1909 | static const struct of_device_id omap_mmc_of_match[] = { | |
1910 | { | |
1911 | .compatible = "ti,omap2-hsmmc", | |
1912 | }, | |
59445b10 NM |
1913 | { |
1914 | .compatible = "ti,omap3-pre-es3-hsmmc", | |
1915 | .data = &omap3_pre_es3_mmc_of_data, | |
1916 | }, | |
46856a68 RN |
1917 | { |
1918 | .compatible = "ti,omap3-hsmmc", | |
1919 | }, | |
1920 | { | |
1921 | .compatible = "ti,omap4-hsmmc", | |
59445b10 | 1922 | .data = &omap4_mmc_of_data, |
46856a68 | 1923 | }, |
2cd3a2a5 AF |
1924 | { |
1925 | .compatible = "ti,am33xx-hsmmc", | |
1926 | .data = &am33xx_mmc_of_data, | |
1927 | }, | |
46856a68 | 1928 | {}, |
b6d085f6 | 1929 | }; |
46856a68 RN |
1930 | MODULE_DEVICE_TABLE(of, omap_mmc_of_match); |
1931 | ||
1932 | static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) | |
1933 | { | |
1934 | struct omap_mmc_platform_data *pdata; | |
1935 | struct device_node *np = dev->of_node; | |
d8714e87 | 1936 | u32 bus_width, max_freq; |
dc642c28 JL |
1937 | int cd_gpio, wp_gpio; |
1938 | ||
1939 | cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); | |
1940 | wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); | |
1941 | if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) | |
1942 | return ERR_PTR(-EPROBE_DEFER); | |
46856a68 RN |
1943 | |
1944 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
1945 | if (!pdata) | |
19df45bc | 1946 | return ERR_PTR(-ENOMEM); /* out of memory */ |
46856a68 RN |
1947 | |
1948 | if (of_find_property(np, "ti,dual-volt", NULL)) | |
1949 | pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; | |
1950 | ||
1951 | /* This driver only supports 1 slot */ | |
1952 | pdata->nr_slots = 1; | |
dc642c28 JL |
1953 | pdata->slots[0].switch_pin = cd_gpio; |
1954 | pdata->slots[0].gpio_wp = wp_gpio; | |
46856a68 RN |
1955 | |
1956 | if (of_find_property(np, "ti,non-removable", NULL)) { | |
1957 | pdata->slots[0].nonremovable = true; | |
1958 | pdata->slots[0].no_regulator_off_init = true; | |
1959 | } | |
7f217794 | 1960 | of_property_read_u32(np, "bus-width", &bus_width); |
46856a68 RN |
1961 | if (bus_width == 4) |
1962 | pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; | |
1963 | else if (bus_width == 8) | |
1964 | pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; | |
1965 | ||
1966 | if (of_find_property(np, "ti,needs-special-reset", NULL)) | |
1967 | pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; | |
1968 | ||
d8714e87 DM |
1969 | if (!of_property_read_u32(np, "max-frequency", &max_freq)) |
1970 | pdata->max_freq = max_freq; | |
1971 | ||
cd587096 HG |
1972 | if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) |
1973 | pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; | |
1974 | ||
c9ae64db DM |
1975 | if (of_find_property(np, "keep-power-in-suspend", NULL)) |
1976 | pdata->slots[0].pm_caps |= MMC_PM_KEEP_POWER; | |
1977 | ||
1978 | if (of_find_property(np, "enable-sdio-wakeup", NULL)) | |
1979 | pdata->slots[0].pm_caps |= MMC_PM_WAKE_SDIO_IRQ; | |
1980 | ||
46856a68 RN |
1981 | return pdata; |
1982 | } | |
1983 | #else | |
1984 | static inline struct omap_mmc_platform_data | |
1985 | *of_get_hsmmc_pdata(struct device *dev) | |
1986 | { | |
19df45bc | 1987 | return ERR_PTR(-EINVAL); |
46856a68 RN |
1988 | } |
1989 | #endif | |
1990 | ||
c3be1efd | 1991 | static int omap_hsmmc_probe(struct platform_device *pdev) |
a45c6cb8 MC |
1992 | { |
1993 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; | |
1994 | struct mmc_host *mmc; | |
70a3341a | 1995 | struct omap_hsmmc_host *host = NULL; |
a45c6cb8 | 1996 | struct resource *res; |
db0fefc5 | 1997 | int ret, irq; |
46856a68 | 1998 | const struct of_device_id *match; |
26b88520 RK |
1999 | dma_cap_mask_t mask; |
2000 | unsigned tx_req, rx_req; | |
59445b10 | 2001 | const struct omap_mmc_of_data *data; |
77fae219 | 2002 | void __iomem *base; |
46856a68 RN |
2003 | |
2004 | match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); | |
2005 | if (match) { | |
2006 | pdata = of_get_hsmmc_pdata(&pdev->dev); | |
dc642c28 JL |
2007 | |
2008 | if (IS_ERR(pdata)) | |
2009 | return PTR_ERR(pdata); | |
2010 | ||
46856a68 | 2011 | if (match->data) { |
59445b10 NM |
2012 | data = match->data; |
2013 | pdata->reg_offset = data->reg_offset; | |
2014 | pdata->controller_flags |= data->controller_flags; | |
46856a68 RN |
2015 | } |
2016 | } | |
a45c6cb8 MC |
2017 | |
2018 | if (pdata == NULL) { | |
2019 | dev_err(&pdev->dev, "Platform Data is missing\n"); | |
2020 | return -ENXIO; | |
2021 | } | |
2022 | ||
2023 | if (pdata->nr_slots == 0) { | |
2024 | dev_err(&pdev->dev, "No Slots\n"); | |
2025 | return -ENXIO; | |
2026 | } | |
2027 | ||
2028 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
2029 | irq = platform_get_irq(pdev, 0); | |
2030 | if (res == NULL || irq < 0) | |
2031 | return -ENXIO; | |
2032 | ||
77fae219 B |
2033 | base = devm_ioremap_resource(&pdev->dev, res); |
2034 | if (IS_ERR(base)) | |
2035 | return PTR_ERR(base); | |
a45c6cb8 | 2036 | |
db0fefc5 AH |
2037 | ret = omap_hsmmc_gpio_init(pdata); |
2038 | if (ret) | |
2039 | goto err; | |
2040 | ||
70a3341a | 2041 | mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); |
a45c6cb8 MC |
2042 | if (!mmc) { |
2043 | ret = -ENOMEM; | |
db0fefc5 | 2044 | goto err_alloc; |
a45c6cb8 MC |
2045 | } |
2046 | ||
2047 | host = mmc_priv(mmc); | |
2048 | host->mmc = mmc; | |
2049 | host->pdata = pdata; | |
2050 | host->dev = &pdev->dev; | |
2051 | host->use_dma = 1; | |
a45c6cb8 MC |
2052 | host->dma_ch = -1; |
2053 | host->irq = irq; | |
a45c6cb8 | 2054 | host->slot_id = 0; |
fc307df8 | 2055 | host->mapbase = res->start + pdata->reg_offset; |
77fae219 | 2056 | host->base = base + pdata->reg_offset; |
6da20c89 | 2057 | host->power_mode = MMC_POWER_OFF; |
9782aff8 | 2058 | host->next_data.cookie = 1; |
e99448ff | 2059 | host->pbias_enabled = 0; |
a45c6cb8 MC |
2060 | |
2061 | platform_set_drvdata(pdev, host); | |
a45c6cb8 | 2062 | |
2cd3a2a5 AF |
2063 | if (pdev->dev.of_node) |
2064 | host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1); | |
2065 | ||
7a8c2cef | 2066 | mmc->ops = &omap_hsmmc_ops; |
dd498eff | 2067 | |
d418ed87 DM |
2068 | mmc->f_min = OMAP_MMC_MIN_CLOCK; |
2069 | ||
2070 | if (pdata->max_freq > 0) | |
2071 | mmc->f_max = pdata->max_freq; | |
2072 | else | |
2073 | mmc->f_max = OMAP_MMC_MAX_CLOCK; | |
a45c6cb8 | 2074 | |
4dffd7a2 | 2075 | spin_lock_init(&host->irq_lock); |
a45c6cb8 | 2076 | |
9618195e | 2077 | host->fclk = devm_clk_get(&pdev->dev, "fck"); |
a45c6cb8 MC |
2078 | if (IS_ERR(host->fclk)) { |
2079 | ret = PTR_ERR(host->fclk); | |
2080 | host->fclk = NULL; | |
a45c6cb8 MC |
2081 | goto err1; |
2082 | } | |
2083 | ||
9b68256c PW |
2084 | if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { |
2085 | dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); | |
2086 | mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; | |
2087 | } | |
dd498eff | 2088 | |
fa4aa2d4 B |
2089 | pm_runtime_enable(host->dev); |
2090 | pm_runtime_get_sync(host->dev); | |
2091 | pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); | |
2092 | pm_runtime_use_autosuspend(host->dev); | |
a45c6cb8 | 2093 | |
92a3aebf B |
2094 | omap_hsmmc_context_save(host); |
2095 | ||
9618195e | 2096 | host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck"); |
cd03d9a8 RN |
2097 | /* |
2098 | * MMC can still work without debounce clock. | |
2099 | */ | |
2100 | if (IS_ERR(host->dbclk)) { | |
cd03d9a8 | 2101 | host->dbclk = NULL; |
94c18149 | 2102 | } else if (clk_prepare_enable(host->dbclk) != 0) { |
cd03d9a8 | 2103 | dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); |
cd03d9a8 | 2104 | host->dbclk = NULL; |
2bec0893 | 2105 | } |
a45c6cb8 | 2106 | |
0ccd76d4 JY |
2107 | /* Since we do only SG emulation, we can have as many segs |
2108 | * as we want. */ | |
a36274e0 | 2109 | mmc->max_segs = 1024; |
0ccd76d4 | 2110 | |
a45c6cb8 MC |
2111 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
2112 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ | |
2113 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
2114 | mmc->max_seg_size = mmc->max_req_size; | |
2115 | ||
13189e78 | 2116 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
93caf8e6 | 2117 | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; |
a45c6cb8 | 2118 | |
3a63833e SG |
2119 | mmc->caps |= mmc_slot(host).caps; |
2120 | if (mmc->caps & MMC_CAP_8_BIT_DATA) | |
a45c6cb8 MC |
2121 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
2122 | ||
191d1f1d | 2123 | if (mmc_slot(host).nonremovable) |
23d99bb9 AH |
2124 | mmc->caps |= MMC_CAP_NONREMOVABLE; |
2125 | ||
6fdc75de EP |
2126 | mmc->pm_caps = mmc_slot(host).pm_caps; |
2127 | ||
70a3341a | 2128 | omap_hsmmc_conf_bus_power(host); |
a45c6cb8 | 2129 | |
4a29b559 SS |
2130 | if (!pdev->dev.of_node) { |
2131 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); | |
2132 | if (!res) { | |
2133 | dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); | |
2134 | ret = -ENXIO; | |
2135 | goto err_irq; | |
2136 | } | |
2137 | tx_req = res->start; | |
b7bf773b | 2138 | |
4a29b559 SS |
2139 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); |
2140 | if (!res) { | |
2141 | dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); | |
2142 | ret = -ENXIO; | |
2143 | goto err_irq; | |
2144 | } | |
2145 | rx_req = res->start; | |
f3e2f1dd | 2146 | } |
a45c6cb8 | 2147 | |
26b88520 RK |
2148 | dma_cap_zero(mask); |
2149 | dma_cap_set(DMA_SLAVE, mask); | |
2150 | ||
d272fbf0 MP |
2151 | host->rx_chan = |
2152 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
2153 | &rx_req, &pdev->dev, "rx"); | |
2154 | ||
26b88520 RK |
2155 | if (!host->rx_chan) { |
2156 | dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); | |
04e8c7bc | 2157 | ret = -ENXIO; |
26b88520 RK |
2158 | goto err_irq; |
2159 | } | |
2160 | ||
d272fbf0 MP |
2161 | host->tx_chan = |
2162 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
2163 | &tx_req, &pdev->dev, "tx"); | |
2164 | ||
26b88520 RK |
2165 | if (!host->tx_chan) { |
2166 | dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); | |
04e8c7bc | 2167 | ret = -ENXIO; |
26b88520 | 2168 | goto err_irq; |
c5c98927 | 2169 | } |
a45c6cb8 MC |
2170 | |
2171 | /* Request IRQ for MMC operations */ | |
e1538ed7 | 2172 | ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0, |
a45c6cb8 MC |
2173 | mmc_hostname(mmc), host); |
2174 | if (ret) { | |
b1e056ae | 2175 | dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); |
a45c6cb8 MC |
2176 | goto err_irq; |
2177 | } | |
2178 | ||
2179 | if (pdata->init != NULL) { | |
2180 | if (pdata->init(&pdev->dev) != 0) { | |
b1e056ae | 2181 | dev_err(mmc_dev(host->mmc), |
70a3341a | 2182 | "Unable to configure MMC IRQs\n"); |
e1538ed7 | 2183 | goto err_irq; |
a45c6cb8 MC |
2184 | } |
2185 | } | |
db0fefc5 | 2186 | |
b702b106 | 2187 | if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { |
db0fefc5 AH |
2188 | ret = omap_hsmmc_reg_get(host); |
2189 | if (ret) | |
2190 | goto err_reg; | |
2191 | host->use_reg = 1; | |
2192 | } | |
2193 | ||
b583f26d | 2194 | mmc->ocr_avail = mmc_slot(host).ocr_mask; |
a45c6cb8 MC |
2195 | |
2196 | /* Request IRQ for card detect */ | |
e1a55f5e | 2197 | if ((mmc_slot(host).card_detect_irq)) { |
9fa0e05e B |
2198 | ret = devm_request_threaded_irq(&pdev->dev, |
2199 | mmc_slot(host).card_detect_irq, | |
2200 | NULL, omap_hsmmc_detect, | |
db35f83e | 2201 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
7efab4f3 | 2202 | mmc_hostname(mmc), host); |
a45c6cb8 | 2203 | if (ret) { |
b1e056ae | 2204 | dev_err(mmc_dev(host->mmc), |
a45c6cb8 MC |
2205 | "Unable to grab MMC CD IRQ\n"); |
2206 | goto err_irq_cd; | |
2207 | } | |
72f2e2c7 | 2208 | pdata->suspend = omap_hsmmc_suspend_cdirq; |
2209 | pdata->resume = omap_hsmmc_resume_cdirq; | |
a45c6cb8 MC |
2210 | } |
2211 | ||
b417577d | 2212 | omap_hsmmc_disable_irq(host); |
a45c6cb8 | 2213 | |
2cd3a2a5 AF |
2214 | /* |
2215 | * For now, only support SDIO interrupt if we have a separate | |
2216 | * wake-up interrupt configured from device tree. This is because | |
2217 | * the wake-up interrupt is needed for idle state and some | |
2218 | * platforms need special quirks. And we don't want to add new | |
2219 | * legacy mux platform init code callbacks any longer as we | |
2220 | * are moving to DT based booting anyways. | |
2221 | */ | |
2222 | ret = omap_hsmmc_configure_wake_irq(host); | |
2223 | if (!ret) | |
2224 | mmc->caps |= MMC_CAP_SDIO_IRQ; | |
2225 | ||
b62f6228 AH |
2226 | omap_hsmmc_protect_card(host); |
2227 | ||
a45c6cb8 MC |
2228 | mmc_add_host(mmc); |
2229 | ||
191d1f1d | 2230 | if (mmc_slot(host).name != NULL) { |
a45c6cb8 MC |
2231 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); |
2232 | if (ret < 0) | |
2233 | goto err_slot_name; | |
2234 | } | |
191d1f1d | 2235 | if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { |
a45c6cb8 MC |
2236 | ret = device_create_file(&mmc->class_dev, |
2237 | &dev_attr_cover_switch); | |
2238 | if (ret < 0) | |
db0fefc5 | 2239 | goto err_slot_name; |
a45c6cb8 MC |
2240 | } |
2241 | ||
70a3341a | 2242 | omap_hsmmc_debugfs(mmc); |
fa4aa2d4 B |
2243 | pm_runtime_mark_last_busy(host->dev); |
2244 | pm_runtime_put_autosuspend(host->dev); | |
d900f712 | 2245 | |
a45c6cb8 MC |
2246 | return 0; |
2247 | ||
a45c6cb8 MC |
2248 | err_slot_name: |
2249 | mmc_remove_host(mmc); | |
db0fefc5 AH |
2250 | err_irq_cd: |
2251 | if (host->use_reg) | |
2252 | omap_hsmmc_reg_put(host); | |
2253 | err_reg: | |
2254 | if (host->pdata->cleanup) | |
2255 | host->pdata->cleanup(&pdev->dev); | |
a45c6cb8 | 2256 | err_irq: |
c5c98927 RK |
2257 | if (host->tx_chan) |
2258 | dma_release_channel(host->tx_chan); | |
2259 | if (host->rx_chan) | |
2260 | dma_release_channel(host->rx_chan); | |
d59d77ed | 2261 | pm_runtime_put_sync(host->dev); |
37f6190d | 2262 | pm_runtime_disable(host->dev); |
9618195e | 2263 | if (host->dbclk) |
94c18149 | 2264 | clk_disable_unprepare(host->dbclk); |
a45c6cb8 | 2265 | err1: |
db0fefc5 AH |
2266 | mmc_free_host(mmc); |
2267 | err_alloc: | |
2268 | omap_hsmmc_gpio_free(pdata); | |
a45c6cb8 | 2269 | err: |
a45c6cb8 MC |
2270 | return ret; |
2271 | } | |
2272 | ||
6e0ee714 | 2273 | static int omap_hsmmc_remove(struct platform_device *pdev) |
a45c6cb8 | 2274 | { |
70a3341a | 2275 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 | 2276 | |
927ce944 FB |
2277 | pm_runtime_get_sync(host->dev); |
2278 | mmc_remove_host(host->mmc); | |
2279 | if (host->use_reg) | |
2280 | omap_hsmmc_reg_put(host); | |
2281 | if (host->pdata->cleanup) | |
2282 | host->pdata->cleanup(&pdev->dev); | |
a45c6cb8 | 2283 | |
c5c98927 RK |
2284 | if (host->tx_chan) |
2285 | dma_release_channel(host->tx_chan); | |
2286 | if (host->rx_chan) | |
2287 | dma_release_channel(host->rx_chan); | |
2288 | ||
927ce944 FB |
2289 | pm_runtime_put_sync(host->dev); |
2290 | pm_runtime_disable(host->dev); | |
9618195e | 2291 | if (host->dbclk) |
94c18149 | 2292 | clk_disable_unprepare(host->dbclk); |
a45c6cb8 | 2293 | |
9ea28ecb | 2294 | omap_hsmmc_gpio_free(host->pdata); |
9d1f0286 | 2295 | mmc_free_host(host->mmc); |
927ce944 | 2296 | |
a45c6cb8 MC |
2297 | return 0; |
2298 | } | |
2299 | ||
2300 | #ifdef CONFIG_PM | |
a48ce884 FB |
2301 | static int omap_hsmmc_prepare(struct device *dev) |
2302 | { | |
2303 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); | |
2304 | ||
2305 | if (host->pdata->suspend) | |
2306 | return host->pdata->suspend(dev, host->slot_id); | |
2307 | ||
2308 | return 0; | |
2309 | } | |
2310 | ||
2311 | static void omap_hsmmc_complete(struct device *dev) | |
2312 | { | |
2313 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); | |
2314 | ||
2315 | if (host->pdata->resume) | |
2316 | host->pdata->resume(dev, host->slot_id); | |
2317 | ||
2318 | } | |
2319 | ||
a791daa1 | 2320 | static int omap_hsmmc_suspend(struct device *dev) |
a45c6cb8 | 2321 | { |
927ce944 | 2322 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
a45c6cb8 | 2323 | |
927ce944 | 2324 | if (!host) |
a45c6cb8 MC |
2325 | return 0; |
2326 | ||
927ce944 | 2327 | pm_runtime_get_sync(host->dev); |
31f9d463 | 2328 | |
927ce944 | 2329 | if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { |
2cd3a2a5 AF |
2330 | OMAP_HSMMC_WRITE(host->base, ISE, 0); |
2331 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
2332 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
927ce944 FB |
2333 | OMAP_HSMMC_WRITE(host->base, HCTL, |
2334 | OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); | |
a45c6cb8 | 2335 | } |
927ce944 | 2336 | |
2cd3a2a5 AF |
2337 | /* do not wake up due to sdio irq */ |
2338 | if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && | |
2339 | !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) | |
2340 | disable_irq(host->wake_irq); | |
2341 | ||
cd03d9a8 | 2342 | if (host->dbclk) |
94c18149 | 2343 | clk_disable_unprepare(host->dbclk); |
3932afd5 | 2344 | |
31f9d463 | 2345 | pm_runtime_put_sync(host->dev); |
3932afd5 | 2346 | return 0; |
a45c6cb8 MC |
2347 | } |
2348 | ||
2349 | /* Routine to resume the MMC device */ | |
a791daa1 | 2350 | static int omap_hsmmc_resume(struct device *dev) |
a45c6cb8 | 2351 | { |
927ce944 FB |
2352 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
2353 | ||
2354 | if (!host) | |
2355 | return 0; | |
a45c6cb8 | 2356 | |
927ce944 | 2357 | pm_runtime_get_sync(host->dev); |
11dd62a7 | 2358 | |
cd03d9a8 | 2359 | if (host->dbclk) |
94c18149 | 2360 | clk_prepare_enable(host->dbclk); |
2bec0893 | 2361 | |
927ce944 FB |
2362 | if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) |
2363 | omap_hsmmc_conf_bus_power(host); | |
1b331e69 | 2364 | |
927ce944 | 2365 | omap_hsmmc_protect_card(host); |
b62f6228 | 2366 | |
2cd3a2a5 AF |
2367 | if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && |
2368 | !(host->mmc->pm_flags & MMC_PM_WAKE_SDIO_IRQ)) | |
2369 | enable_irq(host->wake_irq); | |
2370 | ||
927ce944 FB |
2371 | pm_runtime_mark_last_busy(host->dev); |
2372 | pm_runtime_put_autosuspend(host->dev); | |
3932afd5 | 2373 | return 0; |
a45c6cb8 MC |
2374 | } |
2375 | ||
2376 | #else | |
a48ce884 FB |
2377 | #define omap_hsmmc_prepare NULL |
2378 | #define omap_hsmmc_complete NULL | |
70a3341a | 2379 | #define omap_hsmmc_suspend NULL |
a48ce884 | 2380 | #define omap_hsmmc_resume NULL |
a45c6cb8 MC |
2381 | #endif |
2382 | ||
fa4aa2d4 B |
2383 | static int omap_hsmmc_runtime_suspend(struct device *dev) |
2384 | { | |
2385 | struct omap_hsmmc_host *host; | |
2cd3a2a5 | 2386 | unsigned long flags; |
f945901f | 2387 | int ret = 0; |
fa4aa2d4 B |
2388 | |
2389 | host = platform_get_drvdata(to_platform_device(dev)); | |
2390 | omap_hsmmc_context_save(host); | |
927ce944 | 2391 | dev_dbg(dev, "disabled\n"); |
fa4aa2d4 | 2392 | |
2cd3a2a5 AF |
2393 | spin_lock_irqsave(&host->irq_lock, flags); |
2394 | if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && | |
2395 | (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { | |
2396 | /* disable sdio irq handling to prevent race */ | |
2397 | OMAP_HSMMC_WRITE(host->base, ISE, 0); | |
2398 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
f945901f AF |
2399 | |
2400 | if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) { | |
2401 | /* | |
2402 | * dat1 line low, pending sdio irq | |
2403 | * race condition: possible irq handler running on | |
2404 | * multi-core, abort | |
2405 | */ | |
2406 | dev_dbg(dev, "pending sdio irq, abort suspend\n"); | |
2407 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
2408 | OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); | |
2409 | OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); | |
2410 | pm_runtime_mark_last_busy(dev); | |
2411 | ret = -EBUSY; | |
2412 | goto abort; | |
2413 | } | |
2cd3a2a5 | 2414 | |
97978a44 AF |
2415 | pinctrl_pm_select_idle_state(dev); |
2416 | ||
2cd3a2a5 AF |
2417 | WARN_ON(host->flags & HSMMC_WAKE_IRQ_ENABLED); |
2418 | enable_irq(host->wake_irq); | |
2419 | host->flags |= HSMMC_WAKE_IRQ_ENABLED; | |
97978a44 AF |
2420 | } else { |
2421 | pinctrl_pm_select_idle_state(dev); | |
2cd3a2a5 | 2422 | } |
97978a44 | 2423 | |
f945901f | 2424 | abort: |
2cd3a2a5 | 2425 | spin_unlock_irqrestore(&host->irq_lock, flags); |
f945901f | 2426 | return ret; |
fa4aa2d4 B |
2427 | } |
2428 | ||
2429 | static int omap_hsmmc_runtime_resume(struct device *dev) | |
2430 | { | |
2431 | struct omap_hsmmc_host *host; | |
2cd3a2a5 | 2432 | unsigned long flags; |
fa4aa2d4 B |
2433 | |
2434 | host = platform_get_drvdata(to_platform_device(dev)); | |
2435 | omap_hsmmc_context_restore(host); | |
927ce944 | 2436 | dev_dbg(dev, "enabled\n"); |
fa4aa2d4 | 2437 | |
2cd3a2a5 AF |
2438 | spin_lock_irqsave(&host->irq_lock, flags); |
2439 | if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) && | |
2440 | (host->flags & HSMMC_SDIO_IRQ_ENABLED)) { | |
2441 | /* sdio irq flag can't change while in runtime suspend */ | |
2442 | if (host->flags & HSMMC_WAKE_IRQ_ENABLED) { | |
2443 | disable_irq_nosync(host->wake_irq); | |
2444 | host->flags &= ~HSMMC_WAKE_IRQ_ENABLED; | |
2445 | } | |
2446 | ||
97978a44 AF |
2447 | pinctrl_pm_select_default_state(host->dev); |
2448 | ||
2449 | /* irq lost, if pinmux incorrect */ | |
2cd3a2a5 AF |
2450 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
2451 | OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN); | |
2452 | OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN); | |
97978a44 AF |
2453 | } else { |
2454 | pinctrl_pm_select_default_state(host->dev); | |
2cd3a2a5 AF |
2455 | } |
2456 | spin_unlock_irqrestore(&host->irq_lock, flags); | |
fa4aa2d4 B |
2457 | return 0; |
2458 | } | |
2459 | ||
a791daa1 | 2460 | static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { |
70a3341a DK |
2461 | .suspend = omap_hsmmc_suspend, |
2462 | .resume = omap_hsmmc_resume, | |
a48ce884 FB |
2463 | .prepare = omap_hsmmc_prepare, |
2464 | .complete = omap_hsmmc_complete, | |
fa4aa2d4 B |
2465 | .runtime_suspend = omap_hsmmc_runtime_suspend, |
2466 | .runtime_resume = omap_hsmmc_runtime_resume, | |
a791daa1 KH |
2467 | }; |
2468 | ||
2469 | static struct platform_driver omap_hsmmc_driver = { | |
efa25fd3 | 2470 | .probe = omap_hsmmc_probe, |
0433c143 | 2471 | .remove = omap_hsmmc_remove, |
a45c6cb8 MC |
2472 | .driver = { |
2473 | .name = DRIVER_NAME, | |
2474 | .owner = THIS_MODULE, | |
a791daa1 | 2475 | .pm = &omap_hsmmc_dev_pm_ops, |
46856a68 | 2476 | .of_match_table = of_match_ptr(omap_mmc_of_match), |
a45c6cb8 MC |
2477 | }, |
2478 | }; | |
2479 | ||
b796450b | 2480 | module_platform_driver(omap_hsmmc_driver); |
a45c6cb8 MC |
2481 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); |
2482 | MODULE_LICENSE("GPL"); | |
2483 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2484 | MODULE_AUTHOR("Texas Instruments Inc"); |