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omap_hsmmc: keep track of power mode
[mirror_ubuntu-focal-kernel.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
30#include <linux/io.h>
31#include <linux/semaphore.h>
32#include <mach/dma.h>
33#include <mach/hardware.h>
34#include <mach/board.h>
35#include <mach/mmc.h>
36#include <mach/cpu.h>
37
38/* OMAP HSMMC Host Controller Registers */
39#define OMAP_HSMMC_SYSCONFIG 0x0010
40#define OMAP_HSMMC_CON 0x002C
41#define OMAP_HSMMC_BLK 0x0104
42#define OMAP_HSMMC_ARG 0x0108
43#define OMAP_HSMMC_CMD 0x010C
44#define OMAP_HSMMC_RSP10 0x0110
45#define OMAP_HSMMC_RSP32 0x0114
46#define OMAP_HSMMC_RSP54 0x0118
47#define OMAP_HSMMC_RSP76 0x011C
48#define OMAP_HSMMC_DATA 0x0120
49#define OMAP_HSMMC_HCTL 0x0128
50#define OMAP_HSMMC_SYSCTL 0x012C
51#define OMAP_HSMMC_STAT 0x0130
52#define OMAP_HSMMC_IE 0x0134
53#define OMAP_HSMMC_ISE 0x0138
54#define OMAP_HSMMC_CAPA 0x0140
55
56#define VS18 (1 << 26)
57#define VS30 (1 << 25)
58#define SDVS18 (0x5 << 9)
59#define SDVS30 (0x6 << 9)
eb250826 60#define SDVS33 (0x7 << 9)
1b331e69 61#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 62#define SDVSCLR 0xFFFFF1FF
63#define SDVSDET 0x00000400
64#define AUTOIDLE 0x1
65#define SDBP (1 << 8)
66#define DTO 0xe
67#define ICE 0x1
68#define ICS 0x2
69#define CEN (1 << 2)
70#define CLKD_MASK 0x0000FFC0
71#define CLKD_SHIFT 6
72#define DTO_MASK 0x000F0000
73#define DTO_SHIFT 16
74#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 75#define BWR_ENABLE (1 << 4)
76#define BRR_ENABLE (1 << 5)
a45c6cb8
MC		 77#define INIT_STREAM (1 << 1)
78#define DP_SELECT (1 << 21)
79#define DDIR (1 << 4)
80#define DMA_EN 0x1
81#define MSBS (1 << 5)
82#define BCE (1 << 1)
83#define FOUR_BIT (1 << 1)
73153010 84#define DW8 (1 << 5)
a45c6cb8
MC		 85#define CC 0x1
86#define TC 0x02
87#define OD 0x1
88#define ERR (1 << 15)
89#define CMD_TIMEOUT (1 << 16)
90#define DATA_TIMEOUT (1 << 20)
91#define CMD_CRC (1 << 17)
92#define DATA_CRC (1 << 21)
93#define CARD_ERR (1 << 28)
94#define STAT_CLEAR 0xFFFFFFFF
95#define INIT_STREAM_CMD 0x00000000
96#define DUAL_VOLT_OCR_BIT 7
97#define SRC (1 << 25)
98#define SRD (1 << 26)
99
100/*
101 * FIXME: Most likely all the data using these _DEVID defines should come
102 * from the platform_data, or implemented in controller and slot specific
103 * functions.
104 */
105#define OMAP_MMC1_DEVID 0
106#define OMAP_MMC2_DEVID 1
f3e2f1dd 107#define OMAP_MMC3_DEVID 2
a45c6cb8 108
a45c6cb8
MC		 109#define MMC_TIMEOUT_MS 20
110#define OMAP_MMC_MASTER_CLOCK 96000000
111#define DRIVER_NAME "mmci-omap-hs"
112
113/*
114 * One controller can have multiple slots, like on some omap boards using
115 * omap.c controller driver. Luckily this is not currently done on any known
116 * omap_hsmmc.c device.
117 */
118#define mmc_slot(host) (host->pdata->slots[host->slot_id])
119
120/*
121 * MMC Host controller read/write API's
122 */
123#define OMAP_HSMMC_READ(base, reg) \
124 __raw_readl((base) + OMAP_HSMMC_##reg)
125
126#define OMAP_HSMMC_WRITE(base, reg, val) \
127 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
128
129struct mmc_omap_host {
130 struct device *dev;
131 struct mmc_host *mmc;
132 struct mmc_request *mrq;
133 struct mmc_command *cmd;
134 struct mmc_data *data;
135 struct clk *fclk;
136 struct clk *iclk;
137 struct clk *dbclk;
138 struct semaphore sem;
139 struct work_struct mmc_carddetect_work;
140 void __iomem *base;
141 resource_size_t mapbase;
142 unsigned int id;
143 unsigned int dma_len;
0ccd76d4 144 unsigned int dma_sg_idx;
a45c6cb8 145 unsigned char bus_mode;
a3621465 146 unsigned char power_mode;
a45c6cb8
MC		 147 u32 *buffer;
148 u32 bytesleft;
149 int suspended;
150 int irq;
151 int carddetect;
152 int use_dma, dma_ch;
f3e2f1dd 153 int dma_line_tx, dma_line_rx;
a45c6cb8
MC		 154 int slot_id;
155 int dbclk_enabled;
4a694dc9 156 int response_busy;
a45c6cb8
MC		 157 struct omap_mmc_platform_data *pdata;
158};
159
160/*
161 * Stop clock to the card
162 */
163static void omap_mmc_stop_clock(struct mmc_omap_host *host)
164{
165 OMAP_HSMMC_WRITE(host->base, SYSCTL,
166 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
167 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
168 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
169}
170
171/*
172 * Send init stream sequence to card
173 * before sending IDLE command
174 */
175static void send_init_stream(struct mmc_omap_host *host)
176{
177 int reg = 0;
178 unsigned long timeout;
179
180 disable_irq(host->irq);
181 OMAP_HSMMC_WRITE(host->base, CON,
182 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
183 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
184
185 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
186 while ((reg != CC) && time_before(jiffies, timeout))
187 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
188
189 OMAP_HSMMC_WRITE(host->base, CON,
190 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
191 enable_irq(host->irq);
192}
193
194static inline
195int mmc_omap_cover_is_closed(struct mmc_omap_host *host)
196{
197 int r = 1;
198
199 if (host->pdata->slots[host->slot_id].get_cover_state)
200 r = host->pdata->slots[host->slot_id].get_cover_state(host->dev,
201 host->slot_id);
202 return r;
203}
204
205static ssize_t
206mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr,
207 char *buf)
208{
209 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
210 struct mmc_omap_host *host = mmc_priv(mmc);
211
212 return sprintf(buf, "%s\n", mmc_omap_cover_is_closed(host) ? "closed" :
213 "open");
214}
215
216static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL);
217
218static ssize_t
219mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr,
220 char *buf)
221{
222 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
223 struct mmc_omap_host *host = mmc_priv(mmc);
224 struct omap_mmc_slot_data slot = host->pdata->slots[host->slot_id];
225
e68fdabc 226 return sprintf(buf, "%s\n", slot.name);
a45c6cb8
MC		 227}
228
229static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL);
230
231/*
232 * Configure the response type and send the cmd.
233 */
234static void
235mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd,
236 struct mmc_data *data)
237{
238 int cmdreg = 0, resptype = 0, cmdtype = 0;
239
240 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
241 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
242 host->cmd = cmd;
243
244 /*
245 * Clear status bits and enable interrupts
246 */
247 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
248 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
ccdfe3a6
AG		 249
250 if (host->use_dma)
251 OMAP_HSMMC_WRITE(host->base, IE,
252 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
253 else
254 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8 255
4a694dc9 256 host->response_busy = 0;
a45c6cb8
MC		 257 if (cmd->flags & MMC_RSP_PRESENT) {
258 if (cmd->flags & MMC_RSP_136)
259 resptype = 1;
4a694dc9
AH		 260 else if (cmd->flags & MMC_RSP_BUSY) {
261 resptype = 3;
262 host->response_busy = 1;
263 } else
a45c6cb8
MC		 264 resptype = 2;
265 }
266
267 /*
268 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
269 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
270 * a val of 0x3, rest 0x0.
271 */
272 if (cmd == host->mrq->stop)
273 cmdtype = 0x3;
274
275 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
276
277 if (data) {
278 cmdreg |= DP_SELECT | MSBS | BCE;
279 if (data->flags & MMC_DATA_READ)
280 cmdreg |= DDIR;
281 else
282 cmdreg &= ~(DDIR);
283 }
284
285 if (host->use_dma)
286 cmdreg |= DMA_EN;
287
288 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
289 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
290}
291
0ccd76d4
JY		 292static int
293mmc_omap_get_dma_dir(struct mmc_omap_host *host, struct mmc_data *data)
294{
295 if (data->flags & MMC_DATA_WRITE)
296 return DMA_TO_DEVICE;
297 else
298 return DMA_FROM_DEVICE;
299}
300
a45c6cb8
MC		 301/*
302 * Notify the transfer complete to MMC core
303 */
304static void
305mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data)
306{
4a694dc9
AH		 307 if (!data) {
308 struct mmc_request *mrq = host->mrq;
309
310 host->mrq = NULL;
4a694dc9
AH		 311 mmc_request_done(host->mmc, mrq);
312 return;
313 }
314
a45c6cb8
MC		 315 host->data = NULL;
316
317 if (host->use_dma && host->dma_ch != -1)
318 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
0ccd76d4 319 mmc_omap_get_dma_dir(host, data));
a45c6cb8
MC		 320
321 if (!data->error)
322 data->bytes_xfered += data->blocks * (data->blksz);
323 else
324 data->bytes_xfered = 0;
325
326 if (!data->stop) {
327 host->mrq = NULL;
328 mmc_request_done(host->mmc, data->mrq);
329 return;
330 }
331 mmc_omap_start_command(host, data->stop, NULL);
332}
333
334/*
335 * Notify the core about command completion
336 */
337static void
338mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd)
339{
340 host->cmd = NULL;
341
342 if (cmd->flags & MMC_RSP_PRESENT) {
343 if (cmd->flags & MMC_RSP_136) {
344 /* response type 2 */
345 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
346 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
347 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
348 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
349 } else {
350 /* response types 1, 1b, 3, 4, 5, 6 */
351 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
352 }
353 }
4a694dc9 354 if ((host->data == NULL && !host->response_busy) || cmd->error) {
a45c6cb8
MC		 355 host->mrq = NULL;
356 mmc_request_done(host->mmc, cmd->mrq);
357 }
358}
359
360/*
361 * DMA clean up for command errors
362 */
82788ff5 363static void mmc_dma_cleanup(struct mmc_omap_host *host, int errno)
a45c6cb8 364{
82788ff5 365 host->data->error = errno;
a45c6cb8
MC		 366
367 if (host->use_dma && host->dma_ch != -1) {
368 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
0ccd76d4 369 mmc_omap_get_dma_dir(host, host->data));
a45c6cb8
MC		 370 omap_free_dma(host->dma_ch);
371 host->dma_ch = -1;
372 up(&host->sem);
373 }
374 host->data = NULL;
a45c6cb8
MC		 375}
376
377/*
378 * Readable error output
379 */
380#ifdef CONFIG_MMC_DEBUG
381static void mmc_omap_report_irq(struct mmc_omap_host *host, u32 status)
382{
383 /* --- means reserved bit without definition at documentation */
384 static const char *mmc_omap_status_bits[] = {
385 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
386 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
387 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
388 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
389 };
390 char res[256];
391 char *buf = res;
392 int len, i;
393
394 len = sprintf(buf, "MMC IRQ 0x%x :", status);
395 buf += len;
396
397 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++)
398 if (status & (1 << i)) {
399 len = sprintf(buf, " %s", mmc_omap_status_bits[i]);
400 buf += len;
401 }
402
403 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
404}
405#endif /* CONFIG_MMC_DEBUG */
406
3ebf74b1
JP		 407/*
408 * MMC controller internal state machines reset
409 *
410 * Used to reset command or data internal state machines, using respectively
411 * SRC or SRD bit of SYSCTL register
412 * Can be called from interrupt context
413 */
414static inline void mmc_omap_reset_controller_fsm(struct mmc_omap_host *host,
415 unsigned long bit)
416{
417 unsigned long i = 0;
418 unsigned long limit = (loops_per_jiffy *
419 msecs_to_jiffies(MMC_TIMEOUT_MS));
420
421 OMAP_HSMMC_WRITE(host->base, SYSCTL,
422 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
423
424 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
425 (i++ < limit))
426 cpu_relax();
427
428 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
429 dev_err(mmc_dev(host->mmc),
430 "Timeout waiting on controller reset in %s\n",
431 __func__);
432}
a45c6cb8
MC		 433
434/*
435 * MMC controller IRQ handler
436 */
437static irqreturn_t mmc_omap_irq(int irq, void *dev_id)
438{
439 struct mmc_omap_host *host = dev_id;
440 struct mmc_data *data;
441 int end_cmd = 0, end_trans = 0, status;
442
4a694dc9 443 if (host->mrq == NULL) {
a45c6cb8
MC		 444 OMAP_HSMMC_WRITE(host->base, STAT,
445 OMAP_HSMMC_READ(host->base, STAT));
00adadc1
KH		 446 /* Flush posted write */
447 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8
MC		 448 return IRQ_HANDLED;
449 }
450
451 data = host->data;
452 status = OMAP_HSMMC_READ(host->base, STAT);
453 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
454
455 if (status & ERR) {
456#ifdef CONFIG_MMC_DEBUG
457 mmc_omap_report_irq(host, status);
458#endif
459 if ((status & CMD_TIMEOUT) ||
460 (status & CMD_CRC)) {
461 if (host->cmd) {
462 if (status & CMD_TIMEOUT) {
3ebf74b1 463 mmc_omap_reset_controller_fsm(host, SRC);
a45c6cb8
MC		 464 host->cmd->error = -ETIMEDOUT;
465 } else {
466 host->cmd->error = -EILSEQ;
467 }
468 end_cmd = 1;
469 }
4a694dc9
AH		 470 if (host->data || host->response_busy) {
471 if (host->data)
472 mmc_dma_cleanup(host, -ETIMEDOUT);
473 host->response_busy = 0;
3ebf74b1 474 mmc_omap_reset_controller_fsm(host, SRD);
c232f457 475 }
a45c6cb8
MC		 476 }
477 if ((status & DATA_TIMEOUT) ||
478 (status & DATA_CRC)) {
4a694dc9
AH		 479 if (host->data || host->response_busy) {
480 int err = (status & DATA_TIMEOUT) ?
481 -ETIMEDOUT : -EILSEQ;
482
483 if (host->data)
484 mmc_dma_cleanup(host, err);
a45c6cb8 485 else
4a694dc9
AH		 486 host->mrq->cmd->error = err;
487 host->response_busy = 0;
3ebf74b1 488 mmc_omap_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 489 end_trans = 1;
490 }
491 }
492 if (status & CARD_ERR) {
493 dev_dbg(mmc_dev(host->mmc),
494 "Ignoring card err CMD%d\n", host->cmd->opcode);
495 if (host->cmd)
496 end_cmd = 1;
497 if (host->data)
498 end_trans = 1;
499 }
500 }
501
502 OMAP_HSMMC_WRITE(host->base, STAT, status);
00adadc1
KH		 503 /* Flush posted write */
504 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8 505
a8fe29d8 506 if (end_cmd || ((status & CC) && host->cmd))
a45c6cb8
MC		 507 mmc_omap_cmd_done(host, host->cmd);
508 if (end_trans || (status & TC))
509 mmc_omap_xfer_done(host, data);
510
511 return IRQ_HANDLED;
512}
513
e13bb300
AH		 514static void set_sd_bus_power(struct mmc_omap_host *host)
515{
516 unsigned long i;
517
518 OMAP_HSMMC_WRITE(host->base, HCTL,
519 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
520 for (i = 0; i < loops_per_jiffy; i++) {
521 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
522 break;
523 cpu_relax();
524 }
525}
526
a45c6cb8 527/*
eb250826
DB		 528 * Switch MMC interface voltage ... only relevant for MMC1.
529 *
530 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
531 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
532 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8
MC		 533 */
534static int omap_mmc_switch_opcond(struct mmc_omap_host *host, int vdd)
535{
536 u32 reg_val = 0;
537 int ret;
538
539 /* Disable the clocks */
540 clk_disable(host->fclk);
541 clk_disable(host->iclk);
542 clk_disable(host->dbclk);
543
544 /* Turn the power off */
545 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
546 if (ret != 0)
547 goto err;
548
549 /* Turn the power ON with given VDD 1.8 or 3.0v */
550 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, vdd);
551 if (ret != 0)
552 goto err;
553
554 clk_enable(host->fclk);
555 clk_enable(host->iclk);
556 clk_enable(host->dbclk);
557
558 OMAP_HSMMC_WRITE(host->base, HCTL,
559 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
560 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 561
a45c6cb8
MC		 562 /*
563 * If a MMC dual voltage card is detected, the set_ios fn calls
564 * this fn with VDD bit set for 1.8V. Upon card removal from the
565 * slot, omap_mmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
566 *
eb250826
DB		 567 * Cope with a bit of slop in the range ... per data sheets:
568 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
569 * but recommended values are 1.71V to 1.89V
570 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
571 * but recommended values are 2.7V to 3.3V
572 *
573 * Board setup code shouldn't permit anything very out-of-range.
574 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
575 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 576 */
eb250826 577 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 578 reg_val |= SDVS18;
eb250826
DB		 579 else
580 reg_val |= SDVS30;
a45c6cb8
MC		 581
582 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 583 set_sd_bus_power(host);
a45c6cb8
MC		 584
585 return 0;
586err:
587 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
588 return ret;
589}
590
591/*
592 * Work Item to notify the core about card insertion/removal
593 */
594static void mmc_omap_detect(struct work_struct *work)
595{
596 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host,
597 mmc_carddetect_work);
249d0fa9
DB		 598 struct omap_mmc_slot_data *slot = &mmc_slot(host);
599
e1a55f5e
AH		 600 if (mmc_slot(host).card_detect)
601 host->carddetect = slot->card_detect(slot->card_detect_irq);
602 else
603 host->carddetect = -ENOSYS;
a45c6cb8
MC		 604
605 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
606 if (host->carddetect) {
607 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
608 } else {
5e2ea617 609 mmc_host_enable(host->mmc);
3ebf74b1 610 mmc_omap_reset_controller_fsm(host, SRD);
5e2ea617 611 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 612 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
613 }
614}
615
616/*
617 * ISR for handling card insertion and removal
618 */
619static irqreturn_t omap_mmc_cd_handler(int irq, void *dev_id)
620{
621 struct mmc_omap_host *host = (struct mmc_omap_host *)dev_id;
622
a45c6cb8
MC		 623 schedule_work(&host->mmc_carddetect_work);
624
625 return IRQ_HANDLED;
626}
627
0ccd76d4
JY		 628static int mmc_omap_get_dma_sync_dev(struct mmc_omap_host *host,
629 struct mmc_data *data)
630{
631 int sync_dev;
632
f3e2f1dd
GI		 633 if (data->flags & MMC_DATA_WRITE)
634 sync_dev = host->dma_line_tx;
635 else
636 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 637 return sync_dev;
638}
639
640static void mmc_omap_config_dma_params(struct mmc_omap_host *host,
641 struct mmc_data *data,
642 struct scatterlist *sgl)
643{
644 int blksz, nblk, dma_ch;
645
646 dma_ch = host->dma_ch;
647 if (data->flags & MMC_DATA_WRITE) {
648 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
649 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
650 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
651 sg_dma_address(sgl), 0, 0);
652 } else {
653 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
654 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
655 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
656 sg_dma_address(sgl), 0, 0);
657 }
658
659 blksz = host->data->blksz;
660 nblk = sg_dma_len(sgl) / blksz;
661
662 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
663 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
664 mmc_omap_get_dma_sync_dev(host, data),
665 !(data->flags & MMC_DATA_WRITE));
666
667 omap_start_dma(dma_ch);
668}
669
a45c6cb8
MC		 670/*
671 * DMA call back function
672 */
673static void mmc_omap_dma_cb(int lch, u16 ch_status, void *data)
674{
675 struct mmc_omap_host *host = data;
676
677 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
678 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
679
680 if (host->dma_ch < 0)
681 return;
682
0ccd76d4
JY		 683 host->dma_sg_idx++;
684 if (host->dma_sg_idx < host->dma_len) {
685 /* Fire up the next transfer. */
686 mmc_omap_config_dma_params(host, host->data,
687 host->data->sg + host->dma_sg_idx);
688 return;
689 }
690
a45c6cb8
MC		 691 omap_free_dma(host->dma_ch);
692 host->dma_ch = -1;
693 /*
694 * DMA Callback: run in interrupt context.
85b84322 695 * mutex_unlock will throw a kernel warning if used.
a45c6cb8
MC		 696 */
697 up(&host->sem);
698}
699
a45c6cb8
MC		 700/*
701 * Routine to configure and start DMA for the MMC card
702 */
703static int
704mmc_omap_start_dma_transfer(struct mmc_omap_host *host, struct mmc_request *req)
705{
0ccd76d4 706 int dma_ch = 0, ret = 0, err = 1, i;
a45c6cb8
MC		 707 struct mmc_data *data = req->data;
708
0ccd76d4
JY		 709 /* Sanity check: all the SG entries must be aligned by block size. */
710 for (i = 0; i < host->dma_len; i++) {
711 struct scatterlist *sgl;
712
713 sgl = data->sg + i;
714 if (sgl->length % data->blksz)
715 return -EINVAL;
716 }
717 if ((data->blksz % 4) != 0)
718 /* REVISIT: The MMC buffer increments only when MSB is written.
719 * Return error for blksz which is non multiple of four.
720 */
721 return -EINVAL;
722
a45c6cb8
MC		 723 /*
724 * If for some reason the DMA transfer is still active,
725 * we wait for timeout period and free the dma
726 */
727 if (host->dma_ch != -1) {
728 set_current_state(TASK_UNINTERRUPTIBLE);
729 schedule_timeout(100);
730 if (down_trylock(&host->sem)) {
731 omap_free_dma(host->dma_ch);
732 host->dma_ch = -1;
733 up(&host->sem);
734 return err;
735 }
736 } else {
737 if (down_trylock(&host->sem))
738 return err;
739 }
740
0ccd76d4
JY		 741 ret = omap_request_dma(mmc_omap_get_dma_sync_dev(host, data), "MMC/SD",
742 mmc_omap_dma_cb,host, &dma_ch);
a45c6cb8 743 if (ret != 0) {
0ccd76d4 744 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 745 "%s: omap_request_dma() failed with %d\n",
746 mmc_hostname(host->mmc), ret);
747 return ret;
748 }
749
750 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
0ccd76d4 751 data->sg_len, mmc_omap_get_dma_dir(host, data));
a45c6cb8 752 host->dma_ch = dma_ch;
0ccd76d4 753 host->dma_sg_idx = 0;
a45c6cb8 754
0ccd76d4 755 mmc_omap_config_dma_params(host, data, data->sg);
a45c6cb8 756
a45c6cb8
MC		 757 return 0;
758}
759
760static void set_data_timeout(struct mmc_omap_host *host,
761 struct mmc_request *req)
762{
763 unsigned int timeout, cycle_ns;
764 uint32_t reg, clkd, dto = 0;
765
766 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
767 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
768 if (clkd == 0)
769 clkd = 1;
770
771 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
772 timeout = req->data->timeout_ns / cycle_ns;
773 timeout += req->data->timeout_clks;
774 if (timeout) {
775 while ((timeout & 0x80000000) == 0) {
776 dto += 1;
777 timeout <<= 1;
778 }
779 dto = 31 - dto;
780 timeout <<= 1;
781 if (timeout && dto)
782 dto += 1;
783 if (dto >= 13)
784 dto -= 13;
785 else
786 dto = 0;
787 if (dto > 14)
788 dto = 14;
789 }
790
791 reg &= ~DTO_MASK;
792 reg |= dto << DTO_SHIFT;
793 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
794}
795
796/*
797 * Configure block length for MMC/SD cards and initiate the transfer.
798 */
799static int
800mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req)
801{
802 int ret;
803 host->data = req->data;
804
805 if (req->data == NULL) {
a45c6cb8
MC		 806 OMAP_HSMMC_WRITE(host->base, BLK, 0);
807 return 0;
808 }
809
810 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
811 | (req->data->blocks << 16));
812 set_data_timeout(host, req);
813
a45c6cb8
MC		 814 if (host->use_dma) {
815 ret = mmc_omap_start_dma_transfer(host, req);
816 if (ret != 0) {
817 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
818 return ret;
819 }
820 }
821 return 0;
822}
823
5e2ea617
AH		 824static int omap_mmc_enable(struct mmc_host *mmc)
825{
826 struct mmc_omap_host *host = mmc_priv(mmc);
827 int err;
828
829 err = clk_enable(host->fclk);
830 if (err)
831 return err;
832 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
833 return 0;
834}
835
836static int omap_mmc_disable(struct mmc_host *mmc, int lazy)
837{
838 struct mmc_omap_host *host = mmc_priv(mmc);
839
840 clk_disable(host->fclk);
841 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
842 return 0;
843}
844
a45c6cb8
MC		 845/*
846 * Request function. for read/write operation
847 */
848static void omap_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
849{
850 struct mmc_omap_host *host = mmc_priv(mmc);
851
852 WARN_ON(host->mrq != NULL);
853 host->mrq = req;
854 mmc_omap_prepare_data(host, req);
855 mmc_omap_start_command(host, req->cmd, req->data);
856}
857
858
859/* Routine to configure clock values. Exposed API to core */
860static void omap_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
861{
862 struct mmc_omap_host *host = mmc_priv(mmc);
863 u16 dsor = 0;
864 unsigned long regval;
865 unsigned long timeout;
73153010 866 u32 con;
a3621465 867 int do_send_init_stream = 0;
a45c6cb8 868
5e2ea617
AH		 869 mmc_host_enable(host->mmc);
870
a3621465
AH		 871 if (ios->power_mode != host->power_mode) {
872 switch (ios->power_mode) {
873 case MMC_POWER_OFF:
874 mmc_slot(host).set_power(host->dev, host->slot_id,
875 0, 0);
876 break;
877 case MMC_POWER_UP:
878 mmc_slot(host).set_power(host->dev, host->slot_id,
879 1, ios->vdd);
880 break;
881 case MMC_POWER_ON:
882 do_send_init_stream = 1;
883 break;
884 }
885 host->power_mode = ios->power_mode;
a45c6cb8
MC		 886 }
887
73153010 888 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 889 switch (mmc->ios.bus_width) {
73153010
JL		 890 case MMC_BUS_WIDTH_8:
891 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
892 break;
a45c6cb8 893 case MMC_BUS_WIDTH_4:
73153010 894 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 895 OMAP_HSMMC_WRITE(host->base, HCTL,
896 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
897 break;
898 case MMC_BUS_WIDTH_1:
73153010 899 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 900 OMAP_HSMMC_WRITE(host->base, HCTL,
901 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
902 break;
903 }
904
905 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 906 /* Only MMC1 can interface at 3V without some flavor
907 * of external transceiver; but they all handle 1.8V.
908 */
a45c6cb8
MC		 909 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
910 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
911 /*
912 * The mmc_select_voltage fn of the core does
913 * not seem to set the power_mode to
914 * MMC_POWER_UP upon recalculating the voltage.
915 * vdd 1.8v.
916 */
917 if (omap_mmc_switch_opcond(host, ios->vdd) != 0)
918 dev_dbg(mmc_dev(host->mmc),
919 "Switch operation failed\n");
920 }
921 }
922
923 if (ios->clock) {
924 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
925 if (dsor < 1)
926 dsor = 1;
927
928 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
929 dsor++;
930
931 if (dsor > 250)
932 dsor = 250;
933 }
934 omap_mmc_stop_clock(host);
935 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
936 regval = regval & ~(CLKD_MASK);
937 regval = regval | (dsor << 6) | (DTO << 16);
938 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
939 OMAP_HSMMC_WRITE(host->base, SYSCTL,
940 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
941
942 /* Wait till the ICS bit is set */
943 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
944 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != 0x2
945 && time_before(jiffies, timeout))
946 msleep(1);
947
948 OMAP_HSMMC_WRITE(host->base, SYSCTL,
949 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
950
a3621465 951 if (do_send_init_stream)
a45c6cb8
MC		 952 send_init_stream(host);
953
954 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
955 OMAP_HSMMC_WRITE(host->base, CON,
956 OMAP_HSMMC_READ(host->base, CON) | OD);
5e2ea617
AH		 957
958 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 959}
960
961static int omap_hsmmc_get_cd(struct mmc_host *mmc)
962{
963 struct mmc_omap_host *host = mmc_priv(mmc);
964 struct omap_mmc_platform_data *pdata = host->pdata;
965
966 if (!pdata->slots[0].card_detect)
967 return -ENOSYS;
968 return pdata->slots[0].card_detect(pdata->slots[0].card_detect_irq);
969}
970
971static int omap_hsmmc_get_ro(struct mmc_host *mmc)
972{
973 struct mmc_omap_host *host = mmc_priv(mmc);
974 struct omap_mmc_platform_data *pdata = host->pdata;
975
976 if (!pdata->slots[0].get_ro)
977 return -ENOSYS;
978 return pdata->slots[0].get_ro(host->dev, 0);
979}
980
1b331e69
KK		 981static void omap_hsmmc_init(struct mmc_omap_host *host)
982{
983 u32 hctl, capa, value;
984
985 /* Only MMC1 supports 3.0V */
986 if (host->id == OMAP_MMC1_DEVID) {
987 hctl = SDVS30;
988 capa = VS30 | VS18;
989 } else {
990 hctl = SDVS18;
991 capa = VS18;
992 }
993
994 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
995 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
996
997 value = OMAP_HSMMC_READ(host->base, CAPA);
998 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
999
1000 /* Set the controller to AUTO IDLE mode */
1001 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1002 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1003
1004 /* Set SD bus power bit */
e13bb300 1005 set_sd_bus_power(host);
1b331e69
KK		 1006}
1007
a45c6cb8 1008static struct mmc_host_ops mmc_omap_ops = {
5e2ea617
AH		 1009 .enable = omap_mmc_enable,
1010 .disable = omap_mmc_disable,
a45c6cb8
MC		 1011 .request = omap_mmc_request,
1012 .set_ios = omap_mmc_set_ios,
1013 .get_cd = omap_hsmmc_get_cd,
1014 .get_ro = omap_hsmmc_get_ro,
1015 /* NYET -- enable_sdio_irq */
1016};
1017
d900f712
DK		 1018#ifdef CONFIG_DEBUG_FS
1019
1020static int mmc_regs_show(struct seq_file *s, void *data)
1021{
1022 struct mmc_host *mmc = s->private;
1023 struct mmc_omap_host *host = mmc_priv(mmc);
1024
5e2ea617
AH		 1025 seq_printf(s, "mmc%d:\n"
1026 " enabled:\t%d\n"
1027 " nesting_cnt:\t%d\n"
1028 "\nregs:\n",
1029 mmc->index, mmc->enabled ? 1 : 0, mmc->nesting_cnt);
1030
1031 if (clk_enable(host->fclk) != 0) {
1032 seq_printf(s, "can't read the regs\n");
1033 goto err;
1034 }
d900f712
DK		 1035
1036 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1037 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1038 seq_printf(s, "CON:\t\t0x%08x\n",
1039 OMAP_HSMMC_READ(host->base, CON));
1040 seq_printf(s, "HCTL:\t\t0x%08x\n",
1041 OMAP_HSMMC_READ(host->base, HCTL));
1042 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1043 OMAP_HSMMC_READ(host->base, SYSCTL));
1044 seq_printf(s, "IE:\t\t0x%08x\n",
1045 OMAP_HSMMC_READ(host->base, IE));
1046 seq_printf(s, "ISE:\t\t0x%08x\n",
1047 OMAP_HSMMC_READ(host->base, ISE));
1048 seq_printf(s, "CAPA:\t\t0x%08x\n",
1049 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1050
1051 clk_disable(host->fclk);
1052err:
d900f712
DK		 1053 return 0;
1054}
1055
1056static int mmc_regs_open(struct inode *inode, struct file *file)
1057{
1058 return single_open(file, mmc_regs_show, inode->i_private);
1059}
1060
1061static const struct file_operations mmc_regs_fops = {
1062 .open = mmc_regs_open,
1063 .read = seq_read,
1064 .llseek = seq_lseek,
1065 .release = single_release,
1066};
1067
1068static void omap_mmc_debugfs(struct mmc_host *mmc)
1069{
1070 if (mmc->debugfs_root)
1071 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1072 mmc, &mmc_regs_fops);
1073}
1074
1075#else
1076
1077static void omap_mmc_debugfs(struct mmc_host *mmc)
1078{
1079}
1080
1081#endif
1082
a45c6cb8
MC		 1083static int __init omap_mmc_probe(struct platform_device *pdev)
1084{
1085 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1086 struct mmc_host *mmc;
1087 struct mmc_omap_host *host = NULL;
1088 struct resource *res;
1089 int ret = 0, irq;
a45c6cb8
MC		 1090
1091 if (pdata == NULL) {
1092 dev_err(&pdev->dev, "Platform Data is missing\n");
1093 return -ENXIO;
1094 }
1095
1096 if (pdata->nr_slots == 0) {
1097 dev_err(&pdev->dev, "No Slots\n");
1098 return -ENXIO;
1099 }
1100
1101 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1102 irq = platform_get_irq(pdev, 0);
1103 if (res == NULL || irq < 0)
1104 return -ENXIO;
1105
1106 res = request_mem_region(res->start, res->end - res->start + 1,
1107 pdev->name);
1108 if (res == NULL)
1109 return -EBUSY;
1110
1111 mmc = mmc_alloc_host(sizeof(struct mmc_omap_host), &pdev->dev);
1112 if (!mmc) {
1113 ret = -ENOMEM;
1114 goto err;
1115 }
1116
1117 host = mmc_priv(mmc);
1118 host->mmc = mmc;
1119 host->pdata = pdata;
1120 host->dev = &pdev->dev;
1121 host->use_dma = 1;
1122 host->dev->dma_mask = &pdata->dma_mask;
1123 host->dma_ch = -1;
1124 host->irq = irq;
1125 host->id = pdev->id;
1126 host->slot_id = 0;
1127 host->mapbase = res->start;
1128 host->base = ioremap(host->mapbase, SZ_4K);
a3621465 1129 host->power_mode = -1;
a45c6cb8
MC		 1130
1131 platform_set_drvdata(pdev, host);
1132 INIT_WORK(&host->mmc_carddetect_work, mmc_omap_detect);
1133
1134 mmc->ops = &mmc_omap_ops;
1135 mmc->f_min = 400000;
1136 mmc->f_max = 52000000;
1137
1138 sema_init(&host->sem, 1);
1139
6f7607cc 1140 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 1141 if (IS_ERR(host->iclk)) {
1142 ret = PTR_ERR(host->iclk);
1143 host->iclk = NULL;
1144 goto err1;
1145 }
6f7607cc 1146 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1147 if (IS_ERR(host->fclk)) {
1148 ret = PTR_ERR(host->fclk);
1149 host->fclk = NULL;
1150 clk_put(host->iclk);
1151 goto err1;
1152 }
1153
5e2ea617
AH		 1154 mmc->caps |= MMC_CAP_DISABLE;
1155 mmc_set_disable_delay(mmc, 100);
1156 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 1157 clk_put(host->iclk);
1158 clk_put(host->fclk);
1159 goto err1;
1160 }
1161
1162 if (clk_enable(host->iclk) != 0) {
5e2ea617 1163 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1164 clk_put(host->iclk);
1165 clk_put(host->fclk);
1166 goto err1;
1167 }
1168
1169 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1170 /*
1171 * MMC can still work without debounce clock.
1172 */
1173 if (IS_ERR(host->dbclk))
1174 dev_warn(mmc_dev(host->mmc), "Failed to get debounce clock\n");
1175 else
1176 if (clk_enable(host->dbclk) != 0)
1177 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1178 " clk failed\n");
1179 else
1180 host->dbclk_enabled = 1;
1181
0ccd76d4
JY		 1182 /* Since we do only SG emulation, we can have as many segs
1183 * as we want. */
1184 mmc->max_phys_segs = 1024;
1185 mmc->max_hw_segs = 1024;
1186
a45c6cb8
MC		 1187 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1188 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1189 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1190 mmc->max_seg_size = mmc->max_req_size;
1191
a45c6cb8
MC		 1192 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED;
1193
73153010
JL		 1194 if (pdata->slots[host->slot_id].wires >= 8)
1195 mmc->caps |= MMC_CAP_8_BIT_DATA;
1196 else if (pdata->slots[host->slot_id].wires >= 4)
a45c6cb8
MC		 1197 mmc->caps |= MMC_CAP_4_BIT_DATA;
1198
1b331e69 1199 omap_hsmmc_init(host);
a45c6cb8 1200
f3e2f1dd
GI		 1201 /* Select DMA lines */
1202 switch (host->id) {
1203 case OMAP_MMC1_DEVID:
1204 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1205 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1206 break;
1207 case OMAP_MMC2_DEVID:
1208 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1209 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1210 break;
1211 case OMAP_MMC3_DEVID:
1212 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
1213 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
1214 break;
1215 default:
1216 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
1217 goto err_irq;
1218 }
a45c6cb8
MC		 1219
1220 /* Request IRQ for MMC operations */
1221 ret = request_irq(host->irq, mmc_omap_irq, IRQF_DISABLED,
1222 mmc_hostname(mmc), host);
1223 if (ret) {
1224 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1225 goto err_irq;
1226 }
1227
b583f26d 1228 /* initialize power supplies, gpios, etc */
a45c6cb8
MC		 1229 if (pdata->init != NULL) {
1230 if (pdata->init(&pdev->dev) != 0) {
b583f26d 1231 dev_dbg(mmc_dev(host->mmc), "late init error\n");
a45c6cb8
MC		 1232 goto err_irq_cd_init;
1233 }
1234 }
b583f26d 1235 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1236
1237 /* Request IRQ for card detect */
e1a55f5e 1238 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8
MC		 1239 ret = request_irq(mmc_slot(host).card_detect_irq,
1240 omap_mmc_cd_handler,
1241 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
1242 | IRQF_DISABLED,
1243 mmc_hostname(mmc), host);
1244 if (ret) {
1245 dev_dbg(mmc_dev(host->mmc),
1246 "Unable to grab MMC CD IRQ\n");
1247 goto err_irq_cd;
1248 }
1249 }
1250
1251 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
1252 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
1253
5e2ea617
AH		 1254 mmc_host_lazy_disable(host->mmc);
1255
a45c6cb8
MC		 1256 mmc_add_host(mmc);
1257
1258 if (host->pdata->slots[host->slot_id].name != NULL) {
1259 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
1260 if (ret < 0)
1261 goto err_slot_name;
1262 }
e1a55f5e
AH		 1263 if (mmc_slot(host).card_detect_irq &&
1264 host->pdata->slots[host->slot_id].get_cover_state) {
a45c6cb8
MC		 1265 ret = device_create_file(&mmc->class_dev,
1266 &dev_attr_cover_switch);
1267 if (ret < 0)
1268 goto err_cover_switch;
1269 }
1270
d900f712
DK		 1271 omap_mmc_debugfs(mmc);
1272
a45c6cb8
MC		 1273 return 0;
1274
1275err_cover_switch:
1276 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch);
1277err_slot_name:
1278 mmc_remove_host(mmc);
1279err_irq_cd:
1280 free_irq(mmc_slot(host).card_detect_irq, host);
1281err_irq_cd_init:
1282 free_irq(host->irq, host);
1283err_irq:
5e2ea617 1284 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1285 clk_disable(host->iclk);
1286 clk_put(host->fclk);
1287 clk_put(host->iclk);
1288 if (host->dbclk_enabled) {
1289 clk_disable(host->dbclk);
1290 clk_put(host->dbclk);
1291 }
1292
1293err1:
1294 iounmap(host->base);
1295err:
1296 dev_dbg(mmc_dev(host->mmc), "Probe Failed\n");
1297 release_mem_region(res->start, res->end - res->start + 1);
1298 if (host)
1299 mmc_free_host(mmc);
1300 return ret;
1301}
1302
1303static int omap_mmc_remove(struct platform_device *pdev)
1304{
1305 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1306 struct resource *res;
1307
1308 if (host) {
5e2ea617 1309 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1310 mmc_remove_host(host->mmc);
1311 if (host->pdata->cleanup)
1312 host->pdata->cleanup(&pdev->dev);
1313 free_irq(host->irq, host);
1314 if (mmc_slot(host).card_detect_irq)
1315 free_irq(mmc_slot(host).card_detect_irq, host);
1316 flush_scheduled_work();
1317
5e2ea617 1318 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1319 clk_disable(host->iclk);
1320 clk_put(host->fclk);
1321 clk_put(host->iclk);
1322 if (host->dbclk_enabled) {
1323 clk_disable(host->dbclk);
1324 clk_put(host->dbclk);
1325 }
1326
1327 mmc_free_host(host->mmc);
1328 iounmap(host->base);
1329 }
1330
1331 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1332 if (res)
1333 release_mem_region(res->start, res->end - res->start + 1);
1334 platform_set_drvdata(pdev, NULL);
1335
1336 return 0;
1337}
1338
1339#ifdef CONFIG_PM
1340static int omap_mmc_suspend(struct platform_device *pdev, pm_message_t state)
1341{
1342 int ret = 0;
1343 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1344
1345 if (host && host->suspended)
1346 return 0;
1347
1348 if (host) {
5e2ea617 1349 mmc_host_enable(host->mmc);
a45c6cb8
MC		 1350 ret = mmc_suspend_host(host->mmc, state);
1351 if (ret == 0) {
1352 host->suspended = 1;
1353
1354 OMAP_HSMMC_WRITE(host->base, ISE, 0);
1355 OMAP_HSMMC_WRITE(host->base, IE, 0);
1356
1357 if (host->pdata->suspend) {
1358 ret = host->pdata->suspend(&pdev->dev,
1359 host->slot_id);
1360 if (ret)
1361 dev_dbg(mmc_dev(host->mmc),
1362 "Unable to handle MMC board"
1363 " level suspend\n");
1364 }
1365
0683af48
JL		 1366 OMAP_HSMMC_WRITE(host->base, HCTL,
1367 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 1368 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1369 clk_disable(host->iclk);
1370 clk_disable(host->dbclk);
5e2ea617
AH		 1371 } else
1372 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1373
1374 }
1375 return ret;
1376}
1377
1378/* Routine to resume the MMC device */
1379static int omap_mmc_resume(struct platform_device *pdev)
1380{
1381 int ret = 0;
1382 struct mmc_omap_host *host = platform_get_drvdata(pdev);
1383
1384 if (host && !host->suspended)
1385 return 0;
1386
1387 if (host) {
1388
5e2ea617 1389 if (mmc_host_enable(host->mmc) != 0)
a45c6cb8
MC		 1390 goto clk_en_err;
1391
1392 ret = clk_enable(host->iclk);
1393 if (ret) {
5e2ea617 1394 mmc_host_disable(host->mmc);
a45c6cb8
MC		 1395 clk_put(host->fclk);
1396 goto clk_en_err;
1397 }
1398
1399 if (clk_enable(host->dbclk) != 0)
1400 dev_dbg(mmc_dev(host->mmc),
1401 "Enabling debounce clk failed\n");
1402
1b331e69
KK		 1403 omap_hsmmc_init(host);
1404
a45c6cb8
MC		 1405 if (host->pdata->resume) {
1406 ret = host->pdata->resume(&pdev->dev, host->slot_id);
1407 if (ret)
1408 dev_dbg(mmc_dev(host->mmc),
1409 "Unmask interrupt failed\n");
1410 }
1411
1412 /* Notify the core to resume the host */
1413 ret = mmc_resume_host(host->mmc);
1414 if (ret == 0)
1415 host->suspended = 0;
5e2ea617 1416 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1417 }
1418
1419 return ret;
1420
1421clk_en_err:
1422 dev_dbg(mmc_dev(host->mmc),
1423 "Failed to enable MMC clocks during resume\n");
1424 return ret;
1425}
1426
1427#else
1428#define omap_mmc_suspend NULL
1429#define omap_mmc_resume NULL
1430#endif
1431
1432static struct platform_driver omap_mmc_driver = {
a45c6cb8
MC		 1433 .remove = omap_mmc_remove,
1434 .suspend = omap_mmc_suspend,
1435 .resume = omap_mmc_resume,
1436 .driver = {
1437 .name = DRIVER_NAME,
1438 .owner = THIS_MODULE,
1439 },
1440};
1441
1442static int __init omap_mmc_init(void)
1443{
1444 /* Register the MMC driver */
f400cd8c 1445 return platform_driver_probe(&omap_mmc_driver, omap_mmc_probe);
a45c6cb8
MC		 1446}
1447
1448static void __exit omap_mmc_cleanup(void)
1449{
1450 /* Unregister MMC driver */
1451 platform_driver_unregister(&omap_mmc_driver);
1452}
1453
1454module_init(omap_mmc_init);
1455module_exit(omap_mmc_cleanup);
1456
1457MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
1458MODULE_LICENSE("GPL");
1459MODULE_ALIAS("platform:" DRIVER_NAME);
1460MODULE_AUTHOR("Texas Instruments Inc");
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