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[mirror_ubuntu-zesty-kernel.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712 21#include <linux/debugfs.h>
c5c98927 22#include <linux/dmaengine.h>
d900f712 23#include <linux/seq_file.h>
031cd037 24#include <linux/sizes.h>
a45c6cb8
MC		 25#include <linux/interrupt.h>
26#include <linux/delay.h>
27#include <linux/dma-mapping.h>
28#include <linux/platform_device.h>
a45c6cb8
MC		 29#include <linux/timer.h>
30#include <linux/clk.h>
46856a68 31#include <linux/of.h>
2cd3a2a5 32#include <linux/of_irq.h>
46856a68
RN		 33#include <linux/of_gpio.h>
34#include <linux/of_device.h>
ee526d51 35#include <linux/omap-dmaengine.h>
a45c6cb8 36#include <linux/mmc/host.h>
13189e78 37#include <linux/mmc/core.h>
93caf8e6 38#include <linux/mmc/mmc.h>
41afa314 39#include <linux/mmc/slot-gpio.h>
a45c6cb8 40#include <linux/io.h>
2cd3a2a5 41#include <linux/irq.h>
db0fefc5
AH		 42#include <linux/gpio.h>
43#include <linux/regulator/consumer.h>
46b76035 44#include <linux/pinctrl/consumer.h>
fa4aa2d4 45#include <linux/pm_runtime.h>
5b83b223 46#include <linux/pm_wakeirq.h>
55143438 47#include <linux/platform_data/hsmmc-omap.h>
a45c6cb8
MC		 48
49/* OMAP HSMMC Host Controller Registers */
11dd62a7 50#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8 51#define OMAP_HSMMC_CON 0x002C
a2e77152 52#define OMAP_HSMMC_SDMASA 0x0100
a45c6cb8
MC		 53#define OMAP_HSMMC_BLK 0x0104
54#define OMAP_HSMMC_ARG 0x0108
55#define OMAP_HSMMC_CMD 0x010C
56#define OMAP_HSMMC_RSP10 0x0110
57#define OMAP_HSMMC_RSP32 0x0114
58#define OMAP_HSMMC_RSP54 0x0118
59#define OMAP_HSMMC_RSP76 0x011C
60#define OMAP_HSMMC_DATA 0x0120
bb0635f0 61#define OMAP_HSMMC_PSTATE 0x0124
a45c6cb8
MC		 62#define OMAP_HSMMC_HCTL 0x0128
63#define OMAP_HSMMC_SYSCTL 0x012C
64#define OMAP_HSMMC_STAT 0x0130
65#define OMAP_HSMMC_IE 0x0134
66#define OMAP_HSMMC_ISE 0x0138
a2e77152 67#define OMAP_HSMMC_AC12 0x013C
a45c6cb8
MC		 68#define OMAP_HSMMC_CAPA 0x0140
69
70#define VS18 (1 << 26)
71#define VS30 (1 << 25)
cd587096 72#define HSS (1 << 21)
a45c6cb8
MC		 73#define SDVS18 (0x5 << 9)
74#define SDVS30 (0x6 << 9)
eb250826 75#define SDVS33 (0x7 << 9)
1b331e69 76#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 77#define SDVSCLR 0xFFFFF1FF
78#define SDVSDET 0x00000400
79#define AUTOIDLE 0x1
80#define SDBP (1 << 8)
81#define DTO 0xe
82#define ICE 0x1
83#define ICS 0x2
84#define CEN (1 << 2)
ed164182 85#define CLKD_MAX 0x3FF /* max clock divisor: 1023 */
a45c6cb8
MC		 86#define CLKD_MASK 0x0000FFC0
87#define CLKD_SHIFT 6
88#define DTO_MASK 0x000F0000
89#define DTO_SHIFT 16
a45c6cb8 90#define INIT_STREAM (1 << 1)
a2e77152 91#define ACEN_ACMD23 (2 << 2)
a45c6cb8
MC		 92#define DP_SELECT (1 << 21)
93#define DDIR (1 << 4)
a7e96879 94#define DMAE 0x1
a45c6cb8
MC		 95#define MSBS (1 << 5)
96#define BCE (1 << 1)
97#define FOUR_BIT (1 << 1)
cd587096 98#define HSPE (1 << 2)
5a52b08b 99#define IWE (1 << 24)
03b5d924 100#define DDR (1 << 19)
5a52b08b
B		 101#define CLKEXTFREE (1 << 16)
102#define CTPL (1 << 11)
73153010 103#define DW8 (1 << 5)
a45c6cb8 104#define OD 0x1
a45c6cb8
MC		 105#define STAT_CLEAR 0xFFFFFFFF
106#define INIT_STREAM_CMD 0x00000000
107#define DUAL_VOLT_OCR_BIT 7
108#define SRC (1 << 25)
109#define SRD (1 << 26)
11dd62a7 110#define SOFTRESET (1 << 1)
a45c6cb8 111
f945901f
AF		 112/* PSTATE */
113#define DLEV_DAT(x) (1 << (20 + (x)))
114
a7e96879
V		 115/* Interrupt masks for IE and ISE register */
116#define CC_EN (1 << 0)
117#define TC_EN (1 << 1)
118#define BWR_EN (1 << 4)
119#define BRR_EN (1 << 5)
2cd3a2a5 120#define CIRQ_EN (1 << 8)
a7e96879
V		 121#define ERR_EN (1 << 15)
122#define CTO_EN (1 << 16)
123#define CCRC_EN (1 << 17)
124#define CEB_EN (1 << 18)
125#define CIE_EN (1 << 19)
126#define DTO_EN (1 << 20)
127#define DCRC_EN (1 << 21)
128#define DEB_EN (1 << 22)
a2e77152 129#define ACE_EN (1 << 24)
a7e96879
V		 130#define CERR_EN (1 << 28)
131#define BADA_EN (1 << 29)
132
a2e77152 133#define INT_EN_MASK (BADA_EN | CERR_EN | ACE_EN | DEB_EN | DCRC_EN |\
a7e96879
V		 134 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \
135 BRR_EN | BWR_EN | TC_EN | CC_EN)
136
a2e77152
B		 137#define CNI (1 << 7)
138#define ACIE (1 << 4)
139#define ACEB (1 << 3)
140#define ACCE (1 << 2)
141#define ACTO (1 << 1)
142#define ACNE (1 << 0)
143
fa4aa2d4 144#define MMC_AUTOSUSPEND_DELAY 100
1e881786
JM		 145#define MMC_TIMEOUT_MS 20 /* 20 mSec */
146#define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */
6b206efe
AS		 147#define OMAP_MMC_MIN_CLOCK 400000
148#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 149#define DRIVER_NAME "omap_hsmmc"
a45c6cb8 150
e99448ff
B		 151#define VDD_1V8 1800000 /* 180000 uV */
152#define VDD_3V0 3000000 /* 300000 uV */
153#define VDD_165_195 (ffs(MMC_VDD_165_195) - 1)
154
a45c6cb8
MC		 155/*
156 * One controller can have multiple slots, like on some omap boards using
157 * omap.c controller driver. Luckily this is not currently done on any known
158 * omap_hsmmc.c device.
159 */
326119c9 160#define mmc_pdata(host) host->pdata
a45c6cb8
MC		 161
162/*
163 * MMC Host controller read/write API's
164 */
165#define OMAP_HSMMC_READ(base, reg) \
166 __raw_readl((base) + OMAP_HSMMC_##reg)
167
168#define OMAP_HSMMC_WRITE(base, reg, val) \
169 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
170
9782aff8
PF		 171struct omap_hsmmc_next {
172 unsigned int dma_len;
173 s32 cookie;
174};
175
70a3341a 176struct omap_hsmmc_host {
a45c6cb8
MC		 177 struct device *dev;
178 struct mmc_host *mmc;
179 struct mmc_request *mrq;
180 struct mmc_command *cmd;
181 struct mmc_data *data;
182 struct clk *fclk;
a45c6cb8 183 struct clk *dbclk;
e99448ff 184 struct regulator *pbias;
bb2726b5 185 bool pbias_enabled;
a45c6cb8 186 void __iomem *base;
3f77f702 187 int vqmmc_enabled;
a45c6cb8 188 resource_size_t mapbase;
4dffd7a2 189 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 190 unsigned int dma_len;
0ccd76d4 191 unsigned int dma_sg_idx;
a45c6cb8 192 unsigned char bus_mode;
a3621465 193 unsigned char power_mode;
a45c6cb8 194 int suspended;
0a82e06e
TL		 195 u32 con;
196 u32 hctl;
197 u32 sysctl;
198 u32 capa;
a45c6cb8 199 int irq;
2cd3a2a5 200 int wake_irq;
a45c6cb8 201 int use_dma, dma_ch;
c5c98927
RK		 202 struct dma_chan *tx_chan;
203 struct dma_chan *rx_chan;
4a694dc9 204 int response_busy;
11dd62a7 205 int context_loss;
b62f6228
AH		 206 int protect_card;
207 int reqs_blocked;
b417577d 208 int req_in_progress;
6e3076c2 209 unsigned long clk_rate;
a2e77152 210 unsigned int flags;
2cd3a2a5
AF		 211#define AUTO_CMD23 (1 << 0) /* Auto CMD23 support */
212#define HSMMC_SDIO_IRQ_ENABLED (1 << 1) /* SDIO irq enabled */
9782aff8 213 struct omap_hsmmc_next next_data;
55143438 214 struct omap_hsmmc_platform_data *pdata;
b5cd43f0 215
b5cd43f0
AF		 216 /* return MMC cover switch state, can be NULL if not supported.
217 *
218 * possible return values:
219 * 0 - closed
220 * 1 - open
221 */
80412ca8 222 int (*get_cover_state)(struct device *dev);
b5cd43f0 223
80412ca8 224 int (*card_detect)(struct device *dev);
a45c6cb8
MC		 225};
226
59445b10
NM		 227struct omap_mmc_of_data {
228 u32 reg_offset;
229 u8 controller_flags;
230};
231
bf129e1c
B		 232static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host);
233
80412ca8 234static int omap_hsmmc_card_detect(struct device *dev)
db0fefc5 235{
9ea28ecb 236 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
db0fefc5 237
41afa314 238 return mmc_gpio_get_cd(host->mmc);
db0fefc5
AH		 239}
240
80412ca8 241static int omap_hsmmc_get_cover_state(struct device *dev)
db0fefc5 242{
9ea28ecb 243 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
db0fefc5 244
41afa314 245 return mmc_gpio_get_cd(host->mmc);
db0fefc5
AH		 246}
247
1d17f30b 248static int omap_hsmmc_enable_supply(struct mmc_host *mmc)
2a17f844
KVA		 249{
250 int ret;
3f77f702 251 struct omap_hsmmc_host *host = mmc_priv(mmc);
1d17f30b 252 struct mmc_ios *ios = &mmc->ios;
2a17f844
KVA		 253
254 if (mmc->supply.vmmc) {
1d17f30b 255 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
2a17f844
KVA		 256 if (ret)
257 return ret;
258 }
259
260 /* Enable interface voltage rail, if needed */
3f77f702 261 if (mmc->supply.vqmmc && !host->vqmmc_enabled) {
2a17f844
KVA		 262 ret = regulator_enable(mmc->supply.vqmmc);
263 if (ret) {
264 dev_err(mmc_dev(mmc), "vmmc_aux reg enable failed\n");
265 goto err_vqmmc;
266 }
3f77f702 267 host->vqmmc_enabled = 1;
2a17f844
KVA		 268 }
269
270 return 0;
271
272err_vqmmc:
273 if (mmc->supply.vmmc)
274 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
275
276 return ret;
277}
278
279static int omap_hsmmc_disable_supply(struct mmc_host *mmc)
280{
281 int ret;
282 int status;
3f77f702 283 struct omap_hsmmc_host *host = mmc_priv(mmc);
2a17f844 284
3f77f702 285 if (mmc->supply.vqmmc && host->vqmmc_enabled) {
2a17f844
KVA		 286 ret = regulator_disable(mmc->supply.vqmmc);
287 if (ret) {
288 dev_err(mmc_dev(mmc), "vmmc_aux reg disable failed\n");
289 return ret;
290 }
3f77f702 291 host->vqmmc_enabled = 0;
2a17f844
KVA		 292 }
293
294 if (mmc->supply.vmmc) {
295 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
296 if (ret)
297 goto err_set_ocr;
298 }
299
300 return 0;
301
302err_set_ocr:
303 if (mmc->supply.vqmmc) {
304 status = regulator_enable(mmc->supply.vqmmc);
305 if (status)
306 dev_err(mmc_dev(mmc), "vmmc_aux re-enable failed\n");
307 }
308
309 return ret;
310}
311
ec85c95e
KVA		 312static int omap_hsmmc_set_pbias(struct omap_hsmmc_host *host, bool power_on,
313 int vdd)
314{
315 int ret;
316
317 if (!host->pbias)
318 return 0;
319
320 if (power_on) {
321 if (vdd <= VDD_165_195)
322 ret = regulator_set_voltage(host->pbias, VDD_1V8,
323 VDD_1V8);
324 else
325 ret = regulator_set_voltage(host->pbias, VDD_3V0,
326 VDD_3V0);
327 if (ret < 0) {
328 dev_err(host->dev, "pbias set voltage fail\n");
329 return ret;
330 }
331
bb2726b5 332 if (host->pbias_enabled == 0) {
ec85c95e
KVA		 333 ret = regulator_enable(host->pbias);
334 if (ret) {
335 dev_err(host->dev, "pbias reg enable fail\n");
336 return ret;
337 }
bb2726b5 338 host->pbias_enabled = 1;
ec85c95e
KVA		 339 }
340 } else {
bb2726b5 341 if (host->pbias_enabled == 1) {
ec85c95e
KVA		 342 ret = regulator_disable(host->pbias);
343 if (ret) {
344 dev_err(host->dev, "pbias reg disable fail\n");
345 return ret;
346 }
bb2726b5 347 host->pbias_enabled = 0;
ec85c95e
KVA		 348 }
349 }
350
351 return 0;
352}
353
80412ca8 354static int omap_hsmmc_set_power(struct device *dev, int power_on, int vdd)
db0fefc5
AH		 355{
356 struct omap_hsmmc_host *host =
357 platform_get_drvdata(to_platform_device(dev));
aa9a6801 358 struct mmc_host *mmc = host->mmc;
db0fefc5
AH		 359 int ret = 0;
360
f7f0f035
AF		 361 if (mmc_pdata(host)->set_power)
362 return mmc_pdata(host)->set_power(dev, power_on, vdd);
363
db0fefc5
AH		 364 /*
365 * If we don't see a Vcc regulator, assume it's a fixed
366 * voltage always-on regulator.
367 */
aa9a6801 368 if (!mmc->supply.vmmc)
db0fefc5
AH		 369 return 0;
370
326119c9 371 if (mmc_pdata(host)->before_set_reg)
80412ca8 372 mmc_pdata(host)->before_set_reg(dev, power_on, vdd);
db0fefc5 373
ec85c95e
KVA		 374 ret = omap_hsmmc_set_pbias(host, false, 0);
375 if (ret)
376 return ret;
e99448ff 377
db0fefc5
AH		 378 /*
379 * Assume Vcc regulator is used only to power the card ... OMAP
380 * VDDS is used to power the pins, optionally with a transceiver to
381 * support cards using voltages other than VDDS (1.8V nominal). When a
382 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
383 *
384 * In some cases this regulator won't support enable/disable;
385 * e.g. it's a fixed rail for a WLAN chip.
386 *
387 * In other cases vcc_aux switches interface power. Example, for
388 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
389 * chips/cards need an interface voltage rail too.
390 */
391 if (power_on) {
1d17f30b 392 ret = omap_hsmmc_enable_supply(mmc);
2a17f844
KVA		 393 if (ret)
394 return ret;
97fe7e5a
KVA		 395
396 ret = omap_hsmmc_set_pbias(host, true, vdd);
397 if (ret)
398 goto err_set_voltage;
db0fefc5 399 } else {
2a17f844
KVA		 400 ret = omap_hsmmc_disable_supply(mmc);
401 if (ret)
402 return ret;
db0fefc5
AH		 403 }
404
326119c9 405 if (mmc_pdata(host)->after_set_reg)
80412ca8 406 mmc_pdata(host)->after_set_reg(dev, power_on, vdd);
db0fefc5 407
229f3292
KVA		 408 return 0;
409
410err_set_voltage:
2a17f844 411 omap_hsmmc_disable_supply(mmc);
229f3292 412
db0fefc5
AH		 413 return ret;
414}
415
c8518efa
KVA		 416static int omap_hsmmc_disable_boot_regulator(struct regulator *reg)
417{
418 int ret;
419
420 if (!reg)
421 return 0;
422
423 if (regulator_is_enabled(reg)) {
424 ret = regulator_enable(reg);
425 if (ret)
426 return ret;
427
428 ret = regulator_disable(reg);
429 if (ret)
430 return ret;
431 }
432
433 return 0;
434}
435
436static int omap_hsmmc_disable_boot_regulators(struct omap_hsmmc_host *host)
437{
438 struct mmc_host *mmc = host->mmc;
439 int ret;
440
441 /*
442 * disable regulators enabled during boot and get the usecount
443 * right so that regulators can be enabled/disabled by checking
444 * the return value of regulator_is_enabled
445 */
446 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vmmc);
447 if (ret) {
448 dev_err(host->dev, "fail to disable boot enabled vmmc reg\n");
449 return ret;
450 }
451
452 ret = omap_hsmmc_disable_boot_regulator(mmc->supply.vqmmc);
453 if (ret) {
454 dev_err(host->dev,
455 "fail to disable boot enabled vmmc_aux reg\n");
456 return ret;
457 }
458
459 ret = omap_hsmmc_disable_boot_regulator(host->pbias);
460 if (ret) {
461 dev_err(host->dev,
462 "failed to disable boot enabled pbias reg\n");
463 return ret;
464 }
465
466 return 0;
467}
468
db0fefc5
AH		 469static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
470{
64be9782 471 int ocr_value = 0;
7d607f91 472 int ret;
aa9a6801 473 struct mmc_host *mmc = host->mmc;
db0fefc5 474
f7f0f035
AF		 475 if (mmc_pdata(host)->set_power)
476 return 0;
477
aa9a6801
KVA		 478 mmc->supply.vmmc = devm_regulator_get_optional(host->dev, "vmmc");
479 if (IS_ERR(mmc->supply.vmmc)) {
480 ret = PTR_ERR(mmc->supply.vmmc);
123e20b1 481 if ((ret != -ENODEV) && host->dev->of_node)
7d607f91 482 return ret;
7d607f91 483 dev_dbg(host->dev, "unable to get vmmc regulator %ld\n",
aa9a6801
KVA		 484 PTR_ERR(mmc->supply.vmmc));
485 mmc->supply.vmmc = NULL;
db0fefc5 486 } else {
aa9a6801 487 ocr_value = mmc_regulator_get_ocrmask(mmc->supply.vmmc);
b49069fc 488 if (ocr_value > 0)
326119c9 489 mmc_pdata(host)->ocr_mask = ocr_value;
987fd49b 490 }
db0fefc5 491
987fd49b 492 /* Allow an aux regulator */
aa9a6801
KVA		 493 mmc->supply.vqmmc = devm_regulator_get_optional(host->dev, "vmmc_aux");
494 if (IS_ERR(mmc->supply.vqmmc)) {
495 ret = PTR_ERR(mmc->supply.vqmmc);
123e20b1 496 if ((ret != -ENODEV) && host->dev->of_node)
6a9b2ff0 497 return ret;
6a9b2ff0 498 dev_dbg(host->dev, "unable to get vmmc_aux regulator %ld\n",
aa9a6801
KVA		 499 PTR_ERR(mmc->supply.vqmmc));
500 mmc->supply.vqmmc = NULL;
6a9b2ff0 501 }
987fd49b 502
c299dc39
KVA		 503 host->pbias = devm_regulator_get_optional(host->dev, "pbias");
504 if (IS_ERR(host->pbias)) {
505 ret = PTR_ERR(host->pbias);
123e20b1 506 if ((ret != -ENODEV) && host->dev->of_node)
6a9b2ff0 507 return ret;
6a9b2ff0 508 dev_dbg(host->dev, "unable to get pbias regulator %ld\n",
c299dc39
KVA		 509 PTR_ERR(host->pbias));
510 host->pbias = NULL;
6a9b2ff0 511 }
e99448ff 512
987fd49b 513 /* For eMMC do not power off when not in sleep state */
326119c9 514 if (mmc_pdata(host)->no_regulator_off_init)
987fd49b 515 return 0;
987fd49b 516
c8518efa
KVA		 517 ret = omap_hsmmc_disable_boot_regulators(host);
518 if (ret)
519 return ret;
db0fefc5
AH		 520
521 return 0;
db0fefc5
AH		 522}
523
cde592cb 524static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id);
41afa314
N		 525
526static int omap_hsmmc_gpio_init(struct mmc_host *mmc,
527 struct omap_hsmmc_host *host,
1e363e3b 528 struct omap_hsmmc_platform_data *pdata)
b702b106
AH		 529{
530 int ret;
531
b7a5646f
AF		 532 if (gpio_is_valid(pdata->gpio_cod)) {
533 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cod, 0);
b702b106
AH		 534 if (ret)
535 return ret;
cde592cb
AF		 536
537 host->get_cover_state = omap_hsmmc_get_cover_state;
538 mmc_gpio_set_cd_isr(mmc, omap_hsmmc_cover_irq);
b7a5646f
AF		 539 } else if (gpio_is_valid(pdata->gpio_cd)) {
540 ret = mmc_gpio_request_cd(mmc, pdata->gpio_cd, 0);
cde592cb
AF		 541 if (ret)
542 return ret;
543
544 host->card_detect = omap_hsmmc_card_detect;
326119c9 545 }
b702b106 546
326119c9 547 if (gpio_is_valid(pdata->gpio_wp)) {
41afa314 548 ret = mmc_gpio_request_ro(mmc, pdata->gpio_wp);
b702b106 549 if (ret)
41afa314 550 return ret;
326119c9 551 }
b702b106
AH		 552
553 return 0;
b702b106
AH		 554}
555
e0c7f99b
AS		 556/*
557 * Start clock to the card
558 */
559static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
560{
561 OMAP_HSMMC_WRITE(host->base, SYSCTL,
562 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
563}
564
a45c6cb8
MC		 565/*
566 * Stop clock to the card
567 */
70a3341a 568static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 569{
570 OMAP_HSMMC_WRITE(host->base, SYSCTL,
571 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
572 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
7122bbb0 573 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n");
a45c6cb8
MC		 574}
575
93caf8e6
AH		 576static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
577 struct mmc_command *cmd)
b417577d 578{
2cd3a2a5
AF		 579 u32 irq_mask = INT_EN_MASK;
580 unsigned long flags;
b417577d
AH		 581
582 if (host->use_dma)
2cd3a2a5 583 irq_mask &= ~(BRR_EN | BWR_EN);
b417577d 584
93caf8e6
AH		 585 /* Disable timeout for erases */
586 if (cmd->opcode == MMC_ERASE)
a7e96879 587 irq_mask &= ~DTO_EN;
93caf8e6 588
2cd3a2a5 589 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 590 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
591 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
2cd3a2a5
AF		 592
593 /* latch pending CIRQ, but don't signal MMC core */
594 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
595 irq_mask |= CIRQ_EN;
b417577d 596 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
2cd3a2a5 597 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 598}
599
600static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
601{
2cd3a2a5
AF		 602 u32 irq_mask = 0;
603 unsigned long flags;
604
605 spin_lock_irqsave(&host->irq_lock, flags);
606 /* no transfer running but need to keep cirq if enabled */
607 if (host->flags & HSMMC_SDIO_IRQ_ENABLED)
608 irq_mask |= CIRQ_EN;
609 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
610 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
b417577d 611 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2cd3a2a5 612 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 613}
614
ac330f44 615/* Calculate divisor for the given clock frequency */
d83b6e03 616static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 617{
618 u16 dsor = 0;
619
620 if (ios->clock) {
d83b6e03 621 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ed164182
B		 622 if (dsor > CLKD_MAX)
623 dsor = CLKD_MAX;
ac330f44
AS		 624 }
625
626 return dsor;
627}
628
5934df2f
AS		 629static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
630{
631 struct mmc_ios *ios = &host->mmc->ios;
632 unsigned long regval;
633 unsigned long timeout;
cd587096 634 unsigned long clkdiv;
5934df2f 635
8986d31b 636 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
5934df2f
AS		 637
638 omap_hsmmc_stop_clock(host);
639
640 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
641 regval = regval & ~(CLKD_MASK | DTO_MASK);
cd587096
HG		 642 clkdiv = calc_divisor(host, ios);
643 regval = regval | (clkdiv << 6) | (DTO << 16);
5934df2f
AS		 644 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
645 OMAP_HSMMC_WRITE(host->base, SYSCTL,
646 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
647
648 /* Wait till the ICS bit is set */
649 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
650 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
651 && time_before(jiffies, timeout))
652 cpu_relax();
653
cd587096
HG		 654 /*
655 * Enable High-Speed Support
656 * Pre-Requisites
657 * - Controller should support High-Speed-Enable Bit
658 * - Controller should not be using DDR Mode
659 * - Controller should advertise that it supports High Speed
660 * in capabilities register
661 * - MMC/SD clock coming out of controller > 25MHz
662 */
326119c9 663 if ((mmc_pdata(host)->features & HSMMC_HAS_HSPE_SUPPORT) &&
5438ad95 664 (ios->timing != MMC_TIMING_MMC_DDR52) &&
903101a8 665 (ios->timing != MMC_TIMING_UHS_DDR50) &&
cd587096
HG		 666 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) {
667 regval = OMAP_HSMMC_READ(host->base, HCTL);
668 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000)
669 regval |= HSPE;
670 else
671 regval &= ~HSPE;
672
673 OMAP_HSMMC_WRITE(host->base, HCTL, regval);
674 }
675
5934df2f
AS		 676 omap_hsmmc_start_clock(host);
677}
678
3796fb8a
AS		 679static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
680{
681 struct mmc_ios *ios = &host->mmc->ios;
682 u32 con;
683
684 con = OMAP_HSMMC_READ(host->base, CON);
903101a8
UH		 685 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
686 ios->timing == MMC_TIMING_UHS_DDR50)
03b5d924
B		 687 con |= DDR; /* configure in DDR mode */
688 else
689 con &= ~DDR;
3796fb8a
AS		 690 switch (ios->bus_width) {
691 case MMC_BUS_WIDTH_8:
692 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
693 break;
694 case MMC_BUS_WIDTH_4:
695 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
696 OMAP_HSMMC_WRITE(host->base, HCTL,
697 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
698 break;
699 case MMC_BUS_WIDTH_1:
700 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
701 OMAP_HSMMC_WRITE(host->base, HCTL,
702 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
703 break;
704 }
705}
706
707static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
708{
709 struct mmc_ios *ios = &host->mmc->ios;
710 u32 con;
711
712 con = OMAP_HSMMC_READ(host->base, CON);
713 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
714 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
715 else
716 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
717}
718
11dd62a7
DK		 719#ifdef CONFIG_PM
720
721/*
722 * Restore the MMC host context, if it was lost as result of a
723 * power state change.
724 */
70a3341a 725static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 726{
727 struct mmc_ios *ios = &host->mmc->ios;
3796fb8a 728 u32 hctl, capa;
11dd62a7
DK		 729 unsigned long timeout;
730
0a82e06e
TL		 731 if (host->con == OMAP_HSMMC_READ(host->base, CON) &&
732 host->hctl == OMAP_HSMMC_READ(host->base, HCTL) &&
733 host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) &&
734 host->capa == OMAP_HSMMC_READ(host->base, CAPA))
735 return 0;
736
737 host->context_loss++;
738
c2200efb 739 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 740 if (host->power_mode != MMC_POWER_OFF &&
741 (1 << ios->vdd) <= MMC_VDD_23_24)
742 hctl = SDVS18;
743 else
744 hctl = SDVS30;
745 capa = VS30 | VS18;
746 } else {
747 hctl = SDVS18;
748 capa = VS18;
749 }
750
5a52b08b
B		 751 if (host->mmc->caps & MMC_CAP_SDIO_IRQ)
752 hctl |= IWE;
753
11dd62a7
DK		 754 OMAP_HSMMC_WRITE(host->base, HCTL,
755 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
756
757 OMAP_HSMMC_WRITE(host->base, CAPA,
758 OMAP_HSMMC_READ(host->base, CAPA) | capa);
759
760 OMAP_HSMMC_WRITE(host->base, HCTL,
761 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
762
763 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
764 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
765 && time_before(jiffies, timeout))
766 ;
767
2cd3a2a5
AF		 768 OMAP_HSMMC_WRITE(host->base, ISE, 0);
769 OMAP_HSMMC_WRITE(host->base, IE, 0);
770 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
11dd62a7
DK		 771
772 /* Do not initialize card-specific things if the power is off */
773 if (host->power_mode == MMC_POWER_OFF)
774 goto out;
775
3796fb8a 776 omap_hsmmc_set_bus_width(host);
11dd62a7 777
5934df2f 778 omap_hsmmc_set_clock(host);
11dd62a7 779
3796fb8a
AS		 780 omap_hsmmc_set_bus_mode(host);
781
11dd62a7 782out:
0a82e06e
TL		 783 dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n",
784 host->context_loss);
11dd62a7
DK		 785 return 0;
786}
787
788/*
789 * Save the MMC host context (store the number of power state changes so far).
790 */
70a3341a 791static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7 792{
0a82e06e
TL		 793 host->con = OMAP_HSMMC_READ(host->base, CON);
794 host->hctl = OMAP_HSMMC_READ(host->base, HCTL);
795 host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL);
796 host->capa = OMAP_HSMMC_READ(host->base, CAPA);
11dd62a7
DK		 797}
798
799#else
800
70a3341a 801static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 802{
803 return 0;
804}
805
70a3341a 806static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 807{
808}
809
810#endif
811
a45c6cb8
MC		 812/*
813 * Send init stream sequence to card
814 * before sending IDLE command
815 */
70a3341a 816static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 817{
818 int reg = 0;
819 unsigned long timeout;
820
b62f6228
AH		 821 if (host->protect_card)
822 return;
823
a45c6cb8 824 disable_irq(host->irq);
b417577d
AH		 825
826 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 827 OMAP_HSMMC_WRITE(host->base, CON,
828 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
829 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
830
831 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
a7e96879
V		 832 while ((reg != CC_EN) && time_before(jiffies, timeout))
833 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN;
a45c6cb8
MC		 834
835 OMAP_HSMMC_WRITE(host->base, CON,
836 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 837
838 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
839 OMAP_HSMMC_READ(host->base, STAT);
840
a45c6cb8
MC		 841 enable_irq(host->irq);
842}
843
844static inline
70a3341a 845int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 846{
847 int r = 1;
848
b5cd43f0 849 if (host->get_cover_state)
80412ca8 850 r = host->get_cover_state(host->dev);
a45c6cb8
MC		 851 return r;
852}
853
854static ssize_t
70a3341a 855omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 856 char *buf)
857{
858 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 859 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 860
70a3341a
DK		 861 return sprintf(buf, "%s\n",
862 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 863}
864
70a3341a 865static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 866
867static ssize_t
70a3341a 868omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 869 char *buf)
870{
871 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 872 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 873
326119c9 874 return sprintf(buf, "%s\n", mmc_pdata(host)->name);
a45c6cb8
MC		 875}
876
70a3341a 877static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 878
879/*
880 * Configure the response type and send the cmd.
881 */
882static void
70a3341a 883omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 884 struct mmc_data *data)
885{
886 int cmdreg = 0, resptype = 0, cmdtype = 0;
887
8986d31b 888 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
a45c6cb8
MC		 889 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
890 host->cmd = cmd;
891
93caf8e6 892 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 893
4a694dc9 894 host->response_busy = 0;
a45c6cb8
MC		 895 if (cmd->flags & MMC_RSP_PRESENT) {
896 if (cmd->flags & MMC_RSP_136)
897 resptype = 1;
4a694dc9
AH		 898 else if (cmd->flags & MMC_RSP_BUSY) {
899 resptype = 3;
900 host->response_busy = 1;
901 } else
a45c6cb8
MC		 902 resptype = 2;
903 }
904
905 /*
906 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
907 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
908 * a val of 0x3, rest 0x0.
909 */
910 if (cmd == host->mrq->stop)
911 cmdtype = 0x3;
912
913 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
914
a2e77152
B		 915 if ((host->flags & AUTO_CMD23) && mmc_op_multi(cmd->opcode) &&
916 host->mrq->sbc) {
917 cmdreg |= ACEN_ACMD23;
918 OMAP_HSMMC_WRITE(host->base, SDMASA, host->mrq->sbc->arg);
919 }
a45c6cb8
MC		 920 if (data) {
921 cmdreg |= DP_SELECT | MSBS | BCE;
922 if (data->flags & MMC_DATA_READ)
923 cmdreg |= DDIR;
924 else
925 cmdreg &= ~(DDIR);
926 }
927
928 if (host->use_dma)
a7e96879 929 cmdreg |= DMAE;
a45c6cb8 930
b417577d 931 host->req_in_progress = 1;
4dffd7a2 932
a45c6cb8
MC		 933 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
934 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
935}
936
0ccd76d4 937static int
70a3341a 938omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 939{
940 if (data->flags & MMC_DATA_WRITE)
941 return DMA_TO_DEVICE;
942 else
943 return DMA_FROM_DEVICE;
944}
945
c5c98927
RK		 946static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host,
947 struct mmc_data *data)
948{
949 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan;
950}
951
b417577d
AH		 952static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
953{
954 int dma_ch;
31463b14 955 unsigned long flags;
b417577d 956
31463b14 957 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 958 host->req_in_progress = 0;
959 dma_ch = host->dma_ch;
31463b14 960 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 961
962 omap_hsmmc_disable_irq(host);
963 /* Do not complete the request if DMA is still in progress */
964 if (mrq->data && host->use_dma && dma_ch != -1)
965 return;
966 host->mrq = NULL;
967 mmc_request_done(host->mmc, mrq);
f57ba4ca
N		 968 pm_runtime_mark_last_busy(host->dev);
969 pm_runtime_put_autosuspend(host->dev);
b417577d
AH		 970}
971
a45c6cb8
MC		 972/*
973 * Notify the transfer complete to MMC core
974 */
975static void
70a3341a 976omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 977{
4a694dc9
AH		 978 if (!data) {
979 struct mmc_request *mrq = host->mrq;
980
23050103
AH		 981 /* TC before CC from CMD6 - don't know why, but it happens */
982 if (host->cmd && host->cmd->opcode == 6 &&
983 host->response_busy) {
984 host->response_busy = 0;
985 return;
986 }
987
b417577d 988 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 989 return;
990 }
991
a45c6cb8
MC		 992 host->data = NULL;
993
a45c6cb8
MC		 994 if (!data->error)
995 data->bytes_xfered += data->blocks * (data->blksz);
996 else
997 data->bytes_xfered = 0;
998
bf129e1c
B		 999 if (data->stop && (data->error || !host->mrq->sbc))
1000 omap_hsmmc_start_command(host, data->stop, NULL);
1001 else
b417577d 1002 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 1003}
1004
1005/*
1006 * Notify the core about command completion
1007 */
1008static void
70a3341a 1009omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8 1010{
bf129e1c 1011 if (host->mrq->sbc && (host->cmd == host->mrq->sbc) &&
a2e77152 1012 !host->mrq->sbc->error && !(host->flags & AUTO_CMD23)) {
2177fa94 1013 host->cmd = NULL;
bf129e1c
B		 1014 omap_hsmmc_start_dma_transfer(host);
1015 omap_hsmmc_start_command(host, host->mrq->cmd,
1016 host->mrq->data);
1017 return;
1018 }
1019
2177fa94
B		 1020 host->cmd = NULL;
1021
a45c6cb8
MC		 1022 if (cmd->flags & MMC_RSP_PRESENT) {
1023 if (cmd->flags & MMC_RSP_136) {
1024 /* response type 2 */
1025 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
1026 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
1027 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
1028 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
1029 } else {
1030 /* response types 1, 1b, 3, 4, 5, 6 */
1031 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
1032 }
1033 }
b417577d 1034 if ((host->data == NULL && !host->response_busy) || cmd->error)
d4b2c375 1035 omap_hsmmc_request_done(host, host->mrq);
a45c6cb8
MC		 1036}
1037
1038/*
1039 * DMA clean up for command errors
1040 */
70a3341a 1041static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 1042{
b417577d 1043 int dma_ch;
31463b14 1044 unsigned long flags;
b417577d 1045
82788ff5 1046 host->data->error = errno;
a45c6cb8 1047
31463b14 1048 spin_lock_irqsave(&host->irq_lock, flags);
b417577d
AH		 1049 dma_ch = host->dma_ch;
1050 host->dma_ch = -1;
31463b14 1051 spin_unlock_irqrestore(&host->irq_lock, flags);
b417577d
AH		 1052
1053 if (host->use_dma && dma_ch != -1) {
c5c98927
RK		 1054 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data);
1055
1056 dmaengine_terminate_all(chan);
1057 dma_unmap_sg(chan->device->dev,
1058 host->data->sg, host->data->sg_len,
70a3341a 1059 omap_hsmmc_get_dma_dir(host, host->data));
c5c98927 1060
053bf34f 1061 host->data->host_cookie = 0;
a45c6cb8
MC		 1062 }
1063 host->data = NULL;
a45c6cb8
MC		 1064}
1065
1066/*
1067 * Readable error output
1068 */
1069#ifdef CONFIG_MMC_DEBUG
699b958b 1070static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 1071{
1072 /* --- means reserved bit without definition at documentation */
70a3341a 1073 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 1074 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
1075 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
1076 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
1077 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 1078 };
1079 char res[256];
1080 char *buf = res;
1081 int len, i;
1082
1083 len = sprintf(buf, "MMC IRQ 0x%x :", status);
1084 buf += len;
1085
70a3341a 1086 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 1087 if (status & (1 << i)) {
70a3341a 1088 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 1089 buf += len;
1090 }
1091
8986d31b 1092 dev_vdbg(mmc_dev(host->mmc), "%s\n", res);
a45c6cb8 1093}
699b958b
AH		 1094#else
1095static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1096 u32 status)
1097{
1098}
a45c6cb8
MC		 1099#endif /* CONFIG_MMC_DEBUG */
1100
3ebf74b1
JP		 1101/*
1102 * MMC controller internal state machines reset
1103 *
1104 * Used to reset command or data internal state machines, using respectively
1105 * SRC or SRD bit of SYSCTL register
1106 * Can be called from interrupt context
1107 */
70a3341a
DK		 1108static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1109 unsigned long bit)
3ebf74b1
JP		 1110{
1111 unsigned long i = 0;
1e881786 1112 unsigned long limit = MMC_TIMEOUT_US;
3ebf74b1
JP		 1113
1114 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1115 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1116
07ad64b6
MC		 1117 /*
1118 * OMAP4 ES2 and greater has an updated reset logic.
1119 * Monitor a 0->1 transition first
1120 */
326119c9 1121 if (mmc_pdata(host)->features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1122 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6 1123 && (i++ < limit))
1e881786 1124 udelay(1);
07ad64b6
MC		 1125 }
1126 i = 0;
1127
3ebf74b1
JP		 1128 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1129 (i++ < limit))
1e881786 1130 udelay(1);
3ebf74b1
JP		 1131
1132 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1133 dev_err(mmc_dev(host->mmc),
1134 "Timeout waiting on controller reset in %s\n",
1135 __func__);
1136}
a45c6cb8 1137
25e1897b
B		 1138static void hsmmc_command_incomplete(struct omap_hsmmc_host *host,
1139 int err, int end_cmd)
ae4bf788 1140{
25e1897b 1141 if (end_cmd) {
94d4f272 1142 omap_hsmmc_reset_controller_fsm(host, SRC);
25e1897b
B		 1143 if (host->cmd)
1144 host->cmd->error = err;
1145 }
ae4bf788
V		 1146
1147 if (host->data) {
1148 omap_hsmmc_reset_controller_fsm(host, SRD);
1149 omap_hsmmc_dma_cleanup(host, err);
dc7745bd
B		 1150 } else if (host->mrq && host->mrq->cmd)
1151 host->mrq->cmd->error = err;
ae4bf788
V		 1152}
1153
b417577d 1154static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1155{
a45c6cb8 1156 struct mmc_data *data;
b417577d 1157 int end_cmd = 0, end_trans = 0;
a2e77152 1158 int error = 0;
b417577d 1159
a45c6cb8 1160 data = host->data;
8986d31b 1161 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
a45c6cb8 1162
a7e96879 1163 if (status & ERR_EN) {
699b958b 1164 omap_hsmmc_dbg_report_irq(host, status);
25e1897b 1165
a7e96879 1166 if (status & (CTO_EN | CCRC_EN))
25e1897b 1167 end_cmd = 1;
408806f7
KVA		 1168 if (host->data || host->response_busy) {
1169 end_trans = !end_cmd;
1170 host->response_busy = 0;
1171 }
a7e96879 1172 if (status & (CTO_EN | DTO_EN))
25e1897b 1173 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd);
5027cd1e
V		 1174 else if (status & (CCRC_EN | DCRC_EN | DEB_EN | CEB_EN |
1175 BADA_EN))
25e1897b 1176 hsmmc_command_incomplete(host, -EILSEQ, end_cmd);
ae4bf788 1177
a2e77152
B		 1178 if (status & ACE_EN) {
1179 u32 ac12;
1180 ac12 = OMAP_HSMMC_READ(host->base, AC12);
1181 if (!(ac12 & ACNE) && host->mrq->sbc) {
1182 end_cmd = 1;
1183 if (ac12 & ACTO)
1184 error = -ETIMEDOUT;
1185 else if (ac12 & (ACCE | ACEB | ACIE))
1186 error = -EILSEQ;
1187 host->mrq->sbc->error = error;
1188 hsmmc_command_incomplete(host, error, end_cmd);
1189 }
1190 dev_dbg(mmc_dev(host->mmc), "AC12 err: 0x%x\n", ac12);
1191 }
a45c6cb8
MC		 1192 }
1193
7472bab2 1194 OMAP_HSMMC_WRITE(host->base, STAT, status);
a7e96879 1195 if (end_cmd || ((status & CC_EN) && host->cmd))
70a3341a 1196 omap_hsmmc_cmd_done(host, host->cmd);
a7e96879 1197 if ((end_trans || (status & TC_EN)) && host->mrq)
70a3341a 1198 omap_hsmmc_xfer_done(host, data);
b417577d 1199}
a45c6cb8 1200
b417577d
AH		 1201/*
1202 * MMC controller IRQ handler
1203 */
1204static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1205{
1206 struct omap_hsmmc_host *host = dev_id;
1207 int status;
1208
1209 status = OMAP_HSMMC_READ(host->base, STAT);
2cd3a2a5
AF		 1210 while (status & (INT_EN_MASK | CIRQ_EN)) {
1211 if (host->req_in_progress)
1212 omap_hsmmc_do_irq(host, status);
1213
1214 if (status & CIRQ_EN)
1215 mmc_signal_sdio_irq(host->mmc);
1f6b9fa4 1216
b417577d
AH		 1217 /* Flush posted write */
1218 status = OMAP_HSMMC_READ(host->base, STAT);
1f6b9fa4 1219 }
4dffd7a2 1220
a45c6cb8
MC		 1221 return IRQ_HANDLED;
1222}
1223
70a3341a 1224static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1225{
1226 unsigned long i;
1227
1228 OMAP_HSMMC_WRITE(host->base, HCTL,
1229 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1230 for (i = 0; i < loops_per_jiffy; i++) {
1231 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1232 break;
1233 cpu_relax();
1234 }
1235}
1236
a45c6cb8 1237/*
eb250826
DB		 1238 * Switch MMC interface voltage ... only relevant for MMC1.
1239 *
1240 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1241 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1242 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1243 */
70a3341a 1244static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1245{
1246 u32 reg_val = 0;
1247 int ret;
1248
1249 /* Disable the clocks */
fa4aa2d4 1250 pm_runtime_put_sync(host->dev);
cd03d9a8 1251 if (host->dbclk)
94c18149 1252 clk_disable_unprepare(host->dbclk);
a45c6cb8
MC		 1253
1254 /* Turn the power off */
f7f0f035 1255 ret = omap_hsmmc_set_power(host->dev, 0, 0);
a45c6cb8
MC		 1256
1257 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893 1258 if (!ret)
f7f0f035 1259 ret = omap_hsmmc_set_power(host->dev, 1, vdd);
fa4aa2d4 1260 pm_runtime_get_sync(host->dev);
cd03d9a8 1261 if (host->dbclk)
94c18149 1262 clk_prepare_enable(host->dbclk);
2bec0893 1263
a45c6cb8
MC		 1264 if (ret != 0)
1265 goto err;
1266
a45c6cb8
MC		 1267 OMAP_HSMMC_WRITE(host->base, HCTL,
1268 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1269 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1270
a45c6cb8
MC		 1271 /*
1272 * If a MMC dual voltage card is detected, the set_ios fn calls
1273 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1274 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1275 *
eb250826
DB		 1276 * Cope with a bit of slop in the range ... per data sheets:
1277 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1278 * but recommended values are 1.71V to 1.89V
1279 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1280 * but recommended values are 2.7V to 3.3V
1281 *
1282 * Board setup code shouldn't permit anything very out-of-range.
1283 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1284 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1285 */
eb250826 1286 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1287 reg_val |= SDVS18;
eb250826
DB		 1288 else
1289 reg_val |= SDVS30;
a45c6cb8
MC		 1290
1291 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1292 set_sd_bus_power(host);
a45c6cb8
MC		 1293
1294 return 0;
1295err:
b1e056ae 1296 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
a45c6cb8
MC		 1297 return ret;
1298}
1299
b62f6228
AH		 1300/* Protect the card while the cover is open */
1301static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1302{
b5cd43f0 1303 if (!host->get_cover_state)
b62f6228
AH		 1304 return;
1305
1306 host->reqs_blocked = 0;
80412ca8 1307 if (host->get_cover_state(host->dev)) {
b62f6228 1308 if (host->protect_card) {
2cecdf00 1309 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1310 "card is now accessible\n",
1311 mmc_hostname(host->mmc));
1312 host->protect_card = 0;
1313 }
1314 } else {
1315 if (!host->protect_card) {
2cecdf00 1316 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1317 "card is now inaccessible\n",
1318 mmc_hostname(host->mmc));
1319 host->protect_card = 1;
1320 }
1321 }
1322}
1323
a45c6cb8 1324/*
cde592cb 1325 * irq handler when (cell-phone) cover is mounted/removed
a45c6cb8 1326 */
cde592cb 1327static irqreturn_t omap_hsmmc_cover_irq(int irq, void *dev_id)
a45c6cb8 1328{
7efab4f3 1329 struct omap_hsmmc_host *host = dev_id;
a6b2240d 1330
a6b2240d 1331 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1332
11227d12
AF		 1333 omap_hsmmc_protect_card(host);
1334 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cde592cb
AF		 1335 return IRQ_HANDLED;
1336}
1337
c5c98927 1338static void omap_hsmmc_dma_callback(void *param)
a45c6cb8 1339{
c5c98927
RK		 1340 struct omap_hsmmc_host *host = param;
1341 struct dma_chan *chan;
770d7432 1342 struct mmc_data *data;
c5c98927 1343 int req_in_progress;
a45c6cb8 1344
c5c98927 1345 spin_lock_irq(&host->irq_lock);
b417577d 1346 if (host->dma_ch < 0) {
c5c98927 1347 spin_unlock_irq(&host->irq_lock);
a45c6cb8 1348 return;
b417577d 1349 }
a45c6cb8 1350
770d7432 1351 data = host->mrq->data;
c5c98927 1352 chan = omap_hsmmc_get_dma_chan(host, data);
9782aff8 1353 if (!data->host_cookie)
c5c98927
RK		 1354 dma_unmap_sg(chan->device->dev,
1355 data->sg, data->sg_len,
9782aff8 1356 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1357
1358 req_in_progress = host->req_in_progress;
a45c6cb8 1359 host->dma_ch = -1;
c5c98927 1360 spin_unlock_irq(&host->irq_lock);
b417577d
AH		 1361
1362 /* If DMA has finished after TC, complete the request */
1363 if (!req_in_progress) {
1364 struct mmc_request *mrq = host->mrq;
1365
1366 host->mrq = NULL;
1367 mmc_request_done(host->mmc, mrq);
f57ba4ca
N		 1368 pm_runtime_mark_last_busy(host->dev);
1369 pm_runtime_put_autosuspend(host->dev);
b417577d 1370 }
a45c6cb8
MC		 1371}
1372
9782aff8
PF		 1373static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1374 struct mmc_data *data,
c5c98927 1375 struct omap_hsmmc_next *next,
26b88520 1376 struct dma_chan *chan)
9782aff8
PF		 1377{
1378 int dma_len;
1379
1380 if (!next && data->host_cookie &&
1381 data->host_cookie != host->next_data.cookie) {
2cecdf00 1382 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1383 " host->next_data.cookie %d\n",
1384 __func__, data->host_cookie, host->next_data.cookie);
1385 data->host_cookie = 0;
1386 }
1387
1388 /* Check if next job is already prepared */
b38313d6 1389 if (next || data->host_cookie != host->next_data.cookie) {
26b88520 1390 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len,
9782aff8
PF		 1391 omap_hsmmc_get_dma_dir(host, data));
1392
1393 } else {
1394 dma_len = host->next_data.dma_len;
1395 host->next_data.dma_len = 0;
1396 }
1397
1398
1399 if (dma_len == 0)
1400 return -EINVAL;
1401
1402 if (next) {
1403 next->dma_len = dma_len;
1404 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1405 } else
1406 host->dma_len = dma_len;
1407
1408 return 0;
1409}
1410
a45c6cb8
MC		 1411/*
1412 * Routine to configure and start DMA for the MMC card
1413 */
9d025334 1414static int omap_hsmmc_setup_dma_transfer(struct omap_hsmmc_host *host,
70a3341a 1415 struct mmc_request *req)
a45c6cb8 1416{
26b88520
RK		 1417 struct dma_slave_config cfg;
1418 struct dma_async_tx_descriptor *tx;
1419 int ret = 0, i;
a45c6cb8 1420 struct mmc_data *data = req->data;
c5c98927 1421 struct dma_chan *chan;
a45c6cb8 1422
0ccd76d4 1423 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1424 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1425 struct scatterlist *sgl;
1426
1427 sgl = data->sg + i;
1428 if (sgl->length % data->blksz)
1429 return -EINVAL;
1430 }
1431 if ((data->blksz % 4) != 0)
1432 /* REVISIT: The MMC buffer increments only when MSB is written.
1433 * Return error for blksz which is non multiple of four.
1434 */
1435 return -EINVAL;
1436
b417577d 1437 BUG_ON(host->dma_ch != -1);
a45c6cb8 1438
c5c98927 1439 chan = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1440
26b88520
RK		 1441 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA;
1442 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA;
1443 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1444 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1445 cfg.src_maxburst = data->blksz / 4;
1446 cfg.dst_maxburst = data->blksz / 4;
c5c98927 1447
26b88520
RK		 1448 ret = dmaengine_slave_config(chan, &cfg);
1449 if (ret)
a45c6cb8 1450 return ret;
c5c98927 1451
26b88520 1452 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan);
9782aff8
PF		 1453 if (ret)
1454 return ret;
a45c6cb8 1455
26b88520
RK		 1456 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len,
1457 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM,
1458 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1459 if (!tx) {
1460 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n");
1461 /* FIXME: cleanup */
1462 return -1;
1463 }
a45c6cb8 1464
26b88520
RK		 1465 tx->callback = omap_hsmmc_dma_callback;
1466 tx->callback_param = host;
a45c6cb8 1467
26b88520
RK		 1468 /* Does not fail */
1469 dmaengine_submit(tx);
c5c98927 1470
26b88520 1471 host->dma_ch = 1;
c5c98927 1472
a45c6cb8
MC		 1473 return 0;
1474}
1475
70a3341a 1476static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1477 unsigned int timeout_ns,
1478 unsigned int timeout_clks)
a45c6cb8
MC		 1479{
1480 unsigned int timeout, cycle_ns;
1481 uint32_t reg, clkd, dto = 0;
1482
1483 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1484 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1485 if (clkd == 0)
1486 clkd = 1;
1487
6e3076c2 1488 cycle_ns = 1000000000 / (host->clk_rate / clkd);
e2bf08d6
AH		 1489 timeout = timeout_ns / cycle_ns;
1490 timeout += timeout_clks;
a45c6cb8
MC		 1491 if (timeout) {
1492 while ((timeout & 0x80000000) == 0) {
1493 dto += 1;
1494 timeout <<= 1;
1495 }
1496 dto = 31 - dto;
1497 timeout <<= 1;
1498 if (timeout && dto)
1499 dto += 1;
1500 if (dto >= 13)
1501 dto -= 13;
1502 else
1503 dto = 0;
1504 if (dto > 14)
1505 dto = 14;
1506 }
1507
1508 reg &= ~DTO_MASK;
1509 reg |= dto << DTO_SHIFT;
1510 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1511}
1512
9d025334
B		 1513static void omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host)
1514{
1515 struct mmc_request *req = host->mrq;
1516 struct dma_chan *chan;
1517
1518 if (!req->data)
1519 return;
1520 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1521 | (req->data->blocks << 16));
1522 set_data_timeout(host, req->data->timeout_ns,
1523 req->data->timeout_clks);
1524 chan = omap_hsmmc_get_dma_chan(host, req->data);
1525 dma_async_issue_pending(chan);
1526}
1527
a45c6cb8
MC		 1528/*
1529 * Configure block length for MMC/SD cards and initiate the transfer.
1530 */
1531static int
70a3341a 1532omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1533{
1534 int ret;
1535 host->data = req->data;
1536
1537 if (req->data == NULL) {
a45c6cb8 1538 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1539 /*
1540 * Set an arbitrary 100ms data timeout for commands with
1541 * busy signal.
1542 */
1543 if (req->cmd->flags & MMC_RSP_BUSY)
1544 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1545 return 0;
1546 }
1547
a45c6cb8 1548 if (host->use_dma) {
9d025334 1549 ret = omap_hsmmc_setup_dma_transfer(host, req);
a45c6cb8 1550 if (ret != 0) {
b1e056ae 1551 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n");
a45c6cb8
MC		 1552 return ret;
1553 }
1554 }
1555 return 0;
1556}
1557
9782aff8
PF		 1558static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1559 int err)
1560{
1561 struct omap_hsmmc_host *host = mmc_priv(mmc);
1562 struct mmc_data *data = mrq->data;
1563
26b88520 1564 if (host->use_dma && data->host_cookie) {
c5c98927 1565 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data);
c5c98927 1566
26b88520
RK		 1567 dma_unmap_sg(c->device->dev, data->sg, data->sg_len,
1568 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1569 data->host_cookie = 0;
1570 }
1571}
1572
1573static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1574 bool is_first_req)
1575{
1576 struct omap_hsmmc_host *host = mmc_priv(mmc);
1577
1578 if (mrq->data->host_cookie) {
1579 mrq->data->host_cookie = 0;
1580 return ;
1581 }
1582
c5c98927
RK		 1583 if (host->use_dma) {
1584 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data);
c5c98927 1585
9782aff8 1586 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
26b88520 1587 &host->next_data, c))
9782aff8 1588 mrq->data->host_cookie = 0;
c5c98927 1589 }
9782aff8
PF		 1590}
1591
a45c6cb8
MC		 1592/*
1593 * Request function. for read/write operation
1594 */
70a3341a 1595static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1596{
70a3341a 1597 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1598 int err;
a45c6cb8 1599
b417577d
AH		 1600 BUG_ON(host->req_in_progress);
1601 BUG_ON(host->dma_ch != -1);
f57ba4ca 1602 pm_runtime_get_sync(host->dev);
b417577d
AH		 1603 if (host->protect_card) {
1604 if (host->reqs_blocked < 3) {
1605 /*
1606 * Ensure the controller is left in a consistent
1607 * state by resetting the command and data state
1608 * machines.
1609 */
1610 omap_hsmmc_reset_controller_fsm(host, SRD);
1611 omap_hsmmc_reset_controller_fsm(host, SRC);
1612 host->reqs_blocked += 1;
1613 }
1614 req->cmd->error = -EBADF;
1615 if (req->data)
1616 req->data->error = -EBADF;
1617 req->cmd->retries = 0;
1618 mmc_request_done(mmc, req);
f57ba4ca
N		 1619 pm_runtime_mark_last_busy(host->dev);
1620 pm_runtime_put_autosuspend(host->dev);
b417577d
AH		 1621 return;
1622 } else if (host->reqs_blocked)
1623 host->reqs_blocked = 0;
a45c6cb8
MC		 1624 WARN_ON(host->mrq != NULL);
1625 host->mrq = req;
6e3076c2 1626 host->clk_rate = clk_get_rate(host->fclk);
70a3341a 1627 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1628 if (err) {
1629 req->cmd->error = err;
1630 if (req->data)
1631 req->data->error = err;
1632 host->mrq = NULL;
1633 mmc_request_done(mmc, req);
f57ba4ca
N		 1634 pm_runtime_mark_last_busy(host->dev);
1635 pm_runtime_put_autosuspend(host->dev);
a3f406f8
JL		 1636 return;
1637 }
a2e77152 1638 if (req->sbc && !(host->flags & AUTO_CMD23)) {
bf129e1c
B		 1639 omap_hsmmc_start_command(host, req->sbc, NULL);
1640 return;
1641 }
a3f406f8 1642
9d025334 1643 omap_hsmmc_start_dma_transfer(host);
70a3341a 1644 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1645}
1646
a45c6cb8 1647/* Routine to configure clock values. Exposed API to core */
70a3341a 1648static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1649{
70a3341a 1650 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1651 int do_send_init_stream = 0;
a45c6cb8 1652
fa4aa2d4 1653 pm_runtime_get_sync(host->dev);
5e2ea617 1654
a3621465
AH		 1655 if (ios->power_mode != host->power_mode) {
1656 switch (ios->power_mode) {
1657 case MMC_POWER_OFF:
f7f0f035 1658 omap_hsmmc_set_power(host->dev, 0, 0);
a3621465
AH		 1659 break;
1660 case MMC_POWER_UP:
f7f0f035 1661 omap_hsmmc_set_power(host->dev, 1, ios->vdd);
a3621465
AH		 1662 break;
1663 case MMC_POWER_ON:
1664 do_send_init_stream = 1;
1665 break;
1666 }
1667 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1668 }
1669
dd498eff
DK		 1670 /* FIXME: set registers based only on changes to ios */
1671
3796fb8a 1672 omap_hsmmc_set_bus_width(host);
a45c6cb8 1673
4621d5f8 1674 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1675 /* Only MMC1 can interface at 3V without some flavor
1676 * of external transceiver; but they all handle 1.8V.
1677 */
a45c6cb8 1678 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
2cf171cb 1679 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
a45c6cb8
MC		 1680 /*
1681 * The mmc_select_voltage fn of the core does
1682 * not seem to set the power_mode to
1683 * MMC_POWER_UP upon recalculating the voltage.
1684 * vdd 1.8v.
1685 */
70a3341a
DK		 1686 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1687 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1688 "Switch operation failed\n");
1689 }
1690 }
1691
5934df2f 1692 omap_hsmmc_set_clock(host);
a45c6cb8 1693
a3621465 1694 if (do_send_init_stream)
a45c6cb8
MC		 1695 send_init_stream(host);
1696
3796fb8a 1697 omap_hsmmc_set_bus_mode(host);
5e2ea617 1698
fa4aa2d4 1699 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1700}
1701
1702static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1703{
70a3341a 1704 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1705
b5cd43f0 1706 if (!host->card_detect)
a45c6cb8 1707 return -ENOSYS;
80412ca8 1708 return host->card_detect(host->dev);
a45c6cb8
MC		 1709}
1710
4816858c
GI		 1711static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1712{
1713 struct omap_hsmmc_host *host = mmc_priv(mmc);
1714
326119c9
AF		 1715 if (mmc_pdata(host)->init_card)
1716 mmc_pdata(host)->init_card(card);
4816858c
GI		 1717}
1718
2cd3a2a5
AF		 1719static void omap_hsmmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
1720{
1721 struct omap_hsmmc_host *host = mmc_priv(mmc);
5a52b08b 1722 u32 irq_mask, con;
2cd3a2a5
AF		 1723 unsigned long flags;
1724
1725 spin_lock_irqsave(&host->irq_lock, flags);
1726
5a52b08b 1727 con = OMAP_HSMMC_READ(host->base, CON);
2cd3a2a5
AF		 1728 irq_mask = OMAP_HSMMC_READ(host->base, ISE);
1729 if (enable) {
1730 host->flags |= HSMMC_SDIO_IRQ_ENABLED;
1731 irq_mask |= CIRQ_EN;
5a52b08b 1732 con |= CTPL | CLKEXTFREE;
2cd3a2a5
AF		 1733 } else {
1734 host->flags &= ~HSMMC_SDIO_IRQ_ENABLED;
1735 irq_mask &= ~CIRQ_EN;
5a52b08b 1736 con &= ~(CTPL | CLKEXTFREE);
2cd3a2a5 1737 }
5a52b08b 1738 OMAP_HSMMC_WRITE(host->base, CON, con);
2cd3a2a5
AF		 1739 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
1740
1741 /*
1742 * if enable, piggy back detection on current request
1743 * but always disable immediately
1744 */
1745 if (!host->req_in_progress || !enable)
1746 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
1747
1748 /* flush posted write */
1749 OMAP_HSMMC_READ(host->base, IE);
1750
1751 spin_unlock_irqrestore(&host->irq_lock, flags);
1752}
1753
1754static int omap_hsmmc_configure_wake_irq(struct omap_hsmmc_host *host)
1755{
2cd3a2a5
AF		 1756 int ret;
1757
1758 /*
1759 * For omaps with wake-up path, wakeirq will be irq from pinctrl and
1760 * for other omaps, wakeirq will be from GPIO (dat line remuxed to
1761 * gpio). wakeirq is needed to detect sdio irq in runtime suspend state
1762 * with functional clock disabled.
1763 */
1764 if (!host->dev->of_node || !host->wake_irq)
1765 return -ENODEV;
1766
5b83b223 1767 ret = dev_pm_set_dedicated_wake_irq(host->dev, host->wake_irq);
2cd3a2a5
AF		 1768 if (ret) {
1769 dev_err(mmc_dev(host->mmc), "Unable to request wake IRQ\n");
1770 goto err;
1771 }
1772
1773 /*
1774 * Some omaps don't have wake-up path from deeper idle states
1775 * and need to remux SDIO DAT1 to GPIO for wake-up from idle.
1776 */
1777 if (host->pdata->controller_flags & OMAP_HSMMC_SWAKEUP_MISSING) {
455e5cd6
AF		 1778 struct pinctrl *p = devm_pinctrl_get(host->dev);
1779 if (!p) {
1780 ret = -ENODEV;
1781 goto err_free_irq;
1782 }
1783 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_DEFAULT))) {
1784 dev_info(host->dev, "missing default pinctrl state\n");
1785 devm_pinctrl_put(p);
1786 ret = -EINVAL;
1787 goto err_free_irq;
1788 }
1789
1790 if (IS_ERR(pinctrl_lookup_state(p, PINCTRL_STATE_IDLE))) {
1791 dev_info(host->dev, "missing idle pinctrl state\n");
1792 devm_pinctrl_put(p);
1793 ret = -EINVAL;
1794 goto err_free_irq;
1795 }
1796 devm_pinctrl_put(p);
2cd3a2a5
AF		 1797 }
1798
5a52b08b
B		 1799 OMAP_HSMMC_WRITE(host->base, HCTL,
1800 OMAP_HSMMC_READ(host->base, HCTL) | IWE);
2cd3a2a5
AF		 1801 return 0;
1802
455e5cd6 1803err_free_irq:
5b83b223 1804 dev_pm_clear_wake_irq(host->dev);
2cd3a2a5
AF		 1805err:
1806 dev_warn(host->dev, "no SDIO IRQ support, falling back to polling\n");
1807 host->wake_irq = 0;
1808 return ret;
1809}
1810
70a3341a 1811static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1812{
1813 u32 hctl, capa, value;
1814
1815 /* Only MMC1 supports 3.0V */
4621d5f8 1816 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1817 hctl = SDVS30;
1818 capa = VS30 | VS18;
1819 } else {
1820 hctl = SDVS18;
1821 capa = VS18;
1822 }
1823
1824 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1825 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1826
1827 value = OMAP_HSMMC_READ(host->base, CAPA);
1828 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1829
1b331e69 1830 /* Set SD bus power bit */
e13bb300 1831 set_sd_bus_power(host);
1b331e69
KK		 1832}
1833
afd8c29d
KM		 1834static int omap_hsmmc_multi_io_quirk(struct mmc_card *card,
1835 unsigned int direction, int blk_size)
1836{
1837 /* This controller can't do multiblock reads due to hw bugs */
1838 if (direction == MMC_DATA_READ)
1839 return 1;
1840
1841 return blk_size;
1842}
1843
1844static struct mmc_host_ops omap_hsmmc_ops = {
9782aff8
PF		 1845 .post_req = omap_hsmmc_post_req,
1846 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1847 .request = omap_hsmmc_request,
1848 .set_ios = omap_hsmmc_set_ios,
dd498eff 1849 .get_cd = omap_hsmmc_get_cd,
a49d8353 1850 .get_ro = mmc_gpio_get_ro,
4816858c 1851 .init_card = omap_hsmmc_init_card,
2cd3a2a5 1852 .enable_sdio_irq = omap_hsmmc_enable_sdio_irq,
dd498eff
DK		 1853};
1854
d900f712
DK		 1855#ifdef CONFIG_DEBUG_FS
1856
70a3341a 1857static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1858{
1859 struct mmc_host *mmc = s->private;
70a3341a 1860 struct omap_hsmmc_host *host = mmc_priv(mmc);
d900f712 1861
bb0635f0
AF		 1862 seq_printf(s, "mmc%d:\n", mmc->index);
1863 seq_printf(s, "sdio irq mode\t%s\n",
1864 (mmc->caps & MMC_CAP_SDIO_IRQ) ? "interrupt" : "polling");
5e2ea617 1865
bb0635f0
AF		 1866 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1867 seq_printf(s, "sdio irq \t%s\n",
1868 (host->flags & HSMMC_SDIO_IRQ_ENABLED) ? "enabled"
1869 : "disabled");
1870 }
1871 seq_printf(s, "ctx_loss:\t%d\n", host->context_loss);
d900f712 1872
bb0635f0
AF		 1873 pm_runtime_get_sync(host->dev);
1874 seq_puts(s, "\nregs:\n");
d900f712
DK		 1875 seq_printf(s, "CON:\t\t0x%08x\n",
1876 OMAP_HSMMC_READ(host->base, CON));
bb0635f0
AF		 1877 seq_printf(s, "PSTATE:\t\t0x%08x\n",
1878 OMAP_HSMMC_READ(host->base, PSTATE));
d900f712
DK		 1879 seq_printf(s, "HCTL:\t\t0x%08x\n",
1880 OMAP_HSMMC_READ(host->base, HCTL));
1881 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1882 OMAP_HSMMC_READ(host->base, SYSCTL));
1883 seq_printf(s, "IE:\t\t0x%08x\n",
1884 OMAP_HSMMC_READ(host->base, IE));
1885 seq_printf(s, "ISE:\t\t0x%08x\n",
1886 OMAP_HSMMC_READ(host->base, ISE));
1887 seq_printf(s, "CAPA:\t\t0x%08x\n",
1888 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1889
fa4aa2d4
B		 1890 pm_runtime_mark_last_busy(host->dev);
1891 pm_runtime_put_autosuspend(host->dev);
dd498eff 1892
d900f712
DK		 1893 return 0;
1894}
1895
70a3341a 1896static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1897{
70a3341a 1898 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1899}
1900
1901static const struct file_operations mmc_regs_fops = {
70a3341a 1902 .open = omap_hsmmc_regs_open,
d900f712
DK		 1903 .read = seq_read,
1904 .llseek = seq_lseek,
1905 .release = single_release,
1906};
1907
70a3341a 1908static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1909{
1910 if (mmc->debugfs_root)
1911 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1912 mmc, &mmc_regs_fops);
1913}
1914
1915#else
1916
70a3341a 1917static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1918{
1919}
1920
1921#endif
1922
46856a68 1923#ifdef CONFIG_OF
59445b10
NM		 1924static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
1925 /* See 35xx errata 2.1.1.128 in SPRZ278F */
1926 .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
1927};
1928
1929static const struct omap_mmc_of_data omap4_mmc_of_data = {
1930 .reg_offset = 0x100,
1931};
2cd3a2a5
AF		 1932static const struct omap_mmc_of_data am33xx_mmc_of_data = {
1933 .reg_offset = 0x100,
1934 .controller_flags = OMAP_HSMMC_SWAKEUP_MISSING,
1935};
46856a68
RN		 1936
1937static const struct of_device_id omap_mmc_of_match[] = {
1938 {
1939 .compatible = "ti,omap2-hsmmc",
1940 },
59445b10
NM		 1941 {
1942 .compatible = "ti,omap3-pre-es3-hsmmc",
1943 .data = &omap3_pre_es3_mmc_of_data,
1944 },
46856a68
RN		 1945 {
1946 .compatible = "ti,omap3-hsmmc",
1947 },
1948 {
1949 .compatible = "ti,omap4-hsmmc",
59445b10 1950 .data = &omap4_mmc_of_data,
46856a68 1951 },
2cd3a2a5
AF		 1952 {
1953 .compatible = "ti,am33xx-hsmmc",
1954 .data = &am33xx_mmc_of_data,
1955 },
46856a68 1956 {},
b6d085f6 1957};
46856a68
RN		 1958MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1959
55143438 1960static struct omap_hsmmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
46856a68 1961{
55143438 1962 struct omap_hsmmc_platform_data *pdata;
46856a68 1963 struct device_node *np = dev->of_node;
46856a68
RN		 1964
1965 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1966 if (!pdata)
19df45bc 1967 return ERR_PTR(-ENOMEM); /* out of memory */
46856a68
RN		 1968
1969 if (of_find_property(np, "ti,dual-volt", NULL))
1970 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1971
b7a5646f
AF		 1972 pdata->gpio_cd = -EINVAL;
1973 pdata->gpio_cod = -EINVAL;
fdb9de12 1974 pdata->gpio_wp = -EINVAL;
46856a68
RN		 1975
1976 if (of_find_property(np, "ti,non-removable", NULL)) {
326119c9
AF		 1977 pdata->nonremovable = true;
1978 pdata->no_regulator_off_init = true;
46856a68 1979 }
46856a68
RN		 1980
1981 if (of_find_property(np, "ti,needs-special-reset", NULL))
326119c9 1982 pdata->features |= HSMMC_HAS_UPDATED_RESET;
46856a68 1983
cd587096 1984 if (of_find_property(np, "ti,needs-special-hs-handling", NULL))
326119c9 1985 pdata->features |= HSMMC_HAS_HSPE_SUPPORT;
cd587096 1986
46856a68
RN		 1987 return pdata;
1988}
1989#else
55143438 1990static inline struct omap_hsmmc_platform_data
46856a68
RN		 1991 *of_get_hsmmc_pdata(struct device *dev)
1992{
19df45bc 1993 return ERR_PTR(-EINVAL);
46856a68
RN		 1994}
1995#endif
1996
c3be1efd 1997static int omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8 1998{
55143438 1999 struct omap_hsmmc_platform_data *pdata = pdev->dev.platform_data;
a45c6cb8 2000 struct mmc_host *mmc;
70a3341a 2001 struct omap_hsmmc_host *host = NULL;
a45c6cb8 2002 struct resource *res;
db0fefc5 2003 int ret, irq;
46856a68 2004 const struct of_device_id *match;
26b88520
RK		 2005 dma_cap_mask_t mask;
2006 unsigned tx_req, rx_req;
59445b10 2007 const struct omap_mmc_of_data *data;
77fae219 2008 void __iomem *base;
46856a68
RN		 2009
2010 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
2011 if (match) {
2012 pdata = of_get_hsmmc_pdata(&pdev->dev);
dc642c28
JL		 2013
2014 if (IS_ERR(pdata))
2015 return PTR_ERR(pdata);
2016
46856a68 2017 if (match->data) {
59445b10
NM		 2018 data = match->data;
2019 pdata->reg_offset = data->reg_offset;
2020 pdata->controller_flags |= data->controller_flags;
46856a68
RN		 2021 }
2022 }
a45c6cb8
MC		 2023
2024 if (pdata == NULL) {
2025 dev_err(&pdev->dev, "Platform Data is missing\n");
2026 return -ENXIO;
2027 }
2028
a45c6cb8
MC		 2029 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2030 irq = platform_get_irq(pdev, 0);
2031 if (res == NULL || irq < 0)
2032 return -ENXIO;
2033
77fae219
B		 2034 base = devm_ioremap_resource(&pdev->dev, res);
2035 if (IS_ERR(base))
2036 return PTR_ERR(base);
a45c6cb8 2037
70a3341a 2038 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 2039 if (!mmc) {
2040 ret = -ENOMEM;
1e363e3b 2041 goto err;
a45c6cb8
MC		 2042 }
2043
fdb9de12
N		 2044 ret = mmc_of_parse(mmc);
2045 if (ret)
2046 goto err1;
2047
a45c6cb8
MC		 2048 host = mmc_priv(mmc);
2049 host->mmc = mmc;
2050 host->pdata = pdata;
2051 host->dev = &pdev->dev;
2052 host->use_dma = 1;
a45c6cb8
MC		 2053 host->dma_ch = -1;
2054 host->irq = irq;
fc307df8 2055 host->mapbase = res->start + pdata->reg_offset;
77fae219 2056 host->base = base + pdata->reg_offset;
6da20c89 2057 host->power_mode = MMC_POWER_OFF;
9782aff8 2058 host->next_data.cookie = 1;
bb2726b5 2059 host->pbias_enabled = 0;
3f77f702 2060 host->vqmmc_enabled = 0;
a45c6cb8 2061
41afa314 2062 ret = omap_hsmmc_gpio_init(mmc, host, pdata);
1e363e3b
AF		 2063 if (ret)
2064 goto err_gpio;
2065
a45c6cb8 2066 platform_set_drvdata(pdev, host);
a45c6cb8 2067
2cd3a2a5
AF		 2068 if (pdev->dev.of_node)
2069 host->wake_irq = irq_of_parse_and_map(pdev->dev.of_node, 1);
2070
7a8c2cef 2071 mmc->ops = &omap_hsmmc_ops;
dd498eff 2072
d418ed87
DM		 2073 mmc->f_min = OMAP_MMC_MIN_CLOCK;
2074
2075 if (pdata->max_freq > 0)
2076 mmc->f_max = pdata->max_freq;
fdb9de12 2077 else if (mmc->f_max == 0)
d418ed87 2078 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 2079
4dffd7a2 2080 spin_lock_init(&host->irq_lock);
a45c6cb8 2081
9618195e 2082 host->fclk = devm_clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 2083 if (IS_ERR(host->fclk)) {
2084 ret = PTR_ERR(host->fclk);
2085 host->fclk = NULL;
a45c6cb8
MC		 2086 goto err1;
2087 }
2088
9b68256c
PW		 2089 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
2090 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
afd8c29d 2091 omap_hsmmc_ops.multi_io_quirk = omap_hsmmc_multi_io_quirk;
9b68256c 2092 }
dd498eff 2093
5b83b223 2094 device_init_wakeup(&pdev->dev, true);
fa4aa2d4
B		 2095 pm_runtime_enable(host->dev);
2096 pm_runtime_get_sync(host->dev);
2097 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
2098 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 2099
92a3aebf
B		 2100 omap_hsmmc_context_save(host);
2101
9618195e 2102 host->dbclk = devm_clk_get(&pdev->dev, "mmchsdb_fck");
cd03d9a8
RN		 2103 /*
2104 * MMC can still work without debounce clock.
2105 */
2106 if (IS_ERR(host->dbclk)) {
cd03d9a8 2107 host->dbclk = NULL;
94c18149 2108 } else if (clk_prepare_enable(host->dbclk) != 0) {
cd03d9a8 2109 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n");
cd03d9a8 2110 host->dbclk = NULL;
2bec0893 2111 }
a45c6cb8 2112
0ccd76d4
JY		 2113 /* Since we do only SG emulation, we can have as many segs
2114 * as we want. */
a36274e0 2115 mmc->max_segs = 1024;
0ccd76d4 2116
a45c6cb8
MC		 2117 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2118 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2119 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2120 mmc->max_seg_size = mmc->max_req_size;
2121
13189e78 2122 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 2123 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 2124
326119c9 2125 mmc->caps |= mmc_pdata(host)->caps;
3a63833e 2126 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 2127 mmc->caps |= MMC_CAP_4_BIT_DATA;
2128
326119c9 2129 if (mmc_pdata(host)->nonremovable)
23d99bb9
AH		 2130 mmc->caps |= MMC_CAP_NONREMOVABLE;
2131
fdb9de12 2132 mmc->pm_caps |= mmc_pdata(host)->pm_caps;
6fdc75de 2133
70a3341a 2134 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2135
4a29b559
SS		 2136 if (!pdev->dev.of_node) {
2137 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
2138 if (!res) {
2139 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
2140 ret = -ENXIO;
2141 goto err_irq;
2142 }
2143 tx_req = res->start;
b7bf773b 2144
4a29b559
SS		 2145 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
2146 if (!res) {
2147 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
2148 ret = -ENXIO;
2149 goto err_irq;
2150 }
2151 rx_req = res->start;
f3e2f1dd 2152 }
a45c6cb8 2153
26b88520
RK		 2154 dma_cap_zero(mask);
2155 dma_cap_set(DMA_SLAVE, mask);
2156
d272fbf0
MP		 2157 host->rx_chan =
2158 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2159 &rx_req, &pdev->dev, "rx");
2160
26b88520
RK		 2161 if (!host->rx_chan) {
2162 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
04e8c7bc 2163 ret = -ENXIO;
26b88520
RK		 2164 goto err_irq;
2165 }
2166
d272fbf0
MP		 2167 host->tx_chan =
2168 dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
2169 &tx_req, &pdev->dev, "tx");
2170
26b88520
RK		 2171 if (!host->tx_chan) {
2172 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
04e8c7bc 2173 ret = -ENXIO;
26b88520 2174 goto err_irq;
c5c98927 2175 }
a45c6cb8
MC		 2176
2177 /* Request IRQ for MMC operations */
e1538ed7 2178 ret = devm_request_irq(&pdev->dev, host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 2179 mmc_hostname(mmc), host);
2180 if (ret) {
b1e056ae 2181 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
a45c6cb8
MC		 2182 goto err_irq;
2183 }
2184
987e05c9
KVA		 2185 ret = omap_hsmmc_reg_get(host);
2186 if (ret)
2187 goto err_irq;
db0fefc5 2188
326119c9 2189 mmc->ocr_avail = mmc_pdata(host)->ocr_mask;
a45c6cb8 2190
b417577d 2191 omap_hsmmc_disable_irq(host);
a45c6cb8 2192
2cd3a2a5
AF		 2193 /*
2194 * For now, only support SDIO interrupt if we have a separate
2195 * wake-up interrupt configured from device tree. This is because
2196 * the wake-up interrupt is needed for idle state and some
2197 * platforms need special quirks. And we don't want to add new
2198 * legacy mux platform init code callbacks any longer as we
2199 * are moving to DT based booting anyways.
2200 */
2201 ret = omap_hsmmc_configure_wake_irq(host);
2202 if (!ret)
2203 mmc->caps |= MMC_CAP_SDIO_IRQ;
2204
b62f6228
AH		 2205 omap_hsmmc_protect_card(host);
2206
a45c6cb8
MC		 2207 mmc_add_host(mmc);
2208
326119c9 2209 if (mmc_pdata(host)->name != NULL) {
a45c6cb8
MC		 2210 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2211 if (ret < 0)
2212 goto err_slot_name;
2213 }
cde592cb 2214 if (host->get_cover_state) {
a45c6cb8 2215 ret = device_create_file(&mmc->class_dev,
cde592cb 2216 &dev_attr_cover_switch);
a45c6cb8 2217 if (ret < 0)
db0fefc5 2218 goto err_slot_name;
a45c6cb8
MC		 2219 }
2220
70a3341a 2221 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 2222 pm_runtime_mark_last_busy(host->dev);
2223 pm_runtime_put_autosuspend(host->dev);
d900f712 2224
a45c6cb8
MC		 2225 return 0;
2226
a45c6cb8
MC		 2227err_slot_name:
2228 mmc_remove_host(mmc);
a45c6cb8 2229err_irq:
5b83b223 2230 device_init_wakeup(&pdev->dev, false);
c5c98927
RK		 2231 if (host->tx_chan)
2232 dma_release_channel(host->tx_chan);
2233 if (host->rx_chan)
2234 dma_release_channel(host->rx_chan);
814a3c0c 2235 pm_runtime_dont_use_autosuspend(host->dev);
d59d77ed 2236 pm_runtime_put_sync(host->dev);
37f6190d 2237 pm_runtime_disable(host->dev);
9618195e 2238 if (host->dbclk)
94c18149 2239 clk_disable_unprepare(host->dbclk);
a45c6cb8 2240err1:
1e363e3b 2241err_gpio:
db0fefc5 2242 mmc_free_host(mmc);
a45c6cb8 2243err:
a45c6cb8
MC		 2244 return ret;
2245}
2246
6e0ee714 2247static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2248{
70a3341a 2249 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8 2250
927ce944
FB		 2251 pm_runtime_get_sync(host->dev);
2252 mmc_remove_host(host->mmc);
a45c6cb8 2253
dc28562b
PU		 2254 dma_release_channel(host->tx_chan);
2255 dma_release_channel(host->rx_chan);
c5c98927 2256
814a3c0c 2257 pm_runtime_dont_use_autosuspend(host->dev);
927ce944
FB		 2258 pm_runtime_put_sync(host->dev);
2259 pm_runtime_disable(host->dev);
5b83b223 2260 device_init_wakeup(&pdev->dev, false);
9618195e 2261 if (host->dbclk)
94c18149 2262 clk_disable_unprepare(host->dbclk);
a45c6cb8 2263
9d1f0286 2264 mmc_free_host(host->mmc);
927ce944 2265
a45c6cb8
MC		 2266 return 0;
2267}
2268
3d3bbfbd 2269#ifdef CONFIG_PM_SLEEP
a791daa1 2270static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8 2271{
927ce944 2272 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2273
927ce944 2274 if (!host)
a45c6cb8
MC		 2275 return 0;
2276
927ce944 2277 pm_runtime_get_sync(host->dev);
31f9d463 2278
927ce944 2279 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2cd3a2a5
AF		 2280 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2281 OMAP_HSMMC_WRITE(host->base, IE, 0);
2282 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
927ce944
FB		 2283 OMAP_HSMMC_WRITE(host->base, HCTL,
2284 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2285 }
927ce944 2286
cd03d9a8 2287 if (host->dbclk)
94c18149 2288 clk_disable_unprepare(host->dbclk);
3932afd5 2289
31f9d463 2290 pm_runtime_put_sync(host->dev);
3932afd5 2291 return 0;
a45c6cb8
MC		 2292}
2293
2294/* Routine to resume the MMC device */
a791daa1 2295static int omap_hsmmc_resume(struct device *dev)
a45c6cb8 2296{
927ce944
FB		 2297 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2298
2299 if (!host)
2300 return 0;
a45c6cb8 2301
927ce944 2302 pm_runtime_get_sync(host->dev);
11dd62a7 2303
cd03d9a8 2304 if (host->dbclk)
94c18149 2305 clk_prepare_enable(host->dbclk);
2bec0893 2306
927ce944
FB		 2307 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2308 omap_hsmmc_conf_bus_power(host);
1b331e69 2309
927ce944 2310 omap_hsmmc_protect_card(host);
927ce944
FB		 2311 pm_runtime_mark_last_busy(host->dev);
2312 pm_runtime_put_autosuspend(host->dev);
3932afd5 2313 return 0;
a45c6cb8 2314}
a45c6cb8
MC		 2315#endif
2316
fa4aa2d4
B		 2317static int omap_hsmmc_runtime_suspend(struct device *dev)
2318{
2319 struct omap_hsmmc_host *host;
2cd3a2a5 2320 unsigned long flags;
f945901f 2321 int ret = 0;
fa4aa2d4
B		 2322
2323 host = platform_get_drvdata(to_platform_device(dev));
2324 omap_hsmmc_context_save(host);
927ce944 2325 dev_dbg(dev, "disabled\n");
fa4aa2d4 2326
2cd3a2a5
AF		 2327 spin_lock_irqsave(&host->irq_lock, flags);
2328 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2329 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2330 /* disable sdio irq handling to prevent race */
2331 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2332 OMAP_HSMMC_WRITE(host->base, IE, 0);
f945901f
AF		 2333
2334 if (!(OMAP_HSMMC_READ(host->base, PSTATE) & DLEV_DAT(1))) {
2335 /*
2336 * dat1 line low, pending sdio irq
2337 * race condition: possible irq handler running on
2338 * multi-core, abort
2339 */
2340 dev_dbg(dev, "pending sdio irq, abort suspend\n");
2341 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2342 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2343 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
2344 pm_runtime_mark_last_busy(dev);
2345 ret = -EBUSY;
2346 goto abort;
2347 }
2cd3a2a5 2348
97978a44 2349 pinctrl_pm_select_idle_state(dev);
97978a44
AF		 2350 } else {
2351 pinctrl_pm_select_idle_state(dev);
2cd3a2a5 2352 }
97978a44 2353
f945901f 2354abort:
2cd3a2a5 2355 spin_unlock_irqrestore(&host->irq_lock, flags);
f945901f 2356 return ret;
fa4aa2d4
B		 2357}
2358
2359static int omap_hsmmc_runtime_resume(struct device *dev)
2360{
2361 struct omap_hsmmc_host *host;
2cd3a2a5 2362 unsigned long flags;
fa4aa2d4
B		 2363
2364 host = platform_get_drvdata(to_platform_device(dev));
2365 omap_hsmmc_context_restore(host);
927ce944 2366 dev_dbg(dev, "enabled\n");
fa4aa2d4 2367
2cd3a2a5
AF		 2368 spin_lock_irqsave(&host->irq_lock, flags);
2369 if ((host->mmc->caps & MMC_CAP_SDIO_IRQ) &&
2370 (host->flags & HSMMC_SDIO_IRQ_ENABLED)) {
2cd3a2a5 2371
97978a44
AF		 2372 pinctrl_pm_select_default_state(host->dev);
2373
2374 /* irq lost, if pinmux incorrect */
2cd3a2a5
AF		 2375 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
2376 OMAP_HSMMC_WRITE(host->base, ISE, CIRQ_EN);
2377 OMAP_HSMMC_WRITE(host->base, IE, CIRQ_EN);
97978a44
AF		 2378 } else {
2379 pinctrl_pm_select_default_state(host->dev);
2cd3a2a5
AF		 2380 }
2381 spin_unlock_irqrestore(&host->irq_lock, flags);
fa4aa2d4
B		 2382 return 0;
2383}
2384
a791daa1 2385static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
3d3bbfbd 2386 SET_SYSTEM_SLEEP_PM_OPS(omap_hsmmc_suspend, omap_hsmmc_resume)
fa4aa2d4
B		 2387 .runtime_suspend = omap_hsmmc_runtime_suspend,
2388 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2389};
2390
2391static struct platform_driver omap_hsmmc_driver = {
efa25fd3 2392 .probe = omap_hsmmc_probe,
0433c143 2393 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2394 .driver = {
2395 .name = DRIVER_NAME,
a791daa1 2396 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2397 .of_match_table = of_match_ptr(omap_mmc_of_match),
a45c6cb8
MC		 2398 },
2399};
2400
b796450b 2401module_platform_driver(omap_hsmmc_driver);
a45c6cb8
MC		 2402MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2403MODULE_LICENSE("GPL");
2404MODULE_ALIAS("platform:" DRIVER_NAME);
2405MODULE_AUTHOR("Texas Instruments Inc");
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