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mmc: omap_hsmmc: split duplicate code to calc_divisor() function
[mirror_ubuntu-artful-kernel.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712
DK		 21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
a45c6cb8
MC		 23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
27#include <linux/workqueue.h>
28#include <linux/timer.h>
29#include <linux/clk.h>
30#include <linux/mmc/host.h>
13189e78 31#include <linux/mmc/core.h>
93caf8e6 32#include <linux/mmc/mmc.h>
a45c6cb8
MC		 33#include <linux/io.h>
34#include <linux/semaphore.h>
db0fefc5
AH		 35#include <linux/gpio.h>
36#include <linux/regulator/consumer.h>
fa4aa2d4 37#include <linux/pm_runtime.h>
ce491cf8 38#include <plat/dma.h>
a45c6cb8 39#include <mach/hardware.h>
ce491cf8
TL		 40#include <plat/board.h>
41#include <plat/mmc.h>
42#include <plat/cpu.h>
a45c6cb8
MC		 43
44/* OMAP HSMMC Host Controller Registers */
45#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 46#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 47#define OMAP_HSMMC_CON 0x002C
48#define OMAP_HSMMC_BLK 0x0104
49#define OMAP_HSMMC_ARG 0x0108
50#define OMAP_HSMMC_CMD 0x010C
51#define OMAP_HSMMC_RSP10 0x0110
52#define OMAP_HSMMC_RSP32 0x0114
53#define OMAP_HSMMC_RSP54 0x0118
54#define OMAP_HSMMC_RSP76 0x011C
55#define OMAP_HSMMC_DATA 0x0120
56#define OMAP_HSMMC_HCTL 0x0128
57#define OMAP_HSMMC_SYSCTL 0x012C
58#define OMAP_HSMMC_STAT 0x0130
59#define OMAP_HSMMC_IE 0x0134
60#define OMAP_HSMMC_ISE 0x0138
61#define OMAP_HSMMC_CAPA 0x0140
62
63#define VS18 (1 << 26)
64#define VS30 (1 << 25)
65#define SDVS18 (0x5 << 9)
66#define SDVS30 (0x6 << 9)
eb250826 67#define SDVS33 (0x7 << 9)
1b331e69 68#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 69#define SDVSCLR 0xFFFFF1FF
70#define SDVSDET 0x00000400
71#define AUTOIDLE 0x1
72#define SDBP (1 << 8)
73#define DTO 0xe
74#define ICE 0x1
75#define ICS 0x2
76#define CEN (1 << 2)
77#define CLKD_MASK 0x0000FFC0
78#define CLKD_SHIFT 6
79#define DTO_MASK 0x000F0000
80#define DTO_SHIFT 16
81#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 82#define BWR_ENABLE (1 << 4)
83#define BRR_ENABLE (1 << 5)
93caf8e6 84#define DTO_ENABLE (1 << 20)
a45c6cb8
MC		 85#define INIT_STREAM (1 << 1)
86#define DP_SELECT (1 << 21)
87#define DDIR (1 << 4)
88#define DMA_EN 0x1
89#define MSBS (1 << 5)
90#define BCE (1 << 1)
91#define FOUR_BIT (1 << 1)
73153010 92#define DW8 (1 << 5)
a45c6cb8
MC		 93#define CC 0x1
94#define TC 0x02
95#define OD 0x1
96#define ERR (1 << 15)
97#define CMD_TIMEOUT (1 << 16)
98#define DATA_TIMEOUT (1 << 20)
99#define CMD_CRC (1 << 17)
100#define DATA_CRC (1 << 21)
101#define CARD_ERR (1 << 28)
102#define STAT_CLEAR 0xFFFFFFFF
103#define INIT_STREAM_CMD 0x00000000
104#define DUAL_VOLT_OCR_BIT 7
105#define SRC (1 << 25)
106#define SRD (1 << 26)
11dd62a7
DK		 107#define SOFTRESET (1 << 1)
108#define RESETDONE (1 << 0)
a45c6cb8
MC		 109
110/*
111 * FIXME: Most likely all the data using these _DEVID defines should come
112 * from the platform_data, or implemented in controller and slot specific
113 * functions.
114 */
115#define OMAP_MMC1_DEVID 0
116#define OMAP_MMC2_DEVID 1
f3e2f1dd 117#define OMAP_MMC3_DEVID 2
82cf818d 118#define OMAP_MMC4_DEVID 3
119#define OMAP_MMC5_DEVID 4
a45c6cb8 120
fa4aa2d4 121#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8
MC		 122#define MMC_TIMEOUT_MS 20
123#define OMAP_MMC_MASTER_CLOCK 96000000
6b206efe
AS		 124#define OMAP_MMC_MIN_CLOCK 400000
125#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 126#define DRIVER_NAME "omap_hsmmc"
a45c6cb8
MC		 127
128/*
129 * One controller can have multiple slots, like on some omap boards using
130 * omap.c controller driver. Luckily this is not currently done on any known
131 * omap_hsmmc.c device.
132 */
133#define mmc_slot(host) (host->pdata->slots[host->slot_id])
134
135/*
136 * MMC Host controller read/write API's
137 */
138#define OMAP_HSMMC_READ(base, reg) \
139 __raw_readl((base) + OMAP_HSMMC_##reg)
140
141#define OMAP_HSMMC_WRITE(base, reg, val) \
142 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
143
9782aff8
PF		 144struct omap_hsmmc_next {
145 unsigned int dma_len;
146 s32 cookie;
147};
148
70a3341a 149struct omap_hsmmc_host {
a45c6cb8
MC		 150 struct device *dev;
151 struct mmc_host *mmc;
152 struct mmc_request *mrq;
153 struct mmc_command *cmd;
154 struct mmc_data *data;
155 struct clk *fclk;
a45c6cb8 156 struct clk *dbclk;
db0fefc5
AH		 157 /*
158 * vcc == configured supply
159 * vcc_aux == optional
160 * - MMC1, supply for DAT4..DAT7
161 * - MMC2/MMC2, external level shifter voltage supply, for
162 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
163 */
164 struct regulator *vcc;
165 struct regulator *vcc_aux;
a45c6cb8
MC		 166 struct work_struct mmc_carddetect_work;
167 void __iomem *base;
168 resource_size_t mapbase;
4dffd7a2 169 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8
MC		 170 unsigned int id;
171 unsigned int dma_len;
0ccd76d4 172 unsigned int dma_sg_idx;
a45c6cb8 173 unsigned char bus_mode;
a3621465 174 unsigned char power_mode;
a45c6cb8
MC		 175 u32 *buffer;
176 u32 bytesleft;
177 int suspended;
178 int irq;
a45c6cb8 179 int use_dma, dma_ch;
f3e2f1dd 180 int dma_line_tx, dma_line_rx;
a45c6cb8 181 int slot_id;
2bec0893 182 int got_dbclk;
4a694dc9 183 int response_busy;
11dd62a7 184 int context_loss;
dd498eff 185 int dpm_state;
623821f7 186 int vdd;
b62f6228
AH		 187 int protect_card;
188 int reqs_blocked;
db0fefc5 189 int use_reg;
b417577d 190 int req_in_progress;
9782aff8 191 struct omap_hsmmc_next next_data;
11dd62a7 192
a45c6cb8
MC		 193 struct omap_mmc_platform_data *pdata;
194};
195
db0fefc5
AH		 196static int omap_hsmmc_card_detect(struct device *dev, int slot)
197{
198 struct omap_mmc_platform_data *mmc = dev->platform_data;
199
200 /* NOTE: assumes card detect signal is active-low */
201 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
202}
203
204static int omap_hsmmc_get_wp(struct device *dev, int slot)
205{
206 struct omap_mmc_platform_data *mmc = dev->platform_data;
207
208 /* NOTE: assumes write protect signal is active-high */
209 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
210}
211
212static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
213{
214 struct omap_mmc_platform_data *mmc = dev->platform_data;
215
216 /* NOTE: assumes card detect signal is active-low */
217 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
218}
219
220#ifdef CONFIG_PM
221
222static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
223{
224 struct omap_mmc_platform_data *mmc = dev->platform_data;
225
226 disable_irq(mmc->slots[0].card_detect_irq);
227 return 0;
228}
229
230static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
231{
232 struct omap_mmc_platform_data *mmc = dev->platform_data;
233
234 enable_irq(mmc->slots[0].card_detect_irq);
235 return 0;
236}
237
238#else
239
240#define omap_hsmmc_suspend_cdirq NULL
241#define omap_hsmmc_resume_cdirq NULL
242
243#endif
244
b702b106
AH		 245#ifdef CONFIG_REGULATOR
246
db0fefc5
AH		 247static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
248 int vdd)
249{
250 struct omap_hsmmc_host *host =
251 platform_get_drvdata(to_platform_device(dev));
252 int ret;
253
254 if (mmc_slot(host).before_set_reg)
255 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
256
257 if (power_on)
99fc5131 258 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5 259 else
99fc5131 260 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5
AH		 261
262 if (mmc_slot(host).after_set_reg)
263 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
264
265 return ret;
266}
267
7715db5a 268static int omap_hsmmc_235_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 269 int vdd)
270{
271 struct omap_hsmmc_host *host =
272 platform_get_drvdata(to_platform_device(dev));
273 int ret = 0;
274
275 /*
276 * If we don't see a Vcc regulator, assume it's a fixed
277 * voltage always-on regulator.
278 */
279 if (!host->vcc)
280 return 0;
281
282 if (mmc_slot(host).before_set_reg)
283 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
284
285 /*
286 * Assume Vcc regulator is used only to power the card ... OMAP
287 * VDDS is used to power the pins, optionally with a transceiver to
288 * support cards using voltages other than VDDS (1.8V nominal). When a
289 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
290 *
291 * In some cases this regulator won't support enable/disable;
292 * e.g. it's a fixed rail for a WLAN chip.
293 *
294 * In other cases vcc_aux switches interface power. Example, for
295 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
296 * chips/cards need an interface voltage rail too.
297 */
298 if (power_on) {
99fc5131 299 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 300 /* Enable interface voltage rail, if needed */
301 if (ret == 0 && host->vcc_aux) {
302 ret = regulator_enable(host->vcc_aux);
303 if (ret < 0)
99fc5131
LW		 304 ret = mmc_regulator_set_ocr(host->mmc,
305 host->vcc, 0);
db0fefc5
AH		 306 }
307 } else {
99fc5131 308 /* Shut down the rail */
6da20c89
AH		 309 if (host->vcc_aux)
310 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 311 if (!ret) {
312 /* Then proceed to shut down the local regulator */
313 ret = mmc_regulator_set_ocr(host->mmc,
314 host->vcc, 0);
315 }
db0fefc5
AH		 316 }
317
318 if (mmc_slot(host).after_set_reg)
319 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
320
321 return ret;
322}
323
7715db5a
KK		 324static int omap_hsmmc_4_set_power(struct device *dev, int slot, int power_on,
325 int vdd)
326{
327 return 0;
328}
329
db0fefc5
AH		 330static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
331 int vdd, int cardsleep)
332{
333 struct omap_hsmmc_host *host =
334 platform_get_drvdata(to_platform_device(dev));
335 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
336
337 return regulator_set_mode(host->vcc, mode);
338}
339
7715db5a 340static int omap_hsmmc_235_set_sleep(struct device *dev, int slot, int sleep,
db0fefc5
AH		 341 int vdd, int cardsleep)
342{
343 struct omap_hsmmc_host *host =
344 platform_get_drvdata(to_platform_device(dev));
345 int err, mode;
346
347 /*
348 * If we don't see a Vcc regulator, assume it's a fixed
349 * voltage always-on regulator.
350 */
351 if (!host->vcc)
352 return 0;
353
354 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
355
356 if (!host->vcc_aux)
357 return regulator_set_mode(host->vcc, mode);
358
359 if (cardsleep) {
360 /* VCC can be turned off if card is asleep */
361 if (sleep)
99fc5131 362 err = mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
db0fefc5 363 else
99fc5131 364 err = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 365 } else
366 err = regulator_set_mode(host->vcc, mode);
367 if (err)
368 return err;
e0eb2424
AH		 369
370 if (!mmc_slot(host).vcc_aux_disable_is_sleep)
371 return regulator_set_mode(host->vcc_aux, mode);
372
373 if (sleep)
374 return regulator_disable(host->vcc_aux);
375 else
376 return regulator_enable(host->vcc_aux);
db0fefc5
AH		 377}
378
7715db5a
KK		 379static int omap_hsmmc_4_set_sleep(struct device *dev, int slot, int sleep,
380 int vdd, int cardsleep)
381{
382 return 0;
383}
384
db0fefc5
AH		 385static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
386{
387 struct regulator *reg;
388 int ret = 0;
64be9782 389 int ocr_value = 0;
db0fefc5
AH		 390
391 switch (host->id) {
392 case OMAP_MMC1_DEVID:
393 /* On-chip level shifting via PBIAS0/PBIAS1 */
394 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
395 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
396 break;
397 case OMAP_MMC2_DEVID:
398 case OMAP_MMC3_DEVID:
7715db5a 399 case OMAP_MMC5_DEVID:
db0fefc5 400 /* Off-chip level shifting, or none */
7715db5a
KK		 401 mmc_slot(host).set_power = omap_hsmmc_235_set_power;
402 mmc_slot(host).set_sleep = omap_hsmmc_235_set_sleep;
db0fefc5 403 break;
7715db5a
KK		 404 case OMAP_MMC4_DEVID:
405 mmc_slot(host).set_power = omap_hsmmc_4_set_power;
406 mmc_slot(host).set_sleep = omap_hsmmc_4_set_sleep;
db0fefc5
AH		 407 default:
408 pr_err("MMC%d configuration not supported!\n", host->id);
409 return -EINVAL;
410 }
411
412 reg = regulator_get(host->dev, "vmmc");
413 if (IS_ERR(reg)) {
414 dev_dbg(host->dev, "vmmc regulator missing\n");
415 /*
416 * HACK: until fixed.c regulator is usable,
417 * we don't require a main regulator
418 * for MMC2 or MMC3
419 */
420 if (host->id == OMAP_MMC1_DEVID) {
421 ret = PTR_ERR(reg);
422 goto err;
423 }
424 } else {
425 host->vcc = reg;
64be9782 426 ocr_value = mmc_regulator_get_ocrmask(reg);
427 if (!mmc_slot(host).ocr_mask) {
428 mmc_slot(host).ocr_mask = ocr_value;
429 } else {
430 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
431 pr_err("MMC%d ocrmask %x is not supported\n",
432 host->id, mmc_slot(host).ocr_mask);
433 mmc_slot(host).ocr_mask = 0;
434 return -EINVAL;
435 }
436 }
db0fefc5
AH		 437
438 /* Allow an aux regulator */
439 reg = regulator_get(host->dev, "vmmc_aux");
440 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
441
b1c1df7a
B		 442 /* For eMMC do not power off when not in sleep state */
443 if (mmc_slot(host).no_regulator_off_init)
444 return 0;
db0fefc5
AH		 445 /*
446 * UGLY HACK: workaround regulator framework bugs.
447 * When the bootloader leaves a supply active, it's
448 * initialized with zero usecount ... and we can't
449 * disable it without first enabling it. Until the
450 * framework is fixed, we need a workaround like this
451 * (which is safe for MMC, but not in general).
452 */
453 if (regulator_is_enabled(host->vcc) > 0) {
454 regulator_enable(host->vcc);
455 regulator_disable(host->vcc);
456 }
457 if (host->vcc_aux) {
458 if (regulator_is_enabled(reg) > 0) {
459 regulator_enable(reg);
460 regulator_disable(reg);
461 }
462 }
463 }
464
465 return 0;
466
467err:
468 mmc_slot(host).set_power = NULL;
469 mmc_slot(host).set_sleep = NULL;
470 return ret;
471}
472
473static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
474{
475 regulator_put(host->vcc);
476 regulator_put(host->vcc_aux);
477 mmc_slot(host).set_power = NULL;
478 mmc_slot(host).set_sleep = NULL;
479}
480
b702b106
AH		 481static inline int omap_hsmmc_have_reg(void)
482{
483 return 1;
484}
485
486#else
487
488static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
489{
490 return -EINVAL;
491}
492
493static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
494{
495}
496
497static inline int omap_hsmmc_have_reg(void)
498{
499 return 0;
500}
501
502#endif
503
504static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
505{
506 int ret;
507
508 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 509 if (pdata->slots[0].cover)
510 pdata->slots[0].get_cover_state =
511 omap_hsmmc_get_cover_state;
512 else
513 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
514 pdata->slots[0].card_detect_irq =
515 gpio_to_irq(pdata->slots[0].switch_pin);
516 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
517 if (ret)
518 return ret;
519 ret = gpio_direction_input(pdata->slots[0].switch_pin);
520 if (ret)
521 goto err_free_sp;
522 } else
523 pdata->slots[0].switch_pin = -EINVAL;
524
525 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
526 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
527 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
528 if (ret)
529 goto err_free_cd;
530 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
531 if (ret)
532 goto err_free_wp;
533 } else
534 pdata->slots[0].gpio_wp = -EINVAL;
535
536 return 0;
537
538err_free_wp:
539 gpio_free(pdata->slots[0].gpio_wp);
540err_free_cd:
541 if (gpio_is_valid(pdata->slots[0].switch_pin))
542err_free_sp:
543 gpio_free(pdata->slots[0].switch_pin);
544 return ret;
545}
546
547static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
548{
549 if (gpio_is_valid(pdata->slots[0].gpio_wp))
550 gpio_free(pdata->slots[0].gpio_wp);
551 if (gpio_is_valid(pdata->slots[0].switch_pin))
552 gpio_free(pdata->slots[0].switch_pin);
553}
554
a45c6cb8
MC		 555/*
556 * Stop clock to the card
557 */
70a3341a 558static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 559{
560 OMAP_HSMMC_WRITE(host->base, SYSCTL,
561 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
562 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
563 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
564}
565
93caf8e6
AH		 566static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
567 struct mmc_command *cmd)
b417577d
AH		 568{
569 unsigned int irq_mask;
570
571 if (host->use_dma)
572 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
573 else
574 irq_mask = INT_EN_MASK;
575
93caf8e6
AH		 576 /* Disable timeout for erases */
577 if (cmd->opcode == MMC_ERASE)
578 irq_mask &= ~DTO_ENABLE;
579
b417577d
AH		 580 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
581 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
582 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
583}
584
585static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
586{
587 OMAP_HSMMC_WRITE(host->base, ISE, 0);
588 OMAP_HSMMC_WRITE(host->base, IE, 0);
589 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
590}
591
ac330f44
AS		 592/* Calculate divisor for the given clock frequency */
593static u16 calc_divisor(struct mmc_ios *ios)
594{
595 u16 dsor = 0;
596
597 if (ios->clock) {
598 dsor = DIV_ROUND_UP(OMAP_MMC_MASTER_CLOCK, ios->clock);
599 if (dsor > 250)
600 dsor = 250;
601 }
602
603 return dsor;
604}
605
11dd62a7
DK		 606#ifdef CONFIG_PM
607
608/*
609 * Restore the MMC host context, if it was lost as result of a
610 * power state change.
611 */
70a3341a 612static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 613{
614 struct mmc_ios *ios = &host->mmc->ios;
615 struct omap_mmc_platform_data *pdata = host->pdata;
616 int context_loss = 0;
617 u32 hctl, capa, con;
11dd62a7
DK		 618 unsigned long timeout;
619
620 if (pdata->get_context_loss_count) {
621 context_loss = pdata->get_context_loss_count(host->dev);
622 if (context_loss < 0)
623 return 1;
624 }
625
626 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
627 context_loss == host->context_loss ? "not " : "");
628 if (host->context_loss == context_loss)
629 return 1;
630
631 /* Wait for hardware reset */
632 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
633 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
634 && time_before(jiffies, timeout))
635 ;
636
637 /* Do software reset */
638 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
639 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
640 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
641 && time_before(jiffies, timeout))
642 ;
643
644 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
645 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
646
647 if (host->id == OMAP_MMC1_DEVID) {
648 if (host->power_mode != MMC_POWER_OFF &&
649 (1 << ios->vdd) <= MMC_VDD_23_24)
650 hctl = SDVS18;
651 else
652 hctl = SDVS30;
653 capa = VS30 | VS18;
654 } else {
655 hctl = SDVS18;
656 capa = VS18;
657 }
658
659 OMAP_HSMMC_WRITE(host->base, HCTL,
660 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
661
662 OMAP_HSMMC_WRITE(host->base, CAPA,
663 OMAP_HSMMC_READ(host->base, CAPA) | capa);
664
665 OMAP_HSMMC_WRITE(host->base, HCTL,
666 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
667
668 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
669 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
670 && time_before(jiffies, timeout))
671 ;
672
b417577d 673 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 674
675 /* Do not initialize card-specific things if the power is off */
676 if (host->power_mode == MMC_POWER_OFF)
677 goto out;
678
679 con = OMAP_HSMMC_READ(host->base, CON);
680 switch (ios->bus_width) {
681 case MMC_BUS_WIDTH_8:
682 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
683 break;
684 case MMC_BUS_WIDTH_4:
685 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
686 OMAP_HSMMC_WRITE(host->base, HCTL,
687 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
688 break;
689 case MMC_BUS_WIDTH_1:
690 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
691 OMAP_HSMMC_WRITE(host->base, HCTL,
692 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
693 break;
694 }
695
11dd62a7
DK		 696 OMAP_HSMMC_WRITE(host->base, SYSCTL,
697 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
ac330f44
AS		 698 OMAP_HSMMC_WRITE(host->base, SYSCTL,
699 (calc_divisor(ios) << 6) | (DTO << 16));
11dd62a7
DK		 700 OMAP_HSMMC_WRITE(host->base, SYSCTL,
701 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
702
703 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
704 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
705 && time_before(jiffies, timeout))
706 ;
707
708 OMAP_HSMMC_WRITE(host->base, SYSCTL,
709 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
710
711 con = OMAP_HSMMC_READ(host->base, CON);
712 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
713 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
714 else
715 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
716out:
717 host->context_loss = context_loss;
718
719 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
720 return 0;
721}
722
723/*
724 * Save the MMC host context (store the number of power state changes so far).
725 */
70a3341a 726static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 727{
728 struct omap_mmc_platform_data *pdata = host->pdata;
729 int context_loss;
730
731 if (pdata->get_context_loss_count) {
732 context_loss = pdata->get_context_loss_count(host->dev);
733 if (context_loss < 0)
734 return;
735 host->context_loss = context_loss;
736 }
737}
738
739#else
740
70a3341a 741static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 742{
743 return 0;
744}
745
70a3341a 746static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 747{
748}
749
750#endif
751
a45c6cb8
MC		 752/*
753 * Send init stream sequence to card
754 * before sending IDLE command
755 */
70a3341a 756static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 757{
758 int reg = 0;
759 unsigned long timeout;
760
b62f6228
AH		 761 if (host->protect_card)
762 return;
763
a45c6cb8 764 disable_irq(host->irq);
b417577d
AH		 765
766 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 767 OMAP_HSMMC_WRITE(host->base, CON,
768 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
769 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
770
771 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
772 while ((reg != CC) && time_before(jiffies, timeout))
773 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
774
775 OMAP_HSMMC_WRITE(host->base, CON,
776 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 777
778 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
779 OMAP_HSMMC_READ(host->base, STAT);
780
a45c6cb8
MC		 781 enable_irq(host->irq);
782}
783
784static inline
70a3341a 785int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 786{
787 int r = 1;
788
191d1f1d
DK		 789 if (mmc_slot(host).get_cover_state)
790 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 791 return r;
792}
793
794static ssize_t
70a3341a 795omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 796 char *buf)
797{
798 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 799 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 800
70a3341a
DK		 801 return sprintf(buf, "%s\n",
802 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 803}
804
70a3341a 805static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 806
807static ssize_t
70a3341a 808omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 809 char *buf)
810{
811 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 812 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 813
191d1f1d 814 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 815}
816
70a3341a 817static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 818
819/*
820 * Configure the response type and send the cmd.
821 */
822static void
70a3341a 823omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 824 struct mmc_data *data)
825{
826 int cmdreg = 0, resptype = 0, cmdtype = 0;
827
828 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
829 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
830 host->cmd = cmd;
831
93caf8e6 832 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 833
4a694dc9 834 host->response_busy = 0;
a45c6cb8
MC		 835 if (cmd->flags & MMC_RSP_PRESENT) {
836 if (cmd->flags & MMC_RSP_136)
837 resptype = 1;
4a694dc9
AH		 838 else if (cmd->flags & MMC_RSP_BUSY) {
839 resptype = 3;
840 host->response_busy = 1;
841 } else
a45c6cb8
MC		 842 resptype = 2;
843 }
844
845 /*
846 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
847 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
848 * a val of 0x3, rest 0x0.
849 */
850 if (cmd == host->mrq->stop)
851 cmdtype = 0x3;
852
853 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
854
855 if (data) {
856 cmdreg |= DP_SELECT | MSBS | BCE;
857 if (data->flags & MMC_DATA_READ)
858 cmdreg |= DDIR;
859 else
860 cmdreg &= ~(DDIR);
861 }
862
863 if (host->use_dma)
864 cmdreg |= DMA_EN;
865
b417577d 866 host->req_in_progress = 1;
4dffd7a2 867
a45c6cb8
MC		 868 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
869 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
870}
871
0ccd76d4 872static int
70a3341a 873omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 874{
875 if (data->flags & MMC_DATA_WRITE)
876 return DMA_TO_DEVICE;
877 else
878 return DMA_FROM_DEVICE;
879}
880
b417577d
AH		 881static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
882{
883 int dma_ch;
884
885 spin_lock(&host->irq_lock);
886 host->req_in_progress = 0;
887 dma_ch = host->dma_ch;
888 spin_unlock(&host->irq_lock);
889
890 omap_hsmmc_disable_irq(host);
891 /* Do not complete the request if DMA is still in progress */
892 if (mrq->data && host->use_dma && dma_ch != -1)
893 return;
894 host->mrq = NULL;
895 mmc_request_done(host->mmc, mrq);
896}
897
a45c6cb8
MC		 898/*
899 * Notify the transfer complete to MMC core
900 */
901static void
70a3341a 902omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 903{
4a694dc9
AH		 904 if (!data) {
905 struct mmc_request *mrq = host->mrq;
906
23050103
AH		 907 /* TC before CC from CMD6 - don't know why, but it happens */
908 if (host->cmd && host->cmd->opcode == 6 &&
909 host->response_busy) {
910 host->response_busy = 0;
911 return;
912 }
913
b417577d 914 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 915 return;
916 }
917
a45c6cb8
MC		 918 host->data = NULL;
919
a45c6cb8
MC		 920 if (!data->error)
921 data->bytes_xfered += data->blocks * (data->blksz);
922 else
923 data->bytes_xfered = 0;
924
925 if (!data->stop) {
b417577d 926 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8
MC		 927 return;
928 }
70a3341a 929 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 930}
931
932/*
933 * Notify the core about command completion
934 */
935static void
70a3341a 936omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 937{
938 host->cmd = NULL;
939
940 if (cmd->flags & MMC_RSP_PRESENT) {
941 if (cmd->flags & MMC_RSP_136) {
942 /* response type 2 */
943 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
944 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
945 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
946 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
947 } else {
948 /* response types 1, 1b, 3, 4, 5, 6 */
949 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
950 }
951 }
b417577d
AH		 952 if ((host->data == NULL && !host->response_busy) || cmd->error)
953 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 954}
955
956/*
957 * DMA clean up for command errors
958 */
70a3341a 959static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 960{
b417577d
AH		 961 int dma_ch;
962
82788ff5 963 host->data->error = errno;
a45c6cb8 964
b417577d
AH		 965 spin_lock(&host->irq_lock);
966 dma_ch = host->dma_ch;
967 host->dma_ch = -1;
968 spin_unlock(&host->irq_lock);
969
970 if (host->use_dma && dma_ch != -1) {
a9120c33
PF		 971 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
972 host->data->sg_len,
70a3341a 973 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 974 omap_free_dma(dma_ch);
a45c6cb8
MC		 975 }
976 host->data = NULL;
a45c6cb8
MC		 977}
978
979/*
980 * Readable error output
981 */
982#ifdef CONFIG_MMC_DEBUG
699b958b 983static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 984{
985 /* --- means reserved bit without definition at documentation */
70a3341a 986 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 987 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
988 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
989 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
990 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 991 };
992 char res[256];
993 char *buf = res;
994 int len, i;
995
996 len = sprintf(buf, "MMC IRQ 0x%x :", status);
997 buf += len;
998
70a3341a 999 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 1000 if (status & (1 << i)) {
70a3341a 1001 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 1002 buf += len;
1003 }
1004
1005 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
1006}
699b958b
AH		 1007#else
1008static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
1009 u32 status)
1010{
1011}
a45c6cb8
MC		 1012#endif /* CONFIG_MMC_DEBUG */
1013
3ebf74b1
JP		 1014/*
1015 * MMC controller internal state machines reset
1016 *
1017 * Used to reset command or data internal state machines, using respectively
1018 * SRC or SRD bit of SYSCTL register
1019 * Can be called from interrupt context
1020 */
70a3341a
DK		 1021static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
1022 unsigned long bit)
3ebf74b1
JP		 1023{
1024 unsigned long i = 0;
1025 unsigned long limit = (loops_per_jiffy *
1026 msecs_to_jiffies(MMC_TIMEOUT_MS));
1027
1028 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1029 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
1030
07ad64b6
MC		 1031 /*
1032 * OMAP4 ES2 and greater has an updated reset logic.
1033 * Monitor a 0->1 transition first
1034 */
1035 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 1036 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 1037 && (i++ < limit))
1038 cpu_relax();
1039 }
1040 i = 0;
1041
3ebf74b1
JP		 1042 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
1043 (i++ < limit))
1044 cpu_relax();
1045
1046 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
1047 dev_err(mmc_dev(host->mmc),
1048 "Timeout waiting on controller reset in %s\n",
1049 __func__);
1050}
a45c6cb8 1051
b417577d 1052static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 1053{
a45c6cb8 1054 struct mmc_data *data;
b417577d
AH		 1055 int end_cmd = 0, end_trans = 0;
1056
1057 if (!host->req_in_progress) {
1058 do {
1059 OMAP_HSMMC_WRITE(host->base, STAT, status);
1060 /* Flush posted write */
1061 status = OMAP_HSMMC_READ(host->base, STAT);
1062 } while (status & INT_EN_MASK);
1063 return;
a45c6cb8
MC		 1064 }
1065
1066 data = host->data;
a45c6cb8
MC		 1067 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
1068
1069 if (status & ERR) {
699b958b 1070 omap_hsmmc_dbg_report_irq(host, status);
a45c6cb8
MC		 1071 if ((status & CMD_TIMEOUT) ||
1072 (status & CMD_CRC)) {
1073 if (host->cmd) {
1074 if (status & CMD_TIMEOUT) {
70a3341a
DK		 1075 omap_hsmmc_reset_controller_fsm(host,
1076 SRC);
a45c6cb8
MC		 1077 host->cmd->error = -ETIMEDOUT;
1078 } else {
1079 host->cmd->error = -EILSEQ;
1080 }
1081 end_cmd = 1;
1082 }
4a694dc9
AH		 1083 if (host->data || host->response_busy) {
1084 if (host->data)
70a3341a
DK		 1085 omap_hsmmc_dma_cleanup(host,
1086 -ETIMEDOUT);
4a694dc9 1087 host->response_busy = 0;
70a3341a 1088 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1089 }
a45c6cb8
MC		 1090 }
1091 if ((status & DATA_TIMEOUT) ||
1092 (status & DATA_CRC)) {
4a694dc9
AH		 1093 if (host->data || host->response_busy) {
1094 int err = (status & DATA_TIMEOUT) ?
1095 -ETIMEDOUT : -EILSEQ;
1096
1097 if (host->data)
70a3341a 1098 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1099 else
4a694dc9
AH		 1100 host->mrq->cmd->error = err;
1101 host->response_busy = 0;
70a3341a 1102 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1103 end_trans = 1;
1104 }
1105 }
1106 if (status & CARD_ERR) {
1107 dev_dbg(mmc_dev(host->mmc),
1108 "Ignoring card err CMD%d\n", host->cmd->opcode);
1109 if (host->cmd)
1110 end_cmd = 1;
1111 if (host->data)
1112 end_trans = 1;
1113 }
1114 }
1115
1116 OMAP_HSMMC_WRITE(host->base, STAT, status);
1117
a8fe29d8 1118 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1119 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1120 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1121 omap_hsmmc_xfer_done(host, data);
b417577d 1122}
a45c6cb8 1123
b417577d
AH		 1124/*
1125 * MMC controller IRQ handler
1126 */
1127static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1128{
1129 struct omap_hsmmc_host *host = dev_id;
1130 int status;
1131
1132 status = OMAP_HSMMC_READ(host->base, STAT);
1133 do {
1134 omap_hsmmc_do_irq(host, status);
1135 /* Flush posted write */
1136 status = OMAP_HSMMC_READ(host->base, STAT);
1137 } while (status & INT_EN_MASK);
4dffd7a2 1138
a45c6cb8
MC		 1139 return IRQ_HANDLED;
1140}
1141
70a3341a 1142static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1143{
1144 unsigned long i;
1145
1146 OMAP_HSMMC_WRITE(host->base, HCTL,
1147 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1148 for (i = 0; i < loops_per_jiffy; i++) {
1149 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1150 break;
1151 cpu_relax();
1152 }
1153}
1154
a45c6cb8 1155/*
eb250826
DB		 1156 * Switch MMC interface voltage ... only relevant for MMC1.
1157 *
1158 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1159 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1160 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1161 */
70a3341a 1162static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1163{
1164 u32 reg_val = 0;
1165 int ret;
1166
1167 /* Disable the clocks */
fa4aa2d4 1168 pm_runtime_put_sync(host->dev);
2bec0893
AH		 1169 if (host->got_dbclk)
1170 clk_disable(host->dbclk);
a45c6cb8
MC		 1171
1172 /* Turn the power off */
1173 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1174
1175 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1176 if (!ret)
1177 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1178 vdd);
fa4aa2d4 1179 pm_runtime_get_sync(host->dev);
2bec0893
AH		 1180 if (host->got_dbclk)
1181 clk_enable(host->dbclk);
1182
a45c6cb8
MC		 1183 if (ret != 0)
1184 goto err;
1185
a45c6cb8
MC		 1186 OMAP_HSMMC_WRITE(host->base, HCTL,
1187 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1188 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1189
a45c6cb8
MC		 1190 /*
1191 * If a MMC dual voltage card is detected, the set_ios fn calls
1192 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1193 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1194 *
eb250826
DB		 1195 * Cope with a bit of slop in the range ... per data sheets:
1196 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1197 * but recommended values are 1.71V to 1.89V
1198 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1199 * but recommended values are 2.7V to 3.3V
1200 *
1201 * Board setup code shouldn't permit anything very out-of-range.
1202 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1203 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1204 */
eb250826 1205 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1206 reg_val |= SDVS18;
eb250826
DB		 1207 else
1208 reg_val |= SDVS30;
a45c6cb8
MC		 1209
1210 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1211 set_sd_bus_power(host);
a45c6cb8
MC		 1212
1213 return 0;
1214err:
1215 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1216 return ret;
1217}
1218
b62f6228
AH		 1219/* Protect the card while the cover is open */
1220static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1221{
1222 if (!mmc_slot(host).get_cover_state)
1223 return;
1224
1225 host->reqs_blocked = 0;
1226 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1227 if (host->protect_card) {
1228 printk(KERN_INFO "%s: cover is closed, "
1229 "card is now accessible\n",
1230 mmc_hostname(host->mmc));
1231 host->protect_card = 0;
1232 }
1233 } else {
1234 if (!host->protect_card) {
1235 printk(KERN_INFO "%s: cover is open, "
1236 "card is now inaccessible\n",
1237 mmc_hostname(host->mmc));
1238 host->protect_card = 1;
1239 }
1240 }
1241}
1242
a45c6cb8
MC		 1243/*
1244 * Work Item to notify the core about card insertion/removal
1245 */
70a3341a 1246static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1247{
70a3341a
DK		 1248 struct omap_hsmmc_host *host =
1249 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1250 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1251 int carddetect;
1252
1253 if (host->suspended)
1254 return;
1255
1256 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1257
191d1f1d 1258 if (slot->card_detect)
db0fefc5 1259 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1260 else {
1261 omap_hsmmc_protect_card(host);
a6b2240d 1262 carddetect = -ENOSYS;
b62f6228 1263 }
a45c6cb8 1264
cdeebadd 1265 if (carddetect)
a45c6cb8 1266 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1267 else
a45c6cb8 1268 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1269}
1270
1271/*
1272 * ISR for handling card insertion and removal
1273 */
70a3341a 1274static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1275{
70a3341a 1276 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1277
a6b2240d
AH		 1278 if (host->suspended)
1279 return IRQ_HANDLED;
a45c6cb8
MC		 1280 schedule_work(&host->mmc_carddetect_work);
1281
1282 return IRQ_HANDLED;
1283}
1284
70a3341a 1285static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1286 struct mmc_data *data)
1287{
1288 int sync_dev;
1289
f3e2f1dd
GI		 1290 if (data->flags & MMC_DATA_WRITE)
1291 sync_dev = host->dma_line_tx;
1292 else
1293 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1294 return sync_dev;
1295}
1296
70a3341a 1297static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1298 struct mmc_data *data,
1299 struct scatterlist *sgl)
1300{
1301 int blksz, nblk, dma_ch;
1302
1303 dma_ch = host->dma_ch;
1304 if (data->flags & MMC_DATA_WRITE) {
1305 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1306 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1307 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1308 sg_dma_address(sgl), 0, 0);
1309 } else {
1310 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1311 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1312 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1313 sg_dma_address(sgl), 0, 0);
1314 }
1315
1316 blksz = host->data->blksz;
1317 nblk = sg_dma_len(sgl) / blksz;
1318
1319 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1320 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1321 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1322 !(data->flags & MMC_DATA_WRITE));
1323
1324 omap_start_dma(dma_ch);
1325}
1326
a45c6cb8
MC		 1327/*
1328 * DMA call back function
1329 */
b417577d 1330static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1331{
b417577d
AH		 1332 struct omap_hsmmc_host *host = cb_data;
1333 struct mmc_data *data = host->mrq->data;
1334 int dma_ch, req_in_progress;
a45c6cb8 1335
f3584e5e
V		 1336 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1337 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1338 ch_status);
1339 return;
1340 }
a45c6cb8 1341
b417577d
AH		 1342 spin_lock(&host->irq_lock);
1343 if (host->dma_ch < 0) {
1344 spin_unlock(&host->irq_lock);
a45c6cb8 1345 return;
b417577d 1346 }
a45c6cb8 1347
0ccd76d4
JY		 1348 host->dma_sg_idx++;
1349 if (host->dma_sg_idx < host->dma_len) {
1350 /* Fire up the next transfer. */
b417577d
AH		 1351 omap_hsmmc_config_dma_params(host, data,
1352 data->sg + host->dma_sg_idx);
1353 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1354 return;
1355 }
1356
9782aff8
PF		 1357 if (!data->host_cookie)
1358 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1359 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1360
1361 req_in_progress = host->req_in_progress;
1362 dma_ch = host->dma_ch;
a45c6cb8 1363 host->dma_ch = -1;
b417577d
AH		 1364 spin_unlock(&host->irq_lock);
1365
1366 omap_free_dma(dma_ch);
1367
1368 /* If DMA has finished after TC, complete the request */
1369 if (!req_in_progress) {
1370 struct mmc_request *mrq = host->mrq;
1371
1372 host->mrq = NULL;
1373 mmc_request_done(host->mmc, mrq);
1374 }
a45c6cb8
MC		 1375}
1376
9782aff8
PF		 1377static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1378 struct mmc_data *data,
1379 struct omap_hsmmc_next *next)
1380{
1381 int dma_len;
1382
1383 if (!next && data->host_cookie &&
1384 data->host_cookie != host->next_data.cookie) {
1385 printk(KERN_WARNING "[%s] invalid cookie: data->host_cookie %d"
1386 " host->next_data.cookie %d\n",
1387 __func__, data->host_cookie, host->next_data.cookie);
1388 data->host_cookie = 0;
1389 }
1390
1391 /* Check if next job is already prepared */
1392 if (next ||
1393 (!next && data->host_cookie != host->next_data.cookie)) {
1394 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1395 data->sg_len,
1396 omap_hsmmc_get_dma_dir(host, data));
1397
1398 } else {
1399 dma_len = host->next_data.dma_len;
1400 host->next_data.dma_len = 0;
1401 }
1402
1403
1404 if (dma_len == 0)
1405 return -EINVAL;
1406
1407 if (next) {
1408 next->dma_len = dma_len;
1409 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1410 } else
1411 host->dma_len = dma_len;
1412
1413 return 0;
1414}
1415
a45c6cb8
MC		 1416/*
1417 * Routine to configure and start DMA for the MMC card
1418 */
70a3341a
DK		 1419static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1420 struct mmc_request *req)
a45c6cb8 1421{
b417577d 1422 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1423 struct mmc_data *data = req->data;
1424
0ccd76d4 1425 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1426 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1427 struct scatterlist *sgl;
1428
1429 sgl = data->sg + i;
1430 if (sgl->length % data->blksz)
1431 return -EINVAL;
1432 }
1433 if ((data->blksz % 4) != 0)
1434 /* REVISIT: The MMC buffer increments only when MSB is written.
1435 * Return error for blksz which is non multiple of four.
1436 */
1437 return -EINVAL;
1438
b417577d 1439 BUG_ON(host->dma_ch != -1);
a45c6cb8 1440
70a3341a
DK		 1441 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1442 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1443 if (ret != 0) {
0ccd76d4 1444 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1445 "%s: omap_request_dma() failed with %d\n",
1446 mmc_hostname(host->mmc), ret);
1447 return ret;
1448 }
9782aff8
PF		 1449 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1450 if (ret)
1451 return ret;
a45c6cb8 1452
a45c6cb8 1453 host->dma_ch = dma_ch;
0ccd76d4 1454 host->dma_sg_idx = 0;
a45c6cb8 1455
70a3341a 1456 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1457
a45c6cb8
MC		 1458 return 0;
1459}
1460
70a3341a 1461static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1462 unsigned int timeout_ns,
1463 unsigned int timeout_clks)
a45c6cb8
MC		 1464{
1465 unsigned int timeout, cycle_ns;
1466 uint32_t reg, clkd, dto = 0;
1467
1468 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1469 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1470 if (clkd == 0)
1471 clkd = 1;
1472
1473 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1474 timeout = timeout_ns / cycle_ns;
1475 timeout += timeout_clks;
a45c6cb8
MC		 1476 if (timeout) {
1477 while ((timeout & 0x80000000) == 0) {
1478 dto += 1;
1479 timeout <<= 1;
1480 }
1481 dto = 31 - dto;
1482 timeout <<= 1;
1483 if (timeout && dto)
1484 dto += 1;
1485 if (dto >= 13)
1486 dto -= 13;
1487 else
1488 dto = 0;
1489 if (dto > 14)
1490 dto = 14;
1491 }
1492
1493 reg &= ~DTO_MASK;
1494 reg |= dto << DTO_SHIFT;
1495 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1496}
1497
1498/*
1499 * Configure block length for MMC/SD cards and initiate the transfer.
1500 */
1501static int
70a3341a 1502omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1503{
1504 int ret;
1505 host->data = req->data;
1506
1507 if (req->data == NULL) {
a45c6cb8 1508 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1509 /*
1510 * Set an arbitrary 100ms data timeout for commands with
1511 * busy signal.
1512 */
1513 if (req->cmd->flags & MMC_RSP_BUSY)
1514 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1515 return 0;
1516 }
1517
1518 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1519 | (req->data->blocks << 16));
e2bf08d6 1520 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1521
a45c6cb8 1522 if (host->use_dma) {
70a3341a 1523 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1524 if (ret != 0) {
1525 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1526 return ret;
1527 }
1528 }
1529 return 0;
1530}
1531
9782aff8
PF		 1532static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1533 int err)
1534{
1535 struct omap_hsmmc_host *host = mmc_priv(mmc);
1536 struct mmc_data *data = mrq->data;
1537
1538 if (host->use_dma) {
1539 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1540 omap_hsmmc_get_dma_dir(host, data));
1541 data->host_cookie = 0;
1542 }
1543}
1544
1545static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1546 bool is_first_req)
1547{
1548 struct omap_hsmmc_host *host = mmc_priv(mmc);
1549
1550 if (mrq->data->host_cookie) {
1551 mrq->data->host_cookie = 0;
1552 return ;
1553 }
1554
1555 if (host->use_dma)
1556 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1557 &host->next_data))
1558 mrq->data->host_cookie = 0;
1559}
1560
a45c6cb8
MC		 1561/*
1562 * Request function. for read/write operation
1563 */
70a3341a 1564static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1565{
70a3341a 1566 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1567 int err;
a45c6cb8 1568
b417577d
AH		 1569 BUG_ON(host->req_in_progress);
1570 BUG_ON(host->dma_ch != -1);
1571 if (host->protect_card) {
1572 if (host->reqs_blocked < 3) {
1573 /*
1574 * Ensure the controller is left in a consistent
1575 * state by resetting the command and data state
1576 * machines.
1577 */
1578 omap_hsmmc_reset_controller_fsm(host, SRD);
1579 omap_hsmmc_reset_controller_fsm(host, SRC);
1580 host->reqs_blocked += 1;
1581 }
1582 req->cmd->error = -EBADF;
1583 if (req->data)
1584 req->data->error = -EBADF;
1585 req->cmd->retries = 0;
1586 mmc_request_done(mmc, req);
1587 return;
1588 } else if (host->reqs_blocked)
1589 host->reqs_blocked = 0;
a45c6cb8
MC		 1590 WARN_ON(host->mrq != NULL);
1591 host->mrq = req;
70a3341a 1592 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1593 if (err) {
1594 req->cmd->error = err;
1595 if (req->data)
1596 req->data->error = err;
1597 host->mrq = NULL;
1598 mmc_request_done(mmc, req);
1599 return;
1600 }
1601
70a3341a 1602 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1603}
1604
a45c6cb8 1605/* Routine to configure clock values. Exposed API to core */
70a3341a 1606static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1607{
70a3341a 1608 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8
MC		 1609 unsigned long regval;
1610 unsigned long timeout;
73153010 1611 u32 con;
a3621465 1612 int do_send_init_stream = 0;
a45c6cb8 1613
fa4aa2d4 1614 pm_runtime_get_sync(host->dev);
5e2ea617 1615
a3621465
AH		 1616 if (ios->power_mode != host->power_mode) {
1617 switch (ios->power_mode) {
1618 case MMC_POWER_OFF:
1619 mmc_slot(host).set_power(host->dev, host->slot_id,
1620 0, 0);
623821f7 1621 host->vdd = 0;
a3621465
AH		 1622 break;
1623 case MMC_POWER_UP:
1624 mmc_slot(host).set_power(host->dev, host->slot_id,
1625 1, ios->vdd);
623821f7 1626 host->vdd = ios->vdd;
a3621465
AH		 1627 break;
1628 case MMC_POWER_ON:
1629 do_send_init_stream = 1;
1630 break;
1631 }
1632 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1633 }
1634
dd498eff
DK		 1635 /* FIXME: set registers based only on changes to ios */
1636
73153010 1637 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1638 switch (mmc->ios.bus_width) {
73153010
JL		 1639 case MMC_BUS_WIDTH_8:
1640 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1641 break;
a45c6cb8 1642 case MMC_BUS_WIDTH_4:
73153010 1643 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1644 OMAP_HSMMC_WRITE(host->base, HCTL,
1645 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1646 break;
1647 case MMC_BUS_WIDTH_1:
73153010 1648 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1649 OMAP_HSMMC_WRITE(host->base, HCTL,
1650 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1651 break;
1652 }
1653
4621d5f8 1654 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1655 /* Only MMC1 can interface at 3V without some flavor
1656 * of external transceiver; but they all handle 1.8V.
1657 */
a45c6cb8
MC		 1658 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1659 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1660 /*
1661 * The mmc_select_voltage fn of the core does
1662 * not seem to set the power_mode to
1663 * MMC_POWER_UP upon recalculating the voltage.
1664 * vdd 1.8v.
1665 */
70a3341a
DK		 1666 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1667 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1668 "Switch operation failed\n");
1669 }
1670 }
1671
70a3341a 1672 omap_hsmmc_stop_clock(host);
ac330f44 1673
a45c6cb8
MC		 1674 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1675 regval = regval & ~(CLKD_MASK);
ac330f44 1676 regval = regval | (calc_divisor(ios) << 6) | (DTO << 16);
a45c6cb8
MC		 1677 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1678 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1679 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1680
1681 /* Wait till the ICS bit is set */
1682 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1683 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1684 && time_before(jiffies, timeout))
1685 msleep(1);
1686
1687 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1688 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1689
a3621465 1690 if (do_send_init_stream)
a45c6cb8
MC		 1691 send_init_stream(host);
1692
abb28e73 1693 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1694 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1695 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1696 else
1697 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1698
fa4aa2d4 1699 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1700}
1701
1702static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1703{
70a3341a 1704 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1705
191d1f1d 1706 if (!mmc_slot(host).card_detect)
a45c6cb8 1707 return -ENOSYS;
db0fefc5 1708 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1709}
1710
1711static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1712{
70a3341a 1713 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1714
191d1f1d 1715 if (!mmc_slot(host).get_ro)
a45c6cb8 1716 return -ENOSYS;
191d1f1d 1717 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1718}
1719
4816858c
GI		 1720static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1721{
1722 struct omap_hsmmc_host *host = mmc_priv(mmc);
1723
1724 if (mmc_slot(host).init_card)
1725 mmc_slot(host).init_card(card);
1726}
1727
70a3341a 1728static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1729{
1730 u32 hctl, capa, value;
1731
1732 /* Only MMC1 supports 3.0V */
4621d5f8 1733 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1734 hctl = SDVS30;
1735 capa = VS30 | VS18;
1736 } else {
1737 hctl = SDVS18;
1738 capa = VS18;
1739 }
1740
1741 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1742 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1743
1744 value = OMAP_HSMMC_READ(host->base, CAPA);
1745 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1746
1747 /* Set the controller to AUTO IDLE mode */
1748 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1749 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1750
1751 /* Set SD bus power bit */
e13bb300 1752 set_sd_bus_power(host);
1b331e69
KK		 1753}
1754
70a3341a 1755static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1756{
70a3341a 1757 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1758
fa4aa2d4
B		 1759 pm_runtime_get_sync(host->dev);
1760
dd498eff
DK		 1761 return 0;
1762}
1763
70a3341a 1764static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1765{
70a3341a 1766 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1767
fa4aa2d4
B		 1768 pm_runtime_mark_last_busy(host->dev);
1769 pm_runtime_put_autosuspend(host->dev);
1770
dd498eff
DK		 1771 return 0;
1772}
1773
70a3341a
DK		 1774static const struct mmc_host_ops omap_hsmmc_ops = {
1775 .enable = omap_hsmmc_enable_fclk,
1776 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1777 .post_req = omap_hsmmc_post_req,
1778 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1779 .request = omap_hsmmc_request,
1780 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1781 .get_cd = omap_hsmmc_get_cd,
1782 .get_ro = omap_hsmmc_get_ro,
4816858c 1783 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1784 /* NYET -- enable_sdio_irq */
1785};
1786
d900f712
DK		 1787#ifdef CONFIG_DEBUG_FS
1788
70a3341a 1789static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1790{
1791 struct mmc_host *mmc = s->private;
70a3341a 1792 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1793 int context_loss = 0;
1794
70a3341a
DK		 1795 if (host->pdata->get_context_loss_count)
1796 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1797
5e2ea617
AH		 1798 seq_printf(s, "mmc%d:\n"
1799 " enabled:\t%d\n"
dd498eff 1800 " dpm_state:\t%d\n"
5e2ea617 1801 " nesting_cnt:\t%d\n"
11dd62a7 1802 " ctx_loss:\t%d:%d\n"
5e2ea617 1803 "\nregs:\n",
dd498eff
DK		 1804 mmc->index, mmc->enabled ? 1 : 0,
1805 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1806 host->context_loss, context_loss);
5e2ea617 1807
7a8c2cef 1808 if (host->suspended) {
dd498eff
DK		 1809 seq_printf(s, "host suspended, can't read registers\n");
1810 return 0;
1811 }
1812
fa4aa2d4 1813 pm_runtime_get_sync(host->dev);
d900f712
DK		 1814
1815 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1816 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1817 seq_printf(s, "CON:\t\t0x%08x\n",
1818 OMAP_HSMMC_READ(host->base, CON));
1819 seq_printf(s, "HCTL:\t\t0x%08x\n",
1820 OMAP_HSMMC_READ(host->base, HCTL));
1821 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1822 OMAP_HSMMC_READ(host->base, SYSCTL));
1823 seq_printf(s, "IE:\t\t0x%08x\n",
1824 OMAP_HSMMC_READ(host->base, IE));
1825 seq_printf(s, "ISE:\t\t0x%08x\n",
1826 OMAP_HSMMC_READ(host->base, ISE));
1827 seq_printf(s, "CAPA:\t\t0x%08x\n",
1828 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1829
fa4aa2d4
B		 1830 pm_runtime_mark_last_busy(host->dev);
1831 pm_runtime_put_autosuspend(host->dev);
dd498eff 1832
d900f712
DK		 1833 return 0;
1834}
1835
70a3341a 1836static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1837{
70a3341a 1838 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1839}
1840
1841static const struct file_operations mmc_regs_fops = {
70a3341a 1842 .open = omap_hsmmc_regs_open,
d900f712
DK		 1843 .read = seq_read,
1844 .llseek = seq_lseek,
1845 .release = single_release,
1846};
1847
70a3341a 1848static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1849{
1850 if (mmc->debugfs_root)
1851 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1852 mmc, &mmc_regs_fops);
1853}
1854
1855#else
1856
70a3341a 1857static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1858{
1859}
1860
1861#endif
1862
70a3341a 1863static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1864{
1865 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1866 struct mmc_host *mmc;
70a3341a 1867 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1868 struct resource *res;
db0fefc5 1869 int ret, irq;
a45c6cb8
MC		 1870
1871 if (pdata == NULL) {
1872 dev_err(&pdev->dev, "Platform Data is missing\n");
1873 return -ENXIO;
1874 }
1875
1876 if (pdata->nr_slots == 0) {
1877 dev_err(&pdev->dev, "No Slots\n");
1878 return -ENXIO;
1879 }
1880
1881 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1882 irq = platform_get_irq(pdev, 0);
1883 if (res == NULL || irq < 0)
1884 return -ENXIO;
1885
91a0b089 1886 res->start += pdata->reg_offset;
1887 res->end += pdata->reg_offset;
984b203a 1888 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1889 if (res == NULL)
1890 return -EBUSY;
1891
db0fefc5
AH		 1892 ret = omap_hsmmc_gpio_init(pdata);
1893 if (ret)
1894 goto err;
1895
70a3341a 1896 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1897 if (!mmc) {
1898 ret = -ENOMEM;
db0fefc5 1899 goto err_alloc;
a45c6cb8
MC		 1900 }
1901
1902 host = mmc_priv(mmc);
1903 host->mmc = mmc;
1904 host->pdata = pdata;
1905 host->dev = &pdev->dev;
1906 host->use_dma = 1;
1907 host->dev->dma_mask = &pdata->dma_mask;
1908 host->dma_ch = -1;
1909 host->irq = irq;
1910 host->id = pdev->id;
1911 host->slot_id = 0;
1912 host->mapbase = res->start;
1913 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1914 host->power_mode = MMC_POWER_OFF;
9782aff8 1915 host->next_data.cookie = 1;
a45c6cb8
MC		 1916
1917 platform_set_drvdata(pdev, host);
70a3341a 1918 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 1919
7a8c2cef 1920 mmc->ops = &omap_hsmmc_ops;
dd498eff 1921
e0eb2424
AH		 1922 /*
1923 * If regulator_disable can only put vcc_aux to sleep then there is
1924 * no off state.
1925 */
1926 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1927 mmc_slot(host).no_off = 1;
1928
6b206efe
AS		 1929 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1930 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1931
4dffd7a2 1932 spin_lock_init(&host->irq_lock);
a45c6cb8 1933
6f7607cc 1934 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1935 if (IS_ERR(host->fclk)) {
1936 ret = PTR_ERR(host->fclk);
1937 host->fclk = NULL;
a45c6cb8
MC		 1938 goto err1;
1939 }
1940
70a3341a 1941 omap_hsmmc_context_save(host);
11dd62a7 1942
5e2ea617 1943 mmc->caps |= MMC_CAP_DISABLE;
dd498eff 1944
fa4aa2d4
B		 1945 pm_runtime_enable(host->dev);
1946 pm_runtime_get_sync(host->dev);
1947 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1948 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1949
2bec0893
AH		 1950 if (cpu_is_omap2430()) {
1951 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1952 /*
1953 * MMC can still work without debounce clock.
1954 */
1955 if (IS_ERR(host->dbclk))
1956 dev_warn(mmc_dev(host->mmc),
1957 "Failed to get debounce clock\n");
a45c6cb8 1958 else
2bec0893
AH		 1959 host->got_dbclk = 1;
1960
1961 if (host->got_dbclk)
1962 if (clk_enable(host->dbclk) != 0)
1963 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1964 " clk failed\n");
1965 }
a45c6cb8 1966
0ccd76d4
JY		 1967 /* Since we do only SG emulation, we can have as many segs
1968 * as we want. */
a36274e0 1969 mmc->max_segs = 1024;
0ccd76d4 1970
a45c6cb8
MC		 1971 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1972 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1973 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1974 mmc->max_seg_size = mmc->max_req_size;
1975
13189e78 1976 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1977 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1978
3a63833e
SG		 1979 mmc->caps |= mmc_slot(host).caps;
1980 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1981 mmc->caps |= MMC_CAP_4_BIT_DATA;
1982
191d1f1d 1983 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1984 mmc->caps |= MMC_CAP_NONREMOVABLE;
1985
70a3341a 1986 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1987
f3e2f1dd
GI		 1988 /* Select DMA lines */
1989 switch (host->id) {
1990 case OMAP_MMC1_DEVID:
1991 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
1992 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
1993 break;
1994 case OMAP_MMC2_DEVID:
1995 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
1996 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
1997 break;
1998 case OMAP_MMC3_DEVID:
1999 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2000 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2001 break;
82cf818d 2002 case OMAP_MMC4_DEVID:
2003 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2004 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2005 break;
2006 case OMAP_MMC5_DEVID:
2007 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2008 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2009 break;
f3e2f1dd
GI		 2010 default:
2011 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2012 goto err_irq;
2013 }
a45c6cb8
MC		 2014
2015 /* Request IRQ for MMC operations */
70a3341a 2016 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
a45c6cb8
MC		 2017 mmc_hostname(mmc), host);
2018 if (ret) {
2019 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2020 goto err_irq;
2021 }
2022
2023 if (pdata->init != NULL) {
2024 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2025 dev_dbg(mmc_dev(host->mmc),
2026 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2027 goto err_irq_cd_init;
2028 }
2029 }
db0fefc5 2030
b702b106 2031 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 2032 ret = omap_hsmmc_reg_get(host);
2033 if (ret)
2034 goto err_reg;
2035 host->use_reg = 1;
2036 }
2037
b583f26d 2038 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2039
2040 /* Request IRQ for card detect */
e1a55f5e 2041 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2042 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2043 omap_hsmmc_cd_handler,
a45c6cb8
MC		 2044 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2045 | IRQF_DISABLED,
2046 mmc_hostname(mmc), host);
2047 if (ret) {
2048 dev_dbg(mmc_dev(host->mmc),
2049 "Unable to grab MMC CD IRQ\n");
2050 goto err_irq_cd;
2051 }
72f2e2c7 2052 pdata->suspend = omap_hsmmc_suspend_cdirq;
2053 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 2054 }
2055
b417577d 2056 omap_hsmmc_disable_irq(host);
a45c6cb8 2057
b62f6228
AH		 2058 omap_hsmmc_protect_card(host);
2059
a45c6cb8
MC		 2060 mmc_add_host(mmc);
2061
191d1f1d 2062 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2063 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2064 if (ret < 0)
2065 goto err_slot_name;
2066 }
191d1f1d 2067 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2068 ret = device_create_file(&mmc->class_dev,
2069 &dev_attr_cover_switch);
2070 if (ret < 0)
db0fefc5 2071 goto err_slot_name;
a45c6cb8
MC		 2072 }
2073
70a3341a 2074 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 2075 pm_runtime_mark_last_busy(host->dev);
2076 pm_runtime_put_autosuspend(host->dev);
d900f712 2077
a45c6cb8
MC		 2078 return 0;
2079
a45c6cb8
MC		 2080err_slot_name:
2081 mmc_remove_host(mmc);
a45c6cb8 2082 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2083err_irq_cd:
2084 if (host->use_reg)
2085 omap_hsmmc_reg_put(host);
2086err_reg:
2087 if (host->pdata->cleanup)
2088 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2089err_irq_cd_init:
2090 free_irq(host->irq, host);
2091err_irq:
fa4aa2d4
B		 2092 pm_runtime_mark_last_busy(host->dev);
2093 pm_runtime_put_autosuspend(host->dev);
a45c6cb8 2094 clk_put(host->fclk);
2bec0893 2095 if (host->got_dbclk) {
a45c6cb8
MC		 2096 clk_disable(host->dbclk);
2097 clk_put(host->dbclk);
2098 }
a45c6cb8
MC		 2099err1:
2100 iounmap(host->base);
db0fefc5
AH		 2101 platform_set_drvdata(pdev, NULL);
2102 mmc_free_host(mmc);
2103err_alloc:
2104 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2105err:
984b203a 2106 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2107 return ret;
2108}
2109
70a3341a 2110static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2111{
70a3341a 2112 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2113 struct resource *res;
2114
2115 if (host) {
fa4aa2d4 2116 pm_runtime_get_sync(host->dev);
a45c6cb8 2117 mmc_remove_host(host->mmc);
db0fefc5
AH		 2118 if (host->use_reg)
2119 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2120 if (host->pdata->cleanup)
2121 host->pdata->cleanup(&pdev->dev);
2122 free_irq(host->irq, host);
2123 if (mmc_slot(host).card_detect_irq)
2124 free_irq(mmc_slot(host).card_detect_irq, host);
0d9ee5b2 2125 flush_work_sync(&host->mmc_carddetect_work);
a45c6cb8 2126
fa4aa2d4
B		 2127 pm_runtime_put_sync(host->dev);
2128 pm_runtime_disable(host->dev);
a45c6cb8 2129 clk_put(host->fclk);
2bec0893 2130 if (host->got_dbclk) {
a45c6cb8
MC		 2131 clk_disable(host->dbclk);
2132 clk_put(host->dbclk);
2133 }
2134
2135 mmc_free_host(host->mmc);
2136 iounmap(host->base);
db0fefc5 2137 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2138 }
2139
2140 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2141 if (res)
984b203a 2142 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2143 platform_set_drvdata(pdev, NULL);
2144
2145 return 0;
2146}
2147
2148#ifdef CONFIG_PM
a791daa1 2149static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2150{
2151 int ret = 0;
a791daa1 2152 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2153 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2154
2155 if (host && host->suspended)
2156 return 0;
2157
2158 if (host) {
fa4aa2d4 2159 pm_runtime_get_sync(host->dev);
a6b2240d
AH		 2160 host->suspended = 1;
2161 if (host->pdata->suspend) {
2162 ret = host->pdata->suspend(&pdev->dev,
2163 host->slot_id);
2164 if (ret) {
2165 dev_dbg(mmc_dev(host->mmc),
2166 "Unable to handle MMC board"
2167 " level suspend\n");
2168 host->suspended = 0;
2169 return ret;
2170 }
2171 }
2172 cancel_work_sync(&host->mmc_carddetect_work);
1a13f8fa 2173 ret = mmc_suspend_host(host->mmc);
fa4aa2d4 2174
a45c6cb8 2175 if (ret == 0) {
b417577d 2176 omap_hsmmc_disable_irq(host);
0683af48 2177 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2178 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
2bec0893
AH		 2179 if (host->got_dbclk)
2180 clk_disable(host->dbclk);
a6b2240d
AH		 2181 } else {
2182 host->suspended = 0;
2183 if (host->pdata->resume) {
2184 ret = host->pdata->resume(&pdev->dev,
2185 host->slot_id);
2186 if (ret)
2187 dev_dbg(mmc_dev(host->mmc),
2188 "Unmask interrupt failed\n");
2189 }
a6b2240d 2190 }
fa4aa2d4 2191 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2192 }
2193 return ret;
2194}
2195
2196/* Routine to resume the MMC device */
a791daa1 2197static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2198{
2199 int ret = 0;
a791daa1 2200 struct platform_device *pdev = to_platform_device(dev);
70a3341a 2201 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2202
2203 if (host && !host->suspended)
2204 return 0;
2205
2206 if (host) {
fa4aa2d4 2207 pm_runtime_get_sync(host->dev);
11dd62a7 2208
2bec0893
AH		 2209 if (host->got_dbclk)
2210 clk_enable(host->dbclk);
2211
70a3341a 2212 omap_hsmmc_conf_bus_power(host);
1b331e69 2213
a45c6cb8
MC		 2214 if (host->pdata->resume) {
2215 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2216 if (ret)
2217 dev_dbg(mmc_dev(host->mmc),
2218 "Unmask interrupt failed\n");
2219 }
2220
b62f6228
AH		 2221 omap_hsmmc_protect_card(host);
2222
a45c6cb8
MC		 2223 /* Notify the core to resume the host */
2224 ret = mmc_resume_host(host->mmc);
2225 if (ret == 0)
2226 host->suspended = 0;
fa4aa2d4
B		 2227
2228 pm_runtime_mark_last_busy(host->dev);
2229 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2230 }
2231
2232 return ret;
2233
a45c6cb8
MC		 2234}
2235
2236#else
70a3341a
DK		 2237#define omap_hsmmc_suspend NULL
2238#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2239#endif
2240
fa4aa2d4
B		 2241static int omap_hsmmc_runtime_suspend(struct device *dev)
2242{
2243 struct omap_hsmmc_host *host;
2244
2245 host = platform_get_drvdata(to_platform_device(dev));
2246 omap_hsmmc_context_save(host);
2247 dev_dbg(mmc_dev(host->mmc), "disabled\n");
2248
2249 return 0;
2250}
2251
2252static int omap_hsmmc_runtime_resume(struct device *dev)
2253{
2254 struct omap_hsmmc_host *host;
2255
2256 host = platform_get_drvdata(to_platform_device(dev));
2257 omap_hsmmc_context_restore(host);
2258 dev_dbg(mmc_dev(host->mmc), "enabled\n");
2259
2260 return 0;
2261}
2262
a791daa1 2263static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2264 .suspend = omap_hsmmc_suspend,
2265 .resume = omap_hsmmc_resume,
fa4aa2d4
B		 2266 .runtime_suspend = omap_hsmmc_runtime_suspend,
2267 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2268};
2269
2270static struct platform_driver omap_hsmmc_driver = {
2271 .remove = omap_hsmmc_remove,
a45c6cb8
MC		 2272 .driver = {
2273 .name = DRIVER_NAME,
2274 .owner = THIS_MODULE,
a791daa1 2275 .pm = &omap_hsmmc_dev_pm_ops,
a45c6cb8
MC		 2276 },
2277};
2278
70a3341a 2279static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2280{
2281 /* Register the MMC driver */
8753298a 2282 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2283}
2284
70a3341a 2285static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2286{
2287 /* Unregister MMC driver */
70a3341a 2288 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2289}
2290
70a3341a
DK		 2291module_init(omap_hsmmc_init);
2292module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2293
2294MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2295MODULE_LICENSE("GPL");
2296MODULE_ALIAS("platform:" DRIVER_NAME);
2297MODULE_AUTHOR("Texas Instruments Inc");
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