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Commit | Line | Data |
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a45c6cb8 MC |
1 | /* |
2 | * drivers/mmc/host/omap_hsmmc.c | |
3 | * | |
4 | * Driver for OMAP2430/3430 MMC controller. | |
5 | * | |
6 | * Copyright (C) 2007 Texas Instruments. | |
7 | * | |
8 | * Authors: | |
9 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
10 | * Madhusudhan <madhu.cr@ti.com> | |
11 | * Mohit Jalori <mjalori@ti.com> | |
12 | * | |
13 | * This file is licensed under the terms of the GNU General Public License | |
14 | * version 2. This program is licensed "as is" without any warranty of any | |
15 | * kind, whether express or implied. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
ac330f44 | 20 | #include <linux/kernel.h> |
d900f712 | 21 | #include <linux/debugfs.h> |
c5c98927 | 22 | #include <linux/dmaengine.h> |
d900f712 | 23 | #include <linux/seq_file.h> |
031cd037 | 24 | #include <linux/sizes.h> |
a45c6cb8 MC |
25 | #include <linux/interrupt.h> |
26 | #include <linux/delay.h> | |
27 | #include <linux/dma-mapping.h> | |
28 | #include <linux/platform_device.h> | |
a45c6cb8 MC |
29 | #include <linux/timer.h> |
30 | #include <linux/clk.h> | |
46856a68 RN |
31 | #include <linux/of.h> |
32 | #include <linux/of_gpio.h> | |
33 | #include <linux/of_device.h> | |
3451c067 | 34 | #include <linux/omap-dma.h> |
a45c6cb8 | 35 | #include <linux/mmc/host.h> |
13189e78 | 36 | #include <linux/mmc/core.h> |
93caf8e6 | 37 | #include <linux/mmc/mmc.h> |
a45c6cb8 | 38 | #include <linux/io.h> |
db0fefc5 AH |
39 | #include <linux/gpio.h> |
40 | #include <linux/regulator/consumer.h> | |
46b76035 | 41 | #include <linux/pinctrl/consumer.h> |
fa4aa2d4 | 42 | #include <linux/pm_runtime.h> |
68f39e74 | 43 | #include <linux/platform_data/mmc-omap.h> |
a45c6cb8 MC |
44 | |
45 | /* OMAP HSMMC Host Controller Registers */ | |
11dd62a7 | 46 | #define OMAP_HSMMC_SYSSTATUS 0x0014 |
a45c6cb8 MC |
47 | #define OMAP_HSMMC_CON 0x002C |
48 | #define OMAP_HSMMC_BLK 0x0104 | |
49 | #define OMAP_HSMMC_ARG 0x0108 | |
50 | #define OMAP_HSMMC_CMD 0x010C | |
51 | #define OMAP_HSMMC_RSP10 0x0110 | |
52 | #define OMAP_HSMMC_RSP32 0x0114 | |
53 | #define OMAP_HSMMC_RSP54 0x0118 | |
54 | #define OMAP_HSMMC_RSP76 0x011C | |
55 | #define OMAP_HSMMC_DATA 0x0120 | |
56 | #define OMAP_HSMMC_HCTL 0x0128 | |
57 | #define OMAP_HSMMC_SYSCTL 0x012C | |
58 | #define OMAP_HSMMC_STAT 0x0130 | |
59 | #define OMAP_HSMMC_IE 0x0134 | |
60 | #define OMAP_HSMMC_ISE 0x0138 | |
61 | #define OMAP_HSMMC_CAPA 0x0140 | |
62 | ||
63 | #define VS18 (1 << 26) | |
64 | #define VS30 (1 << 25) | |
cd587096 | 65 | #define HSS (1 << 21) |
a45c6cb8 MC |
66 | #define SDVS18 (0x5 << 9) |
67 | #define SDVS30 (0x6 << 9) | |
eb250826 | 68 | #define SDVS33 (0x7 << 9) |
1b331e69 | 69 | #define SDVS_MASK 0x00000E00 |
a45c6cb8 MC |
70 | #define SDVSCLR 0xFFFFF1FF |
71 | #define SDVSDET 0x00000400 | |
72 | #define AUTOIDLE 0x1 | |
73 | #define SDBP (1 << 8) | |
74 | #define DTO 0xe | |
75 | #define ICE 0x1 | |
76 | #define ICS 0x2 | |
77 | #define CEN (1 << 2) | |
ed164182 | 78 | #define CLKD_MAX 0x3FF /* max clock divisor: 1023 */ |
a45c6cb8 MC |
79 | #define CLKD_MASK 0x0000FFC0 |
80 | #define CLKD_SHIFT 6 | |
81 | #define DTO_MASK 0x000F0000 | |
82 | #define DTO_SHIFT 16 | |
a45c6cb8 MC |
83 | #define INIT_STREAM (1 << 1) |
84 | #define DP_SELECT (1 << 21) | |
85 | #define DDIR (1 << 4) | |
a7e96879 | 86 | #define DMAE 0x1 |
a45c6cb8 MC |
87 | #define MSBS (1 << 5) |
88 | #define BCE (1 << 1) | |
89 | #define FOUR_BIT (1 << 1) | |
cd587096 | 90 | #define HSPE (1 << 2) |
03b5d924 | 91 | #define DDR (1 << 19) |
73153010 | 92 | #define DW8 (1 << 5) |
a45c6cb8 | 93 | #define OD 0x1 |
a45c6cb8 MC |
94 | #define STAT_CLEAR 0xFFFFFFFF |
95 | #define INIT_STREAM_CMD 0x00000000 | |
96 | #define DUAL_VOLT_OCR_BIT 7 | |
97 | #define SRC (1 << 25) | |
98 | #define SRD (1 << 26) | |
11dd62a7 DK |
99 | #define SOFTRESET (1 << 1) |
100 | #define RESETDONE (1 << 0) | |
a45c6cb8 | 101 | |
a7e96879 V |
102 | /* Interrupt masks for IE and ISE register */ |
103 | #define CC_EN (1 << 0) | |
104 | #define TC_EN (1 << 1) | |
105 | #define BWR_EN (1 << 4) | |
106 | #define BRR_EN (1 << 5) | |
107 | #define ERR_EN (1 << 15) | |
108 | #define CTO_EN (1 << 16) | |
109 | #define CCRC_EN (1 << 17) | |
110 | #define CEB_EN (1 << 18) | |
111 | #define CIE_EN (1 << 19) | |
112 | #define DTO_EN (1 << 20) | |
113 | #define DCRC_EN (1 << 21) | |
114 | #define DEB_EN (1 << 22) | |
115 | #define CERR_EN (1 << 28) | |
116 | #define BADA_EN (1 << 29) | |
117 | ||
118 | #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\ | |
119 | DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ | |
120 | BRR_EN | BWR_EN | TC_EN | CC_EN) | |
121 | ||
fa4aa2d4 | 122 | #define MMC_AUTOSUSPEND_DELAY 100 |
1e881786 JM |
123 | #define MMC_TIMEOUT_MS 20 /* 20 mSec */ |
124 | #define MMC_TIMEOUT_US 20000 /* 20000 micro Sec */ | |
6b206efe AS |
125 | #define OMAP_MMC_MIN_CLOCK 400000 |
126 | #define OMAP_MMC_MAX_CLOCK 52000000 | |
0005ae73 | 127 | #define DRIVER_NAME "omap_hsmmc" |
a45c6cb8 MC |
128 | |
129 | /* | |
130 | * One controller can have multiple slots, like on some omap boards using | |
131 | * omap.c controller driver. Luckily this is not currently done on any known | |
132 | * omap_hsmmc.c device. | |
133 | */ | |
134 | #define mmc_slot(host) (host->pdata->slots[host->slot_id]) | |
135 | ||
136 | /* | |
137 | * MMC Host controller read/write API's | |
138 | */ | |
139 | #define OMAP_HSMMC_READ(base, reg) \ | |
140 | __raw_readl((base) + OMAP_HSMMC_##reg) | |
141 | ||
142 | #define OMAP_HSMMC_WRITE(base, reg, val) \ | |
143 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) | |
144 | ||
9782aff8 PF |
145 | struct omap_hsmmc_next { |
146 | unsigned int dma_len; | |
147 | s32 cookie; | |
148 | }; | |
149 | ||
70a3341a | 150 | struct omap_hsmmc_host { |
a45c6cb8 MC |
151 | struct device *dev; |
152 | struct mmc_host *mmc; | |
153 | struct mmc_request *mrq; | |
154 | struct mmc_command *cmd; | |
155 | struct mmc_data *data; | |
156 | struct clk *fclk; | |
a45c6cb8 | 157 | struct clk *dbclk; |
db0fefc5 AH |
158 | /* |
159 | * vcc == configured supply | |
160 | * vcc_aux == optional | |
161 | * - MMC1, supply for DAT4..DAT7 | |
162 | * - MMC2/MMC2, external level shifter voltage supply, for | |
163 | * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) | |
164 | */ | |
165 | struct regulator *vcc; | |
166 | struct regulator *vcc_aux; | |
cf5ae40b | 167 | int pbias_disable; |
a45c6cb8 MC |
168 | void __iomem *base; |
169 | resource_size_t mapbase; | |
4dffd7a2 | 170 | spinlock_t irq_lock; /* Prevent races with irq handler */ |
a45c6cb8 | 171 | unsigned int dma_len; |
0ccd76d4 | 172 | unsigned int dma_sg_idx; |
a45c6cb8 | 173 | unsigned char bus_mode; |
a3621465 | 174 | unsigned char power_mode; |
a45c6cb8 | 175 | int suspended; |
0a82e06e TL |
176 | u32 con; |
177 | u32 hctl; | |
178 | u32 sysctl; | |
179 | u32 capa; | |
a45c6cb8 | 180 | int irq; |
a45c6cb8 | 181 | int use_dma, dma_ch; |
c5c98927 RK |
182 | struct dma_chan *tx_chan; |
183 | struct dma_chan *rx_chan; | |
a45c6cb8 | 184 | int slot_id; |
4a694dc9 | 185 | int response_busy; |
11dd62a7 | 186 | int context_loss; |
b62f6228 AH |
187 | int protect_card; |
188 | int reqs_blocked; | |
db0fefc5 | 189 | int use_reg; |
b417577d | 190 | int req_in_progress; |
9782aff8 | 191 | struct omap_hsmmc_next next_data; |
a45c6cb8 MC |
192 | struct omap_mmc_platform_data *pdata; |
193 | }; | |
194 | ||
db0fefc5 AH |
195 | static int omap_hsmmc_card_detect(struct device *dev, int slot) |
196 | { | |
9ea28ecb B |
197 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
198 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
199 | |
200 | /* NOTE: assumes card detect signal is active-low */ | |
201 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
202 | } | |
203 | ||
204 | static int omap_hsmmc_get_wp(struct device *dev, int slot) | |
205 | { | |
9ea28ecb B |
206 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
207 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
208 | |
209 | /* NOTE: assumes write protect signal is active-high */ | |
210 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | |
211 | } | |
212 | ||
213 | static int omap_hsmmc_get_cover_state(struct device *dev, int slot) | |
214 | { | |
9ea28ecb B |
215 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
216 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
217 | |
218 | /* NOTE: assumes card detect signal is active-low */ | |
219 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
220 | } | |
221 | ||
222 | #ifdef CONFIG_PM | |
223 | ||
224 | static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) | |
225 | { | |
9ea28ecb B |
226 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
227 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
228 | |
229 | disable_irq(mmc->slots[0].card_detect_irq); | |
230 | return 0; | |
231 | } | |
232 | ||
233 | static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) | |
234 | { | |
9ea28ecb B |
235 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
236 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
237 | |
238 | enable_irq(mmc->slots[0].card_detect_irq); | |
239 | return 0; | |
240 | } | |
241 | ||
242 | #else | |
243 | ||
244 | #define omap_hsmmc_suspend_cdirq NULL | |
245 | #define omap_hsmmc_resume_cdirq NULL | |
246 | ||
247 | #endif | |
248 | ||
b702b106 AH |
249 | #ifdef CONFIG_REGULATOR |
250 | ||
69b07ece | 251 | static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, |
db0fefc5 AH |
252 | int vdd) |
253 | { | |
254 | struct omap_hsmmc_host *host = | |
255 | platform_get_drvdata(to_platform_device(dev)); | |
256 | int ret = 0; | |
257 | ||
258 | /* | |
259 | * If we don't see a Vcc regulator, assume it's a fixed | |
260 | * voltage always-on regulator. | |
261 | */ | |
262 | if (!host->vcc) | |
263 | return 0; | |
1f84b71b | 264 | /* |
cf5ae40b | 265 | * With DT, never turn OFF the regulator for MMC1. This is because |
1f84b71b RN |
266 | * the pbias cell programming support is still missing when |
267 | * booting with Device tree | |
268 | */ | |
cf5ae40b | 269 | if (host->pbias_disable && !vdd) |
1f84b71b | 270 | return 0; |
db0fefc5 AH |
271 | |
272 | if (mmc_slot(host).before_set_reg) | |
273 | mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); | |
274 | ||
275 | /* | |
276 | * Assume Vcc regulator is used only to power the card ... OMAP | |
277 | * VDDS is used to power the pins, optionally with a transceiver to | |
278 | * support cards using voltages other than VDDS (1.8V nominal). When a | |
279 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. | |
280 | * | |
281 | * In some cases this regulator won't support enable/disable; | |
282 | * e.g. it's a fixed rail for a WLAN chip. | |
283 | * | |
284 | * In other cases vcc_aux switches interface power. Example, for | |
285 | * eMMC cards it represents VccQ. Sometimes transceivers or SDIO | |
286 | * chips/cards need an interface voltage rail too. | |
287 | */ | |
288 | if (power_on) { | |
99fc5131 | 289 | ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); |
db0fefc5 AH |
290 | /* Enable interface voltage rail, if needed */ |
291 | if (ret == 0 && host->vcc_aux) { | |
292 | ret = regulator_enable(host->vcc_aux); | |
293 | if (ret < 0) | |
99fc5131 LW |
294 | ret = mmc_regulator_set_ocr(host->mmc, |
295 | host->vcc, 0); | |
db0fefc5 AH |
296 | } |
297 | } else { | |
99fc5131 | 298 | /* Shut down the rail */ |
6da20c89 AH |
299 | if (host->vcc_aux) |
300 | ret = regulator_disable(host->vcc_aux); | |
99fc5131 LW |
301 | if (!ret) { |
302 | /* Then proceed to shut down the local regulator */ | |
303 | ret = mmc_regulator_set_ocr(host->mmc, | |
304 | host->vcc, 0); | |
305 | } | |
db0fefc5 AH |
306 | } |
307 | ||
308 | if (mmc_slot(host).after_set_reg) | |
309 | mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); | |
310 | ||
311 | return ret; | |
312 | } | |
313 | ||
db0fefc5 AH |
314 | static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) |
315 | { | |
316 | struct regulator *reg; | |
64be9782 | 317 | int ocr_value = 0; |
db0fefc5 | 318 | |
db0fefc5 AH |
319 | reg = regulator_get(host->dev, "vmmc"); |
320 | if (IS_ERR(reg)) { | |
b1e056ae | 321 | dev_err(host->dev, "vmmc regulator missing\n"); |
1fdc90fb | 322 | return PTR_ERR(reg); |
db0fefc5 | 323 | } else { |
1fdc90fb | 324 | mmc_slot(host).set_power = omap_hsmmc_set_power; |
db0fefc5 | 325 | host->vcc = reg; |
64be9782 | 326 | ocr_value = mmc_regulator_get_ocrmask(reg); |
327 | if (!mmc_slot(host).ocr_mask) { | |
328 | mmc_slot(host).ocr_mask = ocr_value; | |
329 | } else { | |
330 | if (!(mmc_slot(host).ocr_mask & ocr_value)) { | |
2cecdf00 | 331 | dev_err(host->dev, "ocrmask %x is not supported\n", |
e3f1adb6 | 332 | mmc_slot(host).ocr_mask); |
64be9782 | 333 | mmc_slot(host).ocr_mask = 0; |
334 | return -EINVAL; | |
335 | } | |
336 | } | |
db0fefc5 AH |
337 | |
338 | /* Allow an aux regulator */ | |
339 | reg = regulator_get(host->dev, "vmmc_aux"); | |
340 | host->vcc_aux = IS_ERR(reg) ? NULL : reg; | |
341 | ||
b1c1df7a B |
342 | /* For eMMC do not power off when not in sleep state */ |
343 | if (mmc_slot(host).no_regulator_off_init) | |
344 | return 0; | |
db0fefc5 AH |
345 | /* |
346 | * UGLY HACK: workaround regulator framework bugs. | |
347 | * When the bootloader leaves a supply active, it's | |
348 | * initialized with zero usecount ... and we can't | |
349 | * disable it without first enabling it. Until the | |
350 | * framework is fixed, we need a workaround like this | |
351 | * (which is safe for MMC, but not in general). | |
352 | */ | |
e840ce13 AH |
353 | if (regulator_is_enabled(host->vcc) > 0 || |
354 | (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { | |
355 | int vdd = ffs(mmc_slot(host).ocr_mask) - 1; | |
356 | ||
357 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
358 | 1, vdd); | |
359 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
360 | 0, 0); | |
db0fefc5 AH |
361 | } |
362 | } | |
363 | ||
364 | return 0; | |
db0fefc5 AH |
365 | } |
366 | ||
367 | static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) | |
368 | { | |
369 | regulator_put(host->vcc); | |
370 | regulator_put(host->vcc_aux); | |
371 | mmc_slot(host).set_power = NULL; | |
db0fefc5 AH |
372 | } |
373 | ||
b702b106 AH |
374 | static inline int omap_hsmmc_have_reg(void) |
375 | { | |
376 | return 1; | |
377 | } | |
378 | ||
379 | #else | |
380 | ||
381 | static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) | |
382 | { | |
383 | return -EINVAL; | |
384 | } | |
385 | ||
386 | static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) | |
387 | { | |
388 | } | |
389 | ||
390 | static inline int omap_hsmmc_have_reg(void) | |
391 | { | |
392 | return 0; | |
393 | } | |
394 | ||
395 | #endif | |
396 | ||
397 | static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) | |
398 | { | |
399 | int ret; | |
400 | ||
401 | if (gpio_is_valid(pdata->slots[0].switch_pin)) { | |
b702b106 AH |
402 | if (pdata->slots[0].cover) |
403 | pdata->slots[0].get_cover_state = | |
404 | omap_hsmmc_get_cover_state; | |
405 | else | |
406 | pdata->slots[0].card_detect = omap_hsmmc_card_detect; | |
407 | pdata->slots[0].card_detect_irq = | |
408 | gpio_to_irq(pdata->slots[0].switch_pin); | |
409 | ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); | |
410 | if (ret) | |
411 | return ret; | |
412 | ret = gpio_direction_input(pdata->slots[0].switch_pin); | |
413 | if (ret) | |
414 | goto err_free_sp; | |
415 | } else | |
416 | pdata->slots[0].switch_pin = -EINVAL; | |
417 | ||
418 | if (gpio_is_valid(pdata->slots[0].gpio_wp)) { | |
419 | pdata->slots[0].get_ro = omap_hsmmc_get_wp; | |
420 | ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); | |
421 | if (ret) | |
422 | goto err_free_cd; | |
423 | ret = gpio_direction_input(pdata->slots[0].gpio_wp); | |
424 | if (ret) | |
425 | goto err_free_wp; | |
426 | } else | |
427 | pdata->slots[0].gpio_wp = -EINVAL; | |
428 | ||
429 | return 0; | |
430 | ||
431 | err_free_wp: | |
432 | gpio_free(pdata->slots[0].gpio_wp); | |
433 | err_free_cd: | |
434 | if (gpio_is_valid(pdata->slots[0].switch_pin)) | |
435 | err_free_sp: | |
436 | gpio_free(pdata->slots[0].switch_pin); | |
437 | return ret; | |
438 | } | |
439 | ||
440 | static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) | |
441 | { | |
442 | if (gpio_is_valid(pdata->slots[0].gpio_wp)) | |
443 | gpio_free(pdata->slots[0].gpio_wp); | |
444 | if (gpio_is_valid(pdata->slots[0].switch_pin)) | |
445 | gpio_free(pdata->slots[0].switch_pin); | |
446 | } | |
447 | ||
e0c7f99b AS |
448 | /* |
449 | * Start clock to the card | |
450 | */ | |
451 | static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) | |
452 | { | |
453 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
454 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
455 | } | |
456 | ||
a45c6cb8 MC |
457 | /* |
458 | * Stop clock to the card | |
459 | */ | |
70a3341a | 460 | static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
461 | { |
462 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
463 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
464 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) | |
7122bbb0 | 465 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); |
a45c6cb8 MC |
466 | } |
467 | ||
93caf8e6 AH |
468 | static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, |
469 | struct mmc_command *cmd) | |
b417577d AH |
470 | { |
471 | unsigned int irq_mask; | |
472 | ||
473 | if (host->use_dma) | |
a7e96879 | 474 | irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); |
b417577d AH |
475 | else |
476 | irq_mask = INT_EN_MASK; | |
477 | ||
93caf8e6 AH |
478 | /* Disable timeout for erases */ |
479 | if (cmd->opcode == MMC_ERASE) | |
a7e96879 | 480 | irq_mask &= ~DTO_EN; |
93caf8e6 | 481 | |
b417577d AH |
482 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
483 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); | |
484 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); | |
485 | } | |
486 | ||
487 | static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) | |
488 | { | |
489 | OMAP_HSMMC_WRITE(host->base, ISE, 0); | |
490 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
491 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
492 | } | |
493 | ||
ac330f44 | 494 | /* Calculate divisor for the given clock frequency */ |
d83b6e03 | 495 | static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) |
ac330f44 AS |
496 | { |
497 | u16 dsor = 0; | |
498 | ||
499 | if (ios->clock) { | |
d83b6e03 | 500 | dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); |
ed164182 B |
501 | if (dsor > CLKD_MAX) |
502 | dsor = CLKD_MAX; | |
ac330f44 AS |
503 | } |
504 | ||
505 | return dsor; | |
506 | } | |
507 | ||
5934df2f AS |
508 | static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) |
509 | { | |
510 | struct mmc_ios *ios = &host->mmc->ios; | |
511 | unsigned long regval; | |
512 | unsigned long timeout; | |
cd587096 | 513 | unsigned long clkdiv; |
5934df2f | 514 | |
8986d31b | 515 | dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); |
5934df2f AS |
516 | |
517 | omap_hsmmc_stop_clock(host); | |
518 | ||
519 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); | |
520 | regval = regval & ~(CLKD_MASK | DTO_MASK); | |
cd587096 HG |
521 | clkdiv = calc_divisor(host, ios); |
522 | regval = regval | (clkdiv << 6) | (DTO << 16); | |
5934df2f AS |
523 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); |
524 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
525 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
526 | ||
527 | /* Wait till the ICS bit is set */ | |
528 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
529 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS | |
530 | && time_before(jiffies, timeout)) | |
531 | cpu_relax(); | |
532 | ||
cd587096 HG |
533 | /* |
534 | * Enable High-Speed Support | |
535 | * Pre-Requisites | |
536 | * - Controller should support High-Speed-Enable Bit | |
537 | * - Controller should not be using DDR Mode | |
538 | * - Controller should advertise that it supports High Speed | |
539 | * in capabilities register | |
540 | * - MMC/SD clock coming out of controller > 25MHz | |
541 | */ | |
542 | if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && | |
543 | (ios->timing != MMC_TIMING_UHS_DDR50) && | |
544 | ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { | |
545 | regval = OMAP_HSMMC_READ(host->base, HCTL); | |
546 | if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) | |
547 | regval |= HSPE; | |
548 | else | |
549 | regval &= ~HSPE; | |
550 | ||
551 | OMAP_HSMMC_WRITE(host->base, HCTL, regval); | |
552 | } | |
553 | ||
5934df2f AS |
554 | omap_hsmmc_start_clock(host); |
555 | } | |
556 | ||
3796fb8a AS |
557 | static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) |
558 | { | |
559 | struct mmc_ios *ios = &host->mmc->ios; | |
560 | u32 con; | |
561 | ||
562 | con = OMAP_HSMMC_READ(host->base, CON); | |
03b5d924 B |
563 | if (ios->timing == MMC_TIMING_UHS_DDR50) |
564 | con |= DDR; /* configure in DDR mode */ | |
565 | else | |
566 | con &= ~DDR; | |
3796fb8a AS |
567 | switch (ios->bus_width) { |
568 | case MMC_BUS_WIDTH_8: | |
569 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
570 | break; | |
571 | case MMC_BUS_WIDTH_4: | |
572 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
573 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
574 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
575 | break; | |
576 | case MMC_BUS_WIDTH_1: | |
577 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
578 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
579 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
580 | break; | |
581 | } | |
582 | } | |
583 | ||
584 | static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) | |
585 | { | |
586 | struct mmc_ios *ios = &host->mmc->ios; | |
587 | u32 con; | |
588 | ||
589 | con = OMAP_HSMMC_READ(host->base, CON); | |
590 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
591 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); | |
592 | else | |
593 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
594 | } | |
595 | ||
11dd62a7 DK |
596 | #ifdef CONFIG_PM |
597 | ||
598 | /* | |
599 | * Restore the MMC host context, if it was lost as result of a | |
600 | * power state change. | |
601 | */ | |
70a3341a | 602 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
603 | { |
604 | struct mmc_ios *ios = &host->mmc->ios; | |
3796fb8a | 605 | u32 hctl, capa; |
11dd62a7 DK |
606 | unsigned long timeout; |
607 | ||
6c31b215 V |
608 | if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) |
609 | return 1; | |
11dd62a7 | 610 | |
0a82e06e TL |
611 | if (host->con == OMAP_HSMMC_READ(host->base, CON) && |
612 | host->hctl == OMAP_HSMMC_READ(host->base, HCTL) && | |
613 | host->sysctl == OMAP_HSMMC_READ(host->base, SYSCTL) && | |
614 | host->capa == OMAP_HSMMC_READ(host->base, CAPA)) | |
615 | return 0; | |
616 | ||
617 | host->context_loss++; | |
618 | ||
c2200efb | 619 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
11dd62a7 DK |
620 | if (host->power_mode != MMC_POWER_OFF && |
621 | (1 << ios->vdd) <= MMC_VDD_23_24) | |
622 | hctl = SDVS18; | |
623 | else | |
624 | hctl = SDVS30; | |
625 | capa = VS30 | VS18; | |
626 | } else { | |
627 | hctl = SDVS18; | |
628 | capa = VS18; | |
629 | } | |
630 | ||
631 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
632 | OMAP_HSMMC_READ(host->base, HCTL) | hctl); | |
633 | ||
634 | OMAP_HSMMC_WRITE(host->base, CAPA, | |
635 | OMAP_HSMMC_READ(host->base, CAPA) | capa); | |
636 | ||
637 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
638 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
639 | ||
640 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
641 | while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP | |
642 | && time_before(jiffies, timeout)) | |
643 | ; | |
644 | ||
b417577d | 645 | omap_hsmmc_disable_irq(host); |
11dd62a7 DK |
646 | |
647 | /* Do not initialize card-specific things if the power is off */ | |
648 | if (host->power_mode == MMC_POWER_OFF) | |
649 | goto out; | |
650 | ||
3796fb8a | 651 | omap_hsmmc_set_bus_width(host); |
11dd62a7 | 652 | |
5934df2f | 653 | omap_hsmmc_set_clock(host); |
11dd62a7 | 654 | |
3796fb8a AS |
655 | omap_hsmmc_set_bus_mode(host); |
656 | ||
11dd62a7 | 657 | out: |
0a82e06e TL |
658 | dev_dbg(mmc_dev(host->mmc), "context is restored: restore count %d\n", |
659 | host->context_loss); | |
11dd62a7 DK |
660 | return 0; |
661 | } | |
662 | ||
663 | /* | |
664 | * Save the MMC host context (store the number of power state changes so far). | |
665 | */ | |
70a3341a | 666 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 | 667 | { |
0a82e06e TL |
668 | host->con = OMAP_HSMMC_READ(host->base, CON); |
669 | host->hctl = OMAP_HSMMC_READ(host->base, HCTL); | |
670 | host->sysctl = OMAP_HSMMC_READ(host->base, SYSCTL); | |
671 | host->capa = OMAP_HSMMC_READ(host->base, CAPA); | |
11dd62a7 DK |
672 | } |
673 | ||
674 | #else | |
675 | ||
70a3341a | 676 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
677 | { |
678 | return 0; | |
679 | } | |
680 | ||
70a3341a | 681 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
682 | { |
683 | } | |
684 | ||
685 | #endif | |
686 | ||
a45c6cb8 MC |
687 | /* |
688 | * Send init stream sequence to card | |
689 | * before sending IDLE command | |
690 | */ | |
70a3341a | 691 | static void send_init_stream(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
692 | { |
693 | int reg = 0; | |
694 | unsigned long timeout; | |
695 | ||
b62f6228 AH |
696 | if (host->protect_card) |
697 | return; | |
698 | ||
a45c6cb8 | 699 | disable_irq(host->irq); |
b417577d AH |
700 | |
701 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
a45c6cb8 MC |
702 | OMAP_HSMMC_WRITE(host->base, CON, |
703 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); | |
704 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); | |
705 | ||
706 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
a7e96879 V |
707 | while ((reg != CC_EN) && time_before(jiffies, timeout)) |
708 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; | |
a45c6cb8 MC |
709 | |
710 | OMAP_HSMMC_WRITE(host->base, CON, | |
711 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); | |
c653a6d4 AH |
712 | |
713 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
714 | OMAP_HSMMC_READ(host->base, STAT); | |
715 | ||
a45c6cb8 MC |
716 | enable_irq(host->irq); |
717 | } | |
718 | ||
719 | static inline | |
70a3341a | 720 | int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
721 | { |
722 | int r = 1; | |
723 | ||
191d1f1d DK |
724 | if (mmc_slot(host).get_cover_state) |
725 | r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); | |
a45c6cb8 MC |
726 | return r; |
727 | } | |
728 | ||
729 | static ssize_t | |
70a3341a | 730 | omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
731 | char *buf) |
732 | { | |
733 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 734 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 735 | |
70a3341a DK |
736 | return sprintf(buf, "%s\n", |
737 | omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); | |
a45c6cb8 MC |
738 | } |
739 | ||
70a3341a | 740 | static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); |
a45c6cb8 MC |
741 | |
742 | static ssize_t | |
70a3341a | 743 | omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
744 | char *buf) |
745 | { | |
746 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 747 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 748 | |
191d1f1d | 749 | return sprintf(buf, "%s\n", mmc_slot(host).name); |
a45c6cb8 MC |
750 | } |
751 | ||
70a3341a | 752 | static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); |
a45c6cb8 MC |
753 | |
754 | /* | |
755 | * Configure the response type and send the cmd. | |
756 | */ | |
757 | static void | |
70a3341a | 758 | omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, |
a45c6cb8 MC |
759 | struct mmc_data *data) |
760 | { | |
761 | int cmdreg = 0, resptype = 0, cmdtype = 0; | |
762 | ||
8986d31b | 763 | dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", |
a45c6cb8 MC |
764 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); |
765 | host->cmd = cmd; | |
766 | ||
93caf8e6 | 767 | omap_hsmmc_enable_irq(host, cmd); |
a45c6cb8 | 768 | |
4a694dc9 | 769 | host->response_busy = 0; |
a45c6cb8 MC |
770 | if (cmd->flags & MMC_RSP_PRESENT) { |
771 | if (cmd->flags & MMC_RSP_136) | |
772 | resptype = 1; | |
4a694dc9 AH |
773 | else if (cmd->flags & MMC_RSP_BUSY) { |
774 | resptype = 3; | |
775 | host->response_busy = 1; | |
776 | } else | |
a45c6cb8 MC |
777 | resptype = 2; |
778 | } | |
779 | ||
780 | /* | |
781 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on | |
782 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need | |
783 | * a val of 0x3, rest 0x0. | |
784 | */ | |
785 | if (cmd == host->mrq->stop) | |
786 | cmdtype = 0x3; | |
787 | ||
788 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); | |
789 | ||
790 | if (data) { | |
791 | cmdreg |= DP_SELECT | MSBS | BCE; | |
792 | if (data->flags & MMC_DATA_READ) | |
793 | cmdreg |= DDIR; | |
794 | else | |
795 | cmdreg &= ~(DDIR); | |
796 | } | |
797 | ||
798 | if (host->use_dma) | |
a7e96879 | 799 | cmdreg |= DMAE; |
a45c6cb8 | 800 | |
b417577d | 801 | host->req_in_progress = 1; |
4dffd7a2 | 802 | |
a45c6cb8 MC |
803 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); |
804 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); | |
805 | } | |
806 | ||
0ccd76d4 | 807 | static int |
70a3341a | 808 | omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) |
0ccd76d4 JY |
809 | { |
810 | if (data->flags & MMC_DATA_WRITE) | |
811 | return DMA_TO_DEVICE; | |
812 | else | |
813 | return DMA_FROM_DEVICE; | |
814 | } | |
815 | ||
c5c98927 RK |
816 | static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, |
817 | struct mmc_data *data) | |
818 | { | |
819 | return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; | |
820 | } | |
821 | ||
b417577d AH |
822 | static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) |
823 | { | |
824 | int dma_ch; | |
31463b14 | 825 | unsigned long flags; |
b417577d | 826 | |
31463b14 | 827 | spin_lock_irqsave(&host->irq_lock, flags); |
b417577d AH |
828 | host->req_in_progress = 0; |
829 | dma_ch = host->dma_ch; | |
31463b14 | 830 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
831 | |
832 | omap_hsmmc_disable_irq(host); | |
833 | /* Do not complete the request if DMA is still in progress */ | |
834 | if (mrq->data && host->use_dma && dma_ch != -1) | |
835 | return; | |
836 | host->mrq = NULL; | |
837 | mmc_request_done(host->mmc, mrq); | |
838 | } | |
839 | ||
a45c6cb8 MC |
840 | /* |
841 | * Notify the transfer complete to MMC core | |
842 | */ | |
843 | static void | |
70a3341a | 844 | omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) |
a45c6cb8 | 845 | { |
4a694dc9 AH |
846 | if (!data) { |
847 | struct mmc_request *mrq = host->mrq; | |
848 | ||
23050103 AH |
849 | /* TC before CC from CMD6 - don't know why, but it happens */ |
850 | if (host->cmd && host->cmd->opcode == 6 && | |
851 | host->response_busy) { | |
852 | host->response_busy = 0; | |
853 | return; | |
854 | } | |
855 | ||
b417577d | 856 | omap_hsmmc_request_done(host, mrq); |
4a694dc9 AH |
857 | return; |
858 | } | |
859 | ||
a45c6cb8 MC |
860 | host->data = NULL; |
861 | ||
a45c6cb8 MC |
862 | if (!data->error) |
863 | data->bytes_xfered += data->blocks * (data->blksz); | |
864 | else | |
865 | data->bytes_xfered = 0; | |
866 | ||
fe852273 | 867 | if (!data->stop) { |
b417577d | 868 | omap_hsmmc_request_done(host, data->mrq); |
fe852273 | 869 | return; |
a45c6cb8 | 870 | } |
fe852273 | 871 | omap_hsmmc_start_command(host, data->stop, NULL); |
a45c6cb8 MC |
872 | } |
873 | ||
874 | /* | |
875 | * Notify the core about command completion | |
876 | */ | |
877 | static void | |
70a3341a | 878 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) |
a45c6cb8 MC |
879 | { |
880 | host->cmd = NULL; | |
881 | ||
882 | if (cmd->flags & MMC_RSP_PRESENT) { | |
883 | if (cmd->flags & MMC_RSP_136) { | |
884 | /* response type 2 */ | |
885 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); | |
886 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); | |
887 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); | |
888 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); | |
889 | } else { | |
890 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
891 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); | |
892 | } | |
893 | } | |
b417577d AH |
894 | if ((host->data == NULL && !host->response_busy) || cmd->error) |
895 | omap_hsmmc_request_done(host, cmd->mrq); | |
a45c6cb8 MC |
896 | } |
897 | ||
898 | /* | |
899 | * DMA clean up for command errors | |
900 | */ | |
70a3341a | 901 | static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) |
a45c6cb8 | 902 | { |
b417577d | 903 | int dma_ch; |
31463b14 | 904 | unsigned long flags; |
b417577d | 905 | |
82788ff5 | 906 | host->data->error = errno; |
a45c6cb8 | 907 | |
31463b14 | 908 | spin_lock_irqsave(&host->irq_lock, flags); |
b417577d AH |
909 | dma_ch = host->dma_ch; |
910 | host->dma_ch = -1; | |
31463b14 | 911 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
912 | |
913 | if (host->use_dma && dma_ch != -1) { | |
c5c98927 RK |
914 | struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); |
915 | ||
916 | dmaengine_terminate_all(chan); | |
917 | dma_unmap_sg(chan->device->dev, | |
918 | host->data->sg, host->data->sg_len, | |
70a3341a | 919 | omap_hsmmc_get_dma_dir(host, host->data)); |
c5c98927 | 920 | |
053bf34f | 921 | host->data->host_cookie = 0; |
a45c6cb8 MC |
922 | } |
923 | host->data = NULL; | |
a45c6cb8 MC |
924 | } |
925 | ||
926 | /* | |
927 | * Readable error output | |
928 | */ | |
929 | #ifdef CONFIG_MMC_DEBUG | |
699b958b | 930 | static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) |
a45c6cb8 MC |
931 | { |
932 | /* --- means reserved bit without definition at documentation */ | |
70a3341a | 933 | static const char *omap_hsmmc_status_bits[] = { |
699b958b AH |
934 | "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , |
935 | "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", | |
936 | "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , | |
937 | "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" | |
a45c6cb8 MC |
938 | }; |
939 | char res[256]; | |
940 | char *buf = res; | |
941 | int len, i; | |
942 | ||
943 | len = sprintf(buf, "MMC IRQ 0x%x :", status); | |
944 | buf += len; | |
945 | ||
70a3341a | 946 | for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) |
a45c6cb8 | 947 | if (status & (1 << i)) { |
70a3341a | 948 | len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); |
a45c6cb8 MC |
949 | buf += len; |
950 | } | |
951 | ||
8986d31b | 952 | dev_vdbg(mmc_dev(host->mmc), "%s\n", res); |
a45c6cb8 | 953 | } |
699b958b AH |
954 | #else |
955 | static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, | |
956 | u32 status) | |
957 | { | |
958 | } | |
a45c6cb8 MC |
959 | #endif /* CONFIG_MMC_DEBUG */ |
960 | ||
3ebf74b1 JP |
961 | /* |
962 | * MMC controller internal state machines reset | |
963 | * | |
964 | * Used to reset command or data internal state machines, using respectively | |
965 | * SRC or SRD bit of SYSCTL register | |
966 | * Can be called from interrupt context | |
967 | */ | |
70a3341a DK |
968 | static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, |
969 | unsigned long bit) | |
3ebf74b1 JP |
970 | { |
971 | unsigned long i = 0; | |
1e881786 | 972 | unsigned long limit = MMC_TIMEOUT_US; |
3ebf74b1 JP |
973 | |
974 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
975 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); | |
976 | ||
07ad64b6 MC |
977 | /* |
978 | * OMAP4 ES2 and greater has an updated reset logic. | |
979 | * Monitor a 0->1 transition first | |
980 | */ | |
981 | if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { | |
b432b4b3 | 982 | while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) |
07ad64b6 | 983 | && (i++ < limit)) |
1e881786 | 984 | udelay(1); |
07ad64b6 MC |
985 | } |
986 | i = 0; | |
987 | ||
3ebf74b1 JP |
988 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && |
989 | (i++ < limit)) | |
1e881786 | 990 | udelay(1); |
3ebf74b1 JP |
991 | |
992 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) | |
993 | dev_err(mmc_dev(host->mmc), | |
994 | "Timeout waiting on controller reset in %s\n", | |
995 | __func__); | |
996 | } | |
a45c6cb8 | 997 | |
25e1897b B |
998 | static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, |
999 | int err, int end_cmd) | |
ae4bf788 | 1000 | { |
25e1897b | 1001 | if (end_cmd) { |
94d4f272 | 1002 | omap_hsmmc_reset_controller_fsm(host, SRC); |
25e1897b B |
1003 | if (host->cmd) |
1004 | host->cmd->error = err; | |
1005 | } | |
ae4bf788 V |
1006 | |
1007 | if (host->data) { | |
1008 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
1009 | omap_hsmmc_dma_cleanup(host, err); | |
dc7745bd B |
1010 | } else if (host->mrq && host->mrq->cmd) |
1011 | host->mrq->cmd->error = err; | |
ae4bf788 V |
1012 | } |
1013 | ||
b417577d | 1014 | static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) |
a45c6cb8 | 1015 | { |
a45c6cb8 | 1016 | struct mmc_data *data; |
b417577d AH |
1017 | int end_cmd = 0, end_trans = 0; |
1018 | ||
a45c6cb8 | 1019 | data = host->data; |
8986d31b | 1020 | dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); |
a45c6cb8 | 1021 | |
a7e96879 | 1022 | if (status & ERR_EN) { |
699b958b | 1023 | omap_hsmmc_dbg_report_irq(host, status); |
25e1897b | 1024 | |
a7e96879 | 1025 | if (status & (CTO_EN | CCRC_EN)) |
25e1897b | 1026 | end_cmd = 1; |
a7e96879 | 1027 | if (status & (CTO_EN | DTO_EN)) |
25e1897b | 1028 | hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); |
a7e96879 | 1029 | else if (status & (CCRC_EN | DCRC_EN)) |
25e1897b | 1030 | hsmmc_command_incomplete(host, -EILSEQ, end_cmd); |
ae4bf788 | 1031 | |
ae4bf788 | 1032 | if (host->data || host->response_busy) { |
25e1897b | 1033 | end_trans = !end_cmd; |
ae4bf788 | 1034 | host->response_busy = 0; |
a45c6cb8 MC |
1035 | } |
1036 | } | |
1037 | ||
7472bab2 | 1038 | OMAP_HSMMC_WRITE(host->base, STAT, status); |
a7e96879 | 1039 | if (end_cmd || ((status & CC_EN) && host->cmd)) |
70a3341a | 1040 | omap_hsmmc_cmd_done(host, host->cmd); |
a7e96879 | 1041 | if ((end_trans || (status & TC_EN)) && host->mrq) |
70a3341a | 1042 | omap_hsmmc_xfer_done(host, data); |
b417577d | 1043 | } |
a45c6cb8 | 1044 | |
b417577d AH |
1045 | /* |
1046 | * MMC controller IRQ handler | |
1047 | */ | |
1048 | static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) | |
1049 | { | |
1050 | struct omap_hsmmc_host *host = dev_id; | |
1051 | int status; | |
1052 | ||
1053 | status = OMAP_HSMMC_READ(host->base, STAT); | |
1f6b9fa4 | 1054 | while (status & INT_EN_MASK && host->req_in_progress) { |
b417577d | 1055 | omap_hsmmc_do_irq(host, status); |
1f6b9fa4 | 1056 | |
b417577d AH |
1057 | /* Flush posted write */ |
1058 | status = OMAP_HSMMC_READ(host->base, STAT); | |
1f6b9fa4 | 1059 | } |
4dffd7a2 | 1060 | |
a45c6cb8 MC |
1061 | return IRQ_HANDLED; |
1062 | } | |
1063 | ||
70a3341a | 1064 | static void set_sd_bus_power(struct omap_hsmmc_host *host) |
e13bb300 AH |
1065 | { |
1066 | unsigned long i; | |
1067 | ||
1068 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
1069 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
1070 | for (i = 0; i < loops_per_jiffy; i++) { | |
1071 | if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) | |
1072 | break; | |
1073 | cpu_relax(); | |
1074 | } | |
1075 | } | |
1076 | ||
a45c6cb8 | 1077 | /* |
eb250826 DB |
1078 | * Switch MMC interface voltage ... only relevant for MMC1. |
1079 | * | |
1080 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. | |
1081 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. | |
1082 | * Some chips, like eMMC ones, use internal transceivers. | |
a45c6cb8 | 1083 | */ |
70a3341a | 1084 | static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) |
a45c6cb8 MC |
1085 | { |
1086 | u32 reg_val = 0; | |
1087 | int ret; | |
1088 | ||
1089 | /* Disable the clocks */ | |
fa4aa2d4 | 1090 | pm_runtime_put_sync(host->dev); |
cd03d9a8 | 1091 | if (host->dbclk) |
94c18149 | 1092 | clk_disable_unprepare(host->dbclk); |
a45c6cb8 MC |
1093 | |
1094 | /* Turn the power off */ | |
1095 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); | |
a45c6cb8 MC |
1096 | |
1097 | /* Turn the power ON with given VDD 1.8 or 3.0v */ | |
2bec0893 AH |
1098 | if (!ret) |
1099 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, | |
1100 | vdd); | |
fa4aa2d4 | 1101 | pm_runtime_get_sync(host->dev); |
cd03d9a8 | 1102 | if (host->dbclk) |
94c18149 | 1103 | clk_prepare_enable(host->dbclk); |
2bec0893 | 1104 | |
a45c6cb8 MC |
1105 | if (ret != 0) |
1106 | goto err; | |
1107 | ||
a45c6cb8 MC |
1108 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1109 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); | |
1110 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); | |
eb250826 | 1111 | |
a45c6cb8 MC |
1112 | /* |
1113 | * If a MMC dual voltage card is detected, the set_ios fn calls | |
1114 | * this fn with VDD bit set for 1.8V. Upon card removal from the | |
70a3341a | 1115 | * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. |
a45c6cb8 | 1116 | * |
eb250826 DB |
1117 | * Cope with a bit of slop in the range ... per data sheets: |
1118 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, | |
1119 | * but recommended values are 1.71V to 1.89V | |
1120 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, | |
1121 | * but recommended values are 2.7V to 3.3V | |
1122 | * | |
1123 | * Board setup code shouldn't permit anything very out-of-range. | |
1124 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the | |
1125 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. | |
a45c6cb8 | 1126 | */ |
eb250826 | 1127 | if ((1 << vdd) <= MMC_VDD_23_24) |
a45c6cb8 | 1128 | reg_val |= SDVS18; |
eb250826 DB |
1129 | else |
1130 | reg_val |= SDVS30; | |
a45c6cb8 MC |
1131 | |
1132 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); | |
e13bb300 | 1133 | set_sd_bus_power(host); |
a45c6cb8 MC |
1134 | |
1135 | return 0; | |
1136 | err: | |
b1e056ae | 1137 | dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); |
a45c6cb8 MC |
1138 | return ret; |
1139 | } | |
1140 | ||
b62f6228 AH |
1141 | /* Protect the card while the cover is open */ |
1142 | static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) | |
1143 | { | |
1144 | if (!mmc_slot(host).get_cover_state) | |
1145 | return; | |
1146 | ||
1147 | host->reqs_blocked = 0; | |
1148 | if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { | |
1149 | if (host->protect_card) { | |
2cecdf00 | 1150 | dev_info(host->dev, "%s: cover is closed, " |
b62f6228 AH |
1151 | "card is now accessible\n", |
1152 | mmc_hostname(host->mmc)); | |
1153 | host->protect_card = 0; | |
1154 | } | |
1155 | } else { | |
1156 | if (!host->protect_card) { | |
2cecdf00 | 1157 | dev_info(host->dev, "%s: cover is open, " |
b62f6228 AH |
1158 | "card is now inaccessible\n", |
1159 | mmc_hostname(host->mmc)); | |
1160 | host->protect_card = 1; | |
1161 | } | |
1162 | } | |
1163 | } | |
1164 | ||
a45c6cb8 | 1165 | /* |
7efab4f3 | 1166 | * irq handler to notify the core about card insertion/removal |
a45c6cb8 | 1167 | */ |
7efab4f3 | 1168 | static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) |
a45c6cb8 | 1169 | { |
7efab4f3 | 1170 | struct omap_hsmmc_host *host = dev_id; |
249d0fa9 | 1171 | struct omap_mmc_slot_data *slot = &mmc_slot(host); |
a6b2240d AH |
1172 | int carddetect; |
1173 | ||
a6b2240d | 1174 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); |
249d0fa9 | 1175 | |
191d1f1d | 1176 | if (slot->card_detect) |
db0fefc5 | 1177 | carddetect = slot->card_detect(host->dev, host->slot_id); |
b62f6228 AH |
1178 | else { |
1179 | omap_hsmmc_protect_card(host); | |
a6b2240d | 1180 | carddetect = -ENOSYS; |
b62f6228 | 1181 | } |
a45c6cb8 | 1182 | |
cdeebadd | 1183 | if (carddetect) |
a45c6cb8 | 1184 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); |
cdeebadd | 1185 | else |
a45c6cb8 | 1186 | mmc_detect_change(host->mmc, (HZ * 50) / 1000); |
a45c6cb8 MC |
1187 | return IRQ_HANDLED; |
1188 | } | |
1189 | ||
c5c98927 | 1190 | static void omap_hsmmc_dma_callback(void *param) |
a45c6cb8 | 1191 | { |
c5c98927 RK |
1192 | struct omap_hsmmc_host *host = param; |
1193 | struct dma_chan *chan; | |
770d7432 | 1194 | struct mmc_data *data; |
c5c98927 | 1195 | int req_in_progress; |
a45c6cb8 | 1196 | |
c5c98927 | 1197 | spin_lock_irq(&host->irq_lock); |
b417577d | 1198 | if (host->dma_ch < 0) { |
c5c98927 | 1199 | spin_unlock_irq(&host->irq_lock); |
a45c6cb8 | 1200 | return; |
b417577d | 1201 | } |
a45c6cb8 | 1202 | |
770d7432 | 1203 | data = host->mrq->data; |
c5c98927 | 1204 | chan = omap_hsmmc_get_dma_chan(host, data); |
9782aff8 | 1205 | if (!data->host_cookie) |
c5c98927 RK |
1206 | dma_unmap_sg(chan->device->dev, |
1207 | data->sg, data->sg_len, | |
9782aff8 | 1208 | omap_hsmmc_get_dma_dir(host, data)); |
b417577d AH |
1209 | |
1210 | req_in_progress = host->req_in_progress; | |
a45c6cb8 | 1211 | host->dma_ch = -1; |
c5c98927 | 1212 | spin_unlock_irq(&host->irq_lock); |
b417577d AH |
1213 | |
1214 | /* If DMA has finished after TC, complete the request */ | |
1215 | if (!req_in_progress) { | |
1216 | struct mmc_request *mrq = host->mrq; | |
1217 | ||
1218 | host->mrq = NULL; | |
1219 | mmc_request_done(host->mmc, mrq); | |
1220 | } | |
a45c6cb8 MC |
1221 | } |
1222 | ||
9782aff8 PF |
1223 | static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, |
1224 | struct mmc_data *data, | |
c5c98927 | 1225 | struct omap_hsmmc_next *next, |
26b88520 | 1226 | struct dma_chan *chan) |
9782aff8 PF |
1227 | { |
1228 | int dma_len; | |
1229 | ||
1230 | if (!next && data->host_cookie && | |
1231 | data->host_cookie != host->next_data.cookie) { | |
2cecdf00 | 1232 | dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" |
9782aff8 PF |
1233 | " host->next_data.cookie %d\n", |
1234 | __func__, data->host_cookie, host->next_data.cookie); | |
1235 | data->host_cookie = 0; | |
1236 | } | |
1237 | ||
1238 | /* Check if next job is already prepared */ | |
b38313d6 | 1239 | if (next || data->host_cookie != host->next_data.cookie) { |
26b88520 | 1240 | dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, |
9782aff8 PF |
1241 | omap_hsmmc_get_dma_dir(host, data)); |
1242 | ||
1243 | } else { | |
1244 | dma_len = host->next_data.dma_len; | |
1245 | host->next_data.dma_len = 0; | |
1246 | } | |
1247 | ||
1248 | ||
1249 | if (dma_len == 0) | |
1250 | return -EINVAL; | |
1251 | ||
1252 | if (next) { | |
1253 | next->dma_len = dma_len; | |
1254 | data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; | |
1255 | } else | |
1256 | host->dma_len = dma_len; | |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
a45c6cb8 MC |
1261 | /* |
1262 | * Routine to configure and start DMA for the MMC card | |
1263 | */ | |
70a3341a DK |
1264 | static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, |
1265 | struct mmc_request *req) | |
a45c6cb8 | 1266 | { |
26b88520 RK |
1267 | struct dma_slave_config cfg; |
1268 | struct dma_async_tx_descriptor *tx; | |
1269 | int ret = 0, i; | |
a45c6cb8 | 1270 | struct mmc_data *data = req->data; |
c5c98927 | 1271 | struct dma_chan *chan; |
a45c6cb8 | 1272 | |
0ccd76d4 | 1273 | /* Sanity check: all the SG entries must be aligned by block size. */ |
a3f406f8 | 1274 | for (i = 0; i < data->sg_len; i++) { |
0ccd76d4 JY |
1275 | struct scatterlist *sgl; |
1276 | ||
1277 | sgl = data->sg + i; | |
1278 | if (sgl->length % data->blksz) | |
1279 | return -EINVAL; | |
1280 | } | |
1281 | if ((data->blksz % 4) != 0) | |
1282 | /* REVISIT: The MMC buffer increments only when MSB is written. | |
1283 | * Return error for blksz which is non multiple of four. | |
1284 | */ | |
1285 | return -EINVAL; | |
1286 | ||
b417577d | 1287 | BUG_ON(host->dma_ch != -1); |
a45c6cb8 | 1288 | |
c5c98927 | 1289 | chan = omap_hsmmc_get_dma_chan(host, data); |
c5c98927 | 1290 | |
26b88520 RK |
1291 | cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; |
1292 | cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; | |
1293 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1294 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1295 | cfg.src_maxburst = data->blksz / 4; | |
1296 | cfg.dst_maxburst = data->blksz / 4; | |
c5c98927 | 1297 | |
26b88520 RK |
1298 | ret = dmaengine_slave_config(chan, &cfg); |
1299 | if (ret) | |
a45c6cb8 | 1300 | return ret; |
c5c98927 | 1301 | |
26b88520 | 1302 | ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); |
9782aff8 PF |
1303 | if (ret) |
1304 | return ret; | |
a45c6cb8 | 1305 | |
26b88520 RK |
1306 | tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, |
1307 | data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
1308 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1309 | if (!tx) { | |
1310 | dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); | |
1311 | /* FIXME: cleanup */ | |
1312 | return -1; | |
1313 | } | |
a45c6cb8 | 1314 | |
26b88520 RK |
1315 | tx->callback = omap_hsmmc_dma_callback; |
1316 | tx->callback_param = host; | |
a45c6cb8 | 1317 | |
26b88520 RK |
1318 | /* Does not fail */ |
1319 | dmaengine_submit(tx); | |
c5c98927 | 1320 | |
26b88520 | 1321 | host->dma_ch = 1; |
c5c98927 | 1322 | |
26b88520 | 1323 | dma_async_issue_pending(chan); |
a45c6cb8 | 1324 | |
a45c6cb8 MC |
1325 | return 0; |
1326 | } | |
1327 | ||
70a3341a | 1328 | static void set_data_timeout(struct omap_hsmmc_host *host, |
e2bf08d6 AH |
1329 | unsigned int timeout_ns, |
1330 | unsigned int timeout_clks) | |
a45c6cb8 MC |
1331 | { |
1332 | unsigned int timeout, cycle_ns; | |
1333 | uint32_t reg, clkd, dto = 0; | |
1334 | ||
1335 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); | |
1336 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; | |
1337 | if (clkd == 0) | |
1338 | clkd = 1; | |
1339 | ||
1340 | cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); | |
e2bf08d6 AH |
1341 | timeout = timeout_ns / cycle_ns; |
1342 | timeout += timeout_clks; | |
a45c6cb8 MC |
1343 | if (timeout) { |
1344 | while ((timeout & 0x80000000) == 0) { | |
1345 | dto += 1; | |
1346 | timeout <<= 1; | |
1347 | } | |
1348 | dto = 31 - dto; | |
1349 | timeout <<= 1; | |
1350 | if (timeout && dto) | |
1351 | dto += 1; | |
1352 | if (dto >= 13) | |
1353 | dto -= 13; | |
1354 | else | |
1355 | dto = 0; | |
1356 | if (dto > 14) | |
1357 | dto = 14; | |
1358 | } | |
1359 | ||
1360 | reg &= ~DTO_MASK; | |
1361 | reg |= dto << DTO_SHIFT; | |
1362 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); | |
1363 | } | |
1364 | ||
1365 | /* | |
1366 | * Configure block length for MMC/SD cards and initiate the transfer. | |
1367 | */ | |
1368 | static int | |
70a3341a | 1369 | omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) |
a45c6cb8 MC |
1370 | { |
1371 | int ret; | |
1372 | host->data = req->data; | |
1373 | ||
1374 | if (req->data == NULL) { | |
a45c6cb8 | 1375 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
e2bf08d6 AH |
1376 | /* |
1377 | * Set an arbitrary 100ms data timeout for commands with | |
1378 | * busy signal. | |
1379 | */ | |
1380 | if (req->cmd->flags & MMC_RSP_BUSY) | |
1381 | set_data_timeout(host, 100000000U, 0); | |
a45c6cb8 MC |
1382 | return 0; |
1383 | } | |
1384 | ||
1385 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) | |
1386 | | (req->data->blocks << 16)); | |
e2bf08d6 | 1387 | set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); |
a45c6cb8 | 1388 | |
a45c6cb8 | 1389 | if (host->use_dma) { |
70a3341a | 1390 | ret = omap_hsmmc_start_dma_transfer(host, req); |
a45c6cb8 | 1391 | if (ret != 0) { |
b1e056ae | 1392 | dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); |
a45c6cb8 MC |
1393 | return ret; |
1394 | } | |
1395 | } | |
1396 | return 0; | |
1397 | } | |
1398 | ||
9782aff8 PF |
1399 | static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
1400 | int err) | |
1401 | { | |
1402 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1403 | struct mmc_data *data = mrq->data; | |
1404 | ||
26b88520 | 1405 | if (host->use_dma && data->host_cookie) { |
c5c98927 | 1406 | struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); |
c5c98927 | 1407 | |
26b88520 RK |
1408 | dma_unmap_sg(c->device->dev, data->sg, data->sg_len, |
1409 | omap_hsmmc_get_dma_dir(host, data)); | |
9782aff8 PF |
1410 | data->host_cookie = 0; |
1411 | } | |
1412 | } | |
1413 | ||
1414 | static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, | |
1415 | bool is_first_req) | |
1416 | { | |
1417 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1418 | ||
1419 | if (mrq->data->host_cookie) { | |
1420 | mrq->data->host_cookie = 0; | |
1421 | return ; | |
1422 | } | |
1423 | ||
c5c98927 RK |
1424 | if (host->use_dma) { |
1425 | struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); | |
c5c98927 | 1426 | |
9782aff8 | 1427 | if (omap_hsmmc_pre_dma_transfer(host, mrq->data, |
26b88520 | 1428 | &host->next_data, c)) |
9782aff8 | 1429 | mrq->data->host_cookie = 0; |
c5c98927 | 1430 | } |
9782aff8 PF |
1431 | } |
1432 | ||
a45c6cb8 MC |
1433 | /* |
1434 | * Request function. for read/write operation | |
1435 | */ | |
70a3341a | 1436 | static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) |
a45c6cb8 | 1437 | { |
70a3341a | 1438 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3f406f8 | 1439 | int err; |
a45c6cb8 | 1440 | |
b417577d AH |
1441 | BUG_ON(host->req_in_progress); |
1442 | BUG_ON(host->dma_ch != -1); | |
1443 | if (host->protect_card) { | |
1444 | if (host->reqs_blocked < 3) { | |
1445 | /* | |
1446 | * Ensure the controller is left in a consistent | |
1447 | * state by resetting the command and data state | |
1448 | * machines. | |
1449 | */ | |
1450 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
1451 | omap_hsmmc_reset_controller_fsm(host, SRC); | |
1452 | host->reqs_blocked += 1; | |
1453 | } | |
1454 | req->cmd->error = -EBADF; | |
1455 | if (req->data) | |
1456 | req->data->error = -EBADF; | |
1457 | req->cmd->retries = 0; | |
1458 | mmc_request_done(mmc, req); | |
1459 | return; | |
1460 | } else if (host->reqs_blocked) | |
1461 | host->reqs_blocked = 0; | |
a45c6cb8 MC |
1462 | WARN_ON(host->mrq != NULL); |
1463 | host->mrq = req; | |
70a3341a | 1464 | err = omap_hsmmc_prepare_data(host, req); |
a3f406f8 JL |
1465 | if (err) { |
1466 | req->cmd->error = err; | |
1467 | if (req->data) | |
1468 | req->data->error = err; | |
1469 | host->mrq = NULL; | |
1470 | mmc_request_done(mmc, req); | |
1471 | return; | |
1472 | } | |
1473 | ||
70a3341a | 1474 | omap_hsmmc_start_command(host, req->cmd, req->data); |
a45c6cb8 MC |
1475 | } |
1476 | ||
a45c6cb8 | 1477 | /* Routine to configure clock values. Exposed API to core */ |
70a3341a | 1478 | static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
a45c6cb8 | 1479 | { |
70a3341a | 1480 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3621465 | 1481 | int do_send_init_stream = 0; |
a45c6cb8 | 1482 | |
fa4aa2d4 | 1483 | pm_runtime_get_sync(host->dev); |
5e2ea617 | 1484 | |
a3621465 AH |
1485 | if (ios->power_mode != host->power_mode) { |
1486 | switch (ios->power_mode) { | |
1487 | case MMC_POWER_OFF: | |
1488 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1489 | 0, 0); | |
1490 | break; | |
1491 | case MMC_POWER_UP: | |
1492 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1493 | 1, ios->vdd); | |
1494 | break; | |
1495 | case MMC_POWER_ON: | |
1496 | do_send_init_stream = 1; | |
1497 | break; | |
1498 | } | |
1499 | host->power_mode = ios->power_mode; | |
a45c6cb8 MC |
1500 | } |
1501 | ||
dd498eff DK |
1502 | /* FIXME: set registers based only on changes to ios */ |
1503 | ||
3796fb8a | 1504 | omap_hsmmc_set_bus_width(host); |
a45c6cb8 | 1505 | |
4621d5f8 | 1506 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
eb250826 DB |
1507 | /* Only MMC1 can interface at 3V without some flavor |
1508 | * of external transceiver; but they all handle 1.8V. | |
1509 | */ | |
a45c6cb8 | 1510 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
1f84b71b RN |
1511 | (ios->vdd == DUAL_VOLT_OCR_BIT) && |
1512 | /* | |
1513 | * With pbias cell programming missing, this | |
cf5ae40b | 1514 | * can't be allowed on MMC1 when booting with device |
1f84b71b RN |
1515 | * tree. |
1516 | */ | |
cf5ae40b | 1517 | !host->pbias_disable) { |
a45c6cb8 MC |
1518 | /* |
1519 | * The mmc_select_voltage fn of the core does | |
1520 | * not seem to set the power_mode to | |
1521 | * MMC_POWER_UP upon recalculating the voltage. | |
1522 | * vdd 1.8v. | |
1523 | */ | |
70a3341a DK |
1524 | if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) |
1525 | dev_dbg(mmc_dev(host->mmc), | |
a45c6cb8 MC |
1526 | "Switch operation failed\n"); |
1527 | } | |
1528 | } | |
1529 | ||
5934df2f | 1530 | omap_hsmmc_set_clock(host); |
a45c6cb8 | 1531 | |
a3621465 | 1532 | if (do_send_init_stream) |
a45c6cb8 MC |
1533 | send_init_stream(host); |
1534 | ||
3796fb8a | 1535 | omap_hsmmc_set_bus_mode(host); |
5e2ea617 | 1536 | |
fa4aa2d4 | 1537 | pm_runtime_put_autosuspend(host->dev); |
a45c6cb8 MC |
1538 | } |
1539 | ||
1540 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) | |
1541 | { | |
70a3341a | 1542 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1543 | |
191d1f1d | 1544 | if (!mmc_slot(host).card_detect) |
a45c6cb8 | 1545 | return -ENOSYS; |
db0fefc5 | 1546 | return mmc_slot(host).card_detect(host->dev, host->slot_id); |
a45c6cb8 MC |
1547 | } |
1548 | ||
1549 | static int omap_hsmmc_get_ro(struct mmc_host *mmc) | |
1550 | { | |
70a3341a | 1551 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1552 | |
191d1f1d | 1553 | if (!mmc_slot(host).get_ro) |
a45c6cb8 | 1554 | return -ENOSYS; |
191d1f1d | 1555 | return mmc_slot(host).get_ro(host->dev, 0); |
a45c6cb8 MC |
1556 | } |
1557 | ||
4816858c GI |
1558 | static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) |
1559 | { | |
1560 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1561 | ||
1562 | if (mmc_slot(host).init_card) | |
1563 | mmc_slot(host).init_card(card); | |
1564 | } | |
1565 | ||
70a3341a | 1566 | static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) |
1b331e69 KK |
1567 | { |
1568 | u32 hctl, capa, value; | |
1569 | ||
1570 | /* Only MMC1 supports 3.0V */ | |
4621d5f8 | 1571 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
1b331e69 KK |
1572 | hctl = SDVS30; |
1573 | capa = VS30 | VS18; | |
1574 | } else { | |
1575 | hctl = SDVS18; | |
1576 | capa = VS18; | |
1577 | } | |
1578 | ||
1579 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; | |
1580 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); | |
1581 | ||
1582 | value = OMAP_HSMMC_READ(host->base, CAPA); | |
1583 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); | |
1584 | ||
1b331e69 | 1585 | /* Set SD bus power bit */ |
e13bb300 | 1586 | set_sd_bus_power(host); |
1b331e69 KK |
1587 | } |
1588 | ||
70a3341a | 1589 | static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) |
dd498eff | 1590 | { |
70a3341a | 1591 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1592 | |
fa4aa2d4 B |
1593 | pm_runtime_get_sync(host->dev); |
1594 | ||
dd498eff DK |
1595 | return 0; |
1596 | } | |
1597 | ||
907d2e7c | 1598 | static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) |
dd498eff | 1599 | { |
70a3341a | 1600 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1601 | |
fa4aa2d4 B |
1602 | pm_runtime_mark_last_busy(host->dev); |
1603 | pm_runtime_put_autosuspend(host->dev); | |
1604 | ||
dd498eff DK |
1605 | return 0; |
1606 | } | |
1607 | ||
70a3341a DK |
1608 | static const struct mmc_host_ops omap_hsmmc_ops = { |
1609 | .enable = omap_hsmmc_enable_fclk, | |
1610 | .disable = omap_hsmmc_disable_fclk, | |
9782aff8 PF |
1611 | .post_req = omap_hsmmc_post_req, |
1612 | .pre_req = omap_hsmmc_pre_req, | |
70a3341a DK |
1613 | .request = omap_hsmmc_request, |
1614 | .set_ios = omap_hsmmc_set_ios, | |
dd498eff DK |
1615 | .get_cd = omap_hsmmc_get_cd, |
1616 | .get_ro = omap_hsmmc_get_ro, | |
4816858c | 1617 | .init_card = omap_hsmmc_init_card, |
dd498eff DK |
1618 | /* NYET -- enable_sdio_irq */ |
1619 | }; | |
1620 | ||
d900f712 DK |
1621 | #ifdef CONFIG_DEBUG_FS |
1622 | ||
70a3341a | 1623 | static int omap_hsmmc_regs_show(struct seq_file *s, void *data) |
d900f712 DK |
1624 | { |
1625 | struct mmc_host *mmc = s->private; | |
70a3341a | 1626 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
d900f712 | 1627 | |
0a82e06e TL |
1628 | seq_printf(s, "mmc%d:\n ctx_loss:\t%d\n\nregs:\n", |
1629 | mmc->index, host->context_loss); | |
5e2ea617 | 1630 | |
fa4aa2d4 | 1631 | pm_runtime_get_sync(host->dev); |
d900f712 | 1632 | |
d900f712 DK |
1633 | seq_printf(s, "CON:\t\t0x%08x\n", |
1634 | OMAP_HSMMC_READ(host->base, CON)); | |
1635 | seq_printf(s, "HCTL:\t\t0x%08x\n", | |
1636 | OMAP_HSMMC_READ(host->base, HCTL)); | |
1637 | seq_printf(s, "SYSCTL:\t\t0x%08x\n", | |
1638 | OMAP_HSMMC_READ(host->base, SYSCTL)); | |
1639 | seq_printf(s, "IE:\t\t0x%08x\n", | |
1640 | OMAP_HSMMC_READ(host->base, IE)); | |
1641 | seq_printf(s, "ISE:\t\t0x%08x\n", | |
1642 | OMAP_HSMMC_READ(host->base, ISE)); | |
1643 | seq_printf(s, "CAPA:\t\t0x%08x\n", | |
1644 | OMAP_HSMMC_READ(host->base, CAPA)); | |
5e2ea617 | 1645 | |
fa4aa2d4 B |
1646 | pm_runtime_mark_last_busy(host->dev); |
1647 | pm_runtime_put_autosuspend(host->dev); | |
dd498eff | 1648 | |
d900f712 DK |
1649 | return 0; |
1650 | } | |
1651 | ||
70a3341a | 1652 | static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) |
d900f712 | 1653 | { |
70a3341a | 1654 | return single_open(file, omap_hsmmc_regs_show, inode->i_private); |
d900f712 DK |
1655 | } |
1656 | ||
1657 | static const struct file_operations mmc_regs_fops = { | |
70a3341a | 1658 | .open = omap_hsmmc_regs_open, |
d900f712 DK |
1659 | .read = seq_read, |
1660 | .llseek = seq_lseek, | |
1661 | .release = single_release, | |
1662 | }; | |
1663 | ||
70a3341a | 1664 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1665 | { |
1666 | if (mmc->debugfs_root) | |
1667 | debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, | |
1668 | mmc, &mmc_regs_fops); | |
1669 | } | |
1670 | ||
1671 | #else | |
1672 | ||
70a3341a | 1673 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1674 | { |
1675 | } | |
1676 | ||
1677 | #endif | |
1678 | ||
46856a68 RN |
1679 | #ifdef CONFIG_OF |
1680 | static u16 omap4_reg_offset = 0x100; | |
1681 | ||
1682 | static const struct of_device_id omap_mmc_of_match[] = { | |
1683 | { | |
1684 | .compatible = "ti,omap2-hsmmc", | |
1685 | }, | |
1686 | { | |
1687 | .compatible = "ti,omap3-hsmmc", | |
1688 | }, | |
1689 | { | |
1690 | .compatible = "ti,omap4-hsmmc", | |
1691 | .data = &omap4_reg_offset, | |
1692 | }, | |
1693 | {}, | |
b6d085f6 | 1694 | }; |
46856a68 RN |
1695 | MODULE_DEVICE_TABLE(of, omap_mmc_of_match); |
1696 | ||
1697 | static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) | |
1698 | { | |
1699 | struct omap_mmc_platform_data *pdata; | |
1700 | struct device_node *np = dev->of_node; | |
d8714e87 | 1701 | u32 bus_width, max_freq; |
dc642c28 JL |
1702 | int cd_gpio, wp_gpio; |
1703 | ||
1704 | cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); | |
1705 | wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); | |
1706 | if (cd_gpio == -EPROBE_DEFER || wp_gpio == -EPROBE_DEFER) | |
1707 | return ERR_PTR(-EPROBE_DEFER); | |
46856a68 RN |
1708 | |
1709 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
1710 | if (!pdata) | |
1711 | return NULL; /* out of memory */ | |
1712 | ||
1713 | if (of_find_property(np, "ti,dual-volt", NULL)) | |
1714 | pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; | |
1715 | ||
1716 | /* This driver only supports 1 slot */ | |
1717 | pdata->nr_slots = 1; | |
dc642c28 JL |
1718 | pdata->slots[0].switch_pin = cd_gpio; |
1719 | pdata->slots[0].gpio_wp = wp_gpio; | |
46856a68 RN |
1720 | |
1721 | if (of_find_property(np, "ti,non-removable", NULL)) { | |
1722 | pdata->slots[0].nonremovable = true; | |
1723 | pdata->slots[0].no_regulator_off_init = true; | |
1724 | } | |
7f217794 | 1725 | of_property_read_u32(np, "bus-width", &bus_width); |
46856a68 RN |
1726 | if (bus_width == 4) |
1727 | pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; | |
1728 | else if (bus_width == 8) | |
1729 | pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; | |
1730 | ||
1731 | if (of_find_property(np, "ti,needs-special-reset", NULL)) | |
1732 | pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; | |
1733 | ||
d8714e87 DM |
1734 | if (!of_property_read_u32(np, "max-frequency", &max_freq)) |
1735 | pdata->max_freq = max_freq; | |
1736 | ||
cd587096 HG |
1737 | if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) |
1738 | pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; | |
1739 | ||
46856a68 RN |
1740 | return pdata; |
1741 | } | |
1742 | #else | |
1743 | static inline struct omap_mmc_platform_data | |
1744 | *of_get_hsmmc_pdata(struct device *dev) | |
1745 | { | |
1746 | return NULL; | |
1747 | } | |
1748 | #endif | |
1749 | ||
c3be1efd | 1750 | static int omap_hsmmc_probe(struct platform_device *pdev) |
a45c6cb8 MC |
1751 | { |
1752 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; | |
1753 | struct mmc_host *mmc; | |
70a3341a | 1754 | struct omap_hsmmc_host *host = NULL; |
a45c6cb8 | 1755 | struct resource *res; |
db0fefc5 | 1756 | int ret, irq; |
46856a68 | 1757 | const struct of_device_id *match; |
26b88520 RK |
1758 | dma_cap_mask_t mask; |
1759 | unsigned tx_req, rx_req; | |
46b76035 | 1760 | struct pinctrl *pinctrl; |
46856a68 RN |
1761 | |
1762 | match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); | |
1763 | if (match) { | |
1764 | pdata = of_get_hsmmc_pdata(&pdev->dev); | |
dc642c28 JL |
1765 | |
1766 | if (IS_ERR(pdata)) | |
1767 | return PTR_ERR(pdata); | |
1768 | ||
46856a68 | 1769 | if (match->data) { |
efc9b736 | 1770 | const u16 *offsetp = match->data; |
46856a68 RN |
1771 | pdata->reg_offset = *offsetp; |
1772 | } | |
1773 | } | |
a45c6cb8 MC |
1774 | |
1775 | if (pdata == NULL) { | |
1776 | dev_err(&pdev->dev, "Platform Data is missing\n"); | |
1777 | return -ENXIO; | |
1778 | } | |
1779 | ||
1780 | if (pdata->nr_slots == 0) { | |
1781 | dev_err(&pdev->dev, "No Slots\n"); | |
1782 | return -ENXIO; | |
1783 | } | |
1784 | ||
1785 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1786 | irq = platform_get_irq(pdev, 0); | |
1787 | if (res == NULL || irq < 0) | |
1788 | return -ENXIO; | |
1789 | ||
984b203a | 1790 | res = request_mem_region(res->start, resource_size(res), pdev->name); |
a45c6cb8 MC |
1791 | if (res == NULL) |
1792 | return -EBUSY; | |
1793 | ||
db0fefc5 AH |
1794 | ret = omap_hsmmc_gpio_init(pdata); |
1795 | if (ret) | |
1796 | goto err; | |
1797 | ||
70a3341a | 1798 | mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); |
a45c6cb8 MC |
1799 | if (!mmc) { |
1800 | ret = -ENOMEM; | |
db0fefc5 | 1801 | goto err_alloc; |
a45c6cb8 MC |
1802 | } |
1803 | ||
1804 | host = mmc_priv(mmc); | |
1805 | host->mmc = mmc; | |
1806 | host->pdata = pdata; | |
1807 | host->dev = &pdev->dev; | |
1808 | host->use_dma = 1; | |
a45c6cb8 MC |
1809 | host->dma_ch = -1; |
1810 | host->irq = irq; | |
a45c6cb8 | 1811 | host->slot_id = 0; |
fc307df8 | 1812 | host->mapbase = res->start + pdata->reg_offset; |
a45c6cb8 | 1813 | host->base = ioremap(host->mapbase, SZ_4K); |
6da20c89 | 1814 | host->power_mode = MMC_POWER_OFF; |
9782aff8 | 1815 | host->next_data.cookie = 1; |
a45c6cb8 MC |
1816 | |
1817 | platform_set_drvdata(pdev, host); | |
a45c6cb8 | 1818 | |
7a8c2cef | 1819 | mmc->ops = &omap_hsmmc_ops; |
dd498eff | 1820 | |
d418ed87 DM |
1821 | mmc->f_min = OMAP_MMC_MIN_CLOCK; |
1822 | ||
1823 | if (pdata->max_freq > 0) | |
1824 | mmc->f_max = pdata->max_freq; | |
1825 | else | |
1826 | mmc->f_max = OMAP_MMC_MAX_CLOCK; | |
a45c6cb8 | 1827 | |
4dffd7a2 | 1828 | spin_lock_init(&host->irq_lock); |
a45c6cb8 | 1829 | |
6f7607cc | 1830 | host->fclk = clk_get(&pdev->dev, "fck"); |
a45c6cb8 MC |
1831 | if (IS_ERR(host->fclk)) { |
1832 | ret = PTR_ERR(host->fclk); | |
1833 | host->fclk = NULL; | |
a45c6cb8 MC |
1834 | goto err1; |
1835 | } | |
1836 | ||
9b68256c PW |
1837 | if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { |
1838 | dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); | |
1839 | mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; | |
1840 | } | |
dd498eff | 1841 | |
fa4aa2d4 B |
1842 | pm_runtime_enable(host->dev); |
1843 | pm_runtime_get_sync(host->dev); | |
1844 | pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); | |
1845 | pm_runtime_use_autosuspend(host->dev); | |
a45c6cb8 | 1846 | |
92a3aebf B |
1847 | omap_hsmmc_context_save(host); |
1848 | ||
cf5ae40b | 1849 | /* This can be removed once we support PBIAS with DT */ |
e002264f | 1850 | if (host->dev->of_node && res->start == 0x4809c000) |
cf5ae40b TL |
1851 | host->pbias_disable = 1; |
1852 | ||
cd03d9a8 RN |
1853 | host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); |
1854 | /* | |
1855 | * MMC can still work without debounce clock. | |
1856 | */ | |
1857 | if (IS_ERR(host->dbclk)) { | |
cd03d9a8 | 1858 | host->dbclk = NULL; |
94c18149 | 1859 | } else if (clk_prepare_enable(host->dbclk) != 0) { |
cd03d9a8 RN |
1860 | dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); |
1861 | clk_put(host->dbclk); | |
1862 | host->dbclk = NULL; | |
2bec0893 | 1863 | } |
a45c6cb8 | 1864 | |
0ccd76d4 JY |
1865 | /* Since we do only SG emulation, we can have as many segs |
1866 | * as we want. */ | |
a36274e0 | 1867 | mmc->max_segs = 1024; |
0ccd76d4 | 1868 | |
a45c6cb8 MC |
1869 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
1870 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ | |
1871 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1872 | mmc->max_seg_size = mmc->max_req_size; | |
1873 | ||
13189e78 | 1874 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
93caf8e6 | 1875 | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; |
a45c6cb8 | 1876 | |
3a63833e SG |
1877 | mmc->caps |= mmc_slot(host).caps; |
1878 | if (mmc->caps & MMC_CAP_8_BIT_DATA) | |
a45c6cb8 MC |
1879 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
1880 | ||
191d1f1d | 1881 | if (mmc_slot(host).nonremovable) |
23d99bb9 AH |
1882 | mmc->caps |= MMC_CAP_NONREMOVABLE; |
1883 | ||
6fdc75de EP |
1884 | mmc->pm_caps = mmc_slot(host).pm_caps; |
1885 | ||
70a3341a | 1886 | omap_hsmmc_conf_bus_power(host); |
a45c6cb8 | 1887 | |
4a29b559 SS |
1888 | if (!pdev->dev.of_node) { |
1889 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); | |
1890 | if (!res) { | |
1891 | dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); | |
1892 | ret = -ENXIO; | |
1893 | goto err_irq; | |
1894 | } | |
1895 | tx_req = res->start; | |
b7bf773b | 1896 | |
4a29b559 SS |
1897 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); |
1898 | if (!res) { | |
1899 | dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); | |
1900 | ret = -ENXIO; | |
1901 | goto err_irq; | |
1902 | } | |
1903 | rx_req = res->start; | |
f3e2f1dd | 1904 | } |
a45c6cb8 | 1905 | |
26b88520 RK |
1906 | dma_cap_zero(mask); |
1907 | dma_cap_set(DMA_SLAVE, mask); | |
1908 | ||
d272fbf0 MP |
1909 | host->rx_chan = |
1910 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
1911 | &rx_req, &pdev->dev, "rx"); | |
1912 | ||
26b88520 RK |
1913 | if (!host->rx_chan) { |
1914 | dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); | |
04e8c7bc | 1915 | ret = -ENXIO; |
26b88520 RK |
1916 | goto err_irq; |
1917 | } | |
1918 | ||
d272fbf0 MP |
1919 | host->tx_chan = |
1920 | dma_request_slave_channel_compat(mask, omap_dma_filter_fn, | |
1921 | &tx_req, &pdev->dev, "tx"); | |
1922 | ||
26b88520 RK |
1923 | if (!host->tx_chan) { |
1924 | dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); | |
04e8c7bc | 1925 | ret = -ENXIO; |
26b88520 | 1926 | goto err_irq; |
c5c98927 | 1927 | } |
a45c6cb8 MC |
1928 | |
1929 | /* Request IRQ for MMC operations */ | |
d9618e9f | 1930 | ret = request_irq(host->irq, omap_hsmmc_irq, 0, |
a45c6cb8 MC |
1931 | mmc_hostname(mmc), host); |
1932 | if (ret) { | |
b1e056ae | 1933 | dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); |
a45c6cb8 MC |
1934 | goto err_irq; |
1935 | } | |
1936 | ||
1937 | if (pdata->init != NULL) { | |
1938 | if (pdata->init(&pdev->dev) != 0) { | |
b1e056ae | 1939 | dev_err(mmc_dev(host->mmc), |
70a3341a | 1940 | "Unable to configure MMC IRQs\n"); |
a45c6cb8 MC |
1941 | goto err_irq_cd_init; |
1942 | } | |
1943 | } | |
db0fefc5 | 1944 | |
b702b106 | 1945 | if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { |
db0fefc5 AH |
1946 | ret = omap_hsmmc_reg_get(host); |
1947 | if (ret) | |
1948 | goto err_reg; | |
1949 | host->use_reg = 1; | |
1950 | } | |
1951 | ||
b583f26d | 1952 | mmc->ocr_avail = mmc_slot(host).ocr_mask; |
a45c6cb8 MC |
1953 | |
1954 | /* Request IRQ for card detect */ | |
e1a55f5e | 1955 | if ((mmc_slot(host).card_detect_irq)) { |
7efab4f3 N |
1956 | ret = request_threaded_irq(mmc_slot(host).card_detect_irq, |
1957 | NULL, | |
1958 | omap_hsmmc_detect, | |
db35f83e | 1959 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
7efab4f3 | 1960 | mmc_hostname(mmc), host); |
a45c6cb8 | 1961 | if (ret) { |
b1e056ae | 1962 | dev_err(mmc_dev(host->mmc), |
a45c6cb8 MC |
1963 | "Unable to grab MMC CD IRQ\n"); |
1964 | goto err_irq_cd; | |
1965 | } | |
72f2e2c7 | 1966 | pdata->suspend = omap_hsmmc_suspend_cdirq; |
1967 | pdata->resume = omap_hsmmc_resume_cdirq; | |
a45c6cb8 MC |
1968 | } |
1969 | ||
b417577d | 1970 | omap_hsmmc_disable_irq(host); |
a45c6cb8 | 1971 | |
46b76035 DM |
1972 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); |
1973 | if (IS_ERR(pinctrl)) | |
1974 | dev_warn(&pdev->dev, | |
1975 | "pins are not configured from the driver\n"); | |
1976 | ||
b62f6228 AH |
1977 | omap_hsmmc_protect_card(host); |
1978 | ||
a45c6cb8 MC |
1979 | mmc_add_host(mmc); |
1980 | ||
191d1f1d | 1981 | if (mmc_slot(host).name != NULL) { |
a45c6cb8 MC |
1982 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); |
1983 | if (ret < 0) | |
1984 | goto err_slot_name; | |
1985 | } | |
191d1f1d | 1986 | if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { |
a45c6cb8 MC |
1987 | ret = device_create_file(&mmc->class_dev, |
1988 | &dev_attr_cover_switch); | |
1989 | if (ret < 0) | |
db0fefc5 | 1990 | goto err_slot_name; |
a45c6cb8 MC |
1991 | } |
1992 | ||
70a3341a | 1993 | omap_hsmmc_debugfs(mmc); |
fa4aa2d4 B |
1994 | pm_runtime_mark_last_busy(host->dev); |
1995 | pm_runtime_put_autosuspend(host->dev); | |
d900f712 | 1996 | |
a45c6cb8 MC |
1997 | return 0; |
1998 | ||
a45c6cb8 MC |
1999 | err_slot_name: |
2000 | mmc_remove_host(mmc); | |
a45c6cb8 | 2001 | free_irq(mmc_slot(host).card_detect_irq, host); |
db0fefc5 AH |
2002 | err_irq_cd: |
2003 | if (host->use_reg) | |
2004 | omap_hsmmc_reg_put(host); | |
2005 | err_reg: | |
2006 | if (host->pdata->cleanup) | |
2007 | host->pdata->cleanup(&pdev->dev); | |
a45c6cb8 MC |
2008 | err_irq_cd_init: |
2009 | free_irq(host->irq, host); | |
2010 | err_irq: | |
c5c98927 RK |
2011 | if (host->tx_chan) |
2012 | dma_release_channel(host->tx_chan); | |
2013 | if (host->rx_chan) | |
2014 | dma_release_channel(host->rx_chan); | |
d59d77ed | 2015 | pm_runtime_put_sync(host->dev); |
37f6190d | 2016 | pm_runtime_disable(host->dev); |
a45c6cb8 | 2017 | clk_put(host->fclk); |
cd03d9a8 | 2018 | if (host->dbclk) { |
94c18149 | 2019 | clk_disable_unprepare(host->dbclk); |
a45c6cb8 MC |
2020 | clk_put(host->dbclk); |
2021 | } | |
a45c6cb8 MC |
2022 | err1: |
2023 | iounmap(host->base); | |
db0fefc5 AH |
2024 | mmc_free_host(mmc); |
2025 | err_alloc: | |
2026 | omap_hsmmc_gpio_free(pdata); | |
a45c6cb8 | 2027 | err: |
48b332f9 RK |
2028 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2029 | if (res) | |
2030 | release_mem_region(res->start, resource_size(res)); | |
a45c6cb8 MC |
2031 | return ret; |
2032 | } | |
2033 | ||
6e0ee714 | 2034 | static int omap_hsmmc_remove(struct platform_device *pdev) |
a45c6cb8 | 2035 | { |
70a3341a | 2036 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
2037 | struct resource *res; |
2038 | ||
927ce944 FB |
2039 | pm_runtime_get_sync(host->dev); |
2040 | mmc_remove_host(host->mmc); | |
2041 | if (host->use_reg) | |
2042 | omap_hsmmc_reg_put(host); | |
2043 | if (host->pdata->cleanup) | |
2044 | host->pdata->cleanup(&pdev->dev); | |
2045 | free_irq(host->irq, host); | |
2046 | if (mmc_slot(host).card_detect_irq) | |
2047 | free_irq(mmc_slot(host).card_detect_irq, host); | |
a45c6cb8 | 2048 | |
c5c98927 RK |
2049 | if (host->tx_chan) |
2050 | dma_release_channel(host->tx_chan); | |
2051 | if (host->rx_chan) | |
2052 | dma_release_channel(host->rx_chan); | |
2053 | ||
927ce944 FB |
2054 | pm_runtime_put_sync(host->dev); |
2055 | pm_runtime_disable(host->dev); | |
2056 | clk_put(host->fclk); | |
cd03d9a8 | 2057 | if (host->dbclk) { |
94c18149 | 2058 | clk_disable_unprepare(host->dbclk); |
927ce944 | 2059 | clk_put(host->dbclk); |
a45c6cb8 MC |
2060 | } |
2061 | ||
9ea28ecb | 2062 | omap_hsmmc_gpio_free(host->pdata); |
927ce944 | 2063 | iounmap(host->base); |
9d1f0286 | 2064 | mmc_free_host(host->mmc); |
927ce944 | 2065 | |
a45c6cb8 MC |
2066 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2067 | if (res) | |
984b203a | 2068 | release_mem_region(res->start, resource_size(res)); |
a45c6cb8 MC |
2069 | |
2070 | return 0; | |
2071 | } | |
2072 | ||
2073 | #ifdef CONFIG_PM | |
a48ce884 FB |
2074 | static int omap_hsmmc_prepare(struct device *dev) |
2075 | { | |
2076 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); | |
2077 | ||
2078 | if (host->pdata->suspend) | |
2079 | return host->pdata->suspend(dev, host->slot_id); | |
2080 | ||
2081 | return 0; | |
2082 | } | |
2083 | ||
2084 | static void omap_hsmmc_complete(struct device *dev) | |
2085 | { | |
2086 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); | |
2087 | ||
2088 | if (host->pdata->resume) | |
2089 | host->pdata->resume(dev, host->slot_id); | |
2090 | ||
2091 | } | |
2092 | ||
a791daa1 | 2093 | static int omap_hsmmc_suspend(struct device *dev) |
a45c6cb8 | 2094 | { |
927ce944 | 2095 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
a45c6cb8 | 2096 | |
927ce944 | 2097 | if (!host) |
a45c6cb8 MC |
2098 | return 0; |
2099 | ||
927ce944 | 2100 | pm_runtime_get_sync(host->dev); |
31f9d463 | 2101 | |
927ce944 FB |
2102 | if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { |
2103 | omap_hsmmc_disable_irq(host); | |
2104 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
2105 | OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); | |
a45c6cb8 | 2106 | } |
927ce944 | 2107 | |
cd03d9a8 | 2108 | if (host->dbclk) |
94c18149 | 2109 | clk_disable_unprepare(host->dbclk); |
3932afd5 | 2110 | |
31f9d463 | 2111 | pm_runtime_put_sync(host->dev); |
3932afd5 | 2112 | return 0; |
a45c6cb8 MC |
2113 | } |
2114 | ||
2115 | /* Routine to resume the MMC device */ | |
a791daa1 | 2116 | static int omap_hsmmc_resume(struct device *dev) |
a45c6cb8 | 2117 | { |
927ce944 FB |
2118 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
2119 | ||
2120 | if (!host) | |
2121 | return 0; | |
a45c6cb8 | 2122 | |
927ce944 | 2123 | pm_runtime_get_sync(host->dev); |
11dd62a7 | 2124 | |
cd03d9a8 | 2125 | if (host->dbclk) |
94c18149 | 2126 | clk_prepare_enable(host->dbclk); |
2bec0893 | 2127 | |
927ce944 FB |
2128 | if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) |
2129 | omap_hsmmc_conf_bus_power(host); | |
1b331e69 | 2130 | |
927ce944 | 2131 | omap_hsmmc_protect_card(host); |
b62f6228 | 2132 | |
927ce944 FB |
2133 | pm_runtime_mark_last_busy(host->dev); |
2134 | pm_runtime_put_autosuspend(host->dev); | |
3932afd5 | 2135 | return 0; |
a45c6cb8 MC |
2136 | } |
2137 | ||
2138 | #else | |
a48ce884 FB |
2139 | #define omap_hsmmc_prepare NULL |
2140 | #define omap_hsmmc_complete NULL | |
70a3341a | 2141 | #define omap_hsmmc_suspend NULL |
a48ce884 | 2142 | #define omap_hsmmc_resume NULL |
a45c6cb8 MC |
2143 | #endif |
2144 | ||
fa4aa2d4 B |
2145 | static int omap_hsmmc_runtime_suspend(struct device *dev) |
2146 | { | |
2147 | struct omap_hsmmc_host *host; | |
2148 | ||
2149 | host = platform_get_drvdata(to_platform_device(dev)); | |
2150 | omap_hsmmc_context_save(host); | |
927ce944 | 2151 | dev_dbg(dev, "disabled\n"); |
fa4aa2d4 B |
2152 | |
2153 | return 0; | |
2154 | } | |
2155 | ||
2156 | static int omap_hsmmc_runtime_resume(struct device *dev) | |
2157 | { | |
2158 | struct omap_hsmmc_host *host; | |
2159 | ||
2160 | host = platform_get_drvdata(to_platform_device(dev)); | |
2161 | omap_hsmmc_context_restore(host); | |
927ce944 | 2162 | dev_dbg(dev, "enabled\n"); |
fa4aa2d4 B |
2163 | |
2164 | return 0; | |
2165 | } | |
2166 | ||
a791daa1 | 2167 | static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { |
70a3341a DK |
2168 | .suspend = omap_hsmmc_suspend, |
2169 | .resume = omap_hsmmc_resume, | |
a48ce884 FB |
2170 | .prepare = omap_hsmmc_prepare, |
2171 | .complete = omap_hsmmc_complete, | |
fa4aa2d4 B |
2172 | .runtime_suspend = omap_hsmmc_runtime_suspend, |
2173 | .runtime_resume = omap_hsmmc_runtime_resume, | |
a791daa1 KH |
2174 | }; |
2175 | ||
2176 | static struct platform_driver omap_hsmmc_driver = { | |
efa25fd3 | 2177 | .probe = omap_hsmmc_probe, |
0433c143 | 2178 | .remove = omap_hsmmc_remove, |
a45c6cb8 MC |
2179 | .driver = { |
2180 | .name = DRIVER_NAME, | |
2181 | .owner = THIS_MODULE, | |
a791daa1 | 2182 | .pm = &omap_hsmmc_dev_pm_ops, |
46856a68 | 2183 | .of_match_table = of_match_ptr(omap_mmc_of_match), |
a45c6cb8 MC |
2184 | }, |
2185 | }; | |
2186 | ||
b796450b | 2187 | module_platform_driver(omap_hsmmc_driver); |
a45c6cb8 MC |
2188 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); |
2189 | MODULE_LICENSE("GPL"); | |
2190 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2191 | MODULE_AUTHOR("Texas Instruments Inc"); |