]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/mmc/host/omap_hsmmc.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
omap: RX51: Remux to pull eMMC lines down when powering off
[mirror_ubuntu-bionic-kernel.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
d900f712
DK		 20#include <linux/debugfs.h>
21#include <linux/seq_file.h>
a45c6cb8
MC		 22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/dma-mapping.h>
25#include <linux/platform_device.h>
26#include <linux/workqueue.h>
27#include <linux/timer.h>
28#include <linux/clk.h>
29#include <linux/mmc/host.h>
13189e78 30#include <linux/mmc/core.h>
a45c6cb8
MC		 31#include <linux/io.h>
32#include <linux/semaphore.h>
db0fefc5
AH		 33#include <linux/gpio.h>
34#include <linux/regulator/consumer.h>
ce491cf8 35#include <plat/dma.h>
a45c6cb8 36#include <mach/hardware.h>
ce491cf8
TL		 37#include <plat/board.h>
38#include <plat/mmc.h>
39#include <plat/cpu.h>
a45c6cb8
MC		 40
41/* OMAP HSMMC Host Controller Registers */
42#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 43#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 44#define OMAP_HSMMC_CON 0x002C
45#define OMAP_HSMMC_BLK 0x0104
46#define OMAP_HSMMC_ARG 0x0108
47#define OMAP_HSMMC_CMD 0x010C
48#define OMAP_HSMMC_RSP10 0x0110
49#define OMAP_HSMMC_RSP32 0x0114
50#define OMAP_HSMMC_RSP54 0x0118
51#define OMAP_HSMMC_RSP76 0x011C
52#define OMAP_HSMMC_DATA 0x0120
53#define OMAP_HSMMC_HCTL 0x0128
54#define OMAP_HSMMC_SYSCTL 0x012C
55#define OMAP_HSMMC_STAT 0x0130
56#define OMAP_HSMMC_IE 0x0134
57#define OMAP_HSMMC_ISE 0x0138
58#define OMAP_HSMMC_CAPA 0x0140
59
60#define VS18 (1 << 26)
61#define VS30 (1 << 25)
62#define SDVS18 (0x5 << 9)
63#define SDVS30 (0x6 << 9)
eb250826 64#define SDVS33 (0x7 << 9)
1b331e69 65#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 66#define SDVSCLR 0xFFFFF1FF
67#define SDVSDET 0x00000400
68#define AUTOIDLE 0x1
69#define SDBP (1 << 8)
70#define DTO 0xe
71#define ICE 0x1
72#define ICS 0x2
73#define CEN (1 << 2)
74#define CLKD_MASK 0x0000FFC0
75#define CLKD_SHIFT 6
76#define DTO_MASK 0x000F0000
77#define DTO_SHIFT 16
78#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 79#define BWR_ENABLE (1 << 4)
80#define BRR_ENABLE (1 << 5)
a45c6cb8
MC		 81#define INIT_STREAM (1 << 1)
82#define DP_SELECT (1 << 21)
83#define DDIR (1 << 4)
84#define DMA_EN 0x1
85#define MSBS (1 << 5)
86#define BCE (1 << 1)
87#define FOUR_BIT (1 << 1)
73153010 88#define DW8 (1 << 5)
a45c6cb8
MC		 89#define CC 0x1
90#define TC 0x02
91#define OD 0x1
92#define ERR (1 << 15)
93#define CMD_TIMEOUT (1 << 16)
94#define DATA_TIMEOUT (1 << 20)
95#define CMD_CRC (1 << 17)
96#define DATA_CRC (1 << 21)
97#define CARD_ERR (1 << 28)
98#define STAT_CLEAR 0xFFFFFFFF
99#define INIT_STREAM_CMD 0x00000000
100#define DUAL_VOLT_OCR_BIT 7
101#define SRC (1 << 25)
102#define SRD (1 << 26)
11dd62a7
DK		 103#define SOFTRESET (1 << 1)
104#define RESETDONE (1 << 0)
a45c6cb8
MC		 105
106/*
107 * FIXME: Most likely all the data using these _DEVID defines should come
108 * from the platform_data, or implemented in controller and slot specific
109 * functions.
110 */
111#define OMAP_MMC1_DEVID 0
112#define OMAP_MMC2_DEVID 1
f3e2f1dd 113#define OMAP_MMC3_DEVID 2
82cf818d 114#define OMAP_MMC4_DEVID 3
115#define OMAP_MMC5_DEVID 4
a45c6cb8 116
a45c6cb8
MC		 117#define MMC_TIMEOUT_MS 20
118#define OMAP_MMC_MASTER_CLOCK 96000000
119#define DRIVER_NAME "mmci-omap-hs"
120
dd498eff
DK		 121/* Timeouts for entering power saving states on inactivity, msec */
122#define OMAP_MMC_DISABLED_TIMEOUT 100
13189e78
JL		 123#define OMAP_MMC_SLEEP_TIMEOUT 1000
124#define OMAP_MMC_OFF_TIMEOUT 8000
dd498eff 125
a45c6cb8
MC		 126/*
127 * One controller can have multiple slots, like on some omap boards using
128 * omap.c controller driver. Luckily this is not currently done on any known
129 * omap_hsmmc.c device.
130 */
131#define mmc_slot(host) (host->pdata->slots[host->slot_id])
132
133/*
134 * MMC Host controller read/write API's
135 */
136#define OMAP_HSMMC_READ(base, reg) \
137 __raw_readl((base) + OMAP_HSMMC_##reg)
138
139#define OMAP_HSMMC_WRITE(base, reg, val) \
140 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
141
70a3341a 142struct omap_hsmmc_host {
a45c6cb8
MC		 143 struct device *dev;
144 struct mmc_host *mmc;
145 struct mmc_request *mrq;
146 struct mmc_command *cmd;
147 struct mmc_data *data;
148 struct clk *fclk;
149 struct clk *iclk;
150 struct clk *dbclk;
db0fefc5
AH		 151 /*
152 * vcc == configured supply
153 * vcc_aux == optional
154 * - MMC1, supply for DAT4..DAT7
155 * - MMC2/MMC2, external level shifter voltage supply, for
156 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
157 */
158 struct regulator *vcc;
159 struct regulator *vcc_aux;
a45c6cb8
MC		 160 struct semaphore sem;
161 struct work_struct mmc_carddetect_work;
162 void __iomem *base;
163 resource_size_t mapbase;
4dffd7a2
AH		 164 spinlock_t irq_lock; /* Prevent races with irq handler */
165 unsigned long flags;
a45c6cb8
MC		 166 unsigned int id;
167 unsigned int dma_len;
0ccd76d4 168 unsigned int dma_sg_idx;
a45c6cb8 169 unsigned char bus_mode;
a3621465 170 unsigned char power_mode;
a45c6cb8
MC		 171 u32 *buffer;
172 u32 bytesleft;
173 int suspended;
174 int irq;
a45c6cb8 175 int use_dma, dma_ch;
f3e2f1dd 176 int dma_line_tx, dma_line_rx;
a45c6cb8 177 int slot_id;
2bec0893 178 int got_dbclk;
4a694dc9 179 int response_busy;
11dd62a7 180 int context_loss;
dd498eff 181 int dpm_state;
623821f7 182 int vdd;
b62f6228
AH		 183 int protect_card;
184 int reqs_blocked;
db0fefc5 185 int use_reg;
11dd62a7 186
a45c6cb8
MC		 187 struct omap_mmc_platform_data *pdata;
188};
189
db0fefc5
AH		 190static int omap_hsmmc_card_detect(struct device *dev, int slot)
191{
192 struct omap_mmc_platform_data *mmc = dev->platform_data;
193
194 /* NOTE: assumes card detect signal is active-low */
195 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
196}
197
198static int omap_hsmmc_get_wp(struct device *dev, int slot)
199{
200 struct omap_mmc_platform_data *mmc = dev->platform_data;
201
202 /* NOTE: assumes write protect signal is active-high */
203 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
204}
205
206static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
207{
208 struct omap_mmc_platform_data *mmc = dev->platform_data;
209
210 /* NOTE: assumes card detect signal is active-low */
211 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
212}
213
214#ifdef CONFIG_PM
215
216static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
217{
218 struct omap_mmc_platform_data *mmc = dev->platform_data;
219
220 disable_irq(mmc->slots[0].card_detect_irq);
221 return 0;
222}
223
224static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
225{
226 struct omap_mmc_platform_data *mmc = dev->platform_data;
227
228 enable_irq(mmc->slots[0].card_detect_irq);
229 return 0;
230}
231
232#else
233
234#define omap_hsmmc_suspend_cdirq NULL
235#define omap_hsmmc_resume_cdirq NULL
236
237#endif
238
239static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on,
240 int vdd)
241{
242 struct omap_hsmmc_host *host =
243 platform_get_drvdata(to_platform_device(dev));
244 int ret;
245
246 if (mmc_slot(host).before_set_reg)
247 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
248
249 if (power_on)
250 ret = mmc_regulator_set_ocr(host->vcc, vdd);
251 else
252 ret = mmc_regulator_set_ocr(host->vcc, 0);
253
254 if (mmc_slot(host).after_set_reg)
255 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
256
257 return ret;
258}
259
260static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on,
261 int vdd)
262{
263 struct omap_hsmmc_host *host =
264 platform_get_drvdata(to_platform_device(dev));
265 int ret = 0;
266
267 /*
268 * If we don't see a Vcc regulator, assume it's a fixed
269 * voltage always-on regulator.
270 */
271 if (!host->vcc)
272 return 0;
273
274 if (mmc_slot(host).before_set_reg)
275 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
276
277 /*
278 * Assume Vcc regulator is used only to power the card ... OMAP
279 * VDDS is used to power the pins, optionally with a transceiver to
280 * support cards using voltages other than VDDS (1.8V nominal). When a
281 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
282 *
283 * In some cases this regulator won't support enable/disable;
284 * e.g. it's a fixed rail for a WLAN chip.
285 *
286 * In other cases vcc_aux switches interface power. Example, for
287 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
288 * chips/cards need an interface voltage rail too.
289 */
290 if (power_on) {
291 ret = mmc_regulator_set_ocr(host->vcc, vdd);
292 /* Enable interface voltage rail, if needed */
293 if (ret == 0 && host->vcc_aux) {
294 ret = regulator_enable(host->vcc_aux);
295 if (ret < 0)
296 ret = mmc_regulator_set_ocr(host->vcc, 0);
297 }
298 } else {
299 if (host->vcc_aux) {
300 ret = regulator_is_enabled(host->vcc_aux);
301 if (ret > 0)
302 ret = regulator_disable(host->vcc_aux);
303 }
304 if (ret == 0)
305 ret = mmc_regulator_set_ocr(host->vcc, 0);
306 }
307
308 if (mmc_slot(host).after_set_reg)
309 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
310
311 return ret;
312}
313
314static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep,
315 int vdd, int cardsleep)
316{
317 struct omap_hsmmc_host *host =
318 platform_get_drvdata(to_platform_device(dev));
319 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
320
321 return regulator_set_mode(host->vcc, mode);
322}
323
324static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep,
325 int vdd, int cardsleep)
326{
327 struct omap_hsmmc_host *host =
328 platform_get_drvdata(to_platform_device(dev));
329 int err, mode;
330
331 /*
332 * If we don't see a Vcc regulator, assume it's a fixed
333 * voltage always-on regulator.
334 */
335 if (!host->vcc)
336 return 0;
337
338 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL;
339
340 if (!host->vcc_aux)
341 return regulator_set_mode(host->vcc, mode);
342
343 if (cardsleep) {
344 /* VCC can be turned off if card is asleep */
345 if (sleep)
346 err = mmc_regulator_set_ocr(host->vcc, 0);
347 else
348 err = mmc_regulator_set_ocr(host->vcc, vdd);
349 } else
350 err = regulator_set_mode(host->vcc, mode);
351 if (err)
352 return err;
353 return regulator_set_mode(host->vcc_aux, mode);
354}
355
356static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
357{
358 int ret;
359
360 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
361 pdata->suspend = omap_hsmmc_suspend_cdirq;
362 pdata->resume = omap_hsmmc_resume_cdirq;
363 if (pdata->slots[0].cover)
364 pdata->slots[0].get_cover_state =
365 omap_hsmmc_get_cover_state;
366 else
367 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
368 pdata->slots[0].card_detect_irq =
369 gpio_to_irq(pdata->slots[0].switch_pin);
370 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
371 if (ret)
372 return ret;
373 ret = gpio_direction_input(pdata->slots[0].switch_pin);
374 if (ret)
375 goto err_free_sp;
376 } else
377 pdata->slots[0].switch_pin = -EINVAL;
378
379 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
380 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
381 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
382 if (ret)
383 goto err_free_cd;
384 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
385 if (ret)
386 goto err_free_wp;
387 } else
388 pdata->slots[0].gpio_wp = -EINVAL;
389
390 return 0;
391
392err_free_wp:
393 gpio_free(pdata->slots[0].gpio_wp);
394err_free_cd:
395 if (gpio_is_valid(pdata->slots[0].switch_pin))
396err_free_sp:
397 gpio_free(pdata->slots[0].switch_pin);
398 return ret;
399}
400
401static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
402{
403 if (gpio_is_valid(pdata->slots[0].gpio_wp))
404 gpio_free(pdata->slots[0].gpio_wp);
405 if (gpio_is_valid(pdata->slots[0].switch_pin))
406 gpio_free(pdata->slots[0].switch_pin);
407}
408
409static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
410{
411 struct regulator *reg;
412 int ret = 0;
413
414 switch (host->id) {
415 case OMAP_MMC1_DEVID:
416 /* On-chip level shifting via PBIAS0/PBIAS1 */
417 mmc_slot(host).set_power = omap_hsmmc_1_set_power;
418 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep;
419 break;
420 case OMAP_MMC2_DEVID:
421 case OMAP_MMC3_DEVID:
422 /* Off-chip level shifting, or none */
423 mmc_slot(host).set_power = omap_hsmmc_23_set_power;
424 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep;
425 break;
426 default:
427 pr_err("MMC%d configuration not supported!\n", host->id);
428 return -EINVAL;
429 }
430
431 reg = regulator_get(host->dev, "vmmc");
432 if (IS_ERR(reg)) {
433 dev_dbg(host->dev, "vmmc regulator missing\n");
434 /*
435 * HACK: until fixed.c regulator is usable,
436 * we don't require a main regulator
437 * for MMC2 or MMC3
438 */
439 if (host->id == OMAP_MMC1_DEVID) {
440 ret = PTR_ERR(reg);
441 goto err;
442 }
443 } else {
444 host->vcc = reg;
445 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg);
446
447 /* Allow an aux regulator */
448 reg = regulator_get(host->dev, "vmmc_aux");
449 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
450
451 /*
452 * UGLY HACK: workaround regulator framework bugs.
453 * When the bootloader leaves a supply active, it's
454 * initialized with zero usecount ... and we can't
455 * disable it without first enabling it. Until the
456 * framework is fixed, we need a workaround like this
457 * (which is safe for MMC, but not in general).
458 */
459 if (regulator_is_enabled(host->vcc) > 0) {
460 regulator_enable(host->vcc);
461 regulator_disable(host->vcc);
462 }
463 if (host->vcc_aux) {
464 if (regulator_is_enabled(reg) > 0) {
465 regulator_enable(reg);
466 regulator_disable(reg);
467 }
468 }
469 }
470
471 return 0;
472
473err:
474 mmc_slot(host).set_power = NULL;
475 mmc_slot(host).set_sleep = NULL;
476 return ret;
477}
478
479static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
480{
481 regulator_put(host->vcc);
482 regulator_put(host->vcc_aux);
483 mmc_slot(host).set_power = NULL;
484 mmc_slot(host).set_sleep = NULL;
485}
486
a45c6cb8
MC		 487/*
488 * Stop clock to the card
489 */
70a3341a 490static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 491{
492 OMAP_HSMMC_WRITE(host->base, SYSCTL,
493 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
494 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
495 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
496}
497
11dd62a7
DK		 498#ifdef CONFIG_PM
499
500/*
501 * Restore the MMC host context, if it was lost as result of a
502 * power state change.
503 */
70a3341a 504static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 505{
506 struct mmc_ios *ios = &host->mmc->ios;
507 struct omap_mmc_platform_data *pdata = host->pdata;
508 int context_loss = 0;
509 u32 hctl, capa, con;
510 u16 dsor = 0;
511 unsigned long timeout;
512
513 if (pdata->get_context_loss_count) {
514 context_loss = pdata->get_context_loss_count(host->dev);
515 if (context_loss < 0)
516 return 1;
517 }
518
519 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
520 context_loss == host->context_loss ? "not " : "");
521 if (host->context_loss == context_loss)
522 return 1;
523
524 /* Wait for hardware reset */
525 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
526 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
527 && time_before(jiffies, timeout))
528 ;
529
530 /* Do software reset */
531 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
532 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
533 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
534 && time_before(jiffies, timeout))
535 ;
536
537 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
538 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
539
540 if (host->id == OMAP_MMC1_DEVID) {
541 if (host->power_mode != MMC_POWER_OFF &&
542 (1 << ios->vdd) <= MMC_VDD_23_24)
543 hctl = SDVS18;
544 else
545 hctl = SDVS30;
546 capa = VS30 | VS18;
547 } else {
548 hctl = SDVS18;
549 capa = VS18;
550 }
551
552 OMAP_HSMMC_WRITE(host->base, HCTL,
553 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
554
555 OMAP_HSMMC_WRITE(host->base, CAPA,
556 OMAP_HSMMC_READ(host->base, CAPA) | capa);
557
558 OMAP_HSMMC_WRITE(host->base, HCTL,
559 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
560
561 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
562 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
563 && time_before(jiffies, timeout))
564 ;
565
566 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
567 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
568 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
569
570 /* Do not initialize card-specific things if the power is off */
571 if (host->power_mode == MMC_POWER_OFF)
572 goto out;
573
574 con = OMAP_HSMMC_READ(host->base, CON);
575 switch (ios->bus_width) {
576 case MMC_BUS_WIDTH_8:
577 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
578 break;
579 case MMC_BUS_WIDTH_4:
580 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
581 OMAP_HSMMC_WRITE(host->base, HCTL,
582 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
583 break;
584 case MMC_BUS_WIDTH_1:
585 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
586 OMAP_HSMMC_WRITE(host->base, HCTL,
587 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
588 break;
589 }
590
591 if (ios->clock) {
592 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
593 if (dsor < 1)
594 dsor = 1;
595
596 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
597 dsor++;
598
599 if (dsor > 250)
600 dsor = 250;
601 }
602
603 OMAP_HSMMC_WRITE(host->base, SYSCTL,
604 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
605 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16));
606 OMAP_HSMMC_WRITE(host->base, SYSCTL,
607 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
608
609 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
610 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
611 && time_before(jiffies, timeout))
612 ;
613
614 OMAP_HSMMC_WRITE(host->base, SYSCTL,
615 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
616
617 con = OMAP_HSMMC_READ(host->base, CON);
618 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
619 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
620 else
621 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
622out:
623 host->context_loss = context_loss;
624
625 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
626 return 0;
627}
628
629/*
630 * Save the MMC host context (store the number of power state changes so far).
631 */
70a3341a 632static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 633{
634 struct omap_mmc_platform_data *pdata = host->pdata;
635 int context_loss;
636
637 if (pdata->get_context_loss_count) {
638 context_loss = pdata->get_context_loss_count(host->dev);
639 if (context_loss < 0)
640 return;
641 host->context_loss = context_loss;
642 }
643}
644
645#else
646
70a3341a 647static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 648{
649 return 0;
650}
651
70a3341a 652static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 653{
654}
655
656#endif
657
a45c6cb8
MC		 658/*
659 * Send init stream sequence to card
660 * before sending IDLE command
661 */
70a3341a 662static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 663{
664 int reg = 0;
665 unsigned long timeout;
666
b62f6228
AH		 667 if (host->protect_card)
668 return;
669
a45c6cb8
MC		 670 disable_irq(host->irq);
671 OMAP_HSMMC_WRITE(host->base, CON,
672 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
673 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
674
675 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
676 while ((reg != CC) && time_before(jiffies, timeout))
677 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
678
679 OMAP_HSMMC_WRITE(host->base, CON,
680 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 681
682 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
683 OMAP_HSMMC_READ(host->base, STAT);
684
a45c6cb8
MC		 685 enable_irq(host->irq);
686}
687
688static inline
70a3341a 689int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 690{
691 int r = 1;
692
191d1f1d
DK		 693 if (mmc_slot(host).get_cover_state)
694 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 695 return r;
696}
697
698static ssize_t
70a3341a 699omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 700 char *buf)
701{
702 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 703 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 704
70a3341a
DK		 705 return sprintf(buf, "%s\n",
706 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 707}
708
70a3341a 709static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 710
711static ssize_t
70a3341a 712omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 713 char *buf)
714{
715 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 716 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 717
191d1f1d 718 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 719}
720
70a3341a 721static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 722
723/*
724 * Configure the response type and send the cmd.
725 */
726static void
70a3341a 727omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 728 struct mmc_data *data)
729{
730 int cmdreg = 0, resptype = 0, cmdtype = 0;
731
732 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
733 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
734 host->cmd = cmd;
735
736 /*
737 * Clear status bits and enable interrupts
738 */
739 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
740 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
ccdfe3a6
AG		 741
742 if (host->use_dma)
743 OMAP_HSMMC_WRITE(host->base, IE,
744 INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE));
745 else
746 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8 747
4a694dc9 748 host->response_busy = 0;
a45c6cb8
MC		 749 if (cmd->flags & MMC_RSP_PRESENT) {
750 if (cmd->flags & MMC_RSP_136)
751 resptype = 1;
4a694dc9
AH		 752 else if (cmd->flags & MMC_RSP_BUSY) {
753 resptype = 3;
754 host->response_busy = 1;
755 } else
a45c6cb8
MC		 756 resptype = 2;
757 }
758
759 /*
760 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
761 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
762 * a val of 0x3, rest 0x0.
763 */
764 if (cmd == host->mrq->stop)
765 cmdtype = 0x3;
766
767 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
768
769 if (data) {
770 cmdreg |= DP_SELECT | MSBS | BCE;
771 if (data->flags & MMC_DATA_READ)
772 cmdreg |= DDIR;
773 else
774 cmdreg &= ~(DDIR);
775 }
776
777 if (host->use_dma)
778 cmdreg |= DMA_EN;
779
4dffd7a2
AH		 780 /*
781 * In an interrupt context (i.e. STOP command), the spinlock is unlocked
782 * by the interrupt handler, otherwise (i.e. for a new request) it is
783 * unlocked here.
784 */
785 if (!in_interrupt())
786 spin_unlock_irqrestore(&host->irq_lock, host->flags);
787
a45c6cb8
MC		 788 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
789 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
790}
791
0ccd76d4 792static int
70a3341a 793omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 794{
795 if (data->flags & MMC_DATA_WRITE)
796 return DMA_TO_DEVICE;
797 else
798 return DMA_FROM_DEVICE;
799}
800
a45c6cb8
MC		 801/*
802 * Notify the transfer complete to MMC core
803 */
804static void
70a3341a 805omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 806{
4a694dc9
AH		 807 if (!data) {
808 struct mmc_request *mrq = host->mrq;
809
23050103
AH		 810 /* TC before CC from CMD6 - don't know why, but it happens */
811 if (host->cmd && host->cmd->opcode == 6 &&
812 host->response_busy) {
813 host->response_busy = 0;
814 return;
815 }
816
4a694dc9 817 host->mrq = NULL;
4a694dc9
AH		 818 mmc_request_done(host->mmc, mrq);
819 return;
820 }
821
a45c6cb8
MC		 822 host->data = NULL;
823
824 if (host->use_dma && host->dma_ch != -1)
825 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len,
70a3341a 826 omap_hsmmc_get_dma_dir(host, data));
a45c6cb8
MC		 827
828 if (!data->error)
829 data->bytes_xfered += data->blocks * (data->blksz);
830 else
831 data->bytes_xfered = 0;
832
833 if (!data->stop) {
834 host->mrq = NULL;
835 mmc_request_done(host->mmc, data->mrq);
836 return;
837 }
70a3341a 838 omap_hsmmc_start_command(host, data->stop, NULL);
a45c6cb8
MC		 839}
840
841/*
842 * Notify the core about command completion
843 */
844static void
70a3341a 845omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 846{
847 host->cmd = NULL;
848
849 if (cmd->flags & MMC_RSP_PRESENT) {
850 if (cmd->flags & MMC_RSP_136) {
851 /* response type 2 */
852 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
853 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
854 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
855 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
856 } else {
857 /* response types 1, 1b, 3, 4, 5, 6 */
858 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
859 }
860 }
4a694dc9 861 if ((host->data == NULL && !host->response_busy) || cmd->error) {
a45c6cb8
MC		 862 host->mrq = NULL;
863 mmc_request_done(host->mmc, cmd->mrq);
864 }
865}
866
867/*
868 * DMA clean up for command errors
869 */
70a3341a 870static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 871{
82788ff5 872 host->data->error = errno;
a45c6cb8
MC		 873
874 if (host->use_dma && host->dma_ch != -1) {
875 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len,
70a3341a 876 omap_hsmmc_get_dma_dir(host, host->data));
a45c6cb8
MC		 877 omap_free_dma(host->dma_ch);
878 host->dma_ch = -1;
879 up(&host->sem);
880 }
881 host->data = NULL;
a45c6cb8
MC		 882}
883
884/*
885 * Readable error output
886 */
887#ifdef CONFIG_MMC_DEBUG
70a3341a 888static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 889{
890 /* --- means reserved bit without definition at documentation */
70a3341a 891 static const char *omap_hsmmc_status_bits[] = {
a45c6cb8
MC		 892 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ",
893 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC",
894 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---",
895 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---"
896 };
897 char res[256];
898 char *buf = res;
899 int len, i;
900
901 len = sprintf(buf, "MMC IRQ 0x%x :", status);
902 buf += len;
903
70a3341a 904 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 905 if (status & (1 << i)) {
70a3341a 906 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 907 buf += len;
908 }
909
910 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
911}
912#endif /* CONFIG_MMC_DEBUG */
913
3ebf74b1
JP		 914/*
915 * MMC controller internal state machines reset
916 *
917 * Used to reset command or data internal state machines, using respectively
918 * SRC or SRD bit of SYSCTL register
919 * Can be called from interrupt context
920 */
70a3341a
DK		 921static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
922 unsigned long bit)
3ebf74b1
JP		 923{
924 unsigned long i = 0;
925 unsigned long limit = (loops_per_jiffy *
926 msecs_to_jiffies(MMC_TIMEOUT_MS));
927
928 OMAP_HSMMC_WRITE(host->base, SYSCTL,
929 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
930
931 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
932 (i++ < limit))
933 cpu_relax();
934
935 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
936 dev_err(mmc_dev(host->mmc),
937 "Timeout waiting on controller reset in %s\n",
938 __func__);
939}
a45c6cb8
MC		 940
941/*
942 * MMC controller IRQ handler
943 */
70a3341a 944static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
a45c6cb8 945{
70a3341a 946 struct omap_hsmmc_host *host = dev_id;
a45c6cb8
MC		 947 struct mmc_data *data;
948 int end_cmd = 0, end_trans = 0, status;
949
4dffd7a2
AH		 950 spin_lock(&host->irq_lock);
951
4a694dc9 952 if (host->mrq == NULL) {
a45c6cb8
MC		 953 OMAP_HSMMC_WRITE(host->base, STAT,
954 OMAP_HSMMC_READ(host->base, STAT));
00adadc1
KH		 955 /* Flush posted write */
956 OMAP_HSMMC_READ(host->base, STAT);
4dffd7a2 957 spin_unlock(&host->irq_lock);
a45c6cb8
MC		 958 return IRQ_HANDLED;
959 }
960
961 data = host->data;
962 status = OMAP_HSMMC_READ(host->base, STAT);
963 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
964
965 if (status & ERR) {
966#ifdef CONFIG_MMC_DEBUG
70a3341a 967 omap_hsmmc_report_irq(host, status);
a45c6cb8
MC		 968#endif
969 if ((status & CMD_TIMEOUT) ||
970 (status & CMD_CRC)) {
971 if (host->cmd) {
972 if (status & CMD_TIMEOUT) {
70a3341a
DK		 973 omap_hsmmc_reset_controller_fsm(host,
974 SRC);
a45c6cb8
MC		 975 host->cmd->error = -ETIMEDOUT;
976 } else {
977 host->cmd->error = -EILSEQ;
978 }
979 end_cmd = 1;
980 }
4a694dc9
AH		 981 if (host->data || host->response_busy) {
982 if (host->data)
70a3341a
DK		 983 omap_hsmmc_dma_cleanup(host,
984 -ETIMEDOUT);
4a694dc9 985 host->response_busy = 0;
70a3341a 986 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 987 }
a45c6cb8
MC		 988 }
989 if ((status & DATA_TIMEOUT) ||
990 (status & DATA_CRC)) {
4a694dc9
AH		 991 if (host->data || host->response_busy) {
992 int err = (status & DATA_TIMEOUT) ?
993 -ETIMEDOUT : -EILSEQ;
994
995 if (host->data)
70a3341a 996 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 997 else
4a694dc9
AH		 998 host->mrq->cmd->error = err;
999 host->response_busy = 0;
70a3341a 1000 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1001 end_trans = 1;
1002 }
1003 }
1004 if (status & CARD_ERR) {
1005 dev_dbg(mmc_dev(host->mmc),
1006 "Ignoring card err CMD%d\n", host->cmd->opcode);
1007 if (host->cmd)
1008 end_cmd = 1;
1009 if (host->data)
1010 end_trans = 1;
1011 }
1012 }
1013
1014 OMAP_HSMMC_WRITE(host->base, STAT, status);
00adadc1
KH		 1015 /* Flush posted write */
1016 OMAP_HSMMC_READ(host->base, STAT);
a45c6cb8 1017
a8fe29d8 1018 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1019 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1020 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1021 omap_hsmmc_xfer_done(host, data);
a45c6cb8 1022
4dffd7a2
AH		 1023 spin_unlock(&host->irq_lock);
1024
a45c6cb8
MC		 1025 return IRQ_HANDLED;
1026}
1027
70a3341a 1028static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1029{
1030 unsigned long i;
1031
1032 OMAP_HSMMC_WRITE(host->base, HCTL,
1033 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1034 for (i = 0; i < loops_per_jiffy; i++) {
1035 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1036 break;
1037 cpu_relax();
1038 }
1039}
1040
a45c6cb8 1041/*
eb250826
DB		 1042 * Switch MMC interface voltage ... only relevant for MMC1.
1043 *
1044 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1045 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1046 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1047 */
70a3341a 1048static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1049{
1050 u32 reg_val = 0;
1051 int ret;
1052
1053 /* Disable the clocks */
1054 clk_disable(host->fclk);
1055 clk_disable(host->iclk);
2bec0893
AH		 1056 if (host->got_dbclk)
1057 clk_disable(host->dbclk);
a45c6cb8
MC		 1058
1059 /* Turn the power off */
1060 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1061
1062 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1063 if (!ret)
1064 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1065 vdd);
1066 clk_enable(host->iclk);
1067 clk_enable(host->fclk);
1068 if (host->got_dbclk)
1069 clk_enable(host->dbclk);
1070
a45c6cb8
MC		 1071 if (ret != 0)
1072 goto err;
1073
a45c6cb8
MC		 1074 OMAP_HSMMC_WRITE(host->base, HCTL,
1075 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1076 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1077
a45c6cb8
MC		 1078 /*
1079 * If a MMC dual voltage card is detected, the set_ios fn calls
1080 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1081 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1082 *
eb250826
DB		 1083 * Cope with a bit of slop in the range ... per data sheets:
1084 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1085 * but recommended values are 1.71V to 1.89V
1086 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1087 * but recommended values are 2.7V to 3.3V
1088 *
1089 * Board setup code shouldn't permit anything very out-of-range.
1090 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1091 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1092 */
eb250826 1093 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1094 reg_val |= SDVS18;
eb250826
DB		 1095 else
1096 reg_val |= SDVS30;
a45c6cb8
MC		 1097
1098 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1099 set_sd_bus_power(host);
a45c6cb8
MC		 1100
1101 return 0;
1102err:
1103 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1104 return ret;
1105}
1106
b62f6228
AH		 1107/* Protect the card while the cover is open */
1108static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1109{
1110 if (!mmc_slot(host).get_cover_state)
1111 return;
1112
1113 host->reqs_blocked = 0;
1114 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1115 if (host->protect_card) {
1116 printk(KERN_INFO "%s: cover is closed, "
1117 "card is now accessible\n",
1118 mmc_hostname(host->mmc));
1119 host->protect_card = 0;
1120 }
1121 } else {
1122 if (!host->protect_card) {
1123 printk(KERN_INFO "%s: cover is open, "
1124 "card is now inaccessible\n",
1125 mmc_hostname(host->mmc));
1126 host->protect_card = 1;
1127 }
1128 }
1129}
1130
a45c6cb8
MC		 1131/*
1132 * Work Item to notify the core about card insertion/removal
1133 */
70a3341a 1134static void omap_hsmmc_detect(struct work_struct *work)
a45c6cb8 1135{
70a3341a
DK		 1136 struct omap_hsmmc_host *host =
1137 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work);
249d0fa9 1138 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1139 int carddetect;
1140
1141 if (host->suspended)
1142 return;
1143
1144 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1145
191d1f1d 1146 if (slot->card_detect)
db0fefc5 1147 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1148 else {
1149 omap_hsmmc_protect_card(host);
a6b2240d 1150 carddetect = -ENOSYS;
b62f6228 1151 }
a45c6cb8 1152
a6b2240d 1153 if (carddetect) {
a45c6cb8
MC		 1154 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
1155 } else {
5e2ea617 1156 mmc_host_enable(host->mmc);
70a3341a 1157 omap_hsmmc_reset_controller_fsm(host, SRD);
5e2ea617 1158 mmc_host_lazy_disable(host->mmc);
70a3341a 1159
a45c6cb8
MC		 1160 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
1161 }
1162}
1163
1164/*
1165 * ISR for handling card insertion and removal
1166 */
70a3341a 1167static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id)
a45c6cb8 1168{
70a3341a 1169 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id;
a45c6cb8 1170
a6b2240d
AH		 1171 if (host->suspended)
1172 return IRQ_HANDLED;
a45c6cb8
MC		 1173 schedule_work(&host->mmc_carddetect_work);
1174
1175 return IRQ_HANDLED;
1176}
1177
70a3341a 1178static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1179 struct mmc_data *data)
1180{
1181 int sync_dev;
1182
f3e2f1dd
GI		 1183 if (data->flags & MMC_DATA_WRITE)
1184 sync_dev = host->dma_line_tx;
1185 else
1186 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1187 return sync_dev;
1188}
1189
70a3341a 1190static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1191 struct mmc_data *data,
1192 struct scatterlist *sgl)
1193{
1194 int blksz, nblk, dma_ch;
1195
1196 dma_ch = host->dma_ch;
1197 if (data->flags & MMC_DATA_WRITE) {
1198 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1199 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1200 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1201 sg_dma_address(sgl), 0, 0);
1202 } else {
1203 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1204 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1205 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1206 sg_dma_address(sgl), 0, 0);
1207 }
1208
1209 blksz = host->data->blksz;
1210 nblk = sg_dma_len(sgl) / blksz;
1211
1212 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1213 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1214 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1215 !(data->flags & MMC_DATA_WRITE));
1216
1217 omap_start_dma(dma_ch);
1218}
1219
a45c6cb8
MC		 1220/*
1221 * DMA call back function
1222 */
70a3341a 1223static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *data)
a45c6cb8 1224{
70a3341a 1225 struct omap_hsmmc_host *host = data;
a45c6cb8
MC		 1226
1227 if (ch_status & OMAP2_DMA_MISALIGNED_ERR_IRQ)
1228 dev_dbg(mmc_dev(host->mmc), "MISALIGNED_ADRS_ERR\n");
1229
1230 if (host->dma_ch < 0)
1231 return;
1232
0ccd76d4
JY		 1233 host->dma_sg_idx++;
1234 if (host->dma_sg_idx < host->dma_len) {
1235 /* Fire up the next transfer. */
70a3341a 1236 omap_hsmmc_config_dma_params(host, host->data,
0ccd76d4
JY		 1237 host->data->sg + host->dma_sg_idx);
1238 return;
1239 }
1240
a45c6cb8
MC		 1241 omap_free_dma(host->dma_ch);
1242 host->dma_ch = -1;
1243 /*
1244 * DMA Callback: run in interrupt context.
85b84322 1245 * mutex_unlock will throw a kernel warning if used.
a45c6cb8
MC		 1246 */
1247 up(&host->sem);
1248}
1249
a45c6cb8
MC		 1250/*
1251 * Routine to configure and start DMA for the MMC card
1252 */
70a3341a
DK		 1253static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1254 struct mmc_request *req)
a45c6cb8 1255{
0ccd76d4 1256 int dma_ch = 0, ret = 0, err = 1, i;
a45c6cb8
MC		 1257 struct mmc_data *data = req->data;
1258
0ccd76d4 1259 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1260 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1261 struct scatterlist *sgl;
1262
1263 sgl = data->sg + i;
1264 if (sgl->length % data->blksz)
1265 return -EINVAL;
1266 }
1267 if ((data->blksz % 4) != 0)
1268 /* REVISIT: The MMC buffer increments only when MSB is written.
1269 * Return error for blksz which is non multiple of four.
1270 */
1271 return -EINVAL;
1272
a45c6cb8
MC		 1273 /*
1274 * If for some reason the DMA transfer is still active,
1275 * we wait for timeout period and free the dma
1276 */
1277 if (host->dma_ch != -1) {
1278 set_current_state(TASK_UNINTERRUPTIBLE);
1279 schedule_timeout(100);
1280 if (down_trylock(&host->sem)) {
1281 omap_free_dma(host->dma_ch);
1282 host->dma_ch = -1;
1283 up(&host->sem);
1284 return err;
1285 }
1286 } else {
1287 if (down_trylock(&host->sem))
1288 return err;
1289 }
1290
70a3341a
DK		 1291 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1292 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1293 if (ret != 0) {
0ccd76d4 1294 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1295 "%s: omap_request_dma() failed with %d\n",
1296 mmc_hostname(host->mmc), ret);
1297 return ret;
1298 }
1299
1300 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
70a3341a 1301 data->sg_len, omap_hsmmc_get_dma_dir(host, data));
a45c6cb8 1302 host->dma_ch = dma_ch;
0ccd76d4 1303 host->dma_sg_idx = 0;
a45c6cb8 1304
70a3341a 1305 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1306
a45c6cb8
MC		 1307 return 0;
1308}
1309
70a3341a 1310static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1311 unsigned int timeout_ns,
1312 unsigned int timeout_clks)
a45c6cb8
MC		 1313{
1314 unsigned int timeout, cycle_ns;
1315 uint32_t reg, clkd, dto = 0;
1316
1317 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1318 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1319 if (clkd == 0)
1320 clkd = 1;
1321
1322 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1323 timeout = timeout_ns / cycle_ns;
1324 timeout += timeout_clks;
a45c6cb8
MC		 1325 if (timeout) {
1326 while ((timeout & 0x80000000) == 0) {
1327 dto += 1;
1328 timeout <<= 1;
1329 }
1330 dto = 31 - dto;
1331 timeout <<= 1;
1332 if (timeout && dto)
1333 dto += 1;
1334 if (dto >= 13)
1335 dto -= 13;
1336 else
1337 dto = 0;
1338 if (dto > 14)
1339 dto = 14;
1340 }
1341
1342 reg &= ~DTO_MASK;
1343 reg |= dto << DTO_SHIFT;
1344 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1345}
1346
1347/*
1348 * Configure block length for MMC/SD cards and initiate the transfer.
1349 */
1350static int
70a3341a 1351omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1352{
1353 int ret;
1354 host->data = req->data;
1355
1356 if (req->data == NULL) {
a45c6cb8 1357 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1358 /*
1359 * Set an arbitrary 100ms data timeout for commands with
1360 * busy signal.
1361 */
1362 if (req->cmd->flags & MMC_RSP_BUSY)
1363 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1364 return 0;
1365 }
1366
1367 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1368 | (req->data->blocks << 16));
e2bf08d6 1369 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1370
a45c6cb8 1371 if (host->use_dma) {
70a3341a 1372 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1373 if (ret != 0) {
1374 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1375 return ret;
1376 }
1377 }
1378 return 0;
1379}
1380
1381/*
1382 * Request function. for read/write operation
1383 */
70a3341a 1384static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1385{
70a3341a 1386 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1387 int err;
a45c6cb8 1388
4dffd7a2
AH		 1389 /*
1390 * Prevent races with the interrupt handler because of unexpected
1391 * interrupts, but not if we are already in interrupt context i.e.
1392 * retries.
1393 */
b62f6228 1394 if (!in_interrupt()) {
4dffd7a2 1395 spin_lock_irqsave(&host->irq_lock, host->flags);
b62f6228
AH		 1396 /*
1397 * Protect the card from I/O if there is a possibility
1398 * it can be removed.
1399 */
1400 if (host->protect_card) {
1401 if (host->reqs_blocked < 3) {
1402 /*
1403 * Ensure the controller is left in a consistent
1404 * state by resetting the command and data state
1405 * machines.
1406 */
1407 omap_hsmmc_reset_controller_fsm(host, SRD);
1408 omap_hsmmc_reset_controller_fsm(host, SRC);
1409 host->reqs_blocked += 1;
1410 }
1411 req->cmd->error = -EBADF;
1412 if (req->data)
1413 req->data->error = -EBADF;
1414 spin_unlock_irqrestore(&host->irq_lock, host->flags);
1415 mmc_request_done(mmc, req);
1416 return;
1417 } else if (host->reqs_blocked)
1418 host->reqs_blocked = 0;
1419 }
a45c6cb8
MC		 1420 WARN_ON(host->mrq != NULL);
1421 host->mrq = req;
70a3341a 1422 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1423 if (err) {
1424 req->cmd->error = err;
1425 if (req->data)
1426 req->data->error = err;
1427 host->mrq = NULL;
4dffd7a2
AH		 1428 if (!in_interrupt())
1429 spin_unlock_irqrestore(&host->irq_lock, host->flags);
a3f406f8
JL		 1430 mmc_request_done(mmc, req);
1431 return;
1432 }
1433
70a3341a 1434 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1435}
1436
a45c6cb8 1437/* Routine to configure clock values. Exposed API to core */
70a3341a 1438static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1439{
70a3341a 1440 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8
MC		 1441 u16 dsor = 0;
1442 unsigned long regval;
1443 unsigned long timeout;
73153010 1444 u32 con;
a3621465 1445 int do_send_init_stream = 0;
a45c6cb8 1446
5e2ea617
AH		 1447 mmc_host_enable(host->mmc);
1448
a3621465
AH		 1449 if (ios->power_mode != host->power_mode) {
1450 switch (ios->power_mode) {
1451 case MMC_POWER_OFF:
1452 mmc_slot(host).set_power(host->dev, host->slot_id,
1453 0, 0);
623821f7 1454 host->vdd = 0;
a3621465
AH		 1455 break;
1456 case MMC_POWER_UP:
1457 mmc_slot(host).set_power(host->dev, host->slot_id,
1458 1, ios->vdd);
623821f7 1459 host->vdd = ios->vdd;
a3621465
AH		 1460 break;
1461 case MMC_POWER_ON:
1462 do_send_init_stream = 1;
1463 break;
1464 }
1465 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1466 }
1467
dd498eff
DK		 1468 /* FIXME: set registers based only on changes to ios */
1469
73153010 1470 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1471 switch (mmc->ios.bus_width) {
73153010
JL		 1472 case MMC_BUS_WIDTH_8:
1473 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
1474 break;
a45c6cb8 1475 case MMC_BUS_WIDTH_4:
73153010 1476 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1477 OMAP_HSMMC_WRITE(host->base, HCTL,
1478 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
1479 break;
1480 case MMC_BUS_WIDTH_1:
73153010 1481 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
a45c6cb8
MC		 1482 OMAP_HSMMC_WRITE(host->base, HCTL,
1483 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
1484 break;
1485 }
1486
1487 if (host->id == OMAP_MMC1_DEVID) {
eb250826
DB		 1488 /* Only MMC1 can interface at 3V without some flavor
1489 * of external transceiver; but they all handle 1.8V.
1490 */
a45c6cb8
MC		 1491 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1492 (ios->vdd == DUAL_VOLT_OCR_BIT)) {
1493 /*
1494 * The mmc_select_voltage fn of the core does
1495 * not seem to set the power_mode to
1496 * MMC_POWER_UP upon recalculating the voltage.
1497 * vdd 1.8v.
1498 */
70a3341a
DK		 1499 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1500 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1501 "Switch operation failed\n");
1502 }
1503 }
1504
1505 if (ios->clock) {
1506 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock;
1507 if (dsor < 1)
1508 dsor = 1;
1509
1510 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock)
1511 dsor++;
1512
1513 if (dsor > 250)
1514 dsor = 250;
1515 }
70a3341a 1516 omap_hsmmc_stop_clock(host);
a45c6cb8
MC		 1517 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
1518 regval = regval & ~(CLKD_MASK);
1519 regval = regval | (dsor << 6) | (DTO << 16);
1520 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
1521 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1522 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
1523
1524 /* Wait till the ICS bit is set */
1525 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
11dd62a7 1526 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
a45c6cb8
MC		 1527 && time_before(jiffies, timeout))
1528 msleep(1);
1529
1530 OMAP_HSMMC_WRITE(host->base, SYSCTL,
1531 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
1532
a3621465 1533 if (do_send_init_stream)
a45c6cb8
MC		 1534 send_init_stream(host);
1535
abb28e73 1536 con = OMAP_HSMMC_READ(host->base, CON);
a45c6cb8 1537 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
abb28e73
DK		 1538 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
1539 else
1540 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
5e2ea617 1541
dd498eff
DK		 1542 if (host->power_mode == MMC_POWER_OFF)
1543 mmc_host_disable(host->mmc);
1544 else
1545 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 1546}
1547
1548static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1549{
70a3341a 1550 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1551
191d1f1d 1552 if (!mmc_slot(host).card_detect)
a45c6cb8 1553 return -ENOSYS;
db0fefc5 1554 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1555}
1556
1557static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1558{
70a3341a 1559 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1560
191d1f1d 1561 if (!mmc_slot(host).get_ro)
a45c6cb8 1562 return -ENOSYS;
191d1f1d 1563 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1564}
1565
70a3341a 1566static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1567{
1568 u32 hctl, capa, value;
1569
1570 /* Only MMC1 supports 3.0V */
1571 if (host->id == OMAP_MMC1_DEVID) {
1572 hctl = SDVS30;
1573 capa = VS30 | VS18;
1574 } else {
1575 hctl = SDVS18;
1576 capa = VS18;
1577 }
1578
1579 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1580 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1581
1582 value = OMAP_HSMMC_READ(host->base, CAPA);
1583 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1584
1585 /* Set the controller to AUTO IDLE mode */
1586 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1587 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1588
1589 /* Set SD bus power bit */
e13bb300 1590 set_sd_bus_power(host);
1b331e69
KK		 1591}
1592
dd498eff
DK		 1593/*
1594 * Dynamic power saving handling, FSM:
13189e78
JL		 1595 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF
1596 * ^___________| | |
1597 * |______________________|______________________|
dd498eff
DK		 1598 *
1599 * ENABLED: mmc host is fully functional
1600 * DISABLED: fclk is off
13189e78
JL		 1601 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep
1602 * REGSLEEP: fclk is off, voltage regulator is asleep
1603 * OFF: fclk is off, voltage regulator is off
dd498eff
DK		 1604 *
1605 * Transition handlers return the timeout for the next state transition
1606 * or negative error.
1607 */
1608
13189e78 1609enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF};
dd498eff
DK		 1610
1611/* Handler for [ENABLED -> DISABLED] transition */
70a3341a 1612static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host)
dd498eff 1613{
70a3341a 1614 omap_hsmmc_context_save(host);
dd498eff
DK		 1615 clk_disable(host->fclk);
1616 host->dpm_state = DISABLED;
1617
1618 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n");
1619
1620 if (host->power_mode == MMC_POWER_OFF)
1621 return 0;
1622
13189e78 1623 return msecs_to_jiffies(OMAP_MMC_SLEEP_TIMEOUT);
dd498eff
DK		 1624}
1625
13189e78 1626/* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */
70a3341a 1627static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host)
dd498eff 1628{
13189e78 1629 int err, new_state;
dd498eff
DK		 1630
1631 if (!mmc_try_claim_host(host->mmc))
1632 return 0;
1633
1634 clk_enable(host->fclk);
70a3341a 1635 omap_hsmmc_context_restore(host);
13189e78
JL		 1636 if (mmc_card_can_sleep(host->mmc)) {
1637 err = mmc_card_sleep(host->mmc);
1638 if (err < 0) {
1639 clk_disable(host->fclk);
1640 mmc_release_host(host->mmc);
1641 return err;
1642 }
1643 new_state = CARDSLEEP;
70a3341a 1644 } else {
13189e78 1645 new_state = REGSLEEP;
70a3341a 1646 }
13189e78
JL		 1647 if (mmc_slot(host).set_sleep)
1648 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0,
1649 new_state == CARDSLEEP);
1650 /* FIXME: turn off bus power and perhaps interrupts too */
1651 clk_disable(host->fclk);
1652 host->dpm_state = new_state;
1653
1654 mmc_release_host(host->mmc);
1655
1656 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n",
1657 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1658
1659 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1660 mmc_slot(host).card_detect ||
1661 (mmc_slot(host).get_cover_state &&
13189e78
JL		 1662 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))
1663 return msecs_to_jiffies(OMAP_MMC_OFF_TIMEOUT);
1664
1665 return 0;
1666}
1667
1668/* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */
70a3341a 1669static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host)
13189e78
JL		 1670{
1671 if (!mmc_try_claim_host(host->mmc))
1672 return 0;
1673
1674 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
1675 mmc_slot(host).card_detect ||
1676 (mmc_slot(host).get_cover_state &&
1677 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) {
1678 mmc_release_host(host->mmc);
1679 return 0;
623821f7 1680 }
dd498eff 1681
13189e78
JL		 1682 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
1683 host->vdd = 0;
1684 host->power_mode = MMC_POWER_OFF;
dd498eff 1685
13189e78
JL		 1686 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n",
1687 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff 1688
13189e78 1689 host->dpm_state = OFF;
dd498eff
DK		 1690
1691 mmc_release_host(host->mmc);
1692
1693 return 0;
1694}
1695
1696/* Handler for [DISABLED -> ENABLED] transition */
70a3341a 1697static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host)
dd498eff
DK		 1698{
1699 int err;
1700
1701 err = clk_enable(host->fclk);
1702 if (err < 0)
1703 return err;
1704
70a3341a 1705 omap_hsmmc_context_restore(host);
dd498eff
DK		 1706 host->dpm_state = ENABLED;
1707
1708 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n");
1709
1710 return 0;
1711}
1712
13189e78 1713/* Handler for [SLEEP -> ENABLED] transition */
70a3341a 1714static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host)
dd498eff 1715{
13189e78
JL		 1716 if (!mmc_try_claim_host(host->mmc))
1717 return 0;
dd498eff 1718
13189e78 1719 clk_enable(host->fclk);
70a3341a 1720 omap_hsmmc_context_restore(host);
13189e78
JL		 1721 if (mmc_slot(host).set_sleep)
1722 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0,
1723 host->vdd, host->dpm_state == CARDSLEEP);
1724 if (mmc_card_can_sleep(host->mmc))
1725 mmc_card_awake(host->mmc);
1726
1727 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n",
1728 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP");
dd498eff
DK		 1729
1730 host->dpm_state = ENABLED;
1731
13189e78 1732 mmc_release_host(host->mmc);
dd498eff
DK		 1733
1734 return 0;
1735}
1736
13189e78 1737/* Handler for [OFF -> ENABLED] transition */
70a3341a 1738static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host)
623821f7 1739{
623821f7 1740 clk_enable(host->fclk);
623821f7 1741
70a3341a
DK		 1742 omap_hsmmc_context_restore(host);
1743 omap_hsmmc_conf_bus_power(host);
13189e78 1744 mmc_power_restore_host(host->mmc);
623821f7
AH		 1745
1746 host->dpm_state = ENABLED;
1747
13189e78
JL		 1748 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n");
1749
623821f7
AH		 1750 return 0;
1751}
1752
dd498eff
DK		 1753/*
1754 * Bring MMC host to ENABLED from any other PM state.
1755 */
70a3341a 1756static int omap_hsmmc_enable(struct mmc_host *mmc)
dd498eff 1757{
70a3341a 1758 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1759
1760 switch (host->dpm_state) {
1761 case DISABLED:
70a3341a 1762 return omap_hsmmc_disabled_to_enabled(host);
13189e78 1763 case CARDSLEEP:
623821f7 1764 case REGSLEEP:
70a3341a 1765 return omap_hsmmc_sleep_to_enabled(host);
dd498eff 1766 case OFF:
70a3341a 1767 return omap_hsmmc_off_to_enabled(host);
dd498eff
DK		 1768 default:
1769 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1770 return -EINVAL;
1771 }
1772}
1773
1774/*
1775 * Bring MMC host in PM state (one level deeper).
1776 */
70a3341a 1777static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy)
dd498eff 1778{
70a3341a 1779 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1780
1781 switch (host->dpm_state) {
1782 case ENABLED: {
1783 int delay;
1784
70a3341a 1785 delay = omap_hsmmc_enabled_to_disabled(host);
dd498eff
DK		 1786 if (lazy || delay < 0)
1787 return delay;
1788 return 0;
1789 }
1790 case DISABLED:
70a3341a 1791 return omap_hsmmc_disabled_to_sleep(host);
13189e78
JL		 1792 case CARDSLEEP:
1793 case REGSLEEP:
70a3341a 1794 return omap_hsmmc_sleep_to_off(host);
dd498eff
DK		 1795 default:
1796 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n");
1797 return -EINVAL;
1798 }
1799}
1800
70a3341a 1801static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1802{
70a3341a 1803 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff
DK		 1804 int err;
1805
1806 err = clk_enable(host->fclk);
1807 if (err)
1808 return err;
1809 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n");
70a3341a 1810 omap_hsmmc_context_restore(host);
dd498eff
DK		 1811 return 0;
1812}
1813
70a3341a 1814static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy)
dd498eff 1815{
70a3341a 1816 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1817
70a3341a 1818 omap_hsmmc_context_save(host);
dd498eff
DK		 1819 clk_disable(host->fclk);
1820 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n");
1821 return 0;
1822}
1823
70a3341a
DK		 1824static const struct mmc_host_ops omap_hsmmc_ops = {
1825 .enable = omap_hsmmc_enable_fclk,
1826 .disable = omap_hsmmc_disable_fclk,
1827 .request = omap_hsmmc_request,
1828 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1829 .get_cd = omap_hsmmc_get_cd,
1830 .get_ro = omap_hsmmc_get_ro,
1831 /* NYET -- enable_sdio_irq */
1832};
1833
70a3341a
DK		 1834static const struct mmc_host_ops omap_hsmmc_ps_ops = {
1835 .enable = omap_hsmmc_enable,
1836 .disable = omap_hsmmc_disable,
1837 .request = omap_hsmmc_request,
1838 .set_ios = omap_hsmmc_set_ios,
a45c6cb8
MC		 1839 .get_cd = omap_hsmmc_get_cd,
1840 .get_ro = omap_hsmmc_get_ro,
1841 /* NYET -- enable_sdio_irq */
1842};
1843
d900f712
DK		 1844#ifdef CONFIG_DEBUG_FS
1845
70a3341a 1846static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1847{
1848 struct mmc_host *mmc = s->private;
70a3341a 1849 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1850 int context_loss = 0;
1851
70a3341a
DK		 1852 if (host->pdata->get_context_loss_count)
1853 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1854
5e2ea617
AH		 1855 seq_printf(s, "mmc%d:\n"
1856 " enabled:\t%d\n"
dd498eff 1857 " dpm_state:\t%d\n"
5e2ea617 1858 " nesting_cnt:\t%d\n"
11dd62a7 1859 " ctx_loss:\t%d:%d\n"
5e2ea617 1860 "\nregs:\n",
dd498eff
DK		 1861 mmc->index, mmc->enabled ? 1 : 0,
1862 host->dpm_state, mmc->nesting_cnt,
11dd62a7 1863 host->context_loss, context_loss);
5e2ea617 1864
13189e78 1865 if (host->suspended || host->dpm_state == OFF) {
dd498eff
DK		 1866 seq_printf(s, "host suspended, can't read registers\n");
1867 return 0;
1868 }
1869
5e2ea617
AH		 1870 if (clk_enable(host->fclk) != 0) {
1871 seq_printf(s, "can't read the regs\n");
dd498eff 1872 return 0;
5e2ea617 1873 }
d900f712
DK		 1874
1875 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1876 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1877 seq_printf(s, "CON:\t\t0x%08x\n",
1878 OMAP_HSMMC_READ(host->base, CON));
1879 seq_printf(s, "HCTL:\t\t0x%08x\n",
1880 OMAP_HSMMC_READ(host->base, HCTL));
1881 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1882 OMAP_HSMMC_READ(host->base, SYSCTL));
1883 seq_printf(s, "IE:\t\t0x%08x\n",
1884 OMAP_HSMMC_READ(host->base, IE));
1885 seq_printf(s, "ISE:\t\t0x%08x\n",
1886 OMAP_HSMMC_READ(host->base, ISE));
1887 seq_printf(s, "CAPA:\t\t0x%08x\n",
1888 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617
AH		 1889
1890 clk_disable(host->fclk);
dd498eff 1891
d900f712
DK		 1892 return 0;
1893}
1894
70a3341a 1895static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1896{
70a3341a 1897 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1898}
1899
1900static const struct file_operations mmc_regs_fops = {
70a3341a 1901 .open = omap_hsmmc_regs_open,
d900f712
DK		 1902 .read = seq_read,
1903 .llseek = seq_lseek,
1904 .release = single_release,
1905};
1906
70a3341a 1907static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1908{
1909 if (mmc->debugfs_root)
1910 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1911 mmc, &mmc_regs_fops);
1912}
1913
1914#else
1915
70a3341a 1916static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1917{
1918}
1919
1920#endif
1921
70a3341a 1922static int __init omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1923{
1924 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1925 struct mmc_host *mmc;
70a3341a 1926 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1927 struct resource *res;
db0fefc5 1928 int ret, irq;
a45c6cb8
MC		 1929
1930 if (pdata == NULL) {
1931 dev_err(&pdev->dev, "Platform Data is missing\n");
1932 return -ENXIO;
1933 }
1934
1935 if (pdata->nr_slots == 0) {
1936 dev_err(&pdev->dev, "No Slots\n");
1937 return -ENXIO;
1938 }
1939
1940 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1941 irq = platform_get_irq(pdev, 0);
1942 if (res == NULL || irq < 0)
1943 return -ENXIO;
1944
1945 res = request_mem_region(res->start, res->end - res->start + 1,
1946 pdev->name);
1947 if (res == NULL)
1948 return -EBUSY;
1949
db0fefc5
AH		 1950 ret = omap_hsmmc_gpio_init(pdata);
1951 if (ret)
1952 goto err;
1953
70a3341a 1954 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1955 if (!mmc) {
1956 ret = -ENOMEM;
db0fefc5 1957 goto err_alloc;
a45c6cb8
MC		 1958 }
1959
1960 host = mmc_priv(mmc);
1961 host->mmc = mmc;
1962 host->pdata = pdata;
1963 host->dev = &pdev->dev;
1964 host->use_dma = 1;
1965 host->dev->dma_mask = &pdata->dma_mask;
1966 host->dma_ch = -1;
1967 host->irq = irq;
1968 host->id = pdev->id;
1969 host->slot_id = 0;
1970 host->mapbase = res->start;
1971 host->base = ioremap(host->mapbase, SZ_4K);
a3621465 1972 host->power_mode = -1;
a45c6cb8
MC		 1973
1974 platform_set_drvdata(pdev, host);
70a3341a 1975 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect);
a45c6cb8 1976
191d1f1d 1977 if (mmc_slot(host).power_saving)
70a3341a 1978 mmc->ops = &omap_hsmmc_ps_ops;
dd498eff 1979 else
70a3341a 1980 mmc->ops = &omap_hsmmc_ops;
dd498eff 1981
a45c6cb8
MC		 1982 mmc->f_min = 400000;
1983 mmc->f_max = 52000000;
1984
1985 sema_init(&host->sem, 1);
4dffd7a2 1986 spin_lock_init(&host->irq_lock);
a45c6cb8 1987
6f7607cc 1988 host->iclk = clk_get(&pdev->dev, "ick");
a45c6cb8
MC		 1989 if (IS_ERR(host->iclk)) {
1990 ret = PTR_ERR(host->iclk);
1991 host->iclk = NULL;
1992 goto err1;
1993 }
6f7607cc 1994 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1995 if (IS_ERR(host->fclk)) {
1996 ret = PTR_ERR(host->fclk);
1997 host->fclk = NULL;
1998 clk_put(host->iclk);
1999 goto err1;
2000 }
2001
70a3341a 2002 omap_hsmmc_context_save(host);
11dd62a7 2003
5e2ea617 2004 mmc->caps |= MMC_CAP_DISABLE;
dd498eff
DK		 2005 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT);
2006 /* we start off in DISABLED state */
2007 host->dpm_state = DISABLED;
2008
5e2ea617 2009 if (mmc_host_enable(host->mmc) != 0) {
a45c6cb8
MC		 2010 clk_put(host->iclk);
2011 clk_put(host->fclk);
2012 goto err1;
2013 }
2014
2015 if (clk_enable(host->iclk) != 0) {
5e2ea617 2016 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2017 clk_put(host->iclk);
2018 clk_put(host->fclk);
2019 goto err1;
2020 }
2021
2bec0893
AH		 2022 if (cpu_is_omap2430()) {
2023 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
2024 /*
2025 * MMC can still work without debounce clock.
2026 */
2027 if (IS_ERR(host->dbclk))
2028 dev_warn(mmc_dev(host->mmc),
2029 "Failed to get debounce clock\n");
a45c6cb8 2030 else
2bec0893
AH		 2031 host->got_dbclk = 1;
2032
2033 if (host->got_dbclk)
2034 if (clk_enable(host->dbclk) != 0)
2035 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
2036 " clk failed\n");
2037 }
a45c6cb8 2038
0ccd76d4
JY		 2039 /* Since we do only SG emulation, we can have as many segs
2040 * as we want. */
2041 mmc->max_phys_segs = 1024;
2042 mmc->max_hw_segs = 1024;
2043
a45c6cb8
MC		 2044 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
2045 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
2046 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
2047 mmc->max_seg_size = mmc->max_req_size;
2048
13189e78
JL		 2049 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
2050 MMC_CAP_WAIT_WHILE_BUSY;
a45c6cb8 2051
191d1f1d 2052 if (mmc_slot(host).wires >= 8)
73153010 2053 mmc->caps |= MMC_CAP_8_BIT_DATA;
191d1f1d 2054 else if (mmc_slot(host).wires >= 4)
a45c6cb8
MC		 2055 mmc->caps |= MMC_CAP_4_BIT_DATA;
2056
191d1f1d 2057 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 2058 mmc->caps |= MMC_CAP_NONREMOVABLE;
2059
70a3341a 2060 omap_hsmmc_conf_bus_power(host);
a45c6cb8 2061
f3e2f1dd
GI		 2062 /* Select DMA lines */
2063 switch (host->id) {
2064 case OMAP_MMC1_DEVID:
2065 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX;
2066 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX;
2067 break;
2068 case OMAP_MMC2_DEVID:
2069 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX;
2070 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX;
2071 break;
2072 case OMAP_MMC3_DEVID:
2073 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX;
2074 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX;
2075 break;
82cf818d 2076 case OMAP_MMC4_DEVID:
2077 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX;
2078 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX;
2079 break;
2080 case OMAP_MMC5_DEVID:
2081 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX;
2082 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX;
2083 break;
f3e2f1dd
GI		 2084 default:
2085 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n");
2086 goto err_irq;
2087 }
a45c6cb8
MC		 2088
2089 /* Request IRQ for MMC operations */
70a3341a 2090 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED,
a45c6cb8
MC		 2091 mmc_hostname(mmc), host);
2092 if (ret) {
2093 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
2094 goto err_irq;
2095 }
2096
2097 if (pdata->init != NULL) {
2098 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 2099 dev_dbg(mmc_dev(host->mmc),
2100 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 2101 goto err_irq_cd_init;
2102 }
2103 }
db0fefc5
AH		 2104
2105 if (!mmc_slot(host).set_power) {
2106 ret = omap_hsmmc_reg_get(host);
2107 if (ret)
2108 goto err_reg;
2109 host->use_reg = 1;
2110 }
2111
b583f26d 2112 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 2113
2114 /* Request IRQ for card detect */
e1a55f5e 2115 if ((mmc_slot(host).card_detect_irq)) {
a45c6cb8 2116 ret = request_irq(mmc_slot(host).card_detect_irq,
70a3341a 2117 omap_hsmmc_cd_handler,
a45c6cb8
MC		 2118 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
2119 | IRQF_DISABLED,
2120 mmc_hostname(mmc), host);
2121 if (ret) {
2122 dev_dbg(mmc_dev(host->mmc),
2123 "Unable to grab MMC CD IRQ\n");
2124 goto err_irq_cd;
2125 }
2126 }
2127
2128 OMAP_HSMMC_WRITE(host->base, ISE, INT_EN_MASK);
2129 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
2130
5e2ea617
AH		 2131 mmc_host_lazy_disable(host->mmc);
2132
b62f6228
AH		 2133 omap_hsmmc_protect_card(host);
2134
a45c6cb8
MC		 2135 mmc_add_host(mmc);
2136
191d1f1d 2137 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 2138 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2139 if (ret < 0)
2140 goto err_slot_name;
2141 }
191d1f1d 2142 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2143 ret = device_create_file(&mmc->class_dev,
2144 &dev_attr_cover_switch);
2145 if (ret < 0)
db0fefc5 2146 goto err_slot_name;
a45c6cb8
MC		 2147 }
2148
70a3341a 2149 omap_hsmmc_debugfs(mmc);
d900f712 2150
a45c6cb8
MC		 2151 return 0;
2152
a45c6cb8
MC		 2153err_slot_name:
2154 mmc_remove_host(mmc);
a45c6cb8 2155 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2156err_irq_cd:
2157 if (host->use_reg)
2158 omap_hsmmc_reg_put(host);
2159err_reg:
2160 if (host->pdata->cleanup)
2161 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2162err_irq_cd_init:
2163 free_irq(host->irq, host);
2164err_irq:
5e2ea617 2165 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2166 clk_disable(host->iclk);
2167 clk_put(host->fclk);
2168 clk_put(host->iclk);
2bec0893 2169 if (host->got_dbclk) {
a45c6cb8
MC		 2170 clk_disable(host->dbclk);
2171 clk_put(host->dbclk);
2172 }
a45c6cb8
MC		 2173err1:
2174 iounmap(host->base);
db0fefc5
AH		 2175 platform_set_drvdata(pdev, NULL);
2176 mmc_free_host(mmc);
2177err_alloc:
2178 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2179err:
a45c6cb8 2180 release_mem_region(res->start, res->end - res->start + 1);
a45c6cb8
MC		 2181 return ret;
2182}
2183
70a3341a 2184static int omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2185{
70a3341a 2186 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2187 struct resource *res;
2188
2189 if (host) {
5e2ea617 2190 mmc_host_enable(host->mmc);
a45c6cb8 2191 mmc_remove_host(host->mmc);
db0fefc5
AH		 2192 if (host->use_reg)
2193 omap_hsmmc_reg_put(host);
a45c6cb8
MC		 2194 if (host->pdata->cleanup)
2195 host->pdata->cleanup(&pdev->dev);
2196 free_irq(host->irq, host);
2197 if (mmc_slot(host).card_detect_irq)
2198 free_irq(mmc_slot(host).card_detect_irq, host);
2199 flush_scheduled_work();
2200
5e2ea617 2201 mmc_host_disable(host->mmc);
a45c6cb8
MC		 2202 clk_disable(host->iclk);
2203 clk_put(host->fclk);
2204 clk_put(host->iclk);
2bec0893 2205 if (host->got_dbclk) {
a45c6cb8
MC		 2206 clk_disable(host->dbclk);
2207 clk_put(host->dbclk);
2208 }
2209
2210 mmc_free_host(host->mmc);
2211 iounmap(host->base);
db0fefc5 2212 omap_hsmmc_gpio_free(pdev->dev.platform_data);
a45c6cb8
MC		 2213 }
2214
2215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2216 if (res)
2217 release_mem_region(res->start, res->end - res->start + 1);
2218 platform_set_drvdata(pdev, NULL);
2219
2220 return 0;
2221}
2222
2223#ifdef CONFIG_PM
70a3341a 2224static int omap_hsmmc_suspend(struct platform_device *pdev, pm_message_t state)
a45c6cb8
MC		 2225{
2226 int ret = 0;
70a3341a 2227 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2228
2229 if (host && host->suspended)
2230 return 0;
2231
2232 if (host) {
a6b2240d
AH		 2233 host->suspended = 1;
2234 if (host->pdata->suspend) {
2235 ret = host->pdata->suspend(&pdev->dev,
2236 host->slot_id);
2237 if (ret) {
2238 dev_dbg(mmc_dev(host->mmc),
2239 "Unable to handle MMC board"
2240 " level suspend\n");
2241 host->suspended = 0;
2242 return ret;
2243 }
2244 }
2245 cancel_work_sync(&host->mmc_carddetect_work);
5e2ea617 2246 mmc_host_enable(host->mmc);
a45c6cb8
MC		 2247 ret = mmc_suspend_host(host->mmc, state);
2248 if (ret == 0) {
a45c6cb8
MC		 2249 OMAP_HSMMC_WRITE(host->base, ISE, 0);
2250 OMAP_HSMMC_WRITE(host->base, IE, 0);
2251
a45c6cb8 2252
0683af48 2253 OMAP_HSMMC_WRITE(host->base, HCTL,
191d1f1d 2254 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
5e2ea617 2255 mmc_host_disable(host->mmc);
a45c6cb8 2256 clk_disable(host->iclk);
2bec0893
AH		 2257 if (host->got_dbclk)
2258 clk_disable(host->dbclk);
a6b2240d
AH		 2259 } else {
2260 host->suspended = 0;
2261 if (host->pdata->resume) {
2262 ret = host->pdata->resume(&pdev->dev,
2263 host->slot_id);
2264 if (ret)
2265 dev_dbg(mmc_dev(host->mmc),
2266 "Unmask interrupt failed\n");
2267 }
5e2ea617 2268 mmc_host_disable(host->mmc);
a6b2240d 2269 }
a45c6cb8
MC		 2270
2271 }
2272 return ret;
2273}
2274
2275/* Routine to resume the MMC device */
70a3341a 2276static int omap_hsmmc_resume(struct platform_device *pdev)
a45c6cb8
MC		 2277{
2278 int ret = 0;
70a3341a 2279 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2280
2281 if (host && !host->suspended)
2282 return 0;
2283
2284 if (host) {
a45c6cb8 2285 ret = clk_enable(host->iclk);
11dd62a7 2286 if (ret)
a45c6cb8 2287 goto clk_en_err;
a45c6cb8 2288
11dd62a7
DK		 2289 if (mmc_host_enable(host->mmc) != 0) {
2290 clk_disable(host->iclk);
2291 goto clk_en_err;
2292 }
2293
2bec0893
AH		 2294 if (host->got_dbclk)
2295 clk_enable(host->dbclk);
2296
70a3341a 2297 omap_hsmmc_conf_bus_power(host);
1b331e69 2298
a45c6cb8
MC		 2299 if (host->pdata->resume) {
2300 ret = host->pdata->resume(&pdev->dev, host->slot_id);
2301 if (ret)
2302 dev_dbg(mmc_dev(host->mmc),
2303 "Unmask interrupt failed\n");
2304 }
2305
b62f6228
AH		 2306 omap_hsmmc_protect_card(host);
2307
a45c6cb8
MC		 2308 /* Notify the core to resume the host */
2309 ret = mmc_resume_host(host->mmc);
2310 if (ret == 0)
2311 host->suspended = 0;
70a3341a 2312
5e2ea617 2313 mmc_host_lazy_disable(host->mmc);
a45c6cb8
MC		 2314 }
2315
2316 return ret;
2317
2318clk_en_err:
2319 dev_dbg(mmc_dev(host->mmc),
2320 "Failed to enable MMC clocks during resume\n");
2321 return ret;
2322}
2323
2324#else
70a3341a
DK		 2325#define omap_hsmmc_suspend NULL
2326#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2327#endif
2328
70a3341a
DK		 2329static struct platform_driver omap_hsmmc_driver = {
2330 .remove = omap_hsmmc_remove,
2331 .suspend = omap_hsmmc_suspend,
2332 .resume = omap_hsmmc_resume,
a45c6cb8
MC		 2333 .driver = {
2334 .name = DRIVER_NAME,
2335 .owner = THIS_MODULE,
2336 },
2337};
2338
70a3341a 2339static int __init omap_hsmmc_init(void)
a45c6cb8
MC		 2340{
2341 /* Register the MMC driver */
8753298a 2342 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe);
a45c6cb8
MC		 2343}
2344
70a3341a 2345static void __exit omap_hsmmc_cleanup(void)
a45c6cb8
MC		 2346{
2347 /* Unregister MMC driver */
70a3341a 2348 platform_driver_unregister(&omap_hsmmc_driver);
a45c6cb8
MC		 2349}
2350
70a3341a
DK		 2351module_init(omap_hsmmc_init);
2352module_exit(omap_hsmmc_cleanup);
a45c6cb8
MC		 2353
2354MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2355MODULE_LICENSE("GPL");
2356MODULE_ALIAS("platform:" DRIVER_NAME);
2357MODULE_AUTHOR("Texas Instruments Inc");
ubuntu-bionic-kernel mirror