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mmc: omap_hsmmc: Enable Auto CMD12
[mirror_ubuntu-hirsute-kernel.git] / drivers / mmc / host / omap_hsmmc.c
CommitLineData
a45c6cb8
MC		 1/*
2 * drivers/mmc/host/omap_hsmmc.c
3 *
4 * Driver for OMAP2430/3430 MMC controller.
5 *
6 * Copyright (C) 2007 Texas Instruments.
7 *
8 * Authors:
9 * Syed Mohammed Khasim <x0khasim@ti.com>
10 * Madhusudhan <madhu.cr@ti.com>
11 * Mohit Jalori <mjalori@ti.com>
12 *
13 * This file is licensed under the terms of the GNU General Public License
14 * version 2. This program is licensed "as is" without any warranty of any
15 * kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
ac330f44 20#include <linux/kernel.h>
d900f712
DK		 21#include <linux/debugfs.h>
22#include <linux/seq_file.h>
a45c6cb8
MC		 23#include <linux/interrupt.h>
24#include <linux/delay.h>
25#include <linux/dma-mapping.h>
26#include <linux/platform_device.h>
a45c6cb8
MC		 27#include <linux/timer.h>
28#include <linux/clk.h>
46856a68
RN		 29#include <linux/of.h>
30#include <linux/of_gpio.h>
31#include <linux/of_device.h>
a45c6cb8 32#include <linux/mmc/host.h>
13189e78 33#include <linux/mmc/core.h>
93caf8e6 34#include <linux/mmc/mmc.h>
a45c6cb8
MC		 35#include <linux/io.h>
36#include <linux/semaphore.h>
db0fefc5
AH		 37#include <linux/gpio.h>
38#include <linux/regulator/consumer.h>
fa4aa2d4 39#include <linux/pm_runtime.h>
ce491cf8 40#include <plat/dma.h>
a45c6cb8 41#include <mach/hardware.h>
ce491cf8
TL		 42#include <plat/board.h>
43#include <plat/mmc.h>
44#include <plat/cpu.h>
a45c6cb8
MC		 45
46/* OMAP HSMMC Host Controller Registers */
47#define OMAP_HSMMC_SYSCONFIG 0x0010
11dd62a7 48#define OMAP_HSMMC_SYSSTATUS 0x0014
a45c6cb8
MC		 49#define OMAP_HSMMC_CON 0x002C
50#define OMAP_HSMMC_BLK 0x0104
51#define OMAP_HSMMC_ARG 0x0108
52#define OMAP_HSMMC_CMD 0x010C
53#define OMAP_HSMMC_RSP10 0x0110
54#define OMAP_HSMMC_RSP32 0x0114
55#define OMAP_HSMMC_RSP54 0x0118
56#define OMAP_HSMMC_RSP76 0x011C
57#define OMAP_HSMMC_DATA 0x0120
58#define OMAP_HSMMC_HCTL 0x0128
59#define OMAP_HSMMC_SYSCTL 0x012C
60#define OMAP_HSMMC_STAT 0x0130
61#define OMAP_HSMMC_IE 0x0134
62#define OMAP_HSMMC_ISE 0x0138
63#define OMAP_HSMMC_CAPA 0x0140
64
65#define VS18 (1 << 26)
66#define VS30 (1 << 25)
67#define SDVS18 (0x5 << 9)
68#define SDVS30 (0x6 << 9)
eb250826 69#define SDVS33 (0x7 << 9)
1b331e69 70#define SDVS_MASK 0x00000E00
a45c6cb8
MC		 71#define SDVSCLR 0xFFFFF1FF
72#define SDVSDET 0x00000400
73#define AUTOIDLE 0x1
74#define SDBP (1 << 8)
75#define DTO 0xe
76#define ICE 0x1
77#define ICS 0x2
78#define CEN (1 << 2)
79#define CLKD_MASK 0x0000FFC0
80#define CLKD_SHIFT 6
81#define DTO_MASK 0x000F0000
82#define DTO_SHIFT 16
83#define INT_EN_MASK 0x307F0033
ccdfe3a6
AG		 84#define BWR_ENABLE (1 << 4)
85#define BRR_ENABLE (1 << 5)
93caf8e6 86#define DTO_ENABLE (1 << 20)
a45c6cb8 87#define INIT_STREAM (1 << 1)
dba3c29e 88#define ACEN_ACMD12 (1 << 2)
a45c6cb8
MC		 89#define DP_SELECT (1 << 21)
90#define DDIR (1 << 4)
91#define DMA_EN 0x1
92#define MSBS (1 << 5)
93#define BCE (1 << 1)
94#define FOUR_BIT (1 << 1)
73153010 95#define DW8 (1 << 5)
a45c6cb8
MC		 96#define CC 0x1
97#define TC 0x02
98#define OD 0x1
99#define ERR (1 << 15)
100#define CMD_TIMEOUT (1 << 16)
101#define DATA_TIMEOUT (1 << 20)
102#define CMD_CRC (1 << 17)
103#define DATA_CRC (1 << 21)
104#define CARD_ERR (1 << 28)
105#define STAT_CLEAR 0xFFFFFFFF
106#define INIT_STREAM_CMD 0x00000000
107#define DUAL_VOLT_OCR_BIT 7
108#define SRC (1 << 25)
109#define SRD (1 << 26)
11dd62a7
DK		 110#define SOFTRESET (1 << 1)
111#define RESETDONE (1 << 0)
a45c6cb8 112
fa4aa2d4 113#define MMC_AUTOSUSPEND_DELAY 100
a45c6cb8 114#define MMC_TIMEOUT_MS 20
6b206efe
AS		 115#define OMAP_MMC_MIN_CLOCK 400000
116#define OMAP_MMC_MAX_CLOCK 52000000
0005ae73 117#define DRIVER_NAME "omap_hsmmc"
a45c6cb8 118
dba3c29e 119#define AUTO_CMD12 (1 << 0) /* Auto CMD12 support */
a45c6cb8
MC		 120/*
121 * One controller can have multiple slots, like on some omap boards using
122 * omap.c controller driver. Luckily this is not currently done on any known
123 * omap_hsmmc.c device.
124 */
125#define mmc_slot(host) (host->pdata->slots[host->slot_id])
126
127/*
128 * MMC Host controller read/write API's
129 */
130#define OMAP_HSMMC_READ(base, reg) \
131 __raw_readl((base) + OMAP_HSMMC_##reg)
132
133#define OMAP_HSMMC_WRITE(base, reg, val) \
134 __raw_writel((val), (base) + OMAP_HSMMC_##reg)
135
9782aff8
PF		 136struct omap_hsmmc_next {
137 unsigned int dma_len;
138 s32 cookie;
139};
140
70a3341a 141struct omap_hsmmc_host {
a45c6cb8
MC		 142 struct device *dev;
143 struct mmc_host *mmc;
144 struct mmc_request *mrq;
145 struct mmc_command *cmd;
146 struct mmc_data *data;
147 struct clk *fclk;
a45c6cb8 148 struct clk *dbclk;
db0fefc5
AH		 149 /*
150 * vcc == configured supply
151 * vcc_aux == optional
152 * - MMC1, supply for DAT4..DAT7
153 * - MMC2/MMC2, external level shifter voltage supply, for
154 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only)
155 */
156 struct regulator *vcc;
157 struct regulator *vcc_aux;
a45c6cb8
MC		 158 void __iomem *base;
159 resource_size_t mapbase;
4dffd7a2 160 spinlock_t irq_lock; /* Prevent races with irq handler */
a45c6cb8 161 unsigned int dma_len;
0ccd76d4 162 unsigned int dma_sg_idx;
a45c6cb8 163 unsigned char bus_mode;
a3621465 164 unsigned char power_mode;
a45c6cb8
MC		 165 u32 *buffer;
166 u32 bytesleft;
167 int suspended;
168 int irq;
a45c6cb8 169 int use_dma, dma_ch;
f3e2f1dd 170 int dma_line_tx, dma_line_rx;
a45c6cb8 171 int slot_id;
2bec0893 172 int got_dbclk;
4a694dc9 173 int response_busy;
11dd62a7 174 int context_loss;
623821f7 175 int vdd;
b62f6228
AH		 176 int protect_card;
177 int reqs_blocked;
db0fefc5 178 int use_reg;
b417577d 179 int req_in_progress;
dba3c29e 180 unsigned int flags;
9782aff8 181 struct omap_hsmmc_next next_data;
11dd62a7 182
a45c6cb8
MC		 183 struct omap_mmc_platform_data *pdata;
184};
185
db0fefc5
AH		 186static int omap_hsmmc_card_detect(struct device *dev, int slot)
187{
188 struct omap_mmc_platform_data *mmc = dev->platform_data;
189
190 /* NOTE: assumes card detect signal is active-low */
191 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
192}
193
194static int omap_hsmmc_get_wp(struct device *dev, int slot)
195{
196 struct omap_mmc_platform_data *mmc = dev->platform_data;
197
198 /* NOTE: assumes write protect signal is active-high */
199 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp);
200}
201
202static int omap_hsmmc_get_cover_state(struct device *dev, int slot)
203{
204 struct omap_mmc_platform_data *mmc = dev->platform_data;
205
206 /* NOTE: assumes card detect signal is active-low */
207 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin);
208}
209
210#ifdef CONFIG_PM
211
212static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot)
213{
214 struct omap_mmc_platform_data *mmc = dev->platform_data;
215
216 disable_irq(mmc->slots[0].card_detect_irq);
217 return 0;
218}
219
220static int omap_hsmmc_resume_cdirq(struct device *dev, int slot)
221{
222 struct omap_mmc_platform_data *mmc = dev->platform_data;
223
224 enable_irq(mmc->slots[0].card_detect_irq);
225 return 0;
226}
227
228#else
229
230#define omap_hsmmc_suspend_cdirq NULL
231#define omap_hsmmc_resume_cdirq NULL
232
233#endif
234
b702b106
AH		 235#ifdef CONFIG_REGULATOR
236
69b07ece 237static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
db0fefc5
AH		 238 int vdd)
239{
240 struct omap_hsmmc_host *host =
241 platform_get_drvdata(to_platform_device(dev));
242 int ret = 0;
243
244 /*
245 * If we don't see a Vcc regulator, assume it's a fixed
246 * voltage always-on regulator.
247 */
248 if (!host->vcc)
249 return 0;
1f84b71b
RN		 250 /*
251 * With DT, never turn OFF the regulator. This is because
252 * the pbias cell programming support is still missing when
253 * booting with Device tree
254 */
4d048f91 255 if (dev->of_node && !vdd)
1f84b71b 256 return 0;
db0fefc5
AH		 257
258 if (mmc_slot(host).before_set_reg)
259 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd);
260
261 /*
262 * Assume Vcc regulator is used only to power the card ... OMAP
263 * VDDS is used to power the pins, optionally with a transceiver to
264 * support cards using voltages other than VDDS (1.8V nominal). When a
265 * transceiver is used, DAT3..7 are muxed as transceiver control pins.
266 *
267 * In some cases this regulator won't support enable/disable;
268 * e.g. it's a fixed rail for a WLAN chip.
269 *
270 * In other cases vcc_aux switches interface power. Example, for
271 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO
272 * chips/cards need an interface voltage rail too.
273 */
274 if (power_on) {
99fc5131 275 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
db0fefc5
AH		 276 /* Enable interface voltage rail, if needed */
277 if (ret == 0 && host->vcc_aux) {
278 ret = regulator_enable(host->vcc_aux);
279 if (ret < 0)
99fc5131
LW		 280 ret = mmc_regulator_set_ocr(host->mmc,
281 host->vcc, 0);
db0fefc5
AH		 282 }
283 } else {
99fc5131 284 /* Shut down the rail */
6da20c89
AH		 285 if (host->vcc_aux)
286 ret = regulator_disable(host->vcc_aux);
99fc5131
LW		 287 if (!ret) {
288 /* Then proceed to shut down the local regulator */
289 ret = mmc_regulator_set_ocr(host->mmc,
290 host->vcc, 0);
291 }
db0fefc5
AH		 292 }
293
294 if (mmc_slot(host).after_set_reg)
295 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd);
296
297 return ret;
298}
299
db0fefc5
AH		 300static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
301{
302 struct regulator *reg;
64be9782 303 int ocr_value = 0;
db0fefc5 304
1cb9af49 305 mmc_slot(host).set_power = omap_hsmmc_set_power;
db0fefc5
AH		 306
307 reg = regulator_get(host->dev, "vmmc");
308 if (IS_ERR(reg)) {
309 dev_dbg(host->dev, "vmmc regulator missing\n");
db0fefc5
AH		 310 } else {
311 host->vcc = reg;
64be9782 312 ocr_value = mmc_regulator_get_ocrmask(reg);
313 if (!mmc_slot(host).ocr_mask) {
314 mmc_slot(host).ocr_mask = ocr_value;
315 } else {
316 if (!(mmc_slot(host).ocr_mask & ocr_value)) {
2cecdf00 317 dev_err(host->dev, "ocrmask %x is not supported\n",
e3f1adb6 318 mmc_slot(host).ocr_mask);
64be9782 319 mmc_slot(host).ocr_mask = 0;
320 return -EINVAL;
321 }
322 }
db0fefc5
AH		 323
324 /* Allow an aux regulator */
325 reg = regulator_get(host->dev, "vmmc_aux");
326 host->vcc_aux = IS_ERR(reg) ? NULL : reg;
327
b1c1df7a
B		 328 /* For eMMC do not power off when not in sleep state */
329 if (mmc_slot(host).no_regulator_off_init)
330 return 0;
db0fefc5
AH		 331 /*
332 * UGLY HACK: workaround regulator framework bugs.
333 * When the bootloader leaves a supply active, it's
334 * initialized with zero usecount ... and we can't
335 * disable it without first enabling it. Until the
336 * framework is fixed, we need a workaround like this
337 * (which is safe for MMC, but not in general).
338 */
e840ce13
AH		 339 if (regulator_is_enabled(host->vcc) > 0 ||
340 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) {
341 int vdd = ffs(mmc_slot(host).ocr_mask) - 1;
342
343 mmc_slot(host).set_power(host->dev, host->slot_id,
344 1, vdd);
345 mmc_slot(host).set_power(host->dev, host->slot_id,
346 0, 0);
db0fefc5
AH		 347 }
348 }
349
350 return 0;
db0fefc5
AH		 351}
352
353static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
354{
355 regulator_put(host->vcc);
356 regulator_put(host->vcc_aux);
357 mmc_slot(host).set_power = NULL;
db0fefc5
AH		 358}
359
b702b106
AH		 360static inline int omap_hsmmc_have_reg(void)
361{
362 return 1;
363}
364
365#else
366
367static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host)
368{
369 return -EINVAL;
370}
371
372static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host)
373{
374}
375
376static inline int omap_hsmmc_have_reg(void)
377{
378 return 0;
379}
380
381#endif
382
383static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata)
384{
385 int ret;
386
387 if (gpio_is_valid(pdata->slots[0].switch_pin)) {
b702b106
AH		 388 if (pdata->slots[0].cover)
389 pdata->slots[0].get_cover_state =
390 omap_hsmmc_get_cover_state;
391 else
392 pdata->slots[0].card_detect = omap_hsmmc_card_detect;
393 pdata->slots[0].card_detect_irq =
394 gpio_to_irq(pdata->slots[0].switch_pin);
395 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd");
396 if (ret)
397 return ret;
398 ret = gpio_direction_input(pdata->slots[0].switch_pin);
399 if (ret)
400 goto err_free_sp;
401 } else
402 pdata->slots[0].switch_pin = -EINVAL;
403
404 if (gpio_is_valid(pdata->slots[0].gpio_wp)) {
405 pdata->slots[0].get_ro = omap_hsmmc_get_wp;
406 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp");
407 if (ret)
408 goto err_free_cd;
409 ret = gpio_direction_input(pdata->slots[0].gpio_wp);
410 if (ret)
411 goto err_free_wp;
412 } else
413 pdata->slots[0].gpio_wp = -EINVAL;
414
415 return 0;
416
417err_free_wp:
418 gpio_free(pdata->slots[0].gpio_wp);
419err_free_cd:
420 if (gpio_is_valid(pdata->slots[0].switch_pin))
421err_free_sp:
422 gpio_free(pdata->slots[0].switch_pin);
423 return ret;
424}
425
426static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata)
427{
428 if (gpio_is_valid(pdata->slots[0].gpio_wp))
429 gpio_free(pdata->slots[0].gpio_wp);
430 if (gpio_is_valid(pdata->slots[0].switch_pin))
431 gpio_free(pdata->slots[0].switch_pin);
432}
433
e0c7f99b
AS		 434/*
435 * Start clock to the card
436 */
437static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host)
438{
439 OMAP_HSMMC_WRITE(host->base, SYSCTL,
440 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN);
441}
442
a45c6cb8
MC		 443/*
444 * Stop clock to the card
445 */
70a3341a 446static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host)
a45c6cb8
MC		 447{
448 OMAP_HSMMC_WRITE(host->base, SYSCTL,
449 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN);
450 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0)
451 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n");
452}
453
93caf8e6
AH		 454static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host,
455 struct mmc_command *cmd)
b417577d
AH		 456{
457 unsigned int irq_mask;
458
459 if (host->use_dma)
460 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE);
461 else
462 irq_mask = INT_EN_MASK;
463
93caf8e6
AH		 464 /* Disable timeout for erases */
465 if (cmd->opcode == MMC_ERASE)
466 irq_mask &= ~DTO_ENABLE;
467
b417577d
AH		 468 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
469 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask);
470 OMAP_HSMMC_WRITE(host->base, IE, irq_mask);
471}
472
473static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host)
474{
475 OMAP_HSMMC_WRITE(host->base, ISE, 0);
476 OMAP_HSMMC_WRITE(host->base, IE, 0);
477 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
478}
479
ac330f44 480/* Calculate divisor for the given clock frequency */
d83b6e03 481static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios)
ac330f44
AS		 482{
483 u16 dsor = 0;
484
485 if (ios->clock) {
d83b6e03 486 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock);
ac330f44
AS		 487 if (dsor > 250)
488 dsor = 250;
489 }
490
491 return dsor;
492}
493
5934df2f
AS		 494static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host)
495{
496 struct mmc_ios *ios = &host->mmc->ios;
497 unsigned long regval;
498 unsigned long timeout;
499
500 dev_dbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock);
501
502 omap_hsmmc_stop_clock(host);
503
504 regval = OMAP_HSMMC_READ(host->base, SYSCTL);
505 regval = regval & ~(CLKD_MASK | DTO_MASK);
d83b6e03 506 regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16);
5934df2f
AS		 507 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval);
508 OMAP_HSMMC_WRITE(host->base, SYSCTL,
509 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE);
510
511 /* Wait till the ICS bit is set */
512 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
513 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS
514 && time_before(jiffies, timeout))
515 cpu_relax();
516
517 omap_hsmmc_start_clock(host);
518}
519
3796fb8a
AS		 520static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host)
521{
522 struct mmc_ios *ios = &host->mmc->ios;
523 u32 con;
524
525 con = OMAP_HSMMC_READ(host->base, CON);
526 switch (ios->bus_width) {
527 case MMC_BUS_WIDTH_8:
528 OMAP_HSMMC_WRITE(host->base, CON, con | DW8);
529 break;
530 case MMC_BUS_WIDTH_4:
531 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
532 OMAP_HSMMC_WRITE(host->base, HCTL,
533 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT);
534 break;
535 case MMC_BUS_WIDTH_1:
536 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8);
537 OMAP_HSMMC_WRITE(host->base, HCTL,
538 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT);
539 break;
540 }
541}
542
543static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host)
544{
545 struct mmc_ios *ios = &host->mmc->ios;
546 u32 con;
547
548 con = OMAP_HSMMC_READ(host->base, CON);
549 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
550 OMAP_HSMMC_WRITE(host->base, CON, con | OD);
551 else
552 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD);
553}
554
11dd62a7
DK		 555#ifdef CONFIG_PM
556
557/*
558 * Restore the MMC host context, if it was lost as result of a
559 * power state change.
560 */
70a3341a 561static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 562{
563 struct mmc_ios *ios = &host->mmc->ios;
564 struct omap_mmc_platform_data *pdata = host->pdata;
565 int context_loss = 0;
3796fb8a 566 u32 hctl, capa;
11dd62a7
DK		 567 unsigned long timeout;
568
569 if (pdata->get_context_loss_count) {
570 context_loss = pdata->get_context_loss_count(host->dev);
571 if (context_loss < 0)
572 return 1;
573 }
574
575 dev_dbg(mmc_dev(host->mmc), "context was %slost\n",
576 context_loss == host->context_loss ? "not " : "");
577 if (host->context_loss == context_loss)
578 return 1;
579
580 /* Wait for hardware reset */
581 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
582 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
583 && time_before(jiffies, timeout))
584 ;
585
586 /* Do software reset */
587 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET);
588 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
589 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE
590 && time_before(jiffies, timeout))
591 ;
592
593 OMAP_HSMMC_WRITE(host->base, SYSCONFIG,
594 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE);
595
c2200efb 596 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
11dd62a7
DK		 597 if (host->power_mode != MMC_POWER_OFF &&
598 (1 << ios->vdd) <= MMC_VDD_23_24)
599 hctl = SDVS18;
600 else
601 hctl = SDVS30;
602 capa = VS30 | VS18;
603 } else {
604 hctl = SDVS18;
605 capa = VS18;
606 }
607
608 OMAP_HSMMC_WRITE(host->base, HCTL,
609 OMAP_HSMMC_READ(host->base, HCTL) | hctl);
610
611 OMAP_HSMMC_WRITE(host->base, CAPA,
612 OMAP_HSMMC_READ(host->base, CAPA) | capa);
613
614 OMAP_HSMMC_WRITE(host->base, HCTL,
615 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
616
617 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
618 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP
619 && time_before(jiffies, timeout))
620 ;
621
b417577d 622 omap_hsmmc_disable_irq(host);
11dd62a7
DK		 623
624 /* Do not initialize card-specific things if the power is off */
625 if (host->power_mode == MMC_POWER_OFF)
626 goto out;
627
3796fb8a 628 omap_hsmmc_set_bus_width(host);
11dd62a7 629
5934df2f 630 omap_hsmmc_set_clock(host);
11dd62a7 631
3796fb8a
AS		 632 omap_hsmmc_set_bus_mode(host);
633
11dd62a7
DK		 634out:
635 host->context_loss = context_loss;
636
637 dev_dbg(mmc_dev(host->mmc), "context is restored\n");
638 return 0;
639}
640
641/*
642 * Save the MMC host context (store the number of power state changes so far).
643 */
70a3341a 644static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 645{
646 struct omap_mmc_platform_data *pdata = host->pdata;
647 int context_loss;
648
649 if (pdata->get_context_loss_count) {
650 context_loss = pdata->get_context_loss_count(host->dev);
651 if (context_loss < 0)
652 return;
653 host->context_loss = context_loss;
654 }
655}
656
657#else
658
70a3341a 659static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host)
11dd62a7
DK		 660{
661 return 0;
662}
663
70a3341a 664static void omap_hsmmc_context_save(struct omap_hsmmc_host *host)
11dd62a7
DK		 665{
666}
667
668#endif
669
a45c6cb8
MC		 670/*
671 * Send init stream sequence to card
672 * before sending IDLE command
673 */
70a3341a 674static void send_init_stream(struct omap_hsmmc_host *host)
a45c6cb8
MC		 675{
676 int reg = 0;
677 unsigned long timeout;
678
b62f6228
AH		 679 if (host->protect_card)
680 return;
681
a45c6cb8 682 disable_irq(host->irq);
b417577d
AH		 683
684 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK);
a45c6cb8
MC		 685 OMAP_HSMMC_WRITE(host->base, CON,
686 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM);
687 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD);
688
689 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS);
690 while ((reg != CC) && time_before(jiffies, timeout))
691 reg = OMAP_HSMMC_READ(host->base, STAT) & CC;
692
693 OMAP_HSMMC_WRITE(host->base, CON,
694 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM);
c653a6d4
AH		 695
696 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR);
697 OMAP_HSMMC_READ(host->base, STAT);
698
a45c6cb8
MC		 699 enable_irq(host->irq);
700}
701
702static inline
70a3341a 703int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host)
a45c6cb8
MC		 704{
705 int r = 1;
706
191d1f1d
DK		 707 if (mmc_slot(host).get_cover_state)
708 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id);
a45c6cb8
MC		 709 return r;
710}
711
712static ssize_t
70a3341a 713omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 714 char *buf)
715{
716 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 717 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 718
70a3341a
DK		 719 return sprintf(buf, "%s\n",
720 omap_hsmmc_cover_is_closed(host) ? "closed" : "open");
a45c6cb8
MC		 721}
722
70a3341a 723static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL);
a45c6cb8
MC		 724
725static ssize_t
70a3341a 726omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr,
a45c6cb8
MC		 727 char *buf)
728{
729 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev);
70a3341a 730 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 731
191d1f1d 732 return sprintf(buf, "%s\n", mmc_slot(host).name);
a45c6cb8
MC		 733}
734
70a3341a 735static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL);
a45c6cb8
MC		 736
737/*
738 * Configure the response type and send the cmd.
739 */
740static void
70a3341a 741omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd,
a45c6cb8
MC		 742 struct mmc_data *data)
743{
744 int cmdreg = 0, resptype = 0, cmdtype = 0;
745
746 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n",
747 mmc_hostname(host->mmc), cmd->opcode, cmd->arg);
748 host->cmd = cmd;
749
93caf8e6 750 omap_hsmmc_enable_irq(host, cmd);
a45c6cb8 751
4a694dc9 752 host->response_busy = 0;
a45c6cb8
MC		 753 if (cmd->flags & MMC_RSP_PRESENT) {
754 if (cmd->flags & MMC_RSP_136)
755 resptype = 1;
4a694dc9
AH		 756 else if (cmd->flags & MMC_RSP_BUSY) {
757 resptype = 3;
758 host->response_busy = 1;
759 } else
a45c6cb8
MC		 760 resptype = 2;
761 }
762
763 /*
764 * Unlike OMAP1 controller, the cmdtype does not seem to be based on
765 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need
766 * a val of 0x3, rest 0x0.
767 */
768 if (cmd == host->mrq->stop)
769 cmdtype = 0x3;
770
771 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22);
dba3c29e
B		 772 if ((host->flags & AUTO_CMD12) && mmc_op_multi(cmd->opcode))
773 cmdreg |= ACEN_ACMD12;
a45c6cb8
MC		 774
775 if (data) {
776 cmdreg |= DP_SELECT | MSBS | BCE;
777 if (data->flags & MMC_DATA_READ)
778 cmdreg |= DDIR;
779 else
780 cmdreg &= ~(DDIR);
781 }
782
783 if (host->use_dma)
784 cmdreg |= DMA_EN;
785
b417577d 786 host->req_in_progress = 1;
4dffd7a2 787
a45c6cb8
MC		 788 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg);
789 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg);
790}
791
0ccd76d4 792static int
70a3341a 793omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data)
0ccd76d4
JY		 794{
795 if (data->flags & MMC_DATA_WRITE)
796 return DMA_TO_DEVICE;
797 else
798 return DMA_FROM_DEVICE;
799}
800
b417577d
AH		 801static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq)
802{
803 int dma_ch;
804
805 spin_lock(&host->irq_lock);
806 host->req_in_progress = 0;
807 dma_ch = host->dma_ch;
808 spin_unlock(&host->irq_lock);
809
810 omap_hsmmc_disable_irq(host);
811 /* Do not complete the request if DMA is still in progress */
812 if (mrq->data && host->use_dma && dma_ch != -1)
813 return;
814 host->mrq = NULL;
815 mmc_request_done(host->mmc, mrq);
816}
817
a45c6cb8
MC		 818/*
819 * Notify the transfer complete to MMC core
820 */
821static void
70a3341a 822omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data)
a45c6cb8 823{
4a694dc9
AH		 824 if (!data) {
825 struct mmc_request *mrq = host->mrq;
826
23050103
AH		 827 /* TC before CC from CMD6 - don't know why, but it happens */
828 if (host->cmd && host->cmd->opcode == 6 &&
829 host->response_busy) {
830 host->response_busy = 0;
831 return;
832 }
833
b417577d 834 omap_hsmmc_request_done(host, mrq);
4a694dc9
AH		 835 return;
836 }
837
a45c6cb8
MC		 838 host->data = NULL;
839
a45c6cb8
MC		 840 if (!data->error)
841 data->bytes_xfered += data->blocks * (data->blksz);
842 else
843 data->bytes_xfered = 0;
844
dba3c29e
B		 845 if (data->stop && ((!(host->flags & AUTO_CMD12)) || data->error)) {
846 omap_hsmmc_start_command(host, data->stop, NULL);
847 } else {
848 if (data->stop)
849 data->stop->resp[0] = OMAP_HSMMC_READ(host->base,
850 RSP76);
b417577d 851 omap_hsmmc_request_done(host, data->mrq);
a45c6cb8 852 }
a45c6cb8
MC		 853}
854
855/*
856 * Notify the core about command completion
857 */
858static void
70a3341a 859omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd)
a45c6cb8
MC		 860{
861 host->cmd = NULL;
862
863 if (cmd->flags & MMC_RSP_PRESENT) {
864 if (cmd->flags & MMC_RSP_136) {
865 /* response type 2 */
866 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10);
867 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32);
868 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54);
869 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76);
870 } else {
871 /* response types 1, 1b, 3, 4, 5, 6 */
872 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10);
873 }
874 }
b417577d
AH		 875 if ((host->data == NULL && !host->response_busy) || cmd->error)
876 omap_hsmmc_request_done(host, cmd->mrq);
a45c6cb8
MC		 877}
878
879/*
880 * DMA clean up for command errors
881 */
70a3341a 882static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno)
a45c6cb8 883{
b417577d
AH		 884 int dma_ch;
885
82788ff5 886 host->data->error = errno;
a45c6cb8 887
b417577d
AH		 888 spin_lock(&host->irq_lock);
889 dma_ch = host->dma_ch;
890 host->dma_ch = -1;
891 spin_unlock(&host->irq_lock);
892
893 if (host->use_dma && dma_ch != -1) {
a9120c33
PF		 894 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg,
895 host->data->sg_len,
70a3341a 896 omap_hsmmc_get_dma_dir(host, host->data));
b417577d 897 omap_free_dma(dma_ch);
053bf34f 898 host->data->host_cookie = 0;
a45c6cb8
MC		 899 }
900 host->data = NULL;
a45c6cb8
MC		 901}
902
903/*
904 * Readable error output
905 */
906#ifdef CONFIG_MMC_DEBUG
699b958b 907static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status)
a45c6cb8
MC		 908{
909 /* --- means reserved bit without definition at documentation */
70a3341a 910 static const char *omap_hsmmc_status_bits[] = {
699b958b
AH		 911 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" ,
912 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI",
913 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" ,
914 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---"
a45c6cb8
MC		 915 };
916 char res[256];
917 char *buf = res;
918 int len, i;
919
920 len = sprintf(buf, "MMC IRQ 0x%x :", status);
921 buf += len;
922
70a3341a 923 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++)
a45c6cb8 924 if (status & (1 << i)) {
70a3341a 925 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]);
a45c6cb8
MC		 926 buf += len;
927 }
928
929 dev_dbg(mmc_dev(host->mmc), "%s\n", res);
930}
699b958b
AH		 931#else
932static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host,
933 u32 status)
934{
935}
a45c6cb8
MC		 936#endif /* CONFIG_MMC_DEBUG */
937
3ebf74b1
JP		 938/*
939 * MMC controller internal state machines reset
940 *
941 * Used to reset command or data internal state machines, using respectively
942 * SRC or SRD bit of SYSCTL register
943 * Can be called from interrupt context
944 */
70a3341a
DK		 945static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host,
946 unsigned long bit)
3ebf74b1
JP		 947{
948 unsigned long i = 0;
949 unsigned long limit = (loops_per_jiffy *
950 msecs_to_jiffies(MMC_TIMEOUT_MS));
951
952 OMAP_HSMMC_WRITE(host->base, SYSCTL,
953 OMAP_HSMMC_READ(host->base, SYSCTL) | bit);
954
07ad64b6
MC		 955 /*
956 * OMAP4 ES2 and greater has an updated reset logic.
957 * Monitor a 0->1 transition first
958 */
959 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) {
b432b4b3 960 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit))
07ad64b6
MC		 961 && (i++ < limit))
962 cpu_relax();
963 }
964 i = 0;
965
3ebf74b1
JP		 966 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) &&
967 (i++ < limit))
968 cpu_relax();
969
970 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit)
971 dev_err(mmc_dev(host->mmc),
972 "Timeout waiting on controller reset in %s\n",
973 __func__);
974}
a45c6cb8 975
b417577d 976static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status)
a45c6cb8 977{
a45c6cb8 978 struct mmc_data *data;
b417577d
AH		 979 int end_cmd = 0, end_trans = 0;
980
981 if (!host->req_in_progress) {
982 do {
983 OMAP_HSMMC_WRITE(host->base, STAT, status);
984 /* Flush posted write */
985 status = OMAP_HSMMC_READ(host->base, STAT);
986 } while (status & INT_EN_MASK);
987 return;
a45c6cb8
MC		 988 }
989
990 data = host->data;
a45c6cb8
MC		 991 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status);
992
993 if (status & ERR) {
699b958b 994 omap_hsmmc_dbg_report_irq(host, status);
a45c6cb8
MC		 995 if ((status & CMD_TIMEOUT) ||
996 (status & CMD_CRC)) {
997 if (host->cmd) {
998 if (status & CMD_TIMEOUT) {
70a3341a
DK		 999 omap_hsmmc_reset_controller_fsm(host,
1000 SRC);
a45c6cb8
MC		 1001 host->cmd->error = -ETIMEDOUT;
1002 } else {
1003 host->cmd->error = -EILSEQ;
1004 }
1005 end_cmd = 1;
1006 }
4a694dc9
AH		 1007 if (host->data || host->response_busy) {
1008 if (host->data)
70a3341a
DK		 1009 omap_hsmmc_dma_cleanup(host,
1010 -ETIMEDOUT);
4a694dc9 1011 host->response_busy = 0;
70a3341a 1012 omap_hsmmc_reset_controller_fsm(host, SRD);
c232f457 1013 }
a45c6cb8
MC		 1014 }
1015 if ((status & DATA_TIMEOUT) ||
1016 (status & DATA_CRC)) {
4a694dc9
AH		 1017 if (host->data || host->response_busy) {
1018 int err = (status & DATA_TIMEOUT) ?
1019 -ETIMEDOUT : -EILSEQ;
1020
1021 if (host->data)
70a3341a 1022 omap_hsmmc_dma_cleanup(host, err);
a45c6cb8 1023 else
4a694dc9
AH		 1024 host->mrq->cmd->error = err;
1025 host->response_busy = 0;
70a3341a 1026 omap_hsmmc_reset_controller_fsm(host, SRD);
a45c6cb8
MC		 1027 end_trans = 1;
1028 }
1029 }
1030 if (status & CARD_ERR) {
1031 dev_dbg(mmc_dev(host->mmc),
1032 "Ignoring card err CMD%d\n", host->cmd->opcode);
1033 if (host->cmd)
1034 end_cmd = 1;
1035 if (host->data)
1036 end_trans = 1;
1037 }
1038 }
1039
1040 OMAP_HSMMC_WRITE(host->base, STAT, status);
1041
a8fe29d8 1042 if (end_cmd || ((status & CC) && host->cmd))
70a3341a 1043 omap_hsmmc_cmd_done(host, host->cmd);
0a40e647 1044 if ((end_trans || (status & TC)) && host->mrq)
70a3341a 1045 omap_hsmmc_xfer_done(host, data);
b417577d 1046}
a45c6cb8 1047
b417577d
AH		 1048/*
1049 * MMC controller IRQ handler
1050 */
1051static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id)
1052{
1053 struct omap_hsmmc_host *host = dev_id;
1054 int status;
1055
1056 status = OMAP_HSMMC_READ(host->base, STAT);
1057 do {
1058 omap_hsmmc_do_irq(host, status);
1059 /* Flush posted write */
1060 status = OMAP_HSMMC_READ(host->base, STAT);
1061 } while (status & INT_EN_MASK);
4dffd7a2 1062
a45c6cb8
MC		 1063 return IRQ_HANDLED;
1064}
1065
70a3341a 1066static void set_sd_bus_power(struct omap_hsmmc_host *host)
e13bb300
AH		 1067{
1068 unsigned long i;
1069
1070 OMAP_HSMMC_WRITE(host->base, HCTL,
1071 OMAP_HSMMC_READ(host->base, HCTL) | SDBP);
1072 for (i = 0; i < loops_per_jiffy; i++) {
1073 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP)
1074 break;
1075 cpu_relax();
1076 }
1077}
1078
a45c6cb8 1079/*
eb250826
DB		 1080 * Switch MMC interface voltage ... only relevant for MMC1.
1081 *
1082 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver.
1083 * The MMC2 transceiver controls are used instead of DAT4..DAT7.
1084 * Some chips, like eMMC ones, use internal transceivers.
a45c6cb8 1085 */
70a3341a 1086static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd)
a45c6cb8
MC		 1087{
1088 u32 reg_val = 0;
1089 int ret;
1090
1091 /* Disable the clocks */
fa4aa2d4 1092 pm_runtime_put_sync(host->dev);
2bec0893
AH		 1093 if (host->got_dbclk)
1094 clk_disable(host->dbclk);
a45c6cb8
MC		 1095
1096 /* Turn the power off */
1097 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0);
a45c6cb8
MC		 1098
1099 /* Turn the power ON with given VDD 1.8 or 3.0v */
2bec0893
AH		 1100 if (!ret)
1101 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1,
1102 vdd);
fa4aa2d4 1103 pm_runtime_get_sync(host->dev);
2bec0893
AH		 1104 if (host->got_dbclk)
1105 clk_enable(host->dbclk);
1106
a45c6cb8
MC		 1107 if (ret != 0)
1108 goto err;
1109
a45c6cb8
MC		 1110 OMAP_HSMMC_WRITE(host->base, HCTL,
1111 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR);
1112 reg_val = OMAP_HSMMC_READ(host->base, HCTL);
eb250826 1113
a45c6cb8
MC		 1114 /*
1115 * If a MMC dual voltage card is detected, the set_ios fn calls
1116 * this fn with VDD bit set for 1.8V. Upon card removal from the
70a3341a 1117 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF.
a45c6cb8 1118 *
eb250826
DB		 1119 * Cope with a bit of slop in the range ... per data sheets:
1120 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max,
1121 * but recommended values are 1.71V to 1.89V
1122 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max,
1123 * but recommended values are 2.7V to 3.3V
1124 *
1125 * Board setup code shouldn't permit anything very out-of-range.
1126 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the
1127 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V.
a45c6cb8 1128 */
eb250826 1129 if ((1 << vdd) <= MMC_VDD_23_24)
a45c6cb8 1130 reg_val |= SDVS18;
eb250826
DB		 1131 else
1132 reg_val |= SDVS30;
a45c6cb8
MC		 1133
1134 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val);
e13bb300 1135 set_sd_bus_power(host);
a45c6cb8
MC		 1136
1137 return 0;
1138err:
1139 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n");
1140 return ret;
1141}
1142
b62f6228
AH		 1143/* Protect the card while the cover is open */
1144static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host)
1145{
1146 if (!mmc_slot(host).get_cover_state)
1147 return;
1148
1149 host->reqs_blocked = 0;
1150 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) {
1151 if (host->protect_card) {
2cecdf00 1152 dev_info(host->dev, "%s: cover is closed, "
b62f6228
AH		 1153 "card is now accessible\n",
1154 mmc_hostname(host->mmc));
1155 host->protect_card = 0;
1156 }
1157 } else {
1158 if (!host->protect_card) {
2cecdf00 1159 dev_info(host->dev, "%s: cover is open, "
b62f6228
AH		 1160 "card is now inaccessible\n",
1161 mmc_hostname(host->mmc));
1162 host->protect_card = 1;
1163 }
1164 }
1165}
1166
a45c6cb8 1167/*
7efab4f3 1168 * irq handler to notify the core about card insertion/removal
a45c6cb8 1169 */
7efab4f3 1170static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id)
a45c6cb8 1171{
7efab4f3 1172 struct omap_hsmmc_host *host = dev_id;
249d0fa9 1173 struct omap_mmc_slot_data *slot = &mmc_slot(host);
a6b2240d
AH		 1174 int carddetect;
1175
1176 if (host->suspended)
7efab4f3 1177 return IRQ_HANDLED;
a6b2240d
AH		 1178
1179 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch");
249d0fa9 1180
191d1f1d 1181 if (slot->card_detect)
db0fefc5 1182 carddetect = slot->card_detect(host->dev, host->slot_id);
b62f6228
AH		 1183 else {
1184 omap_hsmmc_protect_card(host);
a6b2240d 1185 carddetect = -ENOSYS;
b62f6228 1186 }
a45c6cb8 1187
cdeebadd 1188 if (carddetect)
a45c6cb8 1189 mmc_detect_change(host->mmc, (HZ * 200) / 1000);
cdeebadd 1190 else
a45c6cb8 1191 mmc_detect_change(host->mmc, (HZ * 50) / 1000);
a45c6cb8
MC		 1192 return IRQ_HANDLED;
1193}
1194
70a3341a 1195static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1196 struct mmc_data *data)
1197{
1198 int sync_dev;
1199
f3e2f1dd
GI		 1200 if (data->flags & MMC_DATA_WRITE)
1201 sync_dev = host->dma_line_tx;
1202 else
1203 sync_dev = host->dma_line_rx;
0ccd76d4
JY		 1204 return sync_dev;
1205}
1206
70a3341a 1207static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host,
0ccd76d4
JY		 1208 struct mmc_data *data,
1209 struct scatterlist *sgl)
1210{
1211 int blksz, nblk, dma_ch;
1212
1213 dma_ch = host->dma_ch;
1214 if (data->flags & MMC_DATA_WRITE) {
1215 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
1216 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
1217 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1218 sg_dma_address(sgl), 0, 0);
1219 } else {
1220 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT,
191d1f1d 1221 (host->mapbase + OMAP_HSMMC_DATA), 0, 0);
0ccd76d4
JY		 1222 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC,
1223 sg_dma_address(sgl), 0, 0);
1224 }
1225
1226 blksz = host->data->blksz;
1227 nblk = sg_dma_len(sgl) / blksz;
1228
1229 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32,
1230 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME,
70a3341a 1231 omap_hsmmc_get_dma_sync_dev(host, data),
0ccd76d4
JY		 1232 !(data->flags & MMC_DATA_WRITE));
1233
1234 omap_start_dma(dma_ch);
1235}
1236
a45c6cb8
MC		 1237/*
1238 * DMA call back function
1239 */
b417577d 1240static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data)
a45c6cb8 1241{
b417577d 1242 struct omap_hsmmc_host *host = cb_data;
770d7432 1243 struct mmc_data *data;
b417577d 1244 int dma_ch, req_in_progress;
a45c6cb8 1245
f3584e5e
V		 1246 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) {
1247 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n",
1248 ch_status);
1249 return;
1250 }
a45c6cb8 1251
b417577d
AH		 1252 spin_lock(&host->irq_lock);
1253 if (host->dma_ch < 0) {
1254 spin_unlock(&host->irq_lock);
a45c6cb8 1255 return;
b417577d 1256 }
a45c6cb8 1257
770d7432 1258 data = host->mrq->data;
0ccd76d4
JY		 1259 host->dma_sg_idx++;
1260 if (host->dma_sg_idx < host->dma_len) {
1261 /* Fire up the next transfer. */
b417577d
AH		 1262 omap_hsmmc_config_dma_params(host, data,
1263 data->sg + host->dma_sg_idx);
1264 spin_unlock(&host->irq_lock);
0ccd76d4
JY		 1265 return;
1266 }
1267
9782aff8
PF		 1268 if (!data->host_cookie)
1269 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
1270 omap_hsmmc_get_dma_dir(host, data));
b417577d
AH		 1271
1272 req_in_progress = host->req_in_progress;
1273 dma_ch = host->dma_ch;
a45c6cb8 1274 host->dma_ch = -1;
b417577d
AH		 1275 spin_unlock(&host->irq_lock);
1276
1277 omap_free_dma(dma_ch);
1278
1279 /* If DMA has finished after TC, complete the request */
1280 if (!req_in_progress) {
1281 struct mmc_request *mrq = host->mrq;
1282
1283 host->mrq = NULL;
1284 mmc_request_done(host->mmc, mrq);
1285 }
a45c6cb8
MC		 1286}
1287
9782aff8
PF		 1288static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host,
1289 struct mmc_data *data,
1290 struct omap_hsmmc_next *next)
1291{
1292 int dma_len;
1293
1294 if (!next && data->host_cookie &&
1295 data->host_cookie != host->next_data.cookie) {
2cecdf00 1296 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d"
9782aff8
PF		 1297 " host->next_data.cookie %d\n",
1298 __func__, data->host_cookie, host->next_data.cookie);
1299 data->host_cookie = 0;
1300 }
1301
1302 /* Check if next job is already prepared */
1303 if (next ||
1304 (!next && data->host_cookie != host->next_data.cookie)) {
1305 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg,
1306 data->sg_len,
1307 omap_hsmmc_get_dma_dir(host, data));
1308
1309 } else {
1310 dma_len = host->next_data.dma_len;
1311 host->next_data.dma_len = 0;
1312 }
1313
1314
1315 if (dma_len == 0)
1316 return -EINVAL;
1317
1318 if (next) {
1319 next->dma_len = dma_len;
1320 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie;
1321 } else
1322 host->dma_len = dma_len;
1323
1324 return 0;
1325}
1326
a45c6cb8
MC		 1327/*
1328 * Routine to configure and start DMA for the MMC card
1329 */
70a3341a
DK		 1330static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host,
1331 struct mmc_request *req)
a45c6cb8 1332{
b417577d 1333 int dma_ch = 0, ret = 0, i;
a45c6cb8
MC		 1334 struct mmc_data *data = req->data;
1335
0ccd76d4 1336 /* Sanity check: all the SG entries must be aligned by block size. */
a3f406f8 1337 for (i = 0; i < data->sg_len; i++) {
0ccd76d4
JY		 1338 struct scatterlist *sgl;
1339
1340 sgl = data->sg + i;
1341 if (sgl->length % data->blksz)
1342 return -EINVAL;
1343 }
1344 if ((data->blksz % 4) != 0)
1345 /* REVISIT: The MMC buffer increments only when MSB is written.
1346 * Return error for blksz which is non multiple of four.
1347 */
1348 return -EINVAL;
1349
b417577d 1350 BUG_ON(host->dma_ch != -1);
a45c6cb8 1351
70a3341a
DK		 1352 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data),
1353 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch);
a45c6cb8 1354 if (ret != 0) {
0ccd76d4 1355 dev_err(mmc_dev(host->mmc),
a45c6cb8
MC		 1356 "%s: omap_request_dma() failed with %d\n",
1357 mmc_hostname(host->mmc), ret);
1358 return ret;
1359 }
9782aff8
PF		 1360 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL);
1361 if (ret)
1362 return ret;
a45c6cb8 1363
a45c6cb8 1364 host->dma_ch = dma_ch;
0ccd76d4 1365 host->dma_sg_idx = 0;
a45c6cb8 1366
70a3341a 1367 omap_hsmmc_config_dma_params(host, data, data->sg);
a45c6cb8 1368
a45c6cb8
MC		 1369 return 0;
1370}
1371
70a3341a 1372static void set_data_timeout(struct omap_hsmmc_host *host,
e2bf08d6
AH		 1373 unsigned int timeout_ns,
1374 unsigned int timeout_clks)
a45c6cb8
MC		 1375{
1376 unsigned int timeout, cycle_ns;
1377 uint32_t reg, clkd, dto = 0;
1378
1379 reg = OMAP_HSMMC_READ(host->base, SYSCTL);
1380 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT;
1381 if (clkd == 0)
1382 clkd = 1;
1383
1384 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd);
e2bf08d6
AH		 1385 timeout = timeout_ns / cycle_ns;
1386 timeout += timeout_clks;
a45c6cb8
MC		 1387 if (timeout) {
1388 while ((timeout & 0x80000000) == 0) {
1389 dto += 1;
1390 timeout <<= 1;
1391 }
1392 dto = 31 - dto;
1393 timeout <<= 1;
1394 if (timeout && dto)
1395 dto += 1;
1396 if (dto >= 13)
1397 dto -= 13;
1398 else
1399 dto = 0;
1400 if (dto > 14)
1401 dto = 14;
1402 }
1403
1404 reg &= ~DTO_MASK;
1405 reg |= dto << DTO_SHIFT;
1406 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg);
1407}
1408
1409/*
1410 * Configure block length for MMC/SD cards and initiate the transfer.
1411 */
1412static int
70a3341a 1413omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req)
a45c6cb8
MC		 1414{
1415 int ret;
1416 host->data = req->data;
1417
1418 if (req->data == NULL) {
a45c6cb8 1419 OMAP_HSMMC_WRITE(host->base, BLK, 0);
e2bf08d6
AH		 1420 /*
1421 * Set an arbitrary 100ms data timeout for commands with
1422 * busy signal.
1423 */
1424 if (req->cmd->flags & MMC_RSP_BUSY)
1425 set_data_timeout(host, 100000000U, 0);
a45c6cb8
MC		 1426 return 0;
1427 }
1428
1429 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz)
1430 | (req->data->blocks << 16));
e2bf08d6 1431 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks);
a45c6cb8 1432
a45c6cb8 1433 if (host->use_dma) {
70a3341a 1434 ret = omap_hsmmc_start_dma_transfer(host, req);
a45c6cb8
MC		 1435 if (ret != 0) {
1436 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n");
1437 return ret;
1438 }
1439 }
1440 return 0;
1441}
1442
9782aff8
PF		 1443static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1444 int err)
1445{
1446 struct omap_hsmmc_host *host = mmc_priv(mmc);
1447 struct mmc_data *data = mrq->data;
1448
1449 if (host->use_dma) {
053bf34f
PF		 1450 if (data->host_cookie)
1451 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
1452 data->sg_len,
1453 omap_hsmmc_get_dma_dir(host, data));
9782aff8
PF		 1454 data->host_cookie = 0;
1455 }
1456}
1457
1458static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq,
1459 bool is_first_req)
1460{
1461 struct omap_hsmmc_host *host = mmc_priv(mmc);
1462
1463 if (mrq->data->host_cookie) {
1464 mrq->data->host_cookie = 0;
1465 return ;
1466 }
1467
1468 if (host->use_dma)
1469 if (omap_hsmmc_pre_dma_transfer(host, mrq->data,
1470 &host->next_data))
1471 mrq->data->host_cookie = 0;
1472}
1473
a45c6cb8
MC		 1474/*
1475 * Request function. for read/write operation
1476 */
70a3341a 1477static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req)
a45c6cb8 1478{
70a3341a 1479 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3f406f8 1480 int err;
a45c6cb8 1481
b417577d
AH		 1482 BUG_ON(host->req_in_progress);
1483 BUG_ON(host->dma_ch != -1);
1484 if (host->protect_card) {
1485 if (host->reqs_blocked < 3) {
1486 /*
1487 * Ensure the controller is left in a consistent
1488 * state by resetting the command and data state
1489 * machines.
1490 */
1491 omap_hsmmc_reset_controller_fsm(host, SRD);
1492 omap_hsmmc_reset_controller_fsm(host, SRC);
1493 host->reqs_blocked += 1;
1494 }
1495 req->cmd->error = -EBADF;
1496 if (req->data)
1497 req->data->error = -EBADF;
1498 req->cmd->retries = 0;
1499 mmc_request_done(mmc, req);
1500 return;
1501 } else if (host->reqs_blocked)
1502 host->reqs_blocked = 0;
a45c6cb8
MC		 1503 WARN_ON(host->mrq != NULL);
1504 host->mrq = req;
70a3341a 1505 err = omap_hsmmc_prepare_data(host, req);
a3f406f8
JL		 1506 if (err) {
1507 req->cmd->error = err;
1508 if (req->data)
1509 req->data->error = err;
1510 host->mrq = NULL;
1511 mmc_request_done(mmc, req);
1512 return;
1513 }
1514
70a3341a 1515 omap_hsmmc_start_command(host, req->cmd, req->data);
a45c6cb8
MC		 1516}
1517
a45c6cb8 1518/* Routine to configure clock values. Exposed API to core */
70a3341a 1519static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
a45c6cb8 1520{
70a3341a 1521 struct omap_hsmmc_host *host = mmc_priv(mmc);
a3621465 1522 int do_send_init_stream = 0;
a45c6cb8 1523
fa4aa2d4 1524 pm_runtime_get_sync(host->dev);
5e2ea617 1525
a3621465
AH		 1526 if (ios->power_mode != host->power_mode) {
1527 switch (ios->power_mode) {
1528 case MMC_POWER_OFF:
1529 mmc_slot(host).set_power(host->dev, host->slot_id,
1530 0, 0);
623821f7 1531 host->vdd = 0;
a3621465
AH		 1532 break;
1533 case MMC_POWER_UP:
1534 mmc_slot(host).set_power(host->dev, host->slot_id,
1535 1, ios->vdd);
623821f7 1536 host->vdd = ios->vdd;
a3621465
AH		 1537 break;
1538 case MMC_POWER_ON:
1539 do_send_init_stream = 1;
1540 break;
1541 }
1542 host->power_mode = ios->power_mode;
a45c6cb8
MC		 1543 }
1544
dd498eff
DK		 1545 /* FIXME: set registers based only on changes to ios */
1546
3796fb8a 1547 omap_hsmmc_set_bus_width(host);
a45c6cb8 1548
4621d5f8 1549 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
eb250826
DB		 1550 /* Only MMC1 can interface at 3V without some flavor
1551 * of external transceiver; but they all handle 1.8V.
1552 */
a45c6cb8 1553 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) &&
1f84b71b
RN		 1554 (ios->vdd == DUAL_VOLT_OCR_BIT) &&
1555 /*
1556 * With pbias cell programming missing, this
1557 * can't be allowed when booting with device
1558 * tree.
1559 */
4d048f91 1560 !host->dev->of_node) {
a45c6cb8
MC		 1561 /*
1562 * The mmc_select_voltage fn of the core does
1563 * not seem to set the power_mode to
1564 * MMC_POWER_UP upon recalculating the voltage.
1565 * vdd 1.8v.
1566 */
70a3341a
DK		 1567 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0)
1568 dev_dbg(mmc_dev(host->mmc),
a45c6cb8
MC		 1569 "Switch operation failed\n");
1570 }
1571 }
1572
5934df2f 1573 omap_hsmmc_set_clock(host);
a45c6cb8 1574
a3621465 1575 if (do_send_init_stream)
a45c6cb8
MC		 1576 send_init_stream(host);
1577
3796fb8a 1578 omap_hsmmc_set_bus_mode(host);
5e2ea617 1579
fa4aa2d4 1580 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 1581}
1582
1583static int omap_hsmmc_get_cd(struct mmc_host *mmc)
1584{
70a3341a 1585 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1586
191d1f1d 1587 if (!mmc_slot(host).card_detect)
a45c6cb8 1588 return -ENOSYS;
db0fefc5 1589 return mmc_slot(host).card_detect(host->dev, host->slot_id);
a45c6cb8
MC		 1590}
1591
1592static int omap_hsmmc_get_ro(struct mmc_host *mmc)
1593{
70a3341a 1594 struct omap_hsmmc_host *host = mmc_priv(mmc);
a45c6cb8 1595
191d1f1d 1596 if (!mmc_slot(host).get_ro)
a45c6cb8 1597 return -ENOSYS;
191d1f1d 1598 return mmc_slot(host).get_ro(host->dev, 0);
a45c6cb8
MC		 1599}
1600
4816858c
GI		 1601static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card)
1602{
1603 struct omap_hsmmc_host *host = mmc_priv(mmc);
1604
1605 if (mmc_slot(host).init_card)
1606 mmc_slot(host).init_card(card);
1607}
1608
70a3341a 1609static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host)
1b331e69
KK		 1610{
1611 u32 hctl, capa, value;
1612
1613 /* Only MMC1 supports 3.0V */
4621d5f8 1614 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) {
1b331e69
KK		 1615 hctl = SDVS30;
1616 capa = VS30 | VS18;
1617 } else {
1618 hctl = SDVS18;
1619 capa = VS18;
1620 }
1621
1622 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK;
1623 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl);
1624
1625 value = OMAP_HSMMC_READ(host->base, CAPA);
1626 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa);
1627
1628 /* Set the controller to AUTO IDLE mode */
1629 value = OMAP_HSMMC_READ(host->base, SYSCONFIG);
1630 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE);
1631
1632 /* Set SD bus power bit */
e13bb300 1633 set_sd_bus_power(host);
1b331e69
KK		 1634}
1635
70a3341a 1636static int omap_hsmmc_enable_fclk(struct mmc_host *mmc)
dd498eff 1637{
70a3341a 1638 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1639
fa4aa2d4
B		 1640 pm_runtime_get_sync(host->dev);
1641
dd498eff
DK		 1642 return 0;
1643}
1644
907d2e7c 1645static int omap_hsmmc_disable_fclk(struct mmc_host *mmc)
dd498eff 1646{
70a3341a 1647 struct omap_hsmmc_host *host = mmc_priv(mmc);
dd498eff 1648
fa4aa2d4
B		 1649 pm_runtime_mark_last_busy(host->dev);
1650 pm_runtime_put_autosuspend(host->dev);
1651
dd498eff
DK		 1652 return 0;
1653}
1654
70a3341a
DK		 1655static const struct mmc_host_ops omap_hsmmc_ops = {
1656 .enable = omap_hsmmc_enable_fclk,
1657 .disable = omap_hsmmc_disable_fclk,
9782aff8
PF		 1658 .post_req = omap_hsmmc_post_req,
1659 .pre_req = omap_hsmmc_pre_req,
70a3341a
DK		 1660 .request = omap_hsmmc_request,
1661 .set_ios = omap_hsmmc_set_ios,
dd498eff
DK		 1662 .get_cd = omap_hsmmc_get_cd,
1663 .get_ro = omap_hsmmc_get_ro,
4816858c 1664 .init_card = omap_hsmmc_init_card,
dd498eff
DK		 1665 /* NYET -- enable_sdio_irq */
1666};
1667
d900f712
DK		 1668#ifdef CONFIG_DEBUG_FS
1669
70a3341a 1670static int omap_hsmmc_regs_show(struct seq_file *s, void *data)
d900f712
DK		 1671{
1672 struct mmc_host *mmc = s->private;
70a3341a 1673 struct omap_hsmmc_host *host = mmc_priv(mmc);
11dd62a7
DK		 1674 int context_loss = 0;
1675
70a3341a
DK		 1676 if (host->pdata->get_context_loss_count)
1677 context_loss = host->pdata->get_context_loss_count(host->dev);
d900f712 1678
907d2e7c
AH		 1679 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n",
1680 mmc->index, host->context_loss, context_loss);
5e2ea617 1681
7a8c2cef 1682 if (host->suspended) {
dd498eff
DK		 1683 seq_printf(s, "host suspended, can't read registers\n");
1684 return 0;
1685 }
1686
fa4aa2d4 1687 pm_runtime_get_sync(host->dev);
d900f712
DK		 1688
1689 seq_printf(s, "SYSCONFIG:\t0x%08x\n",
1690 OMAP_HSMMC_READ(host->base, SYSCONFIG));
1691 seq_printf(s, "CON:\t\t0x%08x\n",
1692 OMAP_HSMMC_READ(host->base, CON));
1693 seq_printf(s, "HCTL:\t\t0x%08x\n",
1694 OMAP_HSMMC_READ(host->base, HCTL));
1695 seq_printf(s, "SYSCTL:\t\t0x%08x\n",
1696 OMAP_HSMMC_READ(host->base, SYSCTL));
1697 seq_printf(s, "IE:\t\t0x%08x\n",
1698 OMAP_HSMMC_READ(host->base, IE));
1699 seq_printf(s, "ISE:\t\t0x%08x\n",
1700 OMAP_HSMMC_READ(host->base, ISE));
1701 seq_printf(s, "CAPA:\t\t0x%08x\n",
1702 OMAP_HSMMC_READ(host->base, CAPA));
5e2ea617 1703
fa4aa2d4
B		 1704 pm_runtime_mark_last_busy(host->dev);
1705 pm_runtime_put_autosuspend(host->dev);
dd498eff 1706
d900f712
DK		 1707 return 0;
1708}
1709
70a3341a 1710static int omap_hsmmc_regs_open(struct inode *inode, struct file *file)
d900f712 1711{
70a3341a 1712 return single_open(file, omap_hsmmc_regs_show, inode->i_private);
d900f712
DK		 1713}
1714
1715static const struct file_operations mmc_regs_fops = {
70a3341a 1716 .open = omap_hsmmc_regs_open,
d900f712
DK		 1717 .read = seq_read,
1718 .llseek = seq_lseek,
1719 .release = single_release,
1720};
1721
70a3341a 1722static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1723{
1724 if (mmc->debugfs_root)
1725 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root,
1726 mmc, &mmc_regs_fops);
1727}
1728
1729#else
1730
70a3341a 1731static void omap_hsmmc_debugfs(struct mmc_host *mmc)
d900f712
DK		 1732{
1733}
1734
1735#endif
1736
46856a68
RN		 1737#ifdef CONFIG_OF
1738static u16 omap4_reg_offset = 0x100;
1739
1740static const struct of_device_id omap_mmc_of_match[] = {
1741 {
1742 .compatible = "ti,omap2-hsmmc",
1743 },
1744 {
1745 .compatible = "ti,omap3-hsmmc",
1746 },
1747 {
1748 .compatible = "ti,omap4-hsmmc",
1749 .data = &omap4_reg_offset,
1750 },
1751 {},
b6d085f6 1752};
46856a68
RN		 1753MODULE_DEVICE_TABLE(of, omap_mmc_of_match);
1754
1755static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev)
1756{
1757 struct omap_mmc_platform_data *pdata;
1758 struct device_node *np = dev->of_node;
1759 u32 bus_width;
1760
1761 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1762 if (!pdata)
1763 return NULL; /* out of memory */
1764
1765 if (of_find_property(np, "ti,dual-volt", NULL))
1766 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT;
1767
1768 /* This driver only supports 1 slot */
1769 pdata->nr_slots = 1;
1770 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0);
1771 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0);
1772
1773 if (of_find_property(np, "ti,non-removable", NULL)) {
1774 pdata->slots[0].nonremovable = true;
1775 pdata->slots[0].no_regulator_off_init = true;
1776 }
1777 of_property_read_u32(np, "ti,bus-width", &bus_width);
1778 if (bus_width == 4)
1779 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA;
1780 else if (bus_width == 8)
1781 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA;
1782
1783 if (of_find_property(np, "ti,needs-special-reset", NULL))
1784 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET;
1785
1786 return pdata;
1787}
1788#else
1789static inline struct omap_mmc_platform_data
1790 *of_get_hsmmc_pdata(struct device *dev)
1791{
1792 return NULL;
1793}
1794#endif
1795
efa25fd3 1796static int __devinit omap_hsmmc_probe(struct platform_device *pdev)
a45c6cb8
MC		 1797{
1798 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data;
1799 struct mmc_host *mmc;
70a3341a 1800 struct omap_hsmmc_host *host = NULL;
a45c6cb8 1801 struct resource *res;
db0fefc5 1802 int ret, irq;
46856a68
RN		 1803 const struct of_device_id *match;
1804
1805 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
1806 if (match) {
1807 pdata = of_get_hsmmc_pdata(&pdev->dev);
1808 if (match->data) {
1809 u16 *offsetp = match->data;
1810 pdata->reg_offset = *offsetp;
1811 }
1812 }
a45c6cb8
MC		 1813
1814 if (pdata == NULL) {
1815 dev_err(&pdev->dev, "Platform Data is missing\n");
1816 return -ENXIO;
1817 }
1818
1819 if (pdata->nr_slots == 0) {
1820 dev_err(&pdev->dev, "No Slots\n");
1821 return -ENXIO;
1822 }
1823
1824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1825 irq = platform_get_irq(pdev, 0);
1826 if (res == NULL || irq < 0)
1827 return -ENXIO;
1828
984b203a 1829 res = request_mem_region(res->start, resource_size(res), pdev->name);
a45c6cb8
MC		 1830 if (res == NULL)
1831 return -EBUSY;
1832
db0fefc5
AH		 1833 ret = omap_hsmmc_gpio_init(pdata);
1834 if (ret)
1835 goto err;
1836
70a3341a 1837 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev);
a45c6cb8
MC		 1838 if (!mmc) {
1839 ret = -ENOMEM;
db0fefc5 1840 goto err_alloc;
a45c6cb8
MC		 1841 }
1842
1843 host = mmc_priv(mmc);
1844 host->mmc = mmc;
1845 host->pdata = pdata;
1846 host->dev = &pdev->dev;
1847 host->use_dma = 1;
1848 host->dev->dma_mask = &pdata->dma_mask;
1849 host->dma_ch = -1;
1850 host->irq = irq;
a45c6cb8 1851 host->slot_id = 0;
fc307df8 1852 host->mapbase = res->start + pdata->reg_offset;
a45c6cb8 1853 host->base = ioremap(host->mapbase, SZ_4K);
6da20c89 1854 host->power_mode = MMC_POWER_OFF;
dba3c29e 1855 host->flags = AUTO_CMD12;
9782aff8 1856 host->next_data.cookie = 1;
a45c6cb8
MC		 1857
1858 platform_set_drvdata(pdev, host);
a45c6cb8 1859
7a8c2cef 1860 mmc->ops = &omap_hsmmc_ops;
dd498eff 1861
e0eb2424
AH		 1862 /*
1863 * If regulator_disable can only put vcc_aux to sleep then there is
1864 * no off state.
1865 */
1866 if (mmc_slot(host).vcc_aux_disable_is_sleep)
1867 mmc_slot(host).no_off = 1;
1868
d418ed87
DM		 1869 mmc->f_min = OMAP_MMC_MIN_CLOCK;
1870
1871 if (pdata->max_freq > 0)
1872 mmc->f_max = pdata->max_freq;
1873 else
1874 mmc->f_max = OMAP_MMC_MAX_CLOCK;
a45c6cb8 1875
4dffd7a2 1876 spin_lock_init(&host->irq_lock);
a45c6cb8 1877
6f7607cc 1878 host->fclk = clk_get(&pdev->dev, "fck");
a45c6cb8
MC		 1879 if (IS_ERR(host->fclk)) {
1880 ret = PTR_ERR(host->fclk);
1881 host->fclk = NULL;
a45c6cb8
MC		 1882 goto err1;
1883 }
1884
9b68256c
PW		 1885 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) {
1886 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n");
1887 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ;
1888 }
dd498eff 1889
fa4aa2d4
B		 1890 pm_runtime_enable(host->dev);
1891 pm_runtime_get_sync(host->dev);
1892 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY);
1893 pm_runtime_use_autosuspend(host->dev);
a45c6cb8 1894
92a3aebf
B		 1895 omap_hsmmc_context_save(host);
1896
2bec0893
AH		 1897 if (cpu_is_omap2430()) {
1898 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
1899 /*
1900 * MMC can still work without debounce clock.
1901 */
1902 if (IS_ERR(host->dbclk))
1903 dev_warn(mmc_dev(host->mmc),
1904 "Failed to get debounce clock\n");
a45c6cb8 1905 else
2bec0893
AH		 1906 host->got_dbclk = 1;
1907
1908 if (host->got_dbclk)
1909 if (clk_enable(host->dbclk) != 0)
1910 dev_dbg(mmc_dev(host->mmc), "Enabling debounce"
1911 " clk failed\n");
1912 }
a45c6cb8 1913
0ccd76d4
JY		 1914 /* Since we do only SG emulation, we can have as many segs
1915 * as we want. */
a36274e0 1916 mmc->max_segs = 1024;
0ccd76d4 1917
a45c6cb8
MC		 1918 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */
1919 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */
1920 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1921 mmc->max_seg_size = mmc->max_req_size;
1922
13189e78 1923 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
93caf8e6 1924 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE;
a45c6cb8 1925
3a63833e
SG		 1926 mmc->caps |= mmc_slot(host).caps;
1927 if (mmc->caps & MMC_CAP_8_BIT_DATA)
a45c6cb8
MC		 1928 mmc->caps |= MMC_CAP_4_BIT_DATA;
1929
191d1f1d 1930 if (mmc_slot(host).nonremovable)
23d99bb9
AH		 1931 mmc->caps |= MMC_CAP_NONREMOVABLE;
1932
6fdc75de
EP		 1933 mmc->pm_caps = mmc_slot(host).pm_caps;
1934
70a3341a 1935 omap_hsmmc_conf_bus_power(host);
a45c6cb8 1936
b7bf773b
B		 1937 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
1938 if (!res) {
1939 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
1940 goto err_irq;
1941 }
1942 host->dma_line_tx = res->start;
1943
1944 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
1945 if (!res) {
1946 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
f3e2f1dd
GI		 1947 goto err_irq;
1948 }
b7bf773b 1949 host->dma_line_rx = res->start;
a45c6cb8
MC		 1950
1951 /* Request IRQ for MMC operations */
d9618e9f 1952 ret = request_irq(host->irq, omap_hsmmc_irq, 0,
a45c6cb8
MC		 1953 mmc_hostname(mmc), host);
1954 if (ret) {
1955 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n");
1956 goto err_irq;
1957 }
1958
1959 if (pdata->init != NULL) {
1960 if (pdata->init(&pdev->dev) != 0) {
70a3341a
DK		 1961 dev_dbg(mmc_dev(host->mmc),
1962 "Unable to configure MMC IRQs\n");
a45c6cb8
MC		 1963 goto err_irq_cd_init;
1964 }
1965 }
db0fefc5 1966
b702b106 1967 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) {
db0fefc5
AH		 1968 ret = omap_hsmmc_reg_get(host);
1969 if (ret)
1970 goto err_reg;
1971 host->use_reg = 1;
1972 }
1973
b583f26d 1974 mmc->ocr_avail = mmc_slot(host).ocr_mask;
a45c6cb8
MC		 1975
1976 /* Request IRQ for card detect */
e1a55f5e 1977 if ((mmc_slot(host).card_detect_irq)) {
7efab4f3
N		 1978 ret = request_threaded_irq(mmc_slot(host).card_detect_irq,
1979 NULL,
1980 omap_hsmmc_detect,
1981 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
1982 mmc_hostname(mmc), host);
a45c6cb8
MC		 1983 if (ret) {
1984 dev_dbg(mmc_dev(host->mmc),
1985 "Unable to grab MMC CD IRQ\n");
1986 goto err_irq_cd;
1987 }
72f2e2c7 1988 pdata->suspend = omap_hsmmc_suspend_cdirq;
1989 pdata->resume = omap_hsmmc_resume_cdirq;
a45c6cb8
MC		 1990 }
1991
b417577d 1992 omap_hsmmc_disable_irq(host);
a45c6cb8 1993
b62f6228
AH		 1994 omap_hsmmc_protect_card(host);
1995
a45c6cb8
MC		 1996 mmc_add_host(mmc);
1997
191d1f1d 1998 if (mmc_slot(host).name != NULL) {
a45c6cb8
MC		 1999 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name);
2000 if (ret < 0)
2001 goto err_slot_name;
2002 }
191d1f1d 2003 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) {
a45c6cb8
MC		 2004 ret = device_create_file(&mmc->class_dev,
2005 &dev_attr_cover_switch);
2006 if (ret < 0)
db0fefc5 2007 goto err_slot_name;
a45c6cb8
MC		 2008 }
2009
70a3341a 2010 omap_hsmmc_debugfs(mmc);
fa4aa2d4
B		 2011 pm_runtime_mark_last_busy(host->dev);
2012 pm_runtime_put_autosuspend(host->dev);
d900f712 2013
a45c6cb8
MC		 2014 return 0;
2015
a45c6cb8
MC		 2016err_slot_name:
2017 mmc_remove_host(mmc);
a45c6cb8 2018 free_irq(mmc_slot(host).card_detect_irq, host);
db0fefc5
AH		 2019err_irq_cd:
2020 if (host->use_reg)
2021 omap_hsmmc_reg_put(host);
2022err_reg:
2023 if (host->pdata->cleanup)
2024 host->pdata->cleanup(&pdev->dev);
a45c6cb8
MC		 2025err_irq_cd_init:
2026 free_irq(host->irq, host);
2027err_irq:
d59d77ed 2028 pm_runtime_put_sync(host->dev);
37f6190d 2029 pm_runtime_disable(host->dev);
a45c6cb8 2030 clk_put(host->fclk);
2bec0893 2031 if (host->got_dbclk) {
a45c6cb8
MC		 2032 clk_disable(host->dbclk);
2033 clk_put(host->dbclk);
2034 }
a45c6cb8
MC		 2035err1:
2036 iounmap(host->base);
db0fefc5
AH		 2037 platform_set_drvdata(pdev, NULL);
2038 mmc_free_host(mmc);
2039err_alloc:
2040 omap_hsmmc_gpio_free(pdata);
a45c6cb8 2041err:
984b203a 2042 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2043 return ret;
2044}
2045
efa25fd3 2046static int __devexit omap_hsmmc_remove(struct platform_device *pdev)
a45c6cb8 2047{
70a3341a 2048 struct omap_hsmmc_host *host = platform_get_drvdata(pdev);
a45c6cb8
MC		 2049 struct resource *res;
2050
927ce944
FB		 2051 pm_runtime_get_sync(host->dev);
2052 mmc_remove_host(host->mmc);
2053 if (host->use_reg)
2054 omap_hsmmc_reg_put(host);
2055 if (host->pdata->cleanup)
2056 host->pdata->cleanup(&pdev->dev);
2057 free_irq(host->irq, host);
2058 if (mmc_slot(host).card_detect_irq)
2059 free_irq(mmc_slot(host).card_detect_irq, host);
a45c6cb8 2060
927ce944
FB		 2061 pm_runtime_put_sync(host->dev);
2062 pm_runtime_disable(host->dev);
2063 clk_put(host->fclk);
2064 if (host->got_dbclk) {
2065 clk_disable(host->dbclk);
2066 clk_put(host->dbclk);
a45c6cb8
MC		 2067 }
2068
927ce944
FB		 2069 mmc_free_host(host->mmc);
2070 iounmap(host->base);
2071 omap_hsmmc_gpio_free(pdev->dev.platform_data);
2072
a45c6cb8
MC		 2073 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2074 if (res)
984b203a 2075 release_mem_region(res->start, resource_size(res));
a45c6cb8
MC		 2076 platform_set_drvdata(pdev, NULL);
2077
2078 return 0;
2079}
2080
2081#ifdef CONFIG_PM
a791daa1 2082static int omap_hsmmc_suspend(struct device *dev)
a45c6cb8
MC		 2083{
2084 int ret = 0;
927ce944 2085 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
a45c6cb8 2086
927ce944 2087 if (!host)
a45c6cb8
MC		 2088 return 0;
2089
927ce944
FB		 2090 if (host && host->suspended)
2091 return 0;
fa4aa2d4 2092
927ce944
FB		 2093 pm_runtime_get_sync(host->dev);
2094 host->suspended = 1;
2095 if (host->pdata->suspend) {
2096 ret = host->pdata->suspend(dev, host->slot_id);
31f9d463 2097 if (ret) {
927ce944
FB		 2098 dev_dbg(dev, "Unable to handle MMC board"
2099 " level suspend\n");
a6b2240d 2100 host->suspended = 0;
927ce944 2101 return ret;
a6b2240d 2102 }
927ce944
FB		 2103 }
2104 ret = mmc_suspend_host(host->mmc);
31f9d463 2105
927ce944
FB		 2106 if (ret) {
2107 host->suspended = 0;
2108 if (host->pdata->resume) {
2109 ret = host->pdata->resume(dev, host->slot_id);
2110 if (ret)
2111 dev_dbg(dev, "Unmask interrupt failed\n");
31f9d463 2112 }
927ce944
FB		 2113 goto err;
2114 }
31f9d463 2115
927ce944
FB		 2116 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) {
2117 omap_hsmmc_disable_irq(host);
2118 OMAP_HSMMC_WRITE(host->base, HCTL,
2119 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP);
a45c6cb8 2120 }
927ce944
FB		 2121
2122 if (host->got_dbclk)
2123 clk_disable(host->dbclk);
31f9d463
EP		 2124err:
2125 pm_runtime_put_sync(host->dev);
a45c6cb8
MC		 2126 return ret;
2127}
2128
2129/* Routine to resume the MMC device */
a791daa1 2130static int omap_hsmmc_resume(struct device *dev)
a45c6cb8
MC		 2131{
2132 int ret = 0;
927ce944
FB		 2133 struct omap_hsmmc_host *host = dev_get_drvdata(dev);
2134
2135 if (!host)
2136 return 0;
a45c6cb8
MC		 2137
2138 if (host && !host->suspended)
2139 return 0;
2140
927ce944 2141 pm_runtime_get_sync(host->dev);
11dd62a7 2142
927ce944
FB		 2143 if (host->got_dbclk)
2144 clk_enable(host->dbclk);
2bec0893 2145
927ce944
FB		 2146 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER))
2147 omap_hsmmc_conf_bus_power(host);
1b331e69 2148
927ce944
FB		 2149 if (host->pdata->resume) {
2150 ret = host->pdata->resume(dev, host->slot_id);
2151 if (ret)
2152 dev_dbg(dev, "Unmask interrupt failed\n");
2153 }
a45c6cb8 2154
927ce944 2155 omap_hsmmc_protect_card(host);
b62f6228 2156
927ce944
FB		 2157 /* Notify the core to resume the host */
2158 ret = mmc_resume_host(host->mmc);
2159 if (ret == 0)
2160 host->suspended = 0;
fa4aa2d4 2161
927ce944
FB		 2162 pm_runtime_mark_last_busy(host->dev);
2163 pm_runtime_put_autosuspend(host->dev);
a45c6cb8
MC		 2164
2165 return ret;
2166
a45c6cb8
MC		 2167}
2168
2169#else
70a3341a
DK		 2170#define omap_hsmmc_suspend NULL
2171#define omap_hsmmc_resume NULL
a45c6cb8
MC		 2172#endif
2173
fa4aa2d4
B		 2174static int omap_hsmmc_runtime_suspend(struct device *dev)
2175{
2176 struct omap_hsmmc_host *host;
2177
2178 host = platform_get_drvdata(to_platform_device(dev));
2179 omap_hsmmc_context_save(host);
927ce944 2180 dev_dbg(dev, "disabled\n");
fa4aa2d4
B		 2181
2182 return 0;
2183}
2184
2185static int omap_hsmmc_runtime_resume(struct device *dev)
2186{
2187 struct omap_hsmmc_host *host;
2188
2189 host = platform_get_drvdata(to_platform_device(dev));
2190 omap_hsmmc_context_restore(host);
927ce944 2191 dev_dbg(dev, "enabled\n");
fa4aa2d4
B		 2192
2193 return 0;
2194}
2195
a791daa1 2196static struct dev_pm_ops omap_hsmmc_dev_pm_ops = {
70a3341a
DK		 2197 .suspend = omap_hsmmc_suspend,
2198 .resume = omap_hsmmc_resume,
fa4aa2d4
B		 2199 .runtime_suspend = omap_hsmmc_runtime_suspend,
2200 .runtime_resume = omap_hsmmc_runtime_resume,
a791daa1
KH		 2201};
2202
2203static struct platform_driver omap_hsmmc_driver = {
efa25fd3
FB		 2204 .probe = omap_hsmmc_probe,
2205 .remove = __devexit_p(omap_hsmmc_remove),
a45c6cb8
MC		 2206 .driver = {
2207 .name = DRIVER_NAME,
2208 .owner = THIS_MODULE,
a791daa1 2209 .pm = &omap_hsmmc_dev_pm_ops,
46856a68 2210 .of_match_table = of_match_ptr(omap_mmc_of_match),
a45c6cb8
MC		 2211 },
2212};
2213
b796450b 2214module_platform_driver(omap_hsmmc_driver);
a45c6cb8
MC		 2215MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver");
2216MODULE_LICENSE("GPL");
2217MODULE_ALIAS("platform:" DRIVER_NAME);
2218MODULE_AUTHOR("Texas Instruments Inc");
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