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Commit | Line | Data |
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a45c6cb8 MC |
1 | /* |
2 | * drivers/mmc/host/omap_hsmmc.c | |
3 | * | |
4 | * Driver for OMAP2430/3430 MMC controller. | |
5 | * | |
6 | * Copyright (C) 2007 Texas Instruments. | |
7 | * | |
8 | * Authors: | |
9 | * Syed Mohammed Khasim <x0khasim@ti.com> | |
10 | * Madhusudhan <madhu.cr@ti.com> | |
11 | * Mohit Jalori <mjalori@ti.com> | |
12 | * | |
13 | * This file is licensed under the terms of the GNU General Public License | |
14 | * version 2. This program is licensed "as is" without any warranty of any | |
15 | * kind, whether express or implied. | |
16 | */ | |
17 | ||
18 | #include <linux/module.h> | |
19 | #include <linux/init.h> | |
ac330f44 | 20 | #include <linux/kernel.h> |
d900f712 | 21 | #include <linux/debugfs.h> |
c5c98927 | 22 | #include <linux/dmaengine.h> |
d900f712 | 23 | #include <linux/seq_file.h> |
a45c6cb8 MC |
24 | #include <linux/interrupt.h> |
25 | #include <linux/delay.h> | |
26 | #include <linux/dma-mapping.h> | |
27 | #include <linux/platform_device.h> | |
a45c6cb8 MC |
28 | #include <linux/timer.h> |
29 | #include <linux/clk.h> | |
46856a68 RN |
30 | #include <linux/of.h> |
31 | #include <linux/of_gpio.h> | |
32 | #include <linux/of_device.h> | |
3451c067 | 33 | #include <linux/omap-dma.h> |
a45c6cb8 | 34 | #include <linux/mmc/host.h> |
13189e78 | 35 | #include <linux/mmc/core.h> |
93caf8e6 | 36 | #include <linux/mmc/mmc.h> |
a45c6cb8 | 37 | #include <linux/io.h> |
db0fefc5 AH |
38 | #include <linux/gpio.h> |
39 | #include <linux/regulator/consumer.h> | |
fa4aa2d4 | 40 | #include <linux/pm_runtime.h> |
a45c6cb8 | 41 | #include <mach/hardware.h> |
ce491cf8 TL |
42 | #include <plat/mmc.h> |
43 | #include <plat/cpu.h> | |
a45c6cb8 MC |
44 | |
45 | /* OMAP HSMMC Host Controller Registers */ | |
11dd62a7 | 46 | #define OMAP_HSMMC_SYSSTATUS 0x0014 |
a45c6cb8 MC |
47 | #define OMAP_HSMMC_CON 0x002C |
48 | #define OMAP_HSMMC_BLK 0x0104 | |
49 | #define OMAP_HSMMC_ARG 0x0108 | |
50 | #define OMAP_HSMMC_CMD 0x010C | |
51 | #define OMAP_HSMMC_RSP10 0x0110 | |
52 | #define OMAP_HSMMC_RSP32 0x0114 | |
53 | #define OMAP_HSMMC_RSP54 0x0118 | |
54 | #define OMAP_HSMMC_RSP76 0x011C | |
55 | #define OMAP_HSMMC_DATA 0x0120 | |
56 | #define OMAP_HSMMC_HCTL 0x0128 | |
57 | #define OMAP_HSMMC_SYSCTL 0x012C | |
58 | #define OMAP_HSMMC_STAT 0x0130 | |
59 | #define OMAP_HSMMC_IE 0x0134 | |
60 | #define OMAP_HSMMC_ISE 0x0138 | |
61 | #define OMAP_HSMMC_CAPA 0x0140 | |
62 | ||
63 | #define VS18 (1 << 26) | |
64 | #define VS30 (1 << 25) | |
65 | #define SDVS18 (0x5 << 9) | |
66 | #define SDVS30 (0x6 << 9) | |
eb250826 | 67 | #define SDVS33 (0x7 << 9) |
1b331e69 | 68 | #define SDVS_MASK 0x00000E00 |
a45c6cb8 MC |
69 | #define SDVSCLR 0xFFFFF1FF |
70 | #define SDVSDET 0x00000400 | |
71 | #define AUTOIDLE 0x1 | |
72 | #define SDBP (1 << 8) | |
73 | #define DTO 0xe | |
74 | #define ICE 0x1 | |
75 | #define ICS 0x2 | |
76 | #define CEN (1 << 2) | |
77 | #define CLKD_MASK 0x0000FFC0 | |
78 | #define CLKD_SHIFT 6 | |
79 | #define DTO_MASK 0x000F0000 | |
80 | #define DTO_SHIFT 16 | |
81 | #define INT_EN_MASK 0x307F0033 | |
ccdfe3a6 AG |
82 | #define BWR_ENABLE (1 << 4) |
83 | #define BRR_ENABLE (1 << 5) | |
93caf8e6 | 84 | #define DTO_ENABLE (1 << 20) |
a45c6cb8 MC |
85 | #define INIT_STREAM (1 << 1) |
86 | #define DP_SELECT (1 << 21) | |
87 | #define DDIR (1 << 4) | |
88 | #define DMA_EN 0x1 | |
89 | #define MSBS (1 << 5) | |
90 | #define BCE (1 << 1) | |
91 | #define FOUR_BIT (1 << 1) | |
03b5d924 | 92 | #define DDR (1 << 19) |
73153010 | 93 | #define DW8 (1 << 5) |
a45c6cb8 MC |
94 | #define CC 0x1 |
95 | #define TC 0x02 | |
96 | #define OD 0x1 | |
97 | #define ERR (1 << 15) | |
98 | #define CMD_TIMEOUT (1 << 16) | |
99 | #define DATA_TIMEOUT (1 << 20) | |
100 | #define CMD_CRC (1 << 17) | |
101 | #define DATA_CRC (1 << 21) | |
102 | #define CARD_ERR (1 << 28) | |
103 | #define STAT_CLEAR 0xFFFFFFFF | |
104 | #define INIT_STREAM_CMD 0x00000000 | |
105 | #define DUAL_VOLT_OCR_BIT 7 | |
106 | #define SRC (1 << 25) | |
107 | #define SRD (1 << 26) | |
11dd62a7 DK |
108 | #define SOFTRESET (1 << 1) |
109 | #define RESETDONE (1 << 0) | |
a45c6cb8 | 110 | |
fa4aa2d4 | 111 | #define MMC_AUTOSUSPEND_DELAY 100 |
a45c6cb8 | 112 | #define MMC_TIMEOUT_MS 20 |
6b206efe AS |
113 | #define OMAP_MMC_MIN_CLOCK 400000 |
114 | #define OMAP_MMC_MAX_CLOCK 52000000 | |
0005ae73 | 115 | #define DRIVER_NAME "omap_hsmmc" |
a45c6cb8 MC |
116 | |
117 | /* | |
118 | * One controller can have multiple slots, like on some omap boards using | |
119 | * omap.c controller driver. Luckily this is not currently done on any known | |
120 | * omap_hsmmc.c device. | |
121 | */ | |
122 | #define mmc_slot(host) (host->pdata->slots[host->slot_id]) | |
123 | ||
124 | /* | |
125 | * MMC Host controller read/write API's | |
126 | */ | |
127 | #define OMAP_HSMMC_READ(base, reg) \ | |
128 | __raw_readl((base) + OMAP_HSMMC_##reg) | |
129 | ||
130 | #define OMAP_HSMMC_WRITE(base, reg, val) \ | |
131 | __raw_writel((val), (base) + OMAP_HSMMC_##reg) | |
132 | ||
9782aff8 PF |
133 | struct omap_hsmmc_next { |
134 | unsigned int dma_len; | |
135 | s32 cookie; | |
136 | }; | |
137 | ||
70a3341a | 138 | struct omap_hsmmc_host { |
a45c6cb8 MC |
139 | struct device *dev; |
140 | struct mmc_host *mmc; | |
141 | struct mmc_request *mrq; | |
142 | struct mmc_command *cmd; | |
143 | struct mmc_data *data; | |
144 | struct clk *fclk; | |
a45c6cb8 | 145 | struct clk *dbclk; |
db0fefc5 AH |
146 | /* |
147 | * vcc == configured supply | |
148 | * vcc_aux == optional | |
149 | * - MMC1, supply for DAT4..DAT7 | |
150 | * - MMC2/MMC2, external level shifter voltage supply, for | |
151 | * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) | |
152 | */ | |
153 | struct regulator *vcc; | |
154 | struct regulator *vcc_aux; | |
a45c6cb8 MC |
155 | void __iomem *base; |
156 | resource_size_t mapbase; | |
4dffd7a2 | 157 | spinlock_t irq_lock; /* Prevent races with irq handler */ |
a45c6cb8 | 158 | unsigned int dma_len; |
0ccd76d4 | 159 | unsigned int dma_sg_idx; |
a45c6cb8 | 160 | unsigned char bus_mode; |
a3621465 | 161 | unsigned char power_mode; |
a45c6cb8 MC |
162 | int suspended; |
163 | int irq; | |
a45c6cb8 | 164 | int use_dma, dma_ch; |
c5c98927 RK |
165 | struct dma_chan *tx_chan; |
166 | struct dma_chan *rx_chan; | |
a45c6cb8 | 167 | int slot_id; |
4a694dc9 | 168 | int response_busy; |
11dd62a7 | 169 | int context_loss; |
b62f6228 AH |
170 | int protect_card; |
171 | int reqs_blocked; | |
db0fefc5 | 172 | int use_reg; |
b417577d | 173 | int req_in_progress; |
9782aff8 | 174 | struct omap_hsmmc_next next_data; |
11dd62a7 | 175 | |
a45c6cb8 MC |
176 | struct omap_mmc_platform_data *pdata; |
177 | }; | |
178 | ||
db0fefc5 AH |
179 | static int omap_hsmmc_card_detect(struct device *dev, int slot) |
180 | { | |
9ea28ecb B |
181 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
182 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
183 | |
184 | /* NOTE: assumes card detect signal is active-low */ | |
185 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
186 | } | |
187 | ||
188 | static int omap_hsmmc_get_wp(struct device *dev, int slot) | |
189 | { | |
9ea28ecb B |
190 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
191 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
192 | |
193 | /* NOTE: assumes write protect signal is active-high */ | |
194 | return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); | |
195 | } | |
196 | ||
197 | static int omap_hsmmc_get_cover_state(struct device *dev, int slot) | |
198 | { | |
9ea28ecb B |
199 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
200 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
201 | |
202 | /* NOTE: assumes card detect signal is active-low */ | |
203 | return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); | |
204 | } | |
205 | ||
206 | #ifdef CONFIG_PM | |
207 | ||
208 | static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) | |
209 | { | |
9ea28ecb B |
210 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
211 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
212 | |
213 | disable_irq(mmc->slots[0].card_detect_irq); | |
214 | return 0; | |
215 | } | |
216 | ||
217 | static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) | |
218 | { | |
9ea28ecb B |
219 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
220 | struct omap_mmc_platform_data *mmc = host->pdata; | |
db0fefc5 AH |
221 | |
222 | enable_irq(mmc->slots[0].card_detect_irq); | |
223 | return 0; | |
224 | } | |
225 | ||
226 | #else | |
227 | ||
228 | #define omap_hsmmc_suspend_cdirq NULL | |
229 | #define omap_hsmmc_resume_cdirq NULL | |
230 | ||
231 | #endif | |
232 | ||
b702b106 AH |
233 | #ifdef CONFIG_REGULATOR |
234 | ||
69b07ece | 235 | static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, |
db0fefc5 AH |
236 | int vdd) |
237 | { | |
238 | struct omap_hsmmc_host *host = | |
239 | platform_get_drvdata(to_platform_device(dev)); | |
240 | int ret = 0; | |
241 | ||
242 | /* | |
243 | * If we don't see a Vcc regulator, assume it's a fixed | |
244 | * voltage always-on regulator. | |
245 | */ | |
246 | if (!host->vcc) | |
247 | return 0; | |
1f84b71b RN |
248 | /* |
249 | * With DT, never turn OFF the regulator. This is because | |
250 | * the pbias cell programming support is still missing when | |
251 | * booting with Device tree | |
252 | */ | |
4d048f91 | 253 | if (dev->of_node && !vdd) |
1f84b71b | 254 | return 0; |
db0fefc5 AH |
255 | |
256 | if (mmc_slot(host).before_set_reg) | |
257 | mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); | |
258 | ||
259 | /* | |
260 | * Assume Vcc regulator is used only to power the card ... OMAP | |
261 | * VDDS is used to power the pins, optionally with a transceiver to | |
262 | * support cards using voltages other than VDDS (1.8V nominal). When a | |
263 | * transceiver is used, DAT3..7 are muxed as transceiver control pins. | |
264 | * | |
265 | * In some cases this regulator won't support enable/disable; | |
266 | * e.g. it's a fixed rail for a WLAN chip. | |
267 | * | |
268 | * In other cases vcc_aux switches interface power. Example, for | |
269 | * eMMC cards it represents VccQ. Sometimes transceivers or SDIO | |
270 | * chips/cards need an interface voltage rail too. | |
271 | */ | |
272 | if (power_on) { | |
99fc5131 | 273 | ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); |
db0fefc5 AH |
274 | /* Enable interface voltage rail, if needed */ |
275 | if (ret == 0 && host->vcc_aux) { | |
276 | ret = regulator_enable(host->vcc_aux); | |
277 | if (ret < 0) | |
99fc5131 LW |
278 | ret = mmc_regulator_set_ocr(host->mmc, |
279 | host->vcc, 0); | |
db0fefc5 AH |
280 | } |
281 | } else { | |
99fc5131 | 282 | /* Shut down the rail */ |
6da20c89 AH |
283 | if (host->vcc_aux) |
284 | ret = regulator_disable(host->vcc_aux); | |
99fc5131 LW |
285 | if (!ret) { |
286 | /* Then proceed to shut down the local regulator */ | |
287 | ret = mmc_regulator_set_ocr(host->mmc, | |
288 | host->vcc, 0); | |
289 | } | |
db0fefc5 AH |
290 | } |
291 | ||
292 | if (mmc_slot(host).after_set_reg) | |
293 | mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); | |
294 | ||
295 | return ret; | |
296 | } | |
297 | ||
db0fefc5 AH |
298 | static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) |
299 | { | |
300 | struct regulator *reg; | |
64be9782 | 301 | int ocr_value = 0; |
db0fefc5 | 302 | |
db0fefc5 AH |
303 | reg = regulator_get(host->dev, "vmmc"); |
304 | if (IS_ERR(reg)) { | |
305 | dev_dbg(host->dev, "vmmc regulator missing\n"); | |
1fdc90fb | 306 | return PTR_ERR(reg); |
db0fefc5 | 307 | } else { |
1fdc90fb | 308 | mmc_slot(host).set_power = omap_hsmmc_set_power; |
db0fefc5 | 309 | host->vcc = reg; |
64be9782 | 310 | ocr_value = mmc_regulator_get_ocrmask(reg); |
311 | if (!mmc_slot(host).ocr_mask) { | |
312 | mmc_slot(host).ocr_mask = ocr_value; | |
313 | } else { | |
314 | if (!(mmc_slot(host).ocr_mask & ocr_value)) { | |
2cecdf00 | 315 | dev_err(host->dev, "ocrmask %x is not supported\n", |
e3f1adb6 | 316 | mmc_slot(host).ocr_mask); |
64be9782 | 317 | mmc_slot(host).ocr_mask = 0; |
318 | return -EINVAL; | |
319 | } | |
320 | } | |
db0fefc5 AH |
321 | |
322 | /* Allow an aux regulator */ | |
323 | reg = regulator_get(host->dev, "vmmc_aux"); | |
324 | host->vcc_aux = IS_ERR(reg) ? NULL : reg; | |
325 | ||
b1c1df7a B |
326 | /* For eMMC do not power off when not in sleep state */ |
327 | if (mmc_slot(host).no_regulator_off_init) | |
328 | return 0; | |
db0fefc5 AH |
329 | /* |
330 | * UGLY HACK: workaround regulator framework bugs. | |
331 | * When the bootloader leaves a supply active, it's | |
332 | * initialized with zero usecount ... and we can't | |
333 | * disable it without first enabling it. Until the | |
334 | * framework is fixed, we need a workaround like this | |
335 | * (which is safe for MMC, but not in general). | |
336 | */ | |
e840ce13 AH |
337 | if (regulator_is_enabled(host->vcc) > 0 || |
338 | (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { | |
339 | int vdd = ffs(mmc_slot(host).ocr_mask) - 1; | |
340 | ||
341 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
342 | 1, vdd); | |
343 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
344 | 0, 0); | |
db0fefc5 AH |
345 | } |
346 | } | |
347 | ||
348 | return 0; | |
db0fefc5 AH |
349 | } |
350 | ||
351 | static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) | |
352 | { | |
353 | regulator_put(host->vcc); | |
354 | regulator_put(host->vcc_aux); | |
355 | mmc_slot(host).set_power = NULL; | |
db0fefc5 AH |
356 | } |
357 | ||
b702b106 AH |
358 | static inline int omap_hsmmc_have_reg(void) |
359 | { | |
360 | return 1; | |
361 | } | |
362 | ||
363 | #else | |
364 | ||
365 | static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) | |
366 | { | |
367 | return -EINVAL; | |
368 | } | |
369 | ||
370 | static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) | |
371 | { | |
372 | } | |
373 | ||
374 | static inline int omap_hsmmc_have_reg(void) | |
375 | { | |
376 | return 0; | |
377 | } | |
378 | ||
379 | #endif | |
380 | ||
381 | static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) | |
382 | { | |
383 | int ret; | |
384 | ||
385 | if (gpio_is_valid(pdata->slots[0].switch_pin)) { | |
b702b106 AH |
386 | if (pdata->slots[0].cover) |
387 | pdata->slots[0].get_cover_state = | |
388 | omap_hsmmc_get_cover_state; | |
389 | else | |
390 | pdata->slots[0].card_detect = omap_hsmmc_card_detect; | |
391 | pdata->slots[0].card_detect_irq = | |
392 | gpio_to_irq(pdata->slots[0].switch_pin); | |
393 | ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); | |
394 | if (ret) | |
395 | return ret; | |
396 | ret = gpio_direction_input(pdata->slots[0].switch_pin); | |
397 | if (ret) | |
398 | goto err_free_sp; | |
399 | } else | |
400 | pdata->slots[0].switch_pin = -EINVAL; | |
401 | ||
402 | if (gpio_is_valid(pdata->slots[0].gpio_wp)) { | |
403 | pdata->slots[0].get_ro = omap_hsmmc_get_wp; | |
404 | ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); | |
405 | if (ret) | |
406 | goto err_free_cd; | |
407 | ret = gpio_direction_input(pdata->slots[0].gpio_wp); | |
408 | if (ret) | |
409 | goto err_free_wp; | |
410 | } else | |
411 | pdata->slots[0].gpio_wp = -EINVAL; | |
412 | ||
413 | return 0; | |
414 | ||
415 | err_free_wp: | |
416 | gpio_free(pdata->slots[0].gpio_wp); | |
417 | err_free_cd: | |
418 | if (gpio_is_valid(pdata->slots[0].switch_pin)) | |
419 | err_free_sp: | |
420 | gpio_free(pdata->slots[0].switch_pin); | |
421 | return ret; | |
422 | } | |
423 | ||
424 | static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) | |
425 | { | |
426 | if (gpio_is_valid(pdata->slots[0].gpio_wp)) | |
427 | gpio_free(pdata->slots[0].gpio_wp); | |
428 | if (gpio_is_valid(pdata->slots[0].switch_pin)) | |
429 | gpio_free(pdata->slots[0].switch_pin); | |
430 | } | |
431 | ||
e0c7f99b AS |
432 | /* |
433 | * Start clock to the card | |
434 | */ | |
435 | static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) | |
436 | { | |
437 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
438 | OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); | |
439 | } | |
440 | ||
a45c6cb8 MC |
441 | /* |
442 | * Stop clock to the card | |
443 | */ | |
70a3341a | 444 | static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
445 | { |
446 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
447 | OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); | |
448 | if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) | |
7122bbb0 | 449 | dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); |
a45c6cb8 MC |
450 | } |
451 | ||
93caf8e6 AH |
452 | static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, |
453 | struct mmc_command *cmd) | |
b417577d AH |
454 | { |
455 | unsigned int irq_mask; | |
456 | ||
457 | if (host->use_dma) | |
458 | irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); | |
459 | else | |
460 | irq_mask = INT_EN_MASK; | |
461 | ||
93caf8e6 AH |
462 | /* Disable timeout for erases */ |
463 | if (cmd->opcode == MMC_ERASE) | |
464 | irq_mask &= ~DTO_ENABLE; | |
465 | ||
b417577d AH |
466 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); |
467 | OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); | |
468 | OMAP_HSMMC_WRITE(host->base, IE, irq_mask); | |
469 | } | |
470 | ||
471 | static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) | |
472 | { | |
473 | OMAP_HSMMC_WRITE(host->base, ISE, 0); | |
474 | OMAP_HSMMC_WRITE(host->base, IE, 0); | |
475 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
476 | } | |
477 | ||
ac330f44 | 478 | /* Calculate divisor for the given clock frequency */ |
d83b6e03 | 479 | static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) |
ac330f44 AS |
480 | { |
481 | u16 dsor = 0; | |
482 | ||
483 | if (ios->clock) { | |
d83b6e03 | 484 | dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); |
ac330f44 AS |
485 | if (dsor > 250) |
486 | dsor = 250; | |
487 | } | |
488 | ||
489 | return dsor; | |
490 | } | |
491 | ||
5934df2f AS |
492 | static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) |
493 | { | |
494 | struct mmc_ios *ios = &host->mmc->ios; | |
495 | unsigned long regval; | |
496 | unsigned long timeout; | |
497 | ||
8986d31b | 498 | dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); |
5934df2f AS |
499 | |
500 | omap_hsmmc_stop_clock(host); | |
501 | ||
502 | regval = OMAP_HSMMC_READ(host->base, SYSCTL); | |
503 | regval = regval & ~(CLKD_MASK | DTO_MASK); | |
d83b6e03 | 504 | regval = regval | (calc_divisor(host, ios) << 6) | (DTO << 16); |
5934df2f AS |
505 | OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); |
506 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
507 | OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); | |
508 | ||
509 | /* Wait till the ICS bit is set */ | |
510 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
511 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS | |
512 | && time_before(jiffies, timeout)) | |
513 | cpu_relax(); | |
514 | ||
515 | omap_hsmmc_start_clock(host); | |
516 | } | |
517 | ||
3796fb8a AS |
518 | static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) |
519 | { | |
520 | struct mmc_ios *ios = &host->mmc->ios; | |
521 | u32 con; | |
522 | ||
523 | con = OMAP_HSMMC_READ(host->base, CON); | |
03b5d924 B |
524 | if (ios->timing == MMC_TIMING_UHS_DDR50) |
525 | con |= DDR; /* configure in DDR mode */ | |
526 | else | |
527 | con &= ~DDR; | |
3796fb8a AS |
528 | switch (ios->bus_width) { |
529 | case MMC_BUS_WIDTH_8: | |
530 | OMAP_HSMMC_WRITE(host->base, CON, con | DW8); | |
531 | break; | |
532 | case MMC_BUS_WIDTH_4: | |
533 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
534 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
535 | OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); | |
536 | break; | |
537 | case MMC_BUS_WIDTH_1: | |
538 | OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); | |
539 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
540 | OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); | |
541 | break; | |
542 | } | |
543 | } | |
544 | ||
545 | static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) | |
546 | { | |
547 | struct mmc_ios *ios = &host->mmc->ios; | |
548 | u32 con; | |
549 | ||
550 | con = OMAP_HSMMC_READ(host->base, CON); | |
551 | if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) | |
552 | OMAP_HSMMC_WRITE(host->base, CON, con | OD); | |
553 | else | |
554 | OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); | |
555 | } | |
556 | ||
11dd62a7 DK |
557 | #ifdef CONFIG_PM |
558 | ||
559 | /* | |
560 | * Restore the MMC host context, if it was lost as result of a | |
561 | * power state change. | |
562 | */ | |
70a3341a | 563 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
564 | { |
565 | struct mmc_ios *ios = &host->mmc->ios; | |
566 | struct omap_mmc_platform_data *pdata = host->pdata; | |
567 | int context_loss = 0; | |
3796fb8a | 568 | u32 hctl, capa; |
11dd62a7 DK |
569 | unsigned long timeout; |
570 | ||
571 | if (pdata->get_context_loss_count) { | |
572 | context_loss = pdata->get_context_loss_count(host->dev); | |
573 | if (context_loss < 0) | |
574 | return 1; | |
575 | } | |
576 | ||
577 | dev_dbg(mmc_dev(host->mmc), "context was %slost\n", | |
578 | context_loss == host->context_loss ? "not " : ""); | |
579 | if (host->context_loss == context_loss) | |
580 | return 1; | |
581 | ||
6c31b215 V |
582 | if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) |
583 | return 1; | |
11dd62a7 | 584 | |
c2200efb | 585 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
11dd62a7 DK |
586 | if (host->power_mode != MMC_POWER_OFF && |
587 | (1 << ios->vdd) <= MMC_VDD_23_24) | |
588 | hctl = SDVS18; | |
589 | else | |
590 | hctl = SDVS30; | |
591 | capa = VS30 | VS18; | |
592 | } else { | |
593 | hctl = SDVS18; | |
594 | capa = VS18; | |
595 | } | |
596 | ||
597 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
598 | OMAP_HSMMC_READ(host->base, HCTL) | hctl); | |
599 | ||
600 | OMAP_HSMMC_WRITE(host->base, CAPA, | |
601 | OMAP_HSMMC_READ(host->base, CAPA) | capa); | |
602 | ||
603 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
604 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
605 | ||
606 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
607 | while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP | |
608 | && time_before(jiffies, timeout)) | |
609 | ; | |
610 | ||
b417577d | 611 | omap_hsmmc_disable_irq(host); |
11dd62a7 DK |
612 | |
613 | /* Do not initialize card-specific things if the power is off */ | |
614 | if (host->power_mode == MMC_POWER_OFF) | |
615 | goto out; | |
616 | ||
3796fb8a | 617 | omap_hsmmc_set_bus_width(host); |
11dd62a7 | 618 | |
5934df2f | 619 | omap_hsmmc_set_clock(host); |
11dd62a7 | 620 | |
3796fb8a AS |
621 | omap_hsmmc_set_bus_mode(host); |
622 | ||
11dd62a7 DK |
623 | out: |
624 | host->context_loss = context_loss; | |
625 | ||
626 | dev_dbg(mmc_dev(host->mmc), "context is restored\n"); | |
627 | return 0; | |
628 | } | |
629 | ||
630 | /* | |
631 | * Save the MMC host context (store the number of power state changes so far). | |
632 | */ | |
70a3341a | 633 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
634 | { |
635 | struct omap_mmc_platform_data *pdata = host->pdata; | |
636 | int context_loss; | |
637 | ||
638 | if (pdata->get_context_loss_count) { | |
639 | context_loss = pdata->get_context_loss_count(host->dev); | |
640 | if (context_loss < 0) | |
641 | return; | |
642 | host->context_loss = context_loss; | |
643 | } | |
644 | } | |
645 | ||
646 | #else | |
647 | ||
70a3341a | 648 | static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) |
11dd62a7 DK |
649 | { |
650 | return 0; | |
651 | } | |
652 | ||
70a3341a | 653 | static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) |
11dd62a7 DK |
654 | { |
655 | } | |
656 | ||
657 | #endif | |
658 | ||
a45c6cb8 MC |
659 | /* |
660 | * Send init stream sequence to card | |
661 | * before sending IDLE command | |
662 | */ | |
70a3341a | 663 | static void send_init_stream(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
664 | { |
665 | int reg = 0; | |
666 | unsigned long timeout; | |
667 | ||
b62f6228 AH |
668 | if (host->protect_card) |
669 | return; | |
670 | ||
a45c6cb8 | 671 | disable_irq(host->irq); |
b417577d AH |
672 | |
673 | OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); | |
a45c6cb8 MC |
674 | OMAP_HSMMC_WRITE(host->base, CON, |
675 | OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); | |
676 | OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); | |
677 | ||
678 | timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); | |
679 | while ((reg != CC) && time_before(jiffies, timeout)) | |
680 | reg = OMAP_HSMMC_READ(host->base, STAT) & CC; | |
681 | ||
682 | OMAP_HSMMC_WRITE(host->base, CON, | |
683 | OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); | |
c653a6d4 AH |
684 | |
685 | OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); | |
686 | OMAP_HSMMC_READ(host->base, STAT); | |
687 | ||
a45c6cb8 MC |
688 | enable_irq(host->irq); |
689 | } | |
690 | ||
691 | static inline | |
70a3341a | 692 | int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) |
a45c6cb8 MC |
693 | { |
694 | int r = 1; | |
695 | ||
191d1f1d DK |
696 | if (mmc_slot(host).get_cover_state) |
697 | r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); | |
a45c6cb8 MC |
698 | return r; |
699 | } | |
700 | ||
701 | static ssize_t | |
70a3341a | 702 | omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
703 | char *buf) |
704 | { | |
705 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 706 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 707 | |
70a3341a DK |
708 | return sprintf(buf, "%s\n", |
709 | omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); | |
a45c6cb8 MC |
710 | } |
711 | ||
70a3341a | 712 | static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); |
a45c6cb8 MC |
713 | |
714 | static ssize_t | |
70a3341a | 715 | omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, |
a45c6cb8 MC |
716 | char *buf) |
717 | { | |
718 | struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); | |
70a3341a | 719 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 720 | |
191d1f1d | 721 | return sprintf(buf, "%s\n", mmc_slot(host).name); |
a45c6cb8 MC |
722 | } |
723 | ||
70a3341a | 724 | static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); |
a45c6cb8 MC |
725 | |
726 | /* | |
727 | * Configure the response type and send the cmd. | |
728 | */ | |
729 | static void | |
70a3341a | 730 | omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, |
a45c6cb8 MC |
731 | struct mmc_data *data) |
732 | { | |
733 | int cmdreg = 0, resptype = 0, cmdtype = 0; | |
734 | ||
8986d31b | 735 | dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", |
a45c6cb8 MC |
736 | mmc_hostname(host->mmc), cmd->opcode, cmd->arg); |
737 | host->cmd = cmd; | |
738 | ||
93caf8e6 | 739 | omap_hsmmc_enable_irq(host, cmd); |
a45c6cb8 | 740 | |
4a694dc9 | 741 | host->response_busy = 0; |
a45c6cb8 MC |
742 | if (cmd->flags & MMC_RSP_PRESENT) { |
743 | if (cmd->flags & MMC_RSP_136) | |
744 | resptype = 1; | |
4a694dc9 AH |
745 | else if (cmd->flags & MMC_RSP_BUSY) { |
746 | resptype = 3; | |
747 | host->response_busy = 1; | |
748 | } else | |
a45c6cb8 MC |
749 | resptype = 2; |
750 | } | |
751 | ||
752 | /* | |
753 | * Unlike OMAP1 controller, the cmdtype does not seem to be based on | |
754 | * ac, bc, adtc, bcr. Only commands ending an open ended transfer need | |
755 | * a val of 0x3, rest 0x0. | |
756 | */ | |
757 | if (cmd == host->mrq->stop) | |
758 | cmdtype = 0x3; | |
759 | ||
760 | cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); | |
761 | ||
762 | if (data) { | |
763 | cmdreg |= DP_SELECT | MSBS | BCE; | |
764 | if (data->flags & MMC_DATA_READ) | |
765 | cmdreg |= DDIR; | |
766 | else | |
767 | cmdreg &= ~(DDIR); | |
768 | } | |
769 | ||
770 | if (host->use_dma) | |
771 | cmdreg |= DMA_EN; | |
772 | ||
b417577d | 773 | host->req_in_progress = 1; |
4dffd7a2 | 774 | |
a45c6cb8 MC |
775 | OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); |
776 | OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); | |
777 | } | |
778 | ||
0ccd76d4 | 779 | static int |
70a3341a | 780 | omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) |
0ccd76d4 JY |
781 | { |
782 | if (data->flags & MMC_DATA_WRITE) | |
783 | return DMA_TO_DEVICE; | |
784 | else | |
785 | return DMA_FROM_DEVICE; | |
786 | } | |
787 | ||
c5c98927 RK |
788 | static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, |
789 | struct mmc_data *data) | |
790 | { | |
791 | return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; | |
792 | } | |
793 | ||
b417577d AH |
794 | static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) |
795 | { | |
796 | int dma_ch; | |
31463b14 | 797 | unsigned long flags; |
b417577d | 798 | |
31463b14 | 799 | spin_lock_irqsave(&host->irq_lock, flags); |
b417577d AH |
800 | host->req_in_progress = 0; |
801 | dma_ch = host->dma_ch; | |
31463b14 | 802 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
803 | |
804 | omap_hsmmc_disable_irq(host); | |
805 | /* Do not complete the request if DMA is still in progress */ | |
806 | if (mrq->data && host->use_dma && dma_ch != -1) | |
807 | return; | |
808 | host->mrq = NULL; | |
809 | mmc_request_done(host->mmc, mrq); | |
810 | } | |
811 | ||
a45c6cb8 MC |
812 | /* |
813 | * Notify the transfer complete to MMC core | |
814 | */ | |
815 | static void | |
70a3341a | 816 | omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) |
a45c6cb8 | 817 | { |
4a694dc9 AH |
818 | if (!data) { |
819 | struct mmc_request *mrq = host->mrq; | |
820 | ||
23050103 AH |
821 | /* TC before CC from CMD6 - don't know why, but it happens */ |
822 | if (host->cmd && host->cmd->opcode == 6 && | |
823 | host->response_busy) { | |
824 | host->response_busy = 0; | |
825 | return; | |
826 | } | |
827 | ||
b417577d | 828 | omap_hsmmc_request_done(host, mrq); |
4a694dc9 AH |
829 | return; |
830 | } | |
831 | ||
a45c6cb8 MC |
832 | host->data = NULL; |
833 | ||
a45c6cb8 MC |
834 | if (!data->error) |
835 | data->bytes_xfered += data->blocks * (data->blksz); | |
836 | else | |
837 | data->bytes_xfered = 0; | |
838 | ||
fe852273 | 839 | if (!data->stop) { |
b417577d | 840 | omap_hsmmc_request_done(host, data->mrq); |
fe852273 | 841 | return; |
a45c6cb8 | 842 | } |
fe852273 | 843 | omap_hsmmc_start_command(host, data->stop, NULL); |
a45c6cb8 MC |
844 | } |
845 | ||
846 | /* | |
847 | * Notify the core about command completion | |
848 | */ | |
849 | static void | |
70a3341a | 850 | omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) |
a45c6cb8 MC |
851 | { |
852 | host->cmd = NULL; | |
853 | ||
854 | if (cmd->flags & MMC_RSP_PRESENT) { | |
855 | if (cmd->flags & MMC_RSP_136) { | |
856 | /* response type 2 */ | |
857 | cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); | |
858 | cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); | |
859 | cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); | |
860 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); | |
861 | } else { | |
862 | /* response types 1, 1b, 3, 4, 5, 6 */ | |
863 | cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); | |
864 | } | |
865 | } | |
b417577d AH |
866 | if ((host->data == NULL && !host->response_busy) || cmd->error) |
867 | omap_hsmmc_request_done(host, cmd->mrq); | |
a45c6cb8 MC |
868 | } |
869 | ||
870 | /* | |
871 | * DMA clean up for command errors | |
872 | */ | |
70a3341a | 873 | static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) |
a45c6cb8 | 874 | { |
b417577d | 875 | int dma_ch; |
31463b14 | 876 | unsigned long flags; |
b417577d | 877 | |
82788ff5 | 878 | host->data->error = errno; |
a45c6cb8 | 879 | |
31463b14 | 880 | spin_lock_irqsave(&host->irq_lock, flags); |
b417577d AH |
881 | dma_ch = host->dma_ch; |
882 | host->dma_ch = -1; | |
31463b14 | 883 | spin_unlock_irqrestore(&host->irq_lock, flags); |
b417577d AH |
884 | |
885 | if (host->use_dma && dma_ch != -1) { | |
c5c98927 RK |
886 | struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); |
887 | ||
888 | dmaengine_terminate_all(chan); | |
889 | dma_unmap_sg(chan->device->dev, | |
890 | host->data->sg, host->data->sg_len, | |
70a3341a | 891 | omap_hsmmc_get_dma_dir(host, host->data)); |
c5c98927 | 892 | |
053bf34f | 893 | host->data->host_cookie = 0; |
a45c6cb8 MC |
894 | } |
895 | host->data = NULL; | |
a45c6cb8 MC |
896 | } |
897 | ||
898 | /* | |
899 | * Readable error output | |
900 | */ | |
901 | #ifdef CONFIG_MMC_DEBUG | |
699b958b | 902 | static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) |
a45c6cb8 MC |
903 | { |
904 | /* --- means reserved bit without definition at documentation */ | |
70a3341a | 905 | static const char *omap_hsmmc_status_bits[] = { |
699b958b AH |
906 | "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , |
907 | "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", | |
908 | "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , | |
909 | "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" | |
a45c6cb8 MC |
910 | }; |
911 | char res[256]; | |
912 | char *buf = res; | |
913 | int len, i; | |
914 | ||
915 | len = sprintf(buf, "MMC IRQ 0x%x :", status); | |
916 | buf += len; | |
917 | ||
70a3341a | 918 | for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) |
a45c6cb8 | 919 | if (status & (1 << i)) { |
70a3341a | 920 | len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); |
a45c6cb8 MC |
921 | buf += len; |
922 | } | |
923 | ||
8986d31b | 924 | dev_vdbg(mmc_dev(host->mmc), "%s\n", res); |
a45c6cb8 | 925 | } |
699b958b AH |
926 | #else |
927 | static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, | |
928 | u32 status) | |
929 | { | |
930 | } | |
a45c6cb8 MC |
931 | #endif /* CONFIG_MMC_DEBUG */ |
932 | ||
3ebf74b1 JP |
933 | /* |
934 | * MMC controller internal state machines reset | |
935 | * | |
936 | * Used to reset command or data internal state machines, using respectively | |
937 | * SRC or SRD bit of SYSCTL register | |
938 | * Can be called from interrupt context | |
939 | */ | |
70a3341a DK |
940 | static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, |
941 | unsigned long bit) | |
3ebf74b1 JP |
942 | { |
943 | unsigned long i = 0; | |
944 | unsigned long limit = (loops_per_jiffy * | |
945 | msecs_to_jiffies(MMC_TIMEOUT_MS)); | |
946 | ||
947 | OMAP_HSMMC_WRITE(host->base, SYSCTL, | |
948 | OMAP_HSMMC_READ(host->base, SYSCTL) | bit); | |
949 | ||
07ad64b6 MC |
950 | /* |
951 | * OMAP4 ES2 and greater has an updated reset logic. | |
952 | * Monitor a 0->1 transition first | |
953 | */ | |
954 | if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { | |
b432b4b3 | 955 | while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) |
07ad64b6 MC |
956 | && (i++ < limit)) |
957 | cpu_relax(); | |
958 | } | |
959 | i = 0; | |
960 | ||
3ebf74b1 JP |
961 | while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && |
962 | (i++ < limit)) | |
963 | cpu_relax(); | |
964 | ||
965 | if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) | |
966 | dev_err(mmc_dev(host->mmc), | |
967 | "Timeout waiting on controller reset in %s\n", | |
968 | __func__); | |
969 | } | |
a45c6cb8 | 970 | |
ae4bf788 V |
971 | static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, int err) |
972 | { | |
973 | omap_hsmmc_reset_controller_fsm(host, SRC); | |
974 | host->cmd->error = err; | |
975 | ||
976 | if (host->data) { | |
977 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
978 | omap_hsmmc_dma_cleanup(host, err); | |
979 | } | |
980 | ||
981 | } | |
982 | ||
b417577d | 983 | static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) |
a45c6cb8 | 984 | { |
a45c6cb8 | 985 | struct mmc_data *data; |
b417577d AH |
986 | int end_cmd = 0, end_trans = 0; |
987 | ||
a45c6cb8 | 988 | data = host->data; |
8986d31b | 989 | dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); |
a45c6cb8 MC |
990 | |
991 | if (status & ERR) { | |
699b958b | 992 | omap_hsmmc_dbg_report_irq(host, status); |
ae4bf788 V |
993 | if (status & (CMD_TIMEOUT | DATA_TIMEOUT)) |
994 | hsmmc_command_incomplete(host, -ETIMEDOUT); | |
995 | else if (status & (CMD_CRC | DATA_CRC)) | |
996 | hsmmc_command_incomplete(host, -EILSEQ); | |
997 | ||
998 | end_cmd = 1; | |
999 | if (host->data || host->response_busy) { | |
1000 | end_trans = 1; | |
1001 | host->response_busy = 0; | |
a45c6cb8 MC |
1002 | } |
1003 | } | |
1004 | ||
a8fe29d8 | 1005 | if (end_cmd || ((status & CC) && host->cmd)) |
70a3341a | 1006 | omap_hsmmc_cmd_done(host, host->cmd); |
0a40e647 | 1007 | if ((end_trans || (status & TC)) && host->mrq) |
70a3341a | 1008 | omap_hsmmc_xfer_done(host, data); |
b417577d | 1009 | } |
a45c6cb8 | 1010 | |
b417577d AH |
1011 | /* |
1012 | * MMC controller IRQ handler | |
1013 | */ | |
1014 | static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) | |
1015 | { | |
1016 | struct omap_hsmmc_host *host = dev_id; | |
1017 | int status; | |
1018 | ||
1019 | status = OMAP_HSMMC_READ(host->base, STAT); | |
1f6b9fa4 | 1020 | while (status & INT_EN_MASK && host->req_in_progress) { |
b417577d | 1021 | omap_hsmmc_do_irq(host, status); |
1f6b9fa4 | 1022 | |
b417577d | 1023 | /* Flush posted write */ |
1f6b9fa4 | 1024 | OMAP_HSMMC_WRITE(host->base, STAT, status); |
b417577d | 1025 | status = OMAP_HSMMC_READ(host->base, STAT); |
1f6b9fa4 | 1026 | } |
4dffd7a2 | 1027 | |
a45c6cb8 MC |
1028 | return IRQ_HANDLED; |
1029 | } | |
1030 | ||
70a3341a | 1031 | static void set_sd_bus_power(struct omap_hsmmc_host *host) |
e13bb300 AH |
1032 | { |
1033 | unsigned long i; | |
1034 | ||
1035 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
1036 | OMAP_HSMMC_READ(host->base, HCTL) | SDBP); | |
1037 | for (i = 0; i < loops_per_jiffy; i++) { | |
1038 | if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) | |
1039 | break; | |
1040 | cpu_relax(); | |
1041 | } | |
1042 | } | |
1043 | ||
a45c6cb8 | 1044 | /* |
eb250826 DB |
1045 | * Switch MMC interface voltage ... only relevant for MMC1. |
1046 | * | |
1047 | * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. | |
1048 | * The MMC2 transceiver controls are used instead of DAT4..DAT7. | |
1049 | * Some chips, like eMMC ones, use internal transceivers. | |
a45c6cb8 | 1050 | */ |
70a3341a | 1051 | static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) |
a45c6cb8 MC |
1052 | { |
1053 | u32 reg_val = 0; | |
1054 | int ret; | |
1055 | ||
1056 | /* Disable the clocks */ | |
fa4aa2d4 | 1057 | pm_runtime_put_sync(host->dev); |
cd03d9a8 | 1058 | if (host->dbclk) |
94c18149 | 1059 | clk_disable_unprepare(host->dbclk); |
a45c6cb8 MC |
1060 | |
1061 | /* Turn the power off */ | |
1062 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); | |
a45c6cb8 MC |
1063 | |
1064 | /* Turn the power ON with given VDD 1.8 or 3.0v */ | |
2bec0893 AH |
1065 | if (!ret) |
1066 | ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, | |
1067 | vdd); | |
fa4aa2d4 | 1068 | pm_runtime_get_sync(host->dev); |
cd03d9a8 | 1069 | if (host->dbclk) |
94c18149 | 1070 | clk_prepare_enable(host->dbclk); |
2bec0893 | 1071 | |
a45c6cb8 MC |
1072 | if (ret != 0) |
1073 | goto err; | |
1074 | ||
a45c6cb8 MC |
1075 | OMAP_HSMMC_WRITE(host->base, HCTL, |
1076 | OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); | |
1077 | reg_val = OMAP_HSMMC_READ(host->base, HCTL); | |
eb250826 | 1078 | |
a45c6cb8 MC |
1079 | /* |
1080 | * If a MMC dual voltage card is detected, the set_ios fn calls | |
1081 | * this fn with VDD bit set for 1.8V. Upon card removal from the | |
70a3341a | 1082 | * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. |
a45c6cb8 | 1083 | * |
eb250826 DB |
1084 | * Cope with a bit of slop in the range ... per data sheets: |
1085 | * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, | |
1086 | * but recommended values are 1.71V to 1.89V | |
1087 | * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, | |
1088 | * but recommended values are 2.7V to 3.3V | |
1089 | * | |
1090 | * Board setup code shouldn't permit anything very out-of-range. | |
1091 | * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the | |
1092 | * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. | |
a45c6cb8 | 1093 | */ |
eb250826 | 1094 | if ((1 << vdd) <= MMC_VDD_23_24) |
a45c6cb8 | 1095 | reg_val |= SDVS18; |
eb250826 DB |
1096 | else |
1097 | reg_val |= SDVS30; | |
a45c6cb8 MC |
1098 | |
1099 | OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); | |
e13bb300 | 1100 | set_sd_bus_power(host); |
a45c6cb8 MC |
1101 | |
1102 | return 0; | |
1103 | err: | |
1104 | dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); | |
1105 | return ret; | |
1106 | } | |
1107 | ||
b62f6228 AH |
1108 | /* Protect the card while the cover is open */ |
1109 | static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) | |
1110 | { | |
1111 | if (!mmc_slot(host).get_cover_state) | |
1112 | return; | |
1113 | ||
1114 | host->reqs_blocked = 0; | |
1115 | if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { | |
1116 | if (host->protect_card) { | |
2cecdf00 | 1117 | dev_info(host->dev, "%s: cover is closed, " |
b62f6228 AH |
1118 | "card is now accessible\n", |
1119 | mmc_hostname(host->mmc)); | |
1120 | host->protect_card = 0; | |
1121 | } | |
1122 | } else { | |
1123 | if (!host->protect_card) { | |
2cecdf00 | 1124 | dev_info(host->dev, "%s: cover is open, " |
b62f6228 AH |
1125 | "card is now inaccessible\n", |
1126 | mmc_hostname(host->mmc)); | |
1127 | host->protect_card = 1; | |
1128 | } | |
1129 | } | |
1130 | } | |
1131 | ||
a45c6cb8 | 1132 | /* |
7efab4f3 | 1133 | * irq handler to notify the core about card insertion/removal |
a45c6cb8 | 1134 | */ |
7efab4f3 | 1135 | static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) |
a45c6cb8 | 1136 | { |
7efab4f3 | 1137 | struct omap_hsmmc_host *host = dev_id; |
249d0fa9 | 1138 | struct omap_mmc_slot_data *slot = &mmc_slot(host); |
a6b2240d AH |
1139 | int carddetect; |
1140 | ||
1141 | if (host->suspended) | |
7efab4f3 | 1142 | return IRQ_HANDLED; |
a6b2240d AH |
1143 | |
1144 | sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); | |
249d0fa9 | 1145 | |
191d1f1d | 1146 | if (slot->card_detect) |
db0fefc5 | 1147 | carddetect = slot->card_detect(host->dev, host->slot_id); |
b62f6228 AH |
1148 | else { |
1149 | omap_hsmmc_protect_card(host); | |
a6b2240d | 1150 | carddetect = -ENOSYS; |
b62f6228 | 1151 | } |
a45c6cb8 | 1152 | |
cdeebadd | 1153 | if (carddetect) |
a45c6cb8 | 1154 | mmc_detect_change(host->mmc, (HZ * 200) / 1000); |
cdeebadd | 1155 | else |
a45c6cb8 | 1156 | mmc_detect_change(host->mmc, (HZ * 50) / 1000); |
a45c6cb8 MC |
1157 | return IRQ_HANDLED; |
1158 | } | |
1159 | ||
c5c98927 | 1160 | static void omap_hsmmc_dma_callback(void *param) |
a45c6cb8 | 1161 | { |
c5c98927 RK |
1162 | struct omap_hsmmc_host *host = param; |
1163 | struct dma_chan *chan; | |
770d7432 | 1164 | struct mmc_data *data; |
c5c98927 | 1165 | int req_in_progress; |
a45c6cb8 | 1166 | |
c5c98927 | 1167 | spin_lock_irq(&host->irq_lock); |
b417577d | 1168 | if (host->dma_ch < 0) { |
c5c98927 | 1169 | spin_unlock_irq(&host->irq_lock); |
a45c6cb8 | 1170 | return; |
b417577d | 1171 | } |
a45c6cb8 | 1172 | |
770d7432 | 1173 | data = host->mrq->data; |
c5c98927 | 1174 | chan = omap_hsmmc_get_dma_chan(host, data); |
9782aff8 | 1175 | if (!data->host_cookie) |
c5c98927 RK |
1176 | dma_unmap_sg(chan->device->dev, |
1177 | data->sg, data->sg_len, | |
9782aff8 | 1178 | omap_hsmmc_get_dma_dir(host, data)); |
b417577d AH |
1179 | |
1180 | req_in_progress = host->req_in_progress; | |
a45c6cb8 | 1181 | host->dma_ch = -1; |
c5c98927 | 1182 | spin_unlock_irq(&host->irq_lock); |
b417577d AH |
1183 | |
1184 | /* If DMA has finished after TC, complete the request */ | |
1185 | if (!req_in_progress) { | |
1186 | struct mmc_request *mrq = host->mrq; | |
1187 | ||
1188 | host->mrq = NULL; | |
1189 | mmc_request_done(host->mmc, mrq); | |
1190 | } | |
a45c6cb8 MC |
1191 | } |
1192 | ||
9782aff8 PF |
1193 | static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, |
1194 | struct mmc_data *data, | |
c5c98927 | 1195 | struct omap_hsmmc_next *next, |
26b88520 | 1196 | struct dma_chan *chan) |
9782aff8 PF |
1197 | { |
1198 | int dma_len; | |
1199 | ||
1200 | if (!next && data->host_cookie && | |
1201 | data->host_cookie != host->next_data.cookie) { | |
2cecdf00 | 1202 | dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" |
9782aff8 PF |
1203 | " host->next_data.cookie %d\n", |
1204 | __func__, data->host_cookie, host->next_data.cookie); | |
1205 | data->host_cookie = 0; | |
1206 | } | |
1207 | ||
1208 | /* Check if next job is already prepared */ | |
1209 | if (next || | |
1210 | (!next && data->host_cookie != host->next_data.cookie)) { | |
26b88520 | 1211 | dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, |
9782aff8 PF |
1212 | omap_hsmmc_get_dma_dir(host, data)); |
1213 | ||
1214 | } else { | |
1215 | dma_len = host->next_data.dma_len; | |
1216 | host->next_data.dma_len = 0; | |
1217 | } | |
1218 | ||
1219 | ||
1220 | if (dma_len == 0) | |
1221 | return -EINVAL; | |
1222 | ||
1223 | if (next) { | |
1224 | next->dma_len = dma_len; | |
1225 | data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; | |
1226 | } else | |
1227 | host->dma_len = dma_len; | |
1228 | ||
1229 | return 0; | |
1230 | } | |
1231 | ||
a45c6cb8 MC |
1232 | /* |
1233 | * Routine to configure and start DMA for the MMC card | |
1234 | */ | |
70a3341a DK |
1235 | static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, |
1236 | struct mmc_request *req) | |
a45c6cb8 | 1237 | { |
26b88520 RK |
1238 | struct dma_slave_config cfg; |
1239 | struct dma_async_tx_descriptor *tx; | |
1240 | int ret = 0, i; | |
a45c6cb8 | 1241 | struct mmc_data *data = req->data; |
c5c98927 | 1242 | struct dma_chan *chan; |
a45c6cb8 | 1243 | |
0ccd76d4 | 1244 | /* Sanity check: all the SG entries must be aligned by block size. */ |
a3f406f8 | 1245 | for (i = 0; i < data->sg_len; i++) { |
0ccd76d4 JY |
1246 | struct scatterlist *sgl; |
1247 | ||
1248 | sgl = data->sg + i; | |
1249 | if (sgl->length % data->blksz) | |
1250 | return -EINVAL; | |
1251 | } | |
1252 | if ((data->blksz % 4) != 0) | |
1253 | /* REVISIT: The MMC buffer increments only when MSB is written. | |
1254 | * Return error for blksz which is non multiple of four. | |
1255 | */ | |
1256 | return -EINVAL; | |
1257 | ||
b417577d | 1258 | BUG_ON(host->dma_ch != -1); |
a45c6cb8 | 1259 | |
c5c98927 | 1260 | chan = omap_hsmmc_get_dma_chan(host, data); |
c5c98927 | 1261 | |
26b88520 RK |
1262 | cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; |
1263 | cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; | |
1264 | cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1265 | cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | |
1266 | cfg.src_maxburst = data->blksz / 4; | |
1267 | cfg.dst_maxburst = data->blksz / 4; | |
c5c98927 | 1268 | |
26b88520 RK |
1269 | ret = dmaengine_slave_config(chan, &cfg); |
1270 | if (ret) | |
a45c6cb8 | 1271 | return ret; |
c5c98927 | 1272 | |
26b88520 | 1273 | ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); |
9782aff8 PF |
1274 | if (ret) |
1275 | return ret; | |
a45c6cb8 | 1276 | |
26b88520 RK |
1277 | tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, |
1278 | data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, | |
1279 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1280 | if (!tx) { | |
1281 | dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); | |
1282 | /* FIXME: cleanup */ | |
1283 | return -1; | |
1284 | } | |
a45c6cb8 | 1285 | |
26b88520 RK |
1286 | tx->callback = omap_hsmmc_dma_callback; |
1287 | tx->callback_param = host; | |
a45c6cb8 | 1288 | |
26b88520 RK |
1289 | /* Does not fail */ |
1290 | dmaengine_submit(tx); | |
c5c98927 | 1291 | |
26b88520 | 1292 | host->dma_ch = 1; |
c5c98927 | 1293 | |
26b88520 | 1294 | dma_async_issue_pending(chan); |
a45c6cb8 | 1295 | |
a45c6cb8 MC |
1296 | return 0; |
1297 | } | |
1298 | ||
70a3341a | 1299 | static void set_data_timeout(struct omap_hsmmc_host *host, |
e2bf08d6 AH |
1300 | unsigned int timeout_ns, |
1301 | unsigned int timeout_clks) | |
a45c6cb8 MC |
1302 | { |
1303 | unsigned int timeout, cycle_ns; | |
1304 | uint32_t reg, clkd, dto = 0; | |
1305 | ||
1306 | reg = OMAP_HSMMC_READ(host->base, SYSCTL); | |
1307 | clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; | |
1308 | if (clkd == 0) | |
1309 | clkd = 1; | |
1310 | ||
1311 | cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); | |
e2bf08d6 AH |
1312 | timeout = timeout_ns / cycle_ns; |
1313 | timeout += timeout_clks; | |
a45c6cb8 MC |
1314 | if (timeout) { |
1315 | while ((timeout & 0x80000000) == 0) { | |
1316 | dto += 1; | |
1317 | timeout <<= 1; | |
1318 | } | |
1319 | dto = 31 - dto; | |
1320 | timeout <<= 1; | |
1321 | if (timeout && dto) | |
1322 | dto += 1; | |
1323 | if (dto >= 13) | |
1324 | dto -= 13; | |
1325 | else | |
1326 | dto = 0; | |
1327 | if (dto > 14) | |
1328 | dto = 14; | |
1329 | } | |
1330 | ||
1331 | reg &= ~DTO_MASK; | |
1332 | reg |= dto << DTO_SHIFT; | |
1333 | OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); | |
1334 | } | |
1335 | ||
1336 | /* | |
1337 | * Configure block length for MMC/SD cards and initiate the transfer. | |
1338 | */ | |
1339 | static int | |
70a3341a | 1340 | omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) |
a45c6cb8 MC |
1341 | { |
1342 | int ret; | |
1343 | host->data = req->data; | |
1344 | ||
1345 | if (req->data == NULL) { | |
a45c6cb8 | 1346 | OMAP_HSMMC_WRITE(host->base, BLK, 0); |
e2bf08d6 AH |
1347 | /* |
1348 | * Set an arbitrary 100ms data timeout for commands with | |
1349 | * busy signal. | |
1350 | */ | |
1351 | if (req->cmd->flags & MMC_RSP_BUSY) | |
1352 | set_data_timeout(host, 100000000U, 0); | |
a45c6cb8 MC |
1353 | return 0; |
1354 | } | |
1355 | ||
1356 | OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) | |
1357 | | (req->data->blocks << 16)); | |
e2bf08d6 | 1358 | set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); |
a45c6cb8 | 1359 | |
a45c6cb8 | 1360 | if (host->use_dma) { |
70a3341a | 1361 | ret = omap_hsmmc_start_dma_transfer(host, req); |
a45c6cb8 MC |
1362 | if (ret != 0) { |
1363 | dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); | |
1364 | return ret; | |
1365 | } | |
1366 | } | |
1367 | return 0; | |
1368 | } | |
1369 | ||
9782aff8 PF |
1370 | static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
1371 | int err) | |
1372 | { | |
1373 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1374 | struct mmc_data *data = mrq->data; | |
1375 | ||
26b88520 | 1376 | if (host->use_dma && data->host_cookie) { |
c5c98927 | 1377 | struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); |
c5c98927 | 1378 | |
26b88520 RK |
1379 | dma_unmap_sg(c->device->dev, data->sg, data->sg_len, |
1380 | omap_hsmmc_get_dma_dir(host, data)); | |
9782aff8 PF |
1381 | data->host_cookie = 0; |
1382 | } | |
1383 | } | |
1384 | ||
1385 | static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, | |
1386 | bool is_first_req) | |
1387 | { | |
1388 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1389 | ||
1390 | if (mrq->data->host_cookie) { | |
1391 | mrq->data->host_cookie = 0; | |
1392 | return ; | |
1393 | } | |
1394 | ||
c5c98927 RK |
1395 | if (host->use_dma) { |
1396 | struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); | |
c5c98927 | 1397 | |
9782aff8 | 1398 | if (omap_hsmmc_pre_dma_transfer(host, mrq->data, |
26b88520 | 1399 | &host->next_data, c)) |
9782aff8 | 1400 | mrq->data->host_cookie = 0; |
c5c98927 | 1401 | } |
9782aff8 PF |
1402 | } |
1403 | ||
a45c6cb8 MC |
1404 | /* |
1405 | * Request function. for read/write operation | |
1406 | */ | |
70a3341a | 1407 | static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) |
a45c6cb8 | 1408 | { |
70a3341a | 1409 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3f406f8 | 1410 | int err; |
a45c6cb8 | 1411 | |
b417577d AH |
1412 | BUG_ON(host->req_in_progress); |
1413 | BUG_ON(host->dma_ch != -1); | |
1414 | if (host->protect_card) { | |
1415 | if (host->reqs_blocked < 3) { | |
1416 | /* | |
1417 | * Ensure the controller is left in a consistent | |
1418 | * state by resetting the command and data state | |
1419 | * machines. | |
1420 | */ | |
1421 | omap_hsmmc_reset_controller_fsm(host, SRD); | |
1422 | omap_hsmmc_reset_controller_fsm(host, SRC); | |
1423 | host->reqs_blocked += 1; | |
1424 | } | |
1425 | req->cmd->error = -EBADF; | |
1426 | if (req->data) | |
1427 | req->data->error = -EBADF; | |
1428 | req->cmd->retries = 0; | |
1429 | mmc_request_done(mmc, req); | |
1430 | return; | |
1431 | } else if (host->reqs_blocked) | |
1432 | host->reqs_blocked = 0; | |
a45c6cb8 MC |
1433 | WARN_ON(host->mrq != NULL); |
1434 | host->mrq = req; | |
70a3341a | 1435 | err = omap_hsmmc_prepare_data(host, req); |
a3f406f8 JL |
1436 | if (err) { |
1437 | req->cmd->error = err; | |
1438 | if (req->data) | |
1439 | req->data->error = err; | |
1440 | host->mrq = NULL; | |
1441 | mmc_request_done(mmc, req); | |
1442 | return; | |
1443 | } | |
1444 | ||
70a3341a | 1445 | omap_hsmmc_start_command(host, req->cmd, req->data); |
a45c6cb8 MC |
1446 | } |
1447 | ||
a45c6cb8 | 1448 | /* Routine to configure clock values. Exposed API to core */ |
70a3341a | 1449 | static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
a45c6cb8 | 1450 | { |
70a3341a | 1451 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a3621465 | 1452 | int do_send_init_stream = 0; |
a45c6cb8 | 1453 | |
fa4aa2d4 | 1454 | pm_runtime_get_sync(host->dev); |
5e2ea617 | 1455 | |
a3621465 AH |
1456 | if (ios->power_mode != host->power_mode) { |
1457 | switch (ios->power_mode) { | |
1458 | case MMC_POWER_OFF: | |
1459 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1460 | 0, 0); | |
1461 | break; | |
1462 | case MMC_POWER_UP: | |
1463 | mmc_slot(host).set_power(host->dev, host->slot_id, | |
1464 | 1, ios->vdd); | |
1465 | break; | |
1466 | case MMC_POWER_ON: | |
1467 | do_send_init_stream = 1; | |
1468 | break; | |
1469 | } | |
1470 | host->power_mode = ios->power_mode; | |
a45c6cb8 MC |
1471 | } |
1472 | ||
dd498eff DK |
1473 | /* FIXME: set registers based only on changes to ios */ |
1474 | ||
3796fb8a | 1475 | omap_hsmmc_set_bus_width(host); |
a45c6cb8 | 1476 | |
4621d5f8 | 1477 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
eb250826 DB |
1478 | /* Only MMC1 can interface at 3V without some flavor |
1479 | * of external transceiver; but they all handle 1.8V. | |
1480 | */ | |
a45c6cb8 | 1481 | if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && |
1f84b71b RN |
1482 | (ios->vdd == DUAL_VOLT_OCR_BIT) && |
1483 | /* | |
1484 | * With pbias cell programming missing, this | |
1485 | * can't be allowed when booting with device | |
1486 | * tree. | |
1487 | */ | |
4d048f91 | 1488 | !host->dev->of_node) { |
a45c6cb8 MC |
1489 | /* |
1490 | * The mmc_select_voltage fn of the core does | |
1491 | * not seem to set the power_mode to | |
1492 | * MMC_POWER_UP upon recalculating the voltage. | |
1493 | * vdd 1.8v. | |
1494 | */ | |
70a3341a DK |
1495 | if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) |
1496 | dev_dbg(mmc_dev(host->mmc), | |
a45c6cb8 MC |
1497 | "Switch operation failed\n"); |
1498 | } | |
1499 | } | |
1500 | ||
5934df2f | 1501 | omap_hsmmc_set_clock(host); |
a45c6cb8 | 1502 | |
a3621465 | 1503 | if (do_send_init_stream) |
a45c6cb8 MC |
1504 | send_init_stream(host); |
1505 | ||
3796fb8a | 1506 | omap_hsmmc_set_bus_mode(host); |
5e2ea617 | 1507 | |
fa4aa2d4 | 1508 | pm_runtime_put_autosuspend(host->dev); |
a45c6cb8 MC |
1509 | } |
1510 | ||
1511 | static int omap_hsmmc_get_cd(struct mmc_host *mmc) | |
1512 | { | |
70a3341a | 1513 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1514 | |
191d1f1d | 1515 | if (!mmc_slot(host).card_detect) |
a45c6cb8 | 1516 | return -ENOSYS; |
db0fefc5 | 1517 | return mmc_slot(host).card_detect(host->dev, host->slot_id); |
a45c6cb8 MC |
1518 | } |
1519 | ||
1520 | static int omap_hsmmc_get_ro(struct mmc_host *mmc) | |
1521 | { | |
70a3341a | 1522 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
a45c6cb8 | 1523 | |
191d1f1d | 1524 | if (!mmc_slot(host).get_ro) |
a45c6cb8 | 1525 | return -ENOSYS; |
191d1f1d | 1526 | return mmc_slot(host).get_ro(host->dev, 0); |
a45c6cb8 MC |
1527 | } |
1528 | ||
4816858c GI |
1529 | static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) |
1530 | { | |
1531 | struct omap_hsmmc_host *host = mmc_priv(mmc); | |
1532 | ||
1533 | if (mmc_slot(host).init_card) | |
1534 | mmc_slot(host).init_card(card); | |
1535 | } | |
1536 | ||
70a3341a | 1537 | static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) |
1b331e69 KK |
1538 | { |
1539 | u32 hctl, capa, value; | |
1540 | ||
1541 | /* Only MMC1 supports 3.0V */ | |
4621d5f8 | 1542 | if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { |
1b331e69 KK |
1543 | hctl = SDVS30; |
1544 | capa = VS30 | VS18; | |
1545 | } else { | |
1546 | hctl = SDVS18; | |
1547 | capa = VS18; | |
1548 | } | |
1549 | ||
1550 | value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; | |
1551 | OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); | |
1552 | ||
1553 | value = OMAP_HSMMC_READ(host->base, CAPA); | |
1554 | OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); | |
1555 | ||
1b331e69 | 1556 | /* Set SD bus power bit */ |
e13bb300 | 1557 | set_sd_bus_power(host); |
1b331e69 KK |
1558 | } |
1559 | ||
70a3341a | 1560 | static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) |
dd498eff | 1561 | { |
70a3341a | 1562 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1563 | |
fa4aa2d4 B |
1564 | pm_runtime_get_sync(host->dev); |
1565 | ||
dd498eff DK |
1566 | return 0; |
1567 | } | |
1568 | ||
907d2e7c | 1569 | static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) |
dd498eff | 1570 | { |
70a3341a | 1571 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
dd498eff | 1572 | |
fa4aa2d4 B |
1573 | pm_runtime_mark_last_busy(host->dev); |
1574 | pm_runtime_put_autosuspend(host->dev); | |
1575 | ||
dd498eff DK |
1576 | return 0; |
1577 | } | |
1578 | ||
70a3341a DK |
1579 | static const struct mmc_host_ops omap_hsmmc_ops = { |
1580 | .enable = omap_hsmmc_enable_fclk, | |
1581 | .disable = omap_hsmmc_disable_fclk, | |
9782aff8 PF |
1582 | .post_req = omap_hsmmc_post_req, |
1583 | .pre_req = omap_hsmmc_pre_req, | |
70a3341a DK |
1584 | .request = omap_hsmmc_request, |
1585 | .set_ios = omap_hsmmc_set_ios, | |
dd498eff DK |
1586 | .get_cd = omap_hsmmc_get_cd, |
1587 | .get_ro = omap_hsmmc_get_ro, | |
4816858c | 1588 | .init_card = omap_hsmmc_init_card, |
dd498eff DK |
1589 | /* NYET -- enable_sdio_irq */ |
1590 | }; | |
1591 | ||
d900f712 DK |
1592 | #ifdef CONFIG_DEBUG_FS |
1593 | ||
70a3341a | 1594 | static int omap_hsmmc_regs_show(struct seq_file *s, void *data) |
d900f712 DK |
1595 | { |
1596 | struct mmc_host *mmc = s->private; | |
70a3341a | 1597 | struct omap_hsmmc_host *host = mmc_priv(mmc); |
11dd62a7 DK |
1598 | int context_loss = 0; |
1599 | ||
70a3341a DK |
1600 | if (host->pdata->get_context_loss_count) |
1601 | context_loss = host->pdata->get_context_loss_count(host->dev); | |
d900f712 | 1602 | |
907d2e7c AH |
1603 | seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n", |
1604 | mmc->index, host->context_loss, context_loss); | |
5e2ea617 | 1605 | |
7a8c2cef | 1606 | if (host->suspended) { |
dd498eff DK |
1607 | seq_printf(s, "host suspended, can't read registers\n"); |
1608 | return 0; | |
1609 | } | |
1610 | ||
fa4aa2d4 | 1611 | pm_runtime_get_sync(host->dev); |
d900f712 | 1612 | |
d900f712 DK |
1613 | seq_printf(s, "CON:\t\t0x%08x\n", |
1614 | OMAP_HSMMC_READ(host->base, CON)); | |
1615 | seq_printf(s, "HCTL:\t\t0x%08x\n", | |
1616 | OMAP_HSMMC_READ(host->base, HCTL)); | |
1617 | seq_printf(s, "SYSCTL:\t\t0x%08x\n", | |
1618 | OMAP_HSMMC_READ(host->base, SYSCTL)); | |
1619 | seq_printf(s, "IE:\t\t0x%08x\n", | |
1620 | OMAP_HSMMC_READ(host->base, IE)); | |
1621 | seq_printf(s, "ISE:\t\t0x%08x\n", | |
1622 | OMAP_HSMMC_READ(host->base, ISE)); | |
1623 | seq_printf(s, "CAPA:\t\t0x%08x\n", | |
1624 | OMAP_HSMMC_READ(host->base, CAPA)); | |
5e2ea617 | 1625 | |
fa4aa2d4 B |
1626 | pm_runtime_mark_last_busy(host->dev); |
1627 | pm_runtime_put_autosuspend(host->dev); | |
dd498eff | 1628 | |
d900f712 DK |
1629 | return 0; |
1630 | } | |
1631 | ||
70a3341a | 1632 | static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) |
d900f712 | 1633 | { |
70a3341a | 1634 | return single_open(file, omap_hsmmc_regs_show, inode->i_private); |
d900f712 DK |
1635 | } |
1636 | ||
1637 | static const struct file_operations mmc_regs_fops = { | |
70a3341a | 1638 | .open = omap_hsmmc_regs_open, |
d900f712 DK |
1639 | .read = seq_read, |
1640 | .llseek = seq_lseek, | |
1641 | .release = single_release, | |
1642 | }; | |
1643 | ||
70a3341a | 1644 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1645 | { |
1646 | if (mmc->debugfs_root) | |
1647 | debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, | |
1648 | mmc, &mmc_regs_fops); | |
1649 | } | |
1650 | ||
1651 | #else | |
1652 | ||
70a3341a | 1653 | static void omap_hsmmc_debugfs(struct mmc_host *mmc) |
d900f712 DK |
1654 | { |
1655 | } | |
1656 | ||
1657 | #endif | |
1658 | ||
46856a68 RN |
1659 | #ifdef CONFIG_OF |
1660 | static u16 omap4_reg_offset = 0x100; | |
1661 | ||
1662 | static const struct of_device_id omap_mmc_of_match[] = { | |
1663 | { | |
1664 | .compatible = "ti,omap2-hsmmc", | |
1665 | }, | |
1666 | { | |
1667 | .compatible = "ti,omap3-hsmmc", | |
1668 | }, | |
1669 | { | |
1670 | .compatible = "ti,omap4-hsmmc", | |
1671 | .data = &omap4_reg_offset, | |
1672 | }, | |
1673 | {}, | |
b6d085f6 | 1674 | }; |
46856a68 RN |
1675 | MODULE_DEVICE_TABLE(of, omap_mmc_of_match); |
1676 | ||
1677 | static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) | |
1678 | { | |
1679 | struct omap_mmc_platform_data *pdata; | |
1680 | struct device_node *np = dev->of_node; | |
1681 | u32 bus_width; | |
1682 | ||
1683 | pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); | |
1684 | if (!pdata) | |
1685 | return NULL; /* out of memory */ | |
1686 | ||
1687 | if (of_find_property(np, "ti,dual-volt", NULL)) | |
1688 | pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; | |
1689 | ||
1690 | /* This driver only supports 1 slot */ | |
1691 | pdata->nr_slots = 1; | |
1692 | pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0); | |
1693 | pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); | |
1694 | ||
1695 | if (of_find_property(np, "ti,non-removable", NULL)) { | |
1696 | pdata->slots[0].nonremovable = true; | |
1697 | pdata->slots[0].no_regulator_off_init = true; | |
1698 | } | |
7f217794 | 1699 | of_property_read_u32(np, "bus-width", &bus_width); |
46856a68 RN |
1700 | if (bus_width == 4) |
1701 | pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; | |
1702 | else if (bus_width == 8) | |
1703 | pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; | |
1704 | ||
1705 | if (of_find_property(np, "ti,needs-special-reset", NULL)) | |
1706 | pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; | |
1707 | ||
1708 | return pdata; | |
1709 | } | |
1710 | #else | |
1711 | static inline struct omap_mmc_platform_data | |
1712 | *of_get_hsmmc_pdata(struct device *dev) | |
1713 | { | |
1714 | return NULL; | |
1715 | } | |
1716 | #endif | |
1717 | ||
efa25fd3 | 1718 | static int __devinit omap_hsmmc_probe(struct platform_device *pdev) |
a45c6cb8 MC |
1719 | { |
1720 | struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; | |
1721 | struct mmc_host *mmc; | |
70a3341a | 1722 | struct omap_hsmmc_host *host = NULL; |
a45c6cb8 | 1723 | struct resource *res; |
db0fefc5 | 1724 | int ret, irq; |
46856a68 | 1725 | const struct of_device_id *match; |
26b88520 RK |
1726 | dma_cap_mask_t mask; |
1727 | unsigned tx_req, rx_req; | |
46856a68 RN |
1728 | |
1729 | match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); | |
1730 | if (match) { | |
1731 | pdata = of_get_hsmmc_pdata(&pdev->dev); | |
1732 | if (match->data) { | |
efc9b736 | 1733 | const u16 *offsetp = match->data; |
46856a68 RN |
1734 | pdata->reg_offset = *offsetp; |
1735 | } | |
1736 | } | |
a45c6cb8 MC |
1737 | |
1738 | if (pdata == NULL) { | |
1739 | dev_err(&pdev->dev, "Platform Data is missing\n"); | |
1740 | return -ENXIO; | |
1741 | } | |
1742 | ||
1743 | if (pdata->nr_slots == 0) { | |
1744 | dev_err(&pdev->dev, "No Slots\n"); | |
1745 | return -ENXIO; | |
1746 | } | |
1747 | ||
1748 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1749 | irq = platform_get_irq(pdev, 0); | |
1750 | if (res == NULL || irq < 0) | |
1751 | return -ENXIO; | |
1752 | ||
984b203a | 1753 | res = request_mem_region(res->start, resource_size(res), pdev->name); |
a45c6cb8 MC |
1754 | if (res == NULL) |
1755 | return -EBUSY; | |
1756 | ||
db0fefc5 AH |
1757 | ret = omap_hsmmc_gpio_init(pdata); |
1758 | if (ret) | |
1759 | goto err; | |
1760 | ||
70a3341a | 1761 | mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); |
a45c6cb8 MC |
1762 | if (!mmc) { |
1763 | ret = -ENOMEM; | |
db0fefc5 | 1764 | goto err_alloc; |
a45c6cb8 MC |
1765 | } |
1766 | ||
1767 | host = mmc_priv(mmc); | |
1768 | host->mmc = mmc; | |
1769 | host->pdata = pdata; | |
1770 | host->dev = &pdev->dev; | |
1771 | host->use_dma = 1; | |
a45c6cb8 MC |
1772 | host->dma_ch = -1; |
1773 | host->irq = irq; | |
a45c6cb8 | 1774 | host->slot_id = 0; |
fc307df8 | 1775 | host->mapbase = res->start + pdata->reg_offset; |
a45c6cb8 | 1776 | host->base = ioremap(host->mapbase, SZ_4K); |
6da20c89 | 1777 | host->power_mode = MMC_POWER_OFF; |
9782aff8 | 1778 | host->next_data.cookie = 1; |
a45c6cb8 MC |
1779 | |
1780 | platform_set_drvdata(pdev, host); | |
a45c6cb8 | 1781 | |
7a8c2cef | 1782 | mmc->ops = &omap_hsmmc_ops; |
dd498eff | 1783 | |
e0eb2424 AH |
1784 | /* |
1785 | * If regulator_disable can only put vcc_aux to sleep then there is | |
1786 | * no off state. | |
1787 | */ | |
1788 | if (mmc_slot(host).vcc_aux_disable_is_sleep) | |
1789 | mmc_slot(host).no_off = 1; | |
1790 | ||
d418ed87 DM |
1791 | mmc->f_min = OMAP_MMC_MIN_CLOCK; |
1792 | ||
1793 | if (pdata->max_freq > 0) | |
1794 | mmc->f_max = pdata->max_freq; | |
1795 | else | |
1796 | mmc->f_max = OMAP_MMC_MAX_CLOCK; | |
a45c6cb8 | 1797 | |
4dffd7a2 | 1798 | spin_lock_init(&host->irq_lock); |
a45c6cb8 | 1799 | |
6f7607cc | 1800 | host->fclk = clk_get(&pdev->dev, "fck"); |
a45c6cb8 MC |
1801 | if (IS_ERR(host->fclk)) { |
1802 | ret = PTR_ERR(host->fclk); | |
1803 | host->fclk = NULL; | |
a45c6cb8 MC |
1804 | goto err1; |
1805 | } | |
1806 | ||
9b68256c PW |
1807 | if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { |
1808 | dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); | |
1809 | mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; | |
1810 | } | |
dd498eff | 1811 | |
fa4aa2d4 B |
1812 | pm_runtime_enable(host->dev); |
1813 | pm_runtime_get_sync(host->dev); | |
1814 | pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); | |
1815 | pm_runtime_use_autosuspend(host->dev); | |
a45c6cb8 | 1816 | |
92a3aebf B |
1817 | omap_hsmmc_context_save(host); |
1818 | ||
cd03d9a8 RN |
1819 | host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); |
1820 | /* | |
1821 | * MMC can still work without debounce clock. | |
1822 | */ | |
1823 | if (IS_ERR(host->dbclk)) { | |
1824 | dev_warn(mmc_dev(host->mmc), "Failed to get debounce clk\n"); | |
1825 | host->dbclk = NULL; | |
94c18149 | 1826 | } else if (clk_prepare_enable(host->dbclk) != 0) { |
cd03d9a8 RN |
1827 | dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); |
1828 | clk_put(host->dbclk); | |
1829 | host->dbclk = NULL; | |
2bec0893 | 1830 | } |
a45c6cb8 | 1831 | |
0ccd76d4 JY |
1832 | /* Since we do only SG emulation, we can have as many segs |
1833 | * as we want. */ | |
a36274e0 | 1834 | mmc->max_segs = 1024; |
0ccd76d4 | 1835 | |
a45c6cb8 MC |
1836 | mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ |
1837 | mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ | |
1838 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; | |
1839 | mmc->max_seg_size = mmc->max_req_size; | |
1840 | ||
13189e78 | 1841 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | |
93caf8e6 | 1842 | MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; |
a45c6cb8 | 1843 | |
3a63833e SG |
1844 | mmc->caps |= mmc_slot(host).caps; |
1845 | if (mmc->caps & MMC_CAP_8_BIT_DATA) | |
a45c6cb8 MC |
1846 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
1847 | ||
191d1f1d | 1848 | if (mmc_slot(host).nonremovable) |
23d99bb9 AH |
1849 | mmc->caps |= MMC_CAP_NONREMOVABLE; |
1850 | ||
6fdc75de EP |
1851 | mmc->pm_caps = mmc_slot(host).pm_caps; |
1852 | ||
70a3341a | 1853 | omap_hsmmc_conf_bus_power(host); |
a45c6cb8 | 1854 | |
b7bf773b B |
1855 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); |
1856 | if (!res) { | |
1857 | dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); | |
9c17d08c | 1858 | ret = -ENXIO; |
b7bf773b B |
1859 | goto err_irq; |
1860 | } | |
26b88520 | 1861 | tx_req = res->start; |
b7bf773b B |
1862 | |
1863 | res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); | |
1864 | if (!res) { | |
1865 | dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); | |
9c17d08c | 1866 | ret = -ENXIO; |
f3e2f1dd GI |
1867 | goto err_irq; |
1868 | } | |
26b88520 | 1869 | rx_req = res->start; |
a45c6cb8 | 1870 | |
26b88520 RK |
1871 | dma_cap_zero(mask); |
1872 | dma_cap_set(DMA_SLAVE, mask); | |
1873 | ||
1874 | host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req); | |
1875 | if (!host->rx_chan) { | |
1876 | dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); | |
04e8c7bc | 1877 | ret = -ENXIO; |
26b88520 RK |
1878 | goto err_irq; |
1879 | } | |
1880 | ||
1881 | host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req); | |
1882 | if (!host->tx_chan) { | |
1883 | dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); | |
04e8c7bc | 1884 | ret = -ENXIO; |
26b88520 | 1885 | goto err_irq; |
c5c98927 | 1886 | } |
a45c6cb8 MC |
1887 | |
1888 | /* Request IRQ for MMC operations */ | |
d9618e9f | 1889 | ret = request_irq(host->irq, omap_hsmmc_irq, 0, |
a45c6cb8 MC |
1890 | mmc_hostname(mmc), host); |
1891 | if (ret) { | |
1892 | dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); | |
1893 | goto err_irq; | |
1894 | } | |
1895 | ||
1896 | if (pdata->init != NULL) { | |
1897 | if (pdata->init(&pdev->dev) != 0) { | |
70a3341a DK |
1898 | dev_dbg(mmc_dev(host->mmc), |
1899 | "Unable to configure MMC IRQs\n"); | |
a45c6cb8 MC |
1900 | goto err_irq_cd_init; |
1901 | } | |
1902 | } | |
db0fefc5 | 1903 | |
b702b106 | 1904 | if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { |
db0fefc5 AH |
1905 | ret = omap_hsmmc_reg_get(host); |
1906 | if (ret) | |
1907 | goto err_reg; | |
1908 | host->use_reg = 1; | |
1909 | } | |
1910 | ||
b583f26d | 1911 | mmc->ocr_avail = mmc_slot(host).ocr_mask; |
a45c6cb8 MC |
1912 | |
1913 | /* Request IRQ for card detect */ | |
e1a55f5e | 1914 | if ((mmc_slot(host).card_detect_irq)) { |
7efab4f3 N |
1915 | ret = request_threaded_irq(mmc_slot(host).card_detect_irq, |
1916 | NULL, | |
1917 | omap_hsmmc_detect, | |
db35f83e | 1918 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, |
7efab4f3 | 1919 | mmc_hostname(mmc), host); |
a45c6cb8 MC |
1920 | if (ret) { |
1921 | dev_dbg(mmc_dev(host->mmc), | |
1922 | "Unable to grab MMC CD IRQ\n"); | |
1923 | goto err_irq_cd; | |
1924 | } | |
72f2e2c7 | 1925 | pdata->suspend = omap_hsmmc_suspend_cdirq; |
1926 | pdata->resume = omap_hsmmc_resume_cdirq; | |
a45c6cb8 MC |
1927 | } |
1928 | ||
b417577d | 1929 | omap_hsmmc_disable_irq(host); |
a45c6cb8 | 1930 | |
b62f6228 AH |
1931 | omap_hsmmc_protect_card(host); |
1932 | ||
a45c6cb8 MC |
1933 | mmc_add_host(mmc); |
1934 | ||
191d1f1d | 1935 | if (mmc_slot(host).name != NULL) { |
a45c6cb8 MC |
1936 | ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); |
1937 | if (ret < 0) | |
1938 | goto err_slot_name; | |
1939 | } | |
191d1f1d | 1940 | if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { |
a45c6cb8 MC |
1941 | ret = device_create_file(&mmc->class_dev, |
1942 | &dev_attr_cover_switch); | |
1943 | if (ret < 0) | |
db0fefc5 | 1944 | goto err_slot_name; |
a45c6cb8 MC |
1945 | } |
1946 | ||
70a3341a | 1947 | omap_hsmmc_debugfs(mmc); |
fa4aa2d4 B |
1948 | pm_runtime_mark_last_busy(host->dev); |
1949 | pm_runtime_put_autosuspend(host->dev); | |
d900f712 | 1950 | |
a45c6cb8 MC |
1951 | return 0; |
1952 | ||
a45c6cb8 MC |
1953 | err_slot_name: |
1954 | mmc_remove_host(mmc); | |
a45c6cb8 | 1955 | free_irq(mmc_slot(host).card_detect_irq, host); |
db0fefc5 AH |
1956 | err_irq_cd: |
1957 | if (host->use_reg) | |
1958 | omap_hsmmc_reg_put(host); | |
1959 | err_reg: | |
1960 | if (host->pdata->cleanup) | |
1961 | host->pdata->cleanup(&pdev->dev); | |
a45c6cb8 MC |
1962 | err_irq_cd_init: |
1963 | free_irq(host->irq, host); | |
1964 | err_irq: | |
c5c98927 RK |
1965 | if (host->tx_chan) |
1966 | dma_release_channel(host->tx_chan); | |
1967 | if (host->rx_chan) | |
1968 | dma_release_channel(host->rx_chan); | |
d59d77ed | 1969 | pm_runtime_put_sync(host->dev); |
37f6190d | 1970 | pm_runtime_disable(host->dev); |
a45c6cb8 | 1971 | clk_put(host->fclk); |
cd03d9a8 | 1972 | if (host->dbclk) { |
94c18149 | 1973 | clk_disable_unprepare(host->dbclk); |
a45c6cb8 MC |
1974 | clk_put(host->dbclk); |
1975 | } | |
a45c6cb8 MC |
1976 | err1: |
1977 | iounmap(host->base); | |
db0fefc5 AH |
1978 | platform_set_drvdata(pdev, NULL); |
1979 | mmc_free_host(mmc); | |
1980 | err_alloc: | |
1981 | omap_hsmmc_gpio_free(pdata); | |
a45c6cb8 | 1982 | err: |
48b332f9 RK |
1983 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1984 | if (res) | |
1985 | release_mem_region(res->start, resource_size(res)); | |
a45c6cb8 MC |
1986 | return ret; |
1987 | } | |
1988 | ||
efa25fd3 | 1989 | static int __devexit omap_hsmmc_remove(struct platform_device *pdev) |
a45c6cb8 | 1990 | { |
70a3341a | 1991 | struct omap_hsmmc_host *host = platform_get_drvdata(pdev); |
a45c6cb8 MC |
1992 | struct resource *res; |
1993 | ||
927ce944 FB |
1994 | pm_runtime_get_sync(host->dev); |
1995 | mmc_remove_host(host->mmc); | |
1996 | if (host->use_reg) | |
1997 | omap_hsmmc_reg_put(host); | |
1998 | if (host->pdata->cleanup) | |
1999 | host->pdata->cleanup(&pdev->dev); | |
2000 | free_irq(host->irq, host); | |
2001 | if (mmc_slot(host).card_detect_irq) | |
2002 | free_irq(mmc_slot(host).card_detect_irq, host); | |
a45c6cb8 | 2003 | |
c5c98927 RK |
2004 | if (host->tx_chan) |
2005 | dma_release_channel(host->tx_chan); | |
2006 | if (host->rx_chan) | |
2007 | dma_release_channel(host->rx_chan); | |
2008 | ||
927ce944 FB |
2009 | pm_runtime_put_sync(host->dev); |
2010 | pm_runtime_disable(host->dev); | |
2011 | clk_put(host->fclk); | |
cd03d9a8 | 2012 | if (host->dbclk) { |
94c18149 | 2013 | clk_disable_unprepare(host->dbclk); |
927ce944 | 2014 | clk_put(host->dbclk); |
a45c6cb8 MC |
2015 | } |
2016 | ||
9ea28ecb | 2017 | omap_hsmmc_gpio_free(host->pdata); |
927ce944 | 2018 | iounmap(host->base); |
9d1f0286 | 2019 | mmc_free_host(host->mmc); |
927ce944 | 2020 | |
a45c6cb8 MC |
2021 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
2022 | if (res) | |
984b203a | 2023 | release_mem_region(res->start, resource_size(res)); |
a45c6cb8 MC |
2024 | platform_set_drvdata(pdev, NULL); |
2025 | ||
2026 | return 0; | |
2027 | } | |
2028 | ||
2029 | #ifdef CONFIG_PM | |
a791daa1 | 2030 | static int omap_hsmmc_suspend(struct device *dev) |
a45c6cb8 MC |
2031 | { |
2032 | int ret = 0; | |
927ce944 | 2033 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
a45c6cb8 | 2034 | |
927ce944 | 2035 | if (!host) |
a45c6cb8 MC |
2036 | return 0; |
2037 | ||
927ce944 FB |
2038 | if (host && host->suspended) |
2039 | return 0; | |
fa4aa2d4 | 2040 | |
927ce944 FB |
2041 | pm_runtime_get_sync(host->dev); |
2042 | host->suspended = 1; | |
2043 | if (host->pdata->suspend) { | |
2044 | ret = host->pdata->suspend(dev, host->slot_id); | |
31f9d463 | 2045 | if (ret) { |
927ce944 FB |
2046 | dev_dbg(dev, "Unable to handle MMC board" |
2047 | " level suspend\n"); | |
a6b2240d | 2048 | host->suspended = 0; |
927ce944 | 2049 | return ret; |
a6b2240d | 2050 | } |
927ce944 FB |
2051 | } |
2052 | ret = mmc_suspend_host(host->mmc); | |
31f9d463 | 2053 | |
927ce944 FB |
2054 | if (ret) { |
2055 | host->suspended = 0; | |
2056 | if (host->pdata->resume) { | |
c4c8eeb4 | 2057 | if (host->pdata->resume(dev, host->slot_id)) |
927ce944 | 2058 | dev_dbg(dev, "Unmask interrupt failed\n"); |
31f9d463 | 2059 | } |
927ce944 FB |
2060 | goto err; |
2061 | } | |
31f9d463 | 2062 | |
927ce944 FB |
2063 | if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { |
2064 | omap_hsmmc_disable_irq(host); | |
2065 | OMAP_HSMMC_WRITE(host->base, HCTL, | |
2066 | OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); | |
a45c6cb8 | 2067 | } |
927ce944 | 2068 | |
cd03d9a8 | 2069 | if (host->dbclk) |
94c18149 | 2070 | clk_disable_unprepare(host->dbclk); |
31f9d463 EP |
2071 | err: |
2072 | pm_runtime_put_sync(host->dev); | |
a45c6cb8 MC |
2073 | return ret; |
2074 | } | |
2075 | ||
2076 | /* Routine to resume the MMC device */ | |
a791daa1 | 2077 | static int omap_hsmmc_resume(struct device *dev) |
a45c6cb8 MC |
2078 | { |
2079 | int ret = 0; | |
927ce944 FB |
2080 | struct omap_hsmmc_host *host = dev_get_drvdata(dev); |
2081 | ||
2082 | if (!host) | |
2083 | return 0; | |
a45c6cb8 MC |
2084 | |
2085 | if (host && !host->suspended) | |
2086 | return 0; | |
2087 | ||
927ce944 | 2088 | pm_runtime_get_sync(host->dev); |
11dd62a7 | 2089 | |
cd03d9a8 | 2090 | if (host->dbclk) |
94c18149 | 2091 | clk_prepare_enable(host->dbclk); |
2bec0893 | 2092 | |
927ce944 FB |
2093 | if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) |
2094 | omap_hsmmc_conf_bus_power(host); | |
1b331e69 | 2095 | |
927ce944 FB |
2096 | if (host->pdata->resume) { |
2097 | ret = host->pdata->resume(dev, host->slot_id); | |
2098 | if (ret) | |
2099 | dev_dbg(dev, "Unmask interrupt failed\n"); | |
2100 | } | |
a45c6cb8 | 2101 | |
927ce944 | 2102 | omap_hsmmc_protect_card(host); |
b62f6228 | 2103 | |
927ce944 FB |
2104 | /* Notify the core to resume the host */ |
2105 | ret = mmc_resume_host(host->mmc); | |
2106 | if (ret == 0) | |
2107 | host->suspended = 0; | |
fa4aa2d4 | 2108 | |
927ce944 FB |
2109 | pm_runtime_mark_last_busy(host->dev); |
2110 | pm_runtime_put_autosuspend(host->dev); | |
a45c6cb8 MC |
2111 | |
2112 | return ret; | |
2113 | ||
a45c6cb8 MC |
2114 | } |
2115 | ||
2116 | #else | |
70a3341a DK |
2117 | #define omap_hsmmc_suspend NULL |
2118 | #define omap_hsmmc_resume NULL | |
a45c6cb8 MC |
2119 | #endif |
2120 | ||
fa4aa2d4 B |
2121 | static int omap_hsmmc_runtime_suspend(struct device *dev) |
2122 | { | |
2123 | struct omap_hsmmc_host *host; | |
2124 | ||
2125 | host = platform_get_drvdata(to_platform_device(dev)); | |
2126 | omap_hsmmc_context_save(host); | |
927ce944 | 2127 | dev_dbg(dev, "disabled\n"); |
fa4aa2d4 B |
2128 | |
2129 | return 0; | |
2130 | } | |
2131 | ||
2132 | static int omap_hsmmc_runtime_resume(struct device *dev) | |
2133 | { | |
2134 | struct omap_hsmmc_host *host; | |
2135 | ||
2136 | host = platform_get_drvdata(to_platform_device(dev)); | |
2137 | omap_hsmmc_context_restore(host); | |
927ce944 | 2138 | dev_dbg(dev, "enabled\n"); |
fa4aa2d4 B |
2139 | |
2140 | return 0; | |
2141 | } | |
2142 | ||
a791daa1 | 2143 | static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { |
70a3341a DK |
2144 | .suspend = omap_hsmmc_suspend, |
2145 | .resume = omap_hsmmc_resume, | |
fa4aa2d4 B |
2146 | .runtime_suspend = omap_hsmmc_runtime_suspend, |
2147 | .runtime_resume = omap_hsmmc_runtime_resume, | |
a791daa1 KH |
2148 | }; |
2149 | ||
2150 | static struct platform_driver omap_hsmmc_driver = { | |
efa25fd3 FB |
2151 | .probe = omap_hsmmc_probe, |
2152 | .remove = __devexit_p(omap_hsmmc_remove), | |
a45c6cb8 MC |
2153 | .driver = { |
2154 | .name = DRIVER_NAME, | |
2155 | .owner = THIS_MODULE, | |
a791daa1 | 2156 | .pm = &omap_hsmmc_dev_pm_ops, |
46856a68 | 2157 | .of_match_table = of_match_ptr(omap_mmc_of_match), |
a45c6cb8 MC |
2158 | }, |
2159 | }; | |
2160 | ||
b796450b | 2161 | module_platform_driver(omap_hsmmc_driver); |
a45c6cb8 MC |
2162 | MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); |
2163 | MODULE_LICENSE("GPL"); | |
2164 | MODULE_ALIAS("platform:" DRIVER_NAME); | |
2165 | MODULE_AUTHOR("Texas Instruments Inc"); |