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Commit | Line | Data |
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1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/pxa.c - PXA MMCI driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This hardware is really sick: | |
11 | * - No way to clear interrupts. | |
12 | * - Have to turn off the clock whenever we touch the device. | |
13 | * - Doesn't tell you how many data blocks were transferred. | |
14 | * Yuck! | |
15 | * | |
16 | * 1 and 3 byte data transfers not supported | |
17 | * max block length up to 1023 | |
18 | */ | |
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/ioport.h> | |
d052d1be | 22 | #include <linux/platform_device.h> |
1da177e4 LT |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
6464b714 | 25 | #include <linux/dmaengine.h> |
1da177e4 | 26 | #include <linux/dma-mapping.h> |
ebebd9b0 RK |
27 | #include <linux/clk.h> |
28 | #include <linux/err.h> | |
1da177e4 | 29 | #include <linux/mmc/host.h> |
fd546ee6 | 30 | #include <linux/mmc/slot-gpio.h> |
05678a96 | 31 | #include <linux/io.h> |
8385f9cb | 32 | #include <linux/regulator/consumer.h> |
f54005b5 | 33 | #include <linux/gpio/consumer.h> |
5a0e3ad6 | 34 | #include <linux/gfp.h> |
e6027b46 | 35 | #include <linux/of.h> |
e6027b46 | 36 | #include <linux/of_device.h> |
1da177e4 | 37 | |
1da177e4 LT |
38 | #include <asm/sizes.h> |
39 | ||
05678a96 | 40 | #include <mach/hardware.h> |
293b2da1 | 41 | #include <linux/platform_data/mmc-pxamci.h> |
1da177e4 LT |
42 | |
43 | #include "pxamci.h" | |
44 | ||
1da177e4 LT |
45 | #define DRIVER_NAME "pxa2xx-mci" |
46 | ||
47 | #define NR_SG 1 | |
d8cb70d1 | 48 | #define CLKRT_OFF (~0) |
1da177e4 | 49 | |
fa3f9938 HZ |
50 | #define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \ |
51 | || cpu_is_pxa935()) | |
52 | ||
1da177e4 LT |
53 | struct pxamci_host { |
54 | struct mmc_host *mmc; | |
55 | spinlock_t lock; | |
56 | struct resource *res; | |
57 | void __iomem *base; | |
ebebd9b0 RK |
58 | struct clk *clk; |
59 | unsigned long clkrate; | |
1da177e4 LT |
60 | unsigned int clkrt; |
61 | unsigned int cmdat; | |
62 | unsigned int imask; | |
63 | unsigned int power_mode; | |
38a8dda9 | 64 | unsigned long detect_delay_ms; |
c914a27c | 65 | bool use_ro_gpio; |
f54005b5 | 66 | struct gpio_desc *power; |
1da177e4 LT |
67 | struct pxamci_platform_data *pdata; |
68 | ||
69 | struct mmc_request *mrq; | |
70 | struct mmc_command *cmd; | |
71 | struct mmc_data *data; | |
72 | ||
6464b714 DM |
73 | struct dma_chan *dma_chan_rx; |
74 | struct dma_chan *dma_chan_tx; | |
75 | dma_cookie_t dma_cookie; | |
1da177e4 | 76 | unsigned int dma_len; |
1da177e4 LT |
77 | unsigned int dma_dir; |
78 | }; | |
79 | ||
61951fd6 | 80 | static int pxamci_init_ocr(struct pxamci_host *host) |
8385f9cb | 81 | { |
61951fd6 DM |
82 | struct mmc_host *mmc = host->mmc; |
83 | int ret; | |
84 | ||
85 | ret = mmc_regulator_get_supply(mmc); | |
86 | if (ret < 0) | |
87 | return ret; | |
88 | ||
89 | if (IS_ERR(mmc->supply.vmmc)) { | |
8385f9cb | 90 | /* fall-back to platform data */ |
61951fd6 | 91 | mmc->ocr_avail = host->pdata ? |
8385f9cb DR |
92 | host->pdata->ocr_mask : |
93 | MMC_VDD_32_33 | MMC_VDD_33_34; | |
94 | } | |
61951fd6 DM |
95 | |
96 | return 0; | |
8385f9cb DR |
97 | } |
98 | ||
99fc5131 LW |
99 | static inline int pxamci_set_power(struct pxamci_host *host, |
100 | unsigned char power_mode, | |
101 | unsigned int vdd) | |
8385f9cb | 102 | { |
61951fd6 DM |
103 | struct mmc_host *mmc = host->mmc; |
104 | struct regulator *supply = mmc->supply.vmmc; | |
b405db6c | 105 | |
61951fd6 DM |
106 | if (!IS_ERR(supply)) |
107 | return mmc_regulator_set_ocr(mmc, supply, vdd); | |
99fc5131 | 108 | |
f54005b5 LW |
109 | if (host->power) { |
110 | bool on = !!((1 << vdd) & host->pdata->ocr_mask); | |
111 | gpiod_set_value(host->power, on); | |
b405db6c | 112 | } |
61951fd6 DM |
113 | |
114 | if (host->pdata && host->pdata->setpower) | |
a829abf8 | 115 | return host->pdata->setpower(mmc_dev(host->mmc), vdd); |
99fc5131 LW |
116 | |
117 | return 0; | |
8385f9cb DR |
118 | } |
119 | ||
1da177e4 LT |
120 | static void pxamci_stop_clock(struct pxamci_host *host) |
121 | { | |
122 | if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { | |
123 | unsigned long timeout = 10000; | |
124 | unsigned int v; | |
125 | ||
126 | writel(STOP_CLOCK, host->base + MMC_STRPCL); | |
127 | ||
128 | do { | |
129 | v = readl(host->base + MMC_STAT); | |
130 | if (!(v & STAT_CLK_EN)) | |
131 | break; | |
132 | udelay(1); | |
133 | } while (timeout--); | |
134 | ||
135 | if (v & STAT_CLK_EN) | |
136 | dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); | |
137 | } | |
138 | } | |
139 | ||
140 | static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) | |
141 | { | |
142 | unsigned long flags; | |
143 | ||
144 | spin_lock_irqsave(&host->lock, flags); | |
145 | host->imask &= ~mask; | |
146 | writel(host->imask, host->base + MMC_I_MASK); | |
147 | spin_unlock_irqrestore(&host->lock, flags); | |
148 | } | |
149 | ||
150 | static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) | |
151 | { | |
152 | unsigned long flags; | |
153 | ||
154 | spin_lock_irqsave(&host->lock, flags); | |
155 | host->imask |= mask; | |
156 | writel(host->imask, host->base + MMC_I_MASK); | |
157 | spin_unlock_irqrestore(&host->lock, flags); | |
158 | } | |
159 | ||
6464b714 DM |
160 | static void pxamci_dma_irq(void *param); |
161 | ||
1da177e4 LT |
162 | static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) |
163 | { | |
6464b714 | 164 | struct dma_async_tx_descriptor *tx; |
e60a582b | 165 | enum dma_transfer_direction direction; |
6464b714 DM |
166 | struct dma_slave_config config; |
167 | struct dma_chan *chan; | |
1da177e4 | 168 | unsigned int nob = data->blocks; |
3d63abe5 | 169 | unsigned long long clks; |
1da177e4 | 170 | unsigned int timeout; |
6464b714 | 171 | int ret; |
1da177e4 LT |
172 | |
173 | host->data = data; | |
174 | ||
1da177e4 | 175 | writel(nob, host->base + MMC_NOB); |
2c171bf1 | 176 | writel(data->blksz, host->base + MMC_BLKLEN); |
1da177e4 | 177 | |
ebebd9b0 | 178 | clks = (unsigned long long)data->timeout_ns * host->clkrate; |
3d63abe5 RK |
179 | do_div(clks, 1000000000UL); |
180 | timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); | |
1da177e4 LT |
181 | writel((timeout + 255) / 256, host->base + MMC_RDTO); |
182 | ||
6464b714 DM |
183 | memset(&config, 0, sizeof(config)); |
184 | config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
185 | config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; | |
186 | config.src_addr = host->res->start + MMC_RXFIFO; | |
187 | config.dst_addr = host->res->start + MMC_TXFIFO; | |
188 | config.src_maxburst = 32; | |
189 | config.dst_maxburst = 32; | |
190 | ||
1da177e4 LT |
191 | if (data->flags & MMC_DATA_READ) { |
192 | host->dma_dir = DMA_FROM_DEVICE; | |
6464b714 DM |
193 | direction = DMA_DEV_TO_MEM; |
194 | chan = host->dma_chan_rx; | |
1da177e4 LT |
195 | } else { |
196 | host->dma_dir = DMA_TO_DEVICE; | |
6464b714 DM |
197 | direction = DMA_MEM_TO_DEV; |
198 | chan = host->dma_chan_tx; | |
1da177e4 LT |
199 | } |
200 | ||
6464b714 DM |
201 | config.direction = direction; |
202 | ||
203 | ret = dmaengine_slave_config(chan, &config); | |
204 | if (ret < 0) { | |
205 | dev_err(mmc_dev(host->mmc), "dma slave config failed\n"); | |
206 | return; | |
207 | } | |
1da177e4 | 208 | |
6464b714 | 209 | host->dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, |
1da177e4 LT |
210 | host->dma_dir); |
211 | ||
6464b714 DM |
212 | tx = dmaengine_prep_slave_sg(chan, data->sg, host->dma_len, direction, |
213 | DMA_PREP_INTERRUPT); | |
214 | if (!tx) { | |
215 | dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); | |
216 | return; | |
1da177e4 | 217 | } |
1da177e4 | 218 | |
6464b714 DM |
219 | if (!(data->flags & MMC_DATA_READ)) { |
220 | tx->callback = pxamci_dma_irq; | |
221 | tx->callback_param = host; | |
222 | } | |
223 | ||
224 | host->dma_cookie = dmaengine_submit(tx); | |
b6018958 CB |
225 | |
226 | /* | |
227 | * workaround for erratum #91: | |
228 | * only start DMA now if we are doing a read, | |
229 | * otherwise we wait until CMD/RESP has finished | |
230 | * before starting DMA. | |
231 | */ | |
232 | if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ) | |
6464b714 | 233 | dma_async_issue_pending(chan); |
1da177e4 LT |
234 | } |
235 | ||
236 | static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) | |
237 | { | |
238 | WARN_ON(host->cmd != NULL); | |
239 | host->cmd = cmd; | |
240 | ||
241 | if (cmd->flags & MMC_RSP_BUSY) | |
242 | cmdat |= CMDAT_BUSY; | |
243 | ||
e9225176 RK |
244 | #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) |
245 | switch (RSP_TYPE(mmc_resp_type(cmd))) { | |
6f949909 | 246 | case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */ |
1da177e4 LT |
247 | cmdat |= CMDAT_RESP_SHORT; |
248 | break; | |
e9225176 | 249 | case RSP_TYPE(MMC_RSP_R3): |
1da177e4 LT |
250 | cmdat |= CMDAT_RESP_R3; |
251 | break; | |
e9225176 | 252 | case RSP_TYPE(MMC_RSP_R2): |
1da177e4 LT |
253 | cmdat |= CMDAT_RESP_R2; |
254 | break; | |
255 | default: | |
256 | break; | |
257 | } | |
258 | ||
259 | writel(cmd->opcode, host->base + MMC_CMD); | |
260 | writel(cmd->arg >> 16, host->base + MMC_ARGH); | |
261 | writel(cmd->arg & 0xffff, host->base + MMC_ARGL); | |
262 | writel(cmdat, host->base + MMC_CMDAT); | |
263 | writel(host->clkrt, host->base + MMC_CLKRT); | |
264 | ||
265 | writel(START_CLOCK, host->base + MMC_STRPCL); | |
266 | ||
267 | pxamci_enable_irq(host, END_CMD_RES); | |
268 | } | |
269 | ||
270 | static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq) | |
271 | { | |
1da177e4 LT |
272 | host->mrq = NULL; |
273 | host->cmd = NULL; | |
274 | host->data = NULL; | |
275 | mmc_request_done(host->mmc, mrq); | |
276 | } | |
277 | ||
278 | static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat) | |
279 | { | |
280 | struct mmc_command *cmd = host->cmd; | |
281 | int i; | |
282 | u32 v; | |
283 | ||
284 | if (!cmd) | |
285 | return 0; | |
286 | ||
287 | host->cmd = NULL; | |
288 | ||
289 | /* | |
290 | * Did I mention this is Sick. We always need to | |
291 | * discard the upper 8 bits of the first 16-bit word. | |
292 | */ | |
293 | v = readl(host->base + MMC_RES) & 0xffff; | |
294 | for (i = 0; i < 4; i++) { | |
295 | u32 w1 = readl(host->base + MMC_RES) & 0xffff; | |
296 | u32 w2 = readl(host->base + MMC_RES) & 0xffff; | |
297 | cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8; | |
298 | v = w2; | |
299 | } | |
300 | ||
301 | if (stat & STAT_TIME_OUT_RESPONSE) { | |
17b0429d | 302 | cmd->error = -ETIMEDOUT; |
1da177e4 | 303 | } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { |
1da177e4 LT |
304 | /* |
305 | * workaround for erratum #42: | |
306 | * Intel PXA27x Family Processor Specification Update Rev 001 | |
90e07d9f NP |
307 | * A bogus CRC error can appear if the msb of a 136 bit |
308 | * response is a one. | |
1da177e4 | 309 | */ |
e10a854c CB |
310 | if (cpu_is_pxa27x() && |
311 | (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000)) | |
90e07d9f | 312 | pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode); |
e10a854c CB |
313 | else |
314 | cmd->error = -EILSEQ; | |
1da177e4 LT |
315 | } |
316 | ||
317 | pxamci_disable_irq(host, END_CMD_RES); | |
17b0429d | 318 | if (host->data && !cmd->error) { |
1da177e4 | 319 | pxamci_enable_irq(host, DATA_TRAN_DONE); |
b6018958 CB |
320 | /* |
321 | * workaround for erratum #91, if doing write | |
322 | * enable DMA late | |
323 | */ | |
324 | if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE) | |
6464b714 | 325 | dma_async_issue_pending(host->dma_chan_tx); |
1da177e4 LT |
326 | } else { |
327 | pxamci_finish_request(host, host->mrq); | |
328 | } | |
329 | ||
330 | return 1; | |
331 | } | |
332 | ||
333 | static int pxamci_data_done(struct pxamci_host *host, unsigned int stat) | |
334 | { | |
335 | struct mmc_data *data = host->data; | |
6464b714 | 336 | struct dma_chan *chan; |
1da177e4 LT |
337 | |
338 | if (!data) | |
339 | return 0; | |
340 | ||
6464b714 DM |
341 | if (data->flags & MMC_DATA_READ) |
342 | chan = host->dma_chan_rx; | |
343 | else | |
344 | chan = host->dma_chan_tx; | |
345 | dma_unmap_sg(chan->device->dev, | |
346 | data->sg, data->sg_len, host->dma_dir); | |
1da177e4 LT |
347 | |
348 | if (stat & STAT_READ_TIME_OUT) | |
17b0429d | 349 | data->error = -ETIMEDOUT; |
1da177e4 | 350 | else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR)) |
17b0429d | 351 | data->error = -EILSEQ; |
1da177e4 LT |
352 | |
353 | /* | |
354 | * There appears to be a hardware design bug here. There seems to | |
355 | * be no way to find out how much data was transferred to the card. | |
356 | * This means that if there was an error on any block, we mark all | |
357 | * data blocks as being in error. | |
358 | */ | |
17b0429d | 359 | if (!data->error) |
2c171bf1 | 360 | data->bytes_xfered = data->blocks * data->blksz; |
1da177e4 LT |
361 | else |
362 | data->bytes_xfered = 0; | |
363 | ||
364 | pxamci_disable_irq(host, DATA_TRAN_DONE); | |
365 | ||
366 | host->data = NULL; | |
58741e8b | 367 | if (host->mrq->stop) { |
1da177e4 | 368 | pxamci_stop_clock(host); |
df456f47 | 369 | pxamci_start_cmd(host, host->mrq->stop, host->cmdat); |
1da177e4 LT |
370 | } else { |
371 | pxamci_finish_request(host, host->mrq); | |
372 | } | |
373 | ||
374 | return 1; | |
375 | } | |
376 | ||
7d12e780 | 377 | static irqreturn_t pxamci_irq(int irq, void *devid) |
1da177e4 LT |
378 | { |
379 | struct pxamci_host *host = devid; | |
380 | unsigned int ireg; | |
381 | int handled = 0; | |
382 | ||
81ab570f | 383 | ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK); |
1da177e4 | 384 | |
1da177e4 LT |
385 | if (ireg) { |
386 | unsigned stat = readl(host->base + MMC_STAT); | |
387 | ||
d78e9079 | 388 | pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat); |
1da177e4 LT |
389 | |
390 | if (ireg & END_CMD_RES) | |
391 | handled |= pxamci_cmd_done(host, stat); | |
392 | if (ireg & DATA_TRAN_DONE) | |
393 | handled |= pxamci_data_done(host, stat); | |
5d3ad4e8 BW |
394 | if (ireg & SDIO_INT) { |
395 | mmc_signal_sdio_irq(host->mmc); | |
396 | handled = 1; | |
397 | } | |
1da177e4 LT |
398 | } |
399 | ||
400 | return IRQ_RETVAL(handled); | |
401 | } | |
402 | ||
403 | static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
404 | { | |
405 | struct pxamci_host *host = mmc_priv(mmc); | |
406 | unsigned int cmdat; | |
407 | ||
408 | WARN_ON(host->mrq != NULL); | |
409 | ||
410 | host->mrq = mrq; | |
411 | ||
412 | pxamci_stop_clock(host); | |
413 | ||
414 | cmdat = host->cmdat; | |
415 | host->cmdat &= ~CMDAT_INIT; | |
416 | ||
417 | if (mrq->data) { | |
418 | pxamci_setup_data(host, mrq->data); | |
419 | ||
420 | cmdat &= ~CMDAT_BUSY; | |
421 | cmdat |= CMDAT_DATAEN | CMDAT_DMAEN; | |
422 | if (mrq->data->flags & MMC_DATA_WRITE) | |
423 | cmdat |= CMDAT_WRITE; | |
1da177e4 LT |
424 | } |
425 | ||
426 | pxamci_start_cmd(host, mrq->cmd, cmdat); | |
427 | } | |
428 | ||
e619524f RP |
429 | static int pxamci_get_ro(struct mmc_host *mmc) |
430 | { | |
431 | struct pxamci_host *host = mmc_priv(mmc); | |
432 | ||
c914a27c | 433 | if (host->use_ro_gpio) |
fd546ee6 | 434 | return mmc_gpio_get_ro(mmc); |
e619524f | 435 | if (host->pdata && host->pdata->get_ro) |
08f80bb5 AV |
436 | return !!host->pdata->get_ro(mmc_dev(mmc)); |
437 | /* | |
438 | * Board doesn't support read only detection; let the mmc core | |
439 | * decide what to do. | |
440 | */ | |
441 | return -ENOSYS; | |
e619524f RP |
442 | } |
443 | ||
1da177e4 LT |
444 | static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
445 | { | |
446 | struct pxamci_host *host = mmc_priv(mmc); | |
447 | ||
1da177e4 | 448 | if (ios->clock) { |
ebebd9b0 RK |
449 | unsigned long rate = host->clkrate; |
450 | unsigned int clk = rate / ios->clock; | |
451 | ||
d8cb70d1 | 452 | if (host->clkrt == CLKRT_OFF) |
e7370819 | 453 | clk_prepare_enable(host->clk); |
d8cb70d1 | 454 | |
64eb036a | 455 | if (ios->clock == 26000000) { |
fa3f9938 | 456 | /* to support 26MHz */ |
64eb036a BW |
457 | host->clkrt = 7; |
458 | } else { | |
459 | /* to handle (19.5MHz, 26MHz) */ | |
460 | if (!clk) | |
461 | clk = 1; | |
462 | ||
463 | /* | |
464 | * clk might result in a lower divisor than we | |
465 | * desire. check for that condition and adjust | |
466 | * as appropriate. | |
467 | */ | |
468 | if (rate / clk > ios->clock) | |
469 | clk <<= 1; | |
470 | host->clkrt = fls(clk) - 1; | |
471 | } | |
1da177e4 LT |
472 | |
473 | /* | |
474 | * we write clkrt on the next command | |
475 | */ | |
476 | } else { | |
477 | pxamci_stop_clock(host); | |
d8cb70d1 RK |
478 | if (host->clkrt != CLKRT_OFF) { |
479 | host->clkrt = CLKRT_OFF; | |
e7370819 | 480 | clk_disable_unprepare(host->clk); |
d8cb70d1 | 481 | } |
1da177e4 LT |
482 | } |
483 | ||
484 | if (host->power_mode != ios->power_mode) { | |
99fc5131 LW |
485 | int ret; |
486 | ||
1da177e4 LT |
487 | host->power_mode = ios->power_mode; |
488 | ||
99fc5131 LW |
489 | ret = pxamci_set_power(host, ios->power_mode, ios->vdd); |
490 | if (ret) { | |
491 | dev_err(mmc_dev(mmc), "unable to set power\n"); | |
492 | /* | |
493 | * The .set_ios() function in the mmc_host_ops | |
494 | * struct return void, and failing to set the | |
495 | * power should be rare so we print an error and | |
496 | * return here. | |
497 | */ | |
498 | return; | |
499 | } | |
1da177e4 LT |
500 | |
501 | if (ios->power_mode == MMC_POWER_ON) | |
502 | host->cmdat |= CMDAT_INIT; | |
503 | } | |
504 | ||
df456f47 BW |
505 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
506 | host->cmdat |= CMDAT_SD_4DAT; | |
507 | else | |
508 | host->cmdat &= ~CMDAT_SD_4DAT; | |
509 | ||
99fc5131 LW |
510 | dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n", |
511 | host->clkrt, host->cmdat); | |
1da177e4 LT |
512 | } |
513 | ||
5d3ad4e8 BW |
514 | static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable) |
515 | { | |
516 | struct pxamci_host *pxa_host = mmc_priv(host); | |
517 | ||
518 | if (enable) | |
519 | pxamci_enable_irq(pxa_host, SDIO_INT); | |
520 | else | |
521 | pxamci_disable_irq(pxa_host, SDIO_INT); | |
522 | } | |
523 | ||
ab7aefd0 | 524 | static const struct mmc_host_ops pxamci_ops = { |
5d3ad4e8 | 525 | .request = pxamci_request, |
fd546ee6 | 526 | .get_cd = mmc_gpio_get_cd, |
5d3ad4e8 BW |
527 | .get_ro = pxamci_get_ro, |
528 | .set_ios = pxamci_set_ios, | |
529 | .enable_sdio_irq = pxamci_enable_sdio_irq, | |
1da177e4 LT |
530 | }; |
531 | ||
6464b714 | 532 | static void pxamci_dma_irq(void *param) |
1da177e4 | 533 | { |
6464b714 DM |
534 | struct pxamci_host *host = param; |
535 | struct dma_tx_state state; | |
536 | enum dma_status status; | |
537 | struct dma_chan *chan; | |
538 | unsigned long flags; | |
539 | ||
540 | spin_lock_irqsave(&host->lock, flags); | |
541 | ||
542 | if (!host->data) | |
543 | goto out_unlock; | |
c783837b | 544 | |
6464b714 DM |
545 | if (host->data->flags & MMC_DATA_READ) |
546 | chan = host->dma_chan_rx; | |
547 | else | |
548 | chan = host->dma_chan_tx; | |
549 | ||
550 | status = dmaengine_tx_status(chan, host->dma_cookie, &state); | |
551 | ||
552 | if (likely(status == DMA_COMPLETE)) { | |
c783837b NP |
553 | writel(BUF_PART_FULL, host->base + MMC_PRTBUF); |
554 | } else { | |
6464b714 DM |
555 | pr_err("%s: DMA error on %s channel\n", mmc_hostname(host->mmc), |
556 | host->data->flags & MMC_DATA_READ ? "rx" : "tx"); | |
c783837b NP |
557 | host->data->error = -EIO; |
558 | pxamci_data_done(host, 0); | |
559 | } | |
6464b714 DM |
560 | |
561 | out_unlock: | |
562 | spin_unlock_irqrestore(&host->lock, flags); | |
1da177e4 LT |
563 | } |
564 | ||
7d12e780 | 565 | static irqreturn_t pxamci_detect_irq(int irq, void *devid) |
1da177e4 | 566 | { |
c26971cb RP |
567 | struct pxamci_host *host = mmc_priv(devid); |
568 | ||
38a8dda9 | 569 | mmc_detect_change(devid, msecs_to_jiffies(host->detect_delay_ms)); |
1da177e4 LT |
570 | return IRQ_HANDLED; |
571 | } | |
572 | ||
e6027b46 DM |
573 | #ifdef CONFIG_OF |
574 | static const struct of_device_id pxa_mmc_dt_ids[] = { | |
575 | { .compatible = "marvell,pxa-mmc" }, | |
576 | { } | |
577 | }; | |
578 | ||
579 | MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids); | |
580 | ||
fa3a5115 DM |
581 | static int pxamci_of_init(struct platform_device *pdev, |
582 | struct mmc_host *mmc) | |
e6027b46 | 583 | { |
0da5358b | 584 | struct device_node *np = pdev->dev.of_node; |
38a8dda9 | 585 | struct pxamci_host *host = mmc_priv(mmc); |
0da5358b | 586 | u32 tmp; |
fa3a5115 | 587 | int ret; |
e6027b46 | 588 | |
0da5358b DM |
589 | if (!np) |
590 | return 0; | |
e6027b46 | 591 | |
e6027b46 | 592 | /* pxa-mmc specific */ |
e6027b46 | 593 | if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0) |
38a8dda9 | 594 | host->detect_delay_ms = tmp; |
e6027b46 | 595 | |
fa3a5115 DM |
596 | ret = mmc_of_parse(mmc); |
597 | if (ret < 0) | |
598 | return ret; | |
599 | ||
0da5358b | 600 | return 0; |
e6027b46 DM |
601 | } |
602 | #else | |
fa3a5115 DM |
603 | static int pxamci_of_init(struct platform_device *pdev, |
604 | struct mmc_host *mmc) | |
e6027b46 DM |
605 | { |
606 | return 0; | |
607 | } | |
608 | #endif | |
609 | ||
3ae5eaec | 610 | static int pxamci_probe(struct platform_device *pdev) |
1da177e4 | 611 | { |
1da177e4 LT |
612 | struct mmc_host *mmc; |
613 | struct pxamci_host *host = NULL; | |
23f3ff72 | 614 | struct device *dev = &pdev->dev; |
6b3348f9 | 615 | struct resource *r; |
38a8dda9 | 616 | int ret, irq; |
1da177e4 LT |
617 | |
618 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
619 | irq = platform_get_irq(pdev, 0); | |
07e7716c RJ |
620 | if (irq < 0) |
621 | return irq; | |
1da177e4 | 622 | |
23f3ff72 | 623 | mmc = mmc_alloc_host(sizeof(struct pxamci_host), dev); |
1da177e4 LT |
624 | if (!mmc) { |
625 | ret = -ENOMEM; | |
626 | goto out; | |
627 | } | |
628 | ||
629 | mmc->ops = &pxamci_ops; | |
1da177e4 LT |
630 | |
631 | /* | |
632 | * We can do SG-DMA, but we don't because we never know how much | |
633 | * data we successfully wrote to the card. | |
634 | */ | |
a36274e0 | 635 | mmc->max_segs = NR_SG; |
1da177e4 LT |
636 | |
637 | /* | |
638 | * Our hardware DMA can handle a maximum of one page per SG entry. | |
639 | */ | |
640 | mmc->max_seg_size = PAGE_SIZE; | |
641 | ||
fe4a3c7a | 642 | /* |
fe2dc44e | 643 | * Block length register is only 10 bits before PXA27x. |
fe4a3c7a | 644 | */ |
0ffcbfd5 | 645 | mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048; |
fe4a3c7a | 646 | |
55db890a PO |
647 | /* |
648 | * Block count register is 16 bits. | |
649 | */ | |
650 | mmc->max_blk_count = 65535; | |
651 | ||
fa3a5115 DM |
652 | ret = pxamci_of_init(pdev, mmc); |
653 | if (ret) | |
654 | return ret; | |
655 | ||
1da177e4 LT |
656 | host = mmc_priv(mmc); |
657 | host->mmc = mmc; | |
1da177e4 | 658 | host->pdata = pdev->dev.platform_data; |
d8cb70d1 | 659 | host->clkrt = CLKRT_OFF; |
ebebd9b0 | 660 | |
23f3ff72 | 661 | host->clk = devm_clk_get(dev, NULL); |
ebebd9b0 RK |
662 | if (IS_ERR(host->clk)) { |
663 | ret = PTR_ERR(host->clk); | |
664 | host->clk = NULL; | |
665 | goto out; | |
666 | } | |
667 | ||
668 | host->clkrate = clk_get_rate(host->clk); | |
669 | ||
670 | /* | |
671 | * Calculate minimum clock rate, rounding up. | |
672 | */ | |
673 | mmc->f_min = (host->clkrate + 63) / 64; | |
fa3f9938 | 674 | mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate; |
ebebd9b0 | 675 | |
61951fd6 DM |
676 | ret = pxamci_init_ocr(host); |
677 | if (ret < 0) | |
678 | return ret; | |
8385f9cb | 679 | |
de3ee99b | 680 | mmc->caps = 0; |
5d3ad4e8 | 681 | host->cmdat = 0; |
0ffcbfd5 | 682 | if (!cpu_is_pxa25x()) { |
5d3ad4e8 BW |
683 | mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; |
684 | host->cmdat |= CMDAT_SDIO_INT_EN; | |
fa3f9938 | 685 | if (mmc_has_26MHz()) |
64eb036a BW |
686 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | |
687 | MMC_CAP_SD_HIGHSPEED; | |
5d3ad4e8 | 688 | } |
1da177e4 | 689 | |
1da177e4 LT |
690 | spin_lock_init(&host->lock); |
691 | host->res = r; | |
1da177e4 LT |
692 | host->imask = MMC_I_MASK_ALL; |
693 | ||
23f3ff72 | 694 | host->base = devm_ioremap_resource(dev, r); |
07e7716c RJ |
695 | if (IS_ERR(host->base)) { |
696 | ret = PTR_ERR(host->base); | |
1da177e4 LT |
697 | goto out; |
698 | } | |
699 | ||
700 | /* | |
701 | * Ensure that the host controller is shut down, and setup | |
702 | * with our defaults. | |
703 | */ | |
704 | pxamci_stop_clock(host); | |
705 | writel(0, host->base + MMC_SPI); | |
706 | writel(64, host->base + MMC_RESTO); | |
707 | writel(host->imask, host->base + MMC_I_MASK); | |
708 | ||
23f3ff72 | 709 | ret = devm_request_irq(dev, irq, pxamci_irq, 0, |
07e7716c | 710 | DRIVER_NAME, host); |
1da177e4 LT |
711 | if (ret) |
712 | goto out; | |
713 | ||
3ae5eaec | 714 | platform_set_drvdata(pdev, mmc); |
1da177e4 | 715 | |
23f3ff72 | 716 | host->dma_chan_rx = dma_request_slave_channel(dev, "rx"); |
6464b714 | 717 | if (host->dma_chan_rx == NULL) { |
23f3ff72 | 718 | dev_err(dev, "unable to request rx dma channel\n"); |
6464b714 | 719 | ret = -ENODEV; |
9a788c6b BW |
720 | goto out; |
721 | } | |
9a788c6b | 722 | |
23f3ff72 | 723 | host->dma_chan_tx = dma_request_slave_channel(dev, "tx"); |
6464b714 | 724 | if (host->dma_chan_tx == NULL) { |
23f3ff72 | 725 | dev_err(dev, "unable to request tx dma channel\n"); |
6464b714 | 726 | ret = -ENODEV; |
9a788c6b BW |
727 | goto out; |
728 | } | |
9a788c6b | 729 | |
b405db6c | 730 | if (host->pdata) { |
38a8dda9 DM |
731 | host->detect_delay_ms = host->pdata->detect_delay_ms; |
732 | ||
f54005b5 LW |
733 | host->power = devm_gpiod_get_optional(dev, "power", GPIOD_OUT_LOW); |
734 | if (IS_ERR(host->power)) { | |
735 | dev_err(dev, "Failed requesting gpio_power\n"); | |
736 | goto out; | |
b405db6c | 737 | } |
38a8dda9 | 738 | |
c914a27c LW |
739 | /* FIXME: should we pass detection delay to debounce? */ |
740 | ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL); | |
741 | if (ret && ret != -ENOENT) { | |
742 | dev_err(dev, "Failed requesting gpio_cd\n"); | |
743 | goto out; | |
744 | } | |
c914a27c | 745 | |
a2b760a6 | 746 | ret = mmc_gpiod_request_ro(mmc, "wp", 0, 0, NULL); |
c914a27c LW |
747 | if (ret && ret != -ENOENT) { |
748 | dev_err(dev, "Failed requesting gpio_ro\n"); | |
749 | goto out; | |
750 | } | |
c914a27c LW |
751 | if (!ret) { |
752 | host->use_ro_gpio = true; | |
753 | mmc->caps2 |= host->pdata->gpio_card_ro_invert ? | |
754 | 0 : MMC_CAP2_RO_ACTIVE_HIGH; | |
b3802db5 | 755 | } |
b405db6c | 756 | |
38a8dda9 | 757 | if (host->pdata->init) |
23f3ff72 | 758 | host->pdata->init(dev, pxamci_detect_irq, mmc); |
b405db6c | 759 | |
f54005b5 | 760 | if (host->power && host->pdata->setpower) |
23f3ff72 | 761 | dev_warn(dev, "gpio_power and setpower() both defined\n"); |
c914a27c | 762 | if (host->use_ro_gpio && host->pdata->get_ro) |
23f3ff72 | 763 | dev_warn(dev, "gpio_ro and get_ro() both defined\n"); |
38a8dda9 | 764 | } |
b405db6c | 765 | |
1da177e4 LT |
766 | mmc_add_host(mmc); |
767 | ||
768 | return 0; | |
769 | ||
fd546ee6 | 770 | out: |
1da177e4 | 771 | if (host) { |
6464b714 DM |
772 | if (host->dma_chan_rx) |
773 | dma_release_channel(host->dma_chan_rx); | |
774 | if (host->dma_chan_tx) | |
775 | dma_release_channel(host->dma_chan_tx); | |
1da177e4 LT |
776 | } |
777 | if (mmc) | |
778 | mmc_free_host(mmc); | |
1da177e4 LT |
779 | return ret; |
780 | } | |
781 | ||
3ae5eaec | 782 | static int pxamci_remove(struct platform_device *pdev) |
1da177e4 | 783 | { |
3ae5eaec | 784 | struct mmc_host *mmc = platform_get_drvdata(pdev); |
1da177e4 | 785 | |
1da177e4 LT |
786 | if (mmc) { |
787 | struct pxamci_host *host = mmc_priv(mmc); | |
788 | ||
5d6b1edf DM |
789 | mmc_remove_host(mmc); |
790 | ||
1da177e4 | 791 | if (host->pdata && host->pdata->exit) |
3ae5eaec | 792 | host->pdata->exit(&pdev->dev, mmc); |
1da177e4 | 793 | |
1da177e4 LT |
794 | pxamci_stop_clock(host); |
795 | writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD| | |
796 | END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, | |
797 | host->base + MMC_I_MASK); | |
798 | ||
6464b714 DM |
799 | dmaengine_terminate_all(host->dma_chan_rx); |
800 | dmaengine_terminate_all(host->dma_chan_tx); | |
801 | dma_release_channel(host->dma_chan_rx); | |
802 | dma_release_channel(host->dma_chan_tx); | |
1da177e4 LT |
803 | |
804 | mmc_free_host(mmc); | |
805 | } | |
52c09186 | 806 | |
1da177e4 LT |
807 | return 0; |
808 | } | |
809 | ||
3ae5eaec | 810 | static struct platform_driver pxamci_driver = { |
1da177e4 LT |
811 | .probe = pxamci_probe, |
812 | .remove = pxamci_remove, | |
3ae5eaec RK |
813 | .driver = { |
814 | .name = DRIVER_NAME, | |
e6027b46 | 815 | .of_match_table = of_match_ptr(pxa_mmc_dt_ids), |
3ae5eaec | 816 | }, |
1da177e4 LT |
817 | }; |
818 | ||
d1f81a64 | 819 | module_platform_driver(pxamci_driver); |
1da177e4 LT |
820 | |
821 | MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver"); | |
822 | MODULE_LICENSE("GPL"); | |
bc65c724 | 823 | MODULE_ALIAS("platform:pxa2xx-mci"); |