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Commit | Line | Data |
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1da177e4 | 1 | /* |
70f10482 | 2 | * linux/drivers/mmc/host/pxa.c - PXA MMCI driver |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2003 Russell King, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This hardware is really sick: | |
11 | * - No way to clear interrupts. | |
12 | * - Have to turn off the clock whenever we touch the device. | |
13 | * - Doesn't tell you how many data blocks were transferred. | |
14 | * Yuck! | |
15 | * | |
16 | * 1 and 3 byte data transfers not supported | |
17 | * max block length up to 1023 | |
18 | */ | |
1da177e4 LT |
19 | #include <linux/module.h> |
20 | #include <linux/init.h> | |
21 | #include <linux/ioport.h> | |
d052d1be | 22 | #include <linux/platform_device.h> |
1da177e4 LT |
23 | #include <linux/delay.h> |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/dma-mapping.h> | |
ebebd9b0 RK |
26 | #include <linux/clk.h> |
27 | #include <linux/err.h> | |
1da177e4 | 28 | #include <linux/mmc/host.h> |
05678a96 | 29 | #include <linux/io.h> |
8385f9cb | 30 | #include <linux/regulator/consumer.h> |
b405db6c | 31 | #include <linux/gpio.h> |
5a0e3ad6 | 32 | #include <linux/gfp.h> |
e6027b46 DM |
33 | #include <linux/of.h> |
34 | #include <linux/of_gpio.h> | |
35 | #include <linux/of_device.h> | |
1da177e4 | 36 | |
1da177e4 LT |
37 | #include <asm/sizes.h> |
38 | ||
05678a96 | 39 | #include <mach/hardware.h> |
7ebc8d56 | 40 | #include <mach/dma.h> |
293b2da1 | 41 | #include <linux/platform_data/mmc-pxamci.h> |
1da177e4 LT |
42 | |
43 | #include "pxamci.h" | |
44 | ||
1da177e4 LT |
45 | #define DRIVER_NAME "pxa2xx-mci" |
46 | ||
47 | #define NR_SG 1 | |
d8cb70d1 | 48 | #define CLKRT_OFF (~0) |
1da177e4 | 49 | |
fa3f9938 HZ |
50 | #define mmc_has_26MHz() (cpu_is_pxa300() || cpu_is_pxa310() \ |
51 | || cpu_is_pxa935()) | |
52 | ||
1da177e4 LT |
53 | struct pxamci_host { |
54 | struct mmc_host *mmc; | |
55 | spinlock_t lock; | |
56 | struct resource *res; | |
57 | void __iomem *base; | |
ebebd9b0 RK |
58 | struct clk *clk; |
59 | unsigned long clkrate; | |
1da177e4 LT |
60 | int irq; |
61 | int dma; | |
62 | unsigned int clkrt; | |
63 | unsigned int cmdat; | |
64 | unsigned int imask; | |
65 | unsigned int power_mode; | |
66 | struct pxamci_platform_data *pdata; | |
67 | ||
68 | struct mmc_request *mrq; | |
69 | struct mmc_command *cmd; | |
70 | struct mmc_data *data; | |
71 | ||
72 | dma_addr_t sg_dma; | |
73 | struct pxa_dma_desc *sg_cpu; | |
74 | unsigned int dma_len; | |
75 | ||
76 | unsigned int dma_dir; | |
9a788c6b BW |
77 | unsigned int dma_drcmrrx; |
78 | unsigned int dma_drcmrtx; | |
8385f9cb DR |
79 | |
80 | struct regulator *vcc; | |
1da177e4 LT |
81 | }; |
82 | ||
8385f9cb DR |
83 | static inline void pxamci_init_ocr(struct pxamci_host *host) |
84 | { | |
85 | #ifdef CONFIG_REGULATOR | |
6ae8717a | 86 | host->vcc = regulator_get_optional(mmc_dev(host->mmc), "vmmc"); |
8385f9cb DR |
87 | |
88 | if (IS_ERR(host->vcc)) | |
89 | host->vcc = NULL; | |
90 | else { | |
91 | host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc); | |
92 | if (host->pdata && host->pdata->ocr_mask) | |
93 | dev_warn(mmc_dev(host->mmc), | |
94 | "ocr_mask/setpower will not be used\n"); | |
95 | } | |
96 | #endif | |
97 | if (host->vcc == NULL) { | |
98 | /* fall-back to platform data */ | |
99 | host->mmc->ocr_avail = host->pdata ? | |
100 | host->pdata->ocr_mask : | |
101 | MMC_VDD_32_33 | MMC_VDD_33_34; | |
102 | } | |
103 | } | |
104 | ||
99fc5131 LW |
105 | static inline int pxamci_set_power(struct pxamci_host *host, |
106 | unsigned char power_mode, | |
107 | unsigned int vdd) | |
8385f9cb | 108 | { |
b405db6c RJ |
109 | int on; |
110 | ||
99fc5131 LW |
111 | if (host->vcc) { |
112 | int ret; | |
113 | ||
114 | if (power_mode == MMC_POWER_UP) { | |
115 | ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); | |
116 | if (ret) | |
117 | return ret; | |
118 | } else if (power_mode == MMC_POWER_OFF) { | |
119 | ret = mmc_regulator_set_ocr(host->mmc, host->vcc, 0); | |
120 | if (ret) | |
121 | return ret; | |
122 | } | |
123 | } | |
b405db6c RJ |
124 | if (!host->vcc && host->pdata && |
125 | gpio_is_valid(host->pdata->gpio_power)) { | |
126 | on = ((1 << vdd) & host->pdata->ocr_mask); | |
127 | gpio_set_value(host->pdata->gpio_power, | |
128 | !!on ^ host->pdata->gpio_power_invert); | |
129 | } | |
8385f9cb | 130 | if (!host->vcc && host->pdata && host->pdata->setpower) |
a829abf8 | 131 | return host->pdata->setpower(mmc_dev(host->mmc), vdd); |
99fc5131 LW |
132 | |
133 | return 0; | |
8385f9cb DR |
134 | } |
135 | ||
1da177e4 LT |
136 | static void pxamci_stop_clock(struct pxamci_host *host) |
137 | { | |
138 | if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { | |
139 | unsigned long timeout = 10000; | |
140 | unsigned int v; | |
141 | ||
142 | writel(STOP_CLOCK, host->base + MMC_STRPCL); | |
143 | ||
144 | do { | |
145 | v = readl(host->base + MMC_STAT); | |
146 | if (!(v & STAT_CLK_EN)) | |
147 | break; | |
148 | udelay(1); | |
149 | } while (timeout--); | |
150 | ||
151 | if (v & STAT_CLK_EN) | |
152 | dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); | |
153 | } | |
154 | } | |
155 | ||
156 | static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) | |
157 | { | |
158 | unsigned long flags; | |
159 | ||
160 | spin_lock_irqsave(&host->lock, flags); | |
161 | host->imask &= ~mask; | |
162 | writel(host->imask, host->base + MMC_I_MASK); | |
163 | spin_unlock_irqrestore(&host->lock, flags); | |
164 | } | |
165 | ||
166 | static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) | |
167 | { | |
168 | unsigned long flags; | |
169 | ||
170 | spin_lock_irqsave(&host->lock, flags); | |
171 | host->imask |= mask; | |
172 | writel(host->imask, host->base + MMC_I_MASK); | |
173 | spin_unlock_irqrestore(&host->lock, flags); | |
174 | } | |
175 | ||
176 | static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) | |
177 | { | |
178 | unsigned int nob = data->blocks; | |
3d63abe5 | 179 | unsigned long long clks; |
1da177e4 | 180 | unsigned int timeout; |
97f8571e | 181 | bool dalgn = 0; |
1da177e4 LT |
182 | u32 dcmd; |
183 | int i; | |
184 | ||
185 | host->data = data; | |
186 | ||
187 | if (data->flags & MMC_DATA_STREAM) | |
188 | nob = 0xffff; | |
189 | ||
190 | writel(nob, host->base + MMC_NOB); | |
2c171bf1 | 191 | writel(data->blksz, host->base + MMC_BLKLEN); |
1da177e4 | 192 | |
ebebd9b0 | 193 | clks = (unsigned long long)data->timeout_ns * host->clkrate; |
3d63abe5 RK |
194 | do_div(clks, 1000000000UL); |
195 | timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); | |
1da177e4 LT |
196 | writel((timeout + 255) / 256, host->base + MMC_RDTO); |
197 | ||
198 | if (data->flags & MMC_DATA_READ) { | |
199 | host->dma_dir = DMA_FROM_DEVICE; | |
7eeff481 | 200 | dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC; |
9a788c6b BW |
201 | DRCMR(host->dma_drcmrtx) = 0; |
202 | DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD; | |
1da177e4 LT |
203 | } else { |
204 | host->dma_dir = DMA_TO_DEVICE; | |
7eeff481 | 205 | dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG; |
9a788c6b BW |
206 | DRCMR(host->dma_drcmrrx) = 0; |
207 | DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD; | |
1da177e4 LT |
208 | } |
209 | ||
210 | dcmd |= DCMD_BURST32 | DCMD_WIDTH1; | |
211 | ||
212 | host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, | |
213 | host->dma_dir); | |
214 | ||
215 | for (i = 0; i < host->dma_len; i++) { | |
c783837b NP |
216 | unsigned int length = sg_dma_len(&data->sg[i]); |
217 | host->sg_cpu[i].dcmd = dcmd | length; | |
218 | if (length & 31 && !(data->flags & MMC_DATA_READ)) | |
219 | host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN; | |
97f8571e PZ |
220 | /* Not aligned to 8-byte boundary? */ |
221 | if (sg_dma_address(&data->sg[i]) & 0x7) | |
222 | dalgn = 1; | |
1da177e4 LT |
223 | if (data->flags & MMC_DATA_READ) { |
224 | host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO; | |
225 | host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]); | |
226 | } else { | |
227 | host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]); | |
228 | host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO; | |
229 | } | |
1da177e4 LT |
230 | host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) * |
231 | sizeof(struct pxa_dma_desc); | |
232 | } | |
233 | host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP; | |
234 | wmb(); | |
235 | ||
97f8571e PZ |
236 | /* |
237 | * The PXA27x DMA controller encounters overhead when working with | |
238 | * unaligned (to 8-byte boundaries) data, so switch on byte alignment | |
239 | * mode only if we have unaligned data. | |
240 | */ | |
241 | if (dalgn) | |
242 | DALGN |= (1 << host->dma); | |
243 | else | |
4fe16897 | 244 | DALGN &= ~(1 << host->dma); |
1da177e4 | 245 | DDADR(host->dma) = host->sg_dma; |
b6018958 CB |
246 | |
247 | /* | |
248 | * workaround for erratum #91: | |
249 | * only start DMA now if we are doing a read, | |
250 | * otherwise we wait until CMD/RESP has finished | |
251 | * before starting DMA. | |
252 | */ | |
253 | if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ) | |
254 | DCSR(host->dma) = DCSR_RUN; | |
1da177e4 LT |
255 | } |
256 | ||
257 | static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) | |
258 | { | |
259 | WARN_ON(host->cmd != NULL); | |
260 | host->cmd = cmd; | |
261 | ||
262 | if (cmd->flags & MMC_RSP_BUSY) | |
263 | cmdat |= CMDAT_BUSY; | |
264 | ||
e9225176 RK |
265 | #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) |
266 | switch (RSP_TYPE(mmc_resp_type(cmd))) { | |
6f949909 | 267 | case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */ |
1da177e4 LT |
268 | cmdat |= CMDAT_RESP_SHORT; |
269 | break; | |
e9225176 | 270 | case RSP_TYPE(MMC_RSP_R3): |
1da177e4 LT |
271 | cmdat |= CMDAT_RESP_R3; |
272 | break; | |
e9225176 | 273 | case RSP_TYPE(MMC_RSP_R2): |
1da177e4 LT |
274 | cmdat |= CMDAT_RESP_R2; |
275 | break; | |
276 | default: | |
277 | break; | |
278 | } | |
279 | ||
280 | writel(cmd->opcode, host->base + MMC_CMD); | |
281 | writel(cmd->arg >> 16, host->base + MMC_ARGH); | |
282 | writel(cmd->arg & 0xffff, host->base + MMC_ARGL); | |
283 | writel(cmdat, host->base + MMC_CMDAT); | |
284 | writel(host->clkrt, host->base + MMC_CLKRT); | |
285 | ||
286 | writel(START_CLOCK, host->base + MMC_STRPCL); | |
287 | ||
288 | pxamci_enable_irq(host, END_CMD_RES); | |
289 | } | |
290 | ||
291 | static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq) | |
292 | { | |
1da177e4 LT |
293 | host->mrq = NULL; |
294 | host->cmd = NULL; | |
295 | host->data = NULL; | |
296 | mmc_request_done(host->mmc, mrq); | |
297 | } | |
298 | ||
299 | static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat) | |
300 | { | |
301 | struct mmc_command *cmd = host->cmd; | |
302 | int i; | |
303 | u32 v; | |
304 | ||
305 | if (!cmd) | |
306 | return 0; | |
307 | ||
308 | host->cmd = NULL; | |
309 | ||
310 | /* | |
311 | * Did I mention this is Sick. We always need to | |
312 | * discard the upper 8 bits of the first 16-bit word. | |
313 | */ | |
314 | v = readl(host->base + MMC_RES) & 0xffff; | |
315 | for (i = 0; i < 4; i++) { | |
316 | u32 w1 = readl(host->base + MMC_RES) & 0xffff; | |
317 | u32 w2 = readl(host->base + MMC_RES) & 0xffff; | |
318 | cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8; | |
319 | v = w2; | |
320 | } | |
321 | ||
322 | if (stat & STAT_TIME_OUT_RESPONSE) { | |
17b0429d | 323 | cmd->error = -ETIMEDOUT; |
1da177e4 | 324 | } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { |
1da177e4 LT |
325 | /* |
326 | * workaround for erratum #42: | |
327 | * Intel PXA27x Family Processor Specification Update Rev 001 | |
90e07d9f NP |
328 | * A bogus CRC error can appear if the msb of a 136 bit |
329 | * response is a one. | |
1da177e4 | 330 | */ |
e10a854c CB |
331 | if (cpu_is_pxa27x() && |
332 | (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000)) | |
90e07d9f | 333 | pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode); |
e10a854c CB |
334 | else |
335 | cmd->error = -EILSEQ; | |
1da177e4 LT |
336 | } |
337 | ||
338 | pxamci_disable_irq(host, END_CMD_RES); | |
17b0429d | 339 | if (host->data && !cmd->error) { |
1da177e4 | 340 | pxamci_enable_irq(host, DATA_TRAN_DONE); |
b6018958 CB |
341 | /* |
342 | * workaround for erratum #91, if doing write | |
343 | * enable DMA late | |
344 | */ | |
345 | if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE) | |
346 | DCSR(host->dma) = DCSR_RUN; | |
1da177e4 LT |
347 | } else { |
348 | pxamci_finish_request(host, host->mrq); | |
349 | } | |
350 | ||
351 | return 1; | |
352 | } | |
353 | ||
354 | static int pxamci_data_done(struct pxamci_host *host, unsigned int stat) | |
355 | { | |
356 | struct mmc_data *data = host->data; | |
357 | ||
358 | if (!data) | |
359 | return 0; | |
360 | ||
361 | DCSR(host->dma) = 0; | |
c00a46ab | 362 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
1da177e4 LT |
363 | host->dma_dir); |
364 | ||
365 | if (stat & STAT_READ_TIME_OUT) | |
17b0429d | 366 | data->error = -ETIMEDOUT; |
1da177e4 | 367 | else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR)) |
17b0429d | 368 | data->error = -EILSEQ; |
1da177e4 LT |
369 | |
370 | /* | |
371 | * There appears to be a hardware design bug here. There seems to | |
372 | * be no way to find out how much data was transferred to the card. | |
373 | * This means that if there was an error on any block, we mark all | |
374 | * data blocks as being in error. | |
375 | */ | |
17b0429d | 376 | if (!data->error) |
2c171bf1 | 377 | data->bytes_xfered = data->blocks * data->blksz; |
1da177e4 LT |
378 | else |
379 | data->bytes_xfered = 0; | |
380 | ||
381 | pxamci_disable_irq(host, DATA_TRAN_DONE); | |
382 | ||
383 | host->data = NULL; | |
58741e8b | 384 | if (host->mrq->stop) { |
1da177e4 | 385 | pxamci_stop_clock(host); |
df456f47 | 386 | pxamci_start_cmd(host, host->mrq->stop, host->cmdat); |
1da177e4 LT |
387 | } else { |
388 | pxamci_finish_request(host, host->mrq); | |
389 | } | |
390 | ||
391 | return 1; | |
392 | } | |
393 | ||
7d12e780 | 394 | static irqreturn_t pxamci_irq(int irq, void *devid) |
1da177e4 LT |
395 | { |
396 | struct pxamci_host *host = devid; | |
397 | unsigned int ireg; | |
398 | int handled = 0; | |
399 | ||
81ab570f | 400 | ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK); |
1da177e4 | 401 | |
1da177e4 LT |
402 | if (ireg) { |
403 | unsigned stat = readl(host->base + MMC_STAT); | |
404 | ||
d78e9079 | 405 | pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat); |
1da177e4 LT |
406 | |
407 | if (ireg & END_CMD_RES) | |
408 | handled |= pxamci_cmd_done(host, stat); | |
409 | if (ireg & DATA_TRAN_DONE) | |
410 | handled |= pxamci_data_done(host, stat); | |
5d3ad4e8 BW |
411 | if (ireg & SDIO_INT) { |
412 | mmc_signal_sdio_irq(host->mmc); | |
413 | handled = 1; | |
414 | } | |
1da177e4 LT |
415 | } |
416 | ||
417 | return IRQ_RETVAL(handled); | |
418 | } | |
419 | ||
420 | static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq) | |
421 | { | |
422 | struct pxamci_host *host = mmc_priv(mmc); | |
423 | unsigned int cmdat; | |
424 | ||
425 | WARN_ON(host->mrq != NULL); | |
426 | ||
427 | host->mrq = mrq; | |
428 | ||
429 | pxamci_stop_clock(host); | |
430 | ||
431 | cmdat = host->cmdat; | |
432 | host->cmdat &= ~CMDAT_INIT; | |
433 | ||
434 | if (mrq->data) { | |
435 | pxamci_setup_data(host, mrq->data); | |
436 | ||
437 | cmdat &= ~CMDAT_BUSY; | |
438 | cmdat |= CMDAT_DATAEN | CMDAT_DMAEN; | |
439 | if (mrq->data->flags & MMC_DATA_WRITE) | |
440 | cmdat |= CMDAT_WRITE; | |
441 | ||
442 | if (mrq->data->flags & MMC_DATA_STREAM) | |
443 | cmdat |= CMDAT_STREAM; | |
444 | } | |
445 | ||
446 | pxamci_start_cmd(host, mrq->cmd, cmdat); | |
447 | } | |
448 | ||
e619524f RP |
449 | static int pxamci_get_ro(struct mmc_host *mmc) |
450 | { | |
451 | struct pxamci_host *host = mmc_priv(mmc); | |
452 | ||
b405db6c RJ |
453 | if (host->pdata && gpio_is_valid(host->pdata->gpio_card_ro)) { |
454 | if (host->pdata->gpio_card_ro_invert) | |
455 | return !gpio_get_value(host->pdata->gpio_card_ro); | |
456 | else | |
457 | return gpio_get_value(host->pdata->gpio_card_ro); | |
458 | } | |
e619524f | 459 | if (host->pdata && host->pdata->get_ro) |
08f80bb5 AV |
460 | return !!host->pdata->get_ro(mmc_dev(mmc)); |
461 | /* | |
462 | * Board doesn't support read only detection; let the mmc core | |
463 | * decide what to do. | |
464 | */ | |
465 | return -ENOSYS; | |
e619524f RP |
466 | } |
467 | ||
1da177e4 LT |
468 | static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
469 | { | |
470 | struct pxamci_host *host = mmc_priv(mmc); | |
471 | ||
1da177e4 | 472 | if (ios->clock) { |
ebebd9b0 RK |
473 | unsigned long rate = host->clkrate; |
474 | unsigned int clk = rate / ios->clock; | |
475 | ||
d8cb70d1 RK |
476 | if (host->clkrt == CLKRT_OFF) |
477 | clk_enable(host->clk); | |
478 | ||
64eb036a | 479 | if (ios->clock == 26000000) { |
fa3f9938 | 480 | /* to support 26MHz */ |
64eb036a BW |
481 | host->clkrt = 7; |
482 | } else { | |
483 | /* to handle (19.5MHz, 26MHz) */ | |
484 | if (!clk) | |
485 | clk = 1; | |
486 | ||
487 | /* | |
488 | * clk might result in a lower divisor than we | |
489 | * desire. check for that condition and adjust | |
490 | * as appropriate. | |
491 | */ | |
492 | if (rate / clk > ios->clock) | |
493 | clk <<= 1; | |
494 | host->clkrt = fls(clk) - 1; | |
495 | } | |
1da177e4 LT |
496 | |
497 | /* | |
498 | * we write clkrt on the next command | |
499 | */ | |
500 | } else { | |
501 | pxamci_stop_clock(host); | |
d8cb70d1 RK |
502 | if (host->clkrt != CLKRT_OFF) { |
503 | host->clkrt = CLKRT_OFF; | |
504 | clk_disable(host->clk); | |
505 | } | |
1da177e4 LT |
506 | } |
507 | ||
508 | if (host->power_mode != ios->power_mode) { | |
99fc5131 LW |
509 | int ret; |
510 | ||
1da177e4 LT |
511 | host->power_mode = ios->power_mode; |
512 | ||
99fc5131 LW |
513 | ret = pxamci_set_power(host, ios->power_mode, ios->vdd); |
514 | if (ret) { | |
515 | dev_err(mmc_dev(mmc), "unable to set power\n"); | |
516 | /* | |
517 | * The .set_ios() function in the mmc_host_ops | |
518 | * struct return void, and failing to set the | |
519 | * power should be rare so we print an error and | |
520 | * return here. | |
521 | */ | |
522 | return; | |
523 | } | |
1da177e4 LT |
524 | |
525 | if (ios->power_mode == MMC_POWER_ON) | |
526 | host->cmdat |= CMDAT_INIT; | |
527 | } | |
528 | ||
df456f47 BW |
529 | if (ios->bus_width == MMC_BUS_WIDTH_4) |
530 | host->cmdat |= CMDAT_SD_4DAT; | |
531 | else | |
532 | host->cmdat &= ~CMDAT_SD_4DAT; | |
533 | ||
99fc5131 LW |
534 | dev_dbg(mmc_dev(mmc), "PXAMCI: clkrt = %x cmdat = %x\n", |
535 | host->clkrt, host->cmdat); | |
1da177e4 LT |
536 | } |
537 | ||
5d3ad4e8 BW |
538 | static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable) |
539 | { | |
540 | struct pxamci_host *pxa_host = mmc_priv(host); | |
541 | ||
542 | if (enable) | |
543 | pxamci_enable_irq(pxa_host, SDIO_INT); | |
544 | else | |
545 | pxamci_disable_irq(pxa_host, SDIO_INT); | |
546 | } | |
547 | ||
ab7aefd0 | 548 | static const struct mmc_host_ops pxamci_ops = { |
5d3ad4e8 BW |
549 | .request = pxamci_request, |
550 | .get_ro = pxamci_get_ro, | |
551 | .set_ios = pxamci_set_ios, | |
552 | .enable_sdio_irq = pxamci_enable_sdio_irq, | |
1da177e4 LT |
553 | }; |
554 | ||
7d12e780 | 555 | static void pxamci_dma_irq(int dma, void *devid) |
1da177e4 | 556 | { |
c783837b NP |
557 | struct pxamci_host *host = devid; |
558 | int dcsr = DCSR(dma); | |
559 | DCSR(dma) = dcsr & ~DCSR_STOPIRQEN; | |
560 | ||
561 | if (dcsr & DCSR_ENDINTR) { | |
562 | writel(BUF_PART_FULL, host->base + MMC_PRTBUF); | |
563 | } else { | |
a3c76eb9 | 564 | pr_err("%s: DMA error on channel %d (DCSR=%#x)\n", |
c783837b NP |
565 | mmc_hostname(host->mmc), dma, dcsr); |
566 | host->data->error = -EIO; | |
567 | pxamci_data_done(host, 0); | |
568 | } | |
1da177e4 LT |
569 | } |
570 | ||
7d12e780 | 571 | static irqreturn_t pxamci_detect_irq(int irq, void *devid) |
1da177e4 | 572 | { |
c26971cb RP |
573 | struct pxamci_host *host = mmc_priv(devid); |
574 | ||
f97cab28 | 575 | mmc_detect_change(devid, msecs_to_jiffies(host->pdata->detect_delay_ms)); |
1da177e4 LT |
576 | return IRQ_HANDLED; |
577 | } | |
578 | ||
e6027b46 DM |
579 | #ifdef CONFIG_OF |
580 | static const struct of_device_id pxa_mmc_dt_ids[] = { | |
581 | { .compatible = "marvell,pxa-mmc" }, | |
582 | { } | |
583 | }; | |
584 | ||
585 | MODULE_DEVICE_TABLE(of, pxa_mmc_dt_ids); | |
586 | ||
c3be1efd | 587 | static int pxamci_of_init(struct platform_device *pdev) |
e6027b46 DM |
588 | { |
589 | struct device_node *np = pdev->dev.of_node; | |
590 | struct pxamci_platform_data *pdata; | |
591 | u32 tmp; | |
592 | ||
593 | if (!np) | |
594 | return 0; | |
595 | ||
596 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); | |
597 | if (!pdata) | |
598 | return -ENOMEM; | |
599 | ||
600 | pdata->gpio_card_detect = | |
601 | of_get_named_gpio(np, "cd-gpios", 0); | |
602 | pdata->gpio_card_ro = | |
603 | of_get_named_gpio(np, "wp-gpios", 0); | |
604 | ||
605 | /* pxa-mmc specific */ | |
606 | pdata->gpio_power = | |
607 | of_get_named_gpio(np, "pxa-mmc,gpio-power", 0); | |
608 | ||
609 | if (of_property_read_u32(np, "pxa-mmc,detect-delay-ms", &tmp) == 0) | |
610 | pdata->detect_delay_ms = tmp; | |
611 | ||
612 | pdev->dev.platform_data = pdata; | |
613 | ||
614 | return 0; | |
615 | } | |
616 | #else | |
c3be1efd | 617 | static int pxamci_of_init(struct platform_device *pdev) |
e6027b46 DM |
618 | { |
619 | return 0; | |
620 | } | |
621 | #endif | |
622 | ||
3ae5eaec | 623 | static int pxamci_probe(struct platform_device *pdev) |
1da177e4 | 624 | { |
1da177e4 LT |
625 | struct mmc_host *mmc; |
626 | struct pxamci_host *host = NULL; | |
9a788c6b | 627 | struct resource *r, *dmarx, *dmatx; |
b405db6c | 628 | int ret, irq, gpio_cd = -1, gpio_ro = -1, gpio_power = -1; |
1da177e4 | 629 | |
e6027b46 DM |
630 | ret = pxamci_of_init(pdev); |
631 | if (ret) | |
632 | return ret; | |
633 | ||
1da177e4 LT |
634 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
635 | irq = platform_get_irq(pdev, 0); | |
48944738 | 636 | if (!r || irq < 0) |
1da177e4 LT |
637 | return -ENXIO; |
638 | ||
639 | r = request_mem_region(r->start, SZ_4K, DRIVER_NAME); | |
640 | if (!r) | |
641 | return -EBUSY; | |
642 | ||
3ae5eaec | 643 | mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev); |
1da177e4 LT |
644 | if (!mmc) { |
645 | ret = -ENOMEM; | |
646 | goto out; | |
647 | } | |
648 | ||
649 | mmc->ops = &pxamci_ops; | |
1da177e4 LT |
650 | |
651 | /* | |
652 | * We can do SG-DMA, but we don't because we never know how much | |
653 | * data we successfully wrote to the card. | |
654 | */ | |
a36274e0 | 655 | mmc->max_segs = NR_SG; |
1da177e4 LT |
656 | |
657 | /* | |
658 | * Our hardware DMA can handle a maximum of one page per SG entry. | |
659 | */ | |
660 | mmc->max_seg_size = PAGE_SIZE; | |
661 | ||
fe4a3c7a | 662 | /* |
fe2dc44e | 663 | * Block length register is only 10 bits before PXA27x. |
fe4a3c7a | 664 | */ |
0ffcbfd5 | 665 | mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048; |
fe4a3c7a | 666 | |
55db890a PO |
667 | /* |
668 | * Block count register is 16 bits. | |
669 | */ | |
670 | mmc->max_blk_count = 65535; | |
671 | ||
1da177e4 LT |
672 | host = mmc_priv(mmc); |
673 | host->mmc = mmc; | |
674 | host->dma = -1; | |
675 | host->pdata = pdev->dev.platform_data; | |
d8cb70d1 | 676 | host->clkrt = CLKRT_OFF; |
ebebd9b0 | 677 | |
e0d8b13a | 678 | host->clk = clk_get(&pdev->dev, NULL); |
ebebd9b0 RK |
679 | if (IS_ERR(host->clk)) { |
680 | ret = PTR_ERR(host->clk); | |
681 | host->clk = NULL; | |
682 | goto out; | |
683 | } | |
684 | ||
685 | host->clkrate = clk_get_rate(host->clk); | |
686 | ||
687 | /* | |
688 | * Calculate minimum clock rate, rounding up. | |
689 | */ | |
690 | mmc->f_min = (host->clkrate + 63) / 64; | |
fa3f9938 | 691 | mmc->f_max = (mmc_has_26MHz()) ? 26000000 : host->clkrate; |
ebebd9b0 | 692 | |
8385f9cb DR |
693 | pxamci_init_ocr(host); |
694 | ||
df456f47 | 695 | mmc->caps = 0; |
5d3ad4e8 | 696 | host->cmdat = 0; |
0ffcbfd5 | 697 | if (!cpu_is_pxa25x()) { |
5d3ad4e8 BW |
698 | mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; |
699 | host->cmdat |= CMDAT_SDIO_INT_EN; | |
fa3f9938 | 700 | if (mmc_has_26MHz()) |
64eb036a BW |
701 | mmc->caps |= MMC_CAP_MMC_HIGHSPEED | |
702 | MMC_CAP_SD_HIGHSPEED; | |
5d3ad4e8 | 703 | } |
1da177e4 | 704 | |
3ae5eaec | 705 | host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL); |
1da177e4 LT |
706 | if (!host->sg_cpu) { |
707 | ret = -ENOMEM; | |
708 | goto out; | |
709 | } | |
710 | ||
711 | spin_lock_init(&host->lock); | |
712 | host->res = r; | |
713 | host->irq = irq; | |
714 | host->imask = MMC_I_MASK_ALL; | |
715 | ||
716 | host->base = ioremap(r->start, SZ_4K); | |
717 | if (!host->base) { | |
718 | ret = -ENOMEM; | |
719 | goto out; | |
720 | } | |
721 | ||
722 | /* | |
723 | * Ensure that the host controller is shut down, and setup | |
724 | * with our defaults. | |
725 | */ | |
726 | pxamci_stop_clock(host); | |
727 | writel(0, host->base + MMC_SPI); | |
728 | writel(64, host->base + MMC_RESTO); | |
729 | writel(host->imask, host->base + MMC_I_MASK); | |
730 | ||
731 | host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW, | |
732 | pxamci_dma_irq, host); | |
733 | if (host->dma < 0) { | |
734 | ret = -EBUSY; | |
735 | goto out; | |
736 | } | |
737 | ||
738 | ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host); | |
739 | if (ret) | |
740 | goto out; | |
741 | ||
3ae5eaec | 742 | platform_set_drvdata(pdev, mmc); |
1da177e4 | 743 | |
9a788c6b BW |
744 | dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0); |
745 | if (!dmarx) { | |
746 | ret = -ENXIO; | |
747 | goto out; | |
748 | } | |
749 | host->dma_drcmrrx = dmarx->start; | |
750 | ||
751 | dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1); | |
752 | if (!dmatx) { | |
753 | ret = -ENXIO; | |
754 | goto out; | |
755 | } | |
756 | host->dma_drcmrtx = dmatx->start; | |
757 | ||
b405db6c RJ |
758 | if (host->pdata) { |
759 | gpio_cd = host->pdata->gpio_card_detect; | |
760 | gpio_ro = host->pdata->gpio_card_ro; | |
761 | gpio_power = host->pdata->gpio_power; | |
762 | } | |
763 | if (gpio_is_valid(gpio_power)) { | |
764 | ret = gpio_request(gpio_power, "mmc card power"); | |
765 | if (ret) { | |
766 | dev_err(&pdev->dev, "Failed requesting gpio_power %d\n", gpio_power); | |
767 | goto out; | |
768 | } | |
769 | gpio_direction_output(gpio_power, | |
770 | host->pdata->gpio_power_invert); | |
771 | } | |
772 | if (gpio_is_valid(gpio_ro)) { | |
773 | ret = gpio_request(gpio_ro, "mmc card read only"); | |
774 | if (ret) { | |
48f02954 | 775 | dev_err(&pdev->dev, "Failed requesting gpio_ro %d\n", gpio_ro); |
b405db6c RJ |
776 | goto err_gpio_ro; |
777 | } | |
778 | gpio_direction_input(gpio_ro); | |
779 | } | |
780 | if (gpio_is_valid(gpio_cd)) { | |
781 | ret = gpio_request(gpio_cd, "mmc card detect"); | |
782 | if (ret) { | |
48f02954 | 783 | dev_err(&pdev->dev, "Failed requesting gpio_cd %d\n", gpio_cd); |
b405db6c RJ |
784 | goto err_gpio_cd; |
785 | } | |
786 | gpio_direction_input(gpio_cd); | |
787 | ||
788 | ret = request_irq(gpio_to_irq(gpio_cd), pxamci_detect_irq, | |
789 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, | |
790 | "mmc card detect", mmc); | |
791 | if (ret) { | |
792 | dev_err(&pdev->dev, "failed to request card detect IRQ\n"); | |
793 | goto err_request_irq; | |
794 | } | |
795 | } | |
796 | ||
1da177e4 | 797 | if (host->pdata && host->pdata->init) |
3ae5eaec | 798 | host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); |
1da177e4 | 799 | |
b405db6c RJ |
800 | if (gpio_is_valid(gpio_power) && host->pdata->setpower) |
801 | dev_warn(&pdev->dev, "gpio_power and setpower() both defined\n"); | |
802 | if (gpio_is_valid(gpio_ro) && host->pdata->get_ro) | |
803 | dev_warn(&pdev->dev, "gpio_ro and get_ro() both defined\n"); | |
804 | ||
1da177e4 LT |
805 | mmc_add_host(mmc); |
806 | ||
807 | return 0; | |
808 | ||
b405db6c RJ |
809 | err_request_irq: |
810 | gpio_free(gpio_cd); | |
811 | err_gpio_cd: | |
812 | gpio_free(gpio_ro); | |
813 | err_gpio_ro: | |
814 | gpio_free(gpio_power); | |
1da177e4 LT |
815 | out: |
816 | if (host) { | |
817 | if (host->dma >= 0) | |
818 | pxa_free_dma(host->dma); | |
819 | if (host->base) | |
820 | iounmap(host->base); | |
821 | if (host->sg_cpu) | |
3ae5eaec | 822 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
ebebd9b0 RK |
823 | if (host->clk) |
824 | clk_put(host->clk); | |
1da177e4 LT |
825 | } |
826 | if (mmc) | |
827 | mmc_free_host(mmc); | |
828 | release_resource(r); | |
829 | return ret; | |
830 | } | |
831 | ||
3ae5eaec | 832 | static int pxamci_remove(struct platform_device *pdev) |
1da177e4 | 833 | { |
3ae5eaec | 834 | struct mmc_host *mmc = platform_get_drvdata(pdev); |
b405db6c | 835 | int gpio_cd = -1, gpio_ro = -1, gpio_power = -1; |
1da177e4 | 836 | |
1da177e4 LT |
837 | if (mmc) { |
838 | struct pxamci_host *host = mmc_priv(mmc); | |
839 | ||
5d6b1edf DM |
840 | mmc_remove_host(mmc); |
841 | ||
b405db6c RJ |
842 | if (host->pdata) { |
843 | gpio_cd = host->pdata->gpio_card_detect; | |
844 | gpio_ro = host->pdata->gpio_card_ro; | |
845 | gpio_power = host->pdata->gpio_power; | |
846 | } | |
847 | if (gpio_is_valid(gpio_cd)) { | |
848 | free_irq(gpio_to_irq(gpio_cd), mmc); | |
849 | gpio_free(gpio_cd); | |
850 | } | |
851 | if (gpio_is_valid(gpio_ro)) | |
852 | gpio_free(gpio_ro); | |
853 | if (gpio_is_valid(gpio_power)) | |
854 | gpio_free(gpio_power); | |
8385f9cb DR |
855 | if (host->vcc) |
856 | regulator_put(host->vcc); | |
857 | ||
1da177e4 | 858 | if (host->pdata && host->pdata->exit) |
3ae5eaec | 859 | host->pdata->exit(&pdev->dev, mmc); |
1da177e4 | 860 | |
1da177e4 LT |
861 | pxamci_stop_clock(host); |
862 | writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD| | |
863 | END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, | |
864 | host->base + MMC_I_MASK); | |
865 | ||
9a788c6b BW |
866 | DRCMR(host->dma_drcmrrx) = 0; |
867 | DRCMR(host->dma_drcmrtx) = 0; | |
1da177e4 LT |
868 | |
869 | free_irq(host->irq, host); | |
870 | pxa_free_dma(host->dma); | |
871 | iounmap(host->base); | |
3ae5eaec | 872 | dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); |
1da177e4 | 873 | |
ebebd9b0 RK |
874 | clk_put(host->clk); |
875 | ||
1da177e4 LT |
876 | release_resource(host->res); |
877 | ||
878 | mmc_free_host(mmc); | |
879 | } | |
880 | return 0; | |
881 | } | |
882 | ||
3ae5eaec | 883 | static struct platform_driver pxamci_driver = { |
1da177e4 LT |
884 | .probe = pxamci_probe, |
885 | .remove = pxamci_remove, | |
3ae5eaec RK |
886 | .driver = { |
887 | .name = DRIVER_NAME, | |
bc65c724 | 888 | .owner = THIS_MODULE, |
e6027b46 | 889 | .of_match_table = of_match_ptr(pxa_mmc_dt_ids), |
3ae5eaec | 890 | }, |
1da177e4 LT |
891 | }; |
892 | ||
d1f81a64 | 893 | module_platform_driver(pxamci_driver); |
1da177e4 LT |
894 | |
895 | MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver"); | |
896 | MODULE_LICENSE("GPL"); | |
bc65c724 | 897 | MODULE_ALIAS("platform:pxa2xx-mci"); |