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Commit | Line | Data |
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f707079d | 1 | // SPDX-License-Identifier: GPL-2.0 |
a87d5638 | 2 | /* |
9d08428a | 3 | * Renesas SDHI |
a87d5638 | 4 | * |
f49bdcde WS |
5 | * Copyright (C) 2015-19 Renesas Electronics Corporation |
6 | * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang | |
87317c4d | 7 | * Copyright (C) 2016-17 Horms Solutions, Simon Horman |
a87d5638 MD |
8 | * Copyright (C) 2009 Magnus Damm |
9 | * | |
a87d5638 MD |
10 | * Based on "Compaq ASIC3 support": |
11 | * | |
12 | * Copyright 2001 Compaq Computer Corporation. | |
13 | * Copyright 2004-2005 Phil Blundell | |
14 | * Copyright 2007-2008 OpenedHand Ltd. | |
15 | * | |
16 | * Authors: Phil Blundell <pb@handhelds.org>, | |
17 | * Samuel Ortiz <sameo@openedhand.com> | |
18 | * | |
19 | */ | |
20 | ||
a87d5638 | 21 | #include <linux/clk.h> |
ab07a135 | 22 | #include <linux/delay.h> |
b4d86f37 | 23 | #include <linux/iopoll.h> |
ab07a135 WS |
24 | #include <linux/kernel.h> |
25 | #include <linux/mfd/tmio.h> | |
3c49e810 | 26 | #include <linux/mmc/host.h> |
ce6f92c2 | 27 | #include <linux/mmc/mmc.h> |
ef5332c1 | 28 | #include <linux/mmc/slot-gpio.h> |
ab07a135 WS |
29 | #include <linux/module.h> |
30 | #include <linux/of_device.h> | |
057a4592 WS |
31 | #include <linux/pinctrl/consumer.h> |
32 | #include <linux/pinctrl/pinctrl-state.h> | |
ab07a135 WS |
33 | #include <linux/platform_device.h> |
34 | #include <linux/pm_domain.h> | |
057a4592 | 35 | #include <linux/regulator/consumer.h> |
b4d86f37 | 36 | #include <linux/reset.h> |
ab07a135 WS |
37 | #include <linux/sh_dma.h> |
38 | #include <linux/slab.h> | |
164691aa | 39 | #include <linux/sys_soc.h> |
a87d5638 | 40 | |
c2a96987 | 41 | #include "renesas_sdhi.h" |
42051e8a GL |
42 | #include "tmio_mmc.h" |
43 | ||
4533c3eb WS |
44 | #define CTL_HOST_MODE 0xe4 |
45 | #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) | |
46 | #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) | |
47 | #define HOST_MODE_GEN3_WMODE BIT(0) | |
48 | #define HOST_MODE_GEN3_BUSWIDTH BIT(8) | |
49 | ||
50 | #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE | |
51 | #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) | |
52 | #define HOST_MODE_GEN3_64BIT 0 | |
e3c418f1 | 53 | |
0e08a411 WS |
54 | #define CTL_SDIF_MODE 0xe6 |
55 | #define SDIF_MODE_HS400 BIT(0) | |
56 | ||
a2a16c77 | 57 | #define SDHI_VER_GEN2_SDR50 0x490c |
c7825151 | 58 | #define SDHI_VER_RZ_A1 0x820b |
a2a16c77 WS |
59 | /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ |
60 | #define SDHI_VER_GEN2_SDR104 0xcb0d | |
61 | #define SDHI_VER_GEN3_SD 0xcc10 | |
62 | #define SDHI_VER_GEN3_SDMMC 0xcd10 | |
63 | ||
ce6f92c2 WS |
64 | #define SDHI_GEN3_MMC0_ADDR 0xee140000 |
65 | ||
b5b6a5f4 | 66 | static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) |
f45394d5 KM |
67 | { |
68 | u32 val; | |
69 | ||
70 | /* | |
71 | * see also | |
b5b6a5f4 | 72 | * renesas_sdhi_of_data :: dma_buswidth |
f45394d5 KM |
73 | */ |
74 | switch (sd_ctrl_read16(host, CTL_VERSION)) { | |
a2a16c77 | 75 | case SDHI_VER_GEN2_SDR50: |
4533c3eb | 76 | val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; |
f45394d5 | 77 | break; |
a2a16c77 | 78 | case SDHI_VER_GEN2_SDR104: |
4533c3eb | 79 | val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; |
f45394d5 | 80 | break; |
a2a16c77 WS |
81 | case SDHI_VER_GEN3_SD: |
82 | case SDHI_VER_GEN3_SDMMC: | |
a72e8b17 | 83 | if (width == 64) |
4533c3eb | 84 | val = HOST_MODE_GEN3_64BIT; |
a72e8b17 | 85 | else if (width == 32) |
4533c3eb | 86 | val = HOST_MODE_GEN3_32BIT; |
a72e8b17 | 87 | else |
4533c3eb | 88 | val = HOST_MODE_GEN3_16BIT; |
a72e8b17 | 89 | break; |
f45394d5 KM |
90 | default: |
91 | /* nothing to do */ | |
92 | return; | |
93 | } | |
94 | ||
4533c3eb | 95 | sd_ctrl_write16(host, CTL_HOST_MODE, val); |
f45394d5 KM |
96 | } |
97 | ||
b5b6a5f4 | 98 | static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) |
56c49287 | 99 | { |
0ea28210 | 100 | struct mmc_host *mmc = host->mmc; |
b5b6a5f4 | 101 | struct renesas_sdhi *priv = host_to_priv(host); |
d42c9fff | 102 | int ret; |
56c49287 | 103 | |
34a16547 | 104 | ret = clk_prepare_enable(priv->clk_cd); |
d42c9fff | 105 | if (ret < 0) |
34a16547 | 106 | return ret; |
34a16547 | 107 | |
2fb55956 BH |
108 | /* |
109 | * The clock driver may not know what maximum frequency | |
110 | * actually works, so it should be set with the max-frequency | |
111 | * property which will already have been read to f_max. If it | |
112 | * was missing, assume the current frequency is the maximum. | |
113 | */ | |
114 | if (!mmc->f_max) | |
115 | mmc->f_max = clk_get_rate(priv->clk); | |
116 | ||
117 | /* | |
118 | * Minimum frequency is the minimum input clock frequency | |
119 | * divided by our maximum divider. | |
120 | */ | |
121 | mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); | |
f45394d5 KM |
122 | |
123 | /* enable 16bit data access on SDBUF as default */ | |
b5b6a5f4 | 124 | renesas_sdhi_sdbuf_width(host, 16); |
f45394d5 | 125 | |
56c49287 GL |
126 | return 0; |
127 | } | |
128 | ||
b5b6a5f4 | 129 | static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, |
2fe35968 | 130 | unsigned int new_clock) |
2fb55956 | 131 | { |
b5b6a5f4 | 132 | struct renesas_sdhi *priv = host_to_priv(host); |
3072ba8c | 133 | unsigned int freq, diff, best_freq = 0, diff_min = ~0; |
75eaf49f | 134 | int i; |
2fb55956 | 135 | |
0f93db65 WS |
136 | /* |
137 | * We simply return the current rate if a) we are not on a R-Car Gen2+ | |
138 | * SoC (may work for others, but untested) or b) if the SCC needs its | |
139 | * clock during tuning, so we don't change the external clock setup. | |
140 | */ | |
141 | if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) | |
8fc00998 WS |
142 | return clk_get_rate(priv->clk); |
143 | ||
2fb55956 BH |
144 | /* |
145 | * We want the bus clock to be as close as possible to, but no | |
146 | * greater than, new_clock. As we can divide by 1 << i for | |
147 | * any i in [0, 9] we want the input clock to be as close as | |
148 | * possible, but no greater than, new_clock << i. | |
149 | */ | |
150 | for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { | |
151 | freq = clk_round_rate(priv->clk, new_clock << i); | |
152 | if (freq > (new_clock << i)) { | |
153 | /* Too fast; look for a slightly slower option */ | |
154 | freq = clk_round_rate(priv->clk, | |
155 | (new_clock << i) / 4 * 3); | |
156 | if (freq > (new_clock << i)) | |
157 | continue; | |
158 | } | |
159 | ||
160 | diff = new_clock - (freq >> i); | |
161 | if (diff <= diff_min) { | |
162 | best_freq = freq; | |
163 | diff_min = diff; | |
164 | } | |
165 | } | |
166 | ||
75eaf49f | 167 | clk_set_rate(priv->clk, best_freq); |
2fb55956 | 168 | |
75eaf49f | 169 | return clk_get_rate(priv->clk); |
2fb55956 BH |
170 | } |
171 | ||
68f83127 MY |
172 | static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, |
173 | unsigned int new_clock) | |
0196c8db | 174 | { |
68f83127 | 175 | u32 clk = 0, clock; |
0196c8db | 176 | |
0196c8db MY |
177 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & |
178 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
179 | ||
75eaf49f TS |
180 | if (new_clock == 0) { |
181 | host->mmc->actual_clock = 0; | |
68f83127 | 182 | goto out; |
75eaf49f | 183 | } |
0196c8db | 184 | |
75eaf49f TS |
185 | host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); |
186 | clock = host->mmc->actual_clock / 512; | |
0196c8db MY |
187 | |
188 | for (clk = 0x80000080; new_clock >= (clock << 1); clk >>= 1) | |
189 | clock <<= 1; | |
190 | ||
191 | /* 1/1 clock is option */ | |
192 | if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { | |
193 | if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) | |
194 | clk |= 0xff; | |
195 | else | |
196 | clk &= ~0xff; | |
197 | } | |
198 | ||
0196c8db MY |
199 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clk & CLK_CTL_DIV_MASK); |
200 | if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) | |
201 | usleep_range(10000, 11000); | |
202 | ||
68f83127 MY |
203 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | |
204 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
205 | ||
206 | out: | |
207 | /* HW engineers overrode docs: no sleep needed on R-Car2+ */ | |
208 | if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) | |
209 | usleep_range(10000, 11000); | |
0196c8db MY |
210 | } |
211 | ||
b5b6a5f4 | 212 | static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) |
56c49287 | 213 | { |
b5b6a5f4 | 214 | struct renesas_sdhi *priv = host_to_priv(host); |
0ea28210 | 215 | |
34a16547 | 216 | clk_disable_unprepare(priv->clk_cd); |
56c49287 GL |
217 | } |
218 | ||
b5b6a5f4 | 219 | static int renesas_sdhi_card_busy(struct mmc_host *mmc) |
6a4679f3 WS |
220 | { |
221 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
222 | ||
2fe35968 SH |
223 | return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & |
224 | TMIO_STAT_DAT0); | |
6a4679f3 WS |
225 | } |
226 | ||
b5b6a5f4 | 227 | static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, |
2fe35968 | 228 | struct mmc_ios *ios) |
057a4592 WS |
229 | { |
230 | struct tmio_mmc_host *host = mmc_priv(mmc); | |
b5b6a5f4 | 231 | struct renesas_sdhi *priv = host_to_priv(host); |
057a4592 WS |
232 | struct pinctrl_state *pin_state; |
233 | int ret; | |
234 | ||
235 | switch (ios->signal_voltage) { | |
236 | case MMC_SIGNAL_VOLTAGE_330: | |
237 | pin_state = priv->pins_default; | |
238 | break; | |
239 | case MMC_SIGNAL_VOLTAGE_180: | |
240 | pin_state = priv->pins_uhs; | |
241 | break; | |
242 | default: | |
243 | return -EINVAL; | |
244 | } | |
245 | ||
246 | /* | |
247 | * If anything is missing, assume signal voltage is fixed at | |
248 | * 3.3V and succeed/fail accordingly. | |
249 | */ | |
250 | if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) | |
251 | return ios->signal_voltage == | |
252 | MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; | |
253 | ||
254 | ret = mmc_regulator_set_vqmmc(host->mmc, ios); | |
9cbe0fc8 | 255 | if (ret < 0) |
057a4592 WS |
256 | return ret; |
257 | ||
2272c841 | 258 | return pinctrl_select_state(priv->pinctrl, pin_state); |
057a4592 WS |
259 | } |
260 | ||
06f438dd SH |
261 | /* SCC registers */ |
262 | #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 | |
263 | #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 | |
264 | #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 | |
265 | #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 | |
266 | #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 | |
267 | #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A | |
71cfc927 | 268 | #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C |
26eb2607 | 269 | #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E |
ce6f92c2 WS |
270 | #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 |
271 | #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 | |
272 | #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 | |
273 | #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A | |
274 | #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C | |
06f438dd | 275 | |
06f438dd SH |
276 | #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) |
277 | #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 | |
278 | #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff | |
279 | ||
06f438dd | 280 | #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) |
6199a10e | 281 | |
06f438dd | 282 | #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) |
6199a10e | 283 | |
11a21960 | 284 | #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) |
6199a10e WS |
285 | #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) |
286 | #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) | |
287 | ||
71cfc927 | 288 | #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) |
6199a10e WS |
289 | #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) |
290 | #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) | |
291 | ||
26eb2607 MH |
292 | #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) |
293 | #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) | |
06f438dd | 294 | |
ce6f92c2 WS |
295 | /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ |
296 | #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) | |
297 | ||
298 | /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ | |
299 | #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) | |
300 | #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) | |
301 | #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F | |
302 | ||
303 | /* Definitions for values the SH_MOBILE_SDHI_SCC register */ | |
304 | #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 | |
305 | #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f | |
306 | #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) | |
307 | ||
06f438dd | 308 | static inline u32 sd_scc_read32(struct tmio_mmc_host *host, |
b5b6a5f4 | 309 | struct renesas_sdhi *priv, int addr) |
06f438dd SH |
310 | { |
311 | return readl(priv->scc_ctl + (addr << host->bus_shift)); | |
312 | } | |
313 | ||
314 | static inline void sd_scc_write32(struct tmio_mmc_host *host, | |
b5b6a5f4 | 315 | struct renesas_sdhi *priv, |
06f438dd SH |
316 | int addr, u32 val) |
317 | { | |
318 | writel(val, priv->scc_ctl + (addr << host->bus_shift)); | |
319 | } | |
320 | ||
b5b6a5f4 | 321 | static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) |
06f438dd | 322 | { |
b5b6a5f4 | 323 | struct renesas_sdhi *priv; |
06f438dd | 324 | |
06f438dd SH |
325 | priv = host_to_priv(host); |
326 | ||
06f438dd SH |
327 | /* Initialize SCC */ |
328 | sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); | |
329 | ||
06f438dd SH |
330 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & |
331 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
332 | ||
26eb2607 MH |
333 | /* set sampling clock selection range */ |
334 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, | |
335 | SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | | |
336 | 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); | |
337 | ||
06f438dd SH |
338 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, |
339 | SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | | |
340 | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); | |
341 | ||
06f438dd SH |
342 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, |
343 | ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & | |
344 | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); | |
345 | ||
852d258f | 346 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); |
06f438dd | 347 | |
26eb2607 MH |
348 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | |
349 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
350 | ||
06f438dd SH |
351 | /* Read TAPNUM */ |
352 | return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> | |
353 | SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & | |
354 | SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; | |
355 | } | |
356 | ||
f22084b6 | 357 | static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) |
26eb2607 | 358 | { |
f22084b6 | 359 | struct tmio_mmc_host *host = mmc_priv(mmc); |
26eb2607 | 360 | struct renesas_sdhi *priv = host_to_priv(host); |
a38c078f TS |
361 | u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; |
362 | bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; | |
26eb2607 MH |
363 | |
364 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & | |
365 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
366 | ||
367 | /* Set HS400 mode */ | |
0e08a411 | 368 | sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | |
26eb2607 | 369 | sd_ctrl_read16(host, CTL_SDIF_MODE)); |
f0c8234c TS |
370 | |
371 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, | |
372 | priv->scc_tappos_hs400); | |
373 | ||
9b0d6855 WS |
374 | /* Gen3 can't do automatic tap correction with HS400, so disable it */ |
375 | if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC) | |
376 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, | |
377 | ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & | |
378 | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); | |
379 | ||
26eb2607 MH |
380 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, |
381 | (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | | |
382 | SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | | |
383 | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); | |
384 | ||
26eb2607 MH |
385 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, |
386 | SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | | |
eb2334c4 WS |
387 | sd_scc_read32(host, priv, |
388 | SH_MOBILE_SDHI_SCC_DTCNTL)); | |
26eb2607 | 389 | |
a38c078f TS |
390 | /* Avoid bad TAP */ |
391 | if (bad_taps & BIT(priv->tap_set)) { | |
392 | u32 new_tap = (priv->tap_set + 1) % priv->tap_num; | |
393 | ||
394 | if (bad_taps & BIT(new_tap)) | |
395 | new_tap = (priv->tap_set - 1) % priv->tap_num; | |
26eb2607 | 396 | |
a38c078f TS |
397 | if (bad_taps & BIT(new_tap)) { |
398 | new_tap = priv->tap_set; | |
399 | dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); | |
400 | } | |
401 | ||
402 | priv->tap_set = new_tap; | |
403 | } | |
404 | ||
405 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, | |
406 | priv->tap_set / (use_4tap ? 2 : 1)); | |
26eb2607 MH |
407 | |
408 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, | |
409 | SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | | |
410 | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); | |
411 | ||
412 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | | |
413 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
ce6f92c2 WS |
414 | |
415 | if (priv->adjust_hs400_calib_table) | |
416 | priv->needs_adjust_hs400 = true; | |
26eb2607 MH |
417 | } |
418 | ||
80d0be81 | 419 | static void renesas_sdhi_disable_scc(struct mmc_host *mmc) |
26eb2607 | 420 | { |
80d0be81 WS |
421 | struct tmio_mmc_host *host = mmc_priv(mmc); |
422 | struct renesas_sdhi *priv = host_to_priv(host); | |
423 | ||
26eb2607 MH |
424 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & |
425 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
426 | ||
427 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, | |
428 | ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & | |
429 | sd_scc_read32(host, priv, | |
430 | SH_MOBILE_SDHI_SCC_CKSEL)); | |
26eb2607 MH |
431 | |
432 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, | |
433 | ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & | |
434 | sd_scc_read32(host, priv, | |
435 | SH_MOBILE_SDHI_SCC_DTCNTL)); | |
436 | ||
437 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | | |
438 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
439 | } | |
440 | ||
ce6f92c2 WS |
441 | static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, |
442 | struct renesas_sdhi *priv, u32 addr) | |
443 | { | |
444 | /* read mode */ | |
445 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, | |
446 | SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | | |
447 | (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); | |
448 | ||
449 | /* access start and stop */ | |
450 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, | |
451 | SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); | |
452 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); | |
453 | ||
454 | return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); | |
455 | } | |
456 | ||
457 | static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, | |
458 | struct renesas_sdhi *priv, u32 addr, u32 val) | |
459 | { | |
460 | /* write mode */ | |
461 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, | |
462 | SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | | |
463 | (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); | |
464 | ||
465 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); | |
466 | ||
467 | /* access start and stop */ | |
468 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, | |
469 | SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); | |
470 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); | |
471 | } | |
472 | ||
473 | static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) | |
474 | { | |
475 | struct renesas_sdhi *priv = host_to_priv(host); | |
476 | u32 calib_code; | |
477 | ||
478 | /* disable write protect */ | |
479 | sd_scc_tmpport_write32(host, priv, 0x00, | |
480 | SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); | |
481 | /* read calibration code and adjust */ | |
482 | calib_code = sd_scc_tmpport_read32(host, priv, 0x26); | |
483 | calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; | |
484 | ||
485 | sd_scc_tmpport_write32(host, priv, 0x22, | |
486 | SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | | |
487 | priv->adjust_hs400_calib_table[calib_code]); | |
488 | ||
489 | /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ | |
490 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); | |
491 | ||
492 | /* adjustment done, clear flag */ | |
493 | priv->needs_adjust_hs400 = false; | |
494 | } | |
495 | ||
496 | static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) | |
497 | { | |
498 | struct renesas_sdhi *priv = host_to_priv(host); | |
499 | ||
500 | /* disable write protect */ | |
501 | sd_scc_tmpport_write32(host, priv, 0x00, | |
502 | SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); | |
503 | /* disable manual calibration */ | |
504 | sd_scc_tmpport_write32(host, priv, 0x22, 0); | |
505 | /* clear offset value of TMPPORT3 */ | |
506 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); | |
507 | } | |
508 | ||
26eb2607 MH |
509 | static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, |
510 | struct renesas_sdhi *priv) | |
511 | { | |
512 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & | |
513 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
514 | ||
515 | /* Reset HS400 mode */ | |
0e08a411 | 516 | sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & |
26eb2607 | 517 | sd_ctrl_read16(host, CTL_SDIF_MODE)); |
f0c8234c TS |
518 | |
519 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); | |
520 | ||
26eb2607 MH |
521 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, |
522 | ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | | |
523 | SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & | |
524 | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); | |
525 | ||
ce6f92c2 WS |
526 | if (priv->adjust_hs400_calib_table) |
527 | renesas_sdhi_adjust_hs400_mode_disable(host); | |
528 | ||
26eb2607 MH |
529 | sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | |
530 | sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); | |
531 | } | |
532 | ||
f22084b6 | 533 | static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) |
26eb2607 | 534 | { |
f22084b6 WS |
535 | struct tmio_mmc_host *host = mmc_priv(mmc); |
536 | ||
26eb2607 | 537 | renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); |
f22084b6 | 538 | return 0; |
26eb2607 MH |
539 | } |
540 | ||
0e587014 WS |
541 | static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) |
542 | { | |
543 | renesas_sdhi_disable_scc(host->mmc); | |
544 | renesas_sdhi_reset_hs400_mode(host, priv); | |
545 | priv->needs_adjust_hs400 = false; | |
546 | ||
547 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, | |
548 | ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & | |
549 | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); | |
550 | } | |
551 | ||
9f809065 | 552 | /* only populated for TMIO_MMC_MIN_RCAR2 */ |
5b0739d7 WS |
553 | static void renesas_sdhi_reset(struct tmio_mmc_host *host) |
554 | { | |
555 | struct renesas_sdhi *priv = host_to_priv(host); | |
b4d86f37 | 556 | int ret; |
b191dece | 557 | u16 val; |
5b0739d7 | 558 | |
b4d86f37 WS |
559 | if (priv->rstc) { |
560 | reset_control_reset(priv->rstc); | |
561 | /* Unknown why but without polling reset status, it will hang */ | |
562 | read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, | |
563 | false, priv->rstc); | |
b81bede4 WS |
564 | /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ |
565 | sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); | |
b4d86f37 WS |
566 | priv->needs_adjust_hs400 = false; |
567 | renesas_sdhi_set_clock(host, host->clk_cache); | |
568 | } else if (priv->scc_ctl) { | |
0e587014 | 569 | renesas_sdhi_scc_reset(host, priv); |
b4d86f37 | 570 | } |
5b0739d7 | 571 | |
b191dece WS |
572 | if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { |
573 | val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); | |
574 | val |= CARD_OPT_EXTOP; | |
575 | sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); | |
576 | } | |
577 | } | |
578 | ||
579 | static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) | |
580 | { | |
581 | u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); | |
582 | ||
583 | num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; | |
584 | return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); | |
585 | ||
5b0739d7 WS |
586 | } |
587 | ||
ec4fc1ac | 588 | #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 |
06f438dd | 589 | |
b5b6a5f4 | 590 | static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) |
06f438dd | 591 | { |
b5b6a5f4 | 592 | struct renesas_sdhi *priv = host_to_priv(host); |
92fa2a56 | 593 | unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; |
5fb6bf51 WS |
594 | unsigned int taps_size = priv->tap_num * 2, min_tap_row; |
595 | unsigned long *bitmap; | |
06f438dd | 596 | |
06f438dd SH |
597 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); |
598 | ||
5c99826b NS |
599 | /* |
600 | * When tuning CMD19 is issued twice for each tap, merge the | |
601 | * result requiring the tap to be good in both runs before | |
602 | * considering it for tuning selection. | |
603 | */ | |
92fa2a56 | 604 | for (i = 0; i < taps_size; i++) { |
b2dd9a13 | 605 | int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); |
5c99826b | 606 | |
b2dd9a13 WS |
607 | if (!test_bit(i, priv->taps)) |
608 | clear_bit(i + offset, priv->taps); | |
5fb6bf51 WS |
609 | |
610 | if (!test_bit(i, priv->smpcmp)) | |
611 | clear_bit(i + offset, priv->smpcmp); | |
612 | } | |
613 | ||
614 | /* | |
615 | * If all TAP are OK, the sampling clock position is selected by | |
616 | * identifying the change point of data. | |
617 | */ | |
618 | if (bitmap_full(priv->taps, taps_size)) { | |
619 | bitmap = priv->smpcmp; | |
620 | min_tap_row = 1; | |
621 | } else { | |
622 | bitmap = priv->taps; | |
623 | min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; | |
5c99826b NS |
624 | } |
625 | ||
06f438dd | 626 | /* |
ec4fc1ac WS |
627 | * Find the longest consecutive run of successful probes. If that |
628 | * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the | |
629 | * center index as the tap, otherwise bail out. | |
06f438dd | 630 | */ |
5fb6bf51 | 631 | bitmap_for_each_set_region(bitmap, rs, re, 0, taps_size) { |
92fa2a56 WS |
632 | if (re - rs > tap_cnt) { |
633 | tap_end = re; | |
634 | tap_start = rs; | |
635 | tap_cnt = tap_end - tap_start; | |
06f438dd SH |
636 | } |
637 | } | |
638 | ||
5fb6bf51 | 639 | if (tap_cnt >= min_tap_row) |
b2dd9a13 | 640 | priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; |
06f438dd SH |
641 | else |
642 | return -EIO; | |
643 | ||
644 | /* Set SCC */ | |
b2dd9a13 | 645 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); |
06f438dd SH |
646 | |
647 | /* Enable auto re-tuning */ | |
648 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, | |
649 | SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN | | |
650 | sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
510bfe58 | 655 | static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) |
0c482d82 | 656 | { |
510bfe58 | 657 | struct tmio_mmc_host *host = mmc_priv(mmc); |
0c482d82 | 658 | struct renesas_sdhi *priv = host_to_priv(host); |
5b0739d7 | 659 | int i, ret; |
0c482d82 | 660 | |
b2dd9a13 WS |
661 | priv->tap_num = renesas_sdhi_init_tuning(host); |
662 | if (!priv->tap_num) | |
0c482d82 WS |
663 | return 0; /* Tuning is not supported */ |
664 | ||
b2dd9a13 | 665 | if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { |
3a821a82 WS |
666 | dev_err(&host->pdev->dev, |
667 | "Too many taps, please update 'taps' in tmio_mmc_host!\n"); | |
668 | return -EINVAL; | |
0c482d82 WS |
669 | } |
670 | ||
b2dd9a13 | 671 | bitmap_zero(priv->taps, priv->tap_num * 2); |
5fb6bf51 | 672 | bitmap_zero(priv->smpcmp, priv->tap_num * 2); |
0c482d82 WS |
673 | |
674 | /* Issue CMD19 twice for each tap */ | |
b2dd9a13 | 675 | for (i = 0; i < 2 * priv->tap_num; i++) { |
4271a070 | 676 | int cmd_error = 0; |
2c9017d0 | 677 | |
0c482d82 | 678 | /* Set sampling clock position */ |
b2dd9a13 | 679 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); |
0c482d82 | 680 | |
2c9017d0 | 681 | if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) |
b2dd9a13 | 682 | set_bit(i, priv->taps); |
5fb6bf51 WS |
683 | |
684 | if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) | |
685 | set_bit(i, priv->smpcmp); | |
2c9017d0 WS |
686 | |
687 | if (cmd_error) | |
21adc2e4 | 688 | mmc_send_abort_tuning(mmc, opcode); |
0c482d82 WS |
689 | } |
690 | ||
5b0739d7 WS |
691 | ret = renesas_sdhi_select_tuning(host); |
692 | if (ret < 0) | |
0e587014 | 693 | renesas_sdhi_scc_reset(host, priv); |
5b0739d7 | 694 | return ret; |
0c482d82 WS |
695 | } |
696 | ||
11a21960 TS |
697 | static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) |
698 | { | |
699 | struct renesas_sdhi *priv = host_to_priv(host); | |
a38c078f | 700 | unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; |
11a21960 TS |
701 | u32 val; |
702 | ||
703 | val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); | |
704 | if (!val) | |
705 | return false; | |
706 | ||
707 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); | |
708 | ||
709 | /* Change TAP position according to correction status */ | |
71cfc927 TS |
710 | if (sd_ctrl_read16(host, CTL_VERSION) == SDHI_VER_GEN3_SDMMC && |
711 | host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { | |
a38c078f | 712 | u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; |
71cfc927 TS |
713 | /* |
714 | * With HS400, the DAT signal is based on DS, not CLK. | |
715 | * Therefore, use only CMD status. | |
716 | */ | |
717 | u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & | |
718 | SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; | |
a38c078f | 719 | if (!smpcmp) { |
71cfc927 | 720 | return false; /* no error in CMD signal */ |
a38c078f | 721 | } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { |
71cfc927 | 722 | new_tap++; |
a38c078f TS |
723 | error_tap--; |
724 | } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { | |
71cfc927 | 725 | new_tap--; |
a38c078f TS |
726 | error_tap++; |
727 | } else { | |
71cfc927 | 728 | return true; /* need retune */ |
a38c078f TS |
729 | } |
730 | ||
731 | /* | |
732 | * When new_tap is a bad tap, we cannot change. Then, we compare | |
733 | * with the HS200 tuning result. When smpcmp[error_tap] is OK, | |
734 | * we can at least retune. | |
735 | */ | |
736 | if (bad_taps & BIT(new_tap % priv->tap_num)) | |
737 | return test_bit(error_tap % priv->tap_num, priv->smpcmp); | |
71cfc927 TS |
738 | } else { |
739 | if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) | |
740 | return true; /* need retune */ | |
741 | else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) | |
742 | new_tap++; | |
743 | else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) | |
744 | new_tap--; | |
745 | else | |
746 | return false; | |
747 | } | |
11a21960 | 748 | |
b2dd9a13 | 749 | priv->tap_set = (new_tap % priv->tap_num); |
11a21960 | 750 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, |
b2dd9a13 | 751 | priv->tap_set / (use_4tap ? 2 : 1)); |
11a21960 TS |
752 | |
753 | return false; | |
754 | } | |
755 | ||
756 | static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) | |
757 | { | |
758 | struct renesas_sdhi *priv = host_to_priv(host); | |
759 | ||
760 | /* Check SCC error */ | |
761 | if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & | |
762 | SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { | |
763 | sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); | |
764 | return true; | |
765 | } | |
766 | ||
767 | return false; | |
768 | } | |
769 | ||
ed2fab9a YS |
770 | static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, |
771 | struct mmc_request *mrq) | |
06f438dd | 772 | { |
b5b6a5f4 | 773 | struct renesas_sdhi *priv = host_to_priv(host); |
12e3c55d | 774 | bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; |
ed2fab9a | 775 | bool ret = false; |
75f349a1 MH |
776 | |
777 | /* | |
778 | * Skip checking SCC errors when running on 4 taps in HS400 mode as | |
779 | * any retuning would still result in the same 4 taps being used. | |
780 | */ | |
781 | if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && | |
782 | !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && | |
783 | !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) | |
784 | return false; | |
785 | ||
fbb31330 | 786 | if (mmc_doing_tune(host->mmc)) |
75f349a1 | 787 | return false; |
06f438dd | 788 | |
ed2fab9a YS |
789 | if (((mrq->cmd->error == -ETIMEDOUT) || |
790 | (mrq->data && mrq->data->error == -ETIMEDOUT)) && | |
791 | ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || | |
792 | (host->ops.get_cd && host->ops.get_cd(host->mmc)))) | |
793 | ret |= true; | |
794 | ||
06f438dd | 795 | if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & |
11a21960 | 796 | SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) |
ed2fab9a YS |
797 | ret |= renesas_sdhi_auto_correction(host); |
798 | else | |
799 | ret |= renesas_sdhi_manual_correction(host, use_4tap); | |
06f438dd | 800 | |
ed2fab9a | 801 | return ret; |
06f438dd SH |
802 | } |
803 | ||
4dc48a95 | 804 | static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) |
973ed3af SH |
805 | { |
806 | int timeout = 1000; | |
4dc48a95 WS |
807 | /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ |
808 | u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); | |
973ed3af | 809 | |
4dc48a95 WS |
810 | while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) |
811 | & bit) == wait_state) | |
973ed3af SH |
812 | udelay(1); |
813 | ||
814 | if (!timeout) { | |
94b110af | 815 | dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); |
973ed3af SH |
816 | return -EBUSY; |
817 | } | |
818 | ||
819 | return 0; | |
820 | } | |
821 | ||
b5b6a5f4 | 822 | static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) |
973ed3af | 823 | { |
4dc48a95 WS |
824 | u32 bit = TMIO_STAT_SCLKDIVEN; |
825 | ||
2fe35968 | 826 | switch (addr) { |
973ed3af SH |
827 | case CTL_SD_CMD: |
828 | case CTL_STOP_INTERNAL_ACTION: | |
829 | case CTL_XFER_BLK_COUNT: | |
973ed3af SH |
830 | case CTL_SD_XFER_LEN: |
831 | case CTL_SD_MEM_CARD_OPT: | |
832 | case CTL_TRANSACTION_CTL: | |
833 | case CTL_DMA_ENABLE: | |
4533c3eb | 834 | case CTL_HOST_MODE: |
5124b592 | 835 | if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) |
4dc48a95 | 836 | bit = TMIO_STAT_CMD_BUSY; |
df561f66 | 837 | fallthrough; |
4dc48a95 WS |
838 | case CTL_SD_CARD_CLK_CTL: |
839 | return renesas_sdhi_wait_idle(host, bit); | |
973ed3af SH |
840 | } |
841 | ||
842 | return 0; | |
843 | } | |
844 | ||
b5b6a5f4 | 845 | static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, |
2fe35968 | 846 | unsigned int direction, int blk_size) |
8b4efe2f KM |
847 | { |
848 | /* | |
849 | * In Renesas controllers, when performing a | |
850 | * multiple block read of one or two blocks, | |
851 | * depending on the timing with which the | |
852 | * response register is read, the response | |
853 | * value may not be read properly. | |
854 | * Use single block read for this HW bug | |
855 | */ | |
856 | if ((direction == MMC_DATA_READ) && | |
857 | blk_size == 2) | |
858 | return 1; | |
859 | ||
860 | return blk_size; | |
861 | } | |
862 | ||
ce6f92c2 WS |
863 | static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) |
864 | { | |
865 | struct renesas_sdhi *priv = host_to_priv(host); | |
866 | ||
867 | if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) | |
868 | renesas_sdhi_adjust_hs400_mode_enable(host); | |
869 | } | |
b5b6a5f4 | 870 | static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) |
0c47f6ae | 871 | { |
41279f01 WS |
872 | /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ |
873 | int width = (host->bus_shift == 2) ? 64 : 32; | |
f45394d5 | 874 | |
41279f01 WS |
875 | sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); |
876 | renesas_sdhi_sdbuf_width(host, enable ? width : 16); | |
0c47f6ae KM |
877 | } |
878 | ||
9d08428a | 879 | int renesas_sdhi_probe(struct platform_device *pdev, |
71b7597c YS |
880 | const struct tmio_mmc_dma_ops *dma_ops, |
881 | const struct renesas_sdhi_of_data *of_data, | |
882 | const struct renesas_sdhi_quirks *quirks) | |
a87d5638 | 883 | { |
f33c9d65 | 884 | struct tmio_mmc_data *mmd = pdev->dev.platform_data; |
2fe35968 SH |
885 | struct tmio_mmc_data *mmc_data; |
886 | struct tmio_mmc_dma *dma_priv; | |
42051e8a | 887 | struct tmio_mmc_host *host; |
2fe35968 | 888 | struct renesas_sdhi *priv; |
e8307ec5 | 889 | int num_irqs, irq, ret, i; |
3b159a6e | 890 | struct resource *res; |
c9a9497c | 891 | u16 ver; |
2fe35968 | 892 | |
3b159a6e KM |
893 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
894 | if (!res) | |
895 | return -EINVAL; | |
896 | ||
2fe35968 SH |
897 | priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), |
898 | GFP_KERNEL); | |
2bf8ab6b | 899 | if (!priv) |
a87d5638 | 900 | return -ENOMEM; |
a87d5638 | 901 | |
7af08206 | 902 | priv->quirks = quirks; |
056676da | 903 | mmc_data = &priv->mmc_data; |
87ae7bbe | 904 | dma_priv = &priv->dma_priv; |
056676da | 905 | |
ac51b961 | 906 | priv->clk = devm_clk_get(&pdev->dev, NULL); |
a87d5638 | 907 | if (IS_ERR(priv->clk)) { |
a87d5638 | 908 | ret = PTR_ERR(priv->clk); |
56ae1adc | 909 | dev_err(&pdev->dev, "cannot get clock: %d\n", ret); |
4ce62817 | 910 | return ret; |
a87d5638 MD |
911 | } |
912 | ||
34a16547 CB |
913 | /* |
914 | * Some controllers provide a 2nd clock just to run the internal card | |
915 | * detection logic. Unfortunately, the existing driver architecture does | |
916 | * not support a separation of clocks for runtime PM usage. When | |
917 | * native hotplug is used, the tmio driver assumes that the core | |
918 | * must continue to run for card detect to stay active, so we cannot | |
919 | * disable it. | |
920 | * Additionally, it is prohibited to supply a clock to the core but not | |
921 | * to the card detect circuit. That leaves us with if separate clocks | |
922 | * are presented, we must treat them both as virtually 1 clock. | |
923 | */ | |
924 | priv->clk_cd = devm_clk_get(&pdev->dev, "cd"); | |
925 | if (IS_ERR(priv->clk_cd)) | |
926 | priv->clk_cd = NULL; | |
927 | ||
057a4592 WS |
928 | priv->pinctrl = devm_pinctrl_get(&pdev->dev); |
929 | if (!IS_ERR(priv->pinctrl)) { | |
930 | priv->pins_default = pinctrl_lookup_state(priv->pinctrl, | |
931 | PINCTRL_STATE_DEFAULT); | |
932 | priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, | |
933 | "state_uhs"); | |
934 | } | |
935 | ||
b21fc294 | 936 | host = tmio_mmc_host_alloc(pdev, mmc_data); |
8d09a133 MY |
937 | if (IS_ERR(host)) |
938 | return PTR_ERR(host); | |
94b110af | 939 | |
dc9f1a8d | 940 | if (of_data) { |
a72e8b17 | 941 | mmc_data->flags |= of_data->tmio_flags; |
f19417f3 | 942 | mmc_data->ocr_mask = of_data->tmio_ocr_mask; |
a72e8b17 WS |
943 | mmc_data->capabilities |= of_data->capabilities; |
944 | mmc_data->capabilities2 |= of_data->capabilities2; | |
945 | mmc_data->dma_rx_offset = of_data->dma_rx_offset; | |
603aa14d YS |
946 | mmc_data->max_blk_count = of_data->max_blk_count; |
947 | mmc_data->max_segs = of_data->max_segs; | |
a72e8b17 WS |
948 | dma_priv->dma_buswidth = of_data->dma_buswidth; |
949 | host->bus_shift = of_data->bus_shift; | |
950 | } | |
951 | ||
b5b6a5f4 SH |
952 | host->write16_hook = renesas_sdhi_write16_hook; |
953 | host->clk_enable = renesas_sdhi_clk_enable; | |
b5b6a5f4 | 954 | host->clk_disable = renesas_sdhi_clk_disable; |
0196c8db | 955 | host->set_clock = renesas_sdhi_set_clock; |
b5b6a5f4 | 956 | host->multi_io_quirk = renesas_sdhi_multi_io_quirk; |
bc45719c | 957 | host->dma_ops = dma_ops; |
ff026099 | 958 | |
0f4e2054 NS |
959 | if (quirks && quirks->hs400_disabled) |
960 | host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); | |
961 | ||
ef5332c1 WS |
962 | /* For some SoC, we disable internal WP. GPIO may override this */ |
963 | if (mmc_can_gpio_ro(host->mmc)) | |
964 | mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; | |
965 | ||
ff026099 WS |
966 | /* SDR speeds are only available on Gen2+ */ |
967 | if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { | |
968 | /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ | |
2aaa3c51 MY |
969 | host->ops.card_busy = renesas_sdhi_card_busy; |
970 | host->ops.start_signal_voltage_switch = | |
b5b6a5f4 | 971 | renesas_sdhi_start_signal_voltage_switch; |
1970701f | 972 | host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; |
9f12cac1 | 973 | host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; |
d14ac691 | 974 | host->reset = renesas_sdhi_reset; |
ff026099 | 975 | } |
a72e8b17 WS |
976 | |
977 | /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ | |
978 | if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ | |
95a7dc36 | 979 | host->bus_shift = 1; |
7ecc09ba | 980 | |
84f11d5b | 981 | if (mmd) |
f33c9d65 | 982 | *mmc_data = *mmd; |
84f11d5b | 983 | |
87ae7bbe | 984 | dma_priv->filter = shdma_chan_filter; |
b5b6a5f4 | 985 | dma_priv->enable = renesas_sdhi_enable_dma; |
87ae7bbe | 986 | |
e471df0b | 987 | mmc_data->alignment_shift = 1; /* 2-byte alignment */ |
f33c9d65 | 988 | mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; |
e471df0b | 989 | |
f1334fb3 YG |
990 | /* |
991 | * All SDHI blocks support 2-byte and larger block sizes in 4-bit | |
992 | * bus width mode. | |
993 | */ | |
994 | mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; | |
995 | ||
23b66071 AH |
996 | /* |
997 | * All SDHI blocks support SDIO IRQ signalling. | |
998 | */ | |
999 | mmc_data->flags |= TMIO_MMC_SDIO_IRQ; | |
1000 | ||
2fe35968 | 1001 | /* All SDHI have CMD12 control bit */ |
b8d11962 SU |
1002 | mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; |
1003 | ||
20dd0373 WS |
1004 | /* All SDHI have SDIO status bits which must be 1 */ |
1005 | mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; | |
6b98757e | 1006 | |
30ae3e13 WS |
1007 | /* All SDHI support HW busy detection */ |
1008 | mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; | |
1009 | ||
63fd8ef3 UH |
1010 | dev_pm_domain_start(&pdev->dev); |
1011 | ||
b21fc294 MY |
1012 | ret = renesas_sdhi_clk_enable(host); |
1013 | if (ret) | |
94b110af | 1014 | goto efree; |
a87d5638 | 1015 | |
b4d86f37 WS |
1016 | priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); |
1017 | if (IS_ERR(priv->rstc)) | |
1018 | return PTR_ERR(priv->rstc); | |
1019 | ||
c9a9497c WS |
1020 | ver = sd_ctrl_read16(host, CTL_VERSION); |
1021 | /* GEN2_SDR104 is first known SDHI to use 32bit block count */ | |
1022 | if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) | |
1023 | mmc_data->max_blk_count = U16_MAX; | |
1024 | ||
5124b592 | 1025 | /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ |
c9a9497c | 1026 | if (ver == SDHI_VER_GEN2_SDR50) |
5124b592 WS |
1027 | mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; |
1028 | ||
ce6f92c2 WS |
1029 | if (ver == SDHI_VER_GEN3_SDMMC && quirks && quirks->hs400_calib_table) { |
1030 | host->fixup_request = renesas_sdhi_fixup_request; | |
1031 | priv->adjust_hs400_calib_table = *( | |
1032 | res->start == SDHI_GEN3_MMC0_ADDR ? | |
1033 | quirks->hs400_calib_table : | |
1034 | quirks->hs400_calib_table + 1); | |
1035 | } | |
1036 | ||
b191dece WS |
1037 | /* these have an EXTOP bit */ |
1038 | if (ver >= SDHI_VER_GEN3_SD) | |
1039 | host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; | |
1040 | ||
e831ead3 | 1041 | /* Enable tuning iff we have an SCC and a supported mode */ |
b1c95170 WS |
1042 | if (of_data && of_data->scc_offset && |
1043 | (host->mmc->caps & MMC_CAP_UHS_SDR104 || | |
26eb2607 MH |
1044 | host->mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | |
1045 | MMC_CAP2_HS400_1_8V))) { | |
b5b6a5f4 | 1046 | const struct renesas_sdhi_scc *taps = of_data->taps; |
c1a49782 | 1047 | bool use_4tap = priv->quirks && priv->quirks->hs400_4taps; |
6ade9a2c WS |
1048 | bool hit = false; |
1049 | ||
6ade9a2c WS |
1050 | for (i = 0; i < of_data->taps_num; i++) { |
1051 | if (taps[i].clk_rate == 0 || | |
1052 | taps[i].clk_rate == host->mmc->f_max) { | |
852d258f | 1053 | priv->scc_tappos = taps->tap; |
c1a49782 WS |
1054 | priv->scc_tappos_hs400 = use_4tap ? |
1055 | taps->tap_hs400_4tap : | |
1056 | taps->tap; | |
6ade9a2c WS |
1057 | hit = true; |
1058 | break; | |
06f438dd | 1059 | } |
6ade9a2c | 1060 | } |
06f438dd | 1061 | |
6ade9a2c | 1062 | if (!hit) |
e5088f20 | 1063 | dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); |
06f438dd | 1064 | |
d14ac691 | 1065 | priv->scc_ctl = host->ctl + of_data->scc_offset; |
64982b9f | 1066 | host->check_retune = renesas_sdhi_check_scc_error; |
510bfe58 | 1067 | host->ops.execute_tuning = renesas_sdhi_execute_tuning; |
f22084b6 WS |
1068 | host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; |
1069 | host->ops.hs400_downgrade = renesas_sdhi_disable_scc; | |
1070 | host->ops.hs400_complete = renesas_sdhi_hs400_complete; | |
06f438dd SH |
1071 | } |
1072 | ||
b161d87d WS |
1073 | ret = tmio_mmc_host_probe(host); |
1074 | if (ret < 0) | |
1075 | goto edisclk; | |
1076 | ||
e8307ec5 GU |
1077 | num_irqs = platform_irq_count(pdev); |
1078 | if (num_irqs < 0) { | |
1079 | ret = num_irqs; | |
1080 | goto eirq; | |
1081 | } | |
1082 | ||
1083 | /* There must be at least one IRQ source */ | |
1084 | if (!num_irqs) { | |
1085 | ret = -ENXIO; | |
1086 | goto eirq; | |
1087 | } | |
1088 | ||
1089 | for (i = 0; i < num_irqs; i++) { | |
adcbc949 | 1090 | irq = platform_get_irq(pdev, i); |
e8307ec5 GU |
1091 | if (irq < 0) { |
1092 | ret = irq; | |
1093 | goto eirq; | |
1094 | } | |
1095 | ||
adcbc949 | 1096 | ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, |
2fe35968 | 1097 | dev_name(&pdev->dev), host); |
d5098cb6 | 1098 | if (ret) |
ac51b961 | 1099 | goto eirq; |
d5098cb6 SH |
1100 | } |
1101 | ||
bcf89cb8 WS |
1102 | dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", |
1103 | mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); | |
a87d5638 | 1104 | |
42051e8a | 1105 | return ret; |
a87d5638 | 1106 | |
ac51b961 | 1107 | eirq: |
8e7bfdb3 | 1108 | tmio_mmc_host_remove(host); |
b21fc294 MY |
1109 | edisclk: |
1110 | renesas_sdhi_clk_disable(host); | |
94b110af KM |
1111 | efree: |
1112 | tmio_mmc_host_free(host); | |
4ce62817 | 1113 | |
a87d5638 MD |
1114 | return ret; |
1115 | } | |
9d08428a | 1116 | EXPORT_SYMBOL_GPL(renesas_sdhi_probe); |
a87d5638 | 1117 | |
9d08428a | 1118 | int renesas_sdhi_remove(struct platform_device *pdev) |
a87d5638 | 1119 | { |
a3b05373 | 1120 | struct tmio_mmc_host *host = platform_get_drvdata(pdev); |
d6a1f863 | 1121 | |
742a0c7c | 1122 | tmio_mmc_host_remove(host); |
b21fc294 | 1123 | renesas_sdhi_clk_disable(host); |
e8973201 | 1124 | tmio_mmc_host_free(host); |
742a0c7c | 1125 | |
a87d5638 MD |
1126 | return 0; |
1127 | } | |
9d08428a | 1128 | EXPORT_SYMBOL_GPL(renesas_sdhi_remove); |
967a6a07 MH |
1129 | |
1130 | MODULE_LICENSE("GPL v2"); |